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Commit ddcbed04a21857cb0a457b0ff3de26c750815632

Authored by Chin Liang See
Committed by Marek Vasut
1 parent 13e81d45f8
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: socfpga: Enable DWMMC for SOCFPGA 

Enable the DesignWare MMC controller driver support
for SOCFPGA Cyclone5 dev kit

Signed-off-by: Chin Liang See <clsee@altera.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

Showing 1 changed file with 16 additions and 0 deletions Inline Diff

include/configs/socfpga_cyclone5.h
Diff comments   View file @ ddcbed0
1 /* 1 /*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 #ifndef __CONFIG_H 6 #ifndef __CONFIG_H
7 #define __CONFIG_H 7 #define __CONFIG_H
8 8
9 #include <asm/arch/socfpga_base_addrs.h> 9 #include <asm/arch/socfpga_base_addrs.h>
10 #include "../../board/altera/socfpga/pinmux_config.h" 10 #include "../../board/altera/socfpga/pinmux_config.h"
11 #include "../../board/altera/socfpga/iocsr_config.h" 11 #include "../../board/altera/socfpga/iocsr_config.h"
12 #include "../../board/altera/socfpga/pll_config.h" 12 #include "../../board/altera/socfpga/pll_config.h"
13 13
14 /* 14 /*
15 * High level configuration 15 * High level configuration
16 */ 16 */
17 /* Virtual target or real hardware */ 17 /* Virtual target or real hardware */
18 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET 18 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
19 19
20 #define CONFIG_ARMV7 20 #define CONFIG_ARMV7
21 #undef CONFIG_USE_IRQ 21 #undef CONFIG_USE_IRQ
22 22
23 #define CONFIG_MISC_INIT_R 23 #define CONFIG_MISC_INIT_R
24 #define CONFIG_SINGLE_BOOTLOADER 24 #define CONFIG_SINGLE_BOOTLOADER
25 #define CONFIG_SOCFPGA 25 #define CONFIG_SOCFPGA
26 #define CONFIG_CLOCKS 26 #define CONFIG_CLOCKS
27 27
28 #define CONFIG_SYS_ARM_CACHE_WRITEALLOC 28 #define CONFIG_SYS_ARM_CACHE_WRITEALLOC
29 #define CONFIG_SYS_CACHELINE_SIZE 32 29 #define CONFIG_SYS_CACHELINE_SIZE 32
30 #define CONFIG_SYS_L2_PL310 30 #define CONFIG_SYS_L2_PL310
31 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 31 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
32 32
33 /* base address for .text section */ 33 /* base address for .text section */
34 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 34 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
35 #define CONFIG_SYS_TEXT_BASE 0x08000040 35 #define CONFIG_SYS_TEXT_BASE 0x08000040
36 #else 36 #else
37 #define CONFIG_SYS_TEXT_BASE 0x01000040 37 #define CONFIG_SYS_TEXT_BASE 0x01000040
38 #endif 38 #endif
39 #define CONFIG_SYS_LOAD_ADDR 0x7fc0 39 #define CONFIG_SYS_LOAD_ADDR 0x7fc0
40 40
41 /* Console I/O Buffer Size */ 41 /* Console I/O Buffer Size */
42 #define CONFIG_SYS_CBSIZE 256 42 #define CONFIG_SYS_CBSIZE 256
43 /* Monitor Command Prompt */ 43 /* Monitor Command Prompt */
44 #define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " 44 #define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # "
45 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 45 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
46 sizeof(CONFIG_SYS_PROMPT) + 16) 46 sizeof(CONFIG_SYS_PROMPT) + 16)
47 47
48 /* 48 /*
49 * Display CPU and Board Info 49 * Display CPU and Board Info
50 */ 50 */
51 #define CONFIG_DISPLAY_CPUINFO 51 #define CONFIG_DISPLAY_CPUINFO
52 #define CONFIG_DISPLAY_BOARDINFO 52 #define CONFIG_DISPLAY_BOARDINFO
53 53
54 /* 54 /*
55 * Enable early stage initialization at C environment 55 * Enable early stage initialization at C environment
56 */ 56 */
57 #define CONFIG_BOARD_EARLY_INIT_F 57 #define CONFIG_BOARD_EARLY_INIT_F
58 58
59 /* flat device tree */ 59 /* flat device tree */
60 #define CONFIG_OF_LIBFDT 60 #define CONFIG_OF_LIBFDT
61 /* skip updating the FDT blob */ 61 /* skip updating the FDT blob */
62 #define CONFIG_FDT_BLOB_SKIP_UPDATE 62 #define CONFIG_FDT_BLOB_SKIP_UPDATE
63 /* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ 63 /* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
64 #define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) 64 #define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024))
65 65
66 #define CONFIG_SPL_RAM_DEVICE 66 #define CONFIG_SPL_RAM_DEVICE
67 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 67 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
68 #define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) 68 #define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
69 #define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) 69 #define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
70 70
71 /* 71 /*
72 * Memory allocation (MALLOC) 72 * Memory allocation (MALLOC)
73 */ 73 */
74 /* Room required on the stack for the environment data */ 74 /* Room required on the stack for the environment data */
75 #define CONFIG_ENV_SIZE 1024 75 #define CONFIG_ENV_SIZE 1024
76 /* Size of DRAM reserved for malloc() use */ 76 /* Size of DRAM reserved for malloc() use */
77 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 77 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
78 78
79 /* SP location before relocation, must use scratch RAM */ 79 /* SP location before relocation, must use scratch RAM */
80 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 80 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
81 /* Reserving 0x100 space at back of scratch RAM for debug info */ 81 /* Reserving 0x100 space at back of scratch RAM for debug info */
82 #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) 82 #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
83 /* Stack pointer prior relocation, must situated at on-chip RAM */ 83 /* Stack pointer prior relocation, must situated at on-chip RAM */
84 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 84 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
85 CONFIG_SYS_INIT_RAM_SIZE - \ 85 CONFIG_SYS_INIT_RAM_SIZE - \
86 GENERATED_GBL_DATA_SIZE) 86 GENERATED_GBL_DATA_SIZE)
87 87
88 88
89 /* 89 /*
90 * Command line configuration. 90 * Command line configuration.
91 */ 91 */
92 #define CONFIG_SYS_NO_FLASH 92 #define CONFIG_SYS_NO_FLASH
93 #include <config_cmd_default.h> 93 #include <config_cmd_default.h>
94 /* FAT file system support */ 94 /* FAT file system support */
95 #define CONFIG_CMD_FAT 95 #define CONFIG_CMD_FAT
96 96
97 97
98 /* 98 /*
99 * Misc 99 * Misc
100 */ 100 */
101 #define CONFIG_DOS_PARTITION 1 101 #define CONFIG_DOS_PARTITION 1
102 102
103 #ifdef CONFIG_SPL_BUILD 103 #ifdef CONFIG_SPL_BUILD
104 #undef CONFIG_PARTITIONS 104 #undef CONFIG_PARTITIONS
105 #endif 105 #endif
106 106
107 /* 107 /*
108 * Environment setup 108 * Environment setup
109 */ 109 */
110 110
111 /* Delay before automatically booting the default image */ 111 /* Delay before automatically booting the default image */
112 #define CONFIG_BOOTDELAY 3 112 #define CONFIG_BOOTDELAY 3
113 /* Enable auto completion of commands using TAB */ 113 /* Enable auto completion of commands using TAB */
114 #define CONFIG_AUTO_COMPLETE 114 #define CONFIG_AUTO_COMPLETE
115 /* use "hush" command parser */ 115 /* use "hush" command parser */
116 #define CONFIG_SYS_HUSH_PARSER 116 #define CONFIG_SYS_HUSH_PARSER
117 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 117 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
118 #define CONFIG_CMD_RUN 118 #define CONFIG_CMD_RUN
119 119
120 #define CONFIG_BOOTCOMMAND "run ramboot" 120 #define CONFIG_BOOTCOMMAND "run ramboot"
121 121
122 /* 122 /*
123 * arguments passed to the bootm command. The value of 123 * arguments passed to the bootm command. The value of
124 * CONFIG_BOOTARGS goes into the environment value "bootargs". 124 * CONFIG_BOOTARGS goes into the environment value "bootargs".
125 * Do note the value will overide also the chosen node in FDT blob. 125 * Do note the value will overide also the chosen node in FDT blob.
126 */ 126 */
127 #define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0" 127 #define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0"
128 128
129 #define CONFIG_EXTRA_ENV_SETTINGS \ 129 #define CONFIG_EXTRA_ENV_SETTINGS \
130 "verify=n\0" \ 130 "verify=n\0" \
131 "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 131 "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
132 "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ 132 "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
133 "bootm ${loadaddr} - ${fdt_addr}\0" \ 133 "bootm ${loadaddr} - ${fdt_addr}\0" \
134 "bootimage=uImage\0" \ 134 "bootimage=uImage\0" \
135 "fdt_addr=100\0" \ 135 "fdt_addr=100\0" \
136 "fsloadcmd=ext2load\0" \ 136 "fsloadcmd=ext2load\0" \
137 "bootm ${loadaddr} - ${fdt_addr}\0" \ 137 "bootm ${loadaddr} - ${fdt_addr}\0" \
138 "qspiroot=/dev/mtdblock0\0" \ 138 "qspiroot=/dev/mtdblock0\0" \
139 "qspirootfstype=jffs2\0" \ 139 "qspirootfstype=jffs2\0" \
140 "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ 140 "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
141 " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ 141 " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
142 "bootm ${loadaddr} - ${fdt_addr}\0" 142 "bootm ${loadaddr} - ${fdt_addr}\0"
143 143
144 /* using environment setting for stdin, stdout, stderr */ 144 /* using environment setting for stdin, stdout, stderr */
145 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 145 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
146 /* Enable the call to overwrite_console() */ 146 /* Enable the call to overwrite_console() */
147 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 147 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
148 /* Enable overwrite of previous console environment settings */ 148 /* Enable overwrite of previous console environment settings */
149 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 149 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
150 150
151 /* max number of command args */ 151 /* max number of command args */
152 #define CONFIG_SYS_MAXARGS 16 152 #define CONFIG_SYS_MAXARGS 16
153 153
154 154
155 /* 155 /*
156 * Hardware drivers 156 * Hardware drivers
157 */ 157 */
158 158
159 /* 159 /*
160 * SDRAM Memory Map 160 * SDRAM Memory Map
161 */ 161 */
162 /* We have 1 bank of DRAM */ 162 /* We have 1 bank of DRAM */
163 #define CONFIG_NR_DRAM_BANKS 1 163 #define CONFIG_NR_DRAM_BANKS 1
164 /* SDRAM Bank #1 */ 164 /* SDRAM Bank #1 */
165 #define CONFIG_SYS_SDRAM_BASE 0x00000000 165 #define CONFIG_SYS_SDRAM_BASE 0x00000000
166 /* SDRAM memory size */ 166 /* SDRAM memory size */
167 #define PHYS_SDRAM_1_SIZE 0x40000000 167 #define PHYS_SDRAM_1_SIZE 0x40000000
168 168
169 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 169 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
170 #define CONFIG_SYS_MEMTEST_START 0x00000000 170 #define CONFIG_SYS_MEMTEST_START 0x00000000
171 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 171 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
172 172
173 /* 173 /*
174 * NS16550 Configuration 174 * NS16550 Configuration
175 */ 175 */
176 #define UART0_BASE SOCFPGA_UART0_ADDRESS 176 #define UART0_BASE SOCFPGA_UART0_ADDRESS
177 #define CONFIG_SYS_NS16550 177 #define CONFIG_SYS_NS16550
178 #define CONFIG_SYS_NS16550_SERIAL 178 #define CONFIG_SYS_NS16550_SERIAL
179 #define CONFIG_SYS_NS16550_REG_SIZE -4 179 #define CONFIG_SYS_NS16550_REG_SIZE -4
180 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 180 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
181 #define CONFIG_CONS_INDEX 1 181 #define CONFIG_CONS_INDEX 1
182 #define CONFIG_SYS_NS16550_COM1 UART0_BASE 182 #define CONFIG_SYS_NS16550_COM1 UART0_BASE
183 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} 183 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
184 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 184 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
185 #define V_NS16550_CLK 1000000 185 #define V_NS16550_CLK 1000000
186 #else 186 #else
187 #define V_NS16550_CLK 100000000 187 #define V_NS16550_CLK 100000000
188 #endif 188 #endif
189 #define CONFIG_BAUDRATE 115200 189 #define CONFIG_BAUDRATE 115200
190 190
191 /* 191 /*
192 * FLASH 192 * FLASH
193 */ 193 */
194 #define CONFIG_SYS_NO_FLASH 194 #define CONFIG_SYS_NO_FLASH
195 195
196 /* 196 /*
197 * L4 OSC1 Timer 0 197 * L4 OSC1 Timer 0
198 */ 198 */
199 /* This timer use eosc1 where the clock frequency is fixed 199 /* This timer use eosc1 where the clock frequency is fixed
200 * throughout any condition */ 200 * throughout any condition */
201 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 201 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
202 /* Timer info */ 202 /* Timer info */
203 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 203 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
204 #define CONFIG_SYS_TIMER_RATE 2400000 204 #define CONFIG_SYS_TIMER_RATE 2400000
205 #else 205 #else
206 #define CONFIG_SYS_TIMER_RATE 25000000 206 #define CONFIG_SYS_TIMER_RATE 25000000
207 #endif 207 #endif
208 #define CONFIG_SYS_TIMER_COUNTS_DOWN 208 #define CONFIG_SYS_TIMER_COUNTS_DOWN
209 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 209 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
210 210
211 #define CONFIG_ENV_IS_NOWHERE 211 #define CONFIG_ENV_IS_NOWHERE
212 212
213 /* 213 /*
214 * network support 214 * network support
215 */ 215 */
216 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET 216 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
217 #define CONFIG_DESIGNWARE_ETH 1 217 #define CONFIG_DESIGNWARE_ETH 1
218 #endif 218 #endif
219 219
220 #ifdef CONFIG_DESIGNWARE_ETH 220 #ifdef CONFIG_DESIGNWARE_ETH
221 #define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS 221 #define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS
222 #define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS 222 #define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS
223 /* console support for network */ 223 /* console support for network */
224 #define CONFIG_CMD_DHCP 224 #define CONFIG_CMD_DHCP
225 #define CONFIG_CMD_MII 225 #define CONFIG_CMD_MII
226 #define CONFIG_CMD_NET 226 #define CONFIG_CMD_NET
227 #define CONFIG_CMD_PING 227 #define CONFIG_CMD_PING
228 /* designware */ 228 /* designware */
229 #define CONFIG_NET_MULTI 229 #define CONFIG_NET_MULTI
230 #define CONFIG_DW_ALTDESCRIPTOR 230 #define CONFIG_DW_ALTDESCRIPTOR
231 #define CONFIG_MII 231 #define CONFIG_MII
232 #define CONFIG_PHY_GIGE 232 #define CONFIG_PHY_GIGE
233 #define CONFIG_DW_AUTONEG 233 #define CONFIG_DW_AUTONEG
234 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) 234 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
235 #define CONFIG_PHYLIB 235 #define CONFIG_PHYLIB
236 #define CONFIG_PHY_MICREL 236 #define CONFIG_PHY_MICREL
237 #define CONFIG_PHY_MICREL_KSZ9021 237 #define CONFIG_PHY_MICREL_KSZ9021
238 /* EMAC controller and PHY used */ 238 /* EMAC controller and PHY used */
239 #define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE 239 #define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE
240 #define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR 240 #define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR
241 #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII 241 #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
242 #endif /* CONFIG_DESIGNWARE_ETH */ 242 #endif /* CONFIG_DESIGNWARE_ETH */
243 243
244 /* 244 /*
245 * L4 Watchdog 245 * L4 Watchdog
246 */ 246 */
247 #define CONFIG_HW_WATCHDOG 247 #define CONFIG_HW_WATCHDOG
248 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000 248 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000
249 #define CONFIG_DESIGNWARE_WATCHDOG 249 #define CONFIG_DESIGNWARE_WATCHDOG
250 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 250 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
251 /* Clocks source frequency to watchdog timer */ 251 /* Clocks source frequency to watchdog timer */
252 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 252 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
253 253
254 /*
255 * MMC support
256 */
257 #define CONFIG_MMC
258 #ifdef CONFIG_MMC
259 #define CONFIG_BOUNCE_BUFFER
260 #define CONFIG_CMD_MMC
261 #define CONFIG_GENERIC_MMC
262 #define CONFIG_DWMMC
263 #define CONFIG_SOCFPGA_DWMMC
264 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
265 #define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
266 #define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
267 /* using smaller max blk cnt to avoid flooding the limited stack we have */
268 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
269 #endif /* CONFIG_MMC */
254 270
255 /* 271 /*
256 * SPL "Second Program Loader" aka Initial Software 272 * SPL "Second Program Loader" aka Initial Software
257 */ 273 */
258 274
259 /* Enable building of SPL globally */ 275 /* Enable building of SPL globally */
260 #define CONFIG_SPL_FRAMEWORK 276 #define CONFIG_SPL_FRAMEWORK
261 277
262 /* TEXT_BASE for linking the SPL binary */ 278 /* TEXT_BASE for linking the SPL binary */
263 #define CONFIG_SPL_TEXT_BASE 0xFFFF0000 279 #define CONFIG_SPL_TEXT_BASE 0xFFFF0000
264 280
265 /* Stack size for SPL */ 281 /* Stack size for SPL */
266 #define CONFIG_SPL_STACK_SIZE (4 * 1024) 282 #define CONFIG_SPL_STACK_SIZE (4 * 1024)
267 283
268 /* MALLOC size for SPL */ 284 /* MALLOC size for SPL */
269 #define CONFIG_SPL_MALLOC_SIZE (5 * 1024) 285 #define CONFIG_SPL_MALLOC_SIZE (5 * 1024)
270 286
271 #define CONFIG_SPL_SERIAL_SUPPORT 287 #define CONFIG_SPL_SERIAL_SUPPORT
272 #define CONFIG_SPL_BOARD_INIT 288 #define CONFIG_SPL_BOARD_INIT
273 289
274 #define CHUNKSZ_CRC32 (1 * 1024) 290 #define CHUNKSZ_CRC32 (1 * 1024)
275 291
276 #define CONFIG_CRC32_VERIFY 292 #define CONFIG_CRC32_VERIFY
277 293
278 /* Linker script for SPL */ 294 /* Linker script for SPL */
279 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" 295 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
280 296
281 /* Support for common/libcommon.o in SPL binary */ 297 /* Support for common/libcommon.o in SPL binary */
282 #define CONFIG_SPL_LIBCOMMON_SUPPORT 298 #define CONFIG_SPL_LIBCOMMON_SUPPORT
283 /* Support for lib/libgeneric.o in SPL binary */ 299 /* Support for lib/libgeneric.o in SPL binary */
284 #define CONFIG_SPL_LIBGENERIC_SUPPORT 300 #define CONFIG_SPL_LIBGENERIC_SUPPORT
285 301
286 /* Support for watchdog */ 302 /* Support for watchdog */
287 #define CONFIG_SPL_WATCHDOG_SUPPORT 303 #define CONFIG_SPL_WATCHDOG_SUPPORT
288 304
289 #endif /* __CONFIG_H */ 305 #endif /* __CONFIG_H */
290 306