Eric Lee / smarc-uboot

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Commit ddf4e63c361fe8c4488b73e3b9db575ea5207d66

Authored by Anson Huang
Committed by guoyin.chen
1 parent 7c09ec91b7
Exists in smarc-imx_v2015.04_4.1.15_1.0.0_ga and in 1 other branch imx_v2015.04_4.1.15_1.0.0_ga

MLK-11995 ARM: imx7: add i.mx7d TO1.1 support for LPSR mode 

i.MX7D TO1.1 changes DDR retension mode control to IOMUXC_GPR,
add support to this change for LPSR which needs to exit from
DDR retension mode.

Signed-off-by: Anson Huang <Anson.Huang@freescale.com>

Showing 1 changed file with 16 additions and 6 deletions Side-by-side Diff

board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S
Diff comments   View file @ ddf4e63
... ... @@ -70,9 +70,6 @@
70 70 subs r6, r6, #0x1
71 71 bne 1b
72 72  
73   - ldr r7, =0x0
74   - str r7, [r1, #0x380]
75   -
76 73 /* clear ddr_phy reset */
77 74 ldr r6, =0x1000
78 75 ldr r7, [r2, r6]
79 76  
80 77  
... ... @@ -206,14 +203,27 @@
206 203 bic r7, r7, #0x2
207 204 str r7, [r2, r6]
208 205  
  206 + ldr r7, [r1, #0x800]
  207 + and r7, r7, #0x11
  208 + cmp r7, #0x10
  209 + beq 2f
  210 +
  211 + /* TO1.1 */
  212 + ldr r7, [r11]
  213 + bic r7, r7, #(1 << 27)
  214 + str r7, [r11]
  215 + ldr r7, [r11]
  216 + bic r7, r7, #(1 << 29)
  217 + str r7, [r11]
  218 +2:
209 219 ldr r7, =(0x1 << 30)
210 220 str r7, [r1, #0x380]
211 221  
212 222 /* need to delay ~5mS */
213   - ldr r6, =0x1000000
214   -2:
  223 + ldr r6, =0x100000
  224 +3:
215 225 subs r6, r6, #0x1
216   - bne 2b
  226 + bne 3b
217 227  
218 228 /* restore DDR PHY */
219 229 ldr r6, =0x0