socfpga: Adding Clock Manager driver

Clock Manager driver will be called to reconfigure all the clocks setting based on user input. The input are passed to Preloader through handoff files Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Pavel Machek <pavel@denx.de>

socfpga: Adding Clock Manager driver
Clock Manager driver will be called to reconfigure all the clocks setting based on user input. The input are passed to Preloader through handoff files Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Pavel Machek <pavel@denx.de>
Chin Liang See · Albert ARIBAUD
1 parent 1a9df13d5b
Showing 7 changed files with 776 additions and 1 deletions Side-by-side Diff
arch/arm/cpu/armv7/socfpga/Makefile
arch/arm/cpu/armv7/socfpga/clock_manager.c
arch/arm/cpu/armv7/socfpga/spl.c
arch/arm/include/asm/arch-socfpga/clock_manager.h
arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
board/altera/socfpga/pll_config.h
include/configs/socfpga_cyclone5.h
@@ -8,6 +8,6 @@
 #
  
 obj-y	:= lowlevel_init.o
-obj-y	+= misc.o timer.o reset_manager.o system_manager.o
+obj-y	+= misc.o timer.o reset_manager.o system_manager.o clock_manager.o
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock_manager.h>
+
+static const struct socfpga_clock_manager *clock_manager_base =
+		(void *)SOCFPGA_CLKMGR_ADDRESS;
+
+#define CLKMGR_BYPASS_ENABLE	1
+#define CLKMGR_BYPASS_DISABLE	0
+#define CLKMGR_STAT_IDLE	0
+#define CLKMGR_STAT_BUSY	1
+#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1		0
+#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX	1
+#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1		0
+#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX	1
+
+#define CLEAR_BGP_EN_PWRDN \
+	(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
+	CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
+	CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
+
+#define VCO_EN_BASE \
+	(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
+	CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
+	CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
+
+static inline void cm_wait_for_lock(uint32_t mask)
+{
+	register uint32_t inter_val;
+	do {
+		inter_val = readl(&clock_manager_base->inter) & mask;
+	} while (inter_val != mask);
+}
+
+/* function to poll in the fsm busy bit */
+static inline void cm_wait_for_fsm(void)
+{
+	while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
+		;
+}
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static inline void cm_write_bypass(uint32_t val)
+{
+	writel(val, &clock_manager_base->bypass);
+	cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static inline void cm_write_ctrl(uint32_t val)
+{
+	writel(val, &clock_manager_base->ctrl);
+	cm_wait_for_fsm();
+}
+
+/* function to write a clock register that has phase information */
+static inline void cm_write_with_phase(uint32_t value,
+	uint32_t reg_address, uint32_t mask)
+{
+	/* poll until phase is zero */
+	while (readl(reg_address) & mask)
+		;
+
+	writel(value, reg_address);
+
+	while (readl(reg_address) & mask)
+		;
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ *
+ * Start by being paranoid and gate all sw managed clocks
+ * Put all plls in bypass
+ * Put all plls VCO registers back to reset value (bandgap power down).
+ * Put peripheral and main pll src to reset value to avoid glitch.
+ * Delay 5 us.
+ * Deassert bandgap power down and set numerator and denominator
+ * Start 7 us timer.
+ * set internal dividers
+ * Wait for 7 us timer.
+ * Enable plls
+ * Set external dividers while plls are locking
+ * Wait for pll lock
+ * Assert/deassert outreset all.
+ * Take all pll's out of bypass
+ * Clear safe mode
+ * set source main and peripheral clocks
+ * Ungate clocks
+ */
+
+void cm_basic_init(const cm_config_t *cfg)
+{
+	uint32_t start, timeout;
+
+	/* Start by being paranoid and gate all sw managed clocks */
+
+	/*
+	 * We need to disable nandclk
+	 * and then do another apb access before disabling
+	 * gatting off the rest of the periperal clocks.
+	 */
+	writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
+		readl(&clock_manager_base->per_pll_en),
+		&clock_manager_base->per_pll_en);
+
+	/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
+	writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
+		&clock_manager_base->main_pll_en);
+
+	writel(0, &clock_manager_base->sdr_pll_en);
+
+	/* now we can gate off the rest of the peripheral clocks */
+	writel(0, &clock_manager_base->per_pll_en);
+
+	/* Put all plls in bypass */
+	cm_write_bypass(
+		CLKMGR_BYPASS_PERPLLSRC_SET(
+		CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
+		CLKMGR_BYPASS_SDRPLLSRC_SET(
+		CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
+		CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) |
+		CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) |
+		CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
+
+	/*
+	 * Put all plls VCO registers back to reset value.
+	 * Some code might have messed with them.
+	 */
+	writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
+	       &clock_manager_base->main_pll_vco);
+	writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
+	       &clock_manager_base->per_pll_vco);
+	writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
+	       &clock_manager_base->sdr_pll_vco);
+
+	/*
+	 * The clocks to the flash devices and the L4_MAIN clocks can
+	 * glitch when coming out of safe mode if their source values
+	 * are different from their reset value.  So the trick it to
+	 * put them back to their reset state, and change input
+	 * after exiting safe mode but before ungating the clocks.
+	 */
+	writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
+	       &clock_manager_base->per_pll_src);
+	writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
+	       &clock_manager_base->main_pll_l4src);
+
+	/* read back for the required 5 us delay. */
+	readl(&clock_manager_base->main_pll_vco);
+	readl(&clock_manager_base->per_pll_vco);
+	readl(&clock_manager_base->sdr_pll_vco);
+
+
+	/*
+	 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
+	 * with numerator and denominator.
+	 */
+	writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
+		CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
+		&clock_manager_base->main_pll_vco);
+
+	writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
+		CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
+		&clock_manager_base->per_pll_vco);
+
+	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
+		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
+		cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
+		CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
+		&clock_manager_base->sdr_pll_vco);
+
+	/*
+	 * Time starts here
+	 * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
+	 */
+	reset_timer();
+	start = get_timer(0);
+	/* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
+	timeout = 7;
+
+	/* main mpu */
+	writel(cfg->mpuclk, &clock_manager_base->main_pll_mpuclk);
+
+	/* main main clock */
+	writel(cfg->mainclk, &clock_manager_base->main_pll_mainclk);
+
+	/* main for dbg */
+	writel(cfg->dbgatclk, &clock_manager_base->main_pll_dbgatclk);
+
+	/* main for cfgs2fuser0clk */
+	writel(cfg->cfg2fuser0clk,
+	       &clock_manager_base->main_pll_cfgs2fuser0clk);
+
+	/* Peri emac0 50 MHz default to RMII */
+	writel(cfg->emac0clk, &clock_manager_base->per_pll_emac0clk);
+
+	/* Peri emac1 50 MHz default to RMII */
+	writel(cfg->emac1clk, &clock_manager_base->per_pll_emac1clk);
+
+	/* Peri QSPI */
+	writel(cfg->mainqspiclk, &clock_manager_base->main_pll_mainqspiclk);
+
+	writel(cfg->perqspiclk, &clock_manager_base->per_pll_perqspiclk);
+
+	/* Peri pernandsdmmcclk */
+	writel(cfg->pernandsdmmcclk,
+	       &clock_manager_base->per_pll_pernandsdmmcclk);
+
+	/* Peri perbaseclk */
+	writel(cfg->perbaseclk, &clock_manager_base->per_pll_perbaseclk);
+
+	/* Peri s2fuser1clk */
+	writel(cfg->s2fuser1clk, &clock_manager_base->per_pll_s2fuser1clk);
+
+	/* 7 us must have elapsed before we can enable the VCO */
+	while (get_timer(start) < timeout)
+		;
+
+	/* Enable vco */
+	/* main pll vco */
+	writel(cfg->main_vco_base | VCO_EN_BASE,
+	       &clock_manager_base->main_pll_vco);
+
+	/* periferal pll */
+	writel(cfg->peri_vco_base | VCO_EN_BASE,
+	       &clock_manager_base->per_pll_vco);
+
+	/* sdram pll vco */
+	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
+		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
+		cfg->sdram_vco_base | VCO_EN_BASE,
+		&clock_manager_base->sdr_pll_vco);
+
+	/* L3 MP and L3 SP */
+	writel(cfg->maindiv, &clock_manager_base->main_pll_maindiv);
+
+	writel(cfg->dbgdiv, &clock_manager_base->main_pll_dbgdiv);
+
+	writel(cfg->tracediv, &clock_manager_base->main_pll_tracediv);
+
+	/* L4 MP, L4 SP, can0, and can1 */
+	writel(cfg->perdiv, &clock_manager_base->per_pll_div);
+
+	writel(cfg->gpiodiv, &clock_manager_base->per_pll_gpiodiv);
+
+#define LOCKED_MASK \
+	(CLKMGR_INTER_SDRPLLLOCKED_MASK  | \
+	CLKMGR_INTER_PERPLLLOCKED_MASK  | \
+	CLKMGR_INTER_MAINPLLLOCKED_MASK)
+
+	cm_wait_for_lock(LOCKED_MASK);
+
+	/* write the sdram clock counters before toggling outreset all */
+	writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
+	       &clock_manager_base->sdr_pll_ddrdqsclk);
+
+	writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
+	       &clock_manager_base->sdr_pll_ddr2xdqsclk);
+
+	writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
+	       &clock_manager_base->sdr_pll_ddrdqclk);
+
+	writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
+	       &clock_manager_base->sdr_pll_s2fuser2clk);
+
+	/*
+	 * after locking, but before taking out of bypass
+	 * assert/deassert outresetall
+	 */
+	uint32_t mainvco = readl(&clock_manager_base->main_pll_vco);
+
+	/* assert main outresetall */
+	writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
+	       &clock_manager_base->main_pll_vco);
+
+	uint32_t periphvco = readl(&clock_manager_base->per_pll_vco);
+
+	/* assert pheriph outresetall */
+	writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
+	       &clock_manager_base->per_pll_vco);
+
+	/* assert sdram outresetall */
+	writel(cfg->sdram_vco_base | VCO_EN_BASE|
+		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
+		&clock_manager_base->sdr_pll_vco);
+
+	/* deassert main outresetall */
+	writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
+	       &clock_manager_base->main_pll_vco);
+
+	/* deassert pheriph outresetall */
+	writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
+	       &clock_manager_base->per_pll_vco);
+
+	/* deassert sdram outresetall */
+	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
+		cfg->sdram_vco_base | VCO_EN_BASE,
+		&clock_manager_base->sdr_pll_vco);
+
+	/*
+	 * now that we've toggled outreset all, all the clocks
+	 * are aligned nicely; so we can change any phase.
+	 */
+	cm_write_with_phase(cfg->ddrdqsclk,
+			    (uint32_t)&clock_manager_base->sdr_pll_ddrdqsclk,
+			    CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
+
+	/* SDRAM DDR2XDQSCLK */
+	cm_write_with_phase(cfg->ddr2xdqsclk,
+			    (uint32_t)&clock_manager_base->sdr_pll_ddr2xdqsclk,
+			    CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
+
+	cm_write_with_phase(cfg->ddrdqclk,
+			    (uint32_t)&clock_manager_base->sdr_pll_ddrdqclk,
+			    CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
+
+	cm_write_with_phase(cfg->s2fuser2clk,
+			    (uint32_t)&clock_manager_base->sdr_pll_s2fuser2clk,
+			    CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
+
+	/* Take all three PLLs out of bypass when safe mode is cleared. */
+	cm_write_bypass(
+		CLKMGR_BYPASS_PERPLLSRC_SET(
+			CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
+		CLKMGR_BYPASS_SDRPLLSRC_SET(
+			CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
+		CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) |
+		CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) |
+		CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
+
+	/* clear safe mode */
+	cm_write_ctrl(readl(&clock_manager_base->ctrl) |
+			CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
+
+	/*
+	 * now that safe mode is clear with clocks gated
+	 * it safe to change the source mux for the flashes the the L4_MAIN
+	 */
+	writel(cfg->persrc, &clock_manager_base->per_pll_src);
+	writel(cfg->l4src, &clock_manager_base->main_pll_l4src);
+
+	/* Now ungate non-hw-managed clocks */
+	writel(~0, &clock_manager_base->main_pll_en);
+	writel(~0, &clock_manager_base->per_pll_en);
+	writel(~0, &clock_manager_base->sdr_pll_en);
+}
@@ -28,9 +28,98 @@
 void spl_board_init(void)
 {
 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+	cm_config_t cm_default_cfg = {
+		/* main group */
+		MAIN_VCO_BASE,
+		CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
+		CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
+		CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
+		CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
+		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
+		CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
+		CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) |
+		CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) |
+		CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) |
+		CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
+		CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) |
+		CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
+		CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(
+			CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
+		CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(
+			CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) |
+		CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(
+			CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),
+
+		/* peripheral group */
+		PERI_VCO_BASE,
+		CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
+		CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
+		CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
+		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
+		CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
+		CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
+		CLKMGR_PERPLLGRP_DIV_USBCLK_SET(
+			CONFIG_HPS_PERPLLGRP_DIV_USBCLK) |
+		CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(
+			CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) |
+		CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(
+			CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) |
+		CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(
+			CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
+		CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(
+			CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
+		CLKMGR_PERPLLGRP_SRC_QSPI_SET(
+			CONFIG_HPS_PERPLLGRP_SRC_QSPI) |
+		CLKMGR_PERPLLGRP_SRC_NAND_SET(
+			CONFIG_HPS_PERPLLGRP_SRC_NAND) |
+		CLKMGR_PERPLLGRP_SRC_SDMMC_SET(
+			CONFIG_HPS_PERPLLGRP_SRC_SDMMC),
+
+		/* sdram pll group */
+		SDR_VCO_BASE,
+		CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(
+			CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) |
+		CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(
+			CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
+		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(
+			CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) |
+		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(
+			CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
+		CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(
+			CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) |
+		CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(
+			CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
+		CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(
+			CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) |
+		CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(
+			CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
+	};
+
 	debug("Freezing all I/O banks\n");
 	/* freeze all IO banks */
 	sys_mgr_frzctrl_freeze_req();
+
+	debug("Reconfigure Clock Manager\n");
+	/* reconfigure the PLLs */
+	cm_basic_init(&cm_default_cfg);
  
 	/* configure the pin muxing through system manager */
 	sysmgr_pinmux_init();
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_CLOCK_MANAGER_H_
+#define	_CLOCK_MANAGER_H_
+
+typedef struct {
+	/* main group */
+	uint32_t main_vco_base;
+	uint32_t mpuclk;
+	uint32_t mainclk;
+	uint32_t dbgatclk;
+	uint32_t mainqspiclk;
+	uint32_t mainnandsdmmcclk;
+	uint32_t cfg2fuser0clk;
+	uint32_t maindiv;
+	uint32_t dbgdiv;
+	uint32_t tracediv;
+	uint32_t l4src;
+
+	/* peripheral group */
+	uint32_t peri_vco_base;
+	uint32_t emac0clk;
+	uint32_t emac1clk;
+	uint32_t perqspiclk;
+	uint32_t pernandsdmmcclk;
+	uint32_t perbaseclk;
+	uint32_t s2fuser1clk;
+	uint32_t perdiv;
+	uint32_t gpiodiv;
+	uint32_t persrc;
+
+	/* sdram pll group */
+	uint32_t sdram_vco_base;
+	uint32_t ddrdqsclk;
+	uint32_t ddr2xdqsclk;
+	uint32_t ddrdqclk;
+	uint32_t s2fuser2clk;
+} cm_config_t;
+
+extern void cm_basic_init(const cm_config_t *cfg);
+
+struct socfpga_clock_manager {
+	u32	ctrl;
+	u32	bypass;
+	u32	inter;
+	u32	intren;
+	u32	dbctrl;
+	u32	stat;
+	u32	_pad_0x18_0x3f[10];
+	u32	mainpllgrp;
+	u32	perpllgrp;
+	u32	sdrpllgrp;
+	u32	_pad_0xe0_0x200[72];
+
+	u32	main_pll_vco;
+	u32	main_pll_misc;
+	u32	main_pll_mpuclk;
+	u32	main_pll_mainclk;
+	u32	main_pll_dbgatclk;
+	u32	main_pll_mainqspiclk;
+	u32	main_pll_mainnandsdmmcclk;
+	u32	main_pll_cfgs2fuser0clk;
+	u32	main_pll_en;
+	u32	main_pll_maindiv;
+	u32	main_pll_dbgdiv;
+	u32	main_pll_tracediv;
+	u32	main_pll_l4src;
+	u32	main_pll_stat;
+	u32	main_pll__pad_0x38_0x40[2];
+
+	u32	per_pll_vco;
+	u32	per_pll_misc;
+	u32	per_pll_emac0clk;
+	u32	per_pll_emac1clk;
+	u32	per_pll_perqspiclk;
+	u32	per_pll_pernandsdmmcclk;
+	u32	per_pll_perbaseclk;
+	u32	per_pll_s2fuser1clk;
+	u32	per_pll_en;
+	u32	per_pll_div;
+	u32	per_pll_gpiodiv;
+	u32	per_pll_src;
+	u32	per_pll_stat;
+	u32	per_pll__pad_0x34_0x40[3];
+
+	u32	sdr_pll_vco;
+	u32	sdr_pll_ctrl;
+	u32	sdr_pll_ddrdqsclk;
+	u32	sdr_pll_ddr2xdqsclk;
+	u32	sdr_pll_ddrdqclk;
+	u32	sdr_pll_s2fuser2clk;
+	u32	sdr_pll_en;
+	u32	sdr_pll_stat;
+};
+
+#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
+#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
+#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
+#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
+#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
+#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
+#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x)  (((x) << 7) & 0x00000380)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
+#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
+#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
+#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
+#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
+#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
+#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
+#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
+#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
+#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
+#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) \
+	(((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) \
+	(((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
+#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008)
+#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002)
+#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007)
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
+#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0)
+#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
+#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
+#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
+#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
+#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
+#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
+#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010)
+#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004)
+#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
+#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
+#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
+#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
+#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00
+#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
+#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
+#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
+
+#define MAIN_VCO_BASE \
+	(CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \
+	CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER))
+
+#define PERI_VCO_BASE \
+	(CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \
+	CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \
+	CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER))
+
+#define SDR_VCO_BASE \
+	(CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \
+	CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \
+	CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER))
+
+#endif /* _CLOCK_MANAGER_H_ */
@@ -11,6 +11,7 @@
 #define SOCFPGA_UART0_ADDRESS 0xffc02000
 #define SOCFPGA_UART1_ADDRESS 0xffc03000
 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
  
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ */
+
+/* This file is generated by Preloader Generator */
+
+#ifndef _PRELOADER_PLL_CONFIG_H_
+#define _PRELOADER_PLL_CONFIG_H_
+
+/* PLL configuration data */
+/* Main PLL */
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM			(0)
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER			(63)
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT		(0)
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT		(0)
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT		(0)
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT		(3)
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT	(3)
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT	(12)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK		(1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK		(1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK		(1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK		(1)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK		(0)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK		(1)
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK		(0)
+/*
+ * To tell where is the clock source:
+ * 0 = MAINPLL
+ * 1 = PERIPHPLL
+ */
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP		(1)
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP		(1)
+
+/* Peripheral PLL */
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM			(1)
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER			(79)
+/*
+ * To tell where is the VCOs source:
+ * 0 = EOSC1
+ * 1 = EOSC2
+ * 2 = F2S
+ */
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC			(0)
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT		(3)
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT		(3)
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT		(1)
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT	(4)
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT		(4)
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT		(9)
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK			(0)
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK		(0)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK		(1)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK		(1)
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK		(6249)
+/*
+ * To tell where is the clock source:
+ * 0 = F2S_PERIPH_REF_CLK
+ * 1 = MAIN_CLK
+ * 2 = PERIPH_CLK
+ */
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC			(2)
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND			(2)
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI			(1)
+
+/* SDRAM PLL */
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz
+ * This if..else... is not required if generated by tools */
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM			(2)
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER			(127)
+#else
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM			(0)
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER			(31)
+#endif /* CONFIG_SOCFPGA_ARRIA5 */
+
+/*
+ * To tell where is the VCOs source:
+ * 0 = EOSC1
+ * 1 = EOSC2
+ * 2 = F2S
+ */
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC			(0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT		(1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE		(0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT		(0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE		(0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT		(1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE		(4)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT		(5)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE		(0)
+
+/* Info for driver */
+#define CONFIG_HPS_CLK_OSC1_HZ			(25000000)
+#define CONFIG_HPS_CLK_MAINVCO_HZ		(1600000000)
+#define CONFIG_HPS_CLK_PERVCO_HZ		(1000000000)
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* The if..else... is not required if generated by tools */
+#define CONFIG_HPS_CLK_SDRVCO_HZ		(1066000000)
+#else
+#define CONFIG_HPS_CLK_SDRVCO_HZ		(800000000)
+#endif
+#define CONFIG_HPS_CLK_EMAC0_HZ			(250000000)
+#define CONFIG_HPS_CLK_EMAC1_HZ			(250000000)
+#define CONFIG_HPS_CLK_USBCLK_HZ		(200000000)
+#define CONFIG_HPS_CLK_NAND_HZ			(50000000)
+#define CONFIG_HPS_CLK_SDMMC_HZ			(200000000)
+#define CONFIG_HPS_CLK_QSPI_HZ			(400000000)
+#define CONFIG_HPS_CLK_SPIM_HZ			(200000000)
+#define CONFIG_HPS_CLK_CAN0_HZ			(100000000)
+#define CONFIG_HPS_CLK_CAN1_HZ			(100000000)
+#define CONFIG_HPS_CLK_GPIODB_HZ		(32000)
+#define CONFIG_HPS_CLK_L4_MP_HZ			(100000000)
+#define CONFIG_HPS_CLK_L4_SP_HZ			(100000000)
+
+#endif /* _PRELOADER_PLL_CONFIG_H_ */
@@ -8,6 +8,7 @@
  
 #include <asm/arch/socfpga_base_addrs.h>
 #include "../../board/altera/socfpga/pinmux_config.h"
+#include "../../board/altera/socfpga/pll_config.h"
  
 /*
  * High level configuration
...	...	@@ -8,6 +8,6 @@
8	8	#
9	9
10	10	obj-y := lowlevel_init.o
11		-obj-y += misc.o timer.o reset_manager.o system_manager.o
	11	+obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o
12	12	obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
	1	+/*
	2	+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#include <common.h>
	8	+#include <asm/io.h>
	9	+#include <asm/arch/clock_manager.h>
	10	+
	11	+static const struct socfpga_clock_manager *clock_manager_base =
	12	+ (void *)SOCFPGA_CLKMGR_ADDRESS;
	13	+
	14	+#define CLKMGR_BYPASS_ENABLE 1
	15	+#define CLKMGR_BYPASS_DISABLE 0
	16	+#define CLKMGR_STAT_IDLE 0
	17	+#define CLKMGR_STAT_BUSY 1
	18	+#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0
	19	+#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1
	20	+#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0
	21	+#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1
	22	+
	23	+#define CLEAR_BGP_EN_PWRDN \
	24	+ (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)\| \
	25	+ CLKMGR_MAINPLLGRP_VCO_EN_SET(0)\| \
	26	+ CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
	27	+
	28	+#define VCO_EN_BASE \
	29	+ (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)\| \
	30	+ CLKMGR_MAINPLLGRP_VCO_EN_SET(1)\| \
	31	+ CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
	32	+
	33	+static inline void cm_wait_for_lock(uint32_t mask)
	34	+{
	35	+ register uint32_t inter_val;
	36	+ do {
	37	+ inter_val = readl(&clock_manager_base->inter) & mask;
	38	+ } while (inter_val != mask);
	39	+}
	40	+
	41	+/* function to poll in the fsm busy bit */
	42	+static inline void cm_wait_for_fsm(void)
	43	+{
	44	+ while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
	45	+ ;
	46	+}
	47	+
	48	+/*
	49	+ * function to write the bypass register which requires a poll of the
	50	+ * busy bit
	51	+ */
	52	+static inline void cm_write_bypass(uint32_t val)
	53	+{
	54	+ writel(val, &clock_manager_base->bypass);
	55	+ cm_wait_for_fsm();
	56	+}
	57	+
	58	+/* function to write the ctrl register which requires a poll of the busy bit */
	59	+static inline void cm_write_ctrl(uint32_t val)
	60	+{
	61	+ writel(val, &clock_manager_base->ctrl);
	62	+ cm_wait_for_fsm();
	63	+}
	64	+
	65	+/* function to write a clock register that has phase information */
	66	+static inline void cm_write_with_phase(uint32_t value,
	67	+ uint32_t reg_address, uint32_t mask)
	68	+{
	69	+ /* poll until phase is zero */
	70	+ while (readl(reg_address) & mask)
	71	+ ;
	72	+
	73	+ writel(value, reg_address);
	74	+
	75	+ while (readl(reg_address) & mask)
	76	+ ;
	77	+}
	78	+
	79	+/*
	80	+ * Setup clocks while making no assumptions about previous state of the clocks.
	81	+ *
	82	+ * Start by being paranoid and gate all sw managed clocks
	83	+ * Put all plls in bypass
	84	+ * Put all plls VCO registers back to reset value (bandgap power down).
	85	+ * Put peripheral and main pll src to reset value to avoid glitch.
	86	+ * Delay 5 us.
	87	+ * Deassert bandgap power down and set numerator and denominator
	88	+ * Start 7 us timer.
	89	+ * set internal dividers
	90	+ * Wait for 7 us timer.
	91	+ * Enable plls
	92	+ * Set external dividers while plls are locking
	93	+ * Wait for pll lock
	94	+ * Assert/deassert outreset all.
	95	+ * Take all pll's out of bypass
	96	+ * Clear safe mode
	97	+ * set source main and peripheral clocks
	98	+ * Ungate clocks
	99	+ */
	100	+
	101	+void cm_basic_init(const cm_config_t *cfg)
	102	+{
	103	+ uint32_t start, timeout;
	104	+
	105	+ /* Start by being paranoid and gate all sw managed clocks */
	106	+
	107	+ /*
	108	+ * We need to disable nandclk
	109	+ * and then do another apb access before disabling
	110	+ * gatting off the rest of the periperal clocks.
	111	+ */
	112	+ writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
	113	+ readl(&clock_manager_base->per_pll_en),
	114	+ &clock_manager_base->per_pll_en);
	115	+
	116	+ /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
	117	+ writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK \|
	118	+ CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK \|
	119	+ CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK \|
	120	+ CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK \|
	121	+ CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK \|
	122	+ CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
	123	+ &clock_manager_base->main_pll_en);
	124	+
	125	+ writel(0, &clock_manager_base->sdr_pll_en);
	126	+
	127	+ /* now we can gate off the rest of the peripheral clocks */
	128	+ writel(0, &clock_manager_base->per_pll_en);
	129	+
	130	+ /* Put all plls in bypass */
	131	+ cm_write_bypass(
	132	+ CLKMGR_BYPASS_PERPLLSRC_SET(
	133	+ CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) \|
	134	+ CLKMGR_BYPASS_SDRPLLSRC_SET(
	135	+ CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) \|
	136	+ CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) \|
	137	+ CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) \|
	138	+ CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
	139	+
	140	+ /*
	141	+ * Put all plls VCO registers back to reset value.
	142	+ * Some code might have messed with them.
	143	+ */
	144	+ writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
	145	+ &clock_manager_base->main_pll_vco);
	146	+ writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
	147	+ &clock_manager_base->per_pll_vco);
	148	+ writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
	149	+ &clock_manager_base->sdr_pll_vco);
	150	+
	151	+ /*
	152	+ * The clocks to the flash devices and the L4_MAIN clocks can
	153	+ * glitch when coming out of safe mode if their source values
	154	+ * are different from their reset value. So the trick it to
	155	+ * put them back to their reset state, and change input
	156	+ * after exiting safe mode but before ungating the clocks.
	157	+ */
	158	+ writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
	159	+ &clock_manager_base->per_pll_src);
	160	+ writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
	161	+ &clock_manager_base->main_pll_l4src);
	162	+
	163	+ /* read back for the required 5 us delay. */
	164	+ readl(&clock_manager_base->main_pll_vco);
	165	+ readl(&clock_manager_base->per_pll_vco);
	166	+ readl(&clock_manager_base->sdr_pll_vco);
	167	+
	168	+
	169	+ /*
	170	+ * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
	171	+ * with numerator and denominator.
	172	+ */
	173	+ writel(cfg->main_vco_base \| CLEAR_BGP_EN_PWRDN \|
	174	+ CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
	175	+ &clock_manager_base->main_pll_vco);
	176	+
	177	+ writel(cfg->peri_vco_base \| CLEAR_BGP_EN_PWRDN \|
	178	+ CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
	179	+ &clock_manager_base->per_pll_vco);
	180	+
	181	+ writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) \|
	182	+ CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) \|
	183	+ cfg->sdram_vco_base \| CLEAR_BGP_EN_PWRDN \|
	184	+ CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
	185	+ &clock_manager_base->sdr_pll_vco);
	186	+
	187	+ /*
	188	+ * Time starts here
	189	+ * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
	190	+ */
	191	+ reset_timer();
	192	+ start = get_timer(0);
	193	+ /* timeout in unit of us as CONFIG_SYS_HZ = 10001000 /
	194	+ timeout = 7;
	195	+
	196	+ /* main mpu */
	197	+ writel(cfg->mpuclk, &clock_manager_base->main_pll_mpuclk);
	198	+
	199	+ /* main main clock */
	200	+ writel(cfg->mainclk, &clock_manager_base->main_pll_mainclk);
	201	+
	202	+ /* main for dbg */
	203	+ writel(cfg->dbgatclk, &clock_manager_base->main_pll_dbgatclk);
	204	+
	205	+ /* main for cfgs2fuser0clk */
	206	+ writel(cfg->cfg2fuser0clk,
	207	+ &clock_manager_base->main_pll_cfgs2fuser0clk);
	208	+
	209	+ /* Peri emac0 50 MHz default to RMII */
	210	+ writel(cfg->emac0clk, &clock_manager_base->per_pll_emac0clk);
	211	+
	212	+ /* Peri emac1 50 MHz default to RMII */
	213	+ writel(cfg->emac1clk, &clock_manager_base->per_pll_emac1clk);
	214	+
	215	+ /* Peri QSPI */
	216	+ writel(cfg->mainqspiclk, &clock_manager_base->main_pll_mainqspiclk);
	217	+
	218	+ writel(cfg->perqspiclk, &clock_manager_base->per_pll_perqspiclk);
	219	+
	220	+ /* Peri pernandsdmmcclk */
	221	+ writel(cfg->pernandsdmmcclk,
	222	+ &clock_manager_base->per_pll_pernandsdmmcclk);
	223	+
	224	+ /* Peri perbaseclk */
	225	+ writel(cfg->perbaseclk, &clock_manager_base->per_pll_perbaseclk);
	226	+
	227	+ /* Peri s2fuser1clk */
	228	+ writel(cfg->s2fuser1clk, &clock_manager_base->per_pll_s2fuser1clk);
	229	+
	230	+ /* 7 us must have elapsed before we can enable the VCO */
	231	+ while (get_timer(start) < timeout)
	232	+ ;
	233	+
	234	+ /* Enable vco */
	235	+ /* main pll vco */
	236	+ writel(cfg->main_vco_base \| VCO_EN_BASE,
	237	+ &clock_manager_base->main_pll_vco);
	238	+
	239	+ /* periferal pll */
	240	+ writel(cfg->peri_vco_base \| VCO_EN_BASE,
	241	+ &clock_manager_base->per_pll_vco);
	242	+
	243	+ /* sdram pll vco */
	244	+ writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) \|
	245	+ CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) \|
	246	+ cfg->sdram_vco_base \| VCO_EN_BASE,
	247	+ &clock_manager_base->sdr_pll_vco);
	248	+
	249	+ /* L3 MP and L3 SP */
	250	+ writel(cfg->maindiv, &clock_manager_base->main_pll_maindiv);
	251	+
	252	+ writel(cfg->dbgdiv, &clock_manager_base->main_pll_dbgdiv);
	253	+
	254	+ writel(cfg->tracediv, &clock_manager_base->main_pll_tracediv);
	255	+
	256	+ /* L4 MP, L4 SP, can0, and can1 */
	257	+ writel(cfg->perdiv, &clock_manager_base->per_pll_div);
	258	+
	259	+ writel(cfg->gpiodiv, &clock_manager_base->per_pll_gpiodiv);
	260	+
	261	+#define LOCKED_MASK \
	262	+ (CLKMGR_INTER_SDRPLLLOCKED_MASK \| \
	263	+ CLKMGR_INTER_PERPLLLOCKED_MASK \| \
	264	+ CLKMGR_INTER_MAINPLLLOCKED_MASK)
	265	+
	266	+ cm_wait_for_lock(LOCKED_MASK);
	267	+
	268	+ /* write the sdram clock counters before toggling outreset all */
	269	+ writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
	270	+ &clock_manager_base->sdr_pll_ddrdqsclk);
	271	+
	272	+ writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
	273	+ &clock_manager_base->sdr_pll_ddr2xdqsclk);
	274	+
	275	+ writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
	276	+ &clock_manager_base->sdr_pll_ddrdqclk);
	277	+
	278	+ writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
	279	+ &clock_manager_base->sdr_pll_s2fuser2clk);
	280	+
	281	+ /*
	282	+ * after locking, but before taking out of bypass
	283	+ * assert/deassert outresetall
	284	+ */
	285	+ uint32_t mainvco = readl(&clock_manager_base->main_pll_vco);
	286	+
	287	+ /* assert main outresetall */
	288	+ writel(mainvco \| CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
	289	+ &clock_manager_base->main_pll_vco);
	290	+
	291	+ uint32_t periphvco = readl(&clock_manager_base->per_pll_vco);
	292	+
	293	+ /* assert pheriph outresetall */
	294	+ writel(periphvco \| CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
	295	+ &clock_manager_base->per_pll_vco);
	296	+
	297	+ /* assert sdram outresetall */
	298	+ writel(cfg->sdram_vco_base \| VCO_EN_BASE\|
	299	+ CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
	300	+ &clock_manager_base->sdr_pll_vco);
	301	+
	302	+ /* deassert main outresetall */
	303	+ writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
	304	+ &clock_manager_base->main_pll_vco);
	305	+
	306	+ /* deassert pheriph outresetall */
	307	+ writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
	308	+ &clock_manager_base->per_pll_vco);
	309	+
	310	+ /* deassert sdram outresetall */
	311	+ writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) \|
	312	+ cfg->sdram_vco_base \| VCO_EN_BASE,
	313	+ &clock_manager_base->sdr_pll_vco);
	314	+
	315	+ /*
	316	+ * now that we've toggled outreset all, all the clocks
	317	+ * are aligned nicely; so we can change any phase.
	318	+ */
	319	+ cm_write_with_phase(cfg->ddrdqsclk,
	320	+ (uint32_t)&clock_manager_base->sdr_pll_ddrdqsclk,
	321	+ CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
	322	+
	323	+ /* SDRAM DDR2XDQSCLK */
	324	+ cm_write_with_phase(cfg->ddr2xdqsclk,
	325	+ (uint32_t)&clock_manager_base->sdr_pll_ddr2xdqsclk,
	326	+ CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
	327	+
	328	+ cm_write_with_phase(cfg->ddrdqclk,
	329	+ (uint32_t)&clock_manager_base->sdr_pll_ddrdqclk,
	330	+ CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
	331	+
	332	+ cm_write_with_phase(cfg->s2fuser2clk,
	333	+ (uint32_t)&clock_manager_base->sdr_pll_s2fuser2clk,
	334	+ CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
	335	+
	336	+ /* Take all three PLLs out of bypass when safe mode is cleared. */
	337	+ cm_write_bypass(
	338	+ CLKMGR_BYPASS_PERPLLSRC_SET(
	339	+ CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) \|
	340	+ CLKMGR_BYPASS_SDRPLLSRC_SET(
	341	+ CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) \|
	342	+ CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) \|
	343	+ CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) \|
	344	+ CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
	345	+
	346	+ /* clear safe mode */
	347	+ cm_write_ctrl(readl(&clock_manager_base->ctrl) \|
	348	+ CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
	349	+
	350	+ /*
	351	+ * now that safe mode is clear with clocks gated
	352	+ * it safe to change the source mux for the flashes the the L4_MAIN
	353	+ */
	354	+ writel(cfg->persrc, &clock_manager_base->per_pll_src);
	355	+ writel(cfg->l4src, &clock_manager_base->main_pll_l4src);
	356	+
	357	+ /* Now ungate non-hw-managed clocks */
	358	+ writel(~0, &clock_manager_base->main_pll_en);
	359	+ writel(~0, &clock_manager_base->per_pll_en);
	360	+ writel(~0, &clock_manager_base->sdr_pll_en);
	361	+}
...	...	@@ -28,9 +28,98 @@
28	28	void spl_board_init(void)
29	29	{
30	30	#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
	31	+ cm_config_t cm_default_cfg = {
	32	+ /* main group */
	33	+ MAIN_VCO_BASE,
	34	+ CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(
	35	+ CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
	36	+ CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(
	37	+ CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
	38	+ CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(
	39	+ CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
	40	+ CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(
	41	+ CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
	42	+ CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
	43	+ CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
	44	+ CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(
	45	+ CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
	46	+ CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(
	47	+ CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) \|
	48	+ CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(
	49	+ CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) \|
	50	+ CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(
	51	+ CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) \|
	52	+ CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(
	53	+ CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
	54	+ CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(
	55	+ CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) \|
	56	+ CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(
	57	+ CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
	58	+ CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(
	59	+ CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
	60	+ CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(
	61	+ CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) \|
	62	+ CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(
	63	+ CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),
	64	+
	65	+ /* peripheral group */
	66	+ PERI_VCO_BASE,
	67	+ CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(
	68	+ CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
	69	+ CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(
	70	+ CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
	71	+ CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(
	72	+ CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
	73	+ CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
	74	+ CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
	75	+ CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(
	76	+ CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
	77	+ CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(
	78	+ CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
	79	+ CLKMGR_PERPLLGRP_DIV_USBCLK_SET(
	80	+ CONFIG_HPS_PERPLLGRP_DIV_USBCLK) \|
	81	+ CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(
	82	+ CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) \|
	83	+ CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(
	84	+ CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) \|
	85	+ CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(
	86	+ CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
	87	+ CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(
	88	+ CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
	89	+ CLKMGR_PERPLLGRP_SRC_QSPI_SET(
	90	+ CONFIG_HPS_PERPLLGRP_SRC_QSPI) \|
	91	+ CLKMGR_PERPLLGRP_SRC_NAND_SET(
	92	+ CONFIG_HPS_PERPLLGRP_SRC_NAND) \|
	93	+ CLKMGR_PERPLLGRP_SRC_SDMMC_SET(
	94	+ CONFIG_HPS_PERPLLGRP_SRC_SDMMC),
	95	+
	96	+ /* sdram pll group */
	97	+ SDR_VCO_BASE,
	98	+ CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(
	99	+ CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) \|
	100	+ CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(
	101	+ CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
	102	+ CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(
	103	+ CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) \|
	104	+ CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(
	105	+ CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
	106	+ CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(
	107	+ CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) \|
	108	+ CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(
	109	+ CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
	110	+ CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(
	111	+ CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) \|
	112	+ CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(
	113	+ CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
	114	+ };
	115	+
31	116	debug("Freezing all I/O banks\n");
32	117	/* freeze all IO banks */
33	118	sys_mgr_frzctrl_freeze_req();
	119	+
	120	+ debug("Reconfigure Clock Manager\n");
	121	+ /* reconfigure the PLLs */
	122	+ cm_basic_init(&cm_default_cfg);
34	123
35	124	/* configure the pin muxing through system manager */
36	125	sysmgr_pinmux_init();
...	...	@@ -11,6 +11,7 @@
11	11	#define SOCFPGA_UART0_ADDRESS 0xffc02000
12	12	#define SOCFPGA_UART1_ADDRESS 0xffc03000
13	13	#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
	14	+#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
14	15	#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
15	16	#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
16	17
	1	+/*
	2	+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
	3	+ *
	4	+ * SPDX-License-Identifier: BSD-3-Clause
	5	+ */
	6	+
	7	+/* This file is generated by Preloader Generator */
	8	+
	9	+#ifndef _PRELOADER_PLL_CONFIG_H_
	10	+#define _PRELOADER_PLL_CONFIG_H_
	11	+
	12	+/* PLL configuration data */
	13	+/* Main PLL */
	14	+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0)
	15	+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63)
	16	+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)
	17	+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)
	18	+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
	19	+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3)
	20	+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3)
	21	+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (12)
	22	+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1)
	23	+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1)
	24	+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1)
	25	+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1)
	26	+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0)
	27	+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1)
	28	+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0)
	29	+/*
	30	+ * To tell where is the clock source:
	31	+ * 0 = MAINPLL
	32	+ * 1 = PERIPHPLL
	33	+ */
	34	+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1)
	35	+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1)
	36	+
	37	+/* Peripheral PLL */
	38	+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1)
	39	+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79)
	40	+/*
	41	+ * To tell where is the VCOs source:
	42	+ * 0 = EOSC1
	43	+ * 1 = EOSC2
	44	+ * 2 = F2S
	45	+ */
	46	+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0)
	47	+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3)
	48	+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3)
	49	+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1)
	50	+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4)
	51	+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4)
	52	+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9)
	53	+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0)
	54	+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0)
	55	+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1)
	56	+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1)
	57	+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249)
	58	+/*
	59	+ * To tell where is the clock source:
	60	+ * 0 = F2S_PERIPH_REF_CLK
	61	+ * 1 = MAIN_CLK
	62	+ * 2 = PERIPH_CLK
	63	+ */
	64	+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2)
	65	+#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2)
	66	+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1)
	67	+
	68	+/* SDRAM PLL */
	69	+#ifdef CONFIG_SOCFPGA_ARRIA5
	70	+/* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz
	71	+ * This if..else... is not required if generated by tools */
	72	+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2)
	73	+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (127)
	74	+#else
	75	+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0)
	76	+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31)
	77	+#endif /* CONFIG_SOCFPGA_ARRIA5 */
	78	+
	79	+/*
	80	+ * To tell where is the VCOs source:
	81	+ * 0 = EOSC1
	82	+ * 1 = EOSC2
	83	+ * 2 = F2S
	84	+ */
	85	+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0)
	86	+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1)
	87	+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0)
	88	+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0)
	89	+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0)
	90	+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1)
	91	+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4)
	92	+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5)
	93	+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0)
	94	+
	95	+/* Info for driver */
	96	+#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
	97	+#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
	98	+#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
	99	+#ifdef CONFIG_SOCFPGA_ARRIA5
	100	+/* The if..else... is not required if generated by tools */
	101	+#define CONFIG_HPS_CLK_SDRVCO_HZ (1066000000)
	102	+#else
	103	+#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000)
	104	+#endif
	105	+#define CONFIG_HPS_CLK_EMAC0_HZ (250000000)
	106	+#define CONFIG_HPS_CLK_EMAC1_HZ (250000000)
	107	+#define CONFIG_HPS_CLK_USBCLK_HZ (200000000)
	108	+#define CONFIG_HPS_CLK_NAND_HZ (50000000)
	109	+#define CONFIG_HPS_CLK_SDMMC_HZ (200000000)
	110	+#define CONFIG_HPS_CLK_QSPI_HZ (400000000)
	111	+#define CONFIG_HPS_CLK_SPIM_HZ (200000000)
	112	+#define CONFIG_HPS_CLK_CAN0_HZ (100000000)
	113	+#define CONFIG_HPS_CLK_CAN1_HZ (100000000)
	114	+#define CONFIG_HPS_CLK_GPIODB_HZ (32000)
	115	+#define CONFIG_HPS_CLK_L4_MP_HZ (100000000)
	116	+#define CONFIG_HPS_CLK_L4_SP_HZ (100000000)
	117	+
	118	+#endif /* _PRELOADER_PLL_CONFIG_H_ */
...	...	@@ -8,6 +8,7 @@
8	8
9	9	#include <asm/arch/socfpga_base_addrs.h>
10	10	#include "../../board/altera/socfpga/pinmux_config.h"
	11	+#include "../../board/altera/socfpga/pll_config.h"
11	12
12	13	/*
13	14	* High level configuration