arm: socfpga: Add watchdog disable for socfpga

This adds watchdog disable. It is neccessary for running Linux kernel. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default)

arm: socfpga: Add watchdog disable for socfpga
This adds watchdog disable. It is neccessary for running Linux kernel. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default)
Pavel Machek · Marek Vasut
1 parent be324354ee
Showing 3 changed files with 30 additions and 0 deletions Side-by-side Diff
arch/arm/cpu/armv7/socfpga/misc.c
arch/arm/cpu/armv7/socfpga/reset_manager.c
arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -8,6 +8,7 @@
 #include <asm/io.h>
 #include <miiphy.h>
 #include <netdev.h>
+#include <asm/arch/reset_manager.h>
  
 DECLARE_GLOBAL_DATA_PTR;
  
@@ -35,6 +36,19 @@
 	return 0;
 }
 #endif
+
+int arch_cpu_init(void)
+{
+	/*
+	 * If the HW watchdog is NOT enabled, make sure it is not running,
+	 * for example because it was enabled in the preloader. This might
+	 * trigger a watchdog-triggered reboot of Linux kernel later.
+	 */
+#ifndef CONFIG_HW_WATCHDOG
+	socfpga_watchdog_reset();
+#endif
+	return 0;
+}
  
 int misc_init_r(void)
 {
@@ -14,6 +14,18 @@
 static const struct socfpga_reset_manager *reset_manager_base =
 		(void *)SOCFPGA_RSTMGR_ADDRESS;
  
+/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
+void socfpga_watchdog_reset(void)
+{
+	/* assert reset for watchdog */
+	setbits_le32(&reset_manager_base->per_mod_reset,
+		     1 << RSTMGR_PERMODRST_L4WD0_LSB);
+
+	/* deassert watchdog from reset (watchdog in not running state) */
+	clrbits_le32(&reset_manager_base->per_mod_reset,
+		     1 << RSTMGR_PERMODRST_L4WD0_LSB);
+}
+
 /*
  * Write the reset manager register to cause reset
  */
@@ -10,6 +10,8 @@
 void reset_cpu(ulong addr);
 void reset_deassert_peripherals_handoff(void);
  
+void socfpga_watchdog_reset(void);
+
 struct socfpga_reset_manager {
 	u32	status;
 	u32	ctrl;
@@ -26,6 +28,8 @@
 #else
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
 #endif
+
+#define RSTMGR_PERMODRST_L4WD0_LSB	6
  
 #endif /* _RESET_MANAGER_H_ */
...	...	@@ -8,6 +8,7 @@
8	8	#include <asm/io.h>
9	9	#include <miiphy.h>
10	10	#include <netdev.h>
	11	+#include <asm/arch/reset_manager.h>
11	12
12	13	DECLARE_GLOBAL_DATA_PTR;
13	14
...	...	@@ -35,6 +36,19 @@
35	36	return 0;
36	37	}
37	38	#endif
	39	+
	40	+int arch_cpu_init(void)
	41	+{
	42	+ /*
	43	+ * If the HW watchdog is NOT enabled, make sure it is not running,
	44	+ * for example because it was enabled in the preloader. This might
	45	+ * trigger a watchdog-triggered reboot of Linux kernel later.
	46	+ */
	47	+#ifndef CONFIG_HW_WATCHDOG
	48	+ socfpga_watchdog_reset();
	49	+#endif
	50	+ return 0;
	51	+}
38	52
39	53	int misc_init_r(void)
40	54	{
...	...	@@ -14,6 +14,18 @@
14	14	static const struct socfpga_reset_manager *reset_manager_base =
15	15	(void *)SOCFPGA_RSTMGR_ADDRESS;
16	16
	17	+/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
	18	+void socfpga_watchdog_reset(void)
	19	+{
	20	+ /* assert reset for watchdog */
	21	+ setbits_le32(&reset_manager_base->per_mod_reset,
	22	+ 1 << RSTMGR_PERMODRST_L4WD0_LSB);
	23	+
	24	+ /* deassert watchdog from reset (watchdog in not running state) */
	25	+ clrbits_le32(&reset_manager_base->per_mod_reset,
	26	+ 1 << RSTMGR_PERMODRST_L4WD0_LSB);
	27	+}
	28	+
17	29	/*
18	30	* Write the reset manager register to cause reset
19	31	*/
...	...	@@ -10,6 +10,8 @@
10	10	void reset_cpu(ulong addr);
11	11	void reset_deassert_peripherals_handoff(void);
12	12
	13	+void socfpga_watchdog_reset(void);
	14	+
13	15	struct socfpga_reset_manager {
14	16	u32 status;
15	17	u32 ctrl;
...	...	@@ -26,6 +28,8 @@
26	28	#else
27	29	#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
28	30	#endif
	31	+
	32	+#define RSTMGR_PERMODRST_L4WD0_LSB 6
29	33
30	34	#endif /* _RESET_MANAGER_H_ */