Eric Lee / smarc-uboot

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Commit dee332ffb735f65ab922118791a583c17bb0b795

Authored by Tom Rini
2 parents 1739564e75 e7eb277dce
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge branch 'master' of git://www.denx.de/git/u-boot-imx

Showing 77 changed files Side-by-side Diff

arch/arm/cpu/arm926ejs/mx27/Makefile
Diff comments   View file @ dee332f
... ... @@ -5,4 +5,8 @@
5 5 # SPDX-License-Identifier: GPL-2.0+
6 6  
7 7 obj-y = generic.o reset.o timer.o
  8 +
  9 +ifndef CONFIG_SPL_BUILD
  10 +obj-y += relocate.o
  11 +endif
arch/arm/cpu/arm926ejs/mx27/relocate.S
Diff comments   View file @ dee332f
  1 +/*
  2 + * relocate - i.MX27-specific vector relocation
  3 + *
  4 + * Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <asm-offsets.h>
  10 +#include <config.h>
  11 +#include <linux/linkage.h>
  12 +
  13 +/*
  14 + * The i.MX27 SoC is very specific with respect to exceptions: it
  15 + * does not provide RAM at the high vectors address (0xFFFF0000),
  16 + * thus only the low address (0x00000000) is useable; but that is
  17 + * in ROM. Therefore, vectors cannot be changed at all.
  18 + *
  19 + * However, these ROM-based vectors actually just perform indirect
  20 + * calls through pointers located in RAM at SoC-specific addresses,
  21 + * as follows:
  22 + *
  23 + * Offset Exception Use by ROM code
  24 + * 0x00000000 reset indirect branch to [0x00000014]
  25 + * 0x00000004 undefined instruction indirect branch to [0xfffffef0]
  26 + * 0x00000008 software interrupt indirect branch to [0xfffffef4]
  27 + * 0x0000000c prefetch abort indirect branch to [0xfffffef8]
  28 + * 0x00000010 data abort indirect branch to [0xfffffefc]
  29 + * 0x00000014 (reserved in ARMv5) vector to ROM reset: 0xc0000000
  30 + * 0x00000018 IRQ indirect branch to [0xffffff00]
  31 + * 0x0000001c FIQ indirect branch to [0xffffff04]
  32 + *
  33 + * In order to initialize exceptions on i.MX27, we must copy U-Boot's
  34 + * indirect (not exception!) vector table into 0xfffffef0..0xffffff04
  35 + * taking care not to copy vectors number 5 (reserved exception).
  36 + */
  37 +
  38 + .section .text.relocate_vectors,"ax",%progbits
  39 +
  40 +ENTRY(relocate_vectors)
  41 +
  42 + ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
  43 + ldr r1, =32 /* size of vector table */
  44 + add r0, r0, r1 /* skip to indirect table */
  45 + ldr r1, =0xFFFFFEF0 /* i.MX27 indirect table */
  46 + ldmia r0!, {r2-r8} /* load indirect vectors 1..7 */
  47 + stmia r1!, {r2-r5, r7,r8} /* write all but vector 5 */
  48 +
  49 + bx lr
  50 +
  51 +ENDPROC(relocate_vectors)
arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg
Diff comments   View file @ dee332f
  1 +DISPLAYPROGRESS
1 2 SECTION 0x0 BOOTABLE
2 3 TAG LAST
3 4 LOAD 0x1000 spl/u-boot-spl.bin
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
Diff comments   View file @ dee332f
  1 +DISPLAYPROGRESS
1 2 SECTION 0x0 BOOTABLE
2 3 TAG LAST
3 4 LOAD 0x1000 spl/u-boot-spl.bin
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
Diff comments   View file @ dee332f
  1 +DISPLAYPROGRESS
1 2 SECTION 0x0 BOOTABLE
2 3 TAG LAST
3 4 LOAD 0x1000 spl/u-boot-spl.bin
arch/arm/cpu/armv7/mx5/soc.c
Diff comments   View file @ dee332f
... ... @@ -85,37 +85,6 @@
85 85 }
86 86 #endif
87 87  
88   -void set_chipselect_size(int const cs_size)
89   -{
90   - unsigned int reg;
91   - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
92   - reg = readl(&iomuxc_regs->gpr1);
93   -
94   - switch (cs_size) {
95   - case CS0_128:
96   - reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
97   - reg |= 0x5;
98   - break;
99   - case CS0_64M_CS1_64M:
100   - reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
101   - reg |= 0x1B;
102   - break;
103   - case CS0_64M_CS1_32M_CS2_32M:
104   - reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
105   - reg |= 0x4B;
106   - break;
107   - case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
108   - reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
109   - reg |= 0x249;
110   - break;
111   - default:
112   - printf("Unknown chip select size: %d\n", cs_size);
113   - break;
114   - }
115   -
116   - writel(reg, &iomuxc_regs->gpr1);
117   -}
118   -
119 88 #ifdef CONFIG_MX53
120 89 void boot_mode_apply(unsigned cfg_val)
121 90 {
arch/arm/cpu/armv7/mx6/clock.c
Diff comments   View file @ dee332f
... ... @@ -596,6 +596,14 @@
596 596 ungate_sata_clock();
597 597 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
598 598 }
  599 +
  600 +void disable_sata_clock(void)
  601 +{
  602 + struct mxc_ccm_reg *const imx_ccm =
  603 + (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  604 +
  605 + clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
  606 +}
599 607 #endif
600 608  
601 609 int enable_pcie_clock(void)
... ... @@ -672,6 +680,36 @@
672 680 __raw_writel(reg, &imx_ccm->CCGR6);
673 681 }
674 682 #endif
  683 +
  684 +static void enable_pll3(void)
  685 +{
  686 + struct anatop_regs __iomem *anatop =
  687 + (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
  688 +
  689 + /* make sure pll3 is enabled */
  690 + if ((readl(&anatop->usb1_pll_480_ctrl) &
  691 + BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
  692 + /* enable pll's power */
  693 + writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
  694 + &anatop->usb1_pll_480_ctrl_set);
  695 + writel(0x80, &anatop->ana_misc2_clr);
  696 + /* wait for pll lock */
  697 + while ((readl(&anatop->usb1_pll_480_ctrl) &
  698 + BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
  699 + ;
  700 + /* disable bypass */
  701 + writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
  702 + &anatop->usb1_pll_480_ctrl_clr);
  703 + /* enable pll output */
  704 + writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
  705 + &anatop->usb1_pll_480_ctrl_set);
  706 + }
  707 +}
  708 +
  709 +void enable_thermal_clk(void)
  710 +{
  711 + enable_pll3();
  712 +}
675 713  
676 714 unsigned int mxc_get_clock(enum mxc_clock clk)
677 715 {
arch/arm/cpu/armv7/mx6/soc.c
Diff comments   View file @ dee332f
... ... @@ -22,6 +22,8 @@
22 22 #include <asm/arch/mxc_hdmi.h>
23 23 #include <asm/arch/crm_regs.h>
24 24 #include <asm/bootm.h>
  25 +#include <dm.h>
  26 +#include <imx_thermal.h>
25 27  
26 28 enum ldo_reg {
27 29 LDO_ARM,
... ... @@ -36,6 +38,19 @@
36 38 u32 invalidate;
37 39 u32 fpga_rev;
38 40 };
  41 +
  42 +#if defined(CONFIG_IMX6_THERMAL)
  43 +static const struct imx_thermal_plat imx6_thermal_plat = {
  44 + .regs = (void *)ANATOP_BASE_ADDR,
  45 + .fuse_bank = 1,
  46 + .fuse_word = 6,
  47 +};
  48 +
  49 +U_BOOT_DEVICE(imx6_thermal) = {
  50 + .name = "imx_thermal",
  51 + .platdata = &imx6_thermal_plat,
  52 +};
  53 +#endif
39 54  
40 55 u32 get_nr_cpus(void)
41 56 {
arch/arm/cpu/armv7/omap-common/sata.c
Diff comments   View file @ dee332f
... ... @@ -74,6 +74,11 @@
74 74 return ret;
75 75 }
76 76  
  77 +int reset_sata(int dev)
  78 +{
  79 + return 0;
  80 +}
  81 +
77 82 /* On OMAP platforms SATA provides the SCSI subsystem */
78 83 void scsi_init(void)
79 84 {
arch/arm/imx-common/cpu.c
Diff comments   View file @ dee332f
... ... @@ -17,6 +17,8 @@
17 17 #include <asm/arch/sys_proto.h>
18 18 #include <asm/arch/crm_regs.h>
19 19 #include <ipu_pixfmt.h>
  20 +#include <thermal.h>
  21 +#include <sata.h>
20 22  
21 23 #ifdef CONFIG_FSL_ESDHC
22 24 #include <fsl_esdhc.h>
... ... @@ -134,6 +136,11 @@
134 136 {
135 137 u32 cpurev;
136 138  
  139 +#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
  140 + struct udevice *thermal_dev;
  141 + int cpu_tmp, ret;
  142 +#endif
  143 +
137 144 cpurev = get_cpu_rev();
138 145  
139 146 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
... ... @@ -141,6 +148,21 @@
141 148 (cpurev & 0x000F0) >> 4,
142 149 (cpurev & 0x0000F) >> 0,
143 150 mxc_get_clock(MXC_ARM_CLK) / 1000000);
  151 +
  152 +#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
  153 + ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
  154 + if (!ret) {
  155 + ret = thermal_get_temp(thermal_dev, &cpu_tmp);
  156 +
  157 + if (!ret)
  158 + printf("CPU: Temperature %d C\n", cpu_tmp);
  159 + else
  160 + printf("CPU: Temperature: invalid sensor data\n");
  161 + } else {
  162 + printf("CPU: Temperature: Can't find sensor device\n");
  163 + }
  164 +#endif
  165 +
144 166 printf("Reset cause: %s\n", get_reset_cause());
145 167 return 0;
146 168 }
147 169  
148 170  
149 171  
... ... @@ -180,11 +202,45 @@
180 202 return get_periph_clk() / (ahb_podf + 1);
181 203 }
182 204  
183   -#if defined(CONFIG_VIDEO_IPUV3)
184 205 void arch_preboot_os(void)
185 206 {
  207 +#if defined(CONFIG_CMD_SATA)
  208 + sata_stop();
  209 +#endif
  210 +#if defined(CONFIG_VIDEO_IPUV3)
186 211 /* disable video before launching O/S */
187 212 ipuv3_fb_shutdown();
188   -}
189 213 #endif
  214 +}
  215 +
  216 +void set_chipselect_size(int const cs_size)
  217 +{
  218 + unsigned int reg;
  219 + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  220 + reg = readl(&iomuxc_regs->gpr[1]);
  221 +
  222 + switch (cs_size) {
  223 + case CS0_128:
  224 + reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
  225 + reg |= 0x5;
  226 + break;
  227 + case CS0_64M_CS1_64M:
  228 + reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
  229 + reg |= 0x1B;
  230 + break;
  231 + case CS0_64M_CS1_32M_CS2_32M:
  232 + reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
  233 + reg |= 0x4B;
  234 + break;
  235 + case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
  236 + reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
  237 + reg |= 0x249;
  238 + break;
  239 + default:
  240 + printf("Unknown chip select size: %d\n", cs_size);
  241 + break;
  242 + }
  243 +
  244 + writel(reg, &iomuxc_regs->gpr[1]);
  245 +}
arch/arm/imx-common/spl_sd.cfg
Diff comments   View file @ dee332f
  1 +/*
  2 + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +IMAGE_VERSION 2
  8 +BOOT_FROM sd
arch/arm/include/asm/arch-imx/cpu.h
Diff comments   View file @ dee332f
... ... @@ -12,4 +12,9 @@
12 12 #define MXC_CPU_MX6Q 0x63
13 13 #define MXC_CPU_MX6D 0x64
14 14 #define MXC_CPU_MX6SOLO 0x65 /* dummy ID */
  15 +
  16 +#define CS0_128 0
  17 +#define CS0_64M_CS1_64M 1
  18 +#define CS0_64M_CS1_32M_CS2_32M 2
  19 +#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
arch/arm/include/asm/arch-mx5/imx-regs.h
Diff comments   View file @ dee332f
... ... @@ -202,11 +202,6 @@
202 202 */
203 203 #define WBED 1
204 204  
205   -#define CS0_128 0
206   -#define CS0_64M_CS1_64M 1
207   -#define CS0_64M_CS1_32M_CS2_32M 2
208   -#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
209   -
210 205 /*
211 206 * CSPI register definitions
212 207 */
... ... @@ -414,8 +409,7 @@
414 409  
415 410 #if defined(CONFIG_MX51)
416 411 struct iomuxc {
417   - u32 gpr0;
418   - u32 gpr1;
  412 + u32 gpr[2];
419 413 u32 omux0;
420 414 u32 omux1;
421 415 u32 omux2;
... ... @@ -424,9 +418,7 @@
424 418 };
425 419 #elif defined(CONFIG_MX53)
426 420 struct iomuxc {
427   - u32 gpr0;
428   - u32 gpr1;
429   - u32 gpr2;
  421 + u32 gpr[3];
430 422 u32 omux0;
431 423 u32 omux1;
432 424 u32 omux2;
arch/arm/include/asm/arch-mx6/clock.h
Diff comments   View file @ dee332f
... ... @@ -60,11 +60,13 @@
60 60 int enable_cspi_clock(unsigned char enable, unsigned spi_num);
61 61 int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
62 62 int enable_sata_clock(void);
  63 +void disable_sata_clock(void);
63 64 int enable_pcie_clock(void);
64 65 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
65 66 int enable_spi_clk(unsigned char enable, unsigned spi_num);
66 67 void enable_ipu_clock(void);
67 68 int enable_fec_anatop_clock(enum enet_freq freq);
68 69 void enable_enet_clk(unsigned char enable);
  70 +void enable_thermal_clk(void);
69 71 #endif /* __ASM_ARCH_CLOCK_H */
arch/arm/include/asm/arch-mx6/imx-regs.h
Diff comments   View file @ dee332f
... ... @@ -332,6 +332,43 @@
332 332 #define SRC_SCR_CORE_3_ENABLE_OFFSET 24
333 333 #define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
334 334  
  335 +/* WEIM registers */
  336 +struct weim {
  337 + u32 cs0gcr1;
  338 + u32 cs0gcr2;
  339 + u32 cs0rcr1;
  340 + u32 cs0rcr2;
  341 + u32 cs0wcr1;
  342 + u32 cs0wcr2;
  343 +
  344 + u32 cs1gcr1;
  345 + u32 cs1gcr2;
  346 + u32 cs1rcr1;
  347 + u32 cs1rcr2;
  348 + u32 cs1wcr1;
  349 + u32 cs1wcr2;
  350 +
  351 + u32 cs2gcr1;
  352 + u32 cs2gcr2;
  353 + u32 cs2rcr1;
  354 + u32 cs2rcr2;
  355 + u32 cs2wcr1;
  356 + u32 cs2wcr2;
  357 +
  358 + u32 cs3gcr1;
  359 + u32 cs3gcr2;
  360 + u32 cs3rcr1;
  361 + u32 cs3rcr2;
  362 + u32 cs3wcr1;
  363 + u32 cs3wcr2;
  364 +
  365 + u32 unused[12];
  366 +
  367 + u32 wcr;
  368 + u32 wiar;
  369 + u32 ear;
  370 +};
  371 +
335 372 /* System Reset Controller (SRC) */
336 373 struct src {
337 374 u32 scr;
arch/arm/include/asm/arch-mx6/sys_proto.h
Diff comments   View file @ dee332f
... ... @@ -26,6 +26,7 @@
26 26  
27 27 const char *get_imx_type(u32 imxtype);
28 28 unsigned imx_ddr_size(void);
  29 +void set_chipselect_size(int const);
29 30  
30 31 /*
31 32 * Initializes on-chip ethernet controllers.
... ... @@ -104,6 +104,11 @@
104 104 ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
105 105 b relocate_code
106 106 here:
  107 +/*
  108 + * now relocate vectors
  109 + */
  110 +
  111 + bl relocate_vectors
107 112  
108 113 /* Set up final (full) environment */
109 114  
arch/arm/lib/relocate.S
Diff comments   View file @ dee332f
... ... @@ -11,6 +11,47 @@
11 11 #include <linux/linkage.h>
12 12  
13 13 /*
  14 + * Default/weak exception vectors relocation routine
  15 + *
  16 + * This routine covers the standard ARM cases: normal (0x00000000),
  17 + * high (0xffff0000) and VBAR. SoCs which do not comply with any of
  18 + * the standard cases must provide their own, strong, version.
  19 + */
  20 +
  21 + .section .text.relocate_vectors,"ax",%progbits
  22 + .weak relocate_vectors
  23 +
  24 +ENTRY(relocate_vectors)
  25 +
  26 +#ifdef CONFIG_HAS_VBAR
  27 + /*
  28 + * If the ARM processor has the security extensions,
  29 + * use VBAR to relocate the exception vectors.
  30 + */
  31 + ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
  32 + mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
  33 +#else
  34 + /*
  35 + * Copy the relocated exception vectors to the
  36 + * correct address
  37 + * CP15 c1 V bit gives us the location of the vectors:
  38 + * 0x00000000 or 0xFFFF0000.
  39 + */
  40 + ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
  41 + mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */
  42 + ands r2, r2, #(1 << 13)
  43 + ldreq r1, =0x00000000 /* If V=0 */
  44 + ldrne r1, =0xFFFF0000 /* If V=1 */
  45 + ldmia r0!, {r2-r8,r10}
  46 + stmia r1!, {r2-r8,r10}
  47 + ldmia r0!, {r2-r8,r10}
  48 + stmia r1!, {r2-r8,r10}
  49 +#endif
  50 + bx lr
  51 +
  52 +ENDPROC(relocate_vectors)
  53 +
  54 +/*
14 55 * void relocate_code(addr_moni)
15 56 *
16 57 * This function relocates the monitor code.
... ... @@ -54,34 +95,6 @@
54 95 cmp r2, r3
55 96 blo fixloop
56 97  
57   - /*
58   - * Relocate the exception vectors
59   - */
60   -#ifdef CONFIG_HAS_VBAR
61   - /*
62   - * If the ARM processor has the security extensions,
63   - * use VBAR to relocate the exception vectors.
64   - */
65   - ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
66   - mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
67   -#else
68   - /*
69   - * Copy the relocated exception vectors to the
70   - * correct address
71   - * CP15 c1 V bit gives us the location of the vectors:
72   - * 0x00000000 or 0xFFFF0000.
73   - */
74   - ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
75   - mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */
76   - ands r2, r2, #(1 << 13)
77   - ldreq r1, =0x00000000 /* If V=0 */
78   - ldrne r1, =0xFFFF0000 /* If V=1 */
79   - ldmia r0!, {r2-r8,r10}
80   - stmia r1!, {r2-r8,r10}
81   - ldmia r0!, {r2-r8,r10}
82   - stmia r1!, {r2-r8,r10}
83   -#endif
84   -
85 98 relocate_done:
86 99  
87 100 #ifdef __XSCALE__
88 101  
... ... @@ -96,9 +109,9 @@
96 109 /* ARMv4- don't know bx lr but the assembler fails to see that */
97 110  
98 111 #ifdef __ARM_ARCH_4__
99   - mov pc, lr
  112 + mov pc, lr
100 113 #else
101   - bx lr
  114 + bx lr
102 115 #endif
103 116  
104 117 ENDPROC(relocate_code)
board/bachmann/ot1200/ot1200.c
Diff comments   View file @ dee332f
... ... @@ -173,7 +173,7 @@
173 173  
174 174 int board_mmc_init(bd_t *bis)
175 175 {
176   - s32 status = 0;
  176 + int ret;
177 177 u32 index = 0;
178 178  
179 179 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
180 180  
181 181  
... ... @@ -196,13 +196,15 @@
196 196 printf("Warning: you configured more USDHC controllers"
197 197 "(%d) then supported by the board (%d)\n",
198 198 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
199   - return status;
  199 + return -EINVAL;
200 200 }
201 201  
202   - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  202 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  203 + if (ret)
  204 + return ret;
203 205 }
204 206  
205   - return status;
  207 + return 0;
206 208 }
207 209  
208 210 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
board/boundary/nitrogen6x/nitrogen6x.c
Diff comments   View file @ dee332f
... ... @@ -302,7 +302,7 @@
302 302  
303 303 int board_mmc_init(bd_t *bis)
304 304 {
305   - s32 status = 0;
  305 + int ret;
306 306 u32 index = 0;
307 307  
308 308 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
309 309  
310 310  
... ... @@ -325,13 +325,15 @@
325 325 printf("Warning: you configured more USDHC controllers"
326 326 "(%d) then supported by the board (%d)\n",
327 327 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
328   - return status;
  328 + return -EINVAL;
329 329 }
330 330  
331   - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  331 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  332 + if (ret)
  333 + return ret;
332 334 }
333 335  
334   - return status;
  336 + return 0;
335 337 }
336 338 #endif
337 339  
board/compulab/cm_fx6/cm_fx6.c
Diff comments   View file @ dee332f
... ... @@ -98,9 +98,6 @@
98 98 /* Make sure this gpio has logical 0 value */
99 99 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
100 100 udelay(100);
101   -
102   - cm_fx6_sata_power(0);
103   - mdelay(250);
104 101 cm_fx6_sata_power(1);
105 102  
106 103 for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
... ... @@ -124,6 +121,15 @@
124 121 }
125 122  
126 123 return err;
  124 +}
  125 +
  126 +int sata_stop(void)
  127 +{
  128 + __sata_stop();
  129 + cm_fx6_sata_power(0);
  130 + mdelay(250);
  131 +
  132 + return 0;
127 133 }
128 134 #else
129 135 static int cm_fx6_setup_issd(void) { return 0; }
board/compulab/cm_fx6/imximage.cfg
View file @ dee332f
1   -/*
2   - * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -IMAGE_VERSION 2
8   -BOOT_FROM sd
board/embest/mx6boards/mx6boards.c
Diff comments   View file @ dee332f
... ... @@ -216,7 +216,7 @@
216 216  
217 217 int board_mmc_init(bd_t *bis)
218 218 {
219   - s32 status = 0;
  219 + int ret;
220 220 int i;
221 221  
222 222 /*
223 223  
224 224  
... ... @@ -268,13 +268,15 @@
268 268 printf("Warning: you configured more USDHC controllers"
269 269 "(%d) then supported by the board (%d)\n",
270 270 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
271   - return status;
  271 + return -EINVAL;
272 272 }
273 273  
274   - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  274 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  275 + if (ret)
  276 + return ret;
275 277 }
276 278  
277   - return status;
  279 + return 0;
278 280 }
279 281 #endif
280 282  
board/freescale/common/Makefile
Diff comments   View file @ dee332f
... ... @@ -53,6 +53,7 @@
53 53 obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
54 54 obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
55 55 obj-$(CONFIG_ZM7300) += zm7300.o
  56 +obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
56 57  
57 58 # deal with common files for P-series corenet based devices
58 59 obj-$(CONFIG_P2041RDB) += p_corenet/
board/freescale/common/pfuze.c
Diff comments   View file @ dee332f
  1 +/*
  2 + * Copyright 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <power/pmic.h>
  9 +#include <power/pfuze100_pmic.h>
  10 +
  11 +struct pmic *pfuze_common_init(unsigned char i2cbus)
  12 +{
  13 + struct pmic *p;
  14 + int ret;
  15 + unsigned int reg;
  16 +
  17 + ret = power_pfuze100_init(i2cbus);
  18 + if (ret)
  19 + return NULL;
  20 +
  21 + p = pmic_get("PFUZE100");
  22 + ret = pmic_probe(p);
  23 + if (ret)
  24 + return NULL;
  25 +
  26 + pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
  27 + printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
  28 +
  29 + /* Set SW1AB stanby volage to 0.975V */
  30 + pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
  31 + reg &= ~SW1x_STBY_MASK;
  32 + reg |= SW1x_0_975V;
  33 + pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
  34 +
  35 + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
  36 + pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
  37 + reg &= ~SW1xCONF_DVSSPEED_MASK;
  38 + reg |= SW1xCONF_DVSSPEED_4US;
  39 + pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
  40 +
  41 + /* Set SW1C standby voltage to 0.975V */
  42 + pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
  43 + reg &= ~SW1x_STBY_MASK;
  44 + reg |= SW1x_0_975V;
  45 + pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
  46 +
  47 + /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
  48 + pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
  49 + reg &= ~SW1xCONF_DVSSPEED_MASK;
  50 + reg |= SW1xCONF_DVSSPEED_4US;
  51 + pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
  52 +
  53 + return p;
  54 +}
board/freescale/common/pfuze.h
Diff comments   View file @ dee332f
  1 +/*
  2 + * Copyright 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __PFUZE_BOARD_HELPER__
  8 +#define __PFUZE_BOARD_HELPER__
  9 +
  10 +struct pmic *pfuze_common_init(unsigned char i2cbus);
  11 +
  12 +#endif
board/freescale/mx51evk/mx51evk.c
Diff comments   View file @ dee332f
... ... @@ -320,7 +320,7 @@
320 320 };
321 321  
322 322 u32 index;
323   - s32 status = 0;
  323 + int ret;
324 324  
325 325 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
326 326 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
327 327  
328 328  
... ... @@ -340,11 +340,13 @@
340 340 printf("Warning: you configured more ESDHC controller"
341 341 "(%d) as supported by the board(2)\n",
342 342 CONFIG_SYS_FSL_ESDHC_NUM);
343   - return status;
  343 + return -EINVAL;
344 344 }
345   - status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
  345 + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
  346 + if (ret)
  347 + return ret;
346 348 }
347   - return status;
  349 + return 0;
348 350 }
349 351 #endif
350 352  
board/freescale/mx53ard/mx53ard.c
Diff comments   View file @ dee332f
... ... @@ -166,7 +166,7 @@
166 166 };
167 167  
168 168 u32 index;
169   - s32 status = 0;
  169 + int ret;
170 170  
171 171 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
172 172 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
173 173  
174 174  
... ... @@ -185,12 +185,14 @@
185 185 printf("Warning: you configured more ESDHC controller"
186 186 "(%d) as supported by the board(2)\n",
187 187 CONFIG_SYS_FSL_ESDHC_NUM);
188   - return status;
  188 + return -EINVAL;
189 189 }
190   - status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
  190 + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
  191 + if (ret)
  192 + return ret;
191 193 }
192 194  
193   - return status;
  195 + return 0;
194 196 }
195 197 #endif
196 198  
board/freescale/mx53evk/mx53evk.c
Diff comments   View file @ dee332f
... ... @@ -195,7 +195,7 @@
195 195 };
196 196  
197 197 u32 index;
198   - s32 status = 0;
  198 + int ret;
199 199  
200 200 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
201 201 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
202 202  
203 203  
... ... @@ -214,12 +214,14 @@
214 214 printf("Warning: you configured more ESDHC controller"
215 215 "(%d) as supported by the board(2)\n",
216 216 CONFIG_SYS_FSL_ESDHC_NUM);
217   - return status;
  217 + return -EINVAL;
218 218 }
219   - status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
  219 + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
  220 + if (ret)
  221 + return ret;
220 222 }
221 223  
222   - return status;
  224 + return 0;
223 225 }
224 226 #endif
225 227  
board/freescale/mx53loco/mx53loco.c
Diff comments   View file @ dee332f
... ... @@ -186,7 +186,7 @@
186 186 };
187 187  
188 188 u32 index;
189   - s32 status = 0;
  189 + int ret;
190 190  
191 191 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
192 192 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
193 193  
194 194  
... ... @@ -205,12 +205,14 @@
205 205 printf("Warning: you configured more ESDHC controller"
206 206 "(%d) as supported by the board(2)\n",
207 207 CONFIG_SYS_FSL_ESDHC_NUM);
208   - return status;
  208 + return -EINVAL;
209 209 }
210   - status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
  210 + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
  211 + if (ret)
  212 + return ret;
211 213 }
212 214  
213   - return status;
  215 + return 0;
214 216 }
215 217 #endif
216 218  
board/freescale/mx53smd/mx53smd.c
Diff comments   View file @ dee332f
... ... @@ -106,7 +106,7 @@
106 106 };
107 107  
108 108 u32 index;
109   - s32 status = 0;
  109 + int ret;
110 110  
111 111 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
112 112  
113 113  
114 114  
... ... @@ -121,12 +121,14 @@
121 121 printf("Warning: you configured more ESDHC controller"
122 122 "(%d) as supported by the board(1)\n",
123 123 CONFIG_SYS_FSL_ESDHC_NUM);
124   - return status;
  124 + return -EINVAL;
125 125 }
126   - status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
  126 + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
  127 + if (ret)
  128 + return ret;
127 129 }
128 130  
129   - return status;
  131 + return 0;
130 132 }
131 133 #endif
132 134  
board/freescale/mx6qarm2/mx6qarm2.c
Diff comments   View file @ dee332f
... ... @@ -125,7 +125,7 @@
125 125  
126 126 int board_mmc_init(bd_t *bis)
127 127 {
128   - s32 status = 0;
  128 + int ret;
129 129 u32 index = 0;
130 130  
131 131 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
132 132  
133 133  
... ... @@ -145,13 +145,15 @@
145 145 printf("Warning: you configured more USDHC controllers"
146 146 "(%d) then supported by the board (%d)\n",
147 147 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
148   - return status;
  148 + return -EINVAL;
149 149 }
150 150  
151   - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  151 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  152 + if (ret)
  153 + return ret;
152 154 }
153 155  
154   - return status;
  156 + return 0;
155 157 }
156 158 #endif
157 159  
board/freescale/mx6qsabreauto/mx6qsabreauto.c
Diff comments   View file @ dee332f
... ... @@ -28,6 +28,8 @@
28 28 #include <asm/imx-common/video.h>
29 29 #include <asm/arch/crm_regs.h>
30 30 #include <pca953x.h>
  31 +#include <power/pmic.h>
  32 +#include "../common/pfuze.h"
31 33  
32 34 DECLARE_GLOBAL_DATA_PTR;
33 35  
... ... @@ -53,6 +55,12 @@
53 55  
54 56 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
55 57  
  58 +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  59 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  60 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  61 +
  62 +#define I2C_PMIC 1
  63 +
56 64 int dram_init(void)
57 65 {
58 66 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
... ... @@ -97,6 +105,7 @@
97 105 }
98 106 };
99 107  
  108 +#ifndef CONFIG_SYS_FLASH_CFI
100 109 /*
101 110 * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
102 111 * Compass Sensor, Accelerometer, Res Touch
... ... @@ -113,6 +122,7 @@
113 122 .gp = IMX_GPIO_NR(3, 18)
114 123 }
115 124 };
  125 +#endif
116 126  
117 127 static iomux_v3_cfg_t const i2c3_pads[] = {
118 128 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
... ... @@ -160,6 +170,75 @@
160 170 return 0;
161 171 }
162 172  
  173 +static iomux_v3_cfg_t const eimnor_pads[] = {
  174 + MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  175 + MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  176 + MX6_PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  177 + MX6_PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  178 + MX6_PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  179 + MX6_PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  180 + MX6_PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  181 + MX6_PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  182 + MX6_PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  183 + MX6_PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  184 + MX6_PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  185 + MX6_PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  186 + MX6_PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  187 + MX6_PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  188 + MX6_PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  189 + MX6_PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  190 + MX6_PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  191 + MX6_PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  192 + MX6_PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  193 + MX6_PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  194 + MX6_PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  195 + MX6_PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  196 + MX6_PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  197 + MX6_PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  198 + MX6_PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  199 + MX6_PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  200 + MX6_PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  201 + MX6_PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
  202 + MX6_PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  203 + MX6_PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  204 + MX6_PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  205 + MX6_PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  206 + MX6_PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  207 + MX6_PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  208 + MX6_PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  209 + MX6_PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  210 + MX6_PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  211 + MX6_PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  212 + MX6_PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  213 + MX6_PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  214 + MX6_PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  215 + MX6_PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL),
  216 + MX6_PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  217 +};
  218 +
  219 +static void eimnor_cs_setup(void)
  220 +{
  221 + struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
  222 +
  223 + writel(0x00020181, &weim_regs->cs0gcr1);
  224 + writel(0x00000001, &weim_regs->cs0gcr2);
  225 + writel(0x0a020000, &weim_regs->cs0rcr1);
  226 + writel(0x0000c000, &weim_regs->cs0rcr2);
  227 + writel(0x0804a240, &weim_regs->cs0wcr1);
  228 + writel(0x00000120, &weim_regs->wcr);
  229 +
  230 + set_chipselect_size(CS0_128);
  231 +}
  232 +
  233 +static void setup_iomux_eimnor(void)
  234 +{
  235 + imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
  236 +
  237 + gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
  238 +
  239 + eimnor_cs_setup();
  240 +}
  241 +
163 242 static void setup_iomux_enet(void)
164 243 {
165 244 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
... ... @@ -402,6 +481,7 @@
402 481 #ifdef CONFIG_NAND_MXS
403 482 setup_gpmi_nand();
404 483 #endif
  484 +
405 485 return 0;
406 486 }
407 487  
408 488  
409 489  
... ... @@ -415,11 +495,13 @@
415 495 /* I2C 3 Steer */
416 496 gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
417 497 imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
  498 +#ifndef CONFIG_SYS_FLASH_CFI
418 499 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
419   -
  500 +#endif
420 501 gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
421 502 imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
422 503  
  504 + setup_iomux_eimnor();
423 505 return 0;
424 506 }
425 507  
... ... @@ -429,6 +511,17 @@
429 511 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
430 512 }
431 513 #endif
  514 +
  515 +int power_init_board(void)
  516 +{
  517 + struct pmic *p;
  518 +
  519 + p = pfuze_common_init(I2C_PMIC);
  520 + if (!p)
  521 + return -ENODEV;
  522 +
  523 + return 0;
  524 +}
432 525  
433 526 #ifdef CONFIG_CMD_BMODE
434 527 static const struct boot_mode board_boot_modes[] = {
board/freescale/mx6sabresd/MAINTAINERS
Diff comments   View file @ dee332f
... ... @@ -5,4 +5,5 @@
5 5 F: include/configs/mx6sabresd.h
6 6 F: configs/mx6dlsabresd_defconfig
7 7 F: configs/mx6qsabresd_defconfig
  8 +F: configs/mx6sabresd_spl_defconfig
board/freescale/mx6sabresd/mx6sabresd.c
Diff comments   View file @ dee332f
... ... @@ -27,12 +27,11 @@
27 27 #include <i2c.h>
28 28 #include <power/pmic.h>
29 29 #include <power/pfuze100_pmic.h>
  30 +#include "../common/pfuze.h"
30 31 #include <asm/arch/mx6-ddr.h>
31 32  
32 33 DECLARE_GLOBAL_DATA_PTR;
33 34  
34   -#define BOOT_CFG 0x020D8004
35   -
36 35 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
37 36 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
38 37 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
... ... @@ -300,7 +299,8 @@
300 299  
301 300 return 0;
302 301 #else
303   - unsigned reg = readl(BOOT_CFG) >> 11;
  302 + struct src *psrc = (struct src *)SRC_BASE_ADDR;
  303 + unsigned reg = readl(&psrc->sbmr1) >> 11;
304 304 /*
305 305 * Upon reading BOOT_CFG register the following map is done:
306 306 * Bit 11 and 12 of BOOT_CFG register can determine the current
307 307  
308 308  
309 309  
310 310  
311 311  
312 312  
... ... @@ -560,60 +560,27 @@
560 560 return 0;
561 561 }
562 562  
563   -static int pfuze_init(void)
  563 +int power_init_board(void)
564 564 {
565 565 struct pmic *p;
566   - int ret;
567 566 unsigned int reg;
568 567  
569   - ret = power_pfuze100_init(I2C_PMIC);
570   - if (ret)
571   - return ret;
  568 + p = pfuze_common_init(I2C_PMIC);
  569 + if (!p)
  570 + return -ENODEV;
572 571  
573   - p = pmic_get("PFUZE100");
574   - ret = pmic_probe(p);
575   - if (ret)
576   - return ret;
577   -
578   - pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
579   - printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
580   -
581 572 /* Increase VGEN3 from 2.5 to 2.8V */
582 573 pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
583   - reg &= ~0xf;
584   - reg |= 0xa;
  574 + reg &= ~LDO_VOL_MASK;
  575 + reg |= LDOB_2_80V;
585 576 pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
586 577  
587 578 /* Increase VGEN5 from 2.8 to 3V */
588 579 pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
589   - reg &= ~0xf;
590   - reg |= 0xc;
  580 + reg &= ~LDO_VOL_MASK;
  581 + reg |= LDOB_3_00V;
591 582 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
592 583  
593   - /* Set SW1AB stanby volage to 0.975V */
594   - pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
595   - reg &= ~0x3f;
596   - reg |= 0x1b;
597   - pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
598   -
599   - /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
600   - pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
601   - reg &= ~0xc0;
602   - reg |= 0x40;
603   - pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
604   -
605   - /* Set SW1C standby voltage to 0.975V */
606   - pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
607   - reg &= ~0x3f;
608   - reg |= 0x1b;
609   - pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
610   -
611   - /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
612   - pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
613   - reg &= ~0xc0;
614   - reg |= 0x40;
615   - pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
616   -
617 584 return 0;
618 585 }
619 586  
... ... @@ -640,8 +607,6 @@
640 607 #ifdef CONFIG_CMD_BMODE
641 608 add_board_boot_modes(board_boot_modes);
642 609 #endif
643   - pfuze_init();
644   -
645 610 return 0;
646 611 }
647 612  
648 613  
... ... @@ -729,11 +694,33 @@
729 694 .trasmin = 3500,
730 695 };
731 696  
  697 +static void ccgr_init(void)
  698 +{
  699 + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  700 +
  701 + writel(0x00C03F3F, &ccm->CCGR0);
  702 + writel(0x0030FC03, &ccm->CCGR1);
  703 + writel(0x0FFFC000, &ccm->CCGR2);
  704 + writel(0x3FF00000, &ccm->CCGR3);
  705 + writel(0x00FFF300, &ccm->CCGR4);
  706 + writel(0x0F0000C3, &ccm->CCGR5);
  707 + writel(0x000003FF, &ccm->CCGR6);
  708 +}
  709 +
  710 +static void gpr_init(void)
  711 +{
  712 + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  713 +
  714 + /* enable AXI cache for VDOA/VPU/IPU */
  715 + writel(0xF00000CF, &iomux->gpr[4]);
  716 + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  717 + writel(0x007F007F, &iomux->gpr[6]);
  718 + writel(0x007F007F, &iomux->gpr[7]);
  719 +}
  720 +
732 721 /*
733   - * This section require the differentiation
734   - * between iMX6 Sabre Families.
735   - * But for now, it will configure only for
736   - * SabreSD.
  722 + * This section requires the differentiation between iMX6 Sabre boards, but
  723 + * for now, it will configure only for the mx6q variant.
737 724 */
738 725 static void spl_dram_init(void)
739 726 {
... ... @@ -767,6 +754,9 @@
767 754 {
768 755 /* setup AIPS and disable watchdog */
769 756 arch_cpu_init();
  757 +
  758 + ccgr_init();
  759 + gpr_init();
770 760  
771 761 /* iomux and setup of i2c */
772 762 board_early_init_f();
board/freescale/mx6sabresd/mx6sabresd_spl.cfg
View file @ dee332f
1   -/*
2   - * Copyright (C) 2011 Freescale Semiconductor, Inc.
3   - * Jason Liu <r64343@freescale.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - *
7   - * Refer doc/README.imximage for more details about how-to configure
8   - * and create imximage boot image
9   - *
10   - * The syntax is taken as close as possible with the kwbimage
11   - */
12   -
13   -/* image version */
14   -IMAGE_VERSION 2
15   -
16   -/*
17   - * Boot Device : one of
18   - * spi, sd (the board has no nand neither onenand)
19   - */
20   -BOOT_FROM sd
21   -
22   -/*
23   - * Device Configuration Data (DCD)
24   - *
25   - * Each entry must have the format:
26   - * Addr-type Address Value
27   - *
28   - * where:
29   - * Addr-type register length (1,2 or 4 bytes)
30   - * Address absolute address of the register
31   - * value value to be stored in the register
32   - */
33   -
34   -/* set the default clock gate to save power */
35   -DATA 4 0x020c4068 0x00C03F3F
36   -DATA 4 0x020c406c 0x0030FC03
37   -DATA 4 0x020c4070 0x0FFFC000
38   -DATA 4 0x020c4074 0x3FF00000
39   -DATA 4 0x020c4078 0x00FFF300
40   -DATA 4 0x020c407c 0x0F0000C3
41   -DATA 4 0x020c4080 0x000003FF
42   -
43   -/* enable AXI cache for VDOA/VPU/IPU */
44   -DATA 4 0x020e0010 0xF00000CF
45   -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
46   -DATA 4 0x020e0018 0x007F007F
47   -DATA 4 0x020e001c 0x007F007F
48   -
49   -/*
50   - * Setup CCM_CCOSR register as follows:
51   - *
52   - * cko1_en = 1 --> CKO1 enabled
53   - * cko1_div = 111 --> divide by 8
54   - * cko1_sel = 1011 --> ahb_clk_root
55   - *
56   - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
57   - */
58   -DATA 4 0x020c4060 0x000000fb
board/freescale/mx6slevk/mx6slevk.c
Diff comments   View file @ dee332f
... ... @@ -230,16 +230,11 @@
230 230 static int setup_fec(void)
231 231 {
232 232 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
233   - int ret;
234 233  
235 234 /* clear gpr1[14], gpr1[18:17] to select anatop clock */
236 235 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
237 236  
238   - ret = enable_fec_anatop_clock(ENET_50MHz);
239   - if (ret)
240   - return ret;
241   -
242   - return 0;
  237 + return enable_fec_anatop_clock(ENET_50MHz);
243 238 }
244 239 #endif
245 240  
board/freescale/mx6sxsabresd/mx6sxsabresd.c
Diff comments   View file @ dee332f
... ... @@ -25,6 +25,7 @@
25 25 #include <netdev.h>
26 26 #include <power/pmic.h>
27 27 #include <power/pfuze100_pmic.h>
  28 +#include "../common/pfuze.h"
28 29  
29 30 DECLARE_GLOBAL_DATA_PTR;
30 31  
... ... @@ -68,6 +69,34 @@
68 69 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
69 70 };
70 71  
  72 +static iomux_v3_cfg_t const usdhc2_pads[] = {
  73 + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74 + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75 + MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76 + MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77 + MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  78 + MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79 +};
  80 +
  81 +static iomux_v3_cfg_t const usdhc3_pads[] = {
  82 + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  83 + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84 + MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85 + MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86 + MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87 + MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88 + MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  89 + MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  90 + MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91 + MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  92 +
  93 + /* CD pin */
  94 + MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  95 +
  96 + /* RST_B, used for power reset cycle */
  97 + MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  98 +};
  99 +
71 100 static iomux_v3_cfg_t const usdhc4_pads[] = {
72 101 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
73 102 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
... ... @@ -119,7 +148,6 @@
119 148 {
120 149 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
121 150 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
122   - int ret;
123 151 int reg;
124 152  
125 153 /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
... ... @@ -140,11 +168,7 @@
140 168 reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
141 169 writel(reg, &anatop->pll_enet);
142 170  
143   - ret = enable_fec_anatop_clock(ENET_125MHz);
144   - if (ret)
145   - return ret;
146   -
147   - return 0;
  171 + return enable_fec_anatop_clock(ENET_125MHz);
148 172 }
149 173  
150 174 int board_eth_init(bd_t *bis)
151 175  
152 176  
153 177  
154 178  
... ... @@ -170,52 +194,19 @@
170 194 },
171 195 };
172 196  
173   -static int pfuze_init(void)
  197 +int power_init_board(void)
174 198 {
175 199 struct pmic *p;
176   - int ret;
177 200 unsigned int reg;
178 201  
179   - ret = power_pfuze100_init(I2C_PMIC);
180   - if (ret)
181   - return ret;
  202 + p = pfuze_common_init(I2C_PMIC);
  203 + if (!p)
  204 + return -ENODEV;
182 205  
183   - p = pmic_get("PFUZE100");
184   - ret = pmic_probe(p);
185   - if (ret)
186   - return ret;
187   -
188   - pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
189   - printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
190   -
191   - /* Set SW1AB standby voltage to 0.975V */
192   - pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
193   - reg &= ~0x3f;
194   - reg |= 0x1b;
195   - pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
196   -
197   - /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
198   - pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
199   - reg &= ~0xc0;
200   - reg |= 0x40;
201   - pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
202   -
203   - /* Set SW1C standby voltage to 0.975V */
204   - pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
205   - reg &= ~0x3f;
206   - reg |= 0x1b;
207   - pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
208   -
209   - /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
210   - pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
211   - reg &= ~0xc0;
212   - reg |= 0x40;
213   - pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
214   -
215 206 /* Enable power of VGEN5 3V3, needed for SD3 */
216 207 pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
217   - reg &= ~0x1F;
218   - reg |= 0x1F;
  208 + reg &= ~LDO_VOL_MASK;
  209 + reg |= (LDOB_3_30V | (1 << LDO_EN));
219 210 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
220 211  
221 212 return 0;
... ... @@ -243,7 +234,6 @@
243 234 int board_early_init_f(void)
244 235 {
245 236 setup_iomux_uart();
246   - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
247 237  
248 238 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
249 239 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
250 240  
251 241  
252 242  
253 243  
254 244  
255 245  
256 246  
... ... @@ -255,35 +245,98 @@
255 245 return 0;
256 246 }
257 247  
258   -static struct fsl_esdhc_cfg usdhc_cfg[1] = {
  248 +static struct fsl_esdhc_cfg usdhc_cfg[3] = {
  249 + {USDHC2_BASE_ADDR, 0, 4},
  250 + {USDHC3_BASE_ADDR},
259 251 {USDHC4_BASE_ADDR},
260 252 };
261 253  
  254 +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
  255 +#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
  256 +#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
  257 +
262 258 int board_mmc_getcd(struct mmc *mmc)
263 259 {
264   - return 1; /* Assume boot SD always present */
  260 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  261 + int ret = 0;
  262 +
  263 + switch (cfg->esdhc_base) {
  264 + case USDHC2_BASE_ADDR:
  265 + ret = 1; /* Assume uSDHC2 is always present */
  266 + break;
  267 + case USDHC3_BASE_ADDR:
  268 + ret = !gpio_get_value(USDHC3_CD_GPIO);
  269 + break;
  270 + case USDHC4_BASE_ADDR:
  271 + ret = !gpio_get_value(USDHC4_CD_GPIO);
  272 + break;
  273 + }
  274 +
  275 + return ret;
265 276 }
266 277  
267 278 int board_mmc_init(bd_t *bis)
268 279 {
269   - imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  280 + int i, ret;
270 281  
271   - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
272   - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  282 + /*
  283 + * According to the board_mmc_init() the following map is done:
  284 + * (U-boot device node) (Physical Port)
  285 + * mmc0 USDHC2
  286 + * mmc1 USDHC3
  287 + * mmc2 USDHC4
  288 + */
  289 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  290 + switch (i) {
  291 + case 0:
  292 + imx_iomux_v3_setup_multiple_pads(
  293 + usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  294 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  295 + break;
  296 + case 1:
  297 + imx_iomux_v3_setup_multiple_pads(
  298 + usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  299 + gpio_direction_input(USDHC3_CD_GPIO);
  300 + gpio_direction_output(USDHC3_PWR_GPIO, 1);
  301 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  302 + break;
  303 + case 2:
  304 + imx_iomux_v3_setup_multiple_pads(
  305 + usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  306 + gpio_direction_input(USDHC4_CD_GPIO);
  307 + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  308 + break;
  309 + default:
  310 + printf("Warning: you configured more USDHC controllers"
  311 + "(%d) than supported by the board\n", i + 1);
  312 + return -EINVAL;
  313 + }
  314 +
  315 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  316 + if (ret) {
  317 + printf("Warning: failed to initialize mmc dev %d\n", i);
  318 + return ret;
  319 + }
  320 + }
  321 +
  322 + return 0;
273 323 }
274 324  
  325 +
275 326 int board_init(void)
276 327 {
277 328 /* Address of boot parameters */
278 329 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
279 330  
  331 +#ifdef CONFIG_SYS_I2C_MXC
  332 + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  333 +#endif
  334 +
280 335 return 0;
281 336 }
282 337  
283 338 int board_late_init(void)
284 339 {
285   - pfuze_init();
286   -
287 340 return 0;
288 341 }
289 342  
board/gateworks/gw_ventana/clocks.cfg
View file @ dee332f
1   -/*
2   - * Copyright (C) 2013 Boundary Devices
3   - * Copyright (C) 2013 Gateworks Corporation
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - *
7   - * Device Configuration Data (DCD)
8   - *
9   - * Each entry must have the format:
10   - * Addr-type Address Value
11   - *
12   - * where:
13   - * Addr-type register length (1,2 or 4 bytes)
14   - * Address absolute address of the register
15   - * value value to be stored in the register
16   - */
17   -
18   -/* set the default clock gate to save power */
19   -DATA 4, CCM_CCGR0, 0x00C03F3F
20   -DATA 4, CCM_CCGR1, 0x0030FC03
21   -DATA 4, CCM_CCGR2, 0x0FFFC000
22   -DATA 4, CCM_CCGR3, 0x3FF00000
23   -DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
24   -DATA 4, CCM_CCGR5, 0x0F0000C3
25   -DATA 4, CCM_CCGR6, 0x000003FF
26   -
27   -/* enable AXI cache for VDOA/VPU/IPU */
28   -DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
29   -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
30   -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
31   -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
32   -
33   -/*
34   - * Setup CCM_CCOSR register as follows:
35   - *
36   - * cko1_en = 1 --> CKO1 enabled
37   - * cko1_div = 111 --> divide by 8
38   - * cko1_sel = 1011 --> ahb_clk_root
39   - *
40   - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
41   - */
42   -DATA 4, CCM_CCOSR, 0x000000fb
board/gateworks/gw_ventana/gw_ventana.cfg
View file @ dee332f
1   -/*
2   - * Copyright (C) 2013 Gateworks Corporation
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - *
6   - * Refer doc/README.imximage for more details about how-to configure
7   - * and create imximage boot image
8   - *
9   - * The syntax is taken as close as possible with the kwbimage
10   - */
11   -
12   -/* image version */
13   -IMAGE_VERSION 2
14   -
15   -/*
16   - * Boot Device : one of
17   - * spi, sd, nand, sata
18   - */
19   -#ifdef CONFIG_SPI_FLASH
20   -BOOT_FROM spi
21   -#else
22   -BOOT_FROM nand
23   -#endif
24   -
25   -#define __ASSEMBLY__
26   -#include <config.h>
27   -#include "asm/arch/iomux.h"
28   -#include "asm/arch/crm_regs.h"
29   -#include "clocks.cfg"
board/gateworks/gw_ventana/gw_ventana_spl.c
Diff comments   View file @ dee332f
... ... @@ -8,6 +8,7 @@
8 8 #include <common.h>
9 9 #include <i2c.h>
10 10 #include <asm/io.h>
  11 +#include <asm/arch/crm_regs.h>
11 12 #include <asm/arch/iomux.h>
12 13 #include <asm/arch/mx6-ddr.h>
13 14 #include <asm/arch/mx6-pins.h>
... ... @@ -392,6 +393,30 @@
392 393 mx6_dram_cfg(&sysinfo, calib, mem);
393 394 }
394 395  
  396 +static void ccgr_init(void)
  397 +{
  398 + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  399 +
  400 + writel(0x00C03F3F, &ccm->CCGR0);
  401 + writel(0x0030FC03, &ccm->CCGR1);
  402 + writel(0x0FFFC000, &ccm->CCGR2);
  403 + writel(0x3FF00000, &ccm->CCGR3);
  404 + writel(0x00FFF300, &ccm->CCGR4);
  405 + writel(0x0F0000C3, &ccm->CCGR5);
  406 + writel(0x000003FF, &ccm->CCGR6);
  407 +}
  408 +
  409 +static void gpr_init(void)
  410 +{
  411 + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  412 +
  413 + /* enable AXI cache for VDOA/VPU/IPU */
  414 + writel(0xF00000CF, &iomux->gpr[4]);
  415 + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  416 + writel(0x007F007F, &iomux->gpr[6]);
  417 + writel(0x007F007F, &iomux->gpr[7]);
  418 +}
  419 +
395 420 /*
396 421 * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
397 422 * - we have a stack and a place to store GD, both in SRAM
... ... @@ -404,6 +429,9 @@
404 429  
405 430 /* setup AIPS and disable watchdog */
406 431 arch_cpu_init();
  432 +
  433 + ccgr_init();
  434 + gpr_init();
407 435  
408 436 /* iomux and setup of i2c */
409 437 board_early_init_f();
board/kosagi/novena/novena_spl.c
Diff comments   View file @ dee332f
... ... @@ -17,6 +17,7 @@
17 17 #include <asm/imx-common/boot_mode.h>
18 18 #include <asm/imx-common/iomux-v3.h>
19 19 #include <asm/imx-common/mxc_i2c.h>
  20 +#include <asm/arch/crm_regs.h>
20 21 #include <i2c.h>
21 22 #include <mmc.h>
22 23 #include <fsl_esdhc.h>
... ... @@ -533,6 +534,30 @@
533 534 .trasmin = 3590,
534 535 };
535 536  
  537 +static void ccgr_init(void)
  538 +{
  539 + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  540 +
  541 + writel(0x00C03F3F, &ccm->CCGR0);
  542 + writel(0x0030FC03, &ccm->CCGR1);
  543 + writel(0x0FFFC000, &ccm->CCGR2);
  544 + writel(0x3FF00000, &ccm->CCGR3);
  545 + writel(0xFFFFF300, &ccm->CCGR4);
  546 + writel(0x0F0000C3, &ccm->CCGR5);
  547 + writel(0x000003FF, &ccm->CCGR6);
  548 +}
  549 +
  550 +static void gpr_init(void)
  551 +{
  552 + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  553 +
  554 + /* enable AXI cache for VDOA/VPU/IPU */
  555 + writel(0xF00000CF, &iomux->gpr[4]);
  556 + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  557 + writel(0x007F007F, &iomux->gpr[6]);
  558 + writel(0x007F007F, &iomux->gpr[7]);
  559 +}
  560 +
536 561 /*
537 562 * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
538 563 * - we have a stack and a place to store GD, both in SRAM
... ... @@ -542,6 +567,9 @@
542 567 {
543 568 /* setup AIPS and disable watchdog */
544 569 arch_cpu_init();
  570 +
  571 + ccgr_init();
  572 + gpr_init();
545 573  
546 574 /* setup GP timer */
547 575 timer_init();
board/kosagi/novena/setup.cfg
View file @ dee332f
1   -/*
2   - * Copyright (C) 2014 Marek Vasut <marex@denx.de>
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - *
6   - * Refer docs/README.imxmage for more details about how-to configure
7   - * and create imximage boot image
8   - *
9   - * The syntax is taken as close as possible with the kwbimage
10   - */
11   -
12   -/* image version */
13   -IMAGE_VERSION 2
14   -
15   -/* Boot Device : sd */
16   -BOOT_FROM sd
17   -
18   -#define __ASSEMBLY__
19   -#include <config.h>
20   -#include "asm/arch/iomux.h"
21   -#include "asm/arch/crm_regs.h"
22   -
23   -/* set the default clock gate to save power */
24   -DATA 4, CCM_CCGR0, 0x00C03F3F
25   -DATA 4, CCM_CCGR1, 0x0030FC03
26   -DATA 4, CCM_CCGR2, 0x0FFFC000
27   -DATA 4, CCM_CCGR3, 0x3FF00000
28   -DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
29   -DATA 4, CCM_CCGR5, 0x0F0000C3
30   -DATA 4, CCM_CCGR6, 0x000003FF
31   -
32   -/* enable AXI cache for VDOA/VPU/IPU */
33   -DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
34   -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
35   -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
36   -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
37   -
38   -/*
39   - * Setup CCM_CCOSR register as follows:
40   - *
41   - * cko1_en = 1 --> CKO1 enabled
42   - * cko1_div = 111 --> divide by 8
43   - * cko1_sel = 1011 --> ahb_clk_root
44   - *
45   - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
46   - */
47   -DATA 4, CCM_CCOSR, 0x000000fb
board/tbs/tbs2910/tbs2910.c
Diff comments   View file @ dee332f
... ... @@ -219,15 +219,13 @@
219 219  
220 220 int board_mmc_init(bd_t *bis)
221 221 {
222   - s32 status = 0;
223   - int i;
224   -
225 222 /*
226 223 * (U-boot device node) (Physical Port)
227 224 * mmc0 SD2
228 225 * mmc1 SD3
229 226 * mmc2 eMMC
230 227 */
  228 + int i, ret;
231 229 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
232 230 switch (i) {
233 231 case 0:
234 232  
235 233  
... ... @@ -251,12 +249,13 @@
251 249 printf("Warning: you configured more USDHC controllers"
252 250 "(%d) then supported by the board (%d)\n",
253 251 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
254   - return status;
  252 + return -EINVAL;
255 253 }
256   -
257   - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  254 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  255 + if (ret)
  256 + return ret;
258 257 }
259   - return status;
  258 + return 0;
260 259 }
261 260 #endif /* CONFIG_FSL_ESDHC */
262 261  
board/tqc/tqma6/tqma6.c
Diff comments   View file @ dee332f
... ... @@ -17,6 +17,7 @@
17 17 #include <asm/gpio.h>
18 18 #include <asm/io.h>
19 19 #include <asm/imx-common/mxc_i2c.h>
  20 +#include <asm/imx-common/spi.h>
20 21 #include <common.h>
21 22 #include <fsl_esdhc.h>
22 23 #include <libfdt.h>
... ... @@ -50,7 +51,7 @@
50 51  
51 52 int dram_init(void)
52 53 {
53   - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  54 + gd->ram_size = imx_ddr_size();
54 55  
55 56 return 0;
56 57 }
... ... @@ -180,8 +181,14 @@
180 181  
181 182 static void tqma6_setup_i2c(void)
182 183 {
183   - /* use logical index for bus, e.g. I2C1 -> 0 */
184   - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
  184 + int ret;
  185 + /*
  186 + * use logical index for bus, e.g. I2C1 -> 0
  187 + * warn on error
  188 + */
  189 + ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
  190 + if (ret)
  191 + printf("setup I2C3 failed: %d\n", ret);
185 192 }
186 193  
187 194 int board_early_init_f(void)
board/tqc/tqma6/tqma6_mba6.c
Diff comments   View file @ dee332f
... ... @@ -224,8 +224,14 @@
224 224  
225 225 static void mba6_setup_i2c(void)
226 226 {
227   - /* use logical index for bus, e.g. I2C1 -> 0 */
228   - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads);
  227 + int ret;
  228 + /*
  229 + * use logical index for bus, e.g. I2C1 -> 0
  230 + * warn on error
  231 + */
  232 + ret = setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads);
  233 + if (ret)
  234 + printf("setup I2C1 failed: %d\n", ret);
229 235 }
230 236  
231 237  
board/wandboard/wandboard.c
Diff comments   View file @ dee332f
... ... @@ -144,7 +144,7 @@
144 144  
145 145 int board_mmc_init(bd_t *bis)
146 146 {
147   - s32 status = 0;
  147 + int ret;
148 148 u32 index = 0;
149 149  
150 150 /*
151 151  
152 152  
... ... @@ -173,13 +173,15 @@
173 173 printf("Warning: you configured more USDHC controllers"
174 174 "(%d) then supported by the board (%d)\n",
175 175 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
176   - return status;
  176 + return -EINVAL;
177 177 }
178 178  
179   - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  179 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  180 + if (ret)
  181 + return ret;
180 182 }
181 183  
182   - return status;
  184 + return 0;
183 185 }
184 186  
185 187 static int mx6_rgmii_rework(struct phy_device *phydev)
... ... @@ -48,6 +48,20 @@
48 48 }
49 49 int sata_initialize(void) __attribute__((weak,alias("__sata_initialize")));
50 50  
  51 +__weak int __sata_stop(void)
  52 +{
  53 + int i, err = 0;
  54 +
  55 + for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++)
  56 + err |= reset_sata(i);
  57 +
  58 + if (err)
  59 + printf("Could not reset some SATA devices\n");
  60 +
  61 + return err;
  62 +}
  63 +int sata_stop(void) __attribute__((weak, alias("__sata_stop")));
  64 +
51 65 #ifdef CONFIG_PARTITIONS
52 66 block_dev_desc_t *sata_get_dev(int dev)
53 67 {
54 68  
... ... @@ -59,8 +73,15 @@
59 73 {
60 74 int rc = 0;
61 75  
62   - if (argc == 2 && strcmp(argv[1], "init") == 0)
  76 + if (argc == 2 && strcmp(argv[1], "stop") == 0)
  77 + return sata_stop();
  78 +
  79 + if (argc == 2 && strcmp(argv[1], "init") == 0) {
  80 + if (sata_curr_device != -1)
  81 + sata_stop();
  82 +
63 83 return sata_initialize();
  84 + }
64 85  
65 86 /* If the user has not yet run `sata init`, do it now */
66 87 if (sata_curr_device == -1)
... ... @@ -185,6 +206,7 @@
185 206 sata, 5, 1, do_sata,
186 207 "SATA sub system",
187 208 "init - init SATA sub system\n"
  209 + "sata stop - disable SATA sub system\n"
188 210 "sata info - show available SATA devices\n"
189 211 "sata device [dev] - show or set current device\n"
190 212 "sata part [dev] - print partition table\n"
configs/cm_fx6_defconfig
Diff comments   View file @ dee332f
1 1 CONFIG_SPL=y
2   -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/compulab/cm_fx6/imximage.cfg,MX6QDL,SPL"
  2 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL"
3 3 +S:CONFIG_ARM=y
4 4 +S:CONFIG_TARGET_CM_FX6=y
configs/gwventana_defconfig
Diff comments   View file @ dee332f
1 1 CONFIG_SPL=y
2   -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6QDL"
  2 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
3 3 +S:CONFIG_ARM=y
4 4 +S:CONFIG_TARGET_GW_VENTANA=y
configs/mx6sabresd_spl_defconfig
Diff comments   View file @ dee332f
1 1 CONFIG_SPL=y
2   -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6sabresd_spl.cfg,SPL,MX6Q"
  2 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q"
3 3 +S:CONFIG_ARM=y
4 4 +S:CONFIG_TARGET_MX6SABRESD=y
configs/novena_defconfig
Diff comments   View file @ dee332f
1 1 CONFIG_SPL=y
2   -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/kosagi/novena/setup.cfg,MX6Q"
  2 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
3 3 +S:CONFIG_ARM=y
4 4 +S:CONFIG_TARGET_KOSAGI_NOVENA=y
... ... @@ -27,7 +27,7 @@
27 27 - Each line of the configuration file contains exactly one instruction.
28 28 - Every numeric value must be encoded in hexadecimal and in format 0xabcdef12 .
29 29 - The configuration file is a concatenation of blocks called "sections" and
30   - optionally "DCD blocks" (see below).
  30 + optionally "DCD blocks" (see below), and optional flags lines.
31 31 - Each "section" is started by the "SECTION" instruction.
32 32 - The "SECTION" instruction has the following semantics:
33 33  
... ... @@ -139,9 +139,14 @@
139 139 NOOP
140 140 - This instruction does nothing.
141 141  
142   -- If the verbose output from the BootROM is enabled, the BootROM will produce a
143   - letter on the Debug UART for each instruction it started processing. Here is a
144   - mapping between the above instructions and the BootROM verbose output:
  142 + - An optional flags lines can be one of the following:
  143 +
  144 + DISPLAYPROGRESS
  145 + - Enable boot progress output form the BootROM.
  146 +
  147 +- If the boot progress output from the BootROM is enabled, the BootROM will
  148 + produce a letter on the Debug UART for each instruction it started processing.
  149 + Here is a mapping between the above instructions and the BootROM output:
145 150  
146 151 H -- SB Image header loaded
147 152 T -- TAG instruction
... ... @@ -21,4 +21,5 @@
21 21 obj-y += input/
22 22 # SOC specific infrastructure drivers.
23 23 obj-y += soc/
  24 +obj-y += thermal/
drivers/block/ata_piix.c
Diff comments   View file @ dee332f
... ... @@ -192,6 +192,11 @@
192 192 return 0;
193 193 }
194 194  
  195 +int reset_sata(int dev)
  196 +{
  197 + return 0;
  198 +}
  199 +
195 200 static inline u8 sata_inb(unsigned long ioaddr)
196 201 {
197 202 return inb(ioaddr);
drivers/block/dwc_ahsata.c
Diff comments   View file @ dee332f
... ... @@ -592,6 +592,27 @@
592 592 return 0;
593 593 }
594 594  
  595 +int reset_sata(int dev)
  596 +{
  597 + struct ahci_probe_ent *probe_ent =
  598 + (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
  599 + struct sata_host_regs *host_mmio =
  600 + (struct sata_host_regs *)probe_ent->mmio_base;
  601 +
  602 + if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
  603 + printf("The sata index %d is out of ranges\n\r", dev);
  604 + return -1;
  605 + }
  606 +
  607 + setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
  608 + while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
  609 + udelay(100);
  610 +
  611 + disable_sata_clock();
  612 +
  613 + return 0;
  614 +}
  615 +
595 616 static void dwc_ahsata_print_info(int dev)
596 617 {
597 618 block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
drivers/block/fsl_sata.c
Diff comments   View file @ dee332f
... ... @@ -255,6 +255,11 @@
255 255 return 0;
256 256 }
257 257  
  258 +int reset_sata(int dev)
  259 +{
  260 + return 0;
  261 +}
  262 +
258 263 static void fsl_sata_dump_regs(fsl_sata_reg_t __iomem *reg)
259 264 {
260 265 printf("\n\rSATA: %08x\n\r", (u32)reg);
drivers/block/pata_bfin.c
Diff comments   View file @ dee332f
... ... @@ -1009,6 +1009,11 @@
1009 1009 return res;
1010 1010 }
1011 1011  
  1012 +int reset_sata(int dev)
  1013 +{
  1014 + return 0;
  1015 +}
  1016 +
1012 1017 /* Read up to 255 sectors
1013 1018 *
1014 1019 * Returns sectors read
drivers/block/sata_dwc.c
Diff comments   View file @ dee332f
... ... @@ -423,6 +423,11 @@
423 423 return rc;
424 424 }
425 425  
  426 +int reset_sata(int dev)
  427 +{
  428 + return 0;
  429 +}
  430 +
426 431 static u8 ata_check_altstatus(struct ata_port *ap)
427 432 {
428 433 u8 val = 0;
drivers/block/sata_sil.c
Diff comments   View file @ dee332f
... ... @@ -571,6 +571,11 @@
571 571 return 0;
572 572 }
573 573  
  574 +int reset_sata(int dev)
  575 +{
  576 + return 0;
  577 +}
  578 +
574 579 /*
575 580 * SATA interface between low level driver and command layer
576 581 */
drivers/block/sata_sil3114.c
Diff comments   View file @ dee332f
... ... @@ -702,6 +702,11 @@
702 702 return res;
703 703 }
704 704  
  705 +int reset_sata(int dev)
  706 +{
  707 + return 0;
  708 +}
  709 +
705 710 /* Check if device is connected to port */
706 711 int sata_bus_probe (int portno)
707 712 {
drivers/mmc/fsl_esdhc.c
Diff comments   View file @ dee332f
... ... @@ -23,6 +23,13 @@
23 23  
24 24 DECLARE_GLOBAL_DATA_PTR;
25 25  
  26 +#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
  27 + IRQSTATEN_CINT | \
  28 + IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
  29 + IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
  30 + IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
  31 + IRQSTATEN_DINT)
  32 +
26 33 struct fsl_esdhc {
27 34 uint dsaddr; /* SDMA system address register */
28 35 uint blkattr; /* Block attributes register */
... ... @@ -558,6 +565,7 @@
558 565 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
559 566 | SYSCTL_IPGEN | SYSCTL_CKEN);
560 567  
  568 + writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
561 569 memset(&cfg->cfg, 0, sizeof(cfg->cfg));
562 570  
563 571 voltage_caps = 0;
drivers/thermal/Makefile
Diff comments   View file @ dee332f
  1 +#
  2 +# (C) Copyright 2014 Freescale Semiconductor, Inc.
  3 +# Author: Nitin Garg <nitin.garg@freescale.com>
  4 +#
  5 +# SPDX-License-Identifier: GPL-2.0+
  6 +#
  7 +
  8 +obj-$(CONFIG_DM_THERMAL) += thermal-uclass.o
  9 +obj-$(CONFIG_IMX6_THERMAL) += imx_thermal.o
drivers/thermal/imx_thermal.c
Diff comments   View file @ dee332f
  1 +/*
  2 + * (C) Copyright 2014 Freescale Semiconductor, Inc.
  3 + * Author: Nitin Garg <nitin.garg@freescale.com>
  4 + * Ye Li <Ye.Li@freescale.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <config.h>
  10 +#include <common.h>
  11 +#include <div64.h>
  12 +#include <fuse.h>
  13 +#include <asm/io.h>
  14 +#include <asm/arch/clock.h>
  15 +#include <dm.h>
  16 +#include <errno.h>
  17 +#include <malloc.h>
  18 +#include <thermal.h>
  19 +#include <imx_thermal.h>
  20 +
  21 +#define TEMPERATURE_MIN -40
  22 +#define TEMPERATURE_HOT 80
  23 +#define TEMPERATURE_MAX 125
  24 +#define FACTOR0 10000000
  25 +#define FACTOR1 15976
  26 +#define FACTOR2 4297157
  27 +#define MEASURE_FREQ 327
  28 +
  29 +#define TEMPSENSE0_TEMP_CNT_SHIFT 8
  30 +#define TEMPSENSE0_TEMP_CNT_MASK (0xfff << TEMPSENSE0_TEMP_CNT_SHIFT)
  31 +#define TEMPSENSE0_FINISHED (1 << 2)
  32 +#define TEMPSENSE0_MEASURE_TEMP (1 << 1)
  33 +#define TEMPSENSE0_POWER_DOWN (1 << 0)
  34 +#define MISC0_REFTOP_SELBIASOFF (1 << 3)
  35 +#define TEMPSENSE1_MEASURE_FREQ 0xffff
  36 +
  37 +static int read_cpu_temperature(struct udevice *dev)
  38 +{
  39 + int temperature;
  40 + unsigned int reg, n_meas;
  41 + const struct imx_thermal_plat *pdata = dev_get_platdata(dev);
  42 + struct anatop_regs *anatop = (struct anatop_regs *)pdata->regs;
  43 + unsigned int *priv = dev_get_priv(dev);
  44 + u32 fuse = *priv;
  45 + int t1, n1;
  46 + u32 c1, c2;
  47 + u64 temp64;
  48 +
  49 + /*
  50 + * Sensor data layout:
  51 + * [31:20] - sensor value @ 25C
  52 + * We use universal formula now and only need sensor value @ 25C
  53 + * slope = 0.4297157 - (0.0015976 * 25C fuse)
  54 + */
  55 + n1 = fuse >> 20;
  56 + t1 = 25; /* t1 always 25C */
  57 +
  58 + /*
  59 + * Derived from linear interpolation:
  60 + * slope = 0.4297157 - (0.0015976 * 25C fuse)
  61 + * slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0
  62 + * (Nmeas - n1) / (Tmeas - t1) = slope
  63 + * We want to reduce this down to the minimum computation necessary
  64 + * for each temperature read. Also, we want Tmeas in millicelsius
  65 + * and we don't want to lose precision from integer division. So...
  66 + * Tmeas = (Nmeas - n1) / slope + t1
  67 + * milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1
  68 + * milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1
  69 + * Let constant c1 = (-1000 / slope)
  70 + * milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1
  71 + * Let constant c2 = n1 *c1 + 1000 * t1
  72 + * milli_Tmeas = c2 - Nmeas * c1
  73 + */
  74 + temp64 = FACTOR0;
  75 + temp64 *= 1000;
  76 + do_div(temp64, FACTOR1 * n1 - FACTOR2);
  77 + c1 = temp64;
  78 + c2 = n1 * c1 + 1000 * t1;
  79 +
  80 + /*
  81 + * now we only use single measure, every time we read
  82 + * the temperature, we will power on/down anadig thermal
  83 + * module
  84 + */
  85 + writel(TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr);
  86 + writel(MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
  87 +
  88 + /* setup measure freq */
  89 + reg = readl(&anatop->tempsense1);
  90 + reg &= ~TEMPSENSE1_MEASURE_FREQ;
  91 + reg |= MEASURE_FREQ;
  92 + writel(reg, &anatop->tempsense1);
  93 +
  94 + /* start the measurement process */
  95 + writel(TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr);
  96 + writel(TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
  97 + writel(TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set);
  98 +
  99 + /* make sure that the latest temp is valid */
  100 + while ((readl(&anatop->tempsense0) &
  101 + TEMPSENSE0_FINISHED) == 0)
  102 + udelay(10000);
  103 +
  104 + /* read temperature count */
  105 + reg = readl(&anatop->tempsense0);
  106 + n_meas = (reg & TEMPSENSE0_TEMP_CNT_MASK)
  107 + >> TEMPSENSE0_TEMP_CNT_SHIFT;
  108 + writel(TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
  109 +
  110 + /* milli_Tmeas = c2 - Nmeas * c1 */
  111 + temperature = (c2 - n_meas * c1)/1000;
  112 +
  113 + /* power down anatop thermal sensor */
  114 + writel(TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set);
  115 + writel(MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr);
  116 +
  117 + return temperature;
  118 +}
  119 +
  120 +int imx_thermal_get_temp(struct udevice *dev, int *temp)
  121 +{
  122 + int cpu_tmp = 0;
  123 +
  124 + cpu_tmp = read_cpu_temperature(dev);
  125 + while (cpu_tmp > TEMPERATURE_MIN && cpu_tmp < TEMPERATURE_MAX) {
  126 + if (cpu_tmp >= TEMPERATURE_HOT) {
  127 + printf("CPU Temperature is %d C, too hot to boot, waiting...\n",
  128 + cpu_tmp);
  129 + udelay(5000000);
  130 + cpu_tmp = read_cpu_temperature(dev);
  131 + } else {
  132 + break;
  133 + }
  134 + }
  135 +
  136 + *temp = cpu_tmp;
  137 +
  138 + return 0;
  139 +}
  140 +
  141 +static const struct dm_thermal_ops imx_thermal_ops = {
  142 + .get_temp = imx_thermal_get_temp,
  143 +};
  144 +
  145 +static int imx_thermal_probe(struct udevice *dev)
  146 +{
  147 + unsigned int fuse = ~0;
  148 +
  149 + const struct imx_thermal_plat *pdata = dev_get_platdata(dev);
  150 + unsigned int *priv = dev_get_priv(dev);
  151 +
  152 + /* Read Temperature calibration data fuse */
  153 + fuse_read(pdata->fuse_bank, pdata->fuse_word, &fuse);
  154 +
  155 + /* Check for valid fuse */
  156 + if (fuse == 0 || fuse == ~0) {
  157 + printf("CPU: Thermal invalid data, fuse: 0x%x\n", fuse);
  158 + return -EPERM;
  159 + } else {
  160 + printf("CPU: Thermal calibration data: 0x%x\n", fuse);
  161 + }
  162 +
  163 + *priv = fuse;
  164 +
  165 + enable_thermal_clk();
  166 +
  167 + return 0;
  168 +}
  169 +
  170 +U_BOOT_DRIVER(imx_thermal) = {
  171 + .name = "imx_thermal",
  172 + .id = UCLASS_THERMAL,
  173 + .ops = &imx_thermal_ops,
  174 + .probe = imx_thermal_probe,
  175 + .priv_auto_alloc_size = sizeof(unsigned int),
  176 + .flags = DM_FLAG_PRE_RELOC,
  177 +};
drivers/thermal/thermal-uclass.c
Diff comments   View file @ dee332f
  1 +/*
  2 + * (C) Copyright 2014 Freescale Semiconductor, Inc
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <dm.h>
  9 +#include <thermal.h>
  10 +#include <errno.h>
  11 +#include <fdtdec.h>
  12 +#include <malloc.h>
  13 +#include <asm/io.h>
  14 +#include <linux/list.h>
  15 +
  16 +
  17 +int thermal_get_temp(struct udevice *dev, int *temp)
  18 +{
  19 + const struct dm_thermal_ops *ops = device_get_ops(dev);
  20 +
  21 + if (!ops->get_temp)
  22 + return -ENOSYS;
  23 +
  24 + return ops->get_temp(dev, temp);
  25 +}
  26 +
  27 +UCLASS_DRIVER(thermal) = {
  28 + .id = UCLASS_THERMAL,
  29 + .name = "thermal",
  30 +};
include/configs/mx6qsabreauto.h
Diff comments   View file @ dee332f
... ... @@ -37,6 +37,16 @@
37 37  
38 38 #include "mx6sabre_common.h"
39 39  
  40 +#undef CONFIG_SYS_NO_FLASH
  41 +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
  42 +#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
  43 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  44 +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  45 +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
  46 +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
  47 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
  48 +#define CONFIG_SYS_FLASH_EMPTY_INFO
  49 +
40 50 #define CONFIG_SYS_FSL_USDHC_NUM 2
41 51 #if defined(CONFIG_ENV_IS_IN_MMC)
42 52 #define CONFIG_SYS_MMC_ENV_DEV 0
... ... @@ -63,6 +73,12 @@
63 73 #define CONFIG_APBH_DMA
64 74 #define CONFIG_APBH_DMA_BURST
65 75 #define CONFIG_APBH_DMA_BURST8
  76 +
  77 +/* PMIC */
  78 +#define CONFIG_POWER
  79 +#define CONFIG_POWER_I2C
  80 +#define CONFIG_POWER_PFUZE100
  81 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
66 82  
67 83 #endif /* __MX6QSABREAUTO_CONFIG_H */
include/configs/mx6sabre_common.h
Diff comments   View file @ dee332f
... ... @@ -25,6 +25,11 @@
25 25 #define CONFIG_INITRD_TAG
26 26 #define CONFIG_REVISION_TAG
27 27  
  28 +#define CONFIG_DM
  29 +#define CONFIG_DM_THERMAL
  30 +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
  31 +#define CONFIG_IMX6_THERMAL
  32 +
28 33 #define CONFIG_SYS_GENERIC_BOARD
29 34  
30 35 /* Size of malloc() pool */
... ... @@ -37,7 +42,7 @@
37 42 #define CONFIG_MXC_UART
38 43  
39 44 #define CONFIG_CMD_FUSE
40   -#ifdef CONFIG_CMD_FUSE
  45 +#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
41 46 #define CONFIG_MXC_OCOTP
42 47 #endif
43 48  
include/configs/mx6slevk.h
Diff comments   View file @ dee332f
... ... @@ -87,7 +87,7 @@
87 87 "fdt_addr=0x88000000\0" \
88 88 "boot_fdt=try\0" \
89 89 "ip_dyn=yes\0" \
90   - "mmcdev=0\0" \" \
  90 + "mmcdev=1\0" \" \
91 91 "mmcpart=1\0" \
92 92 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
93 93 "mmcargs=setenv bootargs console=${console},${baudrate} " \
include/configs/mx6sxsabresd.h
Diff comments   View file @ dee332f
... ... @@ -59,7 +59,7 @@
59 59 "fdt_addr=0x88000000\0" \
60 60 "boot_fdt=try\0" \
61 61 "ip_dyn=yes\0" \
62   - "mmcdev=0\0" \" \
  62 + "mmcdev=2\0" \" \
63 63 "mmcpart=1\0" \
64 64 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
65 65 "mmcargs=setenv bootargs console=${console},${baudrate} " \
66 66  
... ... @@ -214,13 +214,17 @@
214 214 #define CONFIG_ENV_OFFSET (6 * SZ_64K)
215 215 #define CONFIG_ENV_SIZE SZ_8K
216 216 #define CONFIG_ENV_IS_IN_MMC
217   -#define CONFIG_SYS_MMC_ENV_DEV 0
218 217  
219 218 #define CONFIG_OF_LIBFDT
220 219 #define CONFIG_CMD_BOOTZ
221 220  
222 221 #ifndef CONFIG_SYS_DCACHE_OFF
223 222 #define CONFIG_CMD_CACHE
  223 +#endif
  224 +
  225 +#define CONFIG_SYS_FSL_USDHC_NUM 3
  226 +#if defined(CONFIG_ENV_IS_IN_MMC)
  227 +#define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/
224 228 #endif
225 229  
226 230 #endif /* __CONFIG_H */
include/configs/tqma6.h
Diff comments   View file @ dee332f
... ... @@ -68,6 +68,8 @@
68 68 #define CONFIG_SPI_FLASH
69 69 #define CONFIG_SPI_FLASH_STMICRO
70 70  
  71 +#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K
  72 +
71 73 #define CONFIG_CMD_SF
72 74 #define CONFIG_SF_DEFAULT_BUS 0
73 75 #define CONFIG_SF_DEFAULT_CS 0
74 76  
... ... @@ -275,12 +277,10 @@
275 277  
276 278 #elif defined(CONFIG_TQMA6X_SPI_BOOT)
277 279  
278   -#define CONFIG_FLASH_SECTOR_SIZE 0x10000
279   -
280 280 #define TQMA6_UBOOT_OFFSET 0x400
281 281 #define TQMA6_UBOOT_SECTOR_START 0x0
282 282 /* max u-boot size: 512k */
283   -#define TQMA6_UBOOT_SECTOR_SIZE CONFIG_FLASH_SECTOR_SIZE
  283 +#define TQMA6_UBOOT_SECTOR_SIZE TQMA6_SPI_FLASH_SECTOR_SIZE
284 284 #define TQMA6_UBOOT_SECTOR_COUNT 0x8
285 285 #define TQMA6_UBOOT_SIZE (TQMA6_UBOOT_SECTOR_SIZE * \
286 286 TQMA6_UBOOT_SECTOR_COUNT)
... ... @@ -288,7 +288,7 @@
288 288 #define CONFIG_ENV_IS_IN_SPI_FLASH
289 289 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
290 290 #define CONFIG_ENV_OFFSET (TQMA6_UBOOT_SIZE)
291   -#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
  291 +#define CONFIG_ENV_SECT_SIZE TQMA6_SPI_FLASH_SECTOR_SIZE
292 292 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
293 293 CONFIG_ENV_SECT_SIZE)
294 294  
... ... @@ -299,7 +299,7 @@
299 299  
300 300 #define TQMA6_FDT_OFFSET (CONFIG_ENV_OFFSET_REDUND + \
301 301 CONFIG_ENV_SECT_SIZE)
302   -#define TQMA6_FDT_SECT_SIZE (CONFIG_FLASH_SECTOR_SIZE)
  302 +#define TQMA6_FDT_SECT_SIZE (TQMA6_SPI_FLASH_SECTOR_SIZE)
303 303  
304 304 #define TQMA6_FDT_SECTOR_START 0x0a /* 8 Sector u-boot, 2 Sector env */
305 305 #define TQMA6_FDT_SECTOR_COUNT 0x01
... ... @@ -320,7 +320,7 @@
320 320 "setexpr blkc ${filesize} + " \
321 321 __stringify(TQMA6_UBOOT_OFFSET) "; " \
322 322 "setexpr size ${uboot_sectors} * " \
323   - __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
  323 + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
324 324 "if itest ${blkc} <= ${size}; then " \
325 325 "sf probe; " \
326 326 "sf erase 0 ${size}; " \
327 327  
... ... @@ -332,9 +332,9 @@
332 332 "update_kernel=run kernel_name; if tftp ${kernel}; then " \
333 333 "if itest ${filesize} > 0; then " \
334 334 "setexpr size ${kernel_sectors} * " \
335   - __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
  335 + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
336 336 "setexpr offset ${kernel_start} * " \
337   - __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
  337 + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
338 338 "if itest ${filesize} <= ${size}; then " \
339 339 "sf probe; " \
340 340 "sf erase ${offset} ${size}; " \
341 341  
... ... @@ -346,9 +346,9 @@
346 346 "update_fdt=if tftp ${fdt_file}; then " \
347 347 "if itest ${filesize} > 0; then " \
348 348 "setexpr size ${fdt_sectors} * " \
349   - __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
  349 + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
350 350 "setexpr offset ${fdt_start} * " \
351   - __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
  351 + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
352 352 "if itest ${filesize} <= ${size}; then " \
353 353 "sf probe; " \
354 354 "sf erase ${offset} ${size}; " \
355 355  
356 356  
357 357  
... ... @@ -359,16 +359,16 @@
359 359 "setenv filesize 0; setenv size ; setenv offset\0" \
360 360 "loadimage=sf probe; " \
361 361 "setexpr size ${kernel_sectors} * " \
362   - __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
  362 + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
363 363 "setexpr offset ${kernel_start} * " \
364   - __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
  364 + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
365 365 "sf read ${loadaddr} ${offset} ${size}; " \
366 366 "setenv size ; setenv offset\0" \
367 367 "loadfdt=sf probe; " \
368 368 "setexpr size ${fdt_sectors} * " \
369   - __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
  369 + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
370 370 "setexpr offset ${fdt_start} * " \
371   - __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
  371 + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
372 372 "sf read ${${fdt_addr}} ${offset} ${size}; " \
373 373 "setenv size ; setenv offset\0" \
374 374  
include/dm/uclass-id.h
Diff comments   View file @ dee332f
... ... @@ -28,6 +28,7 @@
28 28 UCLASS_SPI_GENERIC, /* Generic SPI flash target */
29 29 UCLASS_SPI_FLASH, /* SPI flash */
30 30 UCLASS_CROS_EC, /* Chrome OS EC */
  31 + UCLASS_THERMAL, /* Thermal sensor */
31 32  
32 33 UCLASS_COUNT,
33 34 UCLASS_INVALID = -1,
include/imx_thermal.h
Diff comments   View file @ dee332f
  1 +/*
  2 + *
  3 + * (C) Copyright 2014 Freescale Semiconductor, Inc
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef _IMX_THERMAL_H_
  9 +#define _IMX_THERMAL_H_
  10 +
  11 +struct imx_thermal_plat {
  12 + void *regs;
  13 + int fuse_bank;
  14 + int fuse_word;
  15 +};
  16 +
  17 +#endif /* _IMX_THERMAL_H_ */
include/power/pfuze100_pmic.h
Diff comments   View file @ dee332f
... ... @@ -38,6 +38,86 @@
38 38 };
39 39  
40 40 /*
  41 + * Buck Regulators
  42 + */
  43 +
  44 +/* SW1A/B/C Output Voltage Configuration */
  45 +#define SW1x_0_300V 0
  46 +#define SW1x_0_325V 1
  47 +#define SW1x_0_350V 2
  48 +#define SW1x_0_375V 3
  49 +#define SW1x_0_400V 4
  50 +#define SW1x_0_425V 5
  51 +#define SW1x_0_450V 6
  52 +#define SW1x_0_475V 7
  53 +#define SW1x_0_500V 8
  54 +#define SW1x_0_525V 9
  55 +#define SW1x_0_550V 10
  56 +#define SW1x_0_575V 11
  57 +#define SW1x_0_600V 12
  58 +#define SW1x_0_625V 13
  59 +#define SW1x_0_650V 14
  60 +#define SW1x_0_675V 15
  61 +#define SW1x_0_700V 16
  62 +#define SW1x_0_725V 17
  63 +#define SW1x_0_750V 18
  64 +#define SW1x_0_775V 19
  65 +#define SW1x_0_800V 20
  66 +#define SW1x_0_825V 21
  67 +#define SW1x_0_850V 22
  68 +#define SW1x_0_875V 23
  69 +#define SW1x_0_900V 24
  70 +#define SW1x_0_925V 25
  71 +#define SW1x_0_950V 26
  72 +#define SW1x_0_975V 27
  73 +#define SW1x_1_000V 28
  74 +#define SW1x_1_025V 29
  75 +#define SW1x_1_050V 30
  76 +#define SW1x_1_075V 31
  77 +#define SW1x_1_100V 32
  78 +#define SW1x_1_125V 33
  79 +#define SW1x_1_150V 34
  80 +#define SW1x_1_175V 35
  81 +#define SW1x_1_200V 36
  82 +#define SW1x_1_225V 37
  83 +#define SW1x_1_250V 38
  84 +#define SW1x_1_275V 39
  85 +#define SW1x_1_300V 40
  86 +#define SW1x_1_325V 41
  87 +#define SW1x_1_350V 42
  88 +#define SW1x_1_375V 43
  89 +#define SW1x_1_400V 44
  90 +#define SW1x_1_425V 45
  91 +#define SW1x_1_450V 46
  92 +#define SW1x_1_475V 47
  93 +#define SW1x_1_500V 48
  94 +#define SW1x_1_525V 49
  95 +#define SW1x_1_550V 50
  96 +#define SW1x_1_575V 51
  97 +#define SW1x_1_600V 52
  98 +#define SW1x_1_625V 53
  99 +#define SW1x_1_650V 54
  100 +#define SW1x_1_675V 55
  101 +#define SW1x_1_700V 56
  102 +#define SW1x_1_725V 57
  103 +#define SW1x_1_750V 58
  104 +#define SW1x_1_775V 59
  105 +#define SW1x_1_800V 60
  106 +#define SW1x_1_825V 61
  107 +#define SW1x_1_850V 62
  108 +#define SW1x_1_875V 63
  109 +
  110 +#define SW1x_NORMAL_MASK 0x3f
  111 +#define SW1x_STBY_MASK 0x3f
  112 +#define SW1x_OFF_MASK 0x3f
  113 +
  114 +#define SW1xCONF_DVSSPEED_MASK 0xc0
  115 +#define SW1xCONF_DVSSPEED_2US 0x00
  116 +#define SW1xCONF_DVSSPEED_4US 0x40
  117 +#define SW1xCONF_DVSSPEED_8US 0x80
  118 +#define SW1xCONF_DVSSPEED_16US 0xc0
  119 +
  120 +/*
41 121 * LDO Configuration
42 122 */
43 123  
... ... @@ -3,12 +3,15 @@
3 3 #include <part.h>
4 4  
5 5 int init_sata(int dev);
  6 +int reset_sata(int dev);
6 7 int scan_sata(int dev);
7 8 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer);
8 9 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer);
9 10  
10 11 int sata_initialize(void);
11 12 int __sata_initialize(void);
  13 +int sata_stop(void);
  14 +int __sata_stop(void);
12 15 int sata_port_status(int dev, int port);
13 16  
14 17 extern block_dev_desc_t sata_dev_desc[];
  1 +/*
  2 + *
  3 + * (C) Copyright 2014 Freescale Semiconductor, Inc
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef _THERMAL_H_
  9 +#define _THERMAL_H_
  10 +
  11 +#include <dm.h>
  12 +
  13 +int thermal_get_temp(struct udevice *dev, int *temp);
  14 +
  15 +/**
  16 + * struct struct dm_thermal_ops - Driver model Thermal operations
  17 + *
  18 + * The uclass interface is implemented by all Thermal devices which use
  19 + * driver model.
  20 + */
  21 +struct dm_thermal_ops {
  22 + /**
  23 + * Get the current temperature
  24 + *
  25 + * The device provided is the slave device. It's parent controller
  26 + * will be used to provide the communication.
  27 + *
  28 + * This must be called before doing any transfers with a Thermal slave.
  29 + * It will enable and initialize any Thermal hardware as necessary,
  30 + * and make sure that the SCK line is in the correct idle state. It is
  31 + * not allowed to claim the same bus for several slaves without
  32 + * releasing the bus in between.
  33 + *
  34 + * @dev: The Thermal device
  35 + *
  36 + * Returns: 0 if the bus was claimed successfully, or a negative value
  37 + * if it wasn't.
  38 + */
  39 + int (*get_temp)(struct udevice *dev, int *temp);
  40 +};
  41 +
  42 +#endif /* _THERMAL_H_ */
... ... @@ -125,7 +125,7 @@
125 125 unsigned int in_section:1;
126 126 unsigned int in_dcd:1;
127 127 /* Image configuration */
128   - unsigned int verbose_boot:1;
  128 + unsigned int display_progress:1;
129 129 unsigned int silent_dump:1;
130 130 char *input_filename;
131 131 char *output_filename;
... ... @@ -1308,8 +1308,8 @@
1308 1308 sizeof(struct sb_sections_header) / SB_BLOCK_SIZE;
1309 1309 hdr->timestamp_us = sb_get_timestamp() * 1000000;
1310 1310  
1311   - /* FIXME -- add proper config option */
1312   - hdr->flags = ictx->verbose_boot ? SB_IMAGE_FLAG_VERBOSE : 0,
  1311 + hdr->flags = ictx->display_progress ?
  1312 + SB_IMAGE_FLAG_DISPLAY_PROGRESS : 0;
1313 1313  
1314 1314 /* FIXME -- We support only default key */
1315 1315 hdr->key_count = 1;
... ... @@ -1416,7 +1416,7 @@
1416 1416 {
1417 1417 char *tok;
1418 1418 char *line = cmd->cmd;
1419   - char *rptr;
  1419 + char *rptr = NULL;
1420 1420 int ret;
1421 1421  
1422 1422 /* Analyze the identifier on this line first. */
... ... @@ -1428,6 +1428,12 @@
1428 1428  
1429 1429 cmd->cmd = rptr;
1430 1430  
  1431 + /* set DISPLAY_PROGRESS flag */
  1432 + if (!strcmp(tok, "DISPLAYPROGRESS")) {
  1433 + ictx->display_progress = 1;
  1434 + return 0;
  1435 + }
  1436 +
1431 1437 /* DCD */
1432 1438 if (!strcmp(tok, "DCD")) {
1433 1439 ictx->in_section = 0;
1434 1440  
... ... @@ -1681,10 +1687,11 @@
1681 1687 ntohs(hdr->component_version.minor),
1682 1688 ntohs(hdr->component_version.revision));
1683 1689  
1684   - if (hdr->flags & ~SB_IMAGE_FLAG_VERBOSE)
  1690 + if (hdr->flags & ~SB_IMAGE_FLAGS_MASK)
1685 1691 ret = -EINVAL;
1686 1692 soprintf(ictx, "%s Image flags: %s\n", stat[!!ret],
1687   - hdr->flags & SB_IMAGE_FLAG_VERBOSE ? "Verbose_boot" : "");
  1693 + hdr->flags & SB_IMAGE_FLAG_DISPLAY_PROGRESS ?
  1694 + "Display_progress" : "");
1688 1695 if (ret)
1689 1696 return ret;
1690 1697  
... ... @@ -2287,7 +2294,6 @@
2287 2294  
2288 2295 ctx.cfg_filename = params->imagename;
2289 2296 ctx.output_filename = params->imagefile;
2290   - ctx.verbose_boot = 1;
2291 2297  
2292 2298 ret = sb_build_tree_from_cfg(&ctx);
2293 2299 if (ret)
... ... @@ -81,8 +81,9 @@
81 81 #define SB_VERSION_MAJOR 1
82 82 #define SB_VERSION_MINOR 1
83 83  
84   -/* Enable to HTLLC verbose boot report. */
85   -#define SB_IMAGE_FLAG_VERBOSE (1 << 0)
  84 +/* Enable to HTLLC boot report. */
  85 +#define SB_IMAGE_FLAG_DISPLAY_PROGRESS (1 << 0)
  86 +#define SB_IMAGE_FLAGS_MASK SB_IMAGE_FLAG_DISPLAY_PROGRESS
86 87  
87 88 struct sb_key_dictionary_key {
88 89 /* The CBC-MAC of image and sections header. */