mx25pdk: Add Ethernet support

mx25pdk has a Ethernet port that is connected to its internal FEC controller. In order to power up the Ethernet PHY (DP83640) it is necessary to communicate with the MC34704 PMIC via I2C. Make the FEC ethernet port functional Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

mx25pdk: Add Ethernet support
mx25pdk has a Ethernet port that is connected to its internal FEC controller. In order to power up the Ethernet PHY (DP83640) it is necessary to communicate with the MC34704 PMIC via I2C. Make the FEC ethernet port functional Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam · Stefano Babic
1 parent 787f4f3082
Showing 2 changed files with 83 additions and 0 deletions Side-by-side Diff
board/freescale/mx25pdk/mx25pdk.c
include/configs/mx25pdk.h
@@ -26,7 +26,13 @@
 #include <asm/arch/clock.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
+#include <i2c.h>
+#include <pmic.h>
+#include <fsl_pmic.h>
+#include <mc34704.h>
  
+#define FEC_RESET_B		IMX_GPIO_NR(2, 3)
+#define FEC_ENABLE_B		IMX_GPIO_NR(4, 8)
 #define CARD_DETECT		IMX_GPIO_NR(2, 1)
  
 DECLARE_GLOBAL_DATA_PTR;
@@ -37,6 +43,47 @@
 };
 #endif
  
+static void mx25pdk_fec_init(void)
+{
+	struct iomuxc_mux_ctl *muxctl;
+	struct iomuxc_pad_ctl *padctl;
+	u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
+	u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
+
+	/* FEC pin init is generic */
+	mx25_fec_init_pins();
+
+	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
+	/*
+	 * Set up FEC_RESET_B and FEC_ENABLE_B
+	 *
+	 * FEC_RESET_B: gpio2_3 is ALT 5 mode of pin D12
+	 * FEC_ENABLE_B: gpio4_8 is ALT 5 mode of pin A17
+	 */
+	writel(gpio_mux_mode, &muxctl->pad_d12);
+	writel(gpio_mux_mode, &muxctl->pad_a17);
+
+	writel(0x0, &padctl->pad_d12);
+	writel(0x0, &padctl->pad_a17);
+
+	/* Assert RESET and ENABLE low */
+	gpio_direction_output(FEC_RESET_B, 0);
+	gpio_direction_output(FEC_ENABLE_B, 0);
+
+	udelay(10);
+
+	/* Deassert RESET and ENABLE */
+	gpio_set_value(FEC_RESET_B, 1);
+	gpio_set_value(FEC_ENABLE_B, 1);
+
+	/* Setup I2C pins so that PMIC can turn on PHY supply */
+	writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_clk);
+	writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_dat);
+	writel(0x1E8, &padctl->pad_i2c1_clk);
+	writel(0x1E8, &padctl->pad_i2c1_dat);
+}
+
 int dram_init(void)
 {
 	/* dram_init must store complete ramsize in gd->ram_size */
@@ -56,6 +103,20 @@
 {
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	struct pmic *p;
+
+	mx25pdk_fec_init();
+
+	pmic_init();
+	p = get_pmic();
+	/* Turn on Ethernet PHY supply */
+	pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE);
  
 	return 0;
 }
@@ -43,6 +43,7 @@
 #define PHYS_SDRAM_1_SIZE	(64 * 1024 * 1024)
  
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
  
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 #define CONFIG_SYS_INIT_RAM_ADDR	IMX_RAM_BASE
  
@@ -105,7 +106,28 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 #define CONFIG_SYS_FSL_ESDHC_NUM	1
  
+/* PMIC Configs */
+#define CONFIG_PMIC
+#define CONFIG_PMIC_I2C
+#define CONFIG_PMIC_FSL
+#define CONFIG_PMIC_FSL_MC34704
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x54
+
 #define CONFIG_DOS_PARTITION
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE		IMX_I2C_BASE
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* Ethernet Configs */
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
  
 #define CONFIG_BOOTDELAY	3
...	...	@@ -26,7 +26,13 @@
26	26	#include <asm/arch/clock.h>
27	27	#include <mmc.h>
28	28	#include <fsl_esdhc.h>
	29	+#include <i2c.h>
	30	+#include <pmic.h>
	31	+#include <fsl_pmic.h>
	32	+#include <mc34704.h>
29	33
	34	+#define FEC_RESET_B IMX_GPIO_NR(2, 3)
	35	+#define FEC_ENABLE_B IMX_GPIO_NR(4, 8)
30	36	#define CARD_DETECT IMX_GPIO_NR(2, 1)
31	37
32	38	DECLARE_GLOBAL_DATA_PTR;
...	...	@@ -37,6 +43,47 @@
37	43	};
38	44	#endif
39	45
	46	+static void mx25pdk_fec_init(void)
	47	+{
	48	+ struct iomuxc_mux_ctl *muxctl;
	49	+ struct iomuxc_pad_ctl *padctl;
	50	+ u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
	51	+ u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) \| MX25_PIN_MUX_SION;
	52	+
	53	+ /* FEC pin init is generic */
	54	+ mx25_fec_init_pins();
	55	+
	56	+ muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
	57	+ padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
	58	+ /*
	59	+ * Set up FEC_RESET_B and FEC_ENABLE_B
	60	+ *
	61	+ * FEC_RESET_B: gpio2_3 is ALT 5 mode of pin D12
	62	+ * FEC_ENABLE_B: gpio4_8 is ALT 5 mode of pin A17
	63	+ */
	64	+ writel(gpio_mux_mode, &muxctl->pad_d12);
	65	+ writel(gpio_mux_mode, &muxctl->pad_a17);
	66	+
	67	+ writel(0x0, &padctl->pad_d12);
	68	+ writel(0x0, &padctl->pad_a17);
	69	+
	70	+ /* Assert RESET and ENABLE low */
	71	+ gpio_direction_output(FEC_RESET_B, 0);
	72	+ gpio_direction_output(FEC_ENABLE_B, 0);
	73	+
	74	+ udelay(10);
	75	+
	76	+ /* Deassert RESET and ENABLE */
	77	+ gpio_set_value(FEC_RESET_B, 1);
	78	+ gpio_set_value(FEC_ENABLE_B, 1);
	79	+
	80	+ /* Setup I2C pins so that PMIC can turn on PHY supply */
	81	+ writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_clk);
	82	+ writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_dat);
	83	+ writel(0x1E8, &padctl->pad_i2c1_clk);
	84	+ writel(0x1E8, &padctl->pad_i2c1_dat);
	85	+}
	86	+
40	87	int dram_init(void)
41	88	{
42	89	/* dram_init must store complete ramsize in gd->ram_size */
...	...	@@ -56,6 +103,20 @@
56	103	{
57	104	/* address of boot parameters */
58	105	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
	106	+
	107	+ return 0;
	108	+}
	109	+
	110	+int board_late_init(void)
	111	+{
	112	+ struct pmic *p;
	113	+
	114	+ mx25pdk_fec_init();
	115	+
	116	+ pmic_init();
	117	+ p = get_pmic();
	118	+ /* Turn on Ethernet PHY supply */
	119	+ pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE);
59	120
60	121	return 0;
61	122	}
...	...	@@ -43,6 +43,7 @@
43	43	#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
44	44
45	45	#define CONFIG_BOARD_EARLY_INIT_F
	46	+#define CONFIG_BOARD_LATE_INIT
46	47
47	48	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
48	49	#define CONFIG_SYS_INIT_RAM_ADDR IMX_RAM_BASE
49	50
...	...	@@ -105,7 +106,28 @@
105	106	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
106	107	#define CONFIG_SYS_FSL_ESDHC_NUM 1
107	108
	109	+/* PMIC Configs */
	110	+#define CONFIG_PMIC
	111	+#define CONFIG_PMIC_I2C
	112	+#define CONFIG_PMIC_FSL
	113	+#define CONFIG_PMIC_FSL_MC34704
	114	+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x54
	115	+
108	116	#define CONFIG_DOS_PARTITION
	117	+
	118	+/* I2C Configs */
	119	+#define CONFIG_CMD_I2C
	120	+#define CONFIG_HARD_I2C
	121	+#define CONFIG_I2C_MXC
	122	+#define CONFIG_SYS_I2C_BASE IMX_I2C_BASE
	123	+#define CONFIG_SYS_I2C_SPEED 100000
	124	+
	125	+/* Ethernet Configs */
	126	+
	127	+#define CONFIG_CMD_PING
	128	+#define CONFIG_CMD_DHCP
	129	+#define CONFIG_CMD_MII
	130	+#define CONFIG_CMD_NET
109	131
110	132	#define CONFIG_BOOTDELAY 3
111	133