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Commit e01bd218b00af73499331a1a701625a852cd286f

Authored by Stefan Roese
1 parent 87ed3bfb42
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

[PATCH] Add AMCC PPC405EZ support 

This patch adds support for the new AMCC 405EZ PPC. It is in
preparation for the AMCC Acadia board support.

Please note that this Acadia/405EZ support is still in a beta stage.
Still lot's of cleanup needed but we need a preliminary release now.

Signed-off-by: Stefan Roese <sr@denx.de>

Showing 12 changed files with 979 additions and 151 deletions Side-by-side Diff

cpu/ppc4xx/4xx_enet.c
Diff comments   View file @ e01bd21
... ... @@ -1333,6 +1333,9 @@
1333 1333 }
1334 1334 }
1335 1335 mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
  1336 +#if defined(CONFIG_405EZ)
  1337 + mtsdr (sdricintstat, SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
  1338 +#endif /* defined(CONFIG_405EZ) */
1336 1339 }
1337 1340 while (serviced);
1338 1341  
... ... @@ -47,6 +47,9 @@
47 47  
48 48 #if defined(CONFIG_440)
49 49 #define FREQ_EBC (sys_info.freqEPB)
  50 +#elif defined(CONFIG_405EZ)
  51 +#define FREQ_EBC ((CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / \
  52 + sys_info.pllExtBusDiv)
50 53 #else
51 54 #define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
52 55 #endif
... ... @@ -209,7 +212,8 @@
209 212  
210 213 puts("AMCC PowerPC 4");
211 214  
212   -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
  215 +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
  216 + defined(CONFIG_405EP) || defined(CONFIG_405EZ)
213 217 puts("05");
214 218 #endif
215 219 #if defined(CONFIG_440)
... ... @@ -257,6 +261,10 @@
257 261 puts("EP Rev. B");
258 262 break;
259 263  
  264 + case PVR_405EZ_RA:
  265 + puts("EZ Rev. A");
  266 + break;
  267 +
260 268 #if defined(CONFIG_440)
261 269 case PVR_440GP_RB:
262 270 puts("GP Rev. B");
... ... @@ -386,9 +394,9 @@
386 394 }
387 395  
388 396 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
389   - sys_info.freqPLB / 1000000,
390   - sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
391   - FREQ_EBC / 1000000);
  397 + sys_info.freqPLB / 1000000,
  398 + get_OPB_freq() / 1000000,
  399 + FREQ_EBC / 1000000);
392 400  
393 401 if (addstr[0] != 0)
394 402 printf(" %s\n", addstr);
... ... @@ -418,7 +426,7 @@
418 426 putc('\n');
419 427 #endif
420 428  
421   -#if defined(CONFIG_405EP)
  429 +#if defined(CONFIG_405EP) || defined(CONFIG_405EZ)
422 430 printf (" 16 kB I-Cache 16 kB D-Cache");
423 431 #elif defined(CONFIG_440)
424 432 printf (" 32 kB I-Cache 32 kB D-Cache");
cpu/ppc4xx/cpu_init.c
Diff comments   View file @ e01bd21
... ... @@ -256,7 +256,8 @@
256 256 */
257 257 #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
258 258 #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
259   - defined(CONFIG_405EP) || defined(CONFIG_405))
  259 + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
  260 + defined(CONFIG_405))
260 261 /*
261 262 * Move the next instructions into icache, since these modify the flash
262 263 * we are running from!
... ... @@ -264,7 +264,8 @@
264 264 #endif /* CONFIG_IOP480 */
265 265  
266 266 /*****************************************************************************/
267   -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
  267 +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
  268 + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
268 269 defined(CONFIG_440)
269 270  
270 271 #if defined(CONFIG_440)
... ... @@ -309,7 +310,7 @@
309 310 #define MFREG(a, d) mfsdr(a, d)
310 311 #define MTREG(a, d) mtsdr(a, d)
311 312 #endif /* #if defined(CONFIG_440GP) */
312   -#elif defined(CONFIG_405EP)
  313 +#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
313 314 #define UART0_BASE 0xef600300
314 315 #define UART1_BASE 0xef600400
315 316 #define UCR0_MASK 0x0000007f
316 317  
317 318  
318 319  
319 320  
320 321  
321 322  
322 323  
323 324  
324 325  
325 326  
... ... @@ -392,47 +393,95 @@
392 393  
393 394 #if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
394 395 static void serial_divs (int baudrate, unsigned long *pudiv,
395   - unsigned short *pbdiv )
  396 + unsigned short *pbdiv)
396 397 {
397   - sys_info_t sysinfo;
  398 + sys_info_t sysinfo;
398 399 unsigned long div; /* total divisor udiv * bdiv */
399 400 unsigned long umin; /* minimum udiv */
400   - unsigned short diff; /* smallest diff */
401   - unsigned long udiv; /* best udiv */
402   -
403   - unsigned short idiff; /* current diff */
404   - unsigned short ibdiv; /* current bdiv */
  401 + unsigned short diff; /* smallest diff */
  402 + unsigned long udiv; /* best udiv */
  403 + unsigned short idiff; /* current diff */
  404 + unsigned short ibdiv; /* current bdiv */
405 405 unsigned long i;
406   - unsigned long est; /* current estimate */
  406 + unsigned long est; /* current estimate */
407 407  
408   - get_sys_info( &sysinfo );
  408 + get_sys_info(&sysinfo);
409 409  
410   - udiv = 32; /* Assume lowest possible serial clk */
411   - div = sysinfo.freqPLB/(16*baudrate); /* total divisor */
412   - umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */
413   - diff = 32; /* highest possible */
  410 + udiv = 32; /* Assume lowest possible serial clk */
  411 + div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
  412 + umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
  413 + diff = 32; /* highest possible */
414 414  
415 415 /* i is the test udiv value -- start with the largest
416 416 * possible (32) to minimize serial clock and constrain
417 417 * search to umin.
418 418 */
419   - for( i = 32; i > umin; i-- ){
420   - ibdiv = div/i;
  419 + for (i = 32; i > umin; i--) {
  420 + ibdiv = div / i;
421 421 est = i * ibdiv;
422 422 idiff = (est > div) ? (est-div) : (div-est);
423   - if( idiff == 0 ){
  423 + if (idiff == 0) {
424 424 udiv = i;
425 425 break; /* can't do better */
426   - }
427   - else if( idiff < diff ){
  426 + } else if (idiff < diff) {
428 427 udiv = i; /* best so far */
429 428 diff = idiff; /* update lowest diff*/
430 429 }
431 430 }
432 431  
433 432 *pudiv = udiv;
434   - *pbdiv = div/udiv;
  433 + *pbdiv = div / udiv;
  434 +}
435 435  
  436 +#elif defined(CONFIG_405EZ)
  437 +
  438 +static void serial_divs (int baudrate, unsigned long *pudiv,
  439 + unsigned short *pbdiv)
  440 +{
  441 + sys_info_t sysinfo;
  442 + unsigned long div; /* total divisor udiv * bdiv */
  443 + unsigned long umin; /* minimum udiv */
  444 + unsigned short diff; /* smallest diff */
  445 + unsigned long udiv; /* best udiv */
  446 + unsigned short idiff; /* current diff */
  447 + unsigned short ibdiv; /* current bdiv */
  448 + unsigned long i;
  449 + unsigned long est; /* current estimate */
  450 + unsigned long plloutb;
  451 + u32 reg;
  452 +
  453 + get_sys_info(&sysinfo);
  454 +
  455 + plloutb = ((CONFIG_SYS_CLK_FREQ * sysinfo.pllFwdDiv * sysinfo.pllFbkDiv)
  456 + / sysinfo.pllFwdDivB);
  457 + udiv = 256; /* Assume lowest possible serial clk */
  458 + div = plloutb / (16 * baudrate); /* total divisor */
  459 + umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
  460 + diff = 256; /* highest possible */
  461 +
  462 + /* i is the test udiv value -- start with the largest
  463 + * possible (256) to minimize serial clock and constrain
  464 + * search to umin.
  465 + */
  466 + for (i = 256; i > umin; i--) {
  467 + ibdiv = div / i;
  468 + est = i * ibdiv;
  469 + idiff = (est > div) ? (est-div) : (div-est);
  470 + if (idiff == 0) {
  471 + udiv = i;
  472 + break; /* can't do better */
  473 + } else if (idiff < diff) {
  474 + udiv = i; /* best so far */
  475 + diff = idiff; /* update lowest diff*/
  476 + }
  477 + }
  478 +
  479 + *pudiv = udiv;
  480 + mfcpr(cprperd0, reg);
  481 + reg &= ~0x0000ffff;
  482 + reg |= ((udiv - 0) << 8) | (udiv - 0);
  483 + mtcpr(cprperd0, reg);
  484 + *pbdiv = div / udiv;
436 485 }
437 486 #endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */
438 487  
... ... @@ -518,6 +567,10 @@
518 567 unsigned short bdiv;
519 568 volatile char val;
520 569  
  570 +#if defined(CONFIG_405EZ)
  571 + serial_divs(gd->baudrate, &udiv, &bdiv);
  572 + clk = tmp = reg = 0;
  573 +#else
521 574 #ifdef CONFIG_405EP
522 575 reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
523 576 clk = gd->cpu_clk;
524 577  
... ... @@ -548,9 +601,9 @@
548 601 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
549 602 mtdcr (cntrl0, reg);
550 603 #endif /* CONFIG_405EP */
551   -
552 604 tmp = gd->baudrate * udiv * 16;
553 605 bdiv = (clk + tmp / 2) / tmp;
  606 +#endif /* CONFIG_405EZ */
554 607  
555 608 out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */
556 609 out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */
... ... @@ -767,11 +767,119 @@
767 767 return val;
768 768 }
769 769  
  770 +#elif defined(CONFIG_405EZ)
  771 +void get_sys_info (PPC405_SYS_INFO * sysInfo)
  772 +{
  773 + unsigned long cpr_plld;
  774 + unsigned long cpr_primad;
  775 + unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ/1000);
  776 + unsigned long primad_cpudv;
  777 + unsigned long m;
  778 +
  779 + /*
  780 + * Read PLL Mode registers
  781 + */
  782 + mfcpr(cprplld, cpr_plld);
  783 +
  784 + /*
  785 + * Determine forward divider A
  786 + */
  787 + sysInfo->pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16);
  788 +
  789 + /*
  790 + * Determine forward divider B (should be equal to A)
  791 + */
  792 + sysInfo->pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8);
  793 + if (sysInfo->pllFwdDivB == 0) {
  794 + sysInfo->pllFwdDivB = 8;
  795 + }
  796 +
  797 + /*
  798 + * Determine FBK_DIV.
  799 + */
  800 + sysInfo->pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
  801 + if (sysInfo->pllFbkDiv == 0) {
  802 + sysInfo->pllFbkDiv = 256;
  803 + }
  804 +
  805 + /*
  806 + * Read CPR_PRIMAD register
  807 + */
  808 + mfcpr(cprprimad, cpr_primad);
  809 + /*
  810 + * Determine PLB_DIV.
  811 + */
  812 + sysInfo->pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16);
  813 + if (sysInfo->pllPlbDiv == 0) {
  814 + sysInfo->pllPlbDiv = 16;
  815 + }
  816 +
  817 + /*
  818 + * Determine EXTBUS_DIV.
  819 + */
  820 + sysInfo->pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK);
  821 + if (sysInfo->pllExtBusDiv == 0) {
  822 + sysInfo->pllExtBusDiv = 16;
  823 + }
  824 +
  825 + /*
  826 + * Determine OPB_DIV.
  827 + */
  828 + sysInfo->pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8);
  829 + if (sysInfo->pllOpbDiv == 0) {
  830 + sysInfo->pllOpbDiv = 16;
  831 + }
  832 +
  833 + /*
  834 + * Determine the M factor
  835 + */
  836 + m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;
  837 +
  838 + /*
  839 + * Determine VCO clock frequency
  840 + */
  841 + sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
  842 + (unsigned long long)sysClkPeriodPs;
  843 +
  844 + /*
  845 + * Determine CPU clock frequency
  846 + */
  847 + primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
  848 + if (primad_cpudv == 0) {
  849 + primad_cpudv = 16;
  850 + }
  851 +
  852 + sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / primad_cpudv;
  853 +
  854 + /*
  855 + * Determine PLB clock frequency
  856 + */
  857 + sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / sysInfo->pllPlbDiv;
  858 +}
  859 +
  860 +/********************************************
  861 + * get_OPB_freq
  862 + * return OPB bus freq in Hz
  863 + *********************************************/
  864 +ulong get_OPB_freq (void)
  865 +{
  866 + ulong val = 0;
  867 +
  868 + PPC405_SYS_INFO sys_info;
  869 +
  870 + get_sys_info (&sys_info);
  871 + val = (CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / sys_info.pllOpbDiv;
  872 +
  873 + return val;
  874 +}
  875 +
770 876 #endif
771 877  
772 878 int get_clocks (void)
773 879 {
774   -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405) || defined(CONFIG_405EP)
  880 +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
  881 + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
  882 + defined(CONFIG_440) || defined(CONFIG_405)
775 883 sys_info_t sys_info;
776 884  
777 885 get_sys_info (&sys_info);
... ... @@ -796,7 +904,9 @@
796 904 {
797 905 ulong val;
798 906  
799   -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_440) || defined(CONFIG_405EP)
  907 +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
  908 + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
  909 + defined(CONFIG_440) || defined(CONFIG_405)
800 910 sys_info_t sys_info;
801 911  
802 912 get_sys_info (&sys_info);
... ... @@ -699,7 +699,9 @@
699 699 #endif /* CONFIG_IOP480 */
700 700  
701 701 /*****************************************************************************/
702   -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_405EP)
  702 +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
  703 + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
  704 + defined(CONFIG_405)
703 705 /*----------------------------------------------------------------------- */
704 706 /* Clear and set up some registers. */
705 707 /*----------------------------------------------------------------------- */
706 708  
... ... @@ -727,13 +729,13 @@
727 729 /*----------------------------------------------------------------------- */
728 730 /* Enable two 128MB cachable regions. */
729 731 /*----------------------------------------------------------------------- */
730   - addis r4,r0,0x8000
731   - addi r4,r4,0x0001
  732 + lis r4,0x8000
  733 + ori r4,r4,0x0001
732 734 mticcr r4 /* instruction cache */
733 735 isync
734 736  
735   - addis r4,r0,0x0000
736   - addi r4,r4,0x0000
  737 + lis r4,0x0000
  738 + ori r4,r4,0x0000
737 739 mtdccr r4 /* data cache */
738 740  
739 741 #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
740 742  
... ... @@ -755,7 +757,71 @@
755 757 #endif /* CONFIG_405EP */
756 758  
757 759 #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
  760 +/* test-only... (clean up later when NAND booting is supported) */
  761 +#if defined(CONFIG_405EZ)
758 762 /********************************************************************
  763 + * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
  764 + *******************************************************************/
  765 + /*
  766 + * We can map the OCM on the PLB3, so map it at
  767 + * CFG_OCM_DATA_ADDR + 0x8000
  768 + */
  769 + lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
  770 + ori r3,r3,CFG_OCM_DATA_ADDR@l
  771 + ori r3,r3,0x8270 /* 32K Offset, 16K for Bank 1, R/W/Enable */
  772 + mtdcr ocmplb3cr1,r3 /* Set PLB Access */
  773 + ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
  774 + mtdcr ocmplb3cr2,r3 /* Set PLB Access */
  775 + isync
  776 +
  777 + lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
  778 + ori r3,r3,CFG_OCM_DATA_ADDR@l
  779 + ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
  780 + mtdcr ocmdscr1, r3 /* Set Data Side */
  781 + mtdcr ocmiscr1, r3 /* Set Instruction Side */
  782 + ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
  783 + mtdcr ocmdscr2, r3 /* Set Data Side */
  784 + mtdcr ocmiscr2, r3 /* Set Instruction Side */
  785 + addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
  786 + mtdcr ocmdsisdpc,r4
  787 +
  788 + isync
  789 +
  790 +#if defined(CONFIG_NAND_SPL)
  791 + /*
  792 + * 405EZ can boot from NAND Flash.
  793 + * If we are booting the SPL (Pre-loader), copy code from
  794 + * the mapped 4K NAND Flash to the OCM
  795 + */
  796 + li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
  797 + mtctr r4
  798 + lis r2,CFG_NAND_BOOT_SPL_SRC@h
  799 + ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
  800 + lis r3,CFG_NAND_BOOT_SPL_DST@h
  801 + ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
  802 +spl_loop:
  803 + lwzu r4,4(r2)
  804 + stwu r4,4(r3)
  805 + bdnz spl_loop
  806 +
  807 + /*
  808 + * Jump to code in OCM Ram
  809 + */
  810 + bl 00f
  811 +00: mflr r10
  812 + lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
  813 + ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
  814 + sub r10,r10,r3
  815 + addi r10,r10,28
  816 + mtlr r10
  817 + blr
  818 +start_ram:
  819 + sync
  820 + isync
  821 +#endif
  822 +#else
  823 +/* ...test-only */
  824 + /********************************************************************
759 825 * Setup OCM - On Chip Memory
760 826 *******************************************************************/
761 827 /* Setup OCM */
... ... @@ -774,6 +840,7 @@
774 840 addis r4, 0, 0xC000 /* OCM data area enabled */
775 841 mtdcr ocmdscntl, r4
776 842 isync
  843 +#endif /* CONFIG_405EZ */
777 844 #endif
778 845  
779 846 /*----------------------------------------------------------------------- */
cpu/ppc4xx/usb_ohci.c
Diff comments   View file @ e01bd21
... ... @@ -76,7 +76,7 @@
76 76 #define m16_swap(x) swap_16(x)
77 77 #define m32_swap(x) swap_32(x)
78 78  
79   -#if defined(CONFIG_440EP) || defined(CONFIG_440EPX)
  79 +#if defined(CONFIG_405EZ) || defined(CONFIG_440EP) || defined(CONFIG_440EPX)
80 80 #define ohci_cpu_to_le16(x) (x)
81 81 #define ohci_cpu_to_le32(x) (x)
82 82 #else
... ... @@ -1601,7 +1601,7 @@
1601 1601 gohci.irq = -1;
1602 1602 #if defined(CONFIG_440EP)
1603 1603 gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000);
1604   -#elif defined(CONFIG_440EPX)
  1604 +#elif defined(CONFIG_440EPX) || defined(CFG_USB_HOST)
1605 1605 gohci.regs = (struct ohci_regs *)(CFG_USB_HOST);
1606 1606 #endif
1607 1607  
1608 1608  
... ... @@ -1625,8 +1625,10 @@
1625 1625 ohci_inited = 1;
1626 1626 urb_finished = 1;
1627 1627  
  1628 +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX)
1628 1629 /* init the device driver */
1629 1630 usb_dev_init();
  1631 +#endif
1630 1632  
1631 1633 return 0;
1632 1634 }
... ... @@ -231,6 +231,47 @@
231 231  
232 232 #else /* !defined(CONFIG_440) */
233 233  
  234 +#if defined(CONFIG_405EZ)
  235 +#define VECNUM_D0 0 /* DMA channel 0 */
  236 +#define VECNUM_D1 1 /* DMA channel 1 */
  237 +#define VECNUM_D2 2 /* DMA channel 2 */
  238 +#define VECNUM_D3 3 /* DMA channel 3 */
  239 +#define VECNUM_1588 4 /* IEEE 1588 network synchronization */
  240 +#define VECNUM_U0 5 /* UART0 */
  241 +#define VECNUM_U1 6 /* UART1 */
  242 +#define VECNUM_CAN0 7 /* CAN 0 */
  243 +#define VECNUM_CAN1 8 /* CAN 1 */
  244 +#define VECNUM_SPI 9 /* SPI */
  245 +#define VECNUM_IIC0 10 /* I2C */
  246 +#define VECNUM_CHT0 11 /* Chameleon timer high pri interrupt */
  247 +#define VECNUM_CHT1 12 /* Chameleon timer high pri interrupt */
  248 +#define VECNUM_USBH1 13 /* USB Host 1 */
  249 +#define VECNUM_USBH2 14 /* USB Host 2 */
  250 +#define VECNUM_USBDEV 15 /* USB Device */
  251 +#define VECNUM_ETH0 16 /* 10/100 Ethernet interrupt status */
  252 +#define VECNUM_EWU0 17 /* Ethernet wakeup sequence detected */
  253 +
  254 +#define VECNUM_MADMAL 18 /* Logical OR of following MadMAL int */
  255 +#define VECNUM_MS 18 /* MAL_SERR_INT */
  256 +#define VECNUM_TXDE 18 /* MAL_TXDE_INT */
  257 +#define VECNUM_RXDE 18 /* MAL_RXDE_INT */
  258 +
  259 +#define VECNUM_MTE 19 /* MAL TXEOB */
  260 +#define VECNUM_MTE1 20 /* MAL TXEOB1 */
  261 +#define VECNUM_MRE 21 /* MAL RXEOB */
  262 +#define VECNUM_NAND 22 /* NAND Flash controller */
  263 +#define VECNUM_ADC 23 /* ADC */
  264 +#define VECNUM_DAC 24 /* DAC */
  265 +#define VECNUM_OPB2PLB 25 /* OPB to PLB bridge interrupt */
  266 +#define VECNUM_RESERVED0 26 /* Reserved */
  267 +#define VECNUM_EIR0 27 /* External interrupt 0 */
  268 +#define VECNUM_EIR1 28 /* External interrupt 1 */
  269 +#define VECNUM_EIR2 29 /* External interrupt 2 */
  270 +#define VECNUM_EIR3 30 /* External interrupt 3 */
  271 +#define VECNUM_EIR4 31 /* External interrupt 4 */
  272 +
  273 +#else /* !CONFIG_405EZ */
  274 +
234 275 #define VECNUM_U0 0 /* UART0 */
235 276 #define VECNUM_U1 1 /* UART1 */
236 277 #define VECNUM_D0 5 /* DMA channel 0 */
... ... @@ -251,6 +292,7 @@
251 292 #define VECNUM_EIR4 29 /* External interrupt 4 */
252 293 #define VECNUM_EIR5 30 /* External interrupt 5 */
253 294 #define VECNUM_EIR6 31 /* External interrupt 6 */
  295 +#endif /* defined(CONFIG_405EZ) */
254 296  
255 297 #endif /* defined(CONFIG_440) */
256 298  
include/asm-ppc/processor.h
Diff comments   View file @ e01bd21
... ... @@ -298,6 +298,10 @@
298 298 #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
299 299 #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
300 300 #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
  301 +#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
  302 +#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
  303 +#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
  304 +#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
301 305 #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
302 306 #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
303 307 #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
... ... @@ -529,6 +533,10 @@
529 533 #define SPRG1 SPRN_SPRG1
530 534 #define SPRG2 SPRN_SPRG2
531 535 #define SPRG3 SPRN_SPRG3
  536 +#define SPRG4 SPRN_SPRG4
  537 +#define SPRG5 SPRN_SPRG5
  538 +#define SPRG6 SPRN_SPRG6
  539 +#define SPRG7 SPRN_SPRG7
532 540 #define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
533 541 #define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
534 542 #define SVR SPRN_SVR /* System Version Register */
... ... @@ -731,6 +739,7 @@
731 739 #define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */
732 740 #define PVR_405EP_RA 0x51210950
733 741 #define PVR_405GPR_RB 0x50910951
  742 +#define PVR_405EZ_RA 0x41511460
734 743 #define PVR_440GP_RB 0x40120440
735 744 #define PVR_440GP_RC 0x40120481
736 745 #define PVR_440EP_RA 0x42221850
include/asm-ppc/u-boot.h
Diff comments   View file @ e01bd21
... ... @@ -83,6 +83,7 @@
83 83 defined(CONFIG_405GP) || \
84 84 defined(CONFIG_405CR) || \
85 85 defined(CONFIG_405EP) || \
  86 + defined(CONFIG_405EZ) || \
86 87 defined(CONFIG_440)
87 88 unsigned char bi_s_version[4]; /* Version of this structure */
88 89 unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */
... ... @@ -107,7 +108,8 @@
107 108 unsigned char bi_enet3addr[6];
108 109 #endif
109 110  
110   -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \
  111 +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
  112 + defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
111 113 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
112 114 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
113 115 unsigned int bi_opbfreq; /* OPB clock in Hz */
... ... @@ -117,6 +117,48 @@
117 117 /*-----------------------------------------------------------------------------+
118 118 | Universal interrupt controller interrupts
119 119 +-----------------------------------------------------------------------------*/
  120 +#if defined(CONFIG_405EZ)
  121 +#define UIC_DMA0 0x80000000 /* DMA chan. 0 */
  122 +#define UIC_DMA1 0x40000000 /* DMA chan. 1 */
  123 +#define UIC_DMA2 0x20000000 /* DMA chan. 2 */
  124 +#define UIC_DMA3 0x10000000 /* DMA chan. 3 */
  125 +#define UIC_1588 0x08000000 /* IEEE 1588 network synchronization */
  126 +#define UIC_UART0 0x04000000 /* UART 0 */
  127 +#define UIC_UART1 0x02000000 /* UART 1 */
  128 +#define UIC_CAN0 0x01000000 /* CAN 0 */
  129 +#define UIC_CAN1 0x00800000 /* CAN 1 */
  130 +#define UIC_SPI 0x00400000 /* SPI */
  131 +#define UIC_IIC 0x00200000 /* IIC */
  132 +#define UIC_CHT0 0x00100000 /* Chameleon timer high pri interrupt */
  133 +#define UIC_CHT1 0x00080000 /* Chameleon timer high pri interrupt */
  134 +#define UIC_USBH1 0x00040000 /* USB Host 1 */
  135 +#define UIC_USBH2 0x00020000 /* USB Host 2 */
  136 +#define UIC_USBDEV 0x00010000 /* USB Device */
  137 +#define UIC_ENET 0x00008000 /* Ethernet interrupt status */
  138 +#define UIC_ENET1 0x00008000 /* dummy define */
  139 +#define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */
  140 +
  141 +#define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */
  142 +#define UIC_MAL_SERR 0x00002000 /* MAL SERR */
  143 +#define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */
  144 +#define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */
  145 +
  146 +#define UIC_MAL_TXEOB 0x00001000 /* MAL TXEOB */
  147 +#define UIC_MAL_TXEOB1 0x00000800 /* MAL TXEOB1 */
  148 +#define UIC_MAL_RXEOB 0x00000400 /* MAL RXEOB */
  149 +#define UIC_NAND 0x00000200 /* NAND Flash controller */
  150 +#define UIC_ADC 0x00000100 /* ADC */
  151 +#define UIC_DAC 0x00000080 /* DAC */
  152 +#define UIC_OPB2PLB 0x00000040 /* OPB to PLB bridge interrupt */
  153 +#define UIC_RESERVED0 0x00000020 /* Reserved */
  154 +#define UIC_EXT0 0x00000010 /* External interrupt 0 */
  155 +#define UIC_EXT1 0x00000008 /* External interrupt 1 */
  156 +#define UIC_EXT2 0x00000004 /* External interrupt 2 */
  157 +#define UIC_EXT3 0x00000002 /* External interrupt 3 */
  158 +#define UIC_EXT4 0x00000001 /* External interrupt 4 */
  159 +
  160 +#else /* !defined(CONFIG_405EZ) */
  161 +
120 162 #define UIC_UART0 0x80000000 /* UART 0 */
121 163 #define UIC_UART1 0x40000000 /* UART 1 */
122 164 #define UIC_IIC 0x20000000 /* IIC */
... ... @@ -144,6 +186,7 @@
144 186 #define UIC_EXT4 0x00000004 /* External interrupt 4 */
145 187 #define UIC_EXT5 0x00000002 /* External interrupt 5 */
146 188 #define UIC_EXT6 0x00000001 /* External interrupt 6 */
  189 +#endif /* defined(CONFIG_405EZ) */
147 190  
148 191 /******************************************************************************
149 192 * SDRAM Controller
... ... @@ -496,6 +539,325 @@
496 539 */
497 540 #define VCO_MIN 500
498 541 #define VCO_MAX 1000
  542 +#elif defined(CONFIG_405EZ)
  543 +/******************************************************************************
  544 + * SDR Registers
  545 + ******************************************************************************/
  546 +#define SDR_DCR_BASE 0x0E
  547 +#define sdrcfga (SDR_DCR_BASE+0x0) /* ADDR */
  548 +#define sdrcfgd (SDR_DCR_BASE+0x1) /* Data */
  549 +
  550 +#define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data)
  551 +#define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd)
  552 +
  553 +#define sdrnand0 0x4000
  554 +#define sdrultra0 0x4040
  555 +#define sdrultra1 0x4050
  556 +#define sdricintstat 0x4510
  557 +
  558 +#define SDR_NAND0_NDEN 0x80000000
  559 +
  560 +#define SDR_ULTRA0_NDGPIOBP 0x80000000
  561 +#define SDR_ULTRA0_CSN_MASK 0x78000000
  562 +#define SDR_ULTRA0_CSNSEL0 0x40000000
  563 +#define SDR_ULTRA0_CSNSEL1 0x20000000
  564 +#define SDR_ULTRA0_CSNSEL2 0x10000000
  565 +#define SDR_ULTRA0_CSNSEL3 0x08000000
  566 +
  567 +#define SDR_ULTRA1_LEDNENABLE 0x40000000
  568 +
  569 +#define SDR_ICRX_STAT 0x80000000
  570 +#define SDR_ICTX0_STAT 0x40000000
  571 +#define SDR_ICTX1_STAT 0x20000000
  572 +
  573 +/******************************************************************************
  574 + * Control
  575 + ******************************************************************************/
  576 +#define CNTRL_DCR_BASE 0x0C
  577 +#define cprcfga (CNTRL_DCR_BASE+0x0) /* CPR addr reg */
  578 +#define cprcfgd (CNTRL_DCR_BASE+0x1) /* CPR data reg */
  579 +
  580 +/* CPR Registers */
  581 +#define cprclkupd 0x020 /* CPR_CLKUPD */
  582 +#define cprpllc 0x040 /* CPR_PLLC */
  583 +#define cprplld 0x060 /* CPR_PLLD */
  584 +#define cprprimad 0x080 /* CPR_PRIMAD */
  585 +#define cprperd0 0x0e0 /* CPR_PERD0 */
  586 +#define cprperd1 0x0e1 /* CPR_PERD1 */
  587 +#define cprperc0 0x180 /* CPR_PERC0 */
  588 +#define cprmisc0 0x181 /* CPR_MISC0 */
  589 +#define cprmisc1 0x182 /* CPR_MISC1 */
  590 +
  591 +/*
  592 + * Macro for accessing the indirect CPR register
  593 + */
  594 +#define mtcpr(reg, data) mtdcr(cprcfga,reg);mtdcr(cprcfgd,data)
  595 +#define mfcpr(reg, data) mtdcr(cprcfga,reg);data = mfdcr(cprcfgd)
  596 +
  597 +#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
  598 +#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
  599 +#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
  600 +
  601 +#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
  602 +#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
  603 +#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
  604 +
  605 +#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
  606 +#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
  607 +#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
  608 +#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
  609 +
  610 +#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
  611 +#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
  612 +#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
  613 +#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
  614 +
  615 +#if 0 /* Deprecated */
  616 +#define CNTRL_DCR_BASE 0x0f0
  617 +#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
  618 +#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */
  619 +#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
  620 +#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
  621 +#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */
  622 +#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */
  623 +
  624 +#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
  625 +#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
  626 +#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
  627 +#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
  628 +#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
  629 +#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
  630 +#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
  631 +#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
  632 +#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
  633 +#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
  634 +
  635 +/* Bit definitions */
  636 +#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
  637 +#define PLLMR0_CPU_DIV_BYPASS 0x00000000
  638 +#define PLLMR0_CPU_DIV_2 0x00100000
  639 +#define PLLMR0_CPU_DIV_3 0x00200000
  640 +#define PLLMR0_CPU_DIV_4 0x00300000
  641 +
  642 +#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
  643 +#define PLLMR0_CPU_PLB_DIV_1 0x00000000
  644 +#define PLLMR0_CPU_PLB_DIV_2 0x00010000
  645 +#define PLLMR0_CPU_PLB_DIV_3 0x00020000
  646 +#define PLLMR0_CPU_PLB_DIV_4 0x00030000
  647 +
  648 +#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
  649 +#define PLLMR0_OPB_PLB_DIV_1 0x00000000
  650 +#define PLLMR0_OPB_PLB_DIV_2 0x00001000
  651 +#define PLLMR0_OPB_PLB_DIV_3 0x00002000
  652 +#define PLLMR0_OPB_PLB_DIV_4 0x00003000
  653 +
  654 +#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
  655 +#define PLLMR0_EXB_PLB_DIV_2 0x00000000
  656 +#define PLLMR0_EXB_PLB_DIV_3 0x00000100
  657 +#define PLLMR0_EXB_PLB_DIV_4 0x00000200
  658 +#define PLLMR0_EXB_PLB_DIV_5 0x00000300
  659 +
  660 +#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
  661 +#define PLLMR0_MAL_PLB_DIV_1 0x00000000
  662 +#define PLLMR0_MAL_PLB_DIV_2 0x00000010
  663 +#define PLLMR0_MAL_PLB_DIV_3 0x00000020
  664 +#define PLLMR0_MAL_PLB_DIV_4 0x00000030
  665 +
  666 +#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
  667 +#define PLLMR0_PCI_PLB_DIV_1 0x00000000
  668 +#define PLLMR0_PCI_PLB_DIV_2 0x00000001
  669 +#define PLLMR0_PCI_PLB_DIV_3 0x00000002
  670 +#define PLLMR0_PCI_PLB_DIV_4 0x00000003
  671 +
  672 +#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
  673 +#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
  674 +#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
  675 +#define PLLMR1_FBMUL_DIV_16 0x00000000
  676 +#define PLLMR1_FBMUL_DIV_1 0x00100000
  677 +#define PLLMR1_FBMUL_DIV_2 0x00200000
  678 +#define PLLMR1_FBMUL_DIV_3 0x00300000
  679 +#define PLLMR1_FBMUL_DIV_4 0x00400000
  680 +#define PLLMR1_FBMUL_DIV_5 0x00500000
  681 +#define PLLMR1_FBMUL_DIV_6 0x00600000
  682 +#define PLLMR1_FBMUL_DIV_7 0x00700000
  683 +#define PLLMR1_FBMUL_DIV_8 0x00800000
  684 +#define PLLMR1_FBMUL_DIV_9 0x00900000
  685 +#define PLLMR1_FBMUL_DIV_10 0x00A00000
  686 +#define PLLMR1_FBMUL_DIV_11 0x00B00000
  687 +#define PLLMR1_FBMUL_DIV_12 0x00C00000
  688 +#define PLLMR1_FBMUL_DIV_13 0x00D00000
  689 +#define PLLMR1_FBMUL_DIV_14 0x00E00000
  690 +#define PLLMR1_FBMUL_DIV_15 0x00F00000
  691 +
  692 +#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
  693 +#define PLLMR1_FWDVA_DIV_8 0x00000000
  694 +#define PLLMR1_FWDVA_DIV_7 0x00010000
  695 +#define PLLMR1_FWDVA_DIV_6 0x00020000
  696 +#define PLLMR1_FWDVA_DIV_5 0x00030000
  697 +#define PLLMR1_FWDVA_DIV_4 0x00040000
  698 +#define PLLMR1_FWDVA_DIV_3 0x00050000
  699 +#define PLLMR1_FWDVA_DIV_2 0x00060000
  700 +#define PLLMR1_FWDVA_DIV_1 0x00070000
  701 +#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
  702 +#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
  703 +
  704 +/* Defines for CPC0_EPRCSR register */
  705 +#define CPC0_EPRCSR_E0NFE 0x80000000
  706 +#define CPC0_EPRCSR_E1NFE 0x40000000
  707 +#define CPC0_EPRCSR_E1RPP 0x00000080
  708 +#define CPC0_EPRCSR_E0RPP 0x00000040
  709 +#define CPC0_EPRCSR_E1ERP 0x00000020
  710 +#define CPC0_EPRCSR_E0ERP 0x00000010
  711 +#define CPC0_EPRCSR_E1PCI 0x00000002
  712 +#define CPC0_EPRCSR_E0PCI 0x00000001
  713 +
  714 +/* Defines for CPC0_BOOR Register */
  715 +#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
  716 +
  717 +/* Defines for CPC0_PLLMR1 Register fields */
  718 +#define PLL_ACTIVE 0x80000000
  719 +#define CPC0_PLLMR1_SSCS 0x80000000
  720 +#define PLL_RESET 0x40000000
  721 +#define CPC0_PLLMR1_PLLR 0x40000000
  722 + /* Feedback multiplier */
  723 +#define PLL_FBKDIV 0x00F00000
  724 +#define CPC0_PLLMR1_FBDV 0x00F00000
  725 +#define PLL_FBKDIV_16 0x00000000
  726 +#define PLL_FBKDIV_1 0x00100000
  727 +#define PLL_FBKDIV_2 0x00200000
  728 +#define PLL_FBKDIV_3 0x00300000
  729 +#define PLL_FBKDIV_4 0x00400000
  730 +#define PLL_FBKDIV_5 0x00500000
  731 +#define PLL_FBKDIV_6 0x00600000
  732 +#define PLL_FBKDIV_7 0x00700000
  733 +#define PLL_FBKDIV_8 0x00800000
  734 +#define PLL_FBKDIV_9 0x00900000
  735 +#define PLL_FBKDIV_10 0x00A00000
  736 +#define PLL_FBKDIV_11 0x00B00000
  737 +#define PLL_FBKDIV_12 0x00C00000
  738 +#define PLL_FBKDIV_13 0x00D00000
  739 +#define PLL_FBKDIV_14 0x00E00000
  740 +#define PLL_FBKDIV_15 0x00F00000
  741 + /* Forward A divisor */
  742 +#define PLL_FWDDIVA 0x00070000
  743 +#define CPC0_PLLMR1_FWDVA 0x00070000
  744 +#define PLL_FWDDIVA_8 0x00000000
  745 +#define PLL_FWDDIVA_7 0x00010000
  746 +#define PLL_FWDDIVA_6 0x00020000
  747 +#define PLL_FWDDIVA_5 0x00030000
  748 +#define PLL_FWDDIVA_4 0x00040000
  749 +#define PLL_FWDDIVA_3 0x00050000
  750 +#define PLL_FWDDIVA_2 0x00060000
  751 +#define PLL_FWDDIVA_1 0x00070000
  752 + /* Forward B divisor */
  753 +#define PLL_FWDDIVB 0x00007000
  754 +#define CPC0_PLLMR1_FWDVB 0x00007000
  755 +#define PLL_FWDDIVB_8 0x00000000
  756 +#define PLL_FWDDIVB_7 0x00001000
  757 +#define PLL_FWDDIVB_6 0x00002000
  758 +#define PLL_FWDDIVB_5 0x00003000
  759 +#define PLL_FWDDIVB_4 0x00004000
  760 +#define PLL_FWDDIVB_3 0x00005000
  761 +#define PLL_FWDDIVB_2 0x00006000
  762 +#define PLL_FWDDIVB_1 0x00007000
  763 + /* PLL tune bits */
  764 +#define PLL_TUNE_MASK 0x000003FF
  765 +#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
  766 +#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
  767 +#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
  768 +#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
  769 +#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
  770 +#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
  771 +#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
  772 +
  773 +/* Defines for CPC0_PLLMR0 Register fields */
  774 + /* CPU divisor */
  775 +#define PLL_CPUDIV 0x00300000
  776 +#define CPC0_PLLMR0_CCDV 0x00300000
  777 +#define PLL_CPUDIV_1 0x00000000
  778 +#define PLL_CPUDIV_2 0x00100000
  779 +#define PLL_CPUDIV_3 0x00200000
  780 +#define PLL_CPUDIV_4 0x00300000
  781 + /* PLB divisor */
  782 +#define PLL_PLBDIV 0x00030000
  783 +#define CPC0_PLLMR0_CBDV 0x00030000
  784 +#define PLL_PLBDIV_1 0x00000000
  785 +#define PLL_PLBDIV_2 0x00010000
  786 +#define PLL_PLBDIV_3 0x00020000
  787 +#define PLL_PLBDIV_4 0x00030000
  788 + /* OPB divisor */
  789 +#define PLL_OPBDIV 0x00003000
  790 +#define CPC0_PLLMR0_OPDV 0x00003000
  791 +#define PLL_OPBDIV_1 0x00000000
  792 +#define PLL_OPBDIV_2 0x00001000
  793 +#define PLL_OPBDIV_3 0x00002000
  794 +#define PLL_OPBDIV_4 0x00003000
  795 + /* EBC divisor */
  796 +#define PLL_EXTBUSDIV 0x00000300
  797 +#define CPC0_PLLMR0_EPDV 0x00000300
  798 +#define PLL_EXTBUSDIV_2 0x00000000
  799 +#define PLL_EXTBUSDIV_3 0x00000100
  800 +#define PLL_EXTBUSDIV_4 0x00000200
  801 +#define PLL_EXTBUSDIV_5 0x00000300
  802 + /* MAL divisor */
  803 +#define PLL_MALDIV 0x00000030
  804 +#define CPC0_PLLMR0_MPDV 0x00000030
  805 +#define PLL_MALDIV_1 0x00000000
  806 +#define PLL_MALDIV_2 0x00000010
  807 +#define PLL_MALDIV_3 0x00000020
  808 +#define PLL_MALDIV_4 0x00000030
  809 + /* PCI divisor */
  810 +#define PLL_PCIDIV 0x00000003
  811 +#define CPC0_PLLMR0_PPFD 0x00000003
  812 +#define PLL_PCIDIV_1 0x00000000
  813 +#define PLL_PCIDIV_2 0x00000001
  814 +#define PLL_PCIDIV_3 0x00000002
  815 +#define PLL_PCIDIV_4 0x00000003
  816 +
  817 +/*
  818 + *-------------------------------------------------------------------------------
  819 + * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
  820 + * assuming a 33.3MHz input clock to the 405EP.
  821 + *-------------------------------------------------------------------------------
  822 + */
  823 +#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
  824 + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
  825 + PLL_MALDIV_1 | PLL_PCIDIV_4)
  826 +#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
  827 + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
  828 + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  829 +#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
  830 + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
  831 + PLL_MALDIV_1 | PLL_PCIDIV_4)
  832 +#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
  833 + PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
  834 + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  835 +#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
  836 + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
  837 + PLL_MALDIV_1 | PLL_PCIDIV_4)
  838 +#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
  839 + PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
  840 + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  841 +#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
  842 + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
  843 + PLL_MALDIV_1 | PLL_PCIDIV_4)
  844 +#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
  845 + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
  846 + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  847 +#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
  848 + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
  849 + PLL_MALDIV_1 | PLL_PCIDIV_2)
  850 +#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
  851 + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
  852 + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  853 +
  854 +/*
  855 + * PLL Voltage Controlled Oscillator (VCO) definitions
  856 + * Maximum and minimum values (in MHz) for correct PLL operation.
  857 + */
  858 +#define VCO_MIN 500
  859 +#define VCO_MAX 1000
  860 +#endif /* #if 0 */
499 861 #else /* #ifdef CONFIG_405EP */
500 862 /******************************************************************************
501 863 * Control
... ... @@ -578,6 +940,121 @@
578 940 /******************************************************************************
579 941 * Memory Access Layer
580 942 ******************************************************************************/
  943 +#if defined(CONFIG_405EZ)
  944 +#define MAL_DCR_BASE 0x380
  945 +#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
  946 +#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/
  947 +#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
  948 +#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
  949 +#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/
  950 +#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
  951 +#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
  952 +#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
  953 +/* 0x08-0x0F Reserved */
  954 +#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/
  955 +#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
  956 +#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
  957 +#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
  958 +/* 0x14-0x1F Reserved */
  959 +#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */
  960 +#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */
  961 +#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */
  962 +#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */
  963 +#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */
  964 +#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */
  965 +#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */
  966 +#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */
  967 +#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */
  968 +#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */
  969 +#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */
  970 +#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */
  971 +#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */
  972 +#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */
  973 +#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */
  974 +#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */
  975 +#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */
  976 +#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */
  977 +#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */
  978 +#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */
  979 +#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */
  980 +#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */
  981 +#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */
  982 +#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */
  983 +#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */
  984 +#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */
  985 +#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */
  986 +#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */
  987 +#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */
  988 +#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */
  989 +#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */
  990 +#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */
  991 +#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */
  992 +#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */
  993 +#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */
  994 +#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */
  995 +#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */
  996 +#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */
  997 +#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */
  998 +#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */
  999 +#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */
  1000 +#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */
  1001 +#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */
  1002 +#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */
  1003 +#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */
  1004 +#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */
  1005 +#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */
  1006 +#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */
  1007 +#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */
  1008 +#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */
  1009 +#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */
  1010 +#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */
  1011 +#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */
  1012 +#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */
  1013 +#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */
  1014 +#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */
  1015 +#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */
  1016 +#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */
  1017 +#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */
  1018 +#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */
  1019 +#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */
  1020 +#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */
  1021 +#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */
  1022 +#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */
  1023 +#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
  1024 +#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
  1025 +#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
  1026 +#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
  1027 +#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */
  1028 +#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */
  1029 +#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */
  1030 +#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */
  1031 +#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
  1032 +#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */
  1033 +#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */
  1034 +#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */
  1035 +#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */
  1036 +#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */
  1037 +#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */
  1038 +#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */
  1039 +#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
  1040 +#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */
  1041 +#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */
  1042 +#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */
  1043 +#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */
  1044 +#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */
  1045 +#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */
  1046 +#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */
  1047 +#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
  1048 +#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */
  1049 +#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */
  1050 +#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */
  1051 +#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */
  1052 +#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */
  1053 +#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */
  1054 +#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */
  1055 +
  1056 +#else /* !defined(CONFIG_405EZ) */
  1057 +
581 1058 #define MAL_DCR_BASE 0x180
582 1059 #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
583 1060 #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
... ... @@ -598,6 +1075,7 @@
598 1075 #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
599 1076 #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
600 1077 #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
  1078 +#endif /* defined(CONFIG_405EZ) */
601 1079  
602 1080 /*-----------------------------------------------------------------------------
603 1081 | IIC Register Offsets
604 1082  
605 1083  
606 1084  
... ... @@ -635,16 +1113,77 @@
635 1113 /******************************************************************************
636 1114 * On Chip Memory
637 1115 ******************************************************************************/
  1116 +#if defined(CONFIG_405EZ)
  1117 +#define OCM_DCR_BASE 0x020
  1118 +#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */
  1119 +#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */
  1120 +#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */
  1121 +#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */
  1122 +#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */
  1123 +#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */
  1124 +#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */
  1125 +#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */
  1126 +#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */
  1127 +#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */
  1128 +#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */
  1129 +#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */
  1130 +#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/
  1131 +#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/
  1132 +#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/
  1133 +#else
638 1134 #define OCM_DCR_BASE 0x018
639 1135 #define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
640 1136 #define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
641 1137 #define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
642 1138 #define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
  1139 +#endif /* CONFIG_405EZ */
643 1140  
644 1141 /******************************************************************************
645 1142 * GPIO macro register defines
646 1143 ******************************************************************************/
  1144 +#if defined(CONFIG_405EZ)
  1145 +/* Only the 405EZ has 2 GPIOs */
647 1146 #define GPIO_BASE 0xEF600700
  1147 +#define GPIO0_OR (GPIO_BASE+0x0)
  1148 +#define GPIO0_TCR (GPIO_BASE+0x4)
  1149 +#define GPIO0_OSRL (GPIO_BASE+0x8)
  1150 +#define GPIO0_OSRH (GPIO_BASE+0xC)
  1151 +#define GPIO0_TSRL (GPIO_BASE+0x10)
  1152 +#define GPIO0_TSRH (GPIO_BASE+0x14)
  1153 +#define GPIO0_ODR (GPIO_BASE+0x18)
  1154 +#define GPIO0_IR (GPIO_BASE+0x1C)
  1155 +#define GPIO0_RR1 (GPIO_BASE+0x20)
  1156 +#define GPIO0_RR2 (GPIO_BASE+0x24)
  1157 +#define GPIO0_RR3 (GPIO_BASE+0x28)
  1158 +#define GPIO0_ISR1L (GPIO_BASE+0x30)
  1159 +#define GPIO0_ISR1H (GPIO_BASE+0x34)
  1160 +#define GPIO0_ISR2L (GPIO_BASE+0x38)
  1161 +#define GPIO0_ISR2H (GPIO_BASE+0x3C)
  1162 +#define GPIO0_ISR3L (GPIO_BASE+0x40)
  1163 +#define GPIO0_ISR3H (GPIO_BASE+0x44)
  1164 +
  1165 +#define GPIO1_BASE 0xEF600800
  1166 +#define GPIO1_OR (GPIO1_BASE+0x0)
  1167 +#define GPIO1_TCR (GPIO1_BASE+0x4)
  1168 +#define GPIO1_OSRL (GPIO1_BASE+0x8)
  1169 +#define GPIO1_OSRH (GPIO1_BASE+0xC)
  1170 +#define GPIO1_TSRL (GPIO1_BASE+0x10)
  1171 +#define GPIO1_TSRH (GPIO1_BASE+0x14)
  1172 +#define GPIO1_ODR (GPIO1_BASE+0x18)
  1173 +#define GPIO1_IR (GPIO1_BASE+0x1C)
  1174 +#define GPIO1_RR1 (GPIO1_BASE+0x20)
  1175 +#define GPIO1_RR2 (GPIO1_BASE+0x24)
  1176 +#define GPIO1_RR3 (GPIO1_BASE+0x28)
  1177 +#define GPIO1_ISR1L (GPIO1_BASE+0x30)
  1178 +#define GPIO1_ISR1H (GPIO1_BASE+0x34)
  1179 +#define GPIO1_ISR2L (GPIO1_BASE+0x38)
  1180 +#define GPIO1_ISR2H (GPIO1_BASE+0x3C)
  1181 +#define GPIO1_ISR3L (GPIO1_BASE+0x40)
  1182 +#define GPIO1_ISR3H (GPIO1_BASE+0x44)
  1183 +
  1184 +#else /* !405EZ */
  1185 +
  1186 +#define GPIO_BASE 0xEF600700
648 1187 #define GPIO0_OR (GPIO_BASE+0x0)
649 1188 #define GPIO0_TCR (GPIO_BASE+0x4)
650 1189 #define GPIO0_OSRH (GPIO_BASE+0x8)
... ... @@ -660,6 +1199,7 @@
660 1199 #define GPIO0_ISR2H (GPIO_BASE+0x38)
661 1200 #define GPIO0_ISR2L (GPIO_BASE+0x3C)
662 1201  
  1202 +#endif /* CONFIG_405EZ */
663 1203  
664 1204 /*
665 1205 * Macro for accessing the indirect EBC register
include/ppc4xx_enet.h
Diff comments   View file @ e01bd21
... ... @@ -130,13 +130,13 @@
130 130  
131 131  
132 132 #if defined(CONFIG_440GX)
133   -#define EMAC_NUM_DEV 4
  133 +#define EMAC_NUM_DEV 4
134 134 #elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
135 135 defined(CONFIG_NET_MULTI) && \
136 136 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
137   -#define EMAC_NUM_DEV 2
  137 +#define EMAC_NUM_DEV 2
138 138 #else
139   -#define EMAC_NUM_DEV 1
  139 +#define EMAC_NUM_DEV 1
140 140 #endif
141 141  
142 142 #ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
143 143  
144 144  
145 145  
... ... @@ -153,16 +153,16 @@
153 153 /*ZMII Bridge Register addresses */
154 154 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
155 155 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
156   -#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
  156 +#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
157 157 #else
158   -#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
  158 +#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
159 159 #endif
160   -#define ZMII_FER (ZMII_BASE)
161   -#define ZMII_SSR (ZMII_BASE + 4)
162   -#define ZMII_SMIISR (ZMII_BASE + 8)
  160 +#define ZMII_FER (ZMII_BASE)
  161 +#define ZMII_SSR (ZMII_BASE + 4)
  162 +#define ZMII_SMIISR (ZMII_BASE + 8)
163 163  
164   -#define ZMII_RMII 0x22000000
165   -#define ZMII_MDI0 0x80000000
  164 +#define ZMII_RMII 0x22000000
  165 +#define ZMII_MDI0 0x80000000
166 166  
167 167 /* ZMII FER Register Bit Definitions */
168 168 #define ZMII_FER_DIS (0x0)
169 169  
170 170  
171 171  
172 172  
173 173  
174 174  
175 175  
... ... @@ -299,49 +299,41 @@
299 299 #if defined(CONFIG_440)
300 300 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
301 301 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
302   -#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
  302 +#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
303 303 #else
304   -#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
  304 +#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
305 305 #endif
306 306 #else
307   -#define EMAC_BASE 0xEF600800
  307 +#if defined(CONFIG_405EZ)
  308 +#define EMAC_BASE 0xEF600900
  309 +#else
  310 +#define EMAC_BASE 0xEF600800
308 311 #endif
  312 +#endif
309 313  
310   -#define EMAC_M0 (EMAC_BASE)
311   -#define EMAC_M1 (EMAC_BASE + 4)
312   -#define EMAC_TXM0 (EMAC_BASE + 8)
313   -#define EMAC_TXM1 (EMAC_BASE + 12)
314   -#define EMAC_RXM (EMAC_BASE + 16)
315   -#define EMAC_ISR (EMAC_BASE + 20)
316   -#define EMAC_IER (EMAC_BASE + 24)
317   -#define EMAC_IAH (EMAC_BASE + 28)
318   -#define EMAC_IAL (EMAC_BASE + 32)
319   -#define EMAC_VLAN_TPID_REG (EMAC_BASE + 36)
320   -#define EMAC_VLAN_TCI_REG (EMAC_BASE + 40)
  314 +#define EMAC_M0 (EMAC_BASE)
  315 +#define EMAC_M1 (EMAC_BASE + 4)
  316 +#define EMAC_TXM0 (EMAC_BASE + 8)
  317 +#define EMAC_TXM1 (EMAC_BASE + 12)
  318 +#define EMAC_RXM (EMAC_BASE + 16)
  319 +#define EMAC_ISR (EMAC_BASE + 20)
  320 +#define EMAC_IER (EMAC_BASE + 24)
  321 +#define EMAC_IAH (EMAC_BASE + 28)
  322 +#define EMAC_IAL (EMAC_BASE + 32)
321 323 #define EMAC_PAUSE_TIME_REG (EMAC_BASE + 44)
322   -#define EMAC_IND_HASH_1 (EMAC_BASE + 48)
323   -#define EMAC_IND_HASH_2 (EMAC_BASE + 52)
324   -#define EMAC_IND_HASH_3 (EMAC_BASE + 56)
325   -#define EMAC_IND_HASH_4 (EMAC_BASE + 60)
326   -#define EMAC_GRP_HASH_1 (EMAC_BASE + 64)
327   -#define EMAC_GRP_HASH_2 (EMAC_BASE + 68)
328   -#define EMAC_GRP_HASH_3 (EMAC_BASE + 72)
329   -#define EMAC_GRP_HASH_4 (EMAC_BASE + 76)
330   -#define EMAC_LST_SRC_LOW (EMAC_BASE + 80)
331   -#define EMAC_LST_SRC_HI (EMAC_BASE + 84)
332 324 #define EMAC_I_FRAME_GAP_REG (EMAC_BASE + 88)
333   -#define EMAC_STACR (EMAC_BASE + 92)
334   -#define EMAC_TRTR (EMAC_BASE + 96)
335   -#define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100)
  325 +#define EMAC_STACR (EMAC_BASE + 92)
  326 +#define EMAC_TRTR (EMAC_BASE + 96)
  327 +#define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100)
336 328  
337 329 /* bit definitions */
338 330 /* MODE REG 0 */
339   -#define EMAC_M0_RXI (0x80000000)
340   -#define EMAC_M0_TXI (0x40000000)
341   -#define EMAC_M0_SRST (0x20000000)
342   -#define EMAC_M0_TXE (0x10000000)
343   -#define EMAC_M0_RXE (0x08000000)
344   -#define EMAC_M0_WKE (0x04000000)
  331 +#define EMAC_M0_RXI (0x80000000)
  332 +#define EMAC_M0_TXI (0x40000000)
  333 +#define EMAC_M0_SRST (0x20000000)
  334 +#define EMAC_M0_TXE (0x10000000)
  335 +#define EMAC_M0_RXE (0x08000000)
  336 +#define EMAC_M0_WKE (0x04000000)
345 337  
346 338 /* on 440GX EMAC_MR1 has a different layout! */
347 339 #if defined(CONFIG_440GX) || \
348 340  
... ... @@ -351,23 +343,23 @@
351 343 #define EMAC_M1_FDE (0x80000000)
352 344 #define EMAC_M1_ILE (0x40000000)
353 345 #define EMAC_M1_VLE (0x20000000)
354   -#define EMAC_M1_EIFC (0x10000000)
355   -#define EMAC_M1_APP (0x08000000)
356   -#define EMAC_M1_RSVD (0x06000000)
357   -#define EMAC_M1_IST (0x01000000)
358   -#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
359   -#define EMAC_M1_MF_100MBPS (0x00400000)
360   -#define EMAC_M1_RFS_16K (0x00280000) /* ~4k for 512 byte */
361   -#define EMAC_M1_RFS_8K (0x00200000) /* ~4k for 512 byte */
362   -#define EMAC_M1_RFS_4K (0x00180000) /* ~4k for 512 byte */
363   -#define EMAC_M1_RFS_2K (0x00100000)
364   -#define EMAC_M1_RFS_1K (0x00080000)
365   -#define EMAC_M1_TX_FIFO_16K (0x00050000) /* 0's for 512 byte */
366   -#define EMAC_M1_TX_FIFO_8K (0x00040000)
367   -#define EMAC_M1_TX_FIFO_4K (0x00030000)
  346 +#define EMAC_M1_EIFC (0x10000000)
  347 +#define EMAC_M1_APP (0x08000000)
  348 +#define EMAC_M1_RSVD (0x06000000)
  349 +#define EMAC_M1_IST (0x01000000)
  350 +#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
  351 +#define EMAC_M1_MF_100MBPS (0x00400000)
  352 +#define EMAC_M1_RFS_16K (0x00280000) /* ~4k for 512 byte */
  353 +#define EMAC_M1_RFS_8K (0x00200000) /* ~4k for 512 byte */
  354 +#define EMAC_M1_RFS_4K (0x00180000) /* ~4k for 512 byte */
  355 +#define EMAC_M1_RFS_2K (0x00100000)
  356 +#define EMAC_M1_RFS_1K (0x00080000)
  357 +#define EMAC_M1_TX_FIFO_16K (0x00050000) /* 0's for 512 byte */
  358 +#define EMAC_M1_TX_FIFO_8K (0x00040000)
  359 +#define EMAC_M1_TX_FIFO_4K (0x00030000)
368 360 #define EMAC_M1_TX_FIFO_2K (0x00020000)
369   -#define EMAC_M1_TX_FIFO_1K (0x00010000)
370   -#define EMAC_M1_TR_MULTI (0x00008000) /* 0'x for single packet */
  361 +#define EMAC_M1_TX_FIFO_1K (0x00010000)
  362 +#define EMAC_M1_TR_MULTI (0x00008000) /* 0'x for single packet */
371 363 #define EMAC_M1_MWSW (0x00007000)
372 364 #define EMAC_M1_JUMBO_ENABLE (0x00000800)
373 365 #define EMAC_M1_IPPA (0x000007c0)
374 366  
375 367  
... ... @@ -378,34 +370,34 @@
378 370 #define EMAC_M1_RSVD1 (0x00000007)
379 371 #else /* defined(CONFIG_440GX) */
380 372 /* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
381   -#define EMAC_M1_FDE 0x80000000
382   -#define EMAC_M1_ILE 0x40000000
383   -#define EMAC_M1_VLE 0x20000000
384   -#define EMAC_M1_EIFC 0x10000000
385   -#define EMAC_M1_APP 0x08000000
386   -#define EMAC_M1_AEMI 0x02000000
387   -#define EMAC_M1_IST 0x01000000
388   -#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
389   -#define EMAC_M1_MF_100MBPS 0x00400000
390   -#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */
391   -#define EMAC_M1_RFS_2K 0x00200000
392   -#define EMAC_M1_RFS_1K 0x00100000
393   -#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */
394   -#define EMAC_M1_TX_FIFO_1K 0x00040000
395   -#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
396   -#define EMAC_M1_TR0_MULTI 0x00008000
397   -#define EMAC_M1_TR1_DEPEND 0x00004000
398   -#define EMAC_M1_TR1_MULTI 0x00002000
  373 +#define EMAC_M1_FDE 0x80000000
  374 +#define EMAC_M1_ILE 0x40000000
  375 +#define EMAC_M1_VLE 0x20000000
  376 +#define EMAC_M1_EIFC 0x10000000
  377 +#define EMAC_M1_APP 0x08000000
  378 +#define EMAC_M1_AEMI 0x02000000
  379 +#define EMAC_M1_IST 0x01000000
  380 +#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
  381 +#define EMAC_M1_MF_100MBPS 0x00400000
  382 +#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */
  383 +#define EMAC_M1_RFS_2K 0x00200000
  384 +#define EMAC_M1_RFS_1K 0x00100000
  385 +#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */
  386 +#define EMAC_M1_TX_FIFO_1K 0x00040000
  387 +#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
  388 +#define EMAC_M1_TR0_MULTI 0x00008000
  389 +#define EMAC_M1_TR1_DEPEND 0x00004000
  390 +#define EMAC_M1_TR1_MULTI 0x00002000
399 391 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
400   -#define EMAC_M1_JUMBO_ENABLE 0x00001000
  392 +#define EMAC_M1_JUMBO_ENABLE 0x00001000
401 393 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
402 394 #endif /* defined(CONFIG_440GX) */
403 395  
404 396 /* Transmit Mode Register 0 */
405   -#define EMAC_TXM0_GNP0 (0x80000000)
406   -#define EMAC_TXM0_GNP1 (0x40000000)
407   -#define EMAC_TXM0_GNPD (0x20000000)
408   -#define EMAC_TXM0_FC (0x10000000)
  397 +#define EMAC_TXM0_GNP0 (0x80000000)
  398 +#define EMAC_TXM0_GNP1 (0x40000000)
  399 +#define EMAC_TXM0_GNPD (0x20000000)
  400 +#define EMAC_TXM0_FC (0x10000000)
409 401  
410 402 /* Receive Mode Register */
411 403 #define EMAC_RMR_SP (0x80000000)
412 404  
413 405  
414 406  
415 407  
... ... @@ -427,39 +419,38 @@
427 419 #define EMAC_ISR_PP (0x01000000)
428 420 #define EMAC_ISR_BP (0x00800000)
429 421 #define EMAC_ISR_RP (0x00400000)
430   -#define EMAC_ISR_SE (0x00200000)
431   -#define EMAC_ISR_SYE (0x00100000)
432   -#define EMAC_ISR_BFCS (0x00080000)
433   -#define EMAC_ISR_PTLE (0x00040000)
434   -#define EMAC_ISR_ORE (0x00020000)
435   -#define EMAC_ISR_IRE (0x00010000)
436   -#define EMAC_ISR_DBDM (0x00000200)
437   -#define EMAC_ISR_DB0 (0x00000100)
438   -#define EMAC_ISR_SE0 (0x00000080)
439   -#define EMAC_ISR_TE0 (0x00000040)
440   -#define EMAC_ISR_DB1 (0x00000020)
441   -#define EMAC_ISR_SE1 (0x00000010)
442   -#define EMAC_ISR_TE1 (0x00000008)
443   -#define EMAC_ISR_MOS (0x00000002)
444   -#define EMAC_ISR_MOF (0x00000001)
  422 +#define EMAC_ISR_SE (0x00200000)
  423 +#define EMAC_ISR_SYE (0x00100000)
  424 +#define EMAC_ISR_BFCS (0x00080000)
  425 +#define EMAC_ISR_PTLE (0x00040000)
  426 +#define EMAC_ISR_ORE (0x00020000)
  427 +#define EMAC_ISR_IRE (0x00010000)
  428 +#define EMAC_ISR_DBDM (0x00000200)
  429 +#define EMAC_ISR_DB0 (0x00000100)
  430 +#define EMAC_ISR_SE0 (0x00000080)
  431 +#define EMAC_ISR_TE0 (0x00000040)
  432 +#define EMAC_ISR_DB1 (0x00000020)
  433 +#define EMAC_ISR_SE1 (0x00000010)
  434 +#define EMAC_ISR_TE1 (0x00000008)
  435 +#define EMAC_ISR_MOS (0x00000002)
  436 +#define EMAC_ISR_MOF (0x00000001)
445 437  
446   -
447 438 /* STA CONTROL REG */
448   -#define EMAC_STACR_OC (0x00008000)
449   -#define EMAC_STACR_PHYE (0x00004000)
  439 +#define EMAC_STACR_OC (0x00008000)
  440 +#define EMAC_STACR_PHYE (0x00004000)
450 441  
451 442 #ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
452   -#define EMAC_STACR_INDIRECT_MODE (0x00002000)
453   -#define EMAC_STACR_WRITE (0x00000800) /* $BUC */
454   -#define EMAC_STACR_READ (0x00001000) /* $BUC */
455   -#define EMAC_STACR_OP_MASK (0x00001800)
456   -#define EMAC_STACR_MDIO_ADDR (0x00000000)
457   -#define EMAC_STACR_MDIO_WRITE (0x00000800)
458   -#define EMAC_STACR_MDIO_READ (0x00001800)
459   -#define EMAC_STACR_MDIO_READ_INC (0x00001000)
  443 +#define EMAC_STACR_INDIRECT_MODE (0x00002000)
  444 +#define EMAC_STACR_WRITE (0x00000800) /* $BUC */
  445 +#define EMAC_STACR_READ (0x00001000) /* $BUC */
  446 +#define EMAC_STACR_OP_MASK (0x00001800)
  447 +#define EMAC_STACR_MDIO_ADDR (0x00000000)
  448 +#define EMAC_STACR_MDIO_WRITE (0x00000800)
  449 +#define EMAC_STACR_MDIO_READ (0x00001800)
  450 +#define EMAC_STACR_MDIO_READ_INC (0x00001000)
460 451 #else
461   -#define EMAC_STACR_WRITE (0x00002000)
462   -#define EMAC_STACR_READ (0x00001000)
  452 +#define EMAC_STACR_WRITE (0x00002000)
  453 +#define EMAC_STACR_READ (0x00001000)
463 454 #endif
464 455  
465 456 #define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */
... ... @@ -467,9 +458,9 @@
467 458 #define EMAC_STACR_CLK_100MHZ (0x00000C00)
468 459  
469 460 /* Transmit Request Threshold Register */
470   -#define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */
471   -#define EMAC_TRTR_192 (0x10000000)
472   -#define EMAC_TRTR_128 (0x01000000)
  461 +#define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */
  462 +#define EMAC_TRTR_192 (0x10000000)
  463 +#define EMAC_TRTR_128 (0x01000000)
473 464  
474 465 /* the follwing defines are for the MadMAL status and control registers. */
475 466 /* For bits 0..5 look at the mal.h file */