Eric Lee / smarc-uboot

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Commit e02c521d94b45d7b05aa522e4ccde6b74bf5fe57

Authored by Stefan Roese
1 parent feaa43f3a8
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ppc4xx: Add 44x cache locking to better support init-ram in d-cache 

This patch adds support for locking the init-ram/stack in d-cache,
so that other regions may use d-cache as well

Note, that this current implementation locks exactly 4k of d-cache,
so please make sure that you don't define a bigger init-ram area. Take
a look at the lwmon5 440EPx implementation as a reference.

Signed-off-by: Stefan Roese <sr@denx.de>

Showing 1 changed file with 52 additions and 0 deletions Side-by-side Diff

... ... @@ -636,6 +636,33 @@
636 636 dcbz r0,r3
637 637 addi r3,r3,32
638 638 bdnz ..d_ag
  639 +
  640 + /*
  641 + * Lock the init-ram/stack in d-cache, so that other regions
  642 + * may use d-cache as well
  643 + * Note, that this current implementation locks exactly 4k
  644 + * of d-cache, so please make sure that you don't define a
  645 + * bigger init-ram area. Take a look at the lwmon5 440EPx
  646 + * implementation as a reference.
  647 + */
  648 + msync
  649 + isync
  650 + /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
  651 + lis r1,0x0201
  652 + ori r1,r1,0xf808
  653 + mtspr dvlim,r1
  654 + lis r1,0x0808
  655 + ori r1,r1,0x0808
  656 + mtspr dnv0,r1
  657 + mtspr dnv1,r1
  658 + mtspr dnv2,r1
  659 + mtspr dnv3,r1
  660 + mtspr dtv0,r1
  661 + mtspr dtv1,r1
  662 + mtspr dtv2,r1
  663 + mtspr dtv3,r1
  664 + msync
  665 + isync
639 666 #endif /* CFG_INIT_RAM_DCACHE */
640 667  
641 668 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
... ... @@ -1345,6 +1372,31 @@
1345 1372 mr r4,r10
1346 1373 mr r5,r11
1347 1374 #endif
  1375 +
  1376 +#ifdef CFG_INIT_RAM_DCACHE
  1377 + /*
  1378 + * Unlock the previously locked d-cache
  1379 + */
  1380 + msync
  1381 + isync
  1382 + /* set TFLOOR/NFLOOR to 0 again */
  1383 + lis r6,0x0001
  1384 + ori r6,r6,0xf800
  1385 + mtspr dvlim,r6
  1386 + lis r6,0x0000
  1387 + ori r6,r6,0x0000
  1388 + mtspr dnv0,r6
  1389 + mtspr dnv1,r6
  1390 + mtspr dnv2,r6
  1391 + mtspr dnv3,r6
  1392 + mtspr dtv0,r6
  1393 + mtspr dtv1,r6
  1394 + mtspr dtv2,r6
  1395 + mtspr dtv3,r6
  1396 + msync
  1397 + isync
  1398 +#endif /* CFG_INIT_RAM_DCACHE */
  1399 +
1348 1400 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1349 1401 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1350 1402 defined(CONFIG_440SP) || defined(CONFIG_440SPE)