Eric Lee / smarc-uboot

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Commit e0ac62d798ce60ec5d43125d4786e58b0d881836

Authored by wdenk
1 parent ae3af05ec9
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

* Make Ethernet autonegotiation on INCA-IP work for all clock rates; 

allow selection of clock frequency as "make" target

* Implement memory autosizing code for IceCube boards

* Configure network port on INCA-IP for autonegotiation

* Fix overflow problem in network timeout code

* Patch by Richard Woodruff, 8 Aug 2003:
  Allow crc32 to be used at address 0x000 (crc32_no_comp, too).

Showing 17 changed files with 301 additions and 219 deletions Side-by-side Diff

... ... @@ -2,6 +2,18 @@
2 2 Changes for U-Boot 0.4.5:
3 3 ======================================================================
4 4  
  5 +* Make Ethernet autonegotiation on INCA-IP work for all clock rates;
  6 + allow selection of clock frequency as "make" target
  7 +
  8 +* Implement memory autosizing code for IceCube boards
  9 +
  10 +* Configure network port on INCA-IP for autonegotiation
  11 +
  12 +* Fix overflow problem in network timeout code
  13 +
  14 +* Patch by Richard Woodruff, 8 Aug 2003:
  15 + Allow crc32 to be used at address 0x000 (crc32_no_comp, too).
  16 +
5 17 * Update for TQM board defaults:
6 18 disable clocks_in_mhz, enable boot count limit
7 19  
... ... @@ -848,8 +848,30 @@
848 848 ## MIPS32 4Kc
849 849 #########################################################################
850 850  
851   -incaip_config : unconfig
852   - @./mkconfig $(@:_config=) mips mips incaip
  851 +xtract_incaip = $(subst _100MHz,,$(subst _133MHz,,$(subst _150MHz,,$(subst _config,,$1))))
  852 +
  853 +incaip_100MHz_config \
  854 +incaip_133MHz_config \
  855 +incaip_150MHz_config \
  856 +incaip_config: unconfig
  857 + @ >include/config.h
  858 + @[ -z "$(findstring _100MHz,$@)" ] || \
  859 + { echo "#define CPU_CLOCK_RATE 100000000" >>include/config.h ; \
  860 + echo "... with 100MHz system clock" ; \
  861 + }
  862 + @[ -z "$(findstring _133MHz,$@)" ] || \
  863 + { echo "#define CPU_CLOCK_RATE 133000000" >>include/config.h ; \
  864 + echo "... with 133MHz system clock" ; \
  865 + }
  866 + @[ -z "$(findstring _150MHz,$@)" ] || \
  867 + { echo "#define CPU_CLOCK_RATE 150000000" >>include/config.h ; \
  868 + echo "... with 150MHz system clock" ; \
  869 + }
  870 + @./mkconfig -a $(call xtract_incaip,$@) mips mips incaip
  871 +
  872 +#########################################################################
  873 +## MIPS64 5Kc
  874 +#########################################################################
853 875  
854 876 purple_config : unconfig
855 877 @./mkconfig $(@:_config=) mips mips purple
board/icecube/icecube.c
Diff comments   View file @ e0ac62d
... ... @@ -25,35 +25,84 @@
25 25 #include <mpc5xxx.h>
26 26 #include <pci.h>
27 27  
28   -long int initdram (int board_type)
  28 +static long int dram_size(long int *base, long int maxsize)
29 29 {
30   -#ifndef CFG_RAMBOOT
31   - /* configure SDRAM start/end */
32   -#if defined(CONFIG_MPC5200)
33   - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x00000018;/* 32M at 0x0 */
34   - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x02000000;/* disabled */
  30 + volatile long int *addr;
  31 + ulong cnt, val;
  32 + ulong save[32]; /* to make test non-destructive */
  33 + unsigned char i = 0;
35 34  
36   - /* setup config registers */
37   - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2233a00;
38   - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
  35 + for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
  36 + addr = base + cnt; /* pointer arith! */
39 37  
  38 + save[i++] = *addr;
  39 + *addr = ~cnt;
  40 + }
  41 +
  42 + /* write 0 to base address */
  43 + addr = base;
  44 + save[i] = *addr;
  45 + *addr = 0;
  46 +
  47 + /* check at base address */
  48 + if ((val = *addr) != 0) {
  49 + *addr = save[i];
  50 + return (0);
  51 + }
  52 +
  53 + for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
  54 + addr = base + cnt; /* pointer arith! */
  55 +
  56 + val = *addr;
  57 + *addr = save[--i];
  58 +
  59 + if (val != (~cnt)) {
  60 + return (cnt * sizeof (long));
  61 + }
  62 + }
  63 + return (maxsize);
  64 +}
  65 +
  66 +static void sdram_start (int hi_addr)
  67 +{
  68 + long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  69 +
40 70 /* unlock mode register */
41   - *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000;
  71 + *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000 | hi_addr_bit;
42 72 /* precharge all banks */
43   - *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002;
  73 + *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
44 74 /* set mode register */
  75 +#if defined(CONFIG_MPC5200)
45 76 *(vu_long *)MPC5XXX_SDRAM_MODE = 0x408d0000;
  77 +#elif defined(CONFIG_MGT5100)
  78 + *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
  79 +#endif
46 80 /* precharge all banks */
47   - *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002;
  81 + *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
48 82 /* auto refresh */
49   - *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004;
  83 + *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit;
50 84 /* set mode register */
51 85 *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
52 86 /* normal operation */
53   - *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000;
  87 + *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit;
  88 +}
  89 +
  90 +long int initdram (int board_type)
  91 +{
  92 + ulong test1, test2, dramsize = 0;
  93 +#ifndef CFG_RAMBOOT
  94 + /* configure SDRAM start/end */
  95 +#if defined(CONFIG_MPC5200)
  96 + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
  97 + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
  98 +
  99 + /* setup config registers */
  100 + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2233a00;
  101 + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
  102 +
54 103 #elif defined(CONFIG_MGT5100)
55 104 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
56   - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x000007ff;/* 64M */
  105 + *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
57 106 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
58 107  
59 108 /* setup config registers */
60 109  
61 110  
... ... @@ -62,33 +111,32 @@
62 111  
63 112 /* address select register */
64 113 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000;
65   -
66   - /* unlock mode register */
67   - *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0000;
68   - /* precharge all banks */
69   - *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0002;
70   - /* set mode register */
71   - *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
72   - /* precharge all banks */
73   - *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0002;
74   - /* auto refresh */
75   - *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0004;
76   - /* set mode register */
77   - *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
78   - /* normal operation */
79   - *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x514f0000;
80 114 #endif
  115 + sdram_start(0);
  116 + test1 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
  117 + sdram_start(1);
  118 + test2 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
  119 + if (test1 > test2) {
  120 + sdram_start(0);
  121 + dramsize = test1;
  122 + } else {
  123 + dramsize = test2;
  124 + }
  125 +#if defined(CONFIG_MPC5200)
  126 + *(vu_long *)MPC5XXX_SDRAM_CS0CFG =
  127 + (0x13 + __builtin_ffs(dramsize >> 20) - 1);
  128 + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
  129 +#elif defined(CONFIG_MGT5100)
  130 + *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
  131 +#endif
  132 +
81 133 #else
82 134 #ifdef CONFIG_MGT5100
83 135 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
84 136 #endif
85 137 #endif
86 138 /* return total ram size */
87   -#if defined(CONFIG_MGT5100)
88   - return (64 * 1024 * 1024);
89   -#elif defined(CONFIG_MPC5200)
90   - return (32 * 1024 * 1024);
91   -#endif
  139 + return dramsize;
92 140 }
93 141  
94 142 int checkboard (void)
board/tqm8xx/flash.c
Diff comments   View file @ e0ac62d
... ... @@ -116,14 +116,15 @@
116 116  
117 117 #ifdef CFG_ENV_IS_IN_FLASH
118 118 /* ENV protection ON by default */
119   - debug ("Protect %senvironment: %08lx ... %08lx\n",
120 119 # ifdef CFG_ENV_ADDR_REDUND
121   - "primary ",
  120 + debug ("Protect primary environment: %08lx ... %08lx\n",
  121 + (ulong)CFG_ENV_ADDR,
  122 + (ulong)CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1);
122 123 # else
123   - "",
124   -# endif
  124 + debug ("Protect environment: %08lx ... %08lx\n",
125 125 (ulong)CFG_ENV_ADDR,
126 126 (ulong)CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1);
  127 +# endif
127 128  
128 129 flash_protect(FLAG_PROTECT_SET,
129 130 CFG_ENV_ADDR,
cpu/mpc5xxx/pci_mpc5200.c
Diff comments   View file @ e0ac62d
... ... @@ -51,9 +51,6 @@
51 51 *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
52 52 eieio();
53 53 *(volatile u32 *)MPC5XXX_PCI_CAR = 0;
54   - /* skip MPC5200 */
55   - if (offset == 0 && *value == 0x58031057)
56   - *value = 0xffffffff;
57 54 return 0;
58 55 }
59 56  
... ... @@ -103,7 +103,7 @@
103 103 boot_warm:
104 104 mfmsr r5 /* save msr contents */
105 105  
106   -#if defined(CFG_DEFAULT_MBAR)
  106 +#if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT)
107 107 lis r3, CFG_MBAR@h
108 108 ori r3, r3, CFG_MBAR@l
109 109 #if defined(CONFIG_MPC5200)
... ... @@ -41,5 +41,19 @@
41 41 go 0xb0000000
42 42  
43 43  
  44 +
  45 +Ethernet autonegotiation needs some time to complete. Instead of
  46 +delaying the boot process in all cases, we just start the
  47 +autonegotiation process when U-Boot comes up and that is all. Most
  48 +likely, it will complete by the time the network transfer is
  49 +attempted for the first time. In the worst case, if a transfer is
  50 +attempted before the autonegotiation is complete, just a single
  51 +packet would be lost resulting in a single timeout error, and then
  52 +the transfer would proceed normally. So the time that we would have
  53 +lost unconditionally waiting for the autonegotiation to complete, we
  54 +have to wait only if the file transfer is started immediately after
  55 +reset. We've verified that this works for all the clock
  56 +configurations.
  57 +
44 58 (C) 2003 Wolfgang Denk
drivers/inca-ip_sw.c
Diff comments   View file @ e0ac62d
... ... @@ -70,10 +70,8 @@
70 70  
71 71 typedef struct
72 72 {
73   - union
74   - {
75   - struct
76   - {
  73 + union {
  74 + struct {
77 75 volatile u32 HOLD :1;
78 76 volatile u32 ICpt :1;
79 77 volatile u32 IEop :1;
... ... @@ -89,10 +87,8 @@
89 87  
90 88 volatile u32 RxDataPtr;
91 89  
92   - union
93   - {
94   - struct
95   - {
  90 + union {
  91 + struct {
96 92 volatile u32 C :1;
97 93 volatile u32 Sop :1;
98 94 volatile u32 Eop :1;
... ... @@ -108,10 +104,8 @@
108 104  
109 105 typedef struct
110 106 {
111   - union
112   - {
113   - struct
114   - {
  107 + union {
  108 + struct {
115 109 volatile u32 HOLD :1;
116 110 volatile u32 Eop :1;
117 111 volatile u32 Sop :1;
... ... @@ -159,8 +153,7 @@
159 153 printf("Entered inca_switch_initialize()\n");
160 154 #endif
161 155  
162   - if (!(dev = (struct eth_device *) malloc (sizeof *dev)))
163   - {
  156 + if (!(dev = (struct eth_device *) malloc (sizeof *dev))) {
164 157 printf("Failed to allocate memory\n");
165 158 return 0;
166 159 }
... ... @@ -196,8 +189,8 @@
196 189 printf("Entering inca_switch_init()\n");
197 190 #endif
198 191  
199   - /* Set MAC address.
200   - */
  192 + /* Set MAC address.
  193 + */
201 194 wTmp = (u16)dev->enetaddr[0];
202 195 regValue = (wTmp << 8) | dev->enetaddr[1];
203 196  
204 197  
205 198  
206 199  
207 200  
... ... @@ -211,35 +204,32 @@
211 204  
212 205 SW_WRITE_REG(INCA_IP_Switch_PMAC_SA2, regValue);
213 206  
214   - /* Initialize the descriptor rings.
215   - */
  207 + /* Initialize the descriptor rings.
  208 + */
216 209 for (i = 0; i < NUM_RX_DESC; i++)
217 210 {
218 211 inca_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_ring[i]);
219 212 memset(rx_desc, 0, sizeof(rx_ring[i]));
220 213  
221   - /* Set maximum size of receive buffer.
222   - */
  214 + /* Set maximum size of receive buffer.
  215 + */
223 216 rx_desc->params.field.NFB = PKTSIZE_ALIGN;
224 217  
225   - /* Set the offset of the receive buffer. Zero means
226   - * that the offset mechanism is not used.
227   - */
  218 + /* Set the offset of the receive buffer. Zero means
  219 + * that the offset mechanism is not used.
  220 + */
228 221 rx_desc->params.field.offset = 0;
229 222  
230 223 /* Check if it is the last descriptor.
231 224 */
232   - if (i == (NUM_RX_DESC - 1))
233   - {
234   - /* Let the last descriptor point to the first
235   - * one.
236   - */
  225 + if (i == (NUM_RX_DESC - 1)) {
  226 + /* Let the last descriptor point to the first
  227 + * one.
  228 + */
237 229 rx_desc->nextRxDescPtr = KSEG1ADDR((u32)rx_ring);
238   - }
239   - else
240   - {
241   - /* Set the address of the next descriptor.
242   - */
  230 + } else {
  231 + /* Set the address of the next descriptor.
  232 + */
243 233 rx_desc->nextRxDescPtr = (u32)KSEG1ADDR(&rx_ring[i+1]);
244 234 }
245 235  
... ... @@ -251,8 +241,7 @@
251 241 printf("tx_ring = 0x%08X 0x%08X\n", (u32)tx_ring, (u32)&tx_ring[0]);
252 242 #endif
253 243  
254   - for (i = 0; i < NUM_TX_DESC; i++)
255   - {
  244 + for (i = 0; i < NUM_TX_DESC; i++) {
256 245 inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[i]);
257 246  
258 247 memset(tx_desc, 0, sizeof(tx_ring[i]));
259 248  
260 249  
261 250  
262 251  
263 252  
264 253  
... ... @@ -263,46 +252,43 @@
263 252  
264 253 /* Check if it is the last descriptor.
265 254 */
266   - if (i == (NUM_TX_DESC - 1))
267   - {
  255 + if (i == (NUM_TX_DESC - 1)) {
268 256 /* Let the last descriptor point to the
269 257 * first one.
270 258 */
271 259 tx_desc->nextTxDescPtr = KSEG1ADDR((u32)tx_ring);
272   - }
273   - else
274   - {
  260 + } else {
275 261 /* Set the address of the next descriptor.
276 262 */
277 263 tx_desc->nextTxDescPtr = (u32)KSEG1ADDR(&tx_ring[i+1]);
278 264 }
279 265 }
280 266  
281   - /* Initialize RxDMA.
282   - */
  267 + /* Initialize RxDMA.
  268 + */
283 269 DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v);
284 270 #if 0
285 271 printf("RX status = 0x%08X\n", v);
286 272 #endif
287 273  
288   - /* Writing to the FRDA of CHANNEL.
289   - */
  274 + /* Writing to the FRDA of CHANNEL.
  275 + */
290 276 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXFRDA0, (u32)rx_ring);
291 277  
292   - /* Writing to the COMMAND REG.
293   - */
  278 + /* Writing to the COMMAND REG.
  279 + */
294 280 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0,
295 281 INCA_IP_DMA_DMA_RXCCR0_INIT);
296 282  
297   - /* Initialize TxDMA.
298   - */
  283 + /* Initialize TxDMA.
  284 + */
299 285 DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v);
300 286 #if 0
301 287 printf("TX status = 0x%08X\n", v);
302 288 #endif
303 289  
304   - /* Writing to the FRDA of CHANNEL.
305   - */
  290 + /* Writing to the FRDA of CHANNEL.
  291 + */
306 292 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXFRDA0, (u32)tx_ring);
307 293  
308 294 tx_new = rx_new = 0;
... ... @@ -313,12 +299,12 @@
313 299 #if 0
314 300 rx_ring[rx_hold].params.field.HOLD = 1;
315 301 #endif
316   - /* enable spanning tree forwarding, enable the CPU port */
317   - /* ST_PT:
318   - CPS (CPU port status) 0x3 (forwarding)
319   - LPS (LAN port status) 0x3 (forwarding)
320   - PPS (PC port status) 0x3 (forwarding)
321   - */
  302 + /* enable spanning tree forwarding, enable the CPU port */
  303 + /* ST_PT:
  304 + * CPS (CPU port status) 0x3 (forwarding)
  305 + * LPS (LAN port status) 0x3 (forwarding)
  306 + * PPS (PC port status) 0x3 (forwarding)
  307 + */
322 308 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f);
323 309  
324 310 #if 0
325 311  
326 312  
... ... @@ -342,23 +328,19 @@
342 328 printf("Entered inca_switch_send()\n");
343 329 #endif
344 330  
345   - if (length <= 0)
346   - {
  331 + if (length <= 0) {
347 332 printf ("%s: bad packet size: %d\n", dev->name, length);
348 333 goto Done;
349 334 }
350 335  
351   - for(i = 0; tx_desc->C == 0; i++)
352   - {
353   - if (i >= TOUT_LOOP)
354   - {
  336 + for(i = 0; tx_desc->C == 0; i++) {
  337 + if (i >= TOUT_LOOP) {
355 338 printf("%s: tx error buffer not ready\n", dev->name);
356 339 goto Done;
357 340 }
358 341 }
359 342  
360   - if (tx_old_hold >= 0)
361   - {
  343 + if (tx_old_hold >= 0) {
362 344 KSEG1ADDR(&tx_ring[tx_old_hold])->params.field.HOLD = 1;
363 345 }
364 346 tx_old_hold = tx_hold;
365 347  
... ... @@ -376,13 +358,10 @@
376 358 tx_new = (tx_new + 1) % NUM_TX_DESC;
377 359  
378 360  
379   - if (! initialized)
380   - {
  361 + if (! initialized) {
381 362 command = INCA_IP_DMA_DMA_TXCCR0_INIT;
382 363 initialized = 1;
383   - }
384   - else
385   - {
  364 + } else {
386 365 command = INCA_IP_DMA_DMA_TXCCR0_HR;
387 366 }
388 367  
... ... @@ -394,10 +373,8 @@
394 373 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
395 374  
396 375 #if 1
397   - for(i = 0; KSEG1ADDR(&tx_ring[tx_hold])->C == 0; i++)
398   - {
399   - if (i >= TOUT_LOOP)
400   - {
  376 + for(i = 0; KSEG1ADDR(&tx_ring[tx_hold])->C == 0; i++) {
  377 + if (i >= TOUT_LOOP) {
401 378 printf("%s: tx buffer not ready\n", dev->name);
402 379 goto Done;
403 380 }
404 381  
... ... @@ -421,12 +398,10 @@
421 398 printf("Entered inca_switch_recv()\n");
422 399 #endif
423 400  
424   - for (;;)
425   - {
  401 + for (;;) {
426 402 rx_desc = KSEG1ADDR(&rx_ring[rx_new]);
427 403  
428   - if (rx_desc->status.field.C == 0)
429   - {
  404 + if (rx_desc->status.field.C == 0) {
430 405 break;
431 406 }
432 407  
... ... @@ -434,8 +409,7 @@
434 409 rx_ring[rx_new].params.field.HOLD = 1;
435 410 #endif
436 411  
437   - if (! rx_desc->status.field.Eop)
438   - {
  412 + if (! rx_desc->status.field.Eop) {
439 413 printf("Partly received packet!!!\n");
440 414 break;
441 415 }
442 416  
... ... @@ -454,16 +428,13 @@
454 428 }
455 429 #endif
456 430  
457   - if (length)
458   - {
  431 + if (length) {
459 432 #if 0
460 433 printf("Received %d bytes\n", length);
461 434 #endif
462 435 NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_new]),
463 436 length - 4);
464   - }
465   - else
466   - {
  437 + } else {
467 438 #if 1
468 439 printf("Zero length!!!\n");
469 440 #endif
470 441  
471 442  
... ... @@ -495,16 +466,16 @@
495 466 initialized = 0;
496 467 #endif
497 468 #if 1
498   - /* Disable forwarding to the CPU port.
499   - */
  469 + /* Disable forwarding to the CPU port.
  470 + */
500 471 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
501 472  
502   - /* Close RxDMA channel.
503   - */
  473 + /* Close RxDMA channel.
  474 + */
504 475 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
505 476  
506   - /* Close TxDMA channel.
507   - */
  477 + /* Close TxDMA channel.
  478 + */
508 479 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_TXCCR0_OFF);
509 480  
510 481  
511 482  
512 483  
513 484  
514 485  
515 486  
516 487  
517 488  
... ... @@ -519,88 +490,89 @@
519 490 {
520 491 u32 regValue;
521 492  
522   - /* To workaround a problem with collision counter
523   - * (see Errata sheet).
524   - */
  493 + /* To workaround a problem with collision counter
  494 + * (see Errata sheet).
  495 + */
525 496 SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001);
526 497 SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001);
527 498  
528 499 #if 1
529   - /* init MDIO configuration:
530   - MDS (Poll speed): 0x01 (4ms)
531   - PHY_LAN_ADDR: 0x06
532   - PHY_PC_ADDR: 0x05
533   - UEP (Use External PHY): 0x00 (Internal PHY is used)
534   - PS (Port Select): 0x00 (PT/UMM for LAN)
535   - PT (PHY Test): 0x00 (no test mode)
536   - UMM (Use MDIO Mode): 0x00 (state machine is disabled)
537   - */
  500 + /* init MDIO configuration:
  501 + * MDS (Poll speed): 0x01 (4ms)
  502 + * PHY_LAN_ADDR: 0x06
  503 + * PHY_PC_ADDR: 0x05
  504 + * UEP (Use External PHY): 0x00 (Internal PHY is used)
  505 + * PS (Port Select): 0x00 (PT/UMM for LAN)
  506 + * PT (PHY Test): 0x00 (no test mode)
  507 + * UMM (Use MDIO Mode): 0x00 (state machine is disabled)
  508 + */
538 509 SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50);
539 510  
540   - /* init PHY:
541   - SL (Auto Neg. Speed for LAN)
542   - SP (Auto Neg. Speed for PC)
543   - LL (Link Status for LAN)
544   - LP (Link Status for PC)
545   - DL (Duplex Status for LAN)
546   - DP (Duplex Status for PC)
547   - PL (Auto Neg. Pause Status for LAN)
548   - PP (Auto Neg. Pause Status for PC)
549   - */
  511 + /* init PHY:
  512 + * SL (Auto Neg. Speed for LAN)
  513 + * SP (Auto Neg. Speed for PC)
  514 + * LL (Link Status for LAN)
  515 + * LP (Link Status for PC)
  516 + * DL (Duplex Status for LAN)
  517 + * DP (Duplex Status for PC)
  518 + * PL (Auto Neg. Pause Status for LAN)
  519 + * PP (Auto Neg. Pause Status for PC)
  520 + */
550 521 SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff);
551 522  
552   - /* MDIO_ACC:
553   - RA (Request/Ack) 0x01 (Request)
554   - RW (Read/Write) 0x01 (Write)
555   - PHY_ADDR 0x05 (PC)
556   - REG_ADDR 0x00 (PHY_BCR: basic control register)
557   - PHY_DATA 0x8000
558   - Reset - software reset
559   - LB (loop back) - normal
560   - SS (speed select) - 10 Mbit/s
561   - ANE (auto neg. enable) - disable
562   - PD (power down) - normal
563   - ISO (isolate) - normal
564   - RAN (restart auto neg.) - normal
565   - DM (duplex mode) - half duplex
566   - CT (collision test) - enable
567   - */
568   - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a08000);
  523 + /* MDIO_ACC:
  524 + * RA (Request/Ack) 0x01 (Request)
  525 + * RW (Read/Write) 0x01 (Write)
  526 + * PHY_ADDR 0x05 (PC)
  527 + * REG_ADDR 0x00 (PHY_BCR: basic control register)
  528 + * PHY_DATA 0x8000
  529 + * Reset - software reset
  530 + * LB (loop back) - normal
  531 + * SS (speed select) - 10 Mbit/s
  532 + * ANE (auto neg. enable) - enable
  533 + * PD (power down) - normal
  534 + * ISO (isolate) - normal
  535 + * RAN (restart auto neg.) - normal
  536 + * DM (duplex mode) - half duplex
  537 + * CT (collision test) - enable
  538 + */
  539 + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000);
569 540  
570   - /* MDIO_ACC:
571   - RA (Request/Ack) 0x01 (Request)
572   - RW (Read/Write) 0x01 (Write)
573   - PHY_ADDR 0x06 (LAN)
574   - REG_ADDR 0x00 (PHY_BCR: basic control register)
575   - PHY_DATA 0x8000
576   - Reset - software reset
577   - LB (loop back) - normal
578   - SS (speed select) - 10 Mbit/s
579   - ANE (auto neg. enable) - disable
580   - PD (power down) - normal
581   - ISO (isolate) - normal
582   - RAN (restart auto neg.) - normal
583   - DM (duplex mode) - half duplex
584   - CT (collision test) - enable
585   - */
586   - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c08000);
  541 + /* MDIO_ACC:
  542 + * RA (Request/Ack) 0x01 (Request)
  543 + * RW (Read/Write) 0x01 (Write)
  544 + * PHY_ADDR 0x06 (LAN)
  545 + * REG_ADDR 0x00 (PHY_BCR: basic control register)
  546 + * PHY_DATA 0x8000
  547 + * Reset - software reset
  548 + * LB (loop back) - normal
  549 + * SS (speed select) - 10 Mbit/s
  550 + * ANE (auto neg. enable) - enable
  551 + * PD (power down) - normal
  552 + * ISO (isolate) - normal
  553 + * RAN (restart auto neg.) - normal
  554 + * DM (duplex mode) - half duplex
  555 + * CT (collision test) - enable
  556 + */
  557 + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000);
  558 +
587 559 #endif
588 560  
589   - /* Make sure the CPU port is disabled for now. We
590   - * don't want packets to get stacked for us until
591   - * we enable DMA and are prepared to receive them.
592   - */
  561 + /* Make sure the CPU port is disabled for now. We
  562 + * don't want packets to get stacked for us until
  563 + * we enable DMA and are prepared to receive them.
  564 + */
593 565 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
594 566  
595 567 SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue);
596 568  
597   - /* CRC GEN is enabled.
598   - */
  569 + /* CRC GEN is enabled.
  570 + */
599 571 regValue |= 0x00000200;
600 572 SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue);
601 573  
602   - /* ADD TAG is disabled.
603   - */
  574 + /* ADD TAG is disabled.
  575 + */
604 576 SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
605 577 regValue &= ~0x00000002;
606 578 SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
... ... @@ -609,8 +581,8 @@
609 581  
610 582 static void inca_dma_init(void)
611 583 {
612   - /* Switch off all DMA channels.
613   - */
  584 + /* Switch off all DMA channels.
  585 + */
614 586 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
615 587 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR1, INCA_IP_DMA_DMA_RXCCR1_OFF);
616 588  
617 589  
618 590  
619 591  
... ... @@ -618,20 +590,20 @@
618 590 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR1, INCA_IP_DMA_DMA_TXCCR1_OFF);
619 591 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR2, INCA_IP_DMA_DMA_TXCCR2_OFF);
620 592  
621   - /* Setup TX channel polling time.
622   - */
  593 + /* Setup TX channel polling time.
  594 + */
623 595 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXPOLL, INCA_DMA_TX_POLLING_TIME);
624 596  
625   - /* Setup RX channel polling time.
626   - */
  597 + /* Setup RX channel polling time.
  598 + */
627 599 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXPOLL, INCA_DMA_RX_POLLING_TIME);
628 600  
629   - /* ERRATA: write reset value into the DMA RX IMR register.
630   - */
  601 + /* ERRATA: write reset value into the DMA RX IMR register.
  602 + */
631 603 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXIMR, 0xFFFFFFFF);
632 604  
633   - /* Just in case: disable all transmit interrupts also.
634   - */
  605 + /* Just in case: disable all transmit interrupts also.
  606 + */
635 607 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXIMR, 0xFFFFFFFF);
636 608  
637 609 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXISR, 0xFFFFFFFF);
... ... @@ -323,6 +323,13 @@
323 323 hose->current_busno++;
324 324 break;
325 325  
  326 +#ifdef CONFIG_MPC5200
  327 + case PCI_CLASS_BRIDGE_OTHER:
  328 + DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
  329 + PCI_DEV(dev));
  330 + break;
  331 +#endif
  332 +
326 333 default:
327 334 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
328 335 break;
include/configs/IceCube.h
Diff comments   View file @ e0ac62d
... ... @@ -131,6 +131,9 @@
131 131 */
132 132 #define CFG_MBAR 0xf0000000
133 133 #define CFG_SDRAM_BASE 0x00000000
  134 +#ifdef CONFIG_MPC5200
  135 +#define CFG_DEFAULT_MBAR 0x80000000
  136 +#endif
134 137  
135 138 /* Use SRAM until RAM will be available */
136 139 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
include/configs/incaip.h
Diff comments   View file @ e0ac62d
... ... @@ -31,8 +31,10 @@
31 31 #define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */
32 32 #define CONFIG_INCA_IP 1 /* on a INCA-IP Board */
33 33  
  34 +#ifndef CPU_CLOCK_RATE
34 35 /* allowed values: 100000000, 133000000, and 150000000 */
35 36 #define CPU_CLOCK_RATE 133000000 /* 133 MHz clock for the MIPS core */
  37 +#endif
36 38  
37 39 #if CPU_CLOCK_RATE == 100000000
38 40 #define INFINEON_EBU_BOOTCFG 0x20C4 /* CMULT = 4 for 100 MHz */
... ... @@ -24,7 +24,7 @@
24 24 #ifndef __VERSION_H__
25 25 #define __VERSION_H__
26 26  
27   -#define U_BOOT_VERSION "U-Boot 0.4.5"
  27 +#define U_BOOT_VERSION "U-Boot 0.4.6"
28 28  
29 29 #endif /* __VERSION_H__ */
... ... @@ -178,7 +178,6 @@
178 178 */
179 179 uLong ZEXPORT crc32_no_comp(uLong crc, const Bytef *buf, uInt len)
180 180 {
181   - if (buf == Z_NULL) return 0L;
182 181 #ifdef DYNAMIC_CRC_TABLE
183 182 if (crc_table_empty)
184 183 make_crc_table();
... ... @@ -75,9 +75,7 @@
75 75 ulong tmo;
76 76 ulong start = get_timer(0);
77 77  
78   - tmo = usec * CFG_HZ / 1000;
79   - tmo /= 1000;
80   -
  78 + tmo = usec * (CFG_HZ / 1000000);
81 79 while ((ulong)((mips_count_get() - start)) < tmo)
82 80 /*NOP*/;
83 81 }
... ... @@ -125,7 +125,8 @@
125 125  
126 126 static rxhand_f *packetHandler; /* Current RX packet handler */
127 127 static thand_f *timeHandler; /* Current timeout handler */
128   -static ulong timeValue; /* Current timeout value */
  128 +static ulong timeStart; /* Time base value */
  129 +static ulong timeDelta; /* Current timeout value */
129 130 volatile uchar *NetTxPacket = 0; /* THE transmit packet */
130 131  
131 132 static int net_check_prereq (proto_t protocol);
... ... @@ -391,7 +392,7 @@
391 392 * Check for a timeout, and run the timeout handler
392 393 * if we have one.
393 394 */
394   - if (timeHandler && (get_timer(0) > timeValue)) {
  395 + if (timeHandler && ((get_timer(0) - timeStart) > timeDelta)) {
395 396 thand_f *x;
396 397  
397 398 x = timeHandler;
... ... @@ -491,7 +492,8 @@
491 492 timeHandler = (thand_f *)0;
492 493 } else {
493 494 timeHandler = f;
494   - timeValue = get_timer(0) + iv;
  495 + timeStart = get_timer(0);
  496 + timeDelta = iv;
495 497 }
496 498 }
497 499  
... ... @@ -240,7 +240,7 @@
240 240 static void
241 241 TftpTimeout (void)
242 242 {
243   - if (++TftpTimeoutCount >= TIMEOUT_COUNT) {
  243 + if (++TftpTimeoutCount > TIMEOUT_COUNT) {
244 244 puts ("\nRetry count exceeded; starting again\n");
245 245 NetStartAgain ();
246 246 } else {
... ... @@ -152,6 +152,9 @@
152 152 $(CC) -g $(CFLAGS) -c $<
153 153  
154 154 subdirs:
  155 +ifeq ($(TOOLSUBDIRS),)
  156 + @:
  157 +else
155 158 @for dir in $(TOOLSUBDIRS) ; do \
156 159 $(MAKE) \
157 160 HOSTOS=$(HOSTOS) \
... ... @@ -160,6 +163,8 @@
160 163 HOST_LDFLAGS="$(HOST_LDFLAGS)" \
161 164 -C $$dir || exit 1 ; \
162 165 done
  166 +endif
  167 +
163 168 environment.c:
164 169 ln -s ../common/environment.c environment.c
165 170