Eric Lee / smarc-uboot

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Commit e0f6a4e8b17afead8add6e528936a505367c091c

Authored by Wolfgang Denk
2 parents f588bb034d 4212657c53
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Merge branch 'master' of /home/wd/git/u-boot/custodians 

* 'master' of /home/wd/git/u-boot/custodians:
  powerpc/ppc4xx: Remove typedefs for gdsys FPGA
  powerpc/ppc4xx: Fix typo in gdsys_fpga.h
  powerpc/ppc4xx: Update gdsys board configurations
  powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20
  powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes
  powerpc/ppc4xx: Make gdsys 405ep boards reset more generic
  powerpc/ppc4xx: Adjust environment size on neo

Showing 21 changed files Side-by-side Diff

board/gdsys/405ep/405ep.c
Diff comments   View file @ e0f6a4e
... ... @@ -28,12 +28,9 @@
28 28 #include <asm/ppc4xx-gpio.h>
29 29 #include <asm/global_data.h>
30 30  
  31 +#include "405ep.h"
31 32 #include <gdsys_fpga.h>
32 33  
33   -#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
34   -#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
35   -#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
36   -
37 34 #define REFLECTION_TESTPATTERN 0xdede
38 35 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
39 36  
... ... @@ -55,7 +52,6 @@
55 52 int board_early_init_f(void)
56 53 {
57 54 unsigned k;
58   - unsigned ctr;
59 55  
60 56 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
61 57 gd->fpga_state[k] = 0;
62 58  
63 59  
64 60  
65 61  
66 62  
... ... @@ -73,26 +69,29 @@
73 69 * -> ca. 15 us
74 70 */
75 71 mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
  72 + return 0;
  73 +}
76 74  
77   - /*
78   - * setup io-latches for reset
79   - */
80   - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
81   - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
  75 +int board_early_init_r(void)
  76 +{
  77 + unsigned k;
  78 + unsigned ctr;
82 79  
83   - /*
84   - * set "startup-finished"-gpios
85   - */
86   - gpio_write_bit(21, 0);
87   - gpio_write_bit(22, 1);
  80 + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  81 + gd->fpga_state[k] = 0;
88 82  
89 83 /*
90   - * wait for fpga-done
  84 + * reset FPGA
91 85 */
  86 + gd405ep_init();
  87 +
  88 + gd405ep_set_fpga_reset(1);
  89 +
  90 + gd405ep_setup_hw();
  91 +
92 92 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
93 93 ctr = 0;
94   - while (!(in_le16((void *)LATCH2_BASE)
95   - & CONFIG_SYS_FPGA_DONE(k))) {
  94 + while (!gd405ep_get_fpga_done(k)) {
96 95 udelay(100000);
97 96 if (ctr++ > 5) {
98 97 gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
99 98  
100 99  
101 100  
... ... @@ -101,15 +100,13 @@
101 100 }
102 101 }
103 102  
104   - /*
105   - * setup io-latches for boot (stop reset)
106   - */
107 103 udelay(10);
108   - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
109   - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
110 104  
  105 + gd405ep_set_fpga_reset(0);
  106 +
111 107 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
112   - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
  108 + struct ihs_fpga *fpga =
  109 + (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
113 110 #ifdef CONFIG_SYS_FPGA_NO_RFL_HI
114 111 u16 *reflection_target = &fpga->reflection_low;
115 112 #else
board/gdsys/405ep/405ep.h
Diff comments   View file @ e0f6a4e
  1 +#ifndef __405EP_H_
  2 +#define __405EP_H_
  3 +
  4 +/* functions to be provided by board implementation */
  5 +void gd405ep_init(void);
  6 +void gd405ep_set_fpga_reset(unsigned state);
  7 +void gd405ep_setup_hw(void);
  8 +int gd405ep_get_fpga_done(unsigned fpga);
  9 +
  10 +#endif /* __405EP_H_ */
board/gdsys/405ep/Makefile
Diff comments   View file @ e0f6a4e
... ... @@ -25,6 +25,7 @@
25 25  
26 26 LIB = $(obj)lib$(BOARD).o
27 27  
  28 +COBJS-$(CONFIG_NEO) += neo.o
28 29 COBJS-$(CONFIG_IO) += io.o
29 30 COBJS-$(CONFIG_IOCON) += iocon.o
30 31 COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o
board/gdsys/405ep/dlvision-10g.c
Diff comments   View file @ e0f6a4e
... ... @@ -26,16 +26,20 @@
26 26 #include <asm/processor.h>
27 27 #include <asm/io.h>
28 28 #include <asm/ppc4xx-gpio.h>
  29 +#include <dtt.h>
29 30  
  31 +#include "405ep.h"
30 32 #include <gdsys_fpga.h>
31 33  
32 34 #include "../common/osd.h"
33 35  
  36 +#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
  37 +#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
34 38 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
35   -#define LATCH2_MC2_PRESENT_N 0x0080
36   -
37 39 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
38 40  
  41 +#define LATCH2_MC2_PRESENT_N 0x0080
  42 +
39 43 enum {
40 44 UNITTYPE_VIDEO_USER = 0,
41 45 UNITTYPE_MAIN_USER = 1,
... ... @@ -46,6 +50,8 @@
46 50 enum {
47 51 HWVER_101 = 0,
48 52 HWVER_110 = 1,
  53 + HWVER_120 = 2,
  54 + HWVER_130 = 3,
49 55 };
50 56  
51 57 enum {
... ... @@ -65,6 +71,14 @@
65 71 RAM_DDR2_64 = 2,
66 72 };
67 73  
  74 +int misc_init_r(void)
  75 +{
  76 + /* startup fans */
  77 + dtt_init();
  78 +
  79 + return 0;
  80 +}
  81 +
68 82 static unsigned int get_hwver(void)
69 83 {
70 84 u16 latch3 = in_le16((void *)LATCH3_BASE);
... ... @@ -81,7 +95,7 @@
81 95  
82 96 static void print_fpga_info(unsigned dev)
83 97 {
84   - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
  98 + struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
85 99 u16 versions = in_le16(&fpga->versions);
86 100 u16 fpga_version = in_le16(&fpga->fpga_version);
87 101 u16 fpga_features = in_le16(&fpga->fpga_features);
88 102  
... ... @@ -146,9 +160,17 @@
146 160 break;
147 161  
148 162 case HWVER_110:
149   - printf(" HW-Ver 1.10\n");
  163 + printf(" HW-Ver 1.10-1.12\n");
150 164 break;
151 165  
  166 + case HWVER_120:
  167 + printf(" HW-Ver 1.20\n");
  168 + break;
  169 +
  170 + case HWVER_130:
  171 + printf(" HW-Ver 1.30\n");
  172 + break;
  173 +
152 174 default:
153 175 printf(" HW-Ver %d(not supported)\n",
154 176 hardware_version);
155 177  
156 178  
157 179  
158 180  
159 181  
160 182  
161 183  
... ... @@ -223,32 +245,31 @@
223 245 */
224 246 int checkboard(void)
225 247 {
226   - char buf[64];
227   - int i = getenv_f("serial#", buf, sizeof(buf));
  248 + char *s = getenv("serial#");
228 249  
229   - printf("Board: ");
  250 + puts("Board: ");
230 251  
231   - printf("DLVision 10G");
  252 + puts("DLVision 10G");
232 253  
233   - if (i > 0) {
  254 + if (s != NULL) {
234 255 puts(", serial# ");
235   - puts(buf);
  256 + puts(s);
236 257 }
237 258  
238 259 puts("\n");
239 260  
240   - print_fpga_info(0);
241   - if (get_mc2_present())
242   - print_fpga_info(1);
243   -
244 261 return 0;
245 262 }
246 263  
247 264 int last_stage_init(void)
248 265 {
249   - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
  266 + struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
250 267 u16 versions = in_le16(&fpga->versions);
251 268  
  269 + print_fpga_info(0);
  270 + if (get_mc2_present())
  271 + print_fpga_info(1);
  272 +
252 273 if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
253 274 return 0;
254 275  
... ... @@ -260,5 +281,34 @@
260 281 osd_probe(1);
261 282  
262 283 return 0;
  284 +}
  285 +
  286 +void gd405ep_init(void)
  287 +{
  288 +}
  289 +
  290 +void gd405ep_set_fpga_reset(unsigned state)
  291 +{
  292 + if (state) {
  293 + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
  294 + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
  295 + } else {
  296 + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
  297 + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
  298 + }
  299 +}
  300 +
  301 +void gd405ep_setup_hw(void)
  302 +{
  303 + /*
  304 + * set "startup-finished"-gpios
  305 + */
  306 + gpio_write_bit(21, 0);
  307 + gpio_write_bit(22, 1);
  308 +}
  309 +
  310 +int gd405ep_get_fpga_done(unsigned fpga)
  311 +{
  312 + return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
263 313 }
board/gdsys/405ep/io.c
Diff comments   View file @ e0f6a4e
... ... @@ -27,10 +27,16 @@
27 27 #include <asm/io.h>
28 28 #include <asm/ppc4xx-gpio.h>
29 29  
  30 +#include <dtt.h>
30 31 #include <miiphy.h>
31 32  
  33 +#include "405ep.h"
32 34 #include <gdsys_fpga.h>
33 35  
  36 +#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
  37 +#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
  38 +#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  39 +
34 40 #define PHYREG_CONTROL 0
35 41 #define PHYREG_PAGE_ADDRESS 22
36 42 #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
... ... @@ -47,6 +53,14 @@
47 53 HWVER_122 = 3,
48 54 };
49 55  
  56 +int misc_init_r(void)
  57 +{
  58 + /* startup fans */
  59 + dtt_init();
  60 +
  61 + return 0;
  62 +}
  63 +
50 64 int configure_gbit_phy(unsigned char addr)
51 65 {
52 66 unsigned short value;
... ... @@ -87,9 +101,23 @@
87 101 */
88 102 int checkboard(void)
89 103 {
90   - char buf[64];
91   - int i = getenv_f("serial#", buf, sizeof(buf));
92   - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
  104 + char *s = getenv("serial#");
  105 +
  106 + puts("Board: CATCenter Io");
  107 +
  108 + if (s != NULL) {
  109 + puts(", serial# ");
  110 + puts(s);
  111 + }
  112 +
  113 + puts("\n");
  114 +
  115 + return 0;
  116 +}
  117 +
  118 +static void print_fpga_info(void)
  119 +{
  120 + struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
93 121 u16 versions = in_le16(&fpga->versions);
94 122 u16 fpga_version = in_le16(&fpga->fpga_version);
95 123 u16 fpga_features = in_le16(&fpga->fpga_features);
96 124  
... ... @@ -103,16 +131,8 @@
103 131 feature_channels = fpga_features & 0x007f;
104 132 feature_expansion = fpga_features & (1<<15);
105 133  
106   - printf("Board: ");
  134 + puts("FPGA: ");
107 135  
108   - printf("CATCenter Io");
109   -
110   - if (i > 0) {
111   - puts(", serial# ");
112   - puts(buf);
113   - }
114   - puts("\n ");
115   -
116 136 switch (unit_type) {
117 137 case UNITTYPE_CCD_SWITCH:
118 138 printf("CCD-Switch");
... ... @@ -152,8 +172,6 @@
152 172 printf(" %d channel(s)", feature_channels);
153 173  
154 174 printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
155   -
156   - return 0;
157 175 }
158 176  
159 177 /*
160 178  
... ... @@ -161,9 +179,11 @@
161 179 */
162 180 int last_stage_init(void)
163 181 {
164   - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
  182 + struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
165 183 unsigned int k;
166 184  
  185 + print_fpga_info();
  186 +
167 187 miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
168 188 bb_miiphy_read, bb_miiphy_write);
169 189  
... ... @@ -174,5 +194,34 @@
174 194 out_le16(&fpga->quad_serdes_reset, 0);
175 195  
176 196 return 0;
  197 +}
  198 +
  199 +void gd405ep_init(void)
  200 +{
  201 +}
  202 +
  203 +void gd405ep_set_fpga_reset(unsigned state)
  204 +{
  205 + if (state) {
  206 + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
  207 + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
  208 + } else {
  209 + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
  210 + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
  211 + }
  212 +}
  213 +
  214 +void gd405ep_setup_hw(void)
  215 +{
  216 + /*
  217 + * set "startup-finished"-gpios
  218 + */
  219 + gpio_write_bit(21, 0);
  220 + gpio_write_bit(22, 1);
  221 +}
  222 +
  223 +int gd405ep_get_fpga_done(unsigned fpga)
  224 +{
  225 + return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
177 226 }
board/gdsys/405ep/iocon.c
Diff comments   View file @ e0f6a4e
... ... @@ -27,10 +27,15 @@
27 27 #include <asm/io.h>
28 28 #include <asm/ppc4xx-gpio.h>
29 29  
  30 +#include "405ep.h"
30 31 #include <gdsys_fpga.h>
31 32  
32 33 #include "../common/osd.h"
33 34  
  35 +#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
  36 +#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
  37 +#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  38 +
34 39 enum {
35 40 UNITTYPE_MAIN_SERVER = 0,
36 41 UNITTYPE_MAIN_USER = 1,
... ... @@ -69,9 +74,25 @@
69 74 */
70 75 int checkboard(void)
71 76 {
72   - char buf[64];
73   - int i = getenv_f("serial#", buf, sizeof(buf));
74   - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
  77 + char *s = getenv("serial#");
  78 +
  79 + puts("Board: ");
  80 +
  81 + puts("IoCon");
  82 +
  83 + if (s != NULL) {
  84 + puts(", serial# ");
  85 + puts(s);
  86 + }
  87 +
  88 + puts("\n");
  89 +
  90 + return 0;
  91 +}
  92 +
  93 +static void print_fpga_info(void)
  94 +{
  95 + struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
75 96 u16 versions = in_le16(&fpga->versions);
76 97 u16 fpga_version = in_le16(&fpga->fpga_version);
77 98 u16 fpga_features = in_le16(&fpga->fpga_features);
... ... @@ -95,16 +116,6 @@
95 116 feature_carriers = (fpga_features & 0x000c) >> 2;
96 117 feature_video_channels = fpga_features & 0x0003;
97 118  
98   - printf("Board: ");
99   -
100   - printf("IoCon");
101   -
102   - if (i > 0) {
103   - puts(", serial# ");
104   - puts(buf);
105   - }
106   - puts("\n ");
107   -
108 119 switch (unit_type) {
109 120 case UNITTYPE_MAIN_USER:
110 121 printf("Mainchannel");
111 122  
... ... @@ -205,12 +216,12 @@
205 216 printf(", %d carrier(s)", feature_carriers);
206 217  
207 218 printf(", %d video channel(s)\n", feature_video_channels);
208   -
209   - return 0;
210 219 }
211 220  
212 221 int last_stage_init(void)
213 222 {
  223 + print_fpga_info();
  224 +
214 225 return osd_probe(0);
215 226 }
216 227  
... ... @@ -230,5 +241,34 @@
230 241 int fpga_gpio_get(int pin)
231 242 {
232 243 return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
  244 +}
  245 +
  246 +void gd405ep_init(void)
  247 +{
  248 +}
  249 +
  250 +void gd405ep_set_fpga_reset(unsigned state)
  251 +{
  252 + if (state) {
  253 + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
  254 + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
  255 + } else {
  256 + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
  257 + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
  258 + }
  259 +}
  260 +
  261 +void gd405ep_setup_hw(void)
  262 +{
  263 + /*
  264 + * set "startup-finished"-gpios
  265 + */
  266 + gpio_write_bit(21, 0);
  267 + gpio_write_bit(22, 1);
  268 +}
  269 +
  270 +int gd405ep_get_fpga_done(unsigned fpga)
  271 +{
  272 + return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
233 273 }
board/gdsys/405ep/neo.c
Diff comments   View file @ e0f6a4e
  1 +/*
  2 + * (C) Copyright 2011
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +#include <command.h>
  26 +#include <asm/processor.h>
  27 +#include <asm/io.h>
  28 +#include <asm/ppc4xx-gpio.h>
  29 +#include <dtt.h>
  30 +
  31 +#include "405ep.h"
  32 +#include <gdsys_fpga.h>
  33 +
  34 +#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
  35 +#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
  36 +#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  37 +
  38 +enum {
  39 + UNITTYPE_CCX16 = 1,
  40 + UNITTYPE_CCIP216 = 2,
  41 +};
  42 +
  43 +enum {
  44 + HWVER_300 = 3,
  45 +};
  46 +
  47 +int misc_init_r(void)
  48 +{
  49 + /* startup fans */
  50 + dtt_init();
  51 +
  52 + return 0;
  53 +}
  54 +
  55 +int checkboard(void)
  56 +{
  57 + char *s = getenv("serial#");
  58 +
  59 + puts("Board: CATCenter Neo");
  60 +
  61 + if (s != NULL) {
  62 + puts(", serial# ");
  63 + puts(s);
  64 + }
  65 +
  66 + puts("\n");
  67 +
  68 + return 0;
  69 +}
  70 +
  71 +static void print_fpga_info(void)
  72 +{
  73 + struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
  74 + u16 versions = in_le16(&fpga->versions);
  75 + u16 fpga_version = in_le16(&fpga->fpga_version);
  76 + u16 fpga_features = in_le16(&fpga->fpga_features);
  77 + int fpga_state = get_fpga_state(0);
  78 + unsigned unit_type;
  79 + unsigned hardware_version;
  80 + unsigned feature_channels;
  81 +
  82 + puts("FPGA: ");
  83 + if (fpga_state & FPGA_STATE_DONE_FAILED) {
  84 + printf(" done timed out\n");
  85 + return;
  86 + }
  87 +
  88 + if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
  89 + printf(" refelectione test failed\n");
  90 + return;
  91 + }
  92 +
  93 + unit_type = (versions & 0xf000) >> 12;
  94 + hardware_version = versions & 0x000f;
  95 + feature_channels = fpga_features & 0x007f;
  96 +
  97 + switch (unit_type) {
  98 + case UNITTYPE_CCX16:
  99 + printf("CCX-Switch");
  100 + break;
  101 +
  102 + default:
  103 + printf("UnitType %d(not supported)", unit_type);
  104 + break;
  105 + }
  106 +
  107 + switch (hardware_version) {
  108 + case HWVER_300:
  109 + printf(" HW-Ver 3.00-3.12\n");
  110 + break;
  111 +
  112 + default:
  113 + printf(" HW-Ver %d(not supported)\n",
  114 + hardware_version);
  115 + break;
  116 + }
  117 +
  118 + printf(" FPGA V %d.%02d, features:",
  119 + fpga_version / 100, fpga_version % 100);
  120 +
  121 + printf(" %d channel(s)\n", feature_channels);
  122 +}
  123 +
  124 +int last_stage_init(void)
  125 +{
  126 + print_fpga_info();
  127 +
  128 + return 0;
  129 +}
  130 +
  131 +void gd405ep_init(void)
  132 +{
  133 +}
  134 +
  135 +void gd405ep_set_fpga_reset(unsigned state)
  136 +{
  137 + if (state) {
  138 + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
  139 + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
  140 + } else {
  141 + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
  142 + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
  143 + }
  144 +}
  145 +
  146 +void gd405ep_setup_hw(void)
  147 +{
  148 + /*
  149 + * set "startup-finished"-gpios
  150 + */
  151 + gpio_write_bit(21, 0);
  152 + gpio_write_bit(22, 1);
  153 +}
  154 +
  155 +int gd405ep_get_fpga_done(unsigned fpga)
  156 +{
  157 + /*
  158 + * Neo hardware has no FPGA-DONE GPIO
  159 + */
  160 + return 1;
  161 +}
board/gdsys/405ex/405ex.c
Diff comments   View file @ e0f6a4e
... ... @@ -219,7 +219,8 @@
219 219 gd405ex_set_fpga_reset(0);
220 220  
221 221 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
222   - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
  222 + struct ihs_fpga *fpga =
  223 + (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
223 224 #ifdef CONFIG_SYS_FPGA_NO_RFL_HI
224 225 u16 *reflection_target = &fpga->reflection_low;
225 226 #else
board/gdsys/405ex/io64.c
Diff comments   View file @ e0f6a4e
... ... @@ -100,7 +100,7 @@
100 100  
101 101 static void print_fpga_info(unsigned dev)
102 102 {
103   - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
  103 + struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
104 104 u16 versions = in_le16(&fpga->versions);
105 105 u16 fpga_version = in_le16(&fpga->fpga_version);
106 106 u16 fpga_features = in_le16(&fpga->fpga_features);
... ... @@ -242,8 +242,8 @@
242 242 {
243 243 unsigned int k;
244 244 unsigned int fpga;
245   - ihs_fpga_t *fpga0 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
246   - ihs_fpga_t *fpga1 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(1);
  245 + struct ihs_fpga *fpga0 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
  246 + struct ihs_fpga *fpga1 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(1);
247 247 int failed = 0;
248 248 char str_phys[] = "Setup PHYs -";
249 249 char str_serdes[] = "Start SERDES blocks";
board/gdsys/common/osd.c
Diff comments   View file @ e0f6a4e
... ... @@ -70,8 +70,8 @@
70 70 #if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
71 71 static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
72 72 {
73   - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
74   - ihs_i2c_t *i2c = &fpga->i2c;
  73 + struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
  74 + struct ihs_i2c *i2c = &fpga->i2c;
75 75  
76 76 while (in_le16(&fpga->extended_interrupt) & (1 << 12))
77 77 ;
... ... @@ -81,8 +81,8 @@
81 81  
82 82 static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
83 83 {
84   - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
85   - ihs_i2c_t *i2c = &fpga->i2c;
  84 + struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
  85 + struct ihs_i2c *i2c = &fpga->i2c;
86 86 unsigned int ctr = 0;
87 87  
88 88 while (in_le16(&fpga->extended_interrupt) & (1 << 12))
... ... @@ -129,7 +129,7 @@
129 129  
130 130 static void mpc92469ac_set(unsigned screen, unsigned int fout)
131 131 {
132   - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
  132 + struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
133 133 unsigned int n;
134 134 unsigned int m;
135 135 unsigned int bitval = 0;
... ... @@ -265,8 +265,8 @@
265 265 static int osd_write_videomem(unsigned screen, unsigned offset,
266 266 u16 *data, size_t charcount)
267 267 {
268   - ihs_fpga_t *fpga =
269   - (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
  268 + struct ihs_fpga *fpga =
  269 + (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(screen);
270 270 unsigned int k;
271 271  
272 272 for (k = 0; k < charcount; ++k) {
... ... @@ -318,8 +318,8 @@
318 318  
319 319 int osd_probe(unsigned screen)
320 320 {
321   - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
322   - ihs_osd_t *osd = &fpga->osd;
  321 + struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
  322 + struct ihs_osd *osd = &fpga->osd;
323 323 u16 version = in_le16(&osd->version);
324 324 u16 features = in_le16(&osd->features);
325 325 unsigned width;
board/gdsys/neo/Makefile
View file @ e0f6a4e
1   -#
2   -# (C) Copyright 2007
3   -# Stefan Roese, DENX Software Engineering, sr@denx.de.
4   -#
5   -# See file CREDITS for list of people who contributed to this
6   -# project.
7   -#
8   -# This program is free software; you can redistribute it and/or
9   -# modify it under the terms of the GNU General Public License as
10   -# published by the Free Software Foundation; either version 2 of
11   -# the License, or (at your option) any later version.
12   -#
13   -# This program is distributed in the hope that it will be useful,
14   -# but WITHOUT ANY WARRANTY; without even the implied warranty of
15   -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   -# GNU General Public License for more details.
17   -#
18   -# You should have received a copy of the GNU General Public License
19   -# along with this program; if not, write to the Free Software
20   -# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   -# MA 02111-1307 USA
22   -#
23   -
24   -include $(TOPDIR)/config.mk
25   -
26   -LIB = $(obj)lib$(BOARD).o
27   -
28   -COBJS = $(BOARD).o
29   -SOBJS =
30   -
31   -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
32   -OBJS := $(addprefix $(obj),$(COBJS))
33   -SOBJS := $(addprefix $(obj),$(SOBJS))
34   -
35   -$(LIB): $(OBJS) $(SOBJS)
36   - $(call cmd_link_o_target, $(OBJS) $(SOBJS))
37   -
38   -#########################################################################
39   -
40   -# defines $(obj).depend target
41   -include $(SRCTREE)/rules.mk
42   -
43   -sinclude $(obj).depend
44   -
45   -#########################################################################
board/gdsys/neo/neo.c
View file @ e0f6a4e
1   -/*
2   - * (C) Copyright 2007-2008
3   - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -
24   -#include <common.h>
25   -#include <command.h>
26   -#include <asm/processor.h>
27   -#include <asm/io.h>
28   -
29   -#define HWTYPE_CCX16 1
30   -#define HWREV_300 3
31   -
32   -int board_early_init_f(void)
33   -{
34   - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
35   - mtdcr(UIC0ER, 0x00000000); /* disable all ints */
36   - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
37   - mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
38   - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
39   - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
40   - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
41   -
42   - /*
43   - * EBC Configuration Register: set ready timeout to 512 ebc-clks
44   - * -> ca. 15 us
45   - */
46   - mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
47   -
48   - return 0;
49   -}
50   -
51   -/*
52   - * Check Board Identity:
53   - */
54   -int checkboard(void)
55   -{
56   - char buf[64];
57   - int i = getenv_f("serial#", buf, sizeof(buf));
58   - u16 val = in_le16((void *)CONFIG_FPGA_BASE + 2);
59   - u8 unit_type;
60   - u8 hardware_cpu_ports;
61   - u8 hardware_con_ports;
62   - u8 hardware_version;
63   -
64   - printf("Board: CATCenter Neo");
65   -
66   - if (i > 0) {
67   - puts(", serial# ");
68   - puts(buf);
69   - }
70   - puts("\n ");
71   -
72   - unit_type = (val & 0xf000) >> 12;
73   - hardware_cpu_ports = ((val & 0x0f00) >> 8) * 8;
74   - hardware_con_ports = ((val & 0x00f0) >> 4) * 2;
75   - hardware_version = val & 0x000f;
76   -
77   - switch (unit_type) {
78   - case HWTYPE_CCX16:
79   - printf("CCX16-FPGA (80 UARTs)");
80   - break;
81   -
82   - default:
83   - printf("UnitType %d, unsupported", unit_type);
84   - break;
85   - }
86   -
87   - printf(", %d cpu ports, %d console ports,",
88   - hardware_cpu_ports, hardware_con_ports);
89   -
90   - switch (hardware_version) {
91   - case HWREV_300:
92   - printf(" HW-Ver 3.00\n");
93   - break;
94   -
95   - default:
96   - printf(" HW-Ver %d, unsupported\n",
97   - hardware_version);
98   - break;
99   - }
100   -
101   - return 0;
102   -}
... ... @@ -990,7 +990,7 @@
990 990 io powerpc ppc4xx 405ep gdsys
991 991 io64 powerpc ppc4xx 405ex gdsys
992 992 iocon powerpc ppc4xx 405ep gdsys
993   -neo powerpc ppc4xx - gdsys
  993 +neo powerpc ppc4xx 405ep gdsys
994 994 icon powerpc ppc4xx - mosaixtech
995 995 MIP405 powerpc ppc4xx mip405 mpl
996 996 MIP405T powerpc ppc4xx mip405 mpl - MIP405:MIP405T
include/configs/dlvision-10g.h
Diff comments   View file @ e0f6a4e
... ... @@ -34,10 +34,12 @@
34 34 * Include common defines/options for all AMCC eval boards
35 35 */
36 36 #define CONFIG_HOSTNAME dlvsion-10g
37   -#define CONFIG_IDENT_STRING " dlvision-10g 0.02"
  37 +#define CONFIG_IDENT_STRING " dlvision-10g 0.03"
38 38 #include "amcc-common.h"
39 39  
40   -#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
  40 +#define CONFIG_BOARD_EARLY_INIT_F
  41 +#define CONFIG_BOARD_EARLY_INIT_R
  42 +#define CONFIG_MISC_INIT_R
41 43 #define CONFIG_LAST_STAGE_INIT
42 44  
43 45 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
... ... @@ -80,6 +82,7 @@
80 82 * Commands additional to the ones defined in amcc-common.h
81 83 */
82 84 #define CONFIG_CMD_CACHE
  85 +#define CONFIG_CMD_DTT
83 86 #undef CONFIG_CMD_EEPROM
84 87  
85 88 /*
... ... @@ -115,7 +118,7 @@
115 118  
116 119 /* Temp sensor/hwmon/dtt */
117 120 #define CONFIG_DTT_LM63 1 /* National LM63 */
118   -#define CONFIG_DTT_SENSORS { 0x4c, 0x4e } /* Sensor addresses */
  121 +#define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 } /* Sensor addresses */
119 122 #define CONFIG_DTT_PWM_LOOKUPTABLE \
120 123 { { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
121 124 { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
include/configs/gdppc440etx.h
Diff comments   View file @ e0f6a4e
... ... @@ -50,6 +50,10 @@
50 50 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/
51 51 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
52 52  
  53 +#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
  54 +#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
  55 +#define CONFIG_AUTOBOOT_STOP_STR " "
  56 +
53 57 /*
54 58 * Base addresses -- Note these are effective addresses where the
55 59 * actual resources get mapped (not physical addresses)
include/configs/intip.h
Diff comments   View file @ e0f6a4e
... ... @@ -37,10 +37,10 @@
37 37 #define CONFIG_460EX 1 /* Specific PPC460EX */
38 38 #ifdef CONFIG_DEVCONCENTER
39 39 #define CONFIG_HOSTNAME devconcenter
40   -#define CONFIG_IDENT_STRING " devconcenter 0.05"
  40 +#define CONFIG_IDENT_STRING " devconcenter 0.06"
41 41 #else
42 42 #define CONFIG_HOSTNAME intip
43   -#define CONFIG_IDENT_STRING " intip 0.05"
  43 +#define CONFIG_IDENT_STRING " intip 0.06"
44 44 #endif
45 45 #define CONFIG_440 1
46 46 #define CONFIG_4xx 1 /* ... PPC4xx family */
include/configs/io.h
Diff comments   View file @ e0f6a4e
... ... @@ -34,11 +34,13 @@
34 34 * Include common defines/options for all AMCC eval boards
35 35 */
36 36 #define CONFIG_HOSTNAME io
37   -#define CONFIG_IDENT_STRING " io 0.04"
  37 +#define CONFIG_IDENT_STRING " io 0.05"
38 38 #include "amcc-common.h"
39 39  
40   -#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
41   -#define CONFIG_LAST_STAGE_INIT /* call last_stage_init */
  40 +#define CONFIG_BOARD_EARLY_INIT_F
  41 +#define CONFIG_BOARD_EARLY_INIT_R
  42 +#define CONFIG_MISC_INIT_R
  43 +#define CONFIG_LAST_STAGE_INIT
42 44  
43 45 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
44 46  
... ... @@ -48,6 +50,10 @@
48 50 #define PLLMR0_DEFAULT PLLMR0_266_133_66
49 51 #define PLLMR1_DEFAULT PLLMR1_266_133_66
50 52  
  53 +#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
  54 +#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
  55 +#define CONFIG_AUTOBOOT_STOP_STR " "
  56 +
51 57 /* new uImage format support */
52 58 #define CONFIG_FIT
53 59 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
... ... @@ -76,6 +82,7 @@
76 82 * Commands additional to the ones defined in amcc-common.h
77 83 */
78 84 #define CONFIG_CMD_CACHE
  85 +#define CONFIG_CMD_DTT
79 86 #undef CONFIG_CMD_EEPROM
80 87  
81 88 /*
include/configs/io64.h
Diff comments   View file @ e0f6a4e
... ... @@ -53,7 +53,7 @@
53 53 * Include common defines/options for all AMCC eval boards
54 54 */
55 55 #define CONFIG_HOSTNAME io64
56   -#define CONFIG_IDENT_STRING " io64 0.01"
  56 +#define CONFIG_IDENT_STRING " io64 0.02"
57 57 #include "amcc-common.h"
58 58  
59 59 #define CONFIG_BOARD_EARLY_INIT_F
include/configs/iocon.h
Diff comments   View file @ e0f6a4e
... ... @@ -34,10 +34,11 @@
34 34 * Include common defines/options for all AMCC eval boards
35 35 */
36 36 #define CONFIG_HOSTNAME iocon
37   -#define CONFIG_IDENT_STRING " iocon 0.03"
  37 +#define CONFIG_IDENT_STRING " iocon 0.04"
38 38 #include "amcc-common.h"
39 39  
40   -#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
  40 +#define CONFIG_BOARD_EARLY_INIT_F
  41 +#define CONFIG_BOARD_EARLY_INIT_R
41 42 #define CONFIG_LAST_STAGE_INIT
42 43  
43 44 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
... ... @@ -47,6 +48,10 @@
47 48 */
48 49 #define PLLMR0_DEFAULT PLLMR0_266_133_66
49 50 #define PLLMR1_DEFAULT PLLMR1_266_133_66
  51 +
  52 +#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
  53 +#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
  54 +#define CONFIG_AUTOBOOT_STOP_STR " "
50 55  
51 56 /* new uImage format support */
52 57 #define CONFIG_FIT
include/configs/neo.h
Diff comments   View file @ e0f6a4e
... ... @@ -35,9 +35,13 @@
35 35 * Include common defines/options for all AMCC eval boards
36 36 */
37 37 #define CONFIG_HOSTNAME neo
  38 +#define CONFIG_IDENT_STRING " neo 0.01"
38 39 #include "amcc-common.h"
39 40  
40   -#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
  41 +#define CONFIG_BOARD_EARLY_INIT_F
  42 +#define CONFIG_BOARD_EARLY_INIT_R
  43 +#define CONFIG_MISC_INIT_R
  44 +#define CONFIG_LAST_STAGE_INIT
41 45  
42 46 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
43 47  
44 48  
45 49  
... ... @@ -149,53 +153,53 @@
149 153  
150 154 #ifdef CONFIG_ENV_IS_IN_FLASH
151 155 #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
152   -#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
153   -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
  156 +#define CONFIG_ENV_ADDR 0xFFF00000
  157 +#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
154 158  
155 159 /* Address and size of Redundant Environment Sector */
156   -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
  160 +#define CONFIG_ENV_ADDR_REDUND 0xFFF20000
157 161 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
158 162 #endif
159 163  
160 164 /*
161 165 * PPC405 GPIO Configuration
162 166 */
163   -#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
164   -{ \
165   -/* GPIO Core 0 */ \
166   -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
167   -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
168   -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
169   -{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
170   -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
171   -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
172   -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
173   -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
174   -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
175   -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
176   -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
177   -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
178   -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
179   -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
180   -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
181   -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
182   -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
183   -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
184   -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
185   -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
186   -{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
187   -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
188   -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
189   -{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
190   -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
191   -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
192   -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
193   -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
194   -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
195   -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
196   -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
197   -{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
198   -} \
  167 +#define CONFIG_SYS_4xx_GPIO_TABLE { \
  168 +{ \
  169 +/* GPIO Core 0 */ \
  170 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
  171 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
  172 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
  173 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
  174 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
  175 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
  176 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
  177 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
  178 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
  179 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
  180 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
  181 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
  182 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
  183 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
  184 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
  185 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
  186 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
  187 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
  188 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
  189 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
  190 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
  191 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
  192 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
  193 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
  194 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
  195 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
  196 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
  197 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
  198 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
  199 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
  200 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
  201 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
  202 +} \
199 203 }
200 204  
201 205 /*
202 206  
203 207  
204 208  
... ... @@ -226,13 +230,23 @@
226 230 #define CONFIG_SYS_EBC_PB1CR 0xFB85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
227 231  
228 232 /* Memory Bank 2 (FPGA) initialization */
229   -#define CONFIG_FPGA_BASE 0x7f100000
  233 +#define CONFIG_SYS_FPGA0_BASE 0x7f100000
230 234 #define CONFIG_SYS_EBC_PB2AP 0x92015480
231 235 #define CONFIG_SYS_EBC_PB2CR 0x7f11a000 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
232 236  
  237 +#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
  238 +
  239 +#define CONFIG_SYS_FPGA_COUNT 1
  240 +
233 241 /* Memory Bank 3 (Latches) initialization */
  242 +#define CONFIG_SYS_LATCH_BASE 0x7f200000
234 243 #define CONFIG_SYS_EBC_PB3AP 0x92015480
235 244 #define CONFIG_SYS_EBC_PB3CR 0x7f21a000 /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
  245 +
  246 +#define CONFIG_SYS_LATCH0_RESET 0xffff
  247 +#define CONFIG_SYS_LATCH0_BOOT 0xffff
  248 +#define CONFIG_SYS_LATCH1_RESET 0xffbf
  249 +#define CONFIG_SYS_LATCH1_BOOT 0xffff
236 250  
237 251 #endif /* __CONFIG_H */
include/gdsys_fpga.h
Diff comments   View file @ e0f6a4e
... ... @@ -35,20 +35,20 @@
35 35 int get_fpga_state(unsigned dev);
36 36 void print_fpga_state(unsigned dev);
37 37  
38   -typedef struct ihs_gpio {
  38 +struct ihs_gpio {
39 39 u16 read;
40 40 u16 clear;
41 41 u16 set;
42   -} ihs_gpio_t;
  42 +};
43 43  
44   -typedef struct ihs_i2c {
  44 +struct ihs_i2c {
45 45 u16 write_mailbox;
46 46 u16 write_mailbox_ext;
47 47 u16 read_mailbox;
48 48 u16 read_mailbox_ext;
49   -} ihs_i2c_t;
  49 +};
50 50  
51   -typedef struct ihs_osd {
  51 +struct ihs_osd {
52 52 u16 version;
53 53 u16 features;
54 54 u16 control;
55 55  
56 56  
... ... @@ -56,10 +56,21 @@
56 56 u16 xy_scale;
57 57 u16 x_pos;
58 58 u16 y_pos;
59   -} ihs_osd_t;
  59 +};
60 60  
  61 +#ifdef CONFIG_NEO
  62 +struct ihs_fpga {
  63 + u16 reflection_low; /* 0x0000 */
  64 + u16 versions; /* 0x0002 */
  65 + u16 fpga_features; /* 0x0004 */
  66 + u16 fpga_version; /* 0x0006 */
  67 + u16 reserved_0[8187]; /* 0x0008 */
  68 + u16 reflection_high; /* 0x3ffe */
  69 +};
  70 +#endif
  71 +
61 72 #ifdef CONFIG_IO
62   -typedef struct ihs_fpga {
  73 +struct ihs_fpga {
63 74 u16 reflection_low; /* 0x0000 */
64 75 u16 versions; /* 0x0002 */
65 76 u16 fpga_features; /* 0x0004 */
66 77  
... ... @@ -68,11 +79,11 @@
68 79 u16 quad_serdes_reset; /* 0x0012 */
69 80 u16 reserved_1[8181]; /* 0x0014 */
70 81 u16 reflection_high; /* 0x3ffe */
71   -} ihs_fpga_t;
  82 +};
72 83 #endif
73 84  
74 85 #ifdef CONFIG_IO64
75   -typedef struct ihs_fpga {
  86 +struct ihs_fpga {
76 87 u16 reflection_low; /* 0x0000 */
77 88 u16 versions; /* 0x0002 */
78 89 u16 fpga_features; /* 0x0004 */
79 90  
80 91  
81 92  
82 93  
83 94  
... ... @@ -87,30 +98,30 @@
87 98 u16 ch0_hicb_config_int;/* 0x0502 */
88 99 u16 reserved_3[7549]; /* 0x0504 */
89 100 u16 reflection_high; /* 0x3ffe */
90   -} ihs_fpga_t;
  101 +};
91 102 #endif
92 103  
93 104 #ifdef CONFIG_IOCON
94   -typedef struct ihs_fpga {
  105 +struct ihs_fpga {
95 106 u16 reflection_low; /* 0x0000 */
96 107 u16 versions; /* 0x0002 */
97 108 u16 fpga_version; /* 0x0004 */
98 109 u16 fpga_features; /* 0x0006 */
99 110 u16 reserved_0[6]; /* 0x0008 */
100   - ihs_gpio_t gpio; /* 0x0014 */
  111 + struct ihs_gpio gpio; /* 0x0014 */
101 112 u16 mpc3w_control; /* 0x001a */
102 113 u16 reserved_1[19]; /* 0x001c */
103 114 u16 videocontrol; /* 0x0042 */
104 115 u16 reserved_2[93]; /* 0x0044 */
105 116 u16 reflection_high; /* 0x00fe */
106   - ihs_osd_t osd; /* 0x0100 */
107   - u16 reserved_3[88]; /* 0x010e */
  117 + struct ihs_osd osd; /* 0x0100 */
  118 + u16 reserved_3[889]; /* 0x010e */
108 119 u16 videomem; /* 0x0800 */
109   -} ihs_fpga_t;
  120 +};
110 121 #endif
111 122  
112 123 #ifdef CONFIG_DLVISION_10G
113   -typedef struct ihs_fpga {
  124 +struct ihs_fpga {
114 125 u16 reflection_low; /* 0x0000 */
115 126 u16 versions; /* 0x0002 */
116 127 u16 fpga_version; /* 0x0004 */
117 128  
118 129  
... ... @@ -118,16 +129,16 @@
118 129 u16 reserved_0[10]; /* 0x0008 */
119 130 u16 extended_interrupt; /* 0x001c */
120 131 u16 reserved_1[9]; /* 0x001e */
121   - ihs_i2c_t i2c; /* 0x0030 */
  132 + struct ihs_i2c i2c; /* 0x0030 */
122 133 u16 reserved_2[16]; /* 0x0038 */
123 134 u16 mpc3w_control; /* 0x0058 */
124 135 u16 reserved_3[34]; /* 0x005a */
125 136 u16 videocontrol; /* 0x009e */
126 137 u16 reserved_4[176]; /* 0x00a0 */
127   - ihs_osd_t osd; /* 0x0200 */
  138 + struct ihs_osd osd; /* 0x0200 */
128 139 u16 reserved_5[761]; /* 0x020e */
129 140 u16 videomem; /* 0x0800 */
130   -} ihs_fpga_t;
  141 +};
131 142 #endif
132 143  
133 144 #endif