Eric Lee / smarc-uboot

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Commit e1b342f434f326271799363383581c0ff22a0bfe

Authored by Eric Lee
1 parent 76e077cbbc
Exists in v2016.05-smarct4x

Bug Fix for eMMC Boot up

Showing 2 changed files with 6 additions and 7 deletions Inline Diff

arch/arm/cpu/armv7/am33xx/board.c
Diff comments   View file @ e1b342f
1 /* 1 /*
2 * board.c 2 * board.c
3 * 3 *
4 * Common board functions for AM33XX based boards 4 * Common board functions for AM33XX based boards
5 * 5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 * 7 *
8 * SPDX-License-Identifier: GPL-2.0+ 8 * SPDX-License-Identifier: GPL-2.0+
9 */ 9 */
10 10
11 #include <common.h> 11 #include <common.h>
12 #include <dm.h> 12 #include <dm.h>
13 #include <errno.h> 13 #include <errno.h>
14 #include <ns16550.h> 14 #include <ns16550.h>
15 #include <spl.h> 15 #include <spl.h>
16 #include <asm/arch/cpu.h> 16 #include <asm/arch/cpu.h>
17 #include <asm/arch/hardware.h> 17 #include <asm/arch/hardware.h>
18 #include <asm/arch/omap.h> 18 #include <asm/arch/omap.h>
19 #include <asm/arch/ddr_defs.h> 19 #include <asm/arch/ddr_defs.h>
20 #include <asm/arch/clock.h> 20 #include <asm/arch/clock.h>
21 #include <asm/arch/gpio.h> 21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mem.h> 22 #include <asm/arch/mem.h>
23 #include <asm/arch/mmc_host_def.h> 23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/sys_proto.h> 24 #include <asm/arch/sys_proto.h>
25 #include <asm/io.h> 25 #include <asm/io.h>
26 #include <asm/emif.h> 26 #include <asm/emif.h>
27 #include <asm/gpio.h> 27 #include <asm/gpio.h>
28 #include <i2c.h> 28 #include <i2c.h>
29 #include <miiphy.h> 29 #include <miiphy.h>
30 #include <cpsw.h> 30 #include <cpsw.h>
31 #include <asm/errno.h> 31 #include <asm/errno.h>
32 #include <linux/compiler.h> 32 #include <linux/compiler.h>
33 #include <linux/usb/ch9.h> 33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h> 34 #include <linux/usb/gadget.h>
35 #include <linux/usb/musb.h> 35 #include <linux/usb/musb.h>
36 #include <asm/omap_musb.h> 36 #include <asm/omap_musb.h>
37 #include <asm/davinci_rtc.h> 37 #include <asm/davinci_rtc.h>
38 38
39 DECLARE_GLOBAL_DATA_PTR; 39 DECLARE_GLOBAL_DATA_PTR;
40 40
41 #if !CONFIG_IS_ENABLED(OF_CONTROL) 41 #if !CONFIG_IS_ENABLED(OF_CONTROL)
42 static const struct ns16550_platdata am33xx_serial[] = { 42 static const struct ns16550_platdata am33xx_serial[] = {
43 { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 43 { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
44 # ifdef CONFIG_SYS_NS16550_COM2 44 # ifdef CONFIG_SYS_NS16550_COM2
45 { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 45 { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
46 # ifdef CONFIG_SYS_NS16550_COM3 46 # ifdef CONFIG_SYS_NS16550_COM3
47 { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 47 { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
48 { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 48 { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
49 { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 49 { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
50 { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 50 { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
51 # endif 51 # endif
52 # endif 52 # endif
53 }; 53 };
54 54
55 U_BOOT_DEVICES(am33xx_uarts) = { 55 U_BOOT_DEVICES(am33xx_uarts) = {
56 { "ns16550_serial", &am33xx_serial[0] }, 56 { "ns16550_serial", &am33xx_serial[0] },
57 # ifdef CONFIG_SYS_NS16550_COM2 57 # ifdef CONFIG_SYS_NS16550_COM2
58 { "ns16550_serial", &am33xx_serial[1] }, 58 { "ns16550_serial", &am33xx_serial[1] },
59 # ifdef CONFIG_SYS_NS16550_COM3 59 # ifdef CONFIG_SYS_NS16550_COM3
60 { "ns16550_serial", &am33xx_serial[2] }, 60 { "ns16550_serial", &am33xx_serial[2] },
61 { "ns16550_serial", &am33xx_serial[3] }, 61 { "ns16550_serial", &am33xx_serial[3] },
62 { "ns16550_serial", &am33xx_serial[4] }, 62 { "ns16550_serial", &am33xx_serial[4] },
63 { "ns16550_serial", &am33xx_serial[5] }, 63 { "ns16550_serial", &am33xx_serial[5] },
64 # endif 64 # endif
65 # endif 65 # endif
66 }; 66 };
67 67
68 #ifdef CONFIG_DM_GPIO 68 #ifdef CONFIG_DM_GPIO
69 static const struct omap_gpio_platdata am33xx_gpio[] = { 69 static const struct omap_gpio_platdata am33xx_gpio[] = {
70 { 0, AM33XX_GPIO0_BASE }, 70 { 0, AM33XX_GPIO0_BASE },
71 { 1, AM33XX_GPIO1_BASE }, 71 { 1, AM33XX_GPIO1_BASE },
72 { 2, AM33XX_GPIO2_BASE }, 72 { 2, AM33XX_GPIO2_BASE },
73 { 3, AM33XX_GPIO3_BASE }, 73 { 3, AM33XX_GPIO3_BASE },
74 #ifdef CONFIG_AM43XX 74 #ifdef CONFIG_AM43XX
75 { 4, AM33XX_GPIO4_BASE }, 75 { 4, AM33XX_GPIO4_BASE },
76 { 5, AM33XX_GPIO5_BASE }, 76 { 5, AM33XX_GPIO5_BASE },
77 #endif 77 #endif
78 }; 78 };
79 79
80 U_BOOT_DEVICES(am33xx_gpios) = { 80 U_BOOT_DEVICES(am33xx_gpios) = {
81 { "gpio_omap", &am33xx_gpio[0] }, 81 { "gpio_omap", &am33xx_gpio[0] },
82 { "gpio_omap", &am33xx_gpio[1] }, 82 { "gpio_omap", &am33xx_gpio[1] },
83 { "gpio_omap", &am33xx_gpio[2] }, 83 { "gpio_omap", &am33xx_gpio[2] },
84 { "gpio_omap", &am33xx_gpio[3] }, 84 { "gpio_omap", &am33xx_gpio[3] },
85 #ifdef CONFIG_AM43XX 85 #ifdef CONFIG_AM43XX
86 { "gpio_omap", &am33xx_gpio[4] }, 86 { "gpio_omap", &am33xx_gpio[4] },
87 { "gpio_omap", &am33xx_gpio[5] }, 87 { "gpio_omap", &am33xx_gpio[5] },
88 #endif 88 #endif
89 }; 89 };
90 #endif 90 #endif
91 #endif 91 #endif
92 92
93 #ifndef CONFIG_DM_GPIO 93 #ifndef CONFIG_DM_GPIO
94 static const struct gpio_bank gpio_bank_am33xx[] = { 94 static const struct gpio_bank gpio_bank_am33xx[] = {
95 { (void *)AM33XX_GPIO0_BASE }, 95 { (void *)AM33XX_GPIO0_BASE },
96 { (void *)AM33XX_GPIO1_BASE }, 96 { (void *)AM33XX_GPIO1_BASE },
97 { (void *)AM33XX_GPIO2_BASE }, 97 { (void *)AM33XX_GPIO2_BASE },
98 { (void *)AM33XX_GPIO3_BASE }, 98 { (void *)AM33XX_GPIO3_BASE },
99 #ifdef CONFIG_AM43XX 99 #ifdef CONFIG_AM43XX
100 { (void *)AM33XX_GPIO4_BASE }, 100 { (void *)AM33XX_GPIO4_BASE },
101 { (void *)AM33XX_GPIO5_BASE }, 101 { (void *)AM33XX_GPIO5_BASE },
102 #endif 102 #endif
103 }; 103 };
104 104
105 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; 105 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
106 #endif 106 #endif
107 107
108 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) 108 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
109 int cpu_mmc_init(bd_t *bis) 109 int cpu_mmc_init(bd_t *bis)
110 { 110 {
111 int ret; 111 omap_mmc_init(0, 0, 0, -1, -1);
112 112 omap_mmc_init(1, 0, 0, -1, -1);
113 ret = omap_mmc_init(0, 0, 0, -1, -1); 113 omap_mmc_init(2, 0, 0, -1, -1);
114 if (ret) 114 return 0;
115 return ret;
116
117 return omap_mmc_init(2, 0, 0, -1, -1);
118 } 115 }
116
119 #endif 117 #endif
120 118
121 /* 119 /*
122 * RTC only mode magic value, checked against during boot to see if we have 120 * RTC only mode magic value, checked against during boot to see if we have
123 * a valid config 121 * a valid config
124 */ 122 */
125 #define RTC_MAGIC_VAL 0x8cd0 123 #define RTC_MAGIC_VAL 0x8cd0
126 124
127 /* Board type field bit shift for RTC only mode */ 125 /* Board type field bit shift for RTC only mode */
128 #define RTC_BOARD_TYPE_SHIFT 16 126 #define RTC_BOARD_TYPE_SHIFT 16
129 127
130 /* AM33XX has two MUSB controllers which can be host or gadget */ 128 /* AM33XX has two MUSB controllers which can be host or gadget */
131 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \ 129 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
132 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \ 130 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
133 (!defined(CONFIG_DM_USB)) 131 (!defined(CONFIG_DM_USB))
134 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 132 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
135 133
136 /* USB 2.0 PHY Control */ 134 /* USB 2.0 PHY Control */
137 #define CM_PHY_PWRDN (1 << 0) 135 #define CM_PHY_PWRDN (1 << 0)
138 #define CM_PHY_OTG_PWRDN (1 << 1) 136 #define CM_PHY_OTG_PWRDN (1 << 1)
139 #define OTGVDET_EN (1 << 19) 137 #define OTGVDET_EN (1 << 19)
140 #define OTGSESSENDEN (1 << 20) 138 #define OTGSESSENDEN (1 << 20)
141 139
142 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) 140 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
143 { 141 {
144 if (on) { 142 if (on) {
145 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, 143 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
146 OTGVDET_EN | OTGSESSENDEN); 144 OTGVDET_EN | OTGSESSENDEN);
147 } else { 145 } else {
148 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); 146 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
149 } 147 }
150 } 148 }
151 149
152 static struct musb_hdrc_config musb_config = { 150 static struct musb_hdrc_config musb_config = {
153 .multipoint = 1, 151 .multipoint = 1,
154 .dyn_fifo = 1, 152 .dyn_fifo = 1,
155 .num_eps = 16, 153 .num_eps = 16,
156 .ram_bits = 12, 154 .ram_bits = 12,
157 }; 155 };
158 156
159 #ifdef CONFIG_AM335X_USB0 157 #ifdef CONFIG_AM335X_USB0
160 static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on) 158 static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
161 { 159 {
162 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); 160 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
163 } 161 }
164 162
165 struct omap_musb_board_data otg0_board_data = { 163 struct omap_musb_board_data otg0_board_data = {
166 .set_phy_power = am33xx_otg0_set_phy_power, 164 .set_phy_power = am33xx_otg0_set_phy_power,
167 }; 165 };
168 166
169 static struct musb_hdrc_platform_data otg0_plat = { 167 static struct musb_hdrc_platform_data otg0_plat = {
170 .mode = CONFIG_AM335X_USB0_MODE, 168 .mode = CONFIG_AM335X_USB0_MODE,
171 .config = &musb_config, 169 .config = &musb_config,
172 .power = 50, 170 .power = 50,
173 .platform_ops = &musb_dsps_ops, 171 .platform_ops = &musb_dsps_ops,
174 .board_data = &otg0_board_data, 172 .board_data = &otg0_board_data,
175 }; 173 };
176 #endif 174 #endif
177 175
178 #ifdef CONFIG_AM335X_USB1 176 #ifdef CONFIG_AM335X_USB1
179 static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on) 177 static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
180 { 178 {
181 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); 179 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
182 } 180 }
183 181
184 struct omap_musb_board_data otg1_board_data = { 182 struct omap_musb_board_data otg1_board_data = {
185 .set_phy_power = am33xx_otg1_set_phy_power, 183 .set_phy_power = am33xx_otg1_set_phy_power,
186 }; 184 };
187 185
188 static struct musb_hdrc_platform_data otg1_plat = { 186 static struct musb_hdrc_platform_data otg1_plat = {
189 .mode = CONFIG_AM335X_USB1_MODE, 187 .mode = CONFIG_AM335X_USB1_MODE,
190 .config = &musb_config, 188 .config = &musb_config,
191 .power = 50, 189 .power = 50,
192 .platform_ops = &musb_dsps_ops, 190 .platform_ops = &musb_dsps_ops,
193 .board_data = &otg1_board_data, 191 .board_data = &otg1_board_data,
194 }; 192 };
195 #endif 193 #endif
196 #endif 194 #endif
197 195
198 int arch_misc_init(void) 196 int arch_misc_init(void)
199 { 197 {
200 #ifndef CONFIG_DM_USB 198 #ifndef CONFIG_DM_USB
201 #ifdef CONFIG_AM335X_USB0 199 #ifdef CONFIG_AM335X_USB0
202 musb_register(&otg0_plat, &otg0_board_data, 200 musb_register(&otg0_plat, &otg0_board_data,
203 (void *)USB0_OTG_BASE); 201 (void *)USB0_OTG_BASE);
204 #endif 202 #endif
205 #ifdef CONFIG_AM335X_USB1 203 #ifdef CONFIG_AM335X_USB1
206 musb_register(&otg1_plat, &otg1_board_data, 204 musb_register(&otg1_plat, &otg1_board_data,
207 (void *)USB1_OTG_BASE); 205 (void *)USB1_OTG_BASE);
208 #endif 206 #endif
209 #else 207 #else
210 struct udevice *dev; 208 struct udevice *dev;
211 int ret; 209 int ret;
212 210
213 ret = uclass_first_device(UCLASS_MISC, &dev); 211 ret = uclass_first_device(UCLASS_MISC, &dev);
214 if (ret || !dev) 212 if (ret || !dev)
215 return ret; 213 return ret;
216 214
217 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER) 215 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
218 ret = usb_ether_init(); 216 ret = usb_ether_init();
219 if (ret) { 217 if (ret) {
220 error("USB ether init failed\n"); 218 error("USB ether init failed\n");
221 return ret; 219 return ret;
222 } 220 }
223 #endif 221 #endif
224 #endif 222 #endif
225 return 0; 223 return 0;
226 } 224 }
227 225
228 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 226 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
229 227
230 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \ 228 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
231 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT)) 229 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT))
232 static void rtc32k_unlock(struct davinci_rtc *rtc) 230 static void rtc32k_unlock(struct davinci_rtc *rtc)
233 { 231 {
234 /* 232 /*
235 * Unlock the RTC's registers. For more details please see the 233 * Unlock the RTC's registers. For more details please see the
236 * RTC_SS section of the TRM. In order to unlock we need to 234 * RTC_SS section of the TRM. In order to unlock we need to
237 * write these specific values (keys) in this order. 235 * write these specific values (keys) in this order.
238 */ 236 */
239 writel(RTC_KICK0R_WE, &rtc->kick0r); 237 writel(RTC_KICK0R_WE, &rtc->kick0r);
240 writel(RTC_KICK1R_WE, &rtc->kick1r); 238 writel(RTC_KICK1R_WE, &rtc->kick1r);
241 } 239 }
242 #endif 240 #endif
243 241
244 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT) 242 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT)
245 /* 243 /*
246 * Write contents of the RTC_SCRATCH1 register based on board type 244 * Write contents of the RTC_SCRATCH1 register based on board type
247 * Two things are passed 245 * Two things are passed
248 * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the 246 * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
249 * control gets to kernel, kernel reads the scratchpad register and gets to 247 * control gets to kernel, kernel reads the scratchpad register and gets to
250 * know that bootloader has rtc_only support. 248 * know that bootloader has rtc_only support.
251 * 249 *
252 * Second important thing is the board type (16:31). This is needed in the 250 * Second important thing is the board type (16:31). This is needed in the
253 * rtc_only boot where in we want to avoid costly i2c reads to eeprom to 251 * rtc_only boot where in we want to avoid costly i2c reads to eeprom to
254 * identify the board type and we go ahead and copy the board strings to 252 * identify the board type and we go ahead and copy the board strings to
255 * am43xx_board_name. 253 * am43xx_board_name.
256 */ 254 */
257 void update_rtc_magic(void) 255 void update_rtc_magic(void)
258 { 256 {
259 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 257 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
260 u32 magic = RTC_MAGIC_VAL; 258 u32 magic = RTC_MAGIC_VAL;
261 259
262 magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT); 260 magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
263 261
264 rtc32k_unlock(rtc); 262 rtc32k_unlock(rtc);
265 263
266 /* write magic */ 264 /* write magic */
267 writel(magic, &rtc->scratch1); 265 writel(magic, &rtc->scratch1);
268 } 266 }
269 #endif 267 #endif
270 268
271 /* 269 /*
272 * In the case of non-SPL based booting we'll want to call these 270 * In the case of non-SPL based booting we'll want to call these
273 * functions a tiny bit later as it will require gd to be set and cleared 271 * functions a tiny bit later as it will require gd to be set and cleared
274 * and that's not true in s_init in this case so we cannot do it there. 272 * and that's not true in s_init in this case so we cannot do it there.
275 */ 273 */
276 int board_early_init_f(void) 274 int board_early_init_f(void)
277 { 275 {
278 prcm_init(); 276 prcm_init();
279 set_mux_conf_regs(); 277 set_mux_conf_regs();
280 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT) 278 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT)
281 update_rtc_magic(); 279 update_rtc_magic();
282 #endif 280 #endif
283 return 0; 281 return 0;
284 } 282 }
285 283
286 /* 284 /*
287 * This function is the place to do per-board things such as ramp up the 285 * This function is the place to do per-board things such as ramp up the
288 * MPU clock frequency. 286 * MPU clock frequency.
289 */ 287 */
290 __weak void am33xx_spl_board_init(void) 288 __weak void am33xx_spl_board_init(void)
291 { 289 {
292 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 290 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
293 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); 291 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
294 } 292 }
295 293
296 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 294 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
297 static void rtc32k_enable(void) 295 static void rtc32k_enable(void)
298 { 296 {
299 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 297 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
300 298
301 rtc32k_unlock(rtc); 299 rtc32k_unlock(rtc);
302 300
303 /* Enable the RTC 32K OSC by setting bits 3 and 6. */ 301 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
304 writel((1 << 3) | (1 << 6), &rtc->osc); 302 writel((1 << 3) | (1 << 6), &rtc->osc);
305 } 303 }
306 #endif 304 #endif
307 305
308 static void uart_soft_reset(void) 306 static void uart_soft_reset(void)
309 { 307 {
310 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; 308 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
311 u32 regval; 309 u32 regval;
312 310
313 regval = readl(&uart_base->uartsyscfg); 311 regval = readl(&uart_base->uartsyscfg);
314 regval |= UART_RESET; 312 regval |= UART_RESET;
315 writel(regval, &uart_base->uartsyscfg); 313 writel(regval, &uart_base->uartsyscfg);
316 while ((readl(&uart_base->uartsyssts) & 314 while ((readl(&uart_base->uartsyssts) &
317 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) 315 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
318 ; 316 ;
319 317
320 /* Disable smart idle */ 318 /* Disable smart idle */
321 regval = readl(&uart_base->uartsyscfg); 319 regval = readl(&uart_base->uartsyscfg);
322 regval |= UART_SMART_IDLE_EN; 320 regval |= UART_SMART_IDLE_EN;
323 writel(regval, &uart_base->uartsyscfg); 321 writel(regval, &uart_base->uartsyscfg);
324 } 322 }
325 323
326 static void watchdog_disable(void) 324 static void watchdog_disable(void)
327 { 325 {
328 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 326 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
329 327
330 writel(0xAAAA, &wdtimer->wdtwspr); 328 writel(0xAAAA, &wdtimer->wdtwspr);
331 while (readl(&wdtimer->wdtwwps) != 0x0) 329 while (readl(&wdtimer->wdtwwps) != 0x0)
332 ; 330 ;
333 writel(0x5555, &wdtimer->wdtwspr); 331 writel(0x5555, &wdtimer->wdtwspr);
334 while (readl(&wdtimer->wdtwwps) != 0x0) 332 while (readl(&wdtimer->wdtwwps) != 0x0)
335 ; 333 ;
336 } 334 }
337 335
338 #ifdef CONFIG_SPL_BUILD 336 #ifdef CONFIG_SPL_BUILD
339 void board_init_f(ulong dummy) 337 void board_init_f(ulong dummy)
340 { 338 {
341 board_early_init_f(); 339 board_early_init_f();
342 sdram_init(); 340 sdram_init();
343 } 341 }
344 #endif 342 #endif
345 343
346 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT) 344 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT)
347 /* 345 /*
348 * Check if we are executing rtc-only mode, and resume from it if needed 346 * Check if we are executing rtc-only mode, and resume from it if needed
349 */ 347 */
350 static void rtc_only(void) 348 static void rtc_only(void)
351 { 349 {
352 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 350 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
353 u32 scratch1; 351 u32 scratch1;
354 void (*resume_func)(void); 352 void (*resume_func)(void);
355 353
356 scratch1 = readl(&rtc->scratch1); 354 scratch1 = readl(&rtc->scratch1);
357 355
358 /* 356 /*
359 * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only 357 * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
360 * written to this register when we want to wake up from RTC only 358 * written to this register when we want to wake up from RTC only
361 * mode. Contents of the RTC_SCRATCH1: 359 * mode. Contents of the RTC_SCRATCH1:
362 * bits 0-15: RTC_MAGIC_VAL 360 * bits 0-15: RTC_MAGIC_VAL
363 * bits 16-31: board type (needed for sdram_init) 361 * bits 16-31: board type (needed for sdram_init)
364 */ 362 */
365 if ((scratch1 & 0xffff) != RTC_MAGIC_VAL) 363 if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
366 return; 364 return;
367 365
368 rtc32k_unlock(rtc); 366 rtc32k_unlock(rtc);
369 367
370 /* Clear RTC magic */ 368 /* Clear RTC magic */
371 writel(0, &rtc->scratch1); 369 writel(0, &rtc->scratch1);
372 370
373 /* 371 /*
374 * Update board type based on value stored on RTC_SCRATCH1, this 372 * Update board type based on value stored on RTC_SCRATCH1, this
375 * is done so that we don't need to read the board type from eeprom 373 * is done so that we don't need to read the board type from eeprom
376 * over i2c bus which is expensive 374 * over i2c bus which is expensive
377 */ 375 */
378 rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT); 376 rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
379 377
380 rtc_only_prcm_init(); 378 rtc_only_prcm_init();
381 sdram_init(); 379 sdram_init();
382 380
383 resume_func = (void *)readl(&rtc->scratch0); 381 resume_func = (void *)readl(&rtc->scratch0);
384 if (resume_func) 382 if (resume_func)
385 resume_func(); 383 resume_func();
386 } 384 }
387 #endif 385 #endif
388 386
389 void s_init(void) 387 void s_init(void)
390 { 388 {
391 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT) 389 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT)
392 rtc_only(); 390 rtc_only();
393 #endif 391 #endif
394 /* 392 /*
395 * The ROM will only have set up sufficient pinmux to allow for the 393 * The ROM will only have set up sufficient pinmux to allow for the
396 * first 4KiB NOR to be read, we must finish doing what we know of 394 * first 4KiB NOR to be read, we must finish doing what we know of
397 * the NOR mux in this space in order to continue. 395 * the NOR mux in this space in order to continue.
398 */ 396 */
399 #ifdef CONFIG_NOR_BOOT 397 #ifdef CONFIG_NOR_BOOT
400 enable_norboot_pin_mux(); 398 enable_norboot_pin_mux();
401 #endif 399 #endif
402 watchdog_disable(); 400 watchdog_disable();
403 set_uart_mux_conf(); 401 set_uart_mux_conf();
404 setup_clocks_for_console(); 402 setup_clocks_for_console();
405 uart_soft_reset(); 403 uart_soft_reset();
406 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 404 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
407 /* Enable RTC32K clock */ 405 /* Enable RTC32K clock */
408 rtc32k_enable(); 406 rtc32k_enable();
409 #endif 407 #endif
410 } 408 }
411 #endif 409 #endif
include/configs/smarct437x_evm.h
Diff comments   View file @ e1b342f
1 /* 1 /*
2 * am43xx_evm.h 2 * am43xx_evm.h
3 * 3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #ifndef __CONFIG_SMARCT437X_EVM_H 9 #ifndef __CONFIG_SMARCT437X_EVM_H
10 #define __CONFIG_SMARCT437X_EVM_H 10 #define __CONFIG_SMARCT437X_EVM_H
11 11
12 #define CONFIG_BOARD_LATE_INIT 12 #define CONFIG_BOARD_LATE_INIT
13 #define CONFIG_ARCH_CPU_INIT 13 #define CONFIG_ARCH_CPU_INIT
14 #define CONFIG_SYS_CACHELINE_SIZE 32 14 #define CONFIG_SYS_CACHELINE_SIZE 32
15 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ 15 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */
16 #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ 16 #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
17 17
18 #include <asm/arch/omap.h> 18 #include <asm/arch/omap.h>
19 #define CONFIG_ENV_IS_NOWHERE 19 #define CONFIG_ENV_IS_NOWHERE
20 20
21 /* NS16550 Configuration */ 21 /* NS16550 Configuration */
22 #define CONFIG_SYS_NS16550_CLK 48000000 22 #define CONFIG_SYS_NS16550_CLK 48000000
23 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) 23 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
24 #define CONFIG_SYS_NS16550_SERIAL 24 #define CONFIG_SYS_NS16550_SERIAL
25 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 25 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
26 #endif 26 #endif
27 27
28 /* I2C Configuration */ 28 /* I2C Configuration */
29 #define CONFIG_CMD_EEPROM 29 #define CONFIG_CMD_EEPROM
30 #define CONFIG_ENV_EEPROM_IS_ON_I2C 30 #define CONFIG_ENV_EEPROM_IS_ON_I2C
31 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ 31 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
32 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 32 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
33 #define CONFIG_SYS_I2C_MULTI_EEPROMS 33 #define CONFIG_SYS_I2C_MULTI_EEPROMS
34 34
35 /* Power */ 35 /* Power */
36 #define CONFIG_POWER 36 #define CONFIG_POWER
37 #define CONFIG_POWER_I2C 37 #define CONFIG_POWER_I2C
38 #define CONFIG_POWER_TPS65218 38 #define CONFIG_POWER_TPS65218
39 #define CONFIG_POWER_TPS62362 39 #define CONFIG_POWER_TPS62362
40 40
41 /* SPL defines. */ 41 /* SPL defines. */
42 #define CONFIG_SPL_TEXT_BASE CONFIG_ISW_ENTRY_ADDR 42 #define CONFIG_SPL_TEXT_BASE CONFIG_ISW_ENTRY_ADDR
43 #define CONFIG_SPL_MAX_SIZE (NON_SECURE_SRAM_END - \ 43 #define CONFIG_SPL_MAX_SIZE (NON_SECURE_SRAM_END - \
44 CONFIG_PUB_ROM_DATA_SIZE - \ 44 CONFIG_PUB_ROM_DATA_SIZE - \
45 CONFIG_SPL_TEXT_BASE) 45 CONFIG_SPL_TEXT_BASE)
46 #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ 46 #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
47 (128 << 20)) 47 (128 << 20))
48 #define CONFIG_SPL_POWER_SUPPORT 48 #define CONFIG_SPL_POWER_SUPPORT
49 #define CONFIG_SPL_YMODEM_SUPPORT 49 #define CONFIG_SPL_YMODEM_SUPPORT
50 50
51 /* Enabling L2 Cache */ 51 /* Enabling L2 Cache */
52 #define CONFIG_SYS_L2_PL310 52 #define CONFIG_SYS_L2_PL310
53 #define CONFIG_SYS_PL310_BASE 0x48242000 53 #define CONFIG_SYS_PL310_BASE 0x48242000
54 #define CONFIG_SYS_CACHELINE_SIZE 32 54 #define CONFIG_SYS_CACHELINE_SIZE 32
55 55
56 /* 56 /*
57 * Since SPL did pll and ddr initialization for us, 57 * Since SPL did pll and ddr initialization for us,
58 * we don't need to do it twice. 58 * we don't need to do it twice.
59 */ 59 */
60 #if !defined(CONFIG_SPL_BUILD) /*&& !defined(CONFIG_QSPI_BOOT)*/ 60 #if !defined(CONFIG_SPL_BUILD) /*&& !defined(CONFIG_QSPI_BOOT)*/
61 #define CONFIG_SKIP_LOWLEVEL_INIT 61 #define CONFIG_SKIP_LOWLEVEL_INIT
62 #endif 62 #endif
63 63
64 #define CONFIG_HSMMC2_8BIT 64 #define CONFIG_HSMMC2_8BIT
65 65
66 /* 66 /*
67 * When building U-Boot such that there is no previous loader 67 * When building U-Boot such that there is no previous loader
68 * we need to call board_early_init_f. This is taken care of in 68 * we need to call board_early_init_f. This is taken care of in
69 * s_init when we have SPL used. 69 * s_init when we have SPL used.
70 */ 70 */
71 #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_SPL) 71 #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_SPL)
72 #define CONFIG_BOARD_EARLY_INIT_F 72 #define CONFIG_BOARD_EARLY_INIT_F
73 #endif 73 #endif
74 74
75 /* Now bring in the rest of the common code. */ 75 /* Now bring in the rest of the common code. */
76 #include <configs/embedian_armv7_smarct4x.h> 76 #include <configs/embedian_armv7_smarct4x.h>
77 77
78 /* Always 64 KiB env size */ 78 /* Always 64 KiB env size */
79 #define CONFIG_ENV_SIZE (64 << 10) 79 #define CONFIG_ENV_SIZE (64 << 10)
80 80
81 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 81 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
82 82
83 /* Clock Defines */ 83 /* Clock Defines */
84 #define V_OSCK 24000000 /* Clock output from T2 */ 84 #define V_OSCK 24000000 /* Clock output from T2 */
85 #define V_SCLK (V_OSCK) 85 #define V_SCLK (V_OSCK)
86 86
87 /* NS16550 Configuration */ 87 /* NS16550 Configuration */
88 #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ 88 #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
89 #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ 89 #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
90 #define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ 90 #define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
91 #define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ 91 #define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
92 #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ 92 #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
93 #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ 93 #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
94 #define CONFIG_BAUDRATE 115200 94 #define CONFIG_BAUDRATE 115200
95 95
96 #if !defined(CONFIG_ENV_IS_NOWHERE) 96 #if !defined(CONFIG_ENV_IS_NOWHERE)
97 #define CONFIG_ENV_IS_IN_FAT 97 #define CONFIG_ENV_IS_IN_FAT
98 #define FAT_ENV_INTERFACE "mmc" 98 #define FAT_ENV_INTERFACE "mmc"
99 #define FAT_ENV_DEVICE_AND_PART "0:1" 99 #define FAT_ENV_DEVICE_AND_PART "0:1"
100 #define FAT_ENV_FILE "uboot.env" 100 #define FAT_ENV_FILE "uboot.env"
101 #define CONFIG_FAT_WRITE 101 #define CONFIG_FAT_WRITE
102 #endif 102 #endif
103 103
104 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 104 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
105 105
106 /* SPL USB Support */ 106 /* SPL USB Support */
107 #ifdef CONFIG_SPL_USB_HOST_SUPPORT 107 #ifdef CONFIG_SPL_USB_HOST_SUPPORT
108 #define CONFIG_SPL_USB_SUPPORT 108 #define CONFIG_SPL_USB_SUPPORT
109 #endif 109 #endif
110 110
111 #if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD) 111 #if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
112 #define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 112 #define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
113 #define CONFIG_USB_HOST 113 #define CONFIG_USB_HOST
114 #define CONFIG_USB_XHCI 114 #define CONFIG_USB_XHCI
115 #define CONFIG_USB_XHCI_DWC3 115 #define CONFIG_USB_XHCI_DWC3
116 #define CONFIG_USB_XHCI_OMAP 116 #define CONFIG_USB_XHCI_OMAP
117 #define CONFIG_USB_STORAGE 117 #define CONFIG_USB_STORAGE
118 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 118 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
119 119
120 #define CONFIG_OMAP_USB_PHY 120 #define CONFIG_OMAP_USB_PHY
121 #define CONFIG_AM437X_USB2PHY2_HOST 121 #define CONFIG_AM437X_USB2PHY2_HOST
122 #endif 122 #endif
123 123
124 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USBETH_SUPPORT) 124 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USBETH_SUPPORT)
125 #undef CONFIG_USB_DWC3_PHY_OMAP 125 #undef CONFIG_USB_DWC3_PHY_OMAP
126 #undef CONFIG_USB_DWC3_OMAP 126 #undef CONFIG_USB_DWC3_OMAP
127 #undef CONFIG_USB_DWC3 127 #undef CONFIG_USB_DWC3
128 #undef CONFIG_USB_DWC3_GADGET 128 #undef CONFIG_USB_DWC3_GADGET
129 129
130 #undef CONFIG_USB_GADGET_DOWNLOAD 130 #undef CONFIG_USB_GADGET_DOWNLOAD
131 #undef CONFIG_USB_GADGET_VBUS_DRAW 131 #undef CONFIG_USB_GADGET_VBUS_DRAW
132 #undef CONFIG_G_DNL_MANUFACTURER 132 #undef CONFIG_G_DNL_MANUFACTURER
133 #undef CONFIG_G_DNL_VENDOR_NUM 133 #undef CONFIG_G_DNL_VENDOR_NUM
134 #undef CONFIG_G_DNL_PRODUCT_NUM 134 #undef CONFIG_G_DNL_PRODUCT_NUM
135 #undef CONFIG_USB_GADGET_DUALSPEED 135 #undef CONFIG_USB_GADGET_DUALSPEED
136 #endif 136 #endif
137 137
138 /* 138 /*
139 * Disable MMC DM for SPL build and can be re-enabled after adding 139 * Disable MMC DM for SPL build and can be re-enabled after adding
140 * DM support in SPL 140 * DM support in SPL
141 */ 141 */
142 #ifdef CONFIG_SPL_BUILD 142 #ifdef CONFIG_SPL_BUILD
143 #undef CONFIG_DM_MMC 143 #undef CONFIG_DM_MMC
144 #undef CONFIG_DM_SPI 144 #undef CONFIG_DM_SPI
145 #undef CONFIG_DM_SPI_FLASH 145 #undef CONFIG_DM_SPI_FLASH
146 #undef CONFIG_TIMER 146 #undef CONFIG_TIMER
147 #undef CONFIG_DM_NAND 147 #undef CONFIG_DM_NAND
148 #endif 148 #endif
149 149
150 #ifndef CONFIG_SPL_BUILD 150 #ifndef CONFIG_SPL_BUILD
151 /* USB Device Firmware Update support */ 151 /* USB Device Firmware Update support */
152 #define CONFIG_USB_FUNCTION_DFU 152 #define CONFIG_USB_FUNCTION_DFU
153 #define CONFIG_DFU_RAM 153 #define CONFIG_DFU_RAM
154 154
155 #define CONFIG_DFU_MMC 155 #define CONFIG_DFU_MMC
156 #define DFU_ALT_INFO_MMC \ 156 #define DFU_ALT_INFO_MMC \
157 "dfu_alt_info_mmc=" \ 157 "dfu_alt_info_mmc=" \
158 "boot part 0 1;" \ 158 "boot part 0 1;" \
159 "rootfs part 0 2;" \ 159 "rootfs part 0 2;" \
160 "MLO fat 0 1;" \ 160 "MLO fat 0 1;" \
161 "spl-os-args fat 0 1;" \ 161 "spl-os-args fat 0 1;" \
162 "spl-os-image fat 0 1;" \ 162 "spl-os-image fat 0 1;" \
163 "u-boot.img fat 0 1;" \ 163 "u-boot.img fat 0 1;" \
164 "uEnv.txt fat 0 1\0" 164 "uEnv.txt fat 0 1\0"
165 165
166 #define DFU_ALT_INFO_EMMC \ 166 #define DFU_ALT_INFO_EMMC \
167 "dfu_alt_info_emmc=" \ 167 "dfu_alt_info_emmc=" \
168 "MLO raw 0x100 0x100 mmcpart 0;" \ 168 "MLO raw 0x100 0x100 mmcpart 0;" \
169 "u-boot.img raw 0x300 0x1000 mmcpart 0\0" 169 "u-boot.img raw 0x300 0x1000 mmcpart 0\0"
170 170
171 #define CONFIG_DFU_RAM 171 #define CONFIG_DFU_RAM
172 #define DFU_ALT_INFO_RAM \ 172 #define DFU_ALT_INFO_RAM \
173 "dfu_alt_info_ram=" \ 173 "dfu_alt_info_ram=" \
174 "kernel ram 0x80200000 0x4000000;" \ 174 "kernel ram 0x80200000 0x4000000;" \
175 "fdt ram 0x80f80000 0x80000;" \ 175 "fdt ram 0x80f80000 0x80000;" \
176 "ramdisk ram 0x81000000 0x4000000\0" 176 "ramdisk ram 0x81000000 0x4000000\0"
177 177
178 #define DFUARGS \ 178 #define DFUARGS \
179 "dfu_bufsiz=0x10000\0" \ 179 "dfu_bufsiz=0x10000\0" \
180 DFU_ALT_INFO_MMC \ 180 DFU_ALT_INFO_MMC \
181 DFU_ALT_INFO_EMMC \ 181 DFU_ALT_INFO_EMMC \
182 DFU_ALT_INFO_RAM 182 DFU_ALT_INFO_RAM
183 #else 183 #else
184 #define DFUARGS 184 #define DFUARGS
185 #endif 185 #endif
186 186
187 /* 187 /*
188 * Default to using SPI for environment, etc. 188 * Default to using SPI for environment, etc.
189 * 0x000000 - 0x020000 : SPL (128KiB) 189 * 0x000000 - 0x020000 : SPL (128KiB)
190 * 0x020000 - 0x0A0000 : U-Boot (512KiB) 190 * 0x020000 - 0x0A0000 : U-Boot (512KiB)
191 * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB) 191 * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB)
192 * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB) 192 * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB)
193 * 0x0E0000 - 0x442000 : Linux Kernel 193 * 0x0E0000 - 0x442000 : Linux Kernel
194 * 0x442000 - 0x800000 : Userland 194 * 0x442000 - 0x800000 : Userland
195 */ 195 */
196 #if defined(CONFIG_SPI_BOOT) 196 #if defined(CONFIG_SPI_BOOT)
197 /* SPL related */ 197 /* SPL related */
198 #undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */ 198 #undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */
199 #define CONFIG_SPL_SPI_SUPPORT 199 #define CONFIG_SPL_SPI_SUPPORT
200 #define CONFIG_SPL_SPI_FLASH_SUPPORT 200 #define CONFIG_SPL_SPI_FLASH_SUPPORT
201 #define CONFIG_SPL_SPI_LOAD 201 #define CONFIG_SPL_SPI_LOAD
202 #define CONFIG_SPL_SPI_BUS 0 202 #define CONFIG_SPL_SPI_BUS 0
203 #define CONFIG_SPL_SPI_CS 0 203 #define CONFIG_SPL_SPI_CS 0
204 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 204 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
205 205
206 #undef CONFIG_SPL_OS_BOOT 206 #undef CONFIG_SPL_OS_BOOT
207 #undef CONFIG_ENV_IS_NOWHERE 207 #undef CONFIG_ENV_IS_NOWHERE
208 #define CONFIG_ENV_IS_IN_SPI_FLASH 208 #define CONFIG_ENV_IS_IN_SPI_FLASH
209 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 209 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
210 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 210 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
211 #define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ 211 #define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
212 #define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */ 212 #define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */
213 #define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */ 213 #define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */
214 #define MTDIDS_DEFAULT "nor0=m25p80-flash.0" 214 #define MTDIDS_DEFAULT "nor0=m25p80-flash.0"
215 #define MTDPARTS_DEFAULT "mtdparts=m25p80-flash.0:128k(SPL)," \ 215 #define MTDPARTS_DEFAULT "mtdparts=m25p80-flash.0:128k(SPL)," \
216 "512k(u-boot),128k(u-boot-env1)," \ 216 "512k(u-boot),128k(u-boot-env1)," \
217 "128k(u-boot-env2),3464k(kernel)," \ 217 "128k(u-boot-env2),3464k(kernel)," \
218 "-(rootfs)" 218 "-(rootfs)"
219 #endif 219 #endif
220 220
221 #if defined(CONFIG_EMMC_BOOT) 221 #if defined(CONFIG_EMMC_BOOT)
222 #undef CONFIG_SPL_OS_BOOT 222 #undef CONFIG_SPL_OS_BOOT
223 #undef CONFIG_ENV_IS_NOWHERE 223 #undef CONFIG_ENV_IS_NOWHERE
224 #define CONFIG_ENV_IS_IN_MMC 224 #define CONFIG_ENV_IS_IN_MMC
225 #define CONFIG_SPL_ENV_SUPPORT 225 #define CONFIG_SPL_ENV_SUPPORT
226 #define CONFIG_SYS_MMC_ENV_DEV 1 226 #define CONFIG_SYS_MMC_ENV_DEV 1
227 #define CONFIG_SYS_MMC_ENV_PART 2 227 #define CONFIG_SYS_MMC_ENV_PART 2
228
228 #define CONFIG_ENV_OFFSET 0x0 229 #define CONFIG_ENV_OFFSET 0x0
229 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 230 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
230 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 231 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
231 #endif 232 #endif
232 233
233 /* SPI */ 234 /* SPI */
234 /*#undef CONFIG_OMAP3_SPI*/ 235 /*#undef CONFIG_OMAP3_SPI*/
235 #define CONFIG_TI_SPI_MMAP 236 #define CONFIG_TI_SPI_MMAP
236 #define CONFIG_SF_DEFAULT_BUS 0 237 #define CONFIG_SF_DEFAULT_BUS 0
237 #define CONFIG_SF_DEFAULT_SPEED 24000000 238 #define CONFIG_SF_DEFAULT_SPEED 24000000
238 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 239 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
239 240
240 #define CONFIG_TI_EDMA3 241 #define CONFIG_TI_EDMA3
241 242
242 /* Enhance our eMMC support / experience. */ 243 /* Enhance our eMMC support / experience. */
243 #define CONFIG_CMD_GPT 244 #define CONFIG_CMD_GPT
244 #define CONFIG_EFI_PARTITION 245 #define CONFIG_EFI_PARTITION
245 246
246 #ifndef CONFIG_SPL_BUILD 247 #ifndef CONFIG_SPL_BUILD
247 #define CONFIG_EXTRA_ENV_SETTINGS \ 248 #define CONFIG_EXTRA_ENV_SETTINGS \
248 DEFAULT_LINUX_BOOT_ENV \ 249 DEFAULT_LINUX_BOOT_ENV \
249 DEFAULT_MMC_TI_ARGS \ 250 DEFAULT_MMC_TI_ARGS \
250 "boot_fdt=try\0" \ 251 "boot_fdt=try\0" \
251 "bootpart=0:1\0" \ 252 "bootpart=0:1\0" \
252 "bootdir=\0" \ 253 "bootdir=\0" \
253 "fdtdir=/dtbs\0" \ 254 "fdtdir=/dtbs\0" \
254 "bootfile=zImage\0" \ 255 "bootfile=zImage\0" \
255 "fdtfile=am437x-smarct437x.dtb\0" \ 256 "fdtfile=am437x-smarct437x.dtb\0" \
256 "console=ttyO0,115200n8\0" \ 257 "console=ttyO0,115200n8\0" \
257 "partitions=" \ 258 "partitions=" \
258 "uuid_disk=${uuid_gpt_disk};" \ 259 "uuid_disk=${uuid_gpt_disk};" \
259 "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ 260 "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
260 "optargs=\0" \ 261 "optargs=\0" \
261 "cmdline=\0" \ 262 "cmdline=\0" \
262 "mmcpart=1\0" \ 263 "mmcpart=1\0" \
263 "mmcroot=/dev/mmcblk0p2 ro\0" \ 264 "mmcroot=/dev/mmcblk0p2 ro\0" \
264 "usbroot=/dev/sda2 rw\0" \ 265 "usbroot=/dev/sda2 rw\0" \
265 "usbrootfstype=ext4 rootwait\0" \ 266 "usbrootfstype=ext4 rootwait\0" \
266 "usbdev=0\0" \ 267 "usbdev=0\0" \
267 "ramroot=/dev/ram0 rw\0" \ 268 "ramroot=/dev/ram0 rw\0" \
268 "ramrootfstype=ext2\0" \ 269 "ramrootfstype=ext2\0" \
269 "usbargs=setenv bootargs console=${console} " \ 270 "usbargs=setenv bootargs console=${console} " \
270 "${optargs} " \ 271 "${optargs} " \
271 "root=${usbroot} " \ 272 "root=${usbroot} " \
272 "rootfstype=${usbrootfstype}\0" \ 273 "rootfstype=${usbrootfstype}\0" \
273 "bootenv=uEnv.txt\0" \ 274 "bootenv=uEnv.txt\0" \
274 "script=boot.scr\0" \ 275 "script=boot.scr\0" \
275 "scriptfile=${script}\0" \ 276 "scriptfile=${script}\0" \
276 "loadbootscript=load mmc ${bootpart} ${loadaddr} ${scriptfile};\0" \ 277 "loadbootscript=load mmc ${bootpart} ${loadaddr} ${scriptfile};\0" \
277 "bootscript=echo Running bootscript from mmc${bootpart} ...; " \ 278 "bootscript=echo Running bootscript from mmc${bootpart} ...; " \
278 "source ${loadaddr}\0" \ 279 "source ${loadaddr}\0" \
279 "loadbootenv=load mmc ${bootpart} ${loadaddr} ${bootenv}\0" \ 280 "loadbootenv=load mmc ${bootpart} ${loadaddr} ${bootenv}\0" \
280 "loadusbbootenv=load usb ${bootpart} ${loadaddr} ${bootenv}\0" \ 281 "loadusbbootenv=load usb ${bootpart} ${loadaddr} ${bootenv}\0" \
281 "importbootenv=echo Importing environment from mmc ...; " \ 282 "importbootenv=echo Importing environment from mmc ...; " \
282 "env import -t -r $loadaddr $filesize\0" \ 283 "env import -t -r $loadaddr $filesize\0" \
283 "importusbbootenv=echo Importing environment from usb ...; " \ 284 "importusbbootenv=echo Importing environment from usb ...; " \
284 "env import -t -r $loadaddr $filesize\0" \ 285 "env import -t -r $loadaddr $filesize\0" \
285 "ramargs=setenv bootargs console=${console} " \ 286 "ramargs=setenv bootargs console=${console} " \
286 "${optargs} " \ 287 "${optargs} " \
287 "root=${ramroot} " \ 288 "root=${ramroot} " \
288 "rootfstype=${ramrootfstype}\0" \ 289 "rootfstype=${ramrootfstype}\0" \
289 "loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \ 290 "loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \
290 "loadimage=load ${devtype} ${mmcdev}:1 ${loadaddr} ${bootdir}/${bootfile}\0" \ 291 "loadimage=load ${devtype} ${mmcdev}:1 ${loadaddr} ${bootdir}/${bootfile}\0" \
291 "loadfdt=echo loading ${fdtdir}/${fdtfile} ...; load ${devtype} ${mmcdev}:1 ${fdtaddr} ${bootdir}/${fdtfile}\0" \ 292 "loadfdt=echo loading ${fdtdir}/${fdtfile} ...; load ${devtype} ${mmcdev}:1 ${fdtaddr} ${bootdir}/${fdtfile}\0" \
292 "mmcboot=mmc dev ${mmcdev}; " \ 293 "mmcboot=mmc dev ${mmcdev}; " \
293 "setenv devnum ${mmcdev}; " \ 294 "setenv devnum ${mmcdev}; " \
294 "setenv bootpart ${mmcdev}:1; "\ 295 "setenv bootpart ${mmcdev}:1; "\
295 "setenv devtype mmc; " \ 296 "setenv devtype mmc; " \
296 "if mmc rescan; then " \ 297 "if mmc rescan; then " \
297 "echo SD/MMC found on device ${devnum};" \ 298 "echo SD/MMC found on device ${devnum};" \
298 "if run loadbootenv; then " \ 299 "if run loadbootenv; then " \
299 "echo Loaded environment from ${bootenv};" \ 300 "echo Loaded environment from ${bootenv};" \
300 "run importbootenv;" \ 301 "run importbootenv;" \
301 "fi;" \ 302 "fi;" \
302 "if test -n $uenvcmd; then " \ 303 "if test -n $uenvcmd; then " \
303 "echo Running uenvcmd ...;" \ 304 "echo Running uenvcmd ...;" \
304 "run uenvcmd;" \ 305 "run uenvcmd;" \
305 "fi;" \ 306 "fi;" \
306 "if run loadimage; then " \ 307 "if run loadimage; then " \
307 "run loadfdt; " \ 308 "run loadfdt; " \
308 "echo Booting from mmc${mmcdev} ...; " \ 309 "echo Booting from mmc${mmcdev} ...; " \
309 "run args_mmc; " \ 310 "run args_mmc; " \
310 "bootz ${loadaddr} - ${fdtaddr}; " \ 311 "bootz ${loadaddr} - ${fdtaddr}; " \
311 "fi;" \ 312 "fi;" \
312 "fi;\0" \ 313 "fi;\0" \
313 "usbboot=" \ 314 "usbboot=" \
314 "setenv devnum ${usbdev}; " \ 315 "setenv devnum ${usbdev}; " \
315 "setenv devtype usb; " \ 316 "setenv devtype usb; " \
316 "usb start ${usbdev}; " \ 317 "usb start ${usbdev}; " \
317 "if usb dev ${usbdev}; then " \ 318 "if usb dev ${usbdev}; then " \
318 "if run loadusbbootenv; then " \ 319 "if run loadusbbootenv; then " \
319 "echo Loaded environment from ${bootenv};" \ 320 "echo Loaded environment from ${bootenv};" \
320 "run importusbbootenv;" \ 321 "run importusbbootenv;" \
321 "fi;" \ 322 "fi;" \
322 "if test -n $uenvcmd; then " \ 323 "if test -n $uenvcmd; then " \
323 "echo Running uenvcmd ...;" \ 324 "echo Running uenvcmd ...;" \
324 "run uenvcmd;" \ 325 "run uenvcmd;" \
325 "fi;" \ 326 "fi;" \
326 "if run loadimage; then " \ 327 "if run loadimage; then " \
327 "run loadfdt; " \ 328 "run loadfdt; " \
328 "echo Booting from usb ${usbdev}...; " \ 329 "echo Booting from usb ${usbdev}...; " \
329 "run usbargs;" \ 330 "run usbargs;" \
330 "bootz ${loadaddr} - ${fdtaddr}; " \ 331 "bootz ${loadaddr} - ${fdtaddr}; " \
331 "fi;" \ 332 "fi;" \
332 "fi\0" \ 333 "fi\0" \
333 "fi;" \ 334 "fi;" \
334 "usb stop ${usbdev};\0" \ 335 "usb stop ${usbdev};\0" \
335 "findfdt="\ 336 "findfdt="\
336 "if test $board_name = AM43EPOS; then " \ 337 "if test $board_name = AM43EPOS; then " \
337 "setenv fdtfile am43x-epos-evm.dtb; fi; " \ 338 "setenv fdtfile am43x-epos-evm.dtb; fi; " \
338 "if test $board_name = AM43__GP; then " \ 339 "if test $board_name = AM43__GP; then " \
339 "setenv fdtfile am437x-gp-evm.dtb; fi; " \ 340 "setenv fdtfile am437x-gp-evm.dtb; fi; " \
340 "if test $board_name = AM43XXHS; then " \ 341 "if test $board_name = AM43XXHS; then " \
341 "setenv fdtfile am437x-gp-evm.dtb; fi; " \ 342 "setenv fdtfile am437x-gp-evm.dtb; fi; " \
342 "if test $board_name = AM43__SK; then " \ 343 "if test $board_name = AM43__SK; then " \
343 "setenv fdtfile am437x-sk-evm.dtb; fi; " \ 344 "setenv fdtfile am437x-sk-evm.dtb; fi; " \
344 "if test $board_name = AM43_IDK; then " \ 345 "if test $board_name = AM43_IDK; then " \
345 "setenv fdtfile am437x-idk-evm.dtb; fi; " \ 346 "setenv fdtfile am437x-idk-evm.dtb; fi; " \
346 "if test $board_name = SMCT4X80; then " \ 347 "if test $board_name = SMCT4X80; then " \
347 "setenv fdtfile am437x-smarct437x.dtb; fi; " \ 348 "setenv fdtfile am437x-smarct437x.dtb; fi; " \
348 "if test $board_name = SMCT4X1G; then " \ 349 "if test $board_name = SMCT4X1G; then " \
349 "setenv fdtfile am437x-smarct437x.dtb; fi; " \ 350 "setenv fdtfile am437x-smarct437x.dtb; fi; " \
350 "if test $fdtfile = undefined; then " \ 351 "if test $fdtfile = undefined; then " \
351 "echo WARNING: Could not determine device tree; fi; \0" \ 352 "echo WARNING: Could not determine device tree; fi; \0" \
352 NANDARGS \ 353 NANDARGS \
353 NETARGS \ 354 NETARGS \
354 DFUARGS \ 355 DFUARGS \
355 356
356 #define CONFIG_BOOTCOMMAND \ 357 #define CONFIG_BOOTCOMMAND \
357 "run findfdt; " \ 358 "run findfdt; " \
358 "run envboot;" \ 359 "run envboot;" \
359 "run mmcboot;" \ 360 "run mmcboot;" \
360 "run usbboot;" 361 "run usbboot;"
361 362
362 #endif 363 #endif
363 364
364 #ifndef CONFIG_SPL_BUILD 365 #ifndef CONFIG_SPL_BUILD
365 /* CPSW Ethernet */ 366 /* CPSW Ethernet */
366 #define CONFIG_MII 367 #define CONFIG_MII
367 #define CONFIG_BOOTP_DEFAULT 368 #define CONFIG_BOOTP_DEFAULT
368 #define CONFIG_BOOTP_DNS 369 #define CONFIG_BOOTP_DNS
369 #define CONFIG_BOOTP_DNS2 370 #define CONFIG_BOOTP_DNS2
370 #define CONFIG_BOOTP_SEND_HOSTNAME 371 #define CONFIG_BOOTP_SEND_HOSTNAME
371 #define CONFIG_BOOTP_GATEWAY 372 #define CONFIG_BOOTP_GATEWAY
372 #define CONFIG_BOOTP_SUBNETMASK 373 #define CONFIG_BOOTP_SUBNETMASK
373 #define CONFIG_NET_RETRY_COUNT 10 374 #define CONFIG_NET_RETRY_COUNT 10
374 #define CONFIG_PHY_GIGE 375 #define CONFIG_PHY_GIGE
375 #endif 376 #endif
376 377
377 #define CONFIG_DRIVER_TI_CPSW 378 #define CONFIG_DRIVER_TI_CPSW
378 #define CONFIG_PHYLIB 379 #define CONFIG_PHYLIB
379 #define CONFIG_PHY_ATHEROS 380 #define CONFIG_PHY_ATHEROS
380 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ 381 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
381 382
382 #define CONFIG_SPL_ENV_SUPPORT 383 #define CONFIG_SPL_ENV_SUPPORT
383 #define CONFIG_SPL_NET_VCI_STRING "AM43xx U-Boot SPL" 384 #define CONFIG_SPL_NET_VCI_STRING "AM43xx U-Boot SPL"
384 385
385 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ETH_SUPPORT) 386 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ETH_SUPPORT)
386 #undef CONFIG_ENV_IS_IN_FAT 387 #undef CONFIG_ENV_IS_IN_FAT
387 #define CONFIG_ENV_IS_NOWHERE 388 #define CONFIG_ENV_IS_NOWHERE
388 #define CONFIG_SPL_NET_SUPPORT 389 #define CONFIG_SPL_NET_SUPPORT
389 #endif 390 #endif
390 391
391 #define CONFIG_SYS_RX_ETH_BUFFER 64 392 #define CONFIG_SYS_RX_ETH_BUFFER 64
392 393
393 /* NAND support */ 394 /* NAND support */
394 #ifdef CONFIG_NAND 395 #ifdef CONFIG_NAND
395 /* NAND: device related configs */ 396 /* NAND: device related configs */
396 #define CONFIG_SYS_NAND_PAGE_SIZE 4096 397 #define CONFIG_SYS_NAND_PAGE_SIZE 4096
397 #define CONFIG_SYS_NAND_OOBSIZE 224 398 #define CONFIG_SYS_NAND_OOBSIZE 224
398 #define CONFIG_SYS_NAND_BLOCK_SIZE (256*1024) 399 #define CONFIG_SYS_NAND_BLOCK_SIZE (256*1024)
399 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 400 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
400 CONFIG_SYS_NAND_PAGE_SIZE) 401 CONFIG_SYS_NAND_PAGE_SIZE)
401 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 402 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
402 /* NAND: driver related configs */ 403 /* NAND: driver related configs */
403 #define CONFIG_NAND_OMAP_GPMC 404 #define CONFIG_NAND_OMAP_GPMC
404 #define CONFIG_NAND_OMAP_ELM 405 #define CONFIG_NAND_OMAP_ELM
405 #define CONFIG_SYS_NAND_ONFI_DETECTION 406 #define CONFIG_SYS_NAND_ONFI_DETECTION
406 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW 407 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
407 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 408 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
408 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 409 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
409 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ 410 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
410 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ 411 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
411 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \ 412 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
412 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \ 413 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \
413 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ 414 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
414 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \ 415 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \
415 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ 416 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
416 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \ 417 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \
417 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \ 418 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \
418 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \ 419 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \
419 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \ 420 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \
420 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \ 421 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \
421 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \ 422 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \
422 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \ 423 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \
423 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \ 424 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \
424 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \ 425 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \
425 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \ 426 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \
426 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \ 427 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \
427 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \ 428 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
428 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \ 429 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
429 } 430 }
430 #define CONFIG_SYS_NAND_ECCSIZE 512 431 #define CONFIG_SYS_NAND_ECCSIZE 512
431 #define CONFIG_SYS_NAND_ECCBYTES 26 432 #define CONFIG_SYS_NAND_ECCBYTES 26
432 #define MTDIDS_DEFAULT "nand0=nand.0" 433 #define MTDIDS_DEFAULT "nand0=nand.0"
433 #define MTDPARTS_DEFAULT "mtdparts=nand.0:" \ 434 #define MTDPARTS_DEFAULT "mtdparts=nand.0:" \
434 "256k(NAND.SPL)," \ 435 "256k(NAND.SPL)," \
435 "256k(NAND.SPL.backup1)," \ 436 "256k(NAND.SPL.backup1)," \
436 "256k(NAND.SPL.backup2)," \ 437 "256k(NAND.SPL.backup2)," \
437 "256k(NAND.SPL.backup3)," \ 438 "256k(NAND.SPL.backup3)," \
438 "512k(NAND.u-boot-spl-os)," \ 439 "512k(NAND.u-boot-spl-os)," \
439 "1m(NAND.u-boot)," \ 440 "1m(NAND.u-boot)," \
440 "256k(NAND.u-boot-env)," \ 441 "256k(NAND.u-boot-env)," \
441 "256k(NAND.u-boot-env.backup1)," \ 442 "256k(NAND.u-boot-env.backup1)," \
442 "7m(NAND.kernel)," \ 443 "7m(NAND.kernel)," \
443 "-(NAND.file-system)" 444 "-(NAND.file-system)"
444 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00180000 445 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00180000
445 /* NAND: SPL related configs */ 446 /* NAND: SPL related configs */
446 #ifdef CONFIG_SPL_NAND_SUPPORT 447 #ifdef CONFIG_SPL_NAND_SUPPORT
447 #define CONFIG_SPL_NAND_AM33XX_BCH 448 #define CONFIG_SPL_NAND_AM33XX_BCH
448 #endif 449 #endif
449 /* NAND: SPL falcon mode configs */ 450 /* NAND: SPL falcon mode configs */
450 #ifdef CONFIG_SPL_OS_BOOT 451 #ifdef CONFIG_SPL_OS_BOOT
451 #define CONFIG_CMD_SPL_NAND_OFS 0x00100000 /* os parameters */ 452 #define CONFIG_CMD_SPL_NAND_OFS 0x00100000 /* os parameters */
452 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00300000 /* kernel offset */ 453 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00300000 /* kernel offset */
453 #define CONFIG_CMD_SPL_WRITE_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 454 #define CONFIG_CMD_SPL_WRITE_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
454 #endif 455 #endif
455 #define NANDARGS \ 456 #define NANDARGS \
456 "mtdids=" MTDIDS_DEFAULT "\0" \ 457 "mtdids=" MTDIDS_DEFAULT "\0" \
457 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 458 "mtdparts=" MTDPARTS_DEFAULT "\0" \
458 "nandargs=setenv bootargs console=${console} " \ 459 "nandargs=setenv bootargs console=${console} " \
459 "${optargs} " \ 460 "${optargs} " \
460 "root=${nandroot} " \ 461 "root=${nandroot} " \
461 "rootfstype=${nandrootfstype}\0" \ 462 "rootfstype=${nandrootfstype}\0" \
462 "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,4096\0" \ 463 "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,4096\0" \
463 "nandrootfstype=ubifs rootwait=1\0" \ 464 "nandrootfstype=ubifs rootwait=1\0" \
464 "nandboot=echo Booting from nand ...; " \ 465 "nandboot=echo Booting from nand ...; " \
465 "run nandargs; " \ 466 "run nandargs; " \
466 "nand read ${fdtaddr} NAND.u-boot-spl-os; " \ 467 "nand read ${fdtaddr} NAND.u-boot-spl-os; " \
467 "nand read ${loadaddr} NAND.kernel; " \ 468 "nand read ${loadaddr} NAND.kernel; " \
468 "bootz ${loadaddr} - ${fdtaddr}\0" 469 "bootz ${loadaddr} - ${fdtaddr}\0"
469 #define NANDBOOT "run nandboot; " 470 #define NANDBOOT "run nandboot; "
470 #else /* !CONFIG_NAND */ 471 #else /* !CONFIG_NAND */
471 #define NANDARGS 472 #define NANDARGS
472 #define NANDBOOT 473 #define NANDBOOT
473 #endif /* CONFIG_NAND */ 474 #endif /* CONFIG_NAND */
474 475
475 #endif /* __CONFIG_SMARCT437X_EVM_H */ 476 #endif /* __CONFIG_SMARCT437X_EVM_H */
476 477