Commit e1e332c8f2e5cac70566998a0ba0ccfdea437f10
1 parent
a452002259
Exists in
v2017.01-smarct4x
and in
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dm: spi: Correct status register access width
The status register on ICH9 is a single byte, so use byte access when writing to it, to avoid updating the control register also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Showing 1 changed file with 5 additions and 1 deletions Side-by-side Diff
drivers/spi/ich.c
| ... | ... | @@ -411,6 +411,7 @@ |
| 411 | 411 | const void *dout, void *din, unsigned long flags) |
| 412 | 412 | { |
| 413 | 413 | struct udevice *bus = dev_get_parent(dev); |
| 414 | + struct ich_spi_platdata *plat = dev_get_platdata(bus); | |
| 414 | 415 | struct ich_spi_priv *ctlr = dev_get_priv(bus); |
| 415 | 416 | uint16_t control; |
| 416 | 417 | int16_t opcode_index; |
| ... | ... | @@ -477,7 +478,10 @@ |
| 477 | 478 | if (ret < 0) |
| 478 | 479 | return ret; |
| 479 | 480 | |
| 480 | - ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); | |
| 481 | + if (plat->ich_version == 7) | |
| 482 | + ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); | |
| 483 | + else | |
| 484 | + ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); | |
| 481 | 485 | |
| 482 | 486 | spi_setup_type(trans, using_cmd ? bytes : 0); |
| 483 | 487 | opcode_index = spi_setup_opcode(ctlr, trans); |