Merge branch 'master' of git://git.denx.de/u-boot-mmc

Tom Rini
2 parents 76a8265b4f adebb98ba1
Showing 7 changed files Side-by-side Diff
drivers/mmc/Makefile
drivers/mmc/dw_mmc.c
drivers/mmc/exynos_dw_mmc.c
drivers/mmc/fsl_esdhc_spl.c
drivers/mmc/ftsdc021_sdhci.c
include/dwmmc.h
include/faraday/ftsdc021.h
@@ -9,6 +9,7 @@
 obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
 obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
 obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
+obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o
 obj-$(CONFIG_GENERIC_MMC) += mmc.o
 obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
 obj-$(CONFIG_MMC_SPI) += mmc_spi.o
@@ -11,7 +11,6 @@
 #include <mmc.h>
 #include <dwmmc.h>
 #include <asm-generic/errno.h>
-#include <asm/arch/dwmmc.h>
  
 #define PAGE_SIZE 4096
  
  
@@ -300,17 +299,9 @@
 static int dwmci_init(struct mmc *mmc)
 {
 	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
-	u32 fifo_size;
  
-	if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
-		dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
-		dwmci_writel(host, EMMCP_SEND0, 0);
-		dwmci_writel(host, EMMCP_CTRL0,
-			     MPSCTRL_SECURE_READ_BIT |
-			     MPSCTRL_SECURE_WRITE_BIT |
-			     MPSCTRL_NON_SECURE_READ_BIT |
-			     MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
-	}
+	if (host->board_init)
+		host->board_init(host);
  
 	dwmci_writel(host, DWMCI_PWREN, 1);
  
  
@@ -330,13 +321,9 @@
 	dwmci_writel(host, DWMCI_IDINTEN, 0);
 	dwmci_writel(host, DWMCI_BMOD, 1);
  
-	if (!host->fifoth_val) {
-		fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
-		fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
-		host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
-			TX_WMARK(fifo_size / 2);
+	if (host->fifoth_val) {
+		dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
 	}
-	dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
  
 	dwmci_writel(host, DWMCI_CLKENA, 0);
 	dwmci_writel(host, DWMCI_CLKSRC, 0);
@@ -34,6 +34,19 @@
 	return get_mmc_clk(dev_index);
 }
  
+static void exynos_dwmci_board_init(struct dwmci_host *host)
+{
+	if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
+		dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
+		dwmci_writel(host, EMMCP_SEND0, 0);
+		dwmci_writel(host, EMMCP_CTRL0,
+			     MPSCTRL_SECURE_READ_BIT |
+			     MPSCTRL_SECURE_WRITE_BIT |
+			     MPSCTRL_NON_SECURE_READ_BIT |
+			     MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
+	}
+}
+
 /*
  * This function adds the mmc channel to be registered with mmc core.
  * index -	mmc channel number.
@@ -65,6 +78,7 @@
 #ifdef CONFIG_EXYNOS5420
 	host->quirks = DWMCI_QUIRK_DISABLE_SMU;
 #endif
+	host->board_init = exynos_dwmci_board_init;
  
 	if (clksel) {
 		host->clksel_val = clksel;
@@ -42,6 +42,10 @@
 		hang();
 	}
  
+#ifdef CONFIG_FSL_CORENET
+	offset = CONFIG_SYS_MMC_U_BOOT_OFFS;
+	code_len = CONFIG_SYS_MMC_U_BOOT_SIZE;
+#else
 	blklen = mmc->read_bl_len;
 	tmp_buf = malloc(blklen);
 	if (!tmp_buf) {
@@ -91,6 +95,7 @@
 	/*
 	* Load U-Boot image from mmc into RAM
 	*/
+#endif
 	blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
 	blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len;
 	err = mmc->block_dev.block_read(0, blk_start, blk_cnt,
+/*
+ * (C) Copyright 2013 Faraday Technology
+ * Kuo-Jung Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <sdhci.h>
+
+#ifndef CONFIG_FTSDC021_CLOCK
+#define CONFIG_FTSDC021_CLOCK   clk_get_rate("MMC")
+#endif
+
+int ftsdc021_sdhci_init(u32 regbase)
+{
+	struct sdhci_host *host = NULL;
+	uint32_t freq = CONFIG_FTSDC021_CLOCK;
+
+	host = calloc(1, sizeof(struct sdhci_host));
+	if (!host) {
+		puts("sdh_host malloc fail!\n");
+		return 1;
+	}
+
+	host->name = "FTSDC021";
+	host->ioaddr = (void __iomem *)regbase;
+	host->quirks = 0;
+	add_sdhci(host, freq, 0);
+
+	return 0;
+}
@@ -141,6 +141,7 @@
 	struct mmc *mmc;
  
 	void (*clksel)(struct dwmci_host *host);
+	void (*board_init)(struct dwmci_host *host);
 	unsigned int (*get_mmc_clk)(int dev_index);
 };
  
+/*
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __FTSDC021_H
+#define __FTSDC021_H
+
+int ftsdc021_sdhci_init(u32 regbase);
+
+#endif /* __FTSDC021_H */
...	...	@@ -9,6 +9,7 @@
9	9	obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
10	10	obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
11	11	obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
	12	+obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o
12	13	obj-$(CONFIG_GENERIC_MMC) += mmc.o
13	14	obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
14	15	obj-$(CONFIG_MMC_SPI) += mmc_spi.o
...	...	@@ -11,7 +11,6 @@
11	11	#include <mmc.h>
12	12	#include <dwmmc.h>
13	13	#include <asm-generic/errno.h>
14		-#include <asm/arch/dwmmc.h>
15	14
16	15	#define PAGE_SIZE 4096
17	16
18	17
...	...	@@ -300,17 +299,9 @@
300	299	static int dwmci_init(struct mmc *mmc)
301	300	{
302	301	struct dwmci_host host = (struct dwmci_host )mmc->priv;
303		- u32 fifo_size;
304	302
305		- if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
306		- dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
307		- dwmci_writel(host, EMMCP_SEND0, 0);
308		- dwmci_writel(host, EMMCP_CTRL0,
309		- MPSCTRL_SECURE_READ_BIT \|
310		- MPSCTRL_SECURE_WRITE_BIT \|
311		- MPSCTRL_NON_SECURE_READ_BIT \|
312		- MPSCTRL_NON_SECURE_WRITE_BIT \| MPSCTRL_VALID);
313		- }
	303	+ if (host->board_init)
	304	+ host->board_init(host);
314	305
315	306	dwmci_writel(host, DWMCI_PWREN, 1);
316	307
317	308
...	...	@@ -330,13 +321,9 @@
330	321	dwmci_writel(host, DWMCI_IDINTEN, 0);
331	322	dwmci_writel(host, DWMCI_BMOD, 1);
332	323
333		- if (!host->fifoth_val) {
334		- fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
335		- fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
336		- host->fifoth_val = MSIZE(0x2) \| RX_WMARK(fifo_size / 2 - 1) \|
337		- TX_WMARK(fifo_size / 2);
	324	+ if (host->fifoth_val) {
	325	+ dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
338	326	}
339		- dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
340	327
341	328	dwmci_writel(host, DWMCI_CLKENA, 0);
342	329	dwmci_writel(host, DWMCI_CLKSRC, 0);
...	...	@@ -34,6 +34,19 @@
34	34	return get_mmc_clk(dev_index);
35	35	}
36	36
	37	+static void exynos_dwmci_board_init(struct dwmci_host *host)
	38	+{
	39	+ if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
	40	+ dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
	41	+ dwmci_writel(host, EMMCP_SEND0, 0);
	42	+ dwmci_writel(host, EMMCP_CTRL0,
	43	+ MPSCTRL_SECURE_READ_BIT \|
	44	+ MPSCTRL_SECURE_WRITE_BIT \|
	45	+ MPSCTRL_NON_SECURE_READ_BIT \|
	46	+ MPSCTRL_NON_SECURE_WRITE_BIT \| MPSCTRL_VALID);
	47	+ }
	48	+}
	49	+
37	50	/*
38	51	* This function adds the mmc channel to be registered with mmc core.
39	52	* index - mmc channel number.
...	...	@@ -65,6 +78,7 @@
65	78	#ifdef CONFIG_EXYNOS5420
66	79	host->quirks = DWMCI_QUIRK_DISABLE_SMU;
67	80	#endif
	81	+ host->board_init = exynos_dwmci_board_init;
68	82
69	83	if (clksel) {
70	84	host->clksel_val = clksel;
...	...	@@ -42,6 +42,10 @@
42	42	hang();
43	43	}
44	44
	45	+#ifdef CONFIG_FSL_CORENET
	46	+ offset = CONFIG_SYS_MMC_U_BOOT_OFFS;
	47	+ code_len = CONFIG_SYS_MMC_U_BOOT_SIZE;
	48	+#else
45	49	blklen = mmc->read_bl_len;
46	50	tmp_buf = malloc(blklen);
47	51	if (!tmp_buf) {
...	...	@@ -91,6 +95,7 @@
91	95	/*
92	96	* Load U-Boot image from mmc into RAM
93	97	*/
	98	+#endif
94	99	blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
95	100	blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len;
96	101	err = mmc->block_dev.block_read(0, blk_start, blk_cnt,
	1	+/*
	2	+ * (C) Copyright 2013 Faraday Technology
	3	+ * Kuo-Jung Su <dantesu@faraday-tech.com>
	4	+ *
	5	+ * SPDX-License-Identifier: GPL-2.0+
	6	+ */
	7	+
	8	+#include <common.h>
	9	+#include <malloc.h>
	10	+#include <sdhci.h>
	11	+
	12	+#ifndef CONFIG_FTSDC021_CLOCK
	13	+#define CONFIG_FTSDC021_CLOCK clk_get_rate("MMC")
	14	+#endif
	15	+
	16	+int ftsdc021_sdhci_init(u32 regbase)
	17	+{
	18	+ struct sdhci_host *host = NULL;
	19	+ uint32_t freq = CONFIG_FTSDC021_CLOCK;
	20	+
	21	+ host = calloc(1, sizeof(struct sdhci_host));
	22	+ if (!host) {
	23	+ puts("sdh_host malloc fail!\n");
	24	+ return 1;
	25	+ }
	26	+
	27	+ host->name = "FTSDC021";
	28	+ host->ioaddr = (void __iomem *)regbase;
	29	+ host->quirks = 0;
	30	+ add_sdhci(host, freq, 0);
	31	+
	32	+ return 0;
	33	+}
...	...	@@ -141,6 +141,7 @@
141	141	struct mmc *mmc;
142	142
143	143	void (clksel)(struct dwmci_host host);
	144	+ void (board_init)(struct dwmci_host host);
144	145	unsigned int (*get_mmc_clk)(int dev_index);
145	146	};
146	147
	1	+/*
	2	+ * (C) Copyright 2013 Faraday Technology
	3	+ * Dante Su <dantesu@faraday-tech.com>
	4	+ *
	5	+ * SPDX-License-Identifier: GPL-2.0+
	6	+ */
	7	+
	8	+#ifndef __FTSDC021_H
	9	+#define __FTSDC021_H
	10	+
	11	+int ftsdc021_sdhci_init(u32 regbase);
	12	+
	13	+#endif /* __FTSDC021_H */