Eric Lee / smarc-uboot

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Commit e2a48d1ebf95df7fd9a8c16366bd5453fbd8bb99

Authored by Peng Fan
1 parent 7dc4e15242
Exists in smarc-m6.0.1_2.1.0-ga and in 2 other branches imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga

MLK-11238 imx: mx7d fix usdhc pad settings 

To CD/VSELECT/RST, should use same pad settings with USDHC_PAD_CTRL,
because default NO_PAD_CTRL's settings is 100K Pull-Down. But, we need
pull-up for CD/VSELECT/RST.

Also some board provides external pull-down/up, we'd better use internal
pull-up for these pad settings.

To mx7d_12x12_lpddr3_arm2:
If no card plugged in, "mmc dev 1" will show "Card did not respond to
voltage select". After apply this patch, it will show "MMC: no card present".

To mx7dsabresd:
Alougth without this patch, if no card plugged in sd1, still correct msg
"MMC: no card present", anyway we'd better use pull-up.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>

Showing 5 changed files with 24 additions and 35 deletions Side-by-side Diff

board/freescale/mx7d_12x12_ddr3_arm2/mx7d_12x12_ddr3_arm2.c
Diff comments   View file @ e2a48d1
... ... @@ -33,8 +33,6 @@
33 33 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
34 34 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
35 35 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
36   -#define USDHC_PAD_VSELECT (PAD_CTL_DSE_3P3V_32OHM | \
37   - PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
38 36 #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
39 37 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
40 38 #define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
... ... @@ -94,7 +92,7 @@
94 92 MX7D_PAD_ECSPI1_MISO__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 93 MX7D_PAD_ECSPI1_SS0__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 94  
97   - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  95 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
98 96 };
99 97  
100 98 static iomux_v3_cfg_t const usdhc3_pads[] = {
... ... @@ -105,8 +103,8 @@
105 103 MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 104 MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 105  
108   - MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
109   - MX7D_PAD_GPIO1_IO15__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  106 + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  107 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
110 108 };
111 109  
112 110 static iomux_v3_cfg_t const wdog_pads[] = {
board/freescale/mx7d_12x12_lpddr3_arm2/mx7d_12x12_lpddr3_arm2.c
Diff comments   View file @ e2a48d1
... ... @@ -44,9 +44,6 @@
44 44 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
45 45 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
46 46  
47   -#define USDHC_PAD_VSELECT (PAD_CTL_DSE_3P3V_32OHM | \
48   - PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
49   -
50 47 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
51 48 #define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
52 49  
53 50  
... ... @@ -115,10 +112,10 @@
115 112 MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116 113 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117 114 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118   - MX7D_PAD_GPIO1_IO08__SD1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_VSELECT),
  115 + MX7D_PAD_GPIO1_IO08__SD1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 116  
120   - MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
121   - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(NO_PAD_CTRL),
  117 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  118 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 119 };
123 120  
124 121 static iomux_v3_cfg_t const usdhc2_pads[] = {
125 122  
... ... @@ -129,10 +126,10 @@
129 126 MX7D_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130 127 MX7D_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131 128  
132   - MX7D_PAD_GPIO1_IO12__SD2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_VSELECT),
  129 + MX7D_PAD_GPIO1_IO12__SD2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 130  
134   - MX7D_PAD_SD2_CD_B__GPIO5_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
135   - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  131 + MX7D_PAD_SD2_CD_B__GPIO5_IO9 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  132 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 133 };
137 134  
138 135 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
... ... @@ -147,7 +144,7 @@
147 144 MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
148 145 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
149 146  
150   - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  147 + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
151 148 };
152 149  
153 150  
board/freescale/mx7d_19x19_ddr3_arm2/mx7d_19x19_ddr3_arm2.c
Diff comments   View file @ e2a48d1
... ... @@ -40,9 +40,6 @@
40 40 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
41 41 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
42 42  
43   -#define USDHC_PAD_VSELECT (PAD_CTL_DSE_3P3V_32OHM | \
44   - PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
45   -
46 43 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
47 44 #define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
48 45  
... ... @@ -114,8 +111,8 @@
114 111 MX7D_PAD_ECSPI2_MISO__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
115 112 MX7D_PAD_ECSPI2_SS0__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116 113  
117   - MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
118   - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(NO_PAD_CTRL),
  114 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  115 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 116 };
120 117  
121 118 static iomux_v3_cfg_t const usdhc2_pads[] = {
122 119  
... ... @@ -126,10 +123,10 @@
126 123 MX7D_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
127 124 MX7D_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
128 125  
129   - MX7D_PAD_GPIO1_IO12__SD2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_VSELECT),
  126 + MX7D_PAD_GPIO1_IO12__SD2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130 127  
131   - MX7D_PAD_SD2_CD_B__GPIO5_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
132   - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  128 + MX7D_PAD_SD2_CD_B__GPIO5_IO9 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  129 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 130 };
134 131  
135 132 static iomux_v3_cfg_t const usdhc3_pads[] = {
136 133  
... ... @@ -144,10 +141,10 @@
144 141 MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 142 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 143  
147   - MX7D_PAD_GPIO1_IO13__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_VSELECT),
  144 + MX7D_PAD_GPIO1_IO13__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
148 145  
149   - MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
150   - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  146 + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  147 + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
151 148 };
152 149  
153 150  
board/freescale/mx7d_19x19_lpddr3_arm2/mx7d_19x19_lpddr3_arm2.c
Diff comments   View file @ e2a48d1
... ... @@ -37,9 +37,6 @@
37 37 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
38 38 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
39 39  
40   -#define USDHC_PAD_VSELECT (PAD_CTL_DSE_3P3V_32OHM | \
41   - PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
42   -
43 40 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
44 41 #define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
45 42  
46 43  
... ... @@ -115,10 +112,10 @@
115 112 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116 113 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117 114  
118   - MX7D_PAD_GPIO1_IO08__SD1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_VSELECT),
  115 + MX7D_PAD_GPIO1_IO08__SD1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 116  
120   - MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
121   - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(NO_PAD_CTRL),
  117 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  118 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 119 };
123 120  
124 121 #ifdef CONFIG_SYS_USE_EIMNOR
board/freescale/mx7dsabresd/mx7dsabresd.c
Diff comments   View file @ e2a48d1
... ... @@ -131,8 +131,8 @@
131 131 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 132 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 133  
134   - MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
135   - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(NO_PAD_CTRL),
  134 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  135 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 136 };
137 137  
138 138 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
... ... @@ -148,7 +148,7 @@
148 148 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
149 149 MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
150 150  
151   - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  151 + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
152 152 };
153 153  
154 154 #define IOX_SDI IMX_GPIO_NR(1, 9)