Eric Lee / smarc-uboot

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Commit e2e947ff6ba676e5ba84639fe6f2766aa683e181

Authored by Simon Glass
1 parent 17aa548ced
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

rockchip: Add basic support for jerry 

This builds and displays an SPL message, but does not function beyond that.

Signed-off-by: Simon Glass <sjg@chromium.org>

Showing 13 changed files with 1370 additions and 2 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ e2e947f
... ... @@ -16,7 +16,8 @@
16 16 exynos5800-peach-pi.dtb \
17 17 exynos5422-odroidxu3.dtb
18 18 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
19   - rk3288-firefly.dtb
  19 + rk3288-firefly.dtb \
  20 + rk3288-jerry.dtb
20 21 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
21 22 tegra20-medcom-wide.dtb \
22 23 tegra20-paz00.dtb \
arch/arm/dts/cros-ec-sbs.dtsi
Diff comments   View file @ e2e947f
  1 +/*
  2 + * Smart battery dts fragment for devices that use cros-ec-sbs
  3 + *
  4 + * Copyright (c) 2015 Google, Inc
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0
  7 +*/
  8 +
  9 +&i2c_tunnel {
  10 + battery: sbs-battery@b {
  11 + compatible = "sbs,sbs-battery";
  12 + reg = <0xb>;
  13 + sbs,i2c-retry-count = <2>;
  14 + sbs,poll-retry-count = <1>;
  15 + };
  16 +};
arch/arm/dts/rk3288-jerry.dts
Diff comments   View file @ e2e947f
  1 +/*
  2 + * Google Veyron Jerry Rev 3+ board device tree source
  3 + *
  4 + * Copyright 2014 Google, Inc
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0
  7 + */
  8 +
  9 +/dts-v1/;
  10 +#include "rk3288-veyron-chromebook.dtsi"
  11 +#include "cros-ec-sbs.dtsi"
  12 +
  13 +/ {
  14 + model = "Google Jerry";
  15 + compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
  16 + "google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
  17 + "google,veyron-jerry-rev3", "google,veyron-jerry",
  18 + "google,veyron", "rockchip,rk3288";
  19 +
  20 + chosen {
  21 + stdout-path = &uart2;
  22 + };
  23 +
  24 + panel_regulator: panel-regualtor {
  25 + compatible = "regulator-fixed";
  26 + enable-active-high;
  27 + gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
  28 + pinctrl-names = "default";
  29 + pinctrl-0 = <&lcd_enable_h>;
  30 + regulator-name = "panel_regulator";
  31 + vin-supply = <&vcc33_sys>;
  32 + };
  33 +
  34 + vcc18_lcd: vcc18-lcd {
  35 + compatible = "regulator-fixed";
  36 + enable-active-high;
  37 + gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
  38 + pinctrl-names = "default";
  39 + pinctrl-0 = <&avdd_1v8_disp_en>;
  40 + regulator-name = "vcc18_lcd";
  41 + regulator-always-on;
  42 + regulator-boot-on;
  43 + vin-supply = <&vcc18_wl>;
  44 + };
  45 +
  46 + backlight_regulator: backlight-regulator {
  47 + compatible = "regulator-fixed";
  48 + enable-active-high;
  49 + gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
  50 + pinctrl-names = "default";
  51 + pinctrl-0 = <&bl_pwr_en>;
  52 + regulator-name = "backlight_regulator";
  53 + vin-supply = <&vcc33_sys>;
  54 + startup-delay-us = <15000>;
  55 + };
  56 +};
  57 +
  58 +&gpio_keys {
  59 + power {
  60 + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
  61 + };
  62 +};
  63 +
  64 +&backlight {
  65 + power-supply = <&backlight_regulator>;
  66 +};
  67 +
  68 +&panel {
  69 + power-supply= <&panel_regulator>;
  70 +};
  71 +
  72 +&rk808 {
  73 + pinctrl-names = "default";
  74 + pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
  75 + dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
  76 + <&gpio7 15 GPIO_ACTIVE_HIGH>;
  77 +
  78 + regulators {
  79 + mic_vcc: LDO_REG2 {
  80 + regulator-always-on;
  81 + regulator-boot-on;
  82 + regulator-min-microvolt = <1800000>;
  83 + regulator-max-microvolt = <1800000>;
  84 + regulator-name = "mic_vcc";
  85 + regulator-suspend-mem-disabled;
  86 + };
  87 + };
  88 +};
  89 +
  90 +&sdmmc {
  91 + pinctrl-names = "default";
  92 + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
  93 + &sdmmc_bus4>;
  94 + disable-wp;
  95 +};
  96 +
  97 +&vcc_5v {
  98 + enable-active-high;
  99 + gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
  100 + pinctrl-names = "default";
  101 + pinctrl-0 = <&drv_5v>;
  102 +};
  103 +
  104 +&vcc50_hdmi {
  105 + enable-active-high;
  106 + gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
  107 + pinctrl-names = "default";
  108 + pinctrl-0 = <&vcc50_hdmi_en>;
  109 +};
  110 +
  111 +&edp {
  112 + pinctrl-names = "default";
  113 + pinctrl-0 = <&edp_hpd>;
  114 +};
  115 +
  116 +&pinctrl {
  117 + backlight {
  118 + bl_pwr_en: bl_pwr_en {
  119 + rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
  120 + };
  121 + };
  122 +
  123 + buck-5v {
  124 + drv_5v: drv-5v {
  125 + rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
  126 + };
  127 + };
  128 +
  129 + edp {
  130 + edp_hpd: edp_hpd {
  131 + rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
  132 + };
  133 + };
  134 +
  135 + emmc {
  136 + /* Make sure eMMC is not in reset */
  137 + emmc_deassert_reset: emmc-deassert-reset {
  138 + rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
  139 + };
  140 + };
  141 +
  142 + hdmi {
  143 + vcc50_hdmi_en: vcc50-hdmi-en {
  144 + rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
  145 + };
  146 + };
  147 +
  148 + lcd {
  149 + lcd_enable_h: lcd-en {
  150 + rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
  151 + };
  152 +
  153 + avdd_1v8_disp_en: avdd-1v8-disp-en {
  154 + rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
  155 + };
  156 + };
  157 +
  158 + pmic {
  159 + dvs_1: dvs-1 {
  160 + rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
  161 + };
  162 +
  163 + dvs_2: dvs-2 {
  164 + rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
  165 + };
  166 + };
  167 +};
  168 +
  169 +&i2c4 {
  170 + status = "okay";
  171 +
  172 + /*
  173 + * Trackpad pin control is shared between Elan and Synaptics devices
  174 + * so we have to pull it up to the bus level.
  175 + */
  176 + pinctrl-names = "default";
  177 + pinctrl-0 = <&i2c4_xfer &trackpad_int>;
  178 +
  179 + trackpad@15 {
  180 + compatible = "elan,i2c_touchpad";
  181 + interrupt-parent = <&gpio7>;
  182 + interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
  183 + /*
  184 + * Remove the inherited pinctrl settings to avoid clashing
  185 + * with bus-wide ones.
  186 + */
  187 + /delete-property/pinctrl-names;
  188 + /delete-property/pinctrl-0;
  189 + reg = <0x15>;
  190 + vcc-supply = <&vcc33_io>;
  191 + wakeup-source;
  192 + };
  193 +
  194 + trackpad@2c {
  195 + compatible = "hid-over-i2c";
  196 + interrupt-parent = <&gpio7>;
  197 + interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
  198 + reg = <0x2c>;
  199 + hid-descr-addr = <0x0020>;
  200 + vcc-supply = <&vcc33_io>;
  201 + wakeup-source;
  202 + };
  203 +};
arch/arm/dts/rk3288-veyron-chromebook.dtsi
Diff comments   View file @ e2e947f
  1 +/*
  2 + * Google Veyron (and derivatives) board device tree source
  3 + *
  4 + * Copyright 2014 Google, Inc
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0
  7 + */
  8 +
  9 +#include <dt-bindings/clock/rockchip,rk808.h>
  10 +#include <dt-bindings/input/input.h>
  11 +#include "rk3288-veyron.dtsi"
  12 +
  13 +/ {
  14 + aliases {
  15 + i2c20 = &i2c_tunnel;
  16 + };
  17 +
  18 + gpio_keys: gpio-keys {
  19 + pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;
  20 + lid {
  21 + label = "Lid";
  22 + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
  23 + linux,code = <0>; /* SW_LID */
  24 + linux,input-type = <5>; /* EV_SW */
  25 + debounce-interval = <1>;
  26 + gpio-key,wakeup;
  27 + };
  28 + };
  29 +
  30 + gpio-charger {
  31 + compatible = "gpio-charger";
  32 + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
  33 + pinctrl-names = "default";
  34 + pinctrl-0 = <&ac_present_ap>;
  35 + charger-type = "mains";
  36 + };
  37 +
  38 + /* A non-regulated voltage from power supply or battery */
  39 + vccsys: vccsys {
  40 + compatible = "regulator-fixed";
  41 + regulator-name = "vccsys";
  42 + regulator-boot-on;
  43 + regulator-always-on;
  44 + };
  45 +
  46 + vcc33_sys: vcc33-sys {
  47 + vin-supply = <&vccsys>;
  48 + };
  49 +
  50 + vcc_5v: vcc-5v {
  51 + vin-supply = <&vccsys>;
  52 + };
  53 +
  54 + /* This turns on vbus for host1 (dwc2) */
  55 + vcc5_host1: vcc5-host1-regulator {
  56 + compatible = "regulator-fixed";
  57 + enable-active-high;
  58 + gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
  59 + pinctrl-names = "default";
  60 + pinctrl-0 = <&host1_pwr_en>;
  61 + regulator-name = "vcc5_host1";
  62 + regulator-always-on;
  63 + regulator-boot-on;
  64 + };
  65 +
  66 + /* This turns on vbus for otg for host mode (dwc2) */
  67 + vcc5v_otg: vcc5v-otg-regulator {
  68 + compatible = "regulator-fixed";
  69 + enable-active-high;
  70 + gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
  71 + pinctrl-names = "default";
  72 + pinctrl-0 = <&usbotg_pwren_h>;
  73 + regulator-name = "vcc5_host2";
  74 + regulator-always-on;
  75 + regulator-boot-on;
  76 + };
  77 +};
  78 +
  79 +&rk808 {
  80 + regulators {
  81 + vcc33_ccd: LDO_REG8 {
  82 + regulator-always-on;
  83 + regulator-boot-on;
  84 + regulator-min-microvolt = <3300000>;
  85 + regulator-max-microvolt = <3300000>;
  86 + regulator-name = "vcc33_ccd";
  87 + regulator-suspend-mem-disabled;
  88 + };
  89 + };
  90 +};
  91 +
  92 +&spi0 {
  93 + status = "okay";
  94 +
  95 + cros_ec: ec@0 {
  96 + compatible = "google,cros-ec-spi";
  97 + spi-max-frequency = <3000000>;
  98 + interrupt-parent = <&gpio7>;
  99 + interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
  100 + pinctrl-names = "default";
  101 + pinctrl-0 = <&ec_int>;
  102 + reg = <0>;
  103 + google,cros-ec-spi-pre-delay = <30>;
  104 +
  105 + i2c_tunnel: i2c-tunnel {
  106 + compatible = "google,cros-ec-i2c-tunnel";
  107 + google,remote-bus = <0>;
  108 + #address-cells = <1>;
  109 + #size-cells = <0>;
  110 + };
  111 + };
  112 +};
  113 +
  114 +&i2c4 {
  115 + trackpad@15 {
  116 + compatible = "elan,i2c_touchpad";
  117 + interrupt-parent = <&gpio7>;
  118 + interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
  119 + pinctrl-names = "default";
  120 + pinctrl-0 = <&trackpad_int>;
  121 + reg = <0x15>;
  122 + vcc-supply = <&vcc33_io>;
  123 + wakeup-source;
  124 + };
  125 +};
  126 +
  127 +&pinctrl {
  128 + pinctrl-0 = <
  129 + /* Common for sleep and wake, but no owners */
  130 + &ddr0_retention
  131 + &ddrio_pwroff
  132 + &global_pwroff
  133 +
  134 + /* Wake only */
  135 + &suspend_l_wake
  136 + &bt_dev_wake_awake
  137 + >;
  138 + pinctrl-1 = <
  139 + /* Common for sleep and wake, but no owners */
  140 + &ddr0_retention
  141 + &ddrio_pwroff
  142 + &global_pwroff
  143 +
  144 + /* Sleep only */
  145 + &suspend_l_sleep
  146 + &bt_dev_wake_sleep
  147 + >;
  148 +
  149 + buttons {
  150 + ap_lid_int_l: ap-lid-int-l {
  151 + rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>;
  152 + };
  153 + };
  154 +
  155 + charger {
  156 + ac_present_ap: ac-present-ap {
  157 + rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
  158 + };
  159 + };
  160 +
  161 + cros-ec {
  162 + ec_int: ec-int {
  163 + rockchip,pins = <7 7 RK_FUNC_GPIO &pcfg_pull_none>;
  164 + };
  165 + };
  166 +
  167 + sdmmc {
  168 + sdmmc_wp_gpio: sdmmc-wp-gpio {
  169 + rockchip,pins = <7 10 RK_FUNC_GPIO &pcfg_pull_up>;
  170 + };
  171 + };
  172 +
  173 + suspend {
  174 + suspend_l_wake: suspend-l-wake {
  175 + rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_low>;
  176 + };
  177 +
  178 + suspend_l_sleep: suspend-l-sleep {
  179 + rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_high>;
  180 + };
  181 + };
  182 +
  183 + trackpad {
  184 + trackpad_int: trackpad-int {
  185 + rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_up>;
  186 + };
  187 + };
  188 +
  189 + usb-host {
  190 + host1_pwr_en: host1-pwr-en {
  191 + rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>;
  192 + };
  193 +
  194 + usbotg_pwren_h: usbotg-pwren-h {
  195 + rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
  196 + };
  197 + };
  198 +};
  199 +
  200 +#include "cros-ec-keyboard.dtsi"
arch/arm/dts/rk3288-veyron.dtsi
Diff comments   View file @ e2e947f
  1 +/*
  2 + * Google Veyron (and derivatives) board device tree source
  3 + *
  4 + * Copyright 2014 Google, Inc
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0
  7 + */
  8 +
  9 +#include <dt-bindings/clock/rockchip,rk808.h>
  10 +#include <dt-bindings/input/input.h>
  11 +#include "rk3288.dtsi"
  12 +
  13 +/ {
  14 + memory {
  15 + reg = <0x0 0x80000000>;
  16 + };
  17 +
  18 + chosen {
  19 + stdout-path = &uart2;
  20 + };
  21 +
  22 + config {
  23 + u-boot,dm-pre-reloc;
  24 + u-boot,boot0 = &spi_flash;
  25 + };
  26 +
  27 + firmware {
  28 + chromeos {
  29 + pinctrl-names = "default";
  30 + pinctrl-0 = <&fw_wp_ap>;
  31 + write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>;
  32 + };
  33 + };
  34 +
  35 + backlight: backlight {
  36 + compatible = "pwm-backlight";
  37 + brightness-levels = <
  38 + 0 1 2 3 4 5 6 7
  39 + 8 9 10 11 12 13 14 15
  40 + 16 17 18 19 20 21 22 23
  41 + 24 25 26 27 28 29 30 31
  42 + 32 33 34 35 36 37 38 39
  43 + 40 41 42 43 44 45 46 47
  44 + 48 49 50 51 52 53 54 55
  45 + 56 57 58 59 60 61 62 63
  46 + 64 65 66 67 68 69 70 71
  47 + 72 73 74 75 76 77 78 79
  48 + 80 81 82 83 84 85 86 87
  49 + 88 89 90 91 92 93 94 95
  50 + 96 97 98 99 100 101 102 103
  51 + 104 105 106 107 108 109 110 111
  52 + 112 113 114 115 116 117 118 119
  53 + 120 121 122 123 124 125 126 127
  54 + 128 129 130 131 132 133 134 135
  55 + 136 137 138 139 140 141 142 143
  56 + 144 145 146 147 148 149 150 151
  57 + 152 153 154 155 156 157 158 159
  58 + 160 161 162 163 164 165 166 167
  59 + 168 169 170 171 172 173 174 175
  60 + 176 177 178 179 180 181 182 183
  61 + 184 185 186 187 188 189 190 191
  62 + 192 193 194 195 196 197 198 199
  63 + 200 201 202 203 204 205 206 207
  64 + 208 209 210 211 212 213 214 215
  65 + 216 217 218 219 220 221 222 223
  66 + 224 225 226 227 228 229 230 231
  67 + 232 233 234 235 236 237 238 239
  68 + 240 241 242 243 244 245 246 247
  69 + 248 249 250 251 252 253 254 255>;
  70 + default-brightness-level = <128>;
  71 + enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
  72 + backlight-boot-off;
  73 + pinctrl-names = "default";
  74 + pinctrl-0 = <&bl_en>;
  75 + pwms = <&pwm0 0 1000000 0>;
  76 + };
  77 +
  78 + panel: panel {
  79 + compatible ="cnm,n116bgeea2","simple-panel";
  80 + status = "okay";
  81 + power-supply = <&vcc33_lcd>;
  82 + backlight = <&backlight>;
  83 + };
  84 +
  85 + gpio_keys: gpio-keys {
  86 + compatible = "gpio-keys";
  87 + #address-cells = <1>;
  88 + #size-cells = <0>;
  89 +
  90 + pinctrl-names = "default";
  91 + pinctrl-0 = <&pwr_key_h>;
  92 + power {
  93 + label = "Power";
  94 + gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
  95 + linux,code = <KEY_POWER>;
  96 + debounce-interval = <100>;
  97 + gpio-key,wakeup;
  98 + };
  99 + };
  100 +
  101 + gpio-restart {
  102 + compatible = "gpio-restart";
  103 + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
  104 + pinctrl-names = "default";
  105 + pinctrl-0 = <&ap_warm_reset_h>;
  106 + priority = /bits/ 8 <200>;
  107 + };
  108 +
  109 + sound {
  110 + compatible = "rockchip,rockchip-audio-max98090";
  111 + rockchip,model = "ROCKCHIP-I2S";
  112 + rockchip,i2s-controller = <&i2s>;
  113 + rockchip,audio-codec = <&max98090>;
  114 + rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
  115 + rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
  116 + rockchip,headset-codec = <&headsetcodec>;
  117 + pinctrl-names = "default";
  118 + pinctrl-0 = <&mic_det>, <&hp_det>;
  119 + };
  120 +
  121 + vdd_logic: pwm-regulator {
  122 + compatible = "pwm-regulator";
  123 + pwms = <&pwm1 0 2000 0>;
  124 +
  125 + voltage-table = <1350000 0>,
  126 + <1300000 10>,
  127 + <1250000 20>,
  128 + <1200000 31>,
  129 + <1150000 41>,
  130 + <1100000 52>,
  131 + <1050000 62>,
  132 + <1000000 72>,
  133 + < 950000 83>;
  134 +
  135 + regulator-min-microvolt = <950000>;
  136 + regulator-max-microvolt = <1350000>;
  137 + regulator-name = "vdd_logic";
  138 + regulator-ramp-delay = <4000>;
  139 + };
  140 +
  141 + vcc33_sys: vcc33-sys {
  142 + compatible = "regulator-fixed";
  143 + regulator-name = "vcc33_sys";
  144 + regulator-always-on;
  145 + regulator-boot-on;
  146 + regulator-min-microvolt = <3300000>;
  147 + regulator-max-microvolt = <3300000>;
  148 + vin-supply = <&vccsys>;
  149 + };
  150 +
  151 + vcc_5v: vcc-5v {
  152 + compatible = "regulator-fixed";
  153 + regulator-name = "vcc_5v";
  154 + regulator-always-on;
  155 + regulator-boot-on;
  156 + regulator-min-microvolt = <5000000>;
  157 + regulator-max-microvolt = <5000000>;
  158 + };
  159 +
  160 + vcc50_hdmi: vcc50-hdmi {
  161 + compatible = "regulator-fixed";
  162 + regulator-name = "vcc50_hdmi";
  163 + regulator-always-on;
  164 + regulator-boot-on;
  165 + vin-supply = <&vcc_5v>;
  166 + };
  167 +
  168 + bt_regulator: bt-regulator {
  169 + /*
  170 + * On the module itself this is one of these (depending
  171 + * on the actual card pouplated):
  172 + * - BT_I2S_WS_BT_RFDISABLE_L
  173 + * - No connect
  174 + */
  175 +
  176 + compatible = "regulator-fixed";
  177 + enable-active-high;
  178 + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
  179 + pinctrl-names = "default";
  180 + pinctrl-0 = <&bt_enable_l>;
  181 + regulator-name = "bt_regulator";
  182 + };
  183 +
  184 + wifi_regulator: wifi-regulator {
  185 + /*
  186 + * On the module itself this is one of these (depending
  187 + * on the actual card populated):
  188 + * - SDIO_RESET_L_WL_REG_ON
  189 + * - PDN (power down when low)
  190 + */
  191 +
  192 + compatible = "regulator-fixed";
  193 + enable-active-high;
  194 + gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
  195 + pinctrl-names = "default";
  196 + pinctrl-0 = <&wifi_enable_h>;
  197 + regulator-name = "wifi_regulator";
  198 +
  199 + /* Faux input supply. See bt_regulator description. */
  200 + vin-supply = <&bt_regulator>;
  201 + };
  202 +
  203 + io-domains {
  204 + compatible = "rockchip,rk3288-io-voltage-domain";
  205 + rockchip,grf = <&grf>;
  206 +
  207 + audio-supply = <&vcc18_codec>;
  208 + bb-supply = <&vcc33_io>;
  209 + dvp-supply = <&vcc_18>;
  210 + flash0-supply = <&vcc18_flashio>;
  211 + gpio1830-supply = <&vcc33_io>;
  212 + gpio30-supply = <&vcc33_io>;
  213 + lcdc-supply = <&vcc33_lcd>;
  214 + sdcard-supply = <&vccio_sd>;
  215 + wifi-supply = <&vcc18_wl>;
  216 + };
  217 +};
  218 +
  219 +&cpu0 {
  220 + cpu0-supply = <&vdd_cpu>;
  221 +};
  222 +
  223 +&dmc {
  224 + logic-supply = <&vdd_logic>;
  225 + rockchip,odt-disable-freq = <333000000>;
  226 + rockchip,dll-disable-freq = <333000000>;
  227 + rockchip,sr-enable-freq = <333000000>;
  228 + rockchip,pd-enable-freq = <666000000>;
  229 + rockchip,auto-self-refresh-cnt = <0>;
  230 + rockchip,auto-power-down-cnt = <64>;
  231 + rockchip,ddr-speed-bin = <21>;
  232 + rockchip,trcd = <10>;
  233 + rockchip,trp = <10>;
  234 + operating-points = <
  235 + /* KHz uV */
  236 + 200000 1050000
  237 + 333000 1100000
  238 + 533000 1150000
  239 + 666000 1200000
  240 + >;
  241 + rockchip,num-channels = <2>;
  242 + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
  243 + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
  244 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
  245 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
  246 + 0x5 0x0>;
  247 + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
  248 + 0xa60 0x40 0x10 0x0>;
  249 + rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>;
  250 + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
  251 +};
  252 +
  253 +&efuse {
  254 + status = "okay";
  255 +};
  256 +
  257 +&emmc {
  258 + broken-cd;
  259 + bus-width = <8>;
  260 + cap-mmc-highspeed;
  261 + mmc-hs200-1_8v;
  262 + disable-wp;
  263 + non-removable;
  264 + num-slots = <1>;
  265 + pinctrl-names = "default";
  266 + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_deassert_reset>;
  267 + status = "okay";
  268 +};
  269 +
  270 +&sdio0 {
  271 + broken-cd;
  272 + bus-width = <4>;
  273 + cap-sd-highspeed;
  274 + sd-uhs-sdr12;
  275 + sd-uhs-sdr25;
  276 + sd-uhs-sdr50;
  277 + sd-uhs-sdr104;
  278 + cap-sdio-irq;
  279 + card-external-vcc-supply = <&wifi_regulator>;
  280 + clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>,
  281 + <&cru SCLK_SDIO0_SAMPLE>, <&rk808 RK808_CLKOUT1>;
  282 + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample", "card_ext_clock";
  283 + keep-power-in-suspend;
  284 + non-removable;
  285 + num-slots = <1>;
  286 + pinctrl-names = "default";
  287 + pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
  288 + status = "okay";
  289 + vmmc-supply = <&vcc33_sys>;
  290 + vqmmc-supply = <&vcc18_wl>;
  291 +};
  292 +
  293 +&sdmmc {
  294 + bus-width = <4>;
  295 + cap-mmc-highspeed;
  296 + cap-sd-highspeed;
  297 + sd-uhs-sdr12;
  298 + sd-uhs-sdr25;
  299 + sd-uhs-sdr50;
  300 + sd-uhs-sdr104;
  301 + card-detect-delay = <200>;
  302 + cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
  303 + num-slots = <1>;
  304 + status = "okay";
  305 + vmmc-supply = <&vcc33_sd>;
  306 + vqmmc-supply = <&vccio_sd>;
  307 +};
  308 +
  309 +&spi2 {
  310 + status = "okay";
  311 + u-boot,dm-pre-reloc;
  312 +
  313 + spi_flash: spiflash@0 {
  314 + u-boot,dm-pre-reloc;
  315 + compatible = "spidev", "spi-flash";
  316 + spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */
  317 + reg = <0>;
  318 + };
  319 +};
  320 +
  321 +&i2c0 {
  322 + status = "okay";
  323 +
  324 + clock-frequency = <400000>;
  325 + i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
  326 + i2c-scl-rising-time-ns = <100>; /* 45ns measured */
  327 +
  328 + rk808: pmic@1b {
  329 + compatible = "rockchip,rk808";
  330 + clock-output-names = "xin32k", "wifibt_32kin";
  331 + interrupt-parent = <&gpio0>;
  332 + interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  333 + pinctrl-names = "default";
  334 + pinctrl-0 = <&pmic_int_l>;
  335 + reg = <0x1b>;
  336 + rockchip,system-power-controller;
  337 + wakeup-source;
  338 + #clock-cells = <1>;
  339 +
  340 + vcc1-supply = <&vcc33_sys>;
  341 + vcc2-supply = <&vcc33_sys>;
  342 + vcc3-supply = <&vcc33_sys>;
  343 + vcc4-supply = <&vcc33_sys>;
  344 + vcc6-supply = <&vcc_5v>;
  345 + vcc7-supply = <&vcc33_sys>;
  346 + vcc8-supply = <&vcc33_sys>;
  347 + vcc9-supply = <&vcc_5v>;
  348 + vcc10-supply = <&vcc33_sys>;
  349 + vcc11-supply = <&vcc_5v>;
  350 + vcc12-supply = <&vcc_18>;
  351 +
  352 + vddio-supply = <&vcc33_io>;
  353 +
  354 + regulators {
  355 + vdd_cpu: DCDC_REG1 {
  356 + regulator-always-on;
  357 + regulator-boot-on;
  358 + regulator-min-microvolt = <750000>;
  359 + regulator-max-microvolt = <1450000>;
  360 + regulator-name = "vdd_arm";
  361 + regulator-ramp-delay = <6001>;
  362 + regulator-suspend-mem-disabled;
  363 + };
  364 +
  365 + vdd_gpu: DCDC_REG2 {
  366 + regulator-always-on;
  367 + regulator-boot-on;
  368 + regulator-min-microvolt = <800000>;
  369 + regulator-max-microvolt = <1250000>;
  370 + regulator-name = "vdd_gpu";
  371 + regulator-ramp-delay = <6001>;
  372 + regulator-suspend-mem-disabled;
  373 + };
  374 +
  375 + vcc135_ddr: DCDC_REG3 {
  376 + regulator-always-on;
  377 + regulator-boot-on;
  378 + regulator-name = "vcc135_ddr";
  379 + regulator-suspend-mem-enabled;
  380 + };
  381 +
  382 + /*
  383 + * vcc_18 has several aliases. (vcc18_flashio and
  384 + * vcc18_wl). We'll add those aliases here just to
  385 + * make it easier to follow the schematic. The signals
  386 + * are actually hooked together and only separated for
  387 + * power measurement purposes).
  388 + */
  389 + vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
  390 + regulator-always-on;
  391 + regulator-boot-on;
  392 + regulator-min-microvolt = <1800000>;
  393 + regulator-max-microvolt = <1800000>;
  394 + regulator-name = "vcc_18";
  395 + regulator-suspend-mem-microvolt = <1800000>;
  396 + };
  397 +
  398 + /*
  399 + * Note that both vcc33_io and vcc33_pmuio are always
  400 + * powered together. To simplify the logic in the dts
  401 + * we just refer to vcc33_io every time something is
  402 + * powered from vcc33_pmuio. In fact, on later boards
  403 + * (such as danger) they're the same net.
  404 + */
  405 + vcc33_io: LDO_REG1 {
  406 + regulator-always-on;
  407 + regulator-boot-on;
  408 + regulator-min-microvolt = <3300000>;
  409 + regulator-max-microvolt = <3300000>;
  410 + regulator-name = "vcc33_io";
  411 + regulator-suspend-mem-microvolt = <3300000>;
  412 + };
  413 +
  414 + vdd_10: LDO_REG3 {
  415 + regulator-always-on;
  416 + regulator-boot-on;
  417 + regulator-min-microvolt = <1000000>;
  418 + regulator-max-microvolt = <1000000>;
  419 + regulator-name = "vdd_10";
  420 + regulator-suspend-mem-microvolt = <1000000>;
  421 + };
  422 +
  423 + vccio_sd: LDO_REG4 {
  424 + regulator-min-microvolt = <1800000>;
  425 + regulator-max-microvolt = <3300000>;
  426 + regulator-name = "vccio_sd";
  427 + regulator-suspend-mem-disabled;
  428 + };
  429 +
  430 + vcc33_sd: LDO_REG5 {
  431 + regulator-min-microvolt = <3300000>;
  432 + regulator-max-microvolt = <3300000>;
  433 + regulator-name = "vcc33_sd";
  434 + regulator-suspend-mem-disabled;
  435 + };
  436 +
  437 + vcc18_codec: LDO_REG6 {
  438 + regulator-always-on;
  439 + regulator-boot-on;
  440 + regulator-min-microvolt = <1800000>;
  441 + regulator-max-microvolt = <1800000>;
  442 + regulator-name = "vcc18_codec";
  443 + regulator-suspend-mem-disabled;
  444 + };
  445 +
  446 + vdd10_lcd_pwren_h: LDO_REG7 {
  447 + regulator-always-on;
  448 + regulator-boot-on;
  449 + regulator-min-microvolt = <2500000>;
  450 + regulator-max-microvolt = <2500000>;
  451 + regulator-name = "vdd10_lcd_pwren_h";
  452 + regulator-suspend-mem-disabled;
  453 + };
  454 +
  455 + vcc33_lcd: SWITCH_REG1 {
  456 + regulator-always-on;
  457 + regulator-boot-on;
  458 + regulator-name = "vcc33_lcd";
  459 + regulator-suspend-mem-disabled;
  460 + };
  461 + };
  462 + };
  463 +};
  464 +
  465 +&i2c1 {
  466 + status = "okay";
  467 +
  468 + clock-frequency = <400000>;
  469 + i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
  470 + i2c-scl-rising-time-ns = <100>; /* 40ns measured */
  471 +
  472 + tpm: tpm@20 {
  473 + compatible = "infineon,slb9645tt";
  474 + reg = <0x20>;
  475 + powered-while-suspended;
  476 + };
  477 +};
  478 +
  479 +&i2c2 {
  480 + status = "okay";
  481 +
  482 + /* 100kHz since 4.7k resistors don't rise fast enough */
  483 + clock-frequency = <100000>;
  484 + i2c-scl-falling-time-ns = <50>; /* 10ns measured */
  485 + i2c-scl-rising-time-ns = <800>; /* 600ns measured */
  486 +
  487 + max98090: max98090@10 {
  488 + compatible = "maxim,max98090";
  489 + reg = <0x10>;
  490 + interrupt-parent = <&gpio6>;
  491 + interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
  492 + pinctrl-names = "default";
  493 + pinctrl-0 = <&int_codec>;
  494 + };
  495 +};
  496 +
  497 +&i2c3 {
  498 + status = "okay";
  499 +
  500 + clock-frequency = <400000>;
  501 + i2c-scl-falling-time-ns = <50>;
  502 + i2c-scl-rising-time-ns = <300>;
  503 +};
  504 +
  505 +&i2c4 {
  506 + status = "okay";
  507 +
  508 + clock-frequency = <400000>;
  509 + i2c-scl-falling-time-ns = <50>; /* 11ns measured */
  510 + i2c-scl-rising-time-ns = <300>; /* 225ns measured */
  511 +
  512 + headsetcodec: ts3a227e@3b {
  513 + compatible = "ti,ts3a227e";
  514 + reg = <0x3b>;
  515 + interrupt-parent = <&gpio0>;
  516 + interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
  517 + pinctrl-names = "default";
  518 + pinctrl-0 = <&ts3a227e_int_l>;
  519 + ti,micbias = <7>; /* MICBIAS = 2.8V */
  520 + };
  521 +};
  522 +
  523 +&i2c5 {
  524 + status = "okay";
  525 +
  526 + clock-frequency = <100000>;
  527 + i2c-scl-falling-time-ns = <300>;
  528 + i2c-scl-rising-time-ns = <1000>;
  529 +};
  530 +
  531 +&i2s {
  532 + status = "okay";
  533 + clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
  534 + clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
  535 +};
  536 +
  537 +&wdt {
  538 + status = "okay";
  539 +};
  540 +
  541 +&pwm0 {
  542 + status = "okay";
  543 +};
  544 +
  545 +&pwm1 {
  546 + status = "okay";
  547 +};
  548 +
  549 +&uart0 {
  550 + status = "okay";
  551 +
  552 + /* Pins don't include flow control by default; add that in */
  553 + pinctrl-names = "default";
  554 + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
  555 + /* We need to go faster than 24MHz, so adjust clock parents / rates */
  556 + assigned-clocks = <&cru SCLK_UART0>;
  557 + assigned-clock-rates = <48000000>;
  558 +};
  559 +
  560 +&uart1 {
  561 + status = "okay";
  562 +};
  563 +
  564 +&uart2 {
  565 + status = "okay";
  566 + u-boot,dm-pre-reloc;
  567 + reg-shift = <2>;
  568 +};
  569 +
  570 +&vopb {
  571 + status = "okay";
  572 +};
  573 +
  574 +&vopb_mmu {
  575 + status = "okay";
  576 +};
  577 +
  578 +&vopl {
  579 + status = "okay";
  580 +};
  581 +
  582 +&vopl_mmu {
  583 + status = "okay";
  584 +};
  585 +
  586 +&edp {
  587 + status = "okay";
  588 + rockchip,panel = <&panel>;
  589 +};
  590 +
  591 +&hdmi {
  592 + status = "okay";
  593 +};
  594 +
  595 +&hdmi_audio {
  596 + status = "okay";
  597 +};
  598 +
  599 +&gpu {
  600 + status = "okay";
  601 +};
  602 +
  603 +&tsadc {
  604 + tsadc-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
  605 + tsadc-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
  606 + status = "okay";
  607 +};
  608 +
  609 +&pinctrl {
  610 + u-boot,dm-pre-reloc;
  611 + pinctrl-names = "default", "sleep";
  612 + pinctrl-0 = <
  613 + /* Common for sleep and wake, but no owners */
  614 + &ddr0_retention
  615 + &ddrio_pwroff
  616 + &global_pwroff
  617 +
  618 + /* Wake only */
  619 + &bt_dev_wake_awake
  620 + >;
  621 + pinctrl-1 = <
  622 + /* Common for sleep and wake, but no owners */
  623 + &ddr0_retention
  624 + &ddrio_pwroff
  625 + &global_pwroff
  626 +
  627 + /* Sleep only */
  628 + &bt_dev_wake_sleep
  629 + >;
  630 +
  631 + /* Add this for sdmmc pins to SD card */
  632 + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
  633 + drive-strength = <8>;
  634 + };
  635 +
  636 + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
  637 + bias-pull-up;
  638 + drive-strength = <8>;
  639 + };
  640 +
  641 + pcfg_output_high: pcfg-output-high {
  642 + output-high;
  643 + };
  644 +
  645 + pcfg_output_low: pcfg-output-low {
  646 + output-low;
  647 + };
  648 +
  649 + backlight {
  650 + bl_en: bl-en {
  651 + rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
  652 + };
  653 + };
  654 +
  655 + buttons {
  656 + pwr_key_h: pwr-key-h {
  657 + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>;
  658 + };
  659 + };
  660 +
  661 + codec {
  662 + hp_det: hp-det {
  663 + rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>;
  664 + };
  665 + int_codec: int-codec {
  666 + rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_up>;
  667 + };
  668 + mic_det: mic-det {
  669 + rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>;
  670 + };
  671 + };
  672 +
  673 + emmc {
  674 + /* Make sure eMMC is not in reset */
  675 + emmc_deassert_reset: emmc-deassert-reset {
  676 + rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_up>;
  677 + };
  678 +
  679 + /*
  680 + * We run eMMC at max speed; bump up drive strength.
  681 + * We also have external pulls, so disable the internal ones.
  682 + */
  683 + emmc_clk: emmc-clk {
  684 + rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
  685 + };
  686 +
  687 + emmc_cmd: emmc-cmd {
  688 + rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
  689 + };
  690 +
  691 + emmc_bus8: emmc-bus8 {
  692 + rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
  693 + <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
  694 + <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
  695 + <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
  696 + <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
  697 + <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
  698 + <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
  699 + <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
  700 + };
  701 + };
  702 +
  703 + headset {
  704 + ts3a227e_int_l: ts3a227e-int-l {
  705 + rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
  706 + };
  707 + };
  708 +
  709 + pmic {
  710 + pmic_int_l: pmic-int-l {
  711 + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
  712 + };
  713 + };
  714 +
  715 + reboot {
  716 + ap_warm_reset_h: ap-warm-reset-h {
  717 + rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
  718 + };
  719 + };
  720 +
  721 + sdio0 {
  722 + wifi_enable_h: wifienable-h {
  723 + rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
  724 + };
  725 +
  726 + /* NOTE: mislabelled on schematic; should be bt_enable_h */
  727 + bt_enable_l: bt-enable-l {
  728 + rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
  729 + };
  730 +
  731 + /*
  732 + * We run sdio0 at max speed; bump up drive strength.
  733 + * We also have external pulls, so disable the internal ones.
  734 + */
  735 + sdio0_bus4: sdio0-bus4 {
  736 + rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
  737 + <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
  738 + <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
  739 + <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
  740 + };
  741 +
  742 + sdio0_cmd: sdio0-cmd {
  743 + rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
  744 + };
  745 +
  746 + sdio0_clk: sdio0-clk {
  747 + rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
  748 + };
  749 +
  750 + /*
  751 + * These pins are only present on very new veyron boards; on
  752 + * older boards bt_dev_wake is simply always high. Note that
  753 + * gpio4_26 is a NC on old veyron boards, so it doesn't hurt
  754 + * to map this pin everywhere
  755 + */
  756 + bt_dev_wake_sleep: bt-dev-wake-sleep {
  757 + rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_low>;
  758 + };
  759 +
  760 + bt_dev_wake_awake: bt-dev-wake-awake {
  761 + rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_high>;
  762 + };
  763 + };
  764 +
  765 + sdmmc {
  766 + /*
  767 + * We run sdmmc at max speed; bump up drive strength.
  768 + * We also have external pulls, so disable the internal ones.
  769 + */
  770 + sdmmc_bus4: sdmmc-bus4 {
  771 + rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
  772 + <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
  773 + <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
  774 + <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
  775 + };
  776 +
  777 + sdmmc_clk: sdmmc-clk {
  778 + rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
  779 + };
  780 +
  781 + sdmmc_cmd: sdmmc-cmd {
  782 + rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
  783 + };
  784 +
  785 + /*
  786 + * Builtin CD line is hooked to ground to prevent JTAG at boot
  787 + * (and also to get the voltage rail correct). Make we
  788 + * configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't
  789 + * think there's a card inserted
  790 + */
  791 + sdmmc_cd_disabled: sdmmc-cd-disabled {
  792 + rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>;
  793 + };
  794 +
  795 + /* This is where we actually hook up CD */
  796 + sdmmc_cd_gpio: sdmmc-cd-gpio {
  797 + rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>;
  798 + };
  799 + };
  800 +
  801 + tpm {
  802 + tpm_int_h: tpm-int-h {
  803 + rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
  804 + };
  805 + };
  806 +
  807 + write-protect {
  808 + fw_wp_ap: fw-wp-ap {
  809 + rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
  810 + };
  811 + };
  812 +};
  813 +
  814 +&usbphy {
  815 + status = "okay";
  816 +};
  817 +
  818 +&usb_host0_ehci {
  819 + status = "okay";
  820 + needs-reset-on-resume;
  821 +};
  822 +
  823 +&usb_host1 {
  824 + status = "okay";
  825 +};
  826 +
  827 +&usb_otg {
  828 + dr_mode = "host";
  829 + status = "okay";
  830 + assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
  831 + assigned-clock-parents = <&cru SCLK_OTGPHY0>;
  832 +};
  833 +
  834 +&sdmmc {
  835 + u-boot,dm-pre-reloc;
  836 +};
  837 +
  838 +&gpio3 {
  839 + u-boot,dm-pre-reloc;
  840 +};
  841 +
  842 +&gpio8 {
  843 + u-boot,dm-pre-reloc;
  844 +};
arch/arm/mach-rockchip/rk3288/Kconfig
Diff comments   View file @ e2e947f
... ... @@ -8,8 +8,18 @@
8 8 also includes on-board eMMC and 1GB of SDRAM. Expansion connectors
9 9 provide access to display pins, I2C, SPI, UART and GPIOs.
10 10  
  11 +config TARGET_CHROMEBOOK_JERRY
  12 + bool "Google/Rockchip Veyron-Jerry Chromebook"
  13 + help
  14 + Jerry is a RK3288-based clamshell device with 2 USB 3.0 ports,
  15 + HDMI, an 11.9 inch EDP display, micro-SD card, touchpad and
  16 + WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
  17 + the keyboard and battery functions.
  18 +
11 19 config SYS_SOC
12 20 default "rockchip"
  21 +
  22 +source "board/google/chromebook_jerry/Kconfig"
13 23  
14 24 source "board/firefly/firefly-rk3288/Kconfig"
15 25  
board/google/chromebook_jerry/Kconfig
Diff comments   View file @ e2e947f
  1 +if TARGET_CHROMEBOOK_JERRY
  2 +
  3 +config SYS_BOARD
  4 + default "chromebook_jerry"
  5 +
  6 +config SYS_VENDOR
  7 + default "google"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "chromebook_jerry"
  11 +
  12 +config BOARD_SPECIFIC_OPTIONS # dummy
  13 + def_bool y
  14 +
  15 +endif
board/google/chromebook_jerry/MAINTAINERS
Diff comments   View file @ e2e947f
  1 +CHROMEBOOK JERRY BOARD
  2 +M: Simon Glass <sjg@chromium.org>
  3 +S: Maintained
  4 +F: board/google/chromebook_jerry/
  5 +F: include/configs/chromebook_jerry.h
  6 +F: configs/chromebook_jerry_defconfig
board/google/chromebook_jerry/Makefile
Diff comments   View file @ e2e947f
  1 +#
  2 +# (C) Copyright 2015 Google, Inc
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +obj-y += jerry.o
board/google/chromebook_jerry/jerry.c
Diff comments   View file @ e2e947f
  1 +/*
  2 + * (C) Copyright 2015 Google, Inc
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
board/google/common/Makefile
Diff comments   View file @ e2e947f
... ... @@ -4,5 +4,5 @@
4 4 # SPDX-License-Identifier: GPL-2.0+
5 5 #
6 6  
7   -obj-y += early_init.o
  7 +obj-$(CONFIG_X86) += early_init.o
configs/chromebook_jerry_defconfig
Diff comments   View file @ e2e947f
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_ROCKCHIP=y
  3 +CONFIG_SYS_MALLOC_F_LEN=0x2000
  4 +CONFIG_ROCKCHIP_RK3288=y
  5 +CONFIG_TARGET_CHROMEBOOK_JERRY=y
  6 +CONFIG_DEFAULT_DEVICE_TREE="rk3288-jerry"
  7 +CONFIG_SPL_STACK_R=y
  8 +CONFIG_SPL_STACK_R_ADDR=0x80000
  9 +# CONFIG_CMD_IMLS is not set
  10 +# CONFIG_CMD_SETEXPR is not set
  11 +CONFIG_CMD_PMIC=y
  12 +CONFIG_CMD_REGULATOR=y
  13 +CONFIG_SPL_OF_CONTROL=y
  14 +CONFIG_CLK=y
  15 +CONFIG_SPL_CLK=y
  16 +CONFIG_REGMAP=y
  17 +CONFIG_SYSCON=y
  18 +CONFIG_RESET=y
  19 +CONFIG_LED=y
  20 +CONFIG_SPL_LED=y
  21 +CONFIG_LED_GPIO=y
  22 +CONFIG_DEBUG_UART=y
  23 +CONFIG_DEBUG_UART_BASE=0xff690000
  24 +CONFIG_DEBUG_UART_CLOCK=24000000
  25 +CONFIG_DEBUG_UART_SHIFT=2
  26 +CONFIG_SYS_I2C_ROCKCHIP=y
  27 +CONFIG_PINCTRL=y
  28 +CONFIG_PINCTRL_SIMPLE=y
  29 +CONFIG_SPL_PINCTRL=y
  30 +CONFIG_SPL_PINCTRL_SIMPLE=y
  31 +CONFIG_ROCKCHIP_PINCTRL=y
  32 +CONFIG_ROCKCHIP_GPIO=y
  33 +CONFIG_DM_PMIC=y
  34 +CONFIG_PMIC_ACT8846=y
  35 +CONFIG_DM_REGULATOR=y
  36 +CONFIG_REGULATOR_ACT8846=y
  37 +CONFIG_RAM=y
  38 +CONFIG_SPL_RAM=y
  39 +CONFIG_DM_MMC=y
  40 +CONFIG_ROCKCHIP_DWMMC=y
  41 +CONFIG_USE_PRIVATE_LIBGCC=y
  42 +CONFIG_CMD_DHRYSTONE=y
  43 +CONFIG_ERRNO_STR=y
include/configs/chromebook_jerry.h
Diff comments   View file @ e2e947f
  1 +/*
  2 + * (C) Copyright 2015 Google, Inc
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __CONFIG_H
  8 +#define __CONFIG_H
  9 +
  10 +#include <configs/rk3288_common.h>
  11 +
  12 +#define CONFIG_SPL_SPI_SUPPORT
  13 +#define CONFIG_SPL_SPI_FLASH_SUPPORT
  14 +#define CONFIG_SPL_SPI_LOAD
  15 +
  16 +#endif