MIPS: add support for Broadcom MIPS BCM6358 SoC family

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>

MIPS: add support for Broadcom MIPS BCM6358 SoC family
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas · Daniel Schwierzeck
1 parent ee422142f4
Showing 4 changed files with 190 additions and 1 deletions Side-by-side Diff
arch/mips/dts/brcm,bcm6358.dtsi
arch/mips/mach-bmips/Kconfig
arch/mips/mach-bmips/include/ioremap.h
include/configs/bmips_bcm6358.h
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,bcm6358";
+
+	cpus {
+		reg = <0xfffe0000 0x4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;
+
+		cpu@0 {
+			compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		cpu@1 {
+			compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <1>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	pflash: nor@1e000000 {
+		compatible = "cfi-flash";
+		reg = <0x1e000000 0x2000000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		status = "disabled";
+	};
+
+	ubus {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		pll_cntl: syscon@fffe0008 {
+			compatible = "syscon";
+			reg = <0xfffe0008 0x4>;
+		};
+
+		syscon-reboot {
+			compatible = "syscon-reboot";
+			regmap = <&pll_cntl>;
+			offset = <0x0>;
+			mask = <0x1>;
+		};
+
+		uart0: serial@fffe0100 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0xfffe0100 0x18>;
+			clocks = <&periph_osc>;
+
+			status = "disabled";
+		};
+
+		uart1: serial@fffe0120 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0xfffe0120 0x18>;
+			clocks = <&periph_osc>;
+
+			status = "disabled";
+		};
+
+		memory-controller@fffe1200 {
+			compatible = "brcm,bcm6358-mc";
+			reg = <0xfffe1200 0x1000>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
@@ -2,7 +2,23 @@
 	depends on ARCH_BMIPS
  
 config SYS_SOC
-	default "none"
+	default "bcm6358" if SOC_BMIPS_BCM6358
+
+choice
+	prompt "Broadcom MIPS SoC select"
+
+config SOC_BMIPS_BCM6358
+	bool "BMIPS BCM6358 family"
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select MIPS_TUNE_4KC
+	select MIPS_L1_CACHE_SHIFT_4
+	select SWAP_IO_SPACE
+	select SYSRESET_SYSCON
+	help
+	  This supports BMIPS BCM6358 family including BCM6358 and BCM6359.
+
+endchoice
  
 choice
 	prompt "Boot mode"
+/*
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+#ifndef __ASM_MACH_BMIPS_IOREMAP_H
+#define __ASM_MACH_BMIPS_IOREMAP_H
+
+#include <linux/types.h>
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
+						phys_addr_t size)
+{
+	return phys_addr;
+}
+
+static inline int is_bmips_internal_registers(phys_addr_t offset)
+{
+#if defined(CONFIG_SOC_BMIPS_BCM6358)
+	if (offset >= 0xfffe0000)
+		return 1;
+#endif
+
+	return 0;
+}
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+						unsigned long flags)
+{
+	if (is_bmips_internal_registers(offset))
+		return (void __iomem *)offset;
+
+	return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+	return is_bmips_internal_registers((unsigned long)addr);
+}
+
+#define _page_cachable_default	_CACHE_CACHABLE_NONCOHERENT
+
+#endif /* __ASM_MACH_BMIPS_IOREMAP_H */
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6358_H
+#define __CONFIG_BMIPS_BCM6358_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	150000000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	0x2000
+#endif
+
+#define CONFIG_SYS_FLASH_BASE			0xbe000000
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+
+#endif /* __CONFIG_BMIPS_BCM6358_H */
	1	+/*
	2	+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#include <dt-bindings/gpio/gpio.h>
	8	+#include "skeleton.dtsi"
	9	+
	10	+/ {
	11	+ compatible = "brcm,bcm6358";
	12	+
	13	+ cpus {
	14	+ reg = <0xfffe0000 0x4>;
	15	+ #address-cells = <1>;
	16	+ #size-cells = <0>;
	17	+ u-boot,dm-pre-reloc;
	18	+
	19	+ cpu@0 {
	20	+ compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
	21	+ device_type = "cpu";
	22	+ reg = <0>;
	23	+ u-boot,dm-pre-reloc;
	24	+ };
	25	+
	26	+ cpu@1 {
	27	+ compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
	28	+ device_type = "cpu";
	29	+ reg = <1>;
	30	+ u-boot,dm-pre-reloc;
	31	+ };
	32	+ };
	33	+
	34	+ clocks {
	35	+ compatible = "simple-bus";
	36	+ #address-cells = <1>;
	37	+ #size-cells = <1>;
	38	+ u-boot,dm-pre-reloc;
	39	+
	40	+ periph_osc: periph-osc {
	41	+ compatible = "fixed-clock";
	42	+ #clock-cells = <0>;
	43	+ clock-frequency = <50000000>;
	44	+ u-boot,dm-pre-reloc;
	45	+ };
	46	+ };
	47	+
	48	+ pflash: nor@1e000000 {
	49	+ compatible = "cfi-flash";
	50	+ reg = <0x1e000000 0x2000000>;
	51	+ bank-width = <2>;
	52	+ #address-cells = <1>;
	53	+ #size-cells = <1>;
	54	+
	55	+ status = "disabled";
	56	+ };
	57	+
	58	+ ubus {
	59	+ compatible = "simple-bus";
	60	+ #address-cells = <1>;
	61	+ #size-cells = <1>;
	62	+ u-boot,dm-pre-reloc;
	63	+
	64	+ pll_cntl: syscon@fffe0008 {
	65	+ compatible = "syscon";
	66	+ reg = <0xfffe0008 0x4>;
	67	+ };
	68	+
	69	+ syscon-reboot {
	70	+ compatible = "syscon-reboot";
	71	+ regmap = <&pll_cntl>;
	72	+ offset = <0x0>;
	73	+ mask = <0x1>;
	74	+ };
	75	+
	76	+ uart0: serial@fffe0100 {
	77	+ compatible = "brcm,bcm6345-uart";
	78	+ reg = <0xfffe0100 0x18>;
	79	+ clocks = <&periph_osc>;
	80	+
	81	+ status = "disabled";
	82	+ };
	83	+
	84	+ uart1: serial@fffe0120 {
	85	+ compatible = "brcm,bcm6345-uart";
	86	+ reg = <0xfffe0120 0x18>;
	87	+ clocks = <&periph_osc>;
	88	+
	89	+ status = "disabled";
	90	+ };
	91	+
	92	+ memory-controller@fffe1200 {
	93	+ compatible = "brcm,bcm6358-mc";
	94	+ reg = <0xfffe1200 0x1000>;
	95	+ u-boot,dm-pre-reloc;
	96	+ };
	97	+ };
	98	+};
...	...	@@ -2,7 +2,23 @@
2	2	depends on ARCH_BMIPS
3	3
4	4	config SYS_SOC
5		- default "none"
	5	+ default "bcm6358" if SOC_BMIPS_BCM6358
	6	+
	7	+choice
	8	+ prompt "Broadcom MIPS SoC select"
	9	+
	10	+config SOC_BMIPS_BCM6358
	11	+ bool "BMIPS BCM6358 family"
	12	+ select SUPPORTS_BIG_ENDIAN
	13	+ select SUPPORTS_CPU_MIPS32_R1
	14	+ select MIPS_TUNE_4KC
	15	+ select MIPS_L1_CACHE_SHIFT_4
	16	+ select SWAP_IO_SPACE
	17	+ select SYSRESET_SYSCON
	18	+ help
	19	+ This supports BMIPS BCM6358 family including BCM6358 and BCM6359.
	20	+
	21	+endchoice
6	22
7	23	choice
8	24	prompt "Boot mode"
	1	+/*
	2	+ * SPDX-License-Identifier: GPL-2.0
	3	+ */
	4	+#ifndef __ASM_MACH_BMIPS_IOREMAP_H
	5	+#define __ASM_MACH_BMIPS_IOREMAP_H
	6	+
	7	+#include <linux/types.h>
	8	+
	9	+/*
	10	+ * Allow physical addresses to be fixed up to help peripherals located
	11	+ * outside the low 32-bit range -- generic pass-through version.
	12	+ */
	13	+static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
	14	+ phys_addr_t size)
	15	+{
	16	+ return phys_addr;
	17	+}
	18	+
	19	+static inline int is_bmips_internal_registers(phys_addr_t offset)
	20	+{
	21	+#if defined(CONFIG_SOC_BMIPS_BCM6358)
	22	+ if (offset >= 0xfffe0000)
	23	+ return 1;
	24	+#endif
	25	+
	26	+ return 0;
	27	+}
	28	+
	29	+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
	30	+ unsigned long flags)
	31	+{
	32	+ if (is_bmips_internal_registers(offset))
	33	+ return (void __iomem *)offset;
	34	+
	35	+ return NULL;
	36	+}
	37	+
	38	+static inline int plat_iounmap(const volatile void __iomem *addr)
	39	+{
	40	+ return is_bmips_internal_registers((unsigned long)addr);
	41	+}
	42	+
	43	+#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
	44	+
	45	+#endif /* __ASM_MACH_BMIPS_IOREMAP_H */