Eric Lee / smarc-uboot

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Commit e384b6442463f95ba94a6a23f5252befa5ed239e

Authored by Adrian Alonso
Committed by Ye Li
1 parent c042f46cf7
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

MLK-23927: board: freescale: imx8mm audio board 2.0 

Add support for imx8mm audio board 2.0 support
reuse common settings from imx8mm evk som
Rework for imx_v2020.04 defconfig, dts and SPL

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>

Showing 12 changed files with 3443 additions and 1 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ e384b64
... ... @@ -788,7 +788,8 @@
788 788 imx8mq-ddr3l-val.dtb \
789 789 imx8mq-ddr4-val.dtb \
790 790 imx8mq-evk.dtb \
791   - imx8mp-evk.dtb
  791 + imx8mp-evk.dtb \
  792 + imx8mm-ab2.dtb
792 793  
793 794 dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb
794 795  
arch/arm/dts/imx8mm-ab2-u-boot.dtsi
Diff comments   View file @ e384b64
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2020 NXP
  4 + */
  5 +
  6 +/ {
  7 + firmware {
  8 + optee {
  9 + compatible = "linaro,optee-tz";
  10 + method = "smc";
  11 + };
  12 + };
  13 +};
  14 +
  15 +&{/soc@0} {
  16 + u-boot,dm-pre-reloc;
  17 + u-boot,dm-spl;
  18 +};
  19 +
  20 +&clk {
  21 + u-boot,dm-spl;
  22 + u-boot,dm-pre-reloc;
  23 + /delete-property/ assigned-clocks;
  24 + /delete-property/ assigned-clock-parents;
  25 + /delete-property/ assigned-clock-rates;
  26 +};
  27 +
  28 +&osc_24m {
  29 + u-boot,dm-spl;
  30 + u-boot,dm-pre-reloc;
  31 +};
  32 +
  33 +&aips1 {
  34 + u-boot,dm-spl;
  35 + u-boot,dm-pre-reloc;
  36 +};
  37 +
  38 +&aips2 {
  39 + u-boot,dm-spl;
  40 +};
  41 +
  42 +&aips3 {
  43 + u-boot,dm-spl;
  44 +};
  45 +
  46 +&iomuxc {
  47 + u-boot,dm-spl;
  48 +};
  49 +
  50 +&reg_usdhc2_vmmc {
  51 + u-boot,dm-spl;
  52 +};
  53 +
  54 +&pinctrl_reg_usdhc2_vmmc {
  55 + u-boot,dm-spl;
  56 +};
  57 +
  58 +&pinctrl_uart2 {
  59 + u-boot,dm-spl;
  60 +};
  61 +
  62 +&pinctrl_usdhc2_gpio {
  63 + u-boot,dm-spl;
  64 +};
  65 +
  66 +&pinctrl_usdhc2 {
  67 + u-boot,dm-spl;
  68 +};
  69 +
  70 +&pinctrl_usdhc3 {
  71 + u-boot,dm-spl;
  72 +};
  73 +
  74 +&gpio1 {
  75 + u-boot,dm-spl;
  76 +};
  77 +
  78 +&gpio2 {
  79 + u-boot,dm-spl;
  80 +};
  81 +
  82 +&gpio3 {
  83 + u-boot,dm-spl;
  84 +};
  85 +
  86 +&gpio4 {
  87 + u-boot,dm-spl;
  88 +};
  89 +
  90 +&gpio5 {
  91 + u-boot,dm-spl;
  92 +};
  93 +
  94 +&uart2 {
  95 + u-boot,dm-spl;
  96 +};
  97 +
  98 +&usdhc1 {
  99 + u-boot,dm-spl;
  100 + assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
  101 + assigned-clock-rates = <400000000>;
  102 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
  103 +};
  104 +
  105 +&usdhc2 {
  106 + u-boot,dm-spl;
  107 + sd-uhs-sdr104;
  108 + sd-uhs-ddr50;
  109 + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
  110 + assigned-clock-rates = <400000000>;
  111 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
  112 +};
  113 +
  114 +&usdhc3 {
  115 + u-boot,dm-spl;
  116 + mmc-hs400-1_8v;
  117 + mmc-hs400-enhanced-strobe;
  118 + assigned-clocks = <&clk IMX8MM_CLK_USDHC3>;
  119 + assigned-clock-rates = <400000000>;
  120 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
  121 +};
  122 +
  123 +&i2c1 {
  124 + u-boot,dm-spl;
  125 +};
  126 +
  127 +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
  128 + u-boot,dm-spl;
  129 +};
  130 +
  131 +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
  132 + u-boot,dm-spl;
  133 +};
  134 +
  135 +&pinctrl_i2c1 {
  136 + u-boot,dm-spl;
  137 +};
  138 +
  139 +&pinctrl_pmic {
  140 + u-boot,dm-spl;
  141 +};
  142 +
  143 +&flexspi {
  144 + assigned-clock-rates = <100000000>;
  145 + assigned-clocks = <&clk IMX8MM_CLK_QSPI>;
  146 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
  147 +};
arch/arm/dts/imx8mm-ab2.dts
Diff comments   View file @ e384b64
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 +/*
  3 + * Copyright 2020 NXP
  4 + */
  5 +
  6 +/dts-v1/;
  7 +
  8 +#include "imx8mm.dtsi"
  9 +
  10 +/ {
  11 + model = "NXP i.MX8MM Audio board 2.0";
  12 + compatible = "fsl,imx8mm-ab2", "fsl,imx8mm";
  13 +
  14 + chosen {
  15 + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
  16 + stdout-path = &uart2;
  17 + };
  18 +
  19 + leds {
  20 + compatible = "gpio-leds";
  21 + pinctrl-names = "default";
  22 + pinctrl-0 = <&pinctrl_gpio_led>;
  23 +
  24 + status {
  25 + label = "status";
  26 + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  27 + default-state = "on";
  28 + };
  29 + };
  30 +
  31 + reg_usdhc2_vmmc: regulator-usdhc2 {
  32 + compatible = "regulator-fixed";
  33 + pinctrl-names = "default";
  34 + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  35 + regulator-name = "VSD_3V3";
  36 + regulator-min-microvolt = <3300000>;
  37 + regulator-max-microvolt = <3300000>;
  38 + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  39 + off-on-delay-us = <20000>;
  40 + enable-active-high;
  41 + };
  42 +
  43 + reg_ab2_ana_pwr: regulator-ab2-ana-pwr {
  44 + compatible = "regulator-fixed";
  45 + regulator-name = "ab2_ana_pwr";
  46 + pinctrl-names = "default";
  47 + pinctrl-0 = <&pinctrl_ab2_ana_pwr>;
  48 + regulator-min-microvolt = <3300000>;
  49 + regulator-max-microvolt = <3300000>;
  50 + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
  51 + enable-active-high;
  52 + };
  53 +
  54 + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 {
  55 + compatible = "regulator-fixed";
  56 + regulator-name = "ab2_vdd_pwr_5v0";
  57 + regulator-min-microvolt = <5000000>;
  58 + regulator-max-microvolt = <5000000>;
  59 + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
  60 + enable-active-high;
  61 + startup-delay-us = <100>;
  62 + u-boot,off-on-delay-us = <12000>;
  63 + };
  64 +};
  65 +
  66 +&A53_0 {
  67 + cpu-supply = <&buck2_reg>;
  68 +};
  69 +
  70 +&fec1 {
  71 + pinctrl-names = "default";
  72 + pinctrl-0 = <&pinctrl_fec1>;
  73 + phy-mode = "rgmii-id";
  74 + phy-handle = <&ethphy0>;
  75 + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
  76 + phy-reset-post-delay = <150>;
  77 + phy-reset-duration = <10>;
  78 + fsl,magic-packet;
  79 + status = "okay";
  80 +
  81 + mdio {
  82 + #address-cells = <1>;
  83 + #size-cells = <0>;
  84 +
  85 + ethphy0: ethernet-phy@0 {
  86 + compatible = "ethernet-phy-ieee802.3-c22";
  87 + reg = <1>;
  88 + eee-broken-1000t;
  89 + };
  90 + };
  91 +};
  92 +
  93 +&flexspi {
  94 + pinctrl-names = "default";
  95 + pinctrl-0 = <&pinctrl_flexspi>;
  96 + status = "okay";
  97 +
  98 + flash0: n25q256a@0 {
  99 + reg = <0>;
  100 + #address-cells = <1>;
  101 + #size-cells = <1>;
  102 + compatible = "spi-flash";
  103 + spi-max-frequency = <29000000>;
  104 + spi-nor,ddr-quad-read-dummy = <8>;
  105 + };
  106 +};
  107 +
  108 +&iomuxc {
  109 + pinctrl-names = "default";
  110 + pinctrl-0 = <&pinctrl_hog_1>;
  111 +
  112 + imx8mm-ab2 {
  113 + pinctrl_hog_1: hoggrp-1 {
  114 + fsl,pins = <
  115 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
  116 + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
  117 + >;
  118 + };
  119 +
  120 + pinctrl_fec1: fec1grp {
  121 + fsl,pins = <
  122 + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
  123 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
  124 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
  125 + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
  126 + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
  127 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
  128 + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
  129 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
  130 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
  131 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
  132 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
  133 + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
  134 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
  135 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
  136 + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19
  137 + >;
  138 + };
  139 +
  140 + pinctrl_flexspi: flexspigrp {
  141 + fsl,pins = <
  142 + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
  143 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84
  144 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84
  145 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84
  146 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84
  147 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84
  148 + >;
  149 + };
  150 +
  151 + pinctrl_gpio_led: gpioledgrp {
  152 + fsl,pins = <
  153 + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
  154 + >;
  155 + };
  156 +
  157 + pinctrl_i2c1: i2c1grp {
  158 + fsl,pins = <
  159 + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
  160 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
  161 + >;
  162 + };
  163 +
  164 + pinctrl_i2c2: i2c2grp {
  165 + fsl,pins = <
  166 + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
  167 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
  168 + >;
  169 + };
  170 +
  171 + pinctrl_i2c3: i2c3grp {
  172 + fsl,pins = <
  173 + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
  174 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
  175 + >;
  176 + };
  177 +
  178 + pinctrl_i2c1_gpio: i2c1grp-gpio {
  179 + fsl,pins = <
  180 + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3
  181 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3
  182 + >;
  183 + };
  184 +
  185 + pinctrl_i2c2_gpio: i2c2grp-gpio {
  186 + fsl,pins = <
  187 + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
  188 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
  189 + >;
  190 + };
  191 +
  192 + pinctrl_i2c3_gpio: i2c3grp-gpio {
  193 + fsl,pins = <
  194 + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
  195 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
  196 + >;
  197 + };
  198 +
  199 + pinctrl_pmic: pmicirq {
  200 + fsl,pins = <
  201 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
  202 + >;
  203 + };
  204 +
  205 + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
  206 + fsl,pins = <
  207 + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
  208 + >;
  209 + };
  210 +
  211 + pinctrl_ab2_ana_pwr: ab2anapwrgrp {
  212 + fsl,pins = <
  213 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
  214 + >;
  215 + };
  216 +
  217 + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp {
  218 + fsl,pins = <
  219 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41
  220 + >;
  221 + };
  222 +
  223 + pinctrl_uart2: uart1grp {
  224 + fsl,pins = <
  225 + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
  226 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
  227 + >;
  228 + };
  229 +
  230 + pinctrl_usdhc2_gpio: usdhc2grpgpio {
  231 + fsl,pins = <
  232 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
  233 + >;
  234 + };
  235 +
  236 + pinctrl_usdhc2: usdhc2grp {
  237 + fsl,pins = <
  238 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
  239 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
  240 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
  241 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
  242 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
  243 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
  244 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
  245 + >;
  246 + };
  247 +
  248 + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
  249 + fsl,pins = <
  250 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
  251 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
  252 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
  253 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
  254 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
  255 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
  256 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
  257 + >;
  258 + };
  259 +
  260 + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
  261 + fsl,pins = <
  262 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
  263 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
  264 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
  265 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
  266 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
  267 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
  268 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
  269 + >;
  270 + };
  271 +
  272 + pinctrl_usdhc3: usdhc3grp {
  273 + fsl,pins = <
  274 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
  275 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
  276 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
  277 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
  278 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
  279 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
  280 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
  281 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
  282 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
  283 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
  284 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
  285 + >;
  286 + };
  287 +
  288 + pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  289 + fsl,pins = <
  290 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
  291 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
  292 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
  293 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
  294 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
  295 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
  296 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
  297 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
  298 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
  299 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
  300 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
  301 + >;
  302 + };
  303 +
  304 + pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  305 + fsl,pins = <
  306 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
  307 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
  308 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
  309 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
  310 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
  311 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
  312 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
  313 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
  314 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
  315 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
  316 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
  317 + >;
  318 + };
  319 +
  320 + pinctrl_wdog: wdoggrp {
  321 + fsl,pins = <
  322 + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
  323 + >;
  324 + };
  325 + };
  326 +};
  327 +
  328 +&i2c1 {
  329 + clock-frequency = <400000>;
  330 + pinctrl-names = "default", "gpio";
  331 + pinctrl-0 = <&pinctrl_i2c1>;
  332 + pinctrl-1 = <&pinctrl_i2c1_gpio>;
  333 + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
  334 + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
  335 + status = "okay";
  336 +
  337 + pmic@4b {
  338 + compatible = "rohm,bd71847";
  339 + reg = <0x4b>;
  340 + pinctrl-0 = <&pinctrl_pmic>;
  341 + interrupt-parent = <&gpio1>;
  342 + interrupts = <3 GPIO_ACTIVE_LOW>;
  343 + rohm,reset-snvs-powered;
  344 +
  345 + regulators {
  346 + buck1_reg: BUCK1 {
  347 + regulator-name = "BUCK1";
  348 + regulator-min-microvolt = <700000>;
  349 + regulator-max-microvolt = <1300000>;
  350 + regulator-boot-on;
  351 + regulator-always-on;
  352 + regulator-ramp-delay = <1250>;
  353 + };
  354 +
  355 + buck2_reg: BUCK2 {
  356 + regulator-name = "BUCK2";
  357 + regulator-min-microvolt = <700000>;
  358 + regulator-max-microvolt = <1300000>;
  359 + regulator-boot-on;
  360 + regulator-always-on;
  361 + regulator-ramp-delay = <1250>;
  362 + rohm,dvs-run-voltage = <1000000>;
  363 + rohm,dvs-idle-voltage = <900000>;
  364 + };
  365 +
  366 + buck3_reg: BUCK3 {
  367 + // BUCK5 in datasheet
  368 + regulator-name = "BUCK3";
  369 + regulator-min-microvolt = <700000>;
  370 + regulator-max-microvolt = <1350000>;
  371 + regulator-boot-on;
  372 + regulator-always-on;
  373 + };
  374 +
  375 + buck4_reg: BUCK4 {
  376 + // BUCK6 in datasheet
  377 + regulator-name = "BUCK4";
  378 + regulator-min-microvolt = <3000000>;
  379 + regulator-max-microvolt = <3300000>;
  380 + regulator-boot-on;
  381 + regulator-always-on;
  382 + };
  383 +
  384 + buck5_reg: BUCK5 {
  385 + // BUCK7 in datasheet
  386 + regulator-name = "BUCK5";
  387 + regulator-min-microvolt = <1605000>;
  388 + regulator-max-microvolt = <1995000>;
  389 + regulator-boot-on;
  390 + regulator-always-on;
  391 + };
  392 +
  393 + buck6_reg: BUCK6 {
  394 + // BUCK8 in datasheet
  395 + regulator-name = "BUCK6";
  396 + regulator-min-microvolt = <800000>;
  397 + regulator-max-microvolt = <1400000>;
  398 + regulator-boot-on;
  399 + regulator-always-on;
  400 + };
  401 +
  402 + ldo1_reg: LDO1 {
  403 + regulator-name = "LDO1";
  404 + regulator-min-microvolt = <3000000>;
  405 + regulator-max-microvolt = <3300000>;
  406 + regulator-boot-on;
  407 + regulator-always-on;
  408 + };
  409 +
  410 + ldo2_reg: LDO2 {
  411 + regulator-name = "LDO2";
  412 + regulator-min-microvolt = <900000>;
  413 + regulator-max-microvolt = <900000>;
  414 + regulator-boot-on;
  415 + regulator-always-on;
  416 + };
  417 +
  418 + ldo3_reg: LDO3 {
  419 + regulator-name = "LDO3";
  420 + regulator-min-microvolt = <1800000>;
  421 + regulator-max-microvolt = <3300000>;
  422 + regulator-boot-on;
  423 + regulator-always-on;
  424 + };
  425 +
  426 + ldo4_reg: LDO4 {
  427 + regulator-name = "LDO4";
  428 + regulator-min-microvolt = <900000>;
  429 + regulator-max-microvolt = <1800000>;
  430 + regulator-boot-on;
  431 + regulator-always-on;
  432 + };
  433 +
  434 + ldo6_reg: LDO6 {
  435 + regulator-name = "LDO6";
  436 + regulator-min-microvolt = <900000>;
  437 + regulator-max-microvolt = <1800000>;
  438 + regulator-boot-on;
  439 + regulator-always-on;
  440 + };
  441 + };
  442 + };
  443 +};
  444 +
  445 +&i2c2 {
  446 + clock-frequency = <400000>;
  447 + pinctrl-names = "default", "gpio";
  448 + pinctrl-0 = <&pinctrl_i2c2>;
  449 + pinctrl-1 = <&pinctrl_i2c2_gpio>;
  450 + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
  451 + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
  452 + status = "okay";
  453 +};
  454 +
  455 +&i2c3 {
  456 + clock-frequency = <100000>;
  457 + pinctrl-names = "default", "gpio";
  458 + pinctrl-0 = <&pinctrl_i2c3>;
  459 + pinctrl-1 = <&pinctrl_i2c3_gpio>;
  460 + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
  461 + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
  462 + status = "okay";
  463 +};
  464 +
  465 +&snvs_pwrkey {
  466 + status = "okay";
  467 +};
  468 +
  469 +&uart2 { /* console */
  470 + pinctrl-names = "default";
  471 + pinctrl-0 = <&pinctrl_uart2>;
  472 + status = "okay";
  473 +};
  474 +
  475 +&usdhc2 {
  476 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
  477 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  478 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
  479 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
  480 + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
  481 + bus-width = <4>;
  482 + vmmc-supply = <&reg_usdhc2_vmmc>;
  483 + status = "okay";
  484 +};
  485 +
  486 +&usdhc3 {
  487 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
  488 + pinctrl-0 = <&pinctrl_usdhc3>;
  489 + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  490 + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  491 + bus-width = <8>;
  492 + non-removable;
  493 + status = "okay";
  494 +};
  495 +
  496 +&wdog1 {
  497 + pinctrl-names = "default";
  498 + pinctrl-0 = <&pinctrl_wdog>;
  499 + fsl,ext-reset-output;
  500 + status = "okay";
  501 +};
arch/arm/mach-imx/imx8m/Kconfig
Diff comments   View file @ e384b64
... ... @@ -96,6 +96,12 @@
96 96 select SUPPORT_SPL
97 97 select IMX8M_LPDDR4
98 98  
  99 +config TARGET_IMX8MM_AB2
  100 + bool "imx8mm LPDDR4 Audio board 2.0"
  101 + select IMX8MM
  102 + select SUPPORT_SPL
  103 + select IMX8M_LPDDR4
  104 +
99 105 config TARGET_VERDIN_IMX8MM
100 106 bool "Support Toradex Verdin iMX8M Mini module"
101 107 select IMX8MM
... ... @@ -106,6 +112,7 @@
106 112  
107 113 source "board/freescale/imx8mq_evk/Kconfig"
108 114 source "board/freescale/imx8mq_val/Kconfig"
  115 +source "board/freescale/imx8mm_ab2/Kconfig"
109 116 source "board/freescale/imx8mm_evk/Kconfig"
110 117 source "board/freescale/imx8mm_val/Kconfig"
111 118 source "board/freescale/imx8mn_evk/Kconfig"
board/freescale/imx8mm_ab2/Kconfig
Diff comments   View file @ e384b64
  1 +if TARGET_IMX8MM_AB2
  2 +
  3 +config SYS_BOARD
  4 + default "imx8mm_ab2"
  5 +
  6 +config SYS_VENDOR
  7 + default "freescale"
  8 +
  9 +if TARGET_IMX8MM_AB2
  10 +config SYS_CONFIG_NAME
  11 + default "imx8mm_ab2"
  12 +endif
  13 +
  14 +source "board/freescale/common/Kconfig"
  15 +
  16 +endif
board/freescale/imx8mm_ab2/Makefile
Diff comments   View file @ e384b64
  1 +#
  2 +# Copyright 2020 NXP
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +obj-y += imx8mm_ab2.o
  8 +
  9 +ifdef CONFIG_SPL_BUILD
  10 +obj-y += spl.o
  11 +obj-$(CONFIG_TARGET_IMX8MM_AB2) += lpddr4_imx8mm_som.o
  12 +endif
board/freescale/imx8mm_ab2/imx8mm_ab2.c
Diff comments   View file @ e384b64
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2020 NXP
  4 + */
  5 +
  6 +#include <common.h>
  7 +#include <malloc.h>
  8 +#include <errno.h>
  9 +#include <miiphy.h>
  10 +#include <netdev.h>
  11 +#include <fsl_esdhc.h>
  12 +#include <mmc.h>
  13 +#include <asm/io.h>
  14 +#include <asm/arch/clock.h>
  15 +#ifdef CONFIG_TARGET_IMX8MM_AB2
  16 +#include <asm/arch/imx8mm_pins.h>
  17 +#endif
  18 +#include <asm/arch/sys_proto.h>
  19 +#include <asm-generic/gpio.h>
  20 +#include <asm/mach-imx/dma.h>
  21 +#include <asm/mach-imx/gpio.h>
  22 +#include <asm/mach-imx/iomux-v3.h>
  23 +#include <asm/mach-imx/mxc_i2c.h>
  24 +#include <spl.h>
  25 +
  26 +DECLARE_GLOBAL_DATA_PTR;
  27 +
  28 +#define PWR_EN_5V0 IMX_GPIO_NR(1, 7)
  29 +#define PWR_EN_ANA IMX_GPIO_NR(1, 10)
  30 +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  31 +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  32 +
  33 +#ifdef CONFIG_TARGET_IMX8MM_AB2
  34 +static iomux_v3_cfg_t const uart_pads[] = {
  35 + IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  36 + IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  37 +};
  38 +
  39 +static iomux_v3_cfg_t const wdog_pads[] = {
  40 + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  41 +};
  42 +
  43 +static iomux_v3_cfg_t const pwr_en_5v0[] = {
  44 + IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
  45 +};
  46 +
  47 +static iomux_v3_cfg_t const pwr_en_ana[] = {
  48 + IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  49 +};
  50 +#endif
  51 +
  52 +#ifdef CONFIG_NAND_MXS
  53 +static void setup_gpmi_nand(void)
  54 +{
  55 + init_nand_clk();
  56 +}
  57 +#endif
  58 +
  59 +int board_early_init_f(void)
  60 +{
  61 + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  62 +
  63 + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  64 +
  65 + set_wdog_reset(wdog);
  66 +
  67 + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  68 +
  69 + init_uart_clk(1);
  70 +
  71 + imx_iomux_v3_setup_multiple_pads(pwr_en_5v0, ARRAY_SIZE(pwr_en_5v0));
  72 + gpio_request(PWR_EN_5V0, "pwr_en_5v0");
  73 + gpio_direction_output(PWR_EN_5V0, 1);
  74 +
  75 + imx_iomux_v3_setup_multiple_pads(pwr_en_ana, ARRAY_SIZE(pwr_en_ana));
  76 + gpio_request(PWR_EN_ANA, "pwr_en_ana");
  77 + gpio_direction_output(PWR_EN_ANA, 1);
  78 +
  79 + return 0;
  80 +}
  81 +
  82 +static int setup_fec(void)
  83 +{
  84 + struct iomuxc_gpr_base_regs *gpr =
  85 + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  86 +
  87 + /* Use 125M anatop REF_CLK1 for ENET1, not from external */
  88 + clrsetbits_le32(&gpr->gpr[1],
  89 + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 0);
  90 +
  91 + return set_clk_enet(ENET_125MHZ);
  92 +}
  93 +
  94 +int board_phy_config(struct phy_device *phydev)
  95 +{
  96 + if (phydev->drv->config)
  97 + phydev->drv->config(phydev);
  98 +
  99 + return 0;
  100 +}
  101 +
  102 +int board_init(void)
  103 +{
  104 +#ifdef CONFIG_FEC_MXC
  105 + setup_fec();
  106 +#endif
  107 +
  108 +#ifdef CONFIG_NAND_MXS
  109 + setup_gpmi_nand();
  110 +#endif
  111 + return 0;
  112 +}
  113 +
  114 +int board_late_init(void)
  115 +{
  116 +#ifdef CONFIG_ENV_IS_IN_MMC
  117 + board_late_mmc_env_init();
  118 +#endif
  119 +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  120 + env_set("board_name", "AB2");
  121 + env_set("board_rev", "iMX8MM");
  122 +#endif
  123 + return 0;
  124 +}
board/freescale/imx8mm_ab2/lpddr4_imx8mm_som.c
Diff comments   View file @ e384b64
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright 2020 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Generated code from MX8M_DDR_tool
  7 + */
  8 +
  9 +#include <linux/kernel.h>
  10 +#include <asm/arch/ddr.h>
  11 +
  12 +struct dram_cfg_param ddr_ddrc_cfg[] = {
  13 + /* Initialize DDRC registers */
  14 + { 0x3d400304, 0x1 },
  15 + { 0x3d400030, 0x1 },
  16 + { 0x3d400000, 0xa1080020 },
  17 + { 0x3d400020, 0x223 },
  18 + { 0x3d400024, 0x16e3600 },
  19 + { 0x3d400064, 0x5b00d2 },
  20 + { 0x3d4000d0, 0xc00305ba },
  21 + { 0x3d4000d4, 0x940000 },
  22 + { 0x3d4000dc, 0xd4002d },
  23 + { 0x3d4000e0, 0x310000 },
  24 + { 0x3d4000e8, 0x66004d },
  25 + { 0x3d4000ec, 0x16004d },
  26 + { 0x3d400100, 0x191e1920 },
  27 + { 0x3d400104, 0x60630 },
  28 + { 0x3d40010c, 0xb0b000 },
  29 + { 0x3d400110, 0xe04080e },
  30 + { 0x3d400114, 0x2040c0c },
  31 + { 0x3d400118, 0x1010007 },
  32 + { 0x3d40011c, 0x401 },
  33 + { 0x3d400130, 0x20600 },
  34 + { 0x3d400134, 0xc100002 },
  35 + { 0x3d400138, 0xd8 },
  36 + { 0x3d400144, 0x96004b },
  37 + { 0x3d400180, 0x2ee0017 },
  38 + { 0x3d400184, 0x2605b8e },
  39 + { 0x3d400188, 0x0 },
  40 + { 0x3d400190, 0x497820a },
  41 + { 0x3d400194, 0x80303 },
  42 + { 0x3d4001b4, 0x170a },
  43 + { 0x3d4001a0, 0xe0400018 },
  44 + { 0x3d4001a4, 0xdf00e4 },
  45 + { 0x3d4001a8, 0x80000000 },
  46 + { 0x3d4001b0, 0x11 },
  47 + { 0x3d4001c0, 0x1 },
  48 + { 0x3d4001c4, 0x0 },
  49 + { 0x3d4000f4, 0xc99 },
  50 + { 0x3d400108, 0x70e1617 },
  51 + { 0x3d400200, 0x1f },
  52 + { 0x3d40020c, 0x0 },
  53 + { 0x3d400210, 0x1f1f },
  54 + { 0x3d400204, 0x80808 },
  55 + { 0x3d400214, 0x7070707 },
  56 + { 0x3d400218, 0x7070707 },
  57 +
  58 + /* performance setting */
  59 + { 0x3d400250, 0x29001701 },
  60 + { 0x3d400254, 0x2c },
  61 + { 0x3d40025c, 0x4000030 },
  62 + { 0x3d400264, 0x900093e7 },
  63 + { 0x3d40026c, 0x2005574 },
  64 + { 0x3d400400, 0x111 },
  65 + { 0x3d400408, 0x72ff },
  66 + { 0x3d400494, 0x2100e07 },
  67 + { 0x3d400498, 0x620096 },
  68 + { 0x3d40049c, 0x1100e07 },
  69 + { 0x3d4004a0, 0xc8012c },
  70 +
  71 + /* P1: 400mts */
  72 + { 0x3d402020, 0x21 },
  73 + { 0x3d402024, 0x30d400 },
  74 + { 0x3d402050, 0x20d040 },
  75 + { 0x3d402064, 0xc001c },
  76 + { 0x3d4020dc, 0x840000 },
  77 + { 0x3d4020e0, 0x310000 },
  78 + { 0x3d4020e8, 0x66004d },
  79 + { 0x3d4020ec, 0x16004d },
  80 + { 0x3d402100, 0xa040305 },
  81 + { 0x3d402104, 0x30407 },
  82 + { 0x3d402108, 0x203060b },
  83 + { 0x3d40210c, 0x505000 },
  84 + { 0x3d402110, 0x2040202 },
  85 + { 0x3d402114, 0x2030202 },
  86 + { 0x3d402118, 0x1010004 },
  87 + { 0x3d40211c, 0x301 },
  88 + { 0x3d402130, 0x20300 },
  89 + { 0x3d402134, 0xa100002 },
  90 + { 0x3d402138, 0x1d },
  91 + { 0x3d402144, 0x14000a },
  92 + { 0x3d402180, 0x640004 },
  93 + { 0x3d402190, 0x3818200 },
  94 + { 0x3d402194, 0x80303 },
  95 + { 0x3d4021b4, 0x100 },
  96 +
  97 + /* p2: 100mts */
  98 + { 0x3d403020, 0x21 },
  99 + { 0x3d403024, 0xc3500 },
  100 + { 0x3d403050, 0x20d040 },
  101 + { 0x3d403064, 0x30007 },
  102 + { 0x3d4030dc, 0x840000 },
  103 + { 0x3d4030e0, 0x310000 },
  104 + { 0x3d4030e8, 0x66004d },
  105 + { 0x3d4030ec, 0x16004d },
  106 + { 0x3d403100, 0xa010102 },
  107 + { 0x3d403104, 0x30404 },
  108 + { 0x3d403108, 0x203060b },
  109 + { 0x3d40310c, 0x505000 },
  110 + { 0x3d403110, 0x2040202 },
  111 + { 0x3d403114, 0x2030202 },
  112 + { 0x3d403118, 0x1010004 },
  113 + { 0x3d40311c, 0x301 },
  114 + { 0x3d403130, 0x20300 },
  115 + { 0x3d403134, 0xa100002 },
  116 + { 0x3d403138, 0x8 },
  117 + { 0x3d403144, 0x50003 },
  118 + { 0x3d403180, 0x190004 },
  119 + { 0x3d403190, 0x3818200 },
  120 + { 0x3d403194, 0x80303 },
  121 + { 0x3d4031b4, 0x100 },
  122 +
  123 + /* default boot point */
  124 + { 0x3d400028, 0x0 },
  125 +};
  126 +
  127 +/* PHY Initialize Configuration */
  128 +struct dram_cfg_param ddr_ddrphy_cfg[] = {
  129 + { 0x100a0, 0x0 },
  130 + { 0x100a1, 0x1 },
  131 + { 0x100a2, 0x2 },
  132 + { 0x100a3, 0x3 },
  133 + { 0x100a4, 0x4 },
  134 + { 0x100a5, 0x5 },
  135 + { 0x100a6, 0x6 },
  136 + { 0x100a7, 0x7 },
  137 + { 0x110a0, 0x0 },
  138 + { 0x110a1, 0x1 },
  139 + { 0x110a2, 0x3 },
  140 + { 0x110a3, 0x4 },
  141 + { 0x110a4, 0x5 },
  142 + { 0x110a5, 0x2 },
  143 + { 0x110a6, 0x7 },
  144 + { 0x110a7, 0x6 },
  145 + { 0x120a0, 0x0 },
  146 + { 0x120a1, 0x1 },
  147 + { 0x120a2, 0x3 },
  148 + { 0x120a3, 0x2 },
  149 + { 0x120a4, 0x5 },
  150 + { 0x120a5, 0x4 },
  151 + { 0x120a6, 0x7 },
  152 + { 0x120a7, 0x6 },
  153 + { 0x130a0, 0x0 },
  154 + { 0x130a1, 0x1 },
  155 + { 0x130a2, 0x2 },
  156 + { 0x130a3, 0x3 },
  157 + { 0x130a4, 0x4 },
  158 + { 0x130a5, 0x5 },
  159 + { 0x130a6, 0x6 },
  160 + { 0x130a7, 0x7 },
  161 + { 0x1005f, 0x1ff },
  162 + { 0x1015f, 0x1ff },
  163 + { 0x1105f, 0x1ff },
  164 + { 0x1115f, 0x1ff },
  165 + { 0x1205f, 0x1ff },
  166 + { 0x1215f, 0x1ff },
  167 + { 0x1305f, 0x1ff },
  168 + { 0x1315f, 0x1ff },
  169 + { 0x11005f, 0x1ff },
  170 + { 0x11015f, 0x1ff },
  171 + { 0x11105f, 0x1ff },
  172 + { 0x11115f, 0x1ff },
  173 + { 0x11205f, 0x1ff },
  174 + { 0x11215f, 0x1ff },
  175 + { 0x11305f, 0x1ff },
  176 + { 0x11315f, 0x1ff },
  177 + { 0x21005f, 0x1ff },
  178 + { 0x21015f, 0x1ff },
  179 + { 0x21105f, 0x1ff },
  180 + { 0x21115f, 0x1ff },
  181 + { 0x21205f, 0x1ff },
  182 + { 0x21215f, 0x1ff },
  183 + { 0x21305f, 0x1ff },
  184 + { 0x21315f, 0x1ff },
  185 + { 0x55, 0x1ff },
  186 + { 0x1055, 0x1ff },
  187 + { 0x2055, 0x1ff },
  188 + { 0x3055, 0x1ff },
  189 + { 0x4055, 0x1ff },
  190 + { 0x5055, 0x1ff },
  191 + { 0x6055, 0x1ff },
  192 + { 0x7055, 0x1ff },
  193 + { 0x8055, 0x1ff },
  194 + { 0x9055, 0x1ff },
  195 + { 0x200c5, 0x19 },
  196 + { 0x1200c5, 0x7 },
  197 + { 0x2200c5, 0x7 },
  198 + { 0x2002e, 0x2 },
  199 + { 0x12002e, 0x2 },
  200 + { 0x22002e, 0x2 },
  201 + { 0x90204, 0x0 },
  202 + { 0x190204, 0x0 },
  203 + { 0x290204, 0x0 },
  204 + { 0x20024, 0x1ab },
  205 + { 0x2003a, 0x0 },
  206 + { 0x120024, 0x1ab },
  207 + { 0x2003a, 0x0 },
  208 + { 0x220024, 0x1ab },
  209 + { 0x2003a, 0x0 },
  210 + { 0x20056, 0x3 },
  211 + { 0x120056, 0xa },
  212 + { 0x220056, 0xa },
  213 + { 0x1004d, 0xe00 },
  214 + { 0x1014d, 0xe00 },
  215 + { 0x1104d, 0xe00 },
  216 + { 0x1114d, 0xe00 },
  217 + { 0x1204d, 0xe00 },
  218 + { 0x1214d, 0xe00 },
  219 + { 0x1304d, 0xe00 },
  220 + { 0x1314d, 0xe00 },
  221 + { 0x11004d, 0xe00 },
  222 + { 0x11014d, 0xe00 },
  223 + { 0x11104d, 0xe00 },
  224 + { 0x11114d, 0xe00 },
  225 + { 0x11204d, 0xe00 },
  226 + { 0x11214d, 0xe00 },
  227 + { 0x11304d, 0xe00 },
  228 + { 0x11314d, 0xe00 },
  229 + { 0x21004d, 0xe00 },
  230 + { 0x21014d, 0xe00 },
  231 + { 0x21104d, 0xe00 },
  232 + { 0x21114d, 0xe00 },
  233 + { 0x21204d, 0xe00 },
  234 + { 0x21214d, 0xe00 },
  235 + { 0x21304d, 0xe00 },
  236 + { 0x21314d, 0xe00 },
  237 + { 0x10049, 0xeba },
  238 + { 0x10149, 0xeba },
  239 + { 0x11049, 0xeba },
  240 + { 0x11149, 0xeba },
  241 + { 0x12049, 0xeba },
  242 + { 0x12149, 0xeba },
  243 + { 0x13049, 0xeba },
  244 + { 0x13149, 0xeba },
  245 + { 0x110049, 0xeba },
  246 + { 0x110149, 0xeba },
  247 + { 0x111049, 0xeba },
  248 + { 0x111149, 0xeba },
  249 + { 0x112049, 0xeba },
  250 + { 0x112149, 0xeba },
  251 + { 0x113049, 0xeba },
  252 + { 0x113149, 0xeba },
  253 + { 0x210049, 0xeba },
  254 + { 0x210149, 0xeba },
  255 + { 0x211049, 0xeba },
  256 + { 0x211149, 0xeba },
  257 + { 0x212049, 0xeba },
  258 + { 0x212149, 0xeba },
  259 + { 0x213049, 0xeba },
  260 + { 0x213149, 0xeba },
  261 + { 0x43, 0x63 },
  262 + { 0x1043, 0x63 },
  263 + { 0x2043, 0x63 },
  264 + { 0x3043, 0x63 },
  265 + { 0x4043, 0x63 },
  266 + { 0x5043, 0x63 },
  267 + { 0x6043, 0x63 },
  268 + { 0x7043, 0x63 },
  269 + { 0x8043, 0x63 },
  270 + { 0x9043, 0x63 },
  271 + { 0x20018, 0x3 },
  272 + { 0x20075, 0x4 },
  273 + { 0x20050, 0x0 },
  274 + { 0x20008, 0x2ee },
  275 + { 0x120008, 0x64 },
  276 + { 0x220008, 0x19 },
  277 + { 0x20088, 0x9 },
  278 + { 0x200b2, 0xdc },
  279 + { 0x10043, 0x5a1 },
  280 + { 0x10143, 0x5a1 },
  281 + { 0x11043, 0x5a1 },
  282 + { 0x11143, 0x5a1 },
  283 + { 0x12043, 0x5a1 },
  284 + { 0x12143, 0x5a1 },
  285 + { 0x13043, 0x5a1 },
  286 + { 0x13143, 0x5a1 },
  287 + { 0x1200b2, 0xdc },
  288 + { 0x110043, 0x5a1 },
  289 + { 0x110143, 0x5a1 },
  290 + { 0x111043, 0x5a1 },
  291 + { 0x111143, 0x5a1 },
  292 + { 0x112043, 0x5a1 },
  293 + { 0x112143, 0x5a1 },
  294 + { 0x113043, 0x5a1 },
  295 + { 0x113143, 0x5a1 },
  296 + { 0x2200b2, 0xdc },
  297 + { 0x210043, 0x5a1 },
  298 + { 0x210143, 0x5a1 },
  299 + { 0x211043, 0x5a1 },
  300 + { 0x211143, 0x5a1 },
  301 + { 0x212043, 0x5a1 },
  302 + { 0x212143, 0x5a1 },
  303 + { 0x213043, 0x5a1 },
  304 + { 0x213143, 0x5a1 },
  305 + { 0x200fa, 0x1 },
  306 + { 0x1200fa, 0x1 },
  307 + { 0x2200fa, 0x1 },
  308 + { 0x20019, 0x1 },
  309 + { 0x120019, 0x1 },
  310 + { 0x220019, 0x1 },
  311 + { 0x200f0, 0x660 },
  312 + { 0x200f1, 0x0 },
  313 + { 0x200f2, 0x4444 },
  314 + { 0x200f3, 0x8888 },
  315 + { 0x200f4, 0x5665 },
  316 + { 0x200f5, 0x0 },
  317 + { 0x200f6, 0x0 },
  318 + { 0x200f7, 0xf000 },
  319 + { 0x20025, 0x0 },
  320 + { 0x2002d, 0x0 },
  321 + { 0x12002d, 0x0 },
  322 + { 0x22002d, 0x0 },
  323 + { 0x200c7, 0x21 },
  324 + { 0x1200c7, 0x21 },
  325 + { 0x2200c7, 0x21 },
  326 + { 0x200ca, 0x24 },
  327 + { 0x1200ca, 0x24 },
  328 + { 0x2200ca, 0x24 },
  329 +};
  330 +
  331 +/* ddr phy trained csr */
  332 +struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
  333 + { 0x200b2, 0x0 },
  334 + { 0x1200b2, 0x0 },
  335 + { 0x2200b2, 0x0 },
  336 + { 0x200cb, 0x0 },
  337 + { 0x10043, 0x0 },
  338 + { 0x110043, 0x0 },
  339 + { 0x210043, 0x0 },
  340 + { 0x10143, 0x0 },
  341 + { 0x110143, 0x0 },
  342 + { 0x210143, 0x0 },
  343 + { 0x11043, 0x0 },
  344 + { 0x111043, 0x0 },
  345 + { 0x211043, 0x0 },
  346 + { 0x11143, 0x0 },
  347 + { 0x111143, 0x0 },
  348 + { 0x211143, 0x0 },
  349 + { 0x12043, 0x0 },
  350 + { 0x112043, 0x0 },
  351 + { 0x212043, 0x0 },
  352 + { 0x12143, 0x0 },
  353 + { 0x112143, 0x0 },
  354 + { 0x212143, 0x0 },
  355 + { 0x13043, 0x0 },
  356 + { 0x113043, 0x0 },
  357 + { 0x213043, 0x0 },
  358 + { 0x13143, 0x0 },
  359 + { 0x113143, 0x0 },
  360 + { 0x213143, 0x0 },
  361 + { 0x80, 0x0 },
  362 + { 0x100080, 0x0 },
  363 + { 0x200080, 0x0 },
  364 + { 0x1080, 0x0 },
  365 + { 0x101080, 0x0 },
  366 + { 0x201080, 0x0 },
  367 + { 0x2080, 0x0 },
  368 + { 0x102080, 0x0 },
  369 + { 0x202080, 0x0 },
  370 + { 0x3080, 0x0 },
  371 + { 0x103080, 0x0 },
  372 + { 0x203080, 0x0 },
  373 + { 0x4080, 0x0 },
  374 + { 0x104080, 0x0 },
  375 + { 0x204080, 0x0 },
  376 + { 0x5080, 0x0 },
  377 + { 0x105080, 0x0 },
  378 + { 0x205080, 0x0 },
  379 + { 0x6080, 0x0 },
  380 + { 0x106080, 0x0 },
  381 + { 0x206080, 0x0 },
  382 + { 0x7080, 0x0 },
  383 + { 0x107080, 0x0 },
  384 + { 0x207080, 0x0 },
  385 + { 0x8080, 0x0 },
  386 + { 0x108080, 0x0 },
  387 + { 0x208080, 0x0 },
  388 + { 0x9080, 0x0 },
  389 + { 0x109080, 0x0 },
  390 + { 0x209080, 0x0 },
  391 + { 0x10080, 0x0 },
  392 + { 0x110080, 0x0 },
  393 + { 0x210080, 0x0 },
  394 + { 0x10180, 0x0 },
  395 + { 0x110180, 0x0 },
  396 + { 0x210180, 0x0 },
  397 + { 0x11080, 0x0 },
  398 + { 0x111080, 0x0 },
  399 + { 0x211080, 0x0 },
  400 + { 0x11180, 0x0 },
  401 + { 0x111180, 0x0 },
  402 + { 0x211180, 0x0 },
  403 + { 0x12080, 0x0 },
  404 + { 0x112080, 0x0 },
  405 + { 0x212080, 0x0 },
  406 + { 0x12180, 0x0 },
  407 + { 0x112180, 0x0 },
  408 + { 0x212180, 0x0 },
  409 + { 0x13080, 0x0 },
  410 + { 0x113080, 0x0 },
  411 + { 0x213080, 0x0 },
  412 + { 0x13180, 0x0 },
  413 + { 0x113180, 0x0 },
  414 + { 0x213180, 0x0 },
  415 + { 0x10081, 0x0 },
  416 + { 0x110081, 0x0 },
  417 + { 0x210081, 0x0 },
  418 + { 0x10181, 0x0 },
  419 + { 0x110181, 0x0 },
  420 + { 0x210181, 0x0 },
  421 + { 0x11081, 0x0 },
  422 + { 0x111081, 0x0 },
  423 + { 0x211081, 0x0 },
  424 + { 0x11181, 0x0 },
  425 + { 0x111181, 0x0 },
  426 + { 0x211181, 0x0 },
  427 + { 0x12081, 0x0 },
  428 + { 0x112081, 0x0 },
  429 + { 0x212081, 0x0 },
  430 + { 0x12181, 0x0 },
  431 + { 0x112181, 0x0 },
  432 + { 0x212181, 0x0 },
  433 + { 0x13081, 0x0 },
  434 + { 0x113081, 0x0 },
  435 + { 0x213081, 0x0 },
  436 + { 0x13181, 0x0 },
  437 + { 0x113181, 0x0 },
  438 + { 0x213181, 0x0 },
  439 + { 0x100d0, 0x0 },
  440 + { 0x1100d0, 0x0 },
  441 + { 0x2100d0, 0x0 },
  442 + { 0x101d0, 0x0 },
  443 + { 0x1101d0, 0x0 },
  444 + { 0x2101d0, 0x0 },
  445 + { 0x110d0, 0x0 },
  446 + { 0x1110d0, 0x0 },
  447 + { 0x2110d0, 0x0 },
  448 + { 0x111d0, 0x0 },
  449 + { 0x1111d0, 0x0 },
  450 + { 0x2111d0, 0x0 },
  451 + { 0x120d0, 0x0 },
  452 + { 0x1120d0, 0x0 },
  453 + { 0x2120d0, 0x0 },
  454 + { 0x121d0, 0x0 },
  455 + { 0x1121d0, 0x0 },
  456 + { 0x2121d0, 0x0 },
  457 + { 0x130d0, 0x0 },
  458 + { 0x1130d0, 0x0 },
  459 + { 0x2130d0, 0x0 },
  460 + { 0x131d0, 0x0 },
  461 + { 0x1131d0, 0x0 },
  462 + { 0x2131d0, 0x0 },
  463 + { 0x100d1, 0x0 },
  464 + { 0x1100d1, 0x0 },
  465 + { 0x2100d1, 0x0 },
  466 + { 0x101d1, 0x0 },
  467 + { 0x1101d1, 0x0 },
  468 + { 0x2101d1, 0x0 },
  469 + { 0x110d1, 0x0 },
  470 + { 0x1110d1, 0x0 },
  471 + { 0x2110d1, 0x0 },
  472 + { 0x111d1, 0x0 },
  473 + { 0x1111d1, 0x0 },
  474 + { 0x2111d1, 0x0 },
  475 + { 0x120d1, 0x0 },
  476 + { 0x1120d1, 0x0 },
  477 + { 0x2120d1, 0x0 },
  478 + { 0x121d1, 0x0 },
  479 + { 0x1121d1, 0x0 },
  480 + { 0x2121d1, 0x0 },
  481 + { 0x130d1, 0x0 },
  482 + { 0x1130d1, 0x0 },
  483 + { 0x2130d1, 0x0 },
  484 + { 0x131d1, 0x0 },
  485 + { 0x1131d1, 0x0 },
  486 + { 0x2131d1, 0x0 },
  487 + { 0x10068, 0x0 },
  488 + { 0x10168, 0x0 },
  489 + { 0x10268, 0x0 },
  490 + { 0x10368, 0x0 },
  491 + { 0x10468, 0x0 },
  492 + { 0x10568, 0x0 },
  493 + { 0x10668, 0x0 },
  494 + { 0x10768, 0x0 },
  495 + { 0x10868, 0x0 },
  496 + { 0x11068, 0x0 },
  497 + { 0x11168, 0x0 },
  498 + { 0x11268, 0x0 },
  499 + { 0x11368, 0x0 },
  500 + { 0x11468, 0x0 },
  501 + { 0x11568, 0x0 },
  502 + { 0x11668, 0x0 },
  503 + { 0x11768, 0x0 },
  504 + { 0x11868, 0x0 },
  505 + { 0x12068, 0x0 },
  506 + { 0x12168, 0x0 },
  507 + { 0x12268, 0x0 },
  508 + { 0x12368, 0x0 },
  509 + { 0x12468, 0x0 },
  510 + { 0x12568, 0x0 },
  511 + { 0x12668, 0x0 },
  512 + { 0x12768, 0x0 },
  513 + { 0x12868, 0x0 },
  514 + { 0x13068, 0x0 },
  515 + { 0x13168, 0x0 },
  516 + { 0x13268, 0x0 },
  517 + { 0x13368, 0x0 },
  518 + { 0x13468, 0x0 },
  519 + { 0x13568, 0x0 },
  520 + { 0x13668, 0x0 },
  521 + { 0x13768, 0x0 },
  522 + { 0x13868, 0x0 },
  523 + { 0x10069, 0x0 },
  524 + { 0x10169, 0x0 },
  525 + { 0x10269, 0x0 },
  526 + { 0x10369, 0x0 },
  527 + { 0x10469, 0x0 },
  528 + { 0x10569, 0x0 },
  529 + { 0x10669, 0x0 },
  530 + { 0x10769, 0x0 },
  531 + { 0x10869, 0x0 },
  532 + { 0x11069, 0x0 },
  533 + { 0x11169, 0x0 },
  534 + { 0x11269, 0x0 },
  535 + { 0x11369, 0x0 },
  536 + { 0x11469, 0x0 },
  537 + { 0x11569, 0x0 },
  538 + { 0x11669, 0x0 },
  539 + { 0x11769, 0x0 },
  540 + { 0x11869, 0x0 },
  541 + { 0x12069, 0x0 },
  542 + { 0x12169, 0x0 },
  543 + { 0x12269, 0x0 },
  544 + { 0x12369, 0x0 },
  545 + { 0x12469, 0x0 },
  546 + { 0x12569, 0x0 },
  547 + { 0x12669, 0x0 },
  548 + { 0x12769, 0x0 },
  549 + { 0x12869, 0x0 },
  550 + { 0x13069, 0x0 },
  551 + { 0x13169, 0x0 },
  552 + { 0x13269, 0x0 },
  553 + { 0x13369, 0x0 },
  554 + { 0x13469, 0x0 },
  555 + { 0x13569, 0x0 },
  556 + { 0x13669, 0x0 },
  557 + { 0x13769, 0x0 },
  558 + { 0x13869, 0x0 },
  559 + { 0x1008c, 0x0 },
  560 + { 0x11008c, 0x0 },
  561 + { 0x21008c, 0x0 },
  562 + { 0x1018c, 0x0 },
  563 + { 0x11018c, 0x0 },
  564 + { 0x21018c, 0x0 },
  565 + { 0x1108c, 0x0 },
  566 + { 0x11108c, 0x0 },
  567 + { 0x21108c, 0x0 },
  568 + { 0x1118c, 0x0 },
  569 + { 0x11118c, 0x0 },
  570 + { 0x21118c, 0x0 },
  571 + { 0x1208c, 0x0 },
  572 + { 0x11208c, 0x0 },
  573 + { 0x21208c, 0x0 },
  574 + { 0x1218c, 0x0 },
  575 + { 0x11218c, 0x0 },
  576 + { 0x21218c, 0x0 },
  577 + { 0x1308c, 0x0 },
  578 + { 0x11308c, 0x0 },
  579 + { 0x21308c, 0x0 },
  580 + { 0x1318c, 0x0 },
  581 + { 0x11318c, 0x0 },
  582 + { 0x21318c, 0x0 },
  583 + { 0x1008d, 0x0 },
  584 + { 0x11008d, 0x0 },
  585 + { 0x21008d, 0x0 },
  586 + { 0x1018d, 0x0 },
  587 + { 0x11018d, 0x0 },
  588 + { 0x21018d, 0x0 },
  589 + { 0x1108d, 0x0 },
  590 + { 0x11108d, 0x0 },
  591 + { 0x21108d, 0x0 },
  592 + { 0x1118d, 0x0 },
  593 + { 0x11118d, 0x0 },
  594 + { 0x21118d, 0x0 },
  595 + { 0x1208d, 0x0 },
  596 + { 0x11208d, 0x0 },
  597 + { 0x21208d, 0x0 },
  598 + { 0x1218d, 0x0 },
  599 + { 0x11218d, 0x0 },
  600 + { 0x21218d, 0x0 },
  601 + { 0x1308d, 0x0 },
  602 + { 0x11308d, 0x0 },
  603 + { 0x21308d, 0x0 },
  604 + { 0x1318d, 0x0 },
  605 + { 0x11318d, 0x0 },
  606 + { 0x21318d, 0x0 },
  607 + { 0x100c0, 0x0 },
  608 + { 0x1100c0, 0x0 },
  609 + { 0x2100c0, 0x0 },
  610 + { 0x101c0, 0x0 },
  611 + { 0x1101c0, 0x0 },
  612 + { 0x2101c0, 0x0 },
  613 + { 0x102c0, 0x0 },
  614 + { 0x1102c0, 0x0 },
  615 + { 0x2102c0, 0x0 },
  616 + { 0x103c0, 0x0 },
  617 + { 0x1103c0, 0x0 },
  618 + { 0x2103c0, 0x0 },
  619 + { 0x104c0, 0x0 },
  620 + { 0x1104c0, 0x0 },
  621 + { 0x2104c0, 0x0 },
  622 + { 0x105c0, 0x0 },
  623 + { 0x1105c0, 0x0 },
  624 + { 0x2105c0, 0x0 },
  625 + { 0x106c0, 0x0 },
  626 + { 0x1106c0, 0x0 },
  627 + { 0x2106c0, 0x0 },
  628 + { 0x107c0, 0x0 },
  629 + { 0x1107c0, 0x0 },
  630 + { 0x2107c0, 0x0 },
  631 + { 0x108c0, 0x0 },
  632 + { 0x1108c0, 0x0 },
  633 + { 0x2108c0, 0x0 },
  634 + { 0x110c0, 0x0 },
  635 + { 0x1110c0, 0x0 },
  636 + { 0x2110c0, 0x0 },
  637 + { 0x111c0, 0x0 },
  638 + { 0x1111c0, 0x0 },
  639 + { 0x2111c0, 0x0 },
  640 + { 0x112c0, 0x0 },
  641 + { 0x1112c0, 0x0 },
  642 + { 0x2112c0, 0x0 },
  643 + { 0x113c0, 0x0 },
  644 + { 0x1113c0, 0x0 },
  645 + { 0x2113c0, 0x0 },
  646 + { 0x114c0, 0x0 },
  647 + { 0x1114c0, 0x0 },
  648 + { 0x2114c0, 0x0 },
  649 + { 0x115c0, 0x0 },
  650 + { 0x1115c0, 0x0 },
  651 + { 0x2115c0, 0x0 },
  652 + { 0x116c0, 0x0 },
  653 + { 0x1116c0, 0x0 },
  654 + { 0x2116c0, 0x0 },
  655 + { 0x117c0, 0x0 },
  656 + { 0x1117c0, 0x0 },
  657 + { 0x2117c0, 0x0 },
  658 + { 0x118c0, 0x0 },
  659 + { 0x1118c0, 0x0 },
  660 + { 0x2118c0, 0x0 },
  661 + { 0x120c0, 0x0 },
  662 + { 0x1120c0, 0x0 },
  663 + { 0x2120c0, 0x0 },
  664 + { 0x121c0, 0x0 },
  665 + { 0x1121c0, 0x0 },
  666 + { 0x2121c0, 0x0 },
  667 + { 0x122c0, 0x0 },
  668 + { 0x1122c0, 0x0 },
  669 + { 0x2122c0, 0x0 },
  670 + { 0x123c0, 0x0 },
  671 + { 0x1123c0, 0x0 },
  672 + { 0x2123c0, 0x0 },
  673 + { 0x124c0, 0x0 },
  674 + { 0x1124c0, 0x0 },
  675 + { 0x2124c0, 0x0 },
  676 + { 0x125c0, 0x0 },
  677 + { 0x1125c0, 0x0 },
  678 + { 0x2125c0, 0x0 },
  679 + { 0x126c0, 0x0 },
  680 + { 0x1126c0, 0x0 },
  681 + { 0x2126c0, 0x0 },
  682 + { 0x127c0, 0x0 },
  683 + { 0x1127c0, 0x0 },
  684 + { 0x2127c0, 0x0 },
  685 + { 0x128c0, 0x0 },
  686 + { 0x1128c0, 0x0 },
  687 + { 0x2128c0, 0x0 },
  688 + { 0x130c0, 0x0 },
  689 + { 0x1130c0, 0x0 },
  690 + { 0x2130c0, 0x0 },
  691 + { 0x131c0, 0x0 },
  692 + { 0x1131c0, 0x0 },
  693 + { 0x2131c0, 0x0 },
  694 + { 0x132c0, 0x0 },
  695 + { 0x1132c0, 0x0 },
  696 + { 0x2132c0, 0x0 },
  697 + { 0x133c0, 0x0 },
  698 + { 0x1133c0, 0x0 },
  699 + { 0x2133c0, 0x0 },
  700 + { 0x134c0, 0x0 },
  701 + { 0x1134c0, 0x0 },
  702 + { 0x2134c0, 0x0 },
  703 + { 0x135c0, 0x0 },
  704 + { 0x1135c0, 0x0 },
  705 + { 0x2135c0, 0x0 },
  706 + { 0x136c0, 0x0 },
  707 + { 0x1136c0, 0x0 },
  708 + { 0x2136c0, 0x0 },
  709 + { 0x137c0, 0x0 },
  710 + { 0x1137c0, 0x0 },
  711 + { 0x2137c0, 0x0 },
  712 + { 0x138c0, 0x0 },
  713 + { 0x1138c0, 0x0 },
  714 + { 0x2138c0, 0x0 },
  715 + { 0x100c1, 0x0 },
  716 + { 0x1100c1, 0x0 },
  717 + { 0x2100c1, 0x0 },
  718 + { 0x101c1, 0x0 },
  719 + { 0x1101c1, 0x0 },
  720 + { 0x2101c1, 0x0 },
  721 + { 0x102c1, 0x0 },
  722 + { 0x1102c1, 0x0 },
  723 + { 0x2102c1, 0x0 },
  724 + { 0x103c1, 0x0 },
  725 + { 0x1103c1, 0x0 },
  726 + { 0x2103c1, 0x0 },
  727 + { 0x104c1, 0x0 },
  728 + { 0x1104c1, 0x0 },
  729 + { 0x2104c1, 0x0 },
  730 + { 0x105c1, 0x0 },
  731 + { 0x1105c1, 0x0 },
  732 + { 0x2105c1, 0x0 },
  733 + { 0x106c1, 0x0 },
  734 + { 0x1106c1, 0x0 },
  735 + { 0x2106c1, 0x0 },
  736 + { 0x107c1, 0x0 },
  737 + { 0x1107c1, 0x0 },
  738 + { 0x2107c1, 0x0 },
  739 + { 0x108c1, 0x0 },
  740 + { 0x1108c1, 0x0 },
  741 + { 0x2108c1, 0x0 },
  742 + { 0x110c1, 0x0 },
  743 + { 0x1110c1, 0x0 },
  744 + { 0x2110c1, 0x0 },
  745 + { 0x111c1, 0x0 },
  746 + { 0x1111c1, 0x0 },
  747 + { 0x2111c1, 0x0 },
  748 + { 0x112c1, 0x0 },
  749 + { 0x1112c1, 0x0 },
  750 + { 0x2112c1, 0x0 },
  751 + { 0x113c1, 0x0 },
  752 + { 0x1113c1, 0x0 },
  753 + { 0x2113c1, 0x0 },
  754 + { 0x114c1, 0x0 },
  755 + { 0x1114c1, 0x0 },
  756 + { 0x2114c1, 0x0 },
  757 + { 0x115c1, 0x0 },
  758 + { 0x1115c1, 0x0 },
  759 + { 0x2115c1, 0x0 },
  760 + { 0x116c1, 0x0 },
  761 + { 0x1116c1, 0x0 },
  762 + { 0x2116c1, 0x0 },
  763 + { 0x117c1, 0x0 },
  764 + { 0x1117c1, 0x0 },
  765 + { 0x2117c1, 0x0 },
  766 + { 0x118c1, 0x0 },
  767 + { 0x1118c1, 0x0 },
  768 + { 0x2118c1, 0x0 },
  769 + { 0x120c1, 0x0 },
  770 + { 0x1120c1, 0x0 },
  771 + { 0x2120c1, 0x0 },
  772 + { 0x121c1, 0x0 },
  773 + { 0x1121c1, 0x0 },
  774 + { 0x2121c1, 0x0 },
  775 + { 0x122c1, 0x0 },
  776 + { 0x1122c1, 0x0 },
  777 + { 0x2122c1, 0x0 },
  778 + { 0x123c1, 0x0 },
  779 + { 0x1123c1, 0x0 },
  780 + { 0x2123c1, 0x0 },
  781 + { 0x124c1, 0x0 },
  782 + { 0x1124c1, 0x0 },
  783 + { 0x2124c1, 0x0 },
  784 + { 0x125c1, 0x0 },
  785 + { 0x1125c1, 0x0 },
  786 + { 0x2125c1, 0x0 },
  787 + { 0x126c1, 0x0 },
  788 + { 0x1126c1, 0x0 },
  789 + { 0x2126c1, 0x0 },
  790 + { 0x127c1, 0x0 },
  791 + { 0x1127c1, 0x0 },
  792 + { 0x2127c1, 0x0 },
  793 + { 0x128c1, 0x0 },
  794 + { 0x1128c1, 0x0 },
  795 + { 0x2128c1, 0x0 },
  796 + { 0x130c1, 0x0 },
  797 + { 0x1130c1, 0x0 },
  798 + { 0x2130c1, 0x0 },
  799 + { 0x131c1, 0x0 },
  800 + { 0x1131c1, 0x0 },
  801 + { 0x2131c1, 0x0 },
  802 + { 0x132c1, 0x0 },
  803 + { 0x1132c1, 0x0 },
  804 + { 0x2132c1, 0x0 },
  805 + { 0x133c1, 0x0 },
  806 + { 0x1133c1, 0x0 },
  807 + { 0x2133c1, 0x0 },
  808 + { 0x134c1, 0x0 },
  809 + { 0x1134c1, 0x0 },
  810 + { 0x2134c1, 0x0 },
  811 + { 0x135c1, 0x0 },
  812 + { 0x1135c1, 0x0 },
  813 + { 0x2135c1, 0x0 },
  814 + { 0x136c1, 0x0 },
  815 + { 0x1136c1, 0x0 },
  816 + { 0x2136c1, 0x0 },
  817 + { 0x137c1, 0x0 },
  818 + { 0x1137c1, 0x0 },
  819 + { 0x2137c1, 0x0 },
  820 + { 0x138c1, 0x0 },
  821 + { 0x1138c1, 0x0 },
  822 + { 0x2138c1, 0x0 },
  823 + { 0x10020, 0x0 },
  824 + { 0x110020, 0x0 },
  825 + { 0x210020, 0x0 },
  826 + { 0x11020, 0x0 },
  827 + { 0x111020, 0x0 },
  828 + { 0x211020, 0x0 },
  829 + { 0x12020, 0x0 },
  830 + { 0x112020, 0x0 },
  831 + { 0x212020, 0x0 },
  832 + { 0x13020, 0x0 },
  833 + { 0x113020, 0x0 },
  834 + { 0x213020, 0x0 },
  835 + { 0x20072, 0x0 },
  836 + { 0x20073, 0x0 },
  837 + { 0x20074, 0x0 },
  838 + { 0x100aa, 0x0 },
  839 + { 0x110aa, 0x0 },
  840 + { 0x120aa, 0x0 },
  841 + { 0x130aa, 0x0 },
  842 + { 0x20010, 0x0 },
  843 + { 0x120010, 0x0 },
  844 + { 0x220010, 0x0 },
  845 + { 0x20011, 0x0 },
  846 + { 0x120011, 0x0 },
  847 + { 0x220011, 0x0 },
  848 + { 0x100ae, 0x0 },
  849 + { 0x1100ae, 0x0 },
  850 + { 0x2100ae, 0x0 },
  851 + { 0x100af, 0x0 },
  852 + { 0x1100af, 0x0 },
  853 + { 0x2100af, 0x0 },
  854 + { 0x110ae, 0x0 },
  855 + { 0x1110ae, 0x0 },
  856 + { 0x2110ae, 0x0 },
  857 + { 0x110af, 0x0 },
  858 + { 0x1110af, 0x0 },
  859 + { 0x2110af, 0x0 },
  860 + { 0x120ae, 0x0 },
  861 + { 0x1120ae, 0x0 },
  862 + { 0x2120ae, 0x0 },
  863 + { 0x120af, 0x0 },
  864 + { 0x1120af, 0x0 },
  865 + { 0x2120af, 0x0 },
  866 + { 0x130ae, 0x0 },
  867 + { 0x1130ae, 0x0 },
  868 + { 0x2130ae, 0x0 },
  869 + { 0x130af, 0x0 },
  870 + { 0x1130af, 0x0 },
  871 + { 0x2130af, 0x0 },
  872 + { 0x20020, 0x0 },
  873 + { 0x120020, 0x0 },
  874 + { 0x220020, 0x0 },
  875 + { 0x100a0, 0x0 },
  876 + { 0x100a1, 0x0 },
  877 + { 0x100a2, 0x0 },
  878 + { 0x100a3, 0x0 },
  879 + { 0x100a4, 0x0 },
  880 + { 0x100a5, 0x0 },
  881 + { 0x100a6, 0x0 },
  882 + { 0x100a7, 0x0 },
  883 + { 0x110a0, 0x0 },
  884 + { 0x110a1, 0x0 },
  885 + { 0x110a2, 0x0 },
  886 + { 0x110a3, 0x0 },
  887 + { 0x110a4, 0x0 },
  888 + { 0x110a5, 0x0 },
  889 + { 0x110a6, 0x0 },
  890 + { 0x110a7, 0x0 },
  891 + { 0x120a0, 0x0 },
  892 + { 0x120a1, 0x0 },
  893 + { 0x120a2, 0x0 },
  894 + { 0x120a3, 0x0 },
  895 + { 0x120a4, 0x0 },
  896 + { 0x120a5, 0x0 },
  897 + { 0x120a6, 0x0 },
  898 + { 0x120a7, 0x0 },
  899 + { 0x130a0, 0x0 },
  900 + { 0x130a1, 0x0 },
  901 + { 0x130a2, 0x0 },
  902 + { 0x130a3, 0x0 },
  903 + { 0x130a4, 0x0 },
  904 + { 0x130a5, 0x0 },
  905 + { 0x130a6, 0x0 },
  906 + { 0x130a7, 0x0 },
  907 + { 0x2007c, 0x0 },
  908 + { 0x12007c, 0x0 },
  909 + { 0x22007c, 0x0 },
  910 + { 0x2007d, 0x0 },
  911 + { 0x12007d, 0x0 },
  912 + { 0x22007d, 0x0 },
  913 + { 0x400fd, 0x0 },
  914 + { 0x400c0, 0x0 },
  915 + { 0x90201, 0x0 },
  916 + { 0x190201, 0x0 },
  917 + { 0x290201, 0x0 },
  918 + { 0x90202, 0x0 },
  919 + { 0x190202, 0x0 },
  920 + { 0x290202, 0x0 },
  921 + { 0x90203, 0x0 },
  922 + { 0x190203, 0x0 },
  923 + { 0x290203, 0x0 },
  924 + { 0x90204, 0x0 },
  925 + { 0x190204, 0x0 },
  926 + { 0x290204, 0x0 },
  927 + { 0x90205, 0x0 },
  928 + { 0x190205, 0x0 },
  929 + { 0x290205, 0x0 },
  930 + { 0x90206, 0x0 },
  931 + { 0x190206, 0x0 },
  932 + { 0x290206, 0x0 },
  933 + { 0x90207, 0x0 },
  934 + { 0x190207, 0x0 },
  935 + { 0x290207, 0x0 },
  936 + { 0x90208, 0x0 },
  937 + { 0x190208, 0x0 },
  938 + { 0x290208, 0x0 },
  939 + { 0x10062, 0x0 },
  940 + { 0x10162, 0x0 },
  941 + { 0x10262, 0x0 },
  942 + { 0x10362, 0x0 },
  943 + { 0x10462, 0x0 },
  944 + { 0x10562, 0x0 },
  945 + { 0x10662, 0x0 },
  946 + { 0x10762, 0x0 },
  947 + { 0x10862, 0x0 },
  948 + { 0x11062, 0x0 },
  949 + { 0x11162, 0x0 },
  950 + { 0x11262, 0x0 },
  951 + { 0x11362, 0x0 },
  952 + { 0x11462, 0x0 },
  953 + { 0x11562, 0x0 },
  954 + { 0x11662, 0x0 },
  955 + { 0x11762, 0x0 },
  956 + { 0x11862, 0x0 },
  957 + { 0x12062, 0x0 },
  958 + { 0x12162, 0x0 },
  959 + { 0x12262, 0x0 },
  960 + { 0x12362, 0x0 },
  961 + { 0x12462, 0x0 },
  962 + { 0x12562, 0x0 },
  963 + { 0x12662, 0x0 },
  964 + { 0x12762, 0x0 },
  965 + { 0x12862, 0x0 },
  966 + { 0x13062, 0x0 },
  967 + { 0x13162, 0x0 },
  968 + { 0x13262, 0x0 },
  969 + { 0x13362, 0x0 },
  970 + { 0x13462, 0x0 },
  971 + { 0x13562, 0x0 },
  972 + { 0x13662, 0x0 },
  973 + { 0x13762, 0x0 },
  974 + { 0x13862, 0x0 },
  975 + { 0x20077, 0x0 },
  976 + { 0x10001, 0x0 },
  977 + { 0x11001, 0x0 },
  978 + { 0x12001, 0x0 },
  979 + { 0x13001, 0x0 },
  980 + { 0x10040, 0x0 },
  981 + { 0x10140, 0x0 },
  982 + { 0x10240, 0x0 },
  983 + { 0x10340, 0x0 },
  984 + { 0x10440, 0x0 },
  985 + { 0x10540, 0x0 },
  986 + { 0x10640, 0x0 },
  987 + { 0x10740, 0x0 },
  988 + { 0x10840, 0x0 },
  989 + { 0x10030, 0x0 },
  990 + { 0x10130, 0x0 },
  991 + { 0x10230, 0x0 },
  992 + { 0x10330, 0x0 },
  993 + { 0x10430, 0x0 },
  994 + { 0x10530, 0x0 },
  995 + { 0x10630, 0x0 },
  996 + { 0x10730, 0x0 },
  997 + { 0x10830, 0x0 },
  998 + { 0x11040, 0x0 },
  999 + { 0x11140, 0x0 },
  1000 + { 0x11240, 0x0 },
  1001 + { 0x11340, 0x0 },
  1002 + { 0x11440, 0x0 },
  1003 + { 0x11540, 0x0 },
  1004 + { 0x11640, 0x0 },
  1005 + { 0x11740, 0x0 },
  1006 + { 0x11840, 0x0 },
  1007 + { 0x11030, 0x0 },
  1008 + { 0x11130, 0x0 },
  1009 + { 0x11230, 0x0 },
  1010 + { 0x11330, 0x0 },
  1011 + { 0x11430, 0x0 },
  1012 + { 0x11530, 0x0 },
  1013 + { 0x11630, 0x0 },
  1014 + { 0x11730, 0x0 },
  1015 + { 0x11830, 0x0 },
  1016 + { 0x12040, 0x0 },
  1017 + { 0x12140, 0x0 },
  1018 + { 0x12240, 0x0 },
  1019 + { 0x12340, 0x0 },
  1020 + { 0x12440, 0x0 },
  1021 + { 0x12540, 0x0 },
  1022 + { 0x12640, 0x0 },
  1023 + { 0x12740, 0x0 },
  1024 + { 0x12840, 0x0 },
  1025 + { 0x12030, 0x0 },
  1026 + { 0x12130, 0x0 },
  1027 + { 0x12230, 0x0 },
  1028 + { 0x12330, 0x0 },
  1029 + { 0x12430, 0x0 },
  1030 + { 0x12530, 0x0 },
  1031 + { 0x12630, 0x0 },
  1032 + { 0x12730, 0x0 },
  1033 + { 0x12830, 0x0 },
  1034 + { 0x13040, 0x0 },
  1035 + { 0x13140, 0x0 },
  1036 + { 0x13240, 0x0 },
  1037 + { 0x13340, 0x0 },
  1038 + { 0x13440, 0x0 },
  1039 + { 0x13540, 0x0 },
  1040 + { 0x13640, 0x0 },
  1041 + { 0x13740, 0x0 },
  1042 + { 0x13840, 0x0 },
  1043 + { 0x13030, 0x0 },
  1044 + { 0x13130, 0x0 },
  1045 + { 0x13230, 0x0 },
  1046 + { 0x13330, 0x0 },
  1047 + { 0x13430, 0x0 },
  1048 + { 0x13530, 0x0 },
  1049 + { 0x13630, 0x0 },
  1050 + { 0x13730, 0x0 },
  1051 + { 0x13830, 0x0 },
  1052 +};
  1053 +/* P0 message block paremeter for training firmware */
  1054 +struct dram_cfg_param ddr_fsp0_cfg[] = {
  1055 + { 0xd0000, 0x0 },
  1056 + { 0x54003, 0xbb8 },
  1057 + { 0x54004, 0x2 },
  1058 + { 0x54005, 0x2228 },
  1059 + { 0x54006, 0x11 },
  1060 + { 0x54008, 0x131f },
  1061 + { 0x54009, 0xc8 },
  1062 + { 0x5400b, 0x2 },
  1063 + { 0x5400d, 0x100 },
  1064 + { 0x54012, 0x110 },
  1065 + { 0x54019, 0x2dd4 },
  1066 + { 0x5401a, 0x31 },
  1067 + { 0x5401b, 0x4d66 },
  1068 + { 0x5401c, 0x4d00 },
  1069 + { 0x5401e, 0x16 },
  1070 + { 0x5401f, 0x2dd4 },
  1071 + { 0x54020, 0x31 },
  1072 + { 0x54021, 0x4d66 },
  1073 + { 0x54022, 0x4d00 },
  1074 + { 0x54024, 0x16 },
  1075 + { 0x5402b, 0x1000 },
  1076 + { 0x5402c, 0x1 },
  1077 + { 0x54032, 0xd400 },
  1078 + { 0x54033, 0x312d },
  1079 + { 0x54034, 0x6600 },
  1080 + { 0x54035, 0x4d },
  1081 + { 0x54036, 0x4d },
  1082 + { 0x54037, 0x1600 },
  1083 + { 0x54038, 0xd400 },
  1084 + { 0x54039, 0x312d },
  1085 + { 0x5403a, 0x6600 },
  1086 + { 0x5403b, 0x4d },
  1087 + { 0x5403c, 0x4d },
  1088 + { 0x5403d, 0x1600 },
  1089 + { 0xd0000, 0x1 },
  1090 +};
  1091 +
  1092 +
  1093 +/* P1 message block paremeter for training firmware */
  1094 +struct dram_cfg_param ddr_fsp1_cfg[] = {
  1095 + { 0xd0000, 0x0 },
  1096 + { 0x54002, 0x101 },
  1097 + { 0x54003, 0x190 },
  1098 + { 0x54004, 0x2 },
  1099 + { 0x54005, 0x2228 },
  1100 + { 0x54006, 0x11 },
  1101 + { 0x54008, 0x121f },
  1102 + { 0x54009, 0xc8 },
  1103 + { 0x5400b, 0x2 },
  1104 + { 0x5400d, 0x100 },
  1105 + { 0x54012, 0x110 },
  1106 + { 0x54019, 0x84 },
  1107 + { 0x5401a, 0x31 },
  1108 + { 0x5401b, 0x4d66 },
  1109 + { 0x5401c, 0x4d00 },
  1110 + { 0x5401e, 0x16 },
  1111 + { 0x5401f, 0x84 },
  1112 + { 0x54020, 0x31 },
  1113 + { 0x54021, 0x4d66 },
  1114 + { 0x54022, 0x4d00 },
  1115 + { 0x54024, 0x16 },
  1116 + { 0x5402b, 0x1000 },
  1117 + { 0x5402c, 0x1 },
  1118 + { 0x54032, 0x8400 },
  1119 + { 0x54033, 0x3100 },
  1120 + { 0x54034, 0x6600 },
  1121 + { 0x54035, 0x4d },
  1122 + { 0x54036, 0x4d },
  1123 + { 0x54037, 0x1600 },
  1124 + { 0x54038, 0x8400 },
  1125 + { 0x54039, 0x3100 },
  1126 + { 0x5403a, 0x6600 },
  1127 + { 0x5403b, 0x4d },
  1128 + { 0x5403c, 0x4d },
  1129 + { 0x5403d, 0x1600 },
  1130 + { 0xd0000, 0x1 },
  1131 +};
  1132 +
  1133 +
  1134 +/* P2 message block paremeter for training firmware */
  1135 +struct dram_cfg_param ddr_fsp2_cfg[] = {
  1136 + { 0xd0000, 0x0 },
  1137 + { 0x54002, 0x102 },
  1138 + { 0x54003, 0x64 },
  1139 + { 0x54004, 0x2 },
  1140 + { 0x54005, 0x2228 },
  1141 + { 0x54006, 0x11 },
  1142 + { 0x54008, 0x121f },
  1143 + { 0x54009, 0xc8 },
  1144 + { 0x5400b, 0x2 },
  1145 + { 0x5400d, 0x100 },
  1146 + { 0x54012, 0x110 },
  1147 + { 0x54019, 0x84 },
  1148 + { 0x5401a, 0x31 },
  1149 + { 0x5401b, 0x4d66 },
  1150 + { 0x5401c, 0x4d00 },
  1151 + { 0x5401e, 0x16 },
  1152 + { 0x5401f, 0x84 },
  1153 + { 0x54020, 0x31 },
  1154 + { 0x54021, 0x4d66 },
  1155 + { 0x54022, 0x4d00 },
  1156 + { 0x54024, 0x16 },
  1157 + { 0x5402b, 0x1000 },
  1158 + { 0x5402c, 0x1 },
  1159 + { 0x54032, 0x8400 },
  1160 + { 0x54033, 0x3100 },
  1161 + { 0x54034, 0x6600 },
  1162 + { 0x54035, 0x4d },
  1163 + { 0x54036, 0x4d },
  1164 + { 0x54037, 0x1600 },
  1165 + { 0x54038, 0x8400 },
  1166 + { 0x54039, 0x3100 },
  1167 + { 0x5403a, 0x6600 },
  1168 + { 0x5403b, 0x4d },
  1169 + { 0x5403c, 0x4d },
  1170 + { 0x5403d, 0x1600 },
  1171 + { 0xd0000, 0x1 },
  1172 +};
  1173 +
  1174 +
  1175 +/* P0 2D message block paremeter for training firmware */
  1176 +struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
  1177 + { 0xd0000, 0x0 },
  1178 + { 0x54003, 0xbb8 },
  1179 + { 0x54004, 0x2 },
  1180 + { 0x54005, 0x2228 },
  1181 + { 0x54006, 0x11 },
  1182 + { 0x54008, 0x61 },
  1183 + { 0x54009, 0xc8 },
  1184 + { 0x5400b, 0x2 },
  1185 + { 0x5400f, 0x100 },
  1186 + { 0x54010, 0x1f7f },
  1187 + { 0x54012, 0x110 },
  1188 + { 0x54019, 0x2dd4 },
  1189 + { 0x5401a, 0x31 },
  1190 + { 0x5401b, 0x4d66 },
  1191 + { 0x5401c, 0x4d00 },
  1192 + { 0x5401e, 0x16 },
  1193 + { 0x5401f, 0x2dd4 },
  1194 + { 0x54020, 0x31 },
  1195 + { 0x54021, 0x4d66 },
  1196 + { 0x54022, 0x4d00 },
  1197 + { 0x54024, 0x16 },
  1198 + { 0x5402b, 0x1000 },
  1199 + { 0x5402c, 0x1 },
  1200 + { 0x54032, 0xd400 },
  1201 + { 0x54033, 0x312d },
  1202 + { 0x54034, 0x6600 },
  1203 + { 0x54035, 0x4d },
  1204 + { 0x54036, 0x4d },
  1205 + { 0x54037, 0x1600 },
  1206 + { 0x54038, 0xd400 },
  1207 + { 0x54039, 0x312d },
  1208 + { 0x5403a, 0x6600 },
  1209 + { 0x5403b, 0x4d },
  1210 + { 0x5403c, 0x4d },
  1211 + { 0x5403d, 0x1600 },
  1212 + { 0xd0000, 0x1 },
  1213 +};
  1214 +
  1215 +/* DRAM PHY init engine image */
  1216 +struct dram_cfg_param ddr_phy_pie[] = {
  1217 + { 0xd0000, 0x0 },
  1218 + { 0x90000, 0x10 },
  1219 + { 0x90001, 0x400 },
  1220 + { 0x90002, 0x10e },
  1221 + { 0x90003, 0x0 },
  1222 + { 0x90004, 0x0 },
  1223 + { 0x90005, 0x8 },
  1224 + { 0x90029, 0xb },
  1225 + { 0x9002a, 0x480 },
  1226 + { 0x9002b, 0x109 },
  1227 + { 0x9002c, 0x8 },
  1228 + { 0x9002d, 0x448 },
  1229 + { 0x9002e, 0x139 },
  1230 + { 0x9002f, 0x8 },
  1231 + { 0x90030, 0x478 },
  1232 + { 0x90031, 0x109 },
  1233 + { 0x90032, 0x0 },
  1234 + { 0x90033, 0xe8 },
  1235 + { 0x90034, 0x109 },
  1236 + { 0x90035, 0x2 },
  1237 + { 0x90036, 0x10 },
  1238 + { 0x90037, 0x139 },
  1239 + { 0x90038, 0xf },
  1240 + { 0x90039, 0x7c0 },
  1241 + { 0x9003a, 0x139 },
  1242 + { 0x9003b, 0x44 },
  1243 + { 0x9003c, 0x630 },
  1244 + { 0x9003d, 0x159 },
  1245 + { 0x9003e, 0x14f },
  1246 + { 0x9003f, 0x630 },
  1247 + { 0x90040, 0x159 },
  1248 + { 0x90041, 0x47 },
  1249 + { 0x90042, 0x630 },
  1250 + { 0x90043, 0x149 },
  1251 + { 0x90044, 0x4f },
  1252 + { 0x90045, 0x630 },
  1253 + { 0x90046, 0x179 },
  1254 + { 0x90047, 0x8 },
  1255 + { 0x90048, 0xe0 },
  1256 + { 0x90049, 0x109 },
  1257 + { 0x9004a, 0x0 },
  1258 + { 0x9004b, 0x7c8 },
  1259 + { 0x9004c, 0x109 },
  1260 + { 0x9004d, 0x0 },
  1261 + { 0x9004e, 0x1 },
  1262 + { 0x9004f, 0x8 },
  1263 + { 0x90050, 0x0 },
  1264 + { 0x90051, 0x45a },
  1265 + { 0x90052, 0x9 },
  1266 + { 0x90053, 0x0 },
  1267 + { 0x90054, 0x448 },
  1268 + { 0x90055, 0x109 },
  1269 + { 0x90056, 0x40 },
  1270 + { 0x90057, 0x630 },
  1271 + { 0x90058, 0x179 },
  1272 + { 0x90059, 0x1 },
  1273 + { 0x9005a, 0x618 },
  1274 + { 0x9005b, 0x109 },
  1275 + { 0x9005c, 0x40c0 },
  1276 + { 0x9005d, 0x630 },
  1277 + { 0x9005e, 0x149 },
  1278 + { 0x9005f, 0x8 },
  1279 + { 0x90060, 0x4 },
  1280 + { 0x90061, 0x48 },
  1281 + { 0x90062, 0x4040 },
  1282 + { 0x90063, 0x630 },
  1283 + { 0x90064, 0x149 },
  1284 + { 0x90065, 0x0 },
  1285 + { 0x90066, 0x4 },
  1286 + { 0x90067, 0x48 },
  1287 + { 0x90068, 0x40 },
  1288 + { 0x90069, 0x630 },
  1289 + { 0x9006a, 0x149 },
  1290 + { 0x9006b, 0x10 },
  1291 + { 0x9006c, 0x4 },
  1292 + { 0x9006d, 0x18 },
  1293 + { 0x9006e, 0x0 },
  1294 + { 0x9006f, 0x4 },
  1295 + { 0x90070, 0x78 },
  1296 + { 0x90071, 0x549 },
  1297 + { 0x90072, 0x630 },
  1298 + { 0x90073, 0x159 },
  1299 + { 0x90074, 0xd49 },
  1300 + { 0x90075, 0x630 },
  1301 + { 0x90076, 0x159 },
  1302 + { 0x90077, 0x94a },
  1303 + { 0x90078, 0x630 },
  1304 + { 0x90079, 0x159 },
  1305 + { 0x9007a, 0x441 },
  1306 + { 0x9007b, 0x630 },
  1307 + { 0x9007c, 0x149 },
  1308 + { 0x9007d, 0x42 },
  1309 + { 0x9007e, 0x630 },
  1310 + { 0x9007f, 0x149 },
  1311 + { 0x90080, 0x1 },
  1312 + { 0x90081, 0x630 },
  1313 + { 0x90082, 0x149 },
  1314 + { 0x90083, 0x0 },
  1315 + { 0x90084, 0xe0 },
  1316 + { 0x90085, 0x109 },
  1317 + { 0x90086, 0xa },
  1318 + { 0x90087, 0x10 },
  1319 + { 0x90088, 0x109 },
  1320 + { 0x90089, 0x9 },
  1321 + { 0x9008a, 0x3c0 },
  1322 + { 0x9008b, 0x149 },
  1323 + { 0x9008c, 0x9 },
  1324 + { 0x9008d, 0x3c0 },
  1325 + { 0x9008e, 0x159 },
  1326 + { 0x9008f, 0x18 },
  1327 + { 0x90090, 0x10 },
  1328 + { 0x90091, 0x109 },
  1329 + { 0x90092, 0x0 },
  1330 + { 0x90093, 0x3c0 },
  1331 + { 0x90094, 0x109 },
  1332 + { 0x90095, 0x18 },
  1333 + { 0x90096, 0x4 },
  1334 + { 0x90097, 0x48 },
  1335 + { 0x90098, 0x18 },
  1336 + { 0x90099, 0x4 },
  1337 + { 0x9009a, 0x58 },
  1338 + { 0x9009b, 0xa },
  1339 + { 0x9009c, 0x10 },
  1340 + { 0x9009d, 0x109 },
  1341 + { 0x9009e, 0x2 },
  1342 + { 0x9009f, 0x10 },
  1343 + { 0x900a0, 0x109 },
  1344 + { 0x900a1, 0x5 },
  1345 + { 0x900a2, 0x7c0 },
  1346 + { 0x900a3, 0x109 },
  1347 + { 0x900a4, 0x10 },
  1348 + { 0x900a5, 0x10 },
  1349 + { 0x900a6, 0x109 },
  1350 + { 0x40000, 0x811 },
  1351 + { 0x40020, 0x880 },
  1352 + { 0x40040, 0x0 },
  1353 + { 0x40060, 0x0 },
  1354 + { 0x40001, 0x4008 },
  1355 + { 0x40021, 0x83 },
  1356 + { 0x40041, 0x4f },
  1357 + { 0x40061, 0x0 },
  1358 + { 0x40002, 0x4040 },
  1359 + { 0x40022, 0x83 },
  1360 + { 0x40042, 0x51 },
  1361 + { 0x40062, 0x0 },
  1362 + { 0x40003, 0x811 },
  1363 + { 0x40023, 0x880 },
  1364 + { 0x40043, 0x0 },
  1365 + { 0x40063, 0x0 },
  1366 + { 0x40004, 0x720 },
  1367 + { 0x40024, 0xf },
  1368 + { 0x40044, 0x1740 },
  1369 + { 0x40064, 0x0 },
  1370 + { 0x40005, 0x16 },
  1371 + { 0x40025, 0x83 },
  1372 + { 0x40045, 0x4b },
  1373 + { 0x40065, 0x0 },
  1374 + { 0x40006, 0x716 },
  1375 + { 0x40026, 0xf },
  1376 + { 0x40046, 0x2001 },
  1377 + { 0x40066, 0x0 },
  1378 + { 0x40007, 0x716 },
  1379 + { 0x40027, 0xf },
  1380 + { 0x40047, 0x2800 },
  1381 + { 0x40067, 0x0 },
  1382 + { 0x40008, 0x716 },
  1383 + { 0x40028, 0xf },
  1384 + { 0x40048, 0xf00 },
  1385 + { 0x40068, 0x0 },
  1386 + { 0x40009, 0x720 },
  1387 + { 0x40029, 0xf },
  1388 + { 0x40049, 0x1400 },
  1389 + { 0x40069, 0x0 },
  1390 + { 0x4000a, 0xe08 },
  1391 + { 0x4002a, 0xc15 },
  1392 + { 0x4004a, 0x0 },
  1393 + { 0x4006a, 0x0 },
  1394 + { 0x4000b, 0x623 },
  1395 + { 0x4002b, 0x15 },
  1396 + { 0x4004b, 0x0 },
  1397 + { 0x4006b, 0x0 },
  1398 + { 0x4000c, 0x4028 },
  1399 + { 0x4002c, 0x80 },
  1400 + { 0x4004c, 0x0 },
  1401 + { 0x4006c, 0x0 },
  1402 + { 0x4000d, 0xe08 },
  1403 + { 0x4002d, 0xc1a },
  1404 + { 0x4004d, 0x0 },
  1405 + { 0x4006d, 0x0 },
  1406 + { 0x4000e, 0x623 },
  1407 + { 0x4002e, 0x1a },
  1408 + { 0x4004e, 0x0 },
  1409 + { 0x4006e, 0x0 },
  1410 + { 0x4000f, 0x4040 },
  1411 + { 0x4002f, 0x80 },
  1412 + { 0x4004f, 0x0 },
  1413 + { 0x4006f, 0x0 },
  1414 + { 0x40010, 0x2604 },
  1415 + { 0x40030, 0x15 },
  1416 + { 0x40050, 0x0 },
  1417 + { 0x40070, 0x0 },
  1418 + { 0x40011, 0x708 },
  1419 + { 0x40031, 0x5 },
  1420 + { 0x40051, 0x0 },
  1421 + { 0x40071, 0x2002 },
  1422 + { 0x40012, 0x8 },
  1423 + { 0x40032, 0x80 },
  1424 + { 0x40052, 0x0 },
  1425 + { 0x40072, 0x0 },
  1426 + { 0x40013, 0x2604 },
  1427 + { 0x40033, 0x1a },
  1428 + { 0x40053, 0x0 },
  1429 + { 0x40073, 0x0 },
  1430 + { 0x40014, 0x708 },
  1431 + { 0x40034, 0xa },
  1432 + { 0x40054, 0x0 },
  1433 + { 0x40074, 0x2002 },
  1434 + { 0x40015, 0x4040 },
  1435 + { 0x40035, 0x80 },
  1436 + { 0x40055, 0x0 },
  1437 + { 0x40075, 0x0 },
  1438 + { 0x40016, 0x60a },
  1439 + { 0x40036, 0x15 },
  1440 + { 0x40056, 0x1200 },
  1441 + { 0x40076, 0x0 },
  1442 + { 0x40017, 0x61a },
  1443 + { 0x40037, 0x15 },
  1444 + { 0x40057, 0x1300 },
  1445 + { 0x40077, 0x0 },
  1446 + { 0x40018, 0x60a },
  1447 + { 0x40038, 0x1a },
  1448 + { 0x40058, 0x1200 },
  1449 + { 0x40078, 0x0 },
  1450 + { 0x40019, 0x642 },
  1451 + { 0x40039, 0x1a },
  1452 + { 0x40059, 0x1300 },
  1453 + { 0x40079, 0x0 },
  1454 + { 0x4001a, 0x4808 },
  1455 + { 0x4003a, 0x880 },
  1456 + { 0x4005a, 0x0 },
  1457 + { 0x4007a, 0x0 },
  1458 + { 0x900a7, 0x0 },
  1459 + { 0x900a8, 0x790 },
  1460 + { 0x900a9, 0x11a },
  1461 + { 0x900aa, 0x8 },
  1462 + { 0x900ab, 0x7aa },
  1463 + { 0x900ac, 0x2a },
  1464 + { 0x900ad, 0x10 },
  1465 + { 0x900ae, 0x7b2 },
  1466 + { 0x900af, 0x2a },
  1467 + { 0x900b0, 0x0 },
  1468 + { 0x900b1, 0x7c8 },
  1469 + { 0x900b2, 0x109 },
  1470 + { 0x900b3, 0x10 },
  1471 + { 0x900b4, 0x2a8 },
  1472 + { 0x900b5, 0x129 },
  1473 + { 0x900b6, 0x8 },
  1474 + { 0x900b7, 0x370 },
  1475 + { 0x900b8, 0x129 },
  1476 + { 0x900b9, 0xa },
  1477 + { 0x900ba, 0x3c8 },
  1478 + { 0x900bb, 0x1a9 },
  1479 + { 0x900bc, 0xc },
  1480 + { 0x900bd, 0x408 },
  1481 + { 0x900be, 0x199 },
  1482 + { 0x900bf, 0x14 },
  1483 + { 0x900c0, 0x790 },
  1484 + { 0x900c1, 0x11a },
  1485 + { 0x900c2, 0x8 },
  1486 + { 0x900c3, 0x4 },
  1487 + { 0x900c4, 0x18 },
  1488 + { 0x900c5, 0xe },
  1489 + { 0x900c6, 0x408 },
  1490 + { 0x900c7, 0x199 },
  1491 + { 0x900c8, 0x8 },
  1492 + { 0x900c9, 0x8568 },
  1493 + { 0x900ca, 0x108 },
  1494 + { 0x900cb, 0x18 },
  1495 + { 0x900cc, 0x790 },
  1496 + { 0x900cd, 0x16a },
  1497 + { 0x900ce, 0x8 },
  1498 + { 0x900cf, 0x1d8 },
  1499 + { 0x900d0, 0x169 },
  1500 + { 0x900d1, 0x10 },
  1501 + { 0x900d2, 0x8558 },
  1502 + { 0x900d3, 0x168 },
  1503 + { 0x900d4, 0x70 },
  1504 + { 0x900d5, 0x788 },
  1505 + { 0x900d6, 0x16a },
  1506 + { 0x900d7, 0x1ff8 },
  1507 + { 0x900d8, 0x85a8 },
  1508 + { 0x900d9, 0x1e8 },
  1509 + { 0x900da, 0x50 },
  1510 + { 0x900db, 0x798 },
  1511 + { 0x900dc, 0x16a },
  1512 + { 0x900dd, 0x60 },
  1513 + { 0x900de, 0x7a0 },
  1514 + { 0x900df, 0x16a },
  1515 + { 0x900e0, 0x8 },
  1516 + { 0x900e1, 0x8310 },
  1517 + { 0x900e2, 0x168 },
  1518 + { 0x900e3, 0x8 },
  1519 + { 0x900e4, 0xa310 },
  1520 + { 0x900e5, 0x168 },
  1521 + { 0x900e6, 0xa },
  1522 + { 0x900e7, 0x408 },
  1523 + { 0x900e8, 0x169 },
  1524 + { 0x900e9, 0x6e },
  1525 + { 0x900ea, 0x0 },
  1526 + { 0x900eb, 0x68 },
  1527 + { 0x900ec, 0x0 },
  1528 + { 0x900ed, 0x408 },
  1529 + { 0x900ee, 0x169 },
  1530 + { 0x900ef, 0x0 },
  1531 + { 0x900f0, 0x8310 },
  1532 + { 0x900f1, 0x168 },
  1533 + { 0x900f2, 0x0 },
  1534 + { 0x900f3, 0xa310 },
  1535 + { 0x900f4, 0x168 },
  1536 + { 0x900f5, 0x1ff8 },
  1537 + { 0x900f6, 0x85a8 },
  1538 + { 0x900f7, 0x1e8 },
  1539 + { 0x900f8, 0x68 },
  1540 + { 0x900f9, 0x798 },
  1541 + { 0x900fa, 0x16a },
  1542 + { 0x900fb, 0x78 },
  1543 + { 0x900fc, 0x7a0 },
  1544 + { 0x900fd, 0x16a },
  1545 + { 0x900fe, 0x68 },
  1546 + { 0x900ff, 0x790 },
  1547 + { 0x90100, 0x16a },
  1548 + { 0x90101, 0x8 },
  1549 + { 0x90102, 0x8b10 },
  1550 + { 0x90103, 0x168 },
  1551 + { 0x90104, 0x8 },
  1552 + { 0x90105, 0xab10 },
  1553 + { 0x90106, 0x168 },
  1554 + { 0x90107, 0xa },
  1555 + { 0x90108, 0x408 },
  1556 + { 0x90109, 0x169 },
  1557 + { 0x9010a, 0x58 },
  1558 + { 0x9010b, 0x0 },
  1559 + { 0x9010c, 0x68 },
  1560 + { 0x9010d, 0x0 },
  1561 + { 0x9010e, 0x408 },
  1562 + { 0x9010f, 0x169 },
  1563 + { 0x90110, 0x0 },
  1564 + { 0x90111, 0x8b10 },
  1565 + { 0x90112, 0x168 },
  1566 + { 0x90113, 0x0 },
  1567 + { 0x90114, 0xab10 },
  1568 + { 0x90115, 0x168 },
  1569 + { 0x90116, 0x0 },
  1570 + { 0x90117, 0x1d8 },
  1571 + { 0x90118, 0x169 },
  1572 + { 0x90119, 0x80 },
  1573 + { 0x9011a, 0x790 },
  1574 + { 0x9011b, 0x16a },
  1575 + { 0x9011c, 0x18 },
  1576 + { 0x9011d, 0x7aa },
  1577 + { 0x9011e, 0x6a },
  1578 + { 0x9011f, 0xa },
  1579 + { 0x90120, 0x0 },
  1580 + { 0x90121, 0x1e9 },
  1581 + { 0x90122, 0x8 },
  1582 + { 0x90123, 0x8080 },
  1583 + { 0x90124, 0x108 },
  1584 + { 0x90125, 0xf },
  1585 + { 0x90126, 0x408 },
  1586 + { 0x90127, 0x169 },
  1587 + { 0x90128, 0xc },
  1588 + { 0x90129, 0x0 },
  1589 + { 0x9012a, 0x68 },
  1590 + { 0x9012b, 0x9 },
  1591 + { 0x9012c, 0x0 },
  1592 + { 0x9012d, 0x1a9 },
  1593 + { 0x9012e, 0x0 },
  1594 + { 0x9012f, 0x408 },
  1595 + { 0x90130, 0x169 },
  1596 + { 0x90131, 0x0 },
  1597 + { 0x90132, 0x8080 },
  1598 + { 0x90133, 0x108 },
  1599 + { 0x90134, 0x8 },
  1600 + { 0x90135, 0x7aa },
  1601 + { 0x90136, 0x6a },
  1602 + { 0x90137, 0x0 },
  1603 + { 0x90138, 0x8568 },
  1604 + { 0x90139, 0x108 },
  1605 + { 0x9013a, 0xb7 },
  1606 + { 0x9013b, 0x790 },
  1607 + { 0x9013c, 0x16a },
  1608 + { 0x9013d, 0x1f },
  1609 + { 0x9013e, 0x0 },
  1610 + { 0x9013f, 0x68 },
  1611 + { 0x90140, 0x8 },
  1612 + { 0x90141, 0x8558 },
  1613 + { 0x90142, 0x168 },
  1614 + { 0x90143, 0xf },
  1615 + { 0x90144, 0x408 },
  1616 + { 0x90145, 0x169 },
  1617 + { 0x90146, 0xc },
  1618 + { 0x90147, 0x0 },
  1619 + { 0x90148, 0x68 },
  1620 + { 0x90149, 0x0 },
  1621 + { 0x9014a, 0x408 },
  1622 + { 0x9014b, 0x169 },
  1623 + { 0x9014c, 0x0 },
  1624 + { 0x9014d, 0x8558 },
  1625 + { 0x9014e, 0x168 },
  1626 + { 0x9014f, 0x8 },
  1627 + { 0x90150, 0x3c8 },
  1628 + { 0x90151, 0x1a9 },
  1629 + { 0x90152, 0x3 },
  1630 + { 0x90153, 0x370 },
  1631 + { 0x90154, 0x129 },
  1632 + { 0x90155, 0x20 },
  1633 + { 0x90156, 0x2aa },
  1634 + { 0x90157, 0x9 },
  1635 + { 0x90158, 0x0 },
  1636 + { 0x90159, 0x400 },
  1637 + { 0x9015a, 0x10e },
  1638 + { 0x9015b, 0x8 },
  1639 + { 0x9015c, 0xe8 },
  1640 + { 0x9015d, 0x109 },
  1641 + { 0x9015e, 0x0 },
  1642 + { 0x9015f, 0x8140 },
  1643 + { 0x90160, 0x10c },
  1644 + { 0x90161, 0x10 },
  1645 + { 0x90162, 0x8138 },
  1646 + { 0x90163, 0x10c },
  1647 + { 0x90164, 0x8 },
  1648 + { 0x90165, 0x7c8 },
  1649 + { 0x90166, 0x101 },
  1650 + { 0x90167, 0x8 },
  1651 + { 0x90168, 0x0 },
  1652 + { 0x90169, 0x8 },
  1653 + { 0x9016a, 0x8 },
  1654 + { 0x9016b, 0x448 },
  1655 + { 0x9016c, 0x109 },
  1656 + { 0x9016d, 0xf },
  1657 + { 0x9016e, 0x7c0 },
  1658 + { 0x9016f, 0x109 },
  1659 + { 0x90170, 0x0 },
  1660 + { 0x90171, 0xe8 },
  1661 + { 0x90172, 0x109 },
  1662 + { 0x90173, 0x47 },
  1663 + { 0x90174, 0x630 },
  1664 + { 0x90175, 0x109 },
  1665 + { 0x90176, 0x8 },
  1666 + { 0x90177, 0x618 },
  1667 + { 0x90178, 0x109 },
  1668 + { 0x90179, 0x8 },
  1669 + { 0x9017a, 0xe0 },
  1670 + { 0x9017b, 0x109 },
  1671 + { 0x9017c, 0x0 },
  1672 + { 0x9017d, 0x7c8 },
  1673 + { 0x9017e, 0x109 },
  1674 + { 0x9017f, 0x8 },
  1675 + { 0x90180, 0x8140 },
  1676 + { 0x90181, 0x10c },
  1677 + { 0x90182, 0x0 },
  1678 + { 0x90183, 0x1 },
  1679 + { 0x90184, 0x8 },
  1680 + { 0x90185, 0x8 },
  1681 + { 0x90186, 0x4 },
  1682 + { 0x90187, 0x8 },
  1683 + { 0x90188, 0x8 },
  1684 + { 0x90189, 0x7c8 },
  1685 + { 0x9018a, 0x101 },
  1686 + { 0x90006, 0x0 },
  1687 + { 0x90007, 0x0 },
  1688 + { 0x90008, 0x8 },
  1689 + { 0x90009, 0x0 },
  1690 + { 0x9000a, 0x0 },
  1691 + { 0x9000b, 0x0 },
  1692 + { 0xd00e7, 0x400 },
  1693 + { 0x90017, 0x0 },
  1694 + { 0x9001f, 0x2a },
  1695 + { 0x90026, 0x6a },
  1696 + { 0x400d0, 0x0 },
  1697 + { 0x400d1, 0x101 },
  1698 + { 0x400d2, 0x105 },
  1699 + { 0x400d3, 0x107 },
  1700 + { 0x400d4, 0x10f },
  1701 + { 0x400d5, 0x202 },
  1702 + { 0x400d6, 0x20a },
  1703 + { 0x400d7, 0x20b },
  1704 + { 0x2003a, 0x2 },
  1705 + { 0x2000b, 0x5d },
  1706 + { 0x2000c, 0xbb },
  1707 + { 0x2000d, 0x753 },
  1708 + { 0x2000e, 0x2c },
  1709 + { 0x12000b, 0xc },
  1710 + { 0x12000c, 0x19 },
  1711 + { 0x12000d, 0xfa },
  1712 + { 0x12000e, 0x10 },
  1713 + { 0x22000b, 0x3 },
  1714 + { 0x22000c, 0x6 },
  1715 + { 0x22000d, 0x3e },
  1716 + { 0x22000e, 0x10 },
  1717 + { 0x9000c, 0x0 },
  1718 + { 0x9000d, 0x173 },
  1719 + { 0x9000e, 0x60 },
  1720 + { 0x9000f, 0x6110 },
  1721 + { 0x90010, 0x2152 },
  1722 + { 0x90011, 0xdfbd },
  1723 + { 0x90012, 0x60 },
  1724 + { 0x90013, 0x6152 },
  1725 + { 0x20010, 0x5a },
  1726 + { 0x20011, 0x3 },
  1727 + { 0x120010, 0x5a },
  1728 + { 0x120011, 0x3 },
  1729 + { 0x220010, 0x5a },
  1730 + { 0x220011, 0x3 },
  1731 + { 0x40080, 0xe0 },
  1732 + { 0x40081, 0x12 },
  1733 + { 0x40082, 0xe0 },
  1734 + { 0x40083, 0x12 },
  1735 + { 0x40084, 0xe0 },
  1736 + { 0x40085, 0x12 },
  1737 + { 0x140080, 0xe0 },
  1738 + { 0x140081, 0x12 },
  1739 + { 0x140082, 0xe0 },
  1740 + { 0x140083, 0x12 },
  1741 + { 0x140084, 0xe0 },
  1742 + { 0x140085, 0x12 },
  1743 + { 0x240080, 0xe0 },
  1744 + { 0x240081, 0x12 },
  1745 + { 0x240082, 0xe0 },
  1746 + { 0x240083, 0x12 },
  1747 + { 0x240084, 0xe0 },
  1748 + { 0x240085, 0x12 },
  1749 + { 0x400fd, 0xf },
  1750 + { 0x10011, 0x1 },
  1751 + { 0x10012, 0x1 },
  1752 + { 0x10013, 0x180 },
  1753 + { 0x10018, 0x1 },
  1754 + { 0x10002, 0x6209 },
  1755 + { 0x100b2, 0x1 },
  1756 + { 0x101b4, 0x1 },
  1757 + { 0x102b4, 0x1 },
  1758 + { 0x103b4, 0x1 },
  1759 + { 0x104b4, 0x1 },
  1760 + { 0x105b4, 0x1 },
  1761 + { 0x106b4, 0x1 },
  1762 + { 0x107b4, 0x1 },
  1763 + { 0x108b4, 0x1 },
  1764 + { 0x11011, 0x1 },
  1765 + { 0x11012, 0x1 },
  1766 + { 0x11013, 0x180 },
  1767 + { 0x11018, 0x1 },
  1768 + { 0x11002, 0x6209 },
  1769 + { 0x110b2, 0x1 },
  1770 + { 0x111b4, 0x1 },
  1771 + { 0x112b4, 0x1 },
  1772 + { 0x113b4, 0x1 },
  1773 + { 0x114b4, 0x1 },
  1774 + { 0x115b4, 0x1 },
  1775 + { 0x116b4, 0x1 },
  1776 + { 0x117b4, 0x1 },
  1777 + { 0x118b4, 0x1 },
  1778 + { 0x12011, 0x1 },
  1779 + { 0x12012, 0x1 },
  1780 + { 0x12013, 0x180 },
  1781 + { 0x12018, 0x1 },
  1782 + { 0x12002, 0x6209 },
  1783 + { 0x120b2, 0x1 },
  1784 + { 0x121b4, 0x1 },
  1785 + { 0x122b4, 0x1 },
  1786 + { 0x123b4, 0x1 },
  1787 + { 0x124b4, 0x1 },
  1788 + { 0x125b4, 0x1 },
  1789 + { 0x126b4, 0x1 },
  1790 + { 0x127b4, 0x1 },
  1791 + { 0x128b4, 0x1 },
  1792 + { 0x13011, 0x1 },
  1793 + { 0x13012, 0x1 },
  1794 + { 0x13013, 0x180 },
  1795 + { 0x13018, 0x1 },
  1796 + { 0x13002, 0x6209 },
  1797 + { 0x130b2, 0x1 },
  1798 + { 0x131b4, 0x1 },
  1799 + { 0x132b4, 0x1 },
  1800 + { 0x133b4, 0x1 },
  1801 + { 0x134b4, 0x1 },
  1802 + { 0x135b4, 0x1 },
  1803 + { 0x136b4, 0x1 },
  1804 + { 0x137b4, 0x1 },
  1805 + { 0x138b4, 0x1 },
  1806 + { 0x2003a, 0x2 },
  1807 + { 0xc0080, 0x2 },
  1808 + { 0xd0000, 0x1 }
  1809 +};
  1810 +
  1811 +struct dram_fsp_msg ddr_dram_fsp_msg[] = {
  1812 + {
  1813 + /* P0 3000mts 1D */
  1814 + .drate = 3000,
  1815 + .fw_type = FW_1D_IMAGE,
  1816 + .fsp_cfg = ddr_fsp0_cfg,
  1817 + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
  1818 + },
  1819 + {
  1820 + /* P1 400mts 1D */
  1821 + .drate = 400,
  1822 + .fw_type = FW_1D_IMAGE,
  1823 + .fsp_cfg = ddr_fsp1_cfg,
  1824 + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
  1825 + },
  1826 + {
  1827 + /* P2 100mts 1D */
  1828 + .drate = 100,
  1829 + .fw_type = FW_1D_IMAGE,
  1830 + .fsp_cfg = ddr_fsp2_cfg,
  1831 + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
  1832 + },
  1833 + {
  1834 + /* P0 3000mts 2D */
  1835 + .drate = 3000,
  1836 + .fw_type = FW_2D_IMAGE,
  1837 + .fsp_cfg = ddr_fsp0_2d_cfg,
  1838 + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
  1839 + },
  1840 +};
  1841 +
  1842 +/* ddr timing config params */
  1843 +struct dram_timing_info dram_timing = {
  1844 + .ddrc_cfg = ddr_ddrc_cfg,
  1845 + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
  1846 + .ddrphy_cfg = ddr_ddrphy_cfg,
  1847 + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
  1848 + .fsp_msg = ddr_dram_fsp_msg,
  1849 + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
  1850 + .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
  1851 + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
  1852 + .ddrphy_pie = ddr_phy_pie,
  1853 + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
  1854 + .fsp_table = { 3000, 400, 100, },
  1855 +};
board/freescale/imx8mm_ab2/spl.c
Diff comments   View file @ e384b64
  1 +/*
  2 + * Copyright 2020 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <cpu_func.h>
  9 +#include <hang.h>
  10 +#include <spl.h>
  11 +#include <asm/io.h>
  12 +#include <errno.h>
  13 +#include <asm/io.h>
  14 +#include <asm/mach-imx/iomux-v3.h>
  15 +#include <asm/arch/sys_proto.h>
  16 +#include <asm/mach-imx/boot_mode.h>
  17 +#include <power/pmic.h>
  18 +#include <asm/arch/clock.h>
  19 +#include <asm/mach-imx/gpio.h>
  20 +#include <asm/mach-imx/mxc_i2c.h>
  21 +#include <fsl_esdhc_imx.h>
  22 +#include <mmc.h>
  23 +#include <asm/arch/ddr.h>
  24 +
  25 +#ifdef CONFIG_TARGET_IMX8MM_AB2
  26 +#include <asm/arch/imx8mm_pins.h>
  27 +#endif
  28 +
  29 +#ifdef CONFIG_POWER_PCA9450
  30 +#include <power/pca9450.h>
  31 +#else
  32 +#include <power/bd71837.h>
  33 +#endif
  34 +
  35 +DECLARE_GLOBAL_DATA_PTR;
  36 +
  37 +int spl_board_boot_device(enum boot_device boot_dev_spl)
  38 +{
  39 + switch (boot_dev_spl) {
  40 + case SD2_BOOT:
  41 + case MMC2_BOOT:
  42 + return BOOT_DEVICE_MMC1;
  43 + case SD3_BOOT:
  44 + case MMC3_BOOT:
  45 + return BOOT_DEVICE_MMC2;
  46 + case QSPI_BOOT:
  47 + return BOOT_DEVICE_NOR;
  48 + case NAND_BOOT:
  49 + return BOOT_DEVICE_NAND;
  50 + case USB_BOOT:
  51 + return BOOT_DEVICE_NONE;
  52 + default:
  53 + return BOOT_DEVICE_NONE;
  54 + }
  55 +}
  56 +
  57 +void spl_dram_init(void)
  58 +{
  59 + ddr_init(&dram_timing);
  60 +}
  61 +
  62 +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
  63 +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  64 +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \
  65 + PAD_CTL_FSEL2)
  66 +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
  67 +#define USDHC_CD_PAD_CTRL (PAD_CTL_PE |PAD_CTL_PUE |PAD_CTL_HYS | PAD_CTL_DSE4)
  68 +
  69 +#ifdef CONFIG_TARGET_IMX8MM_AB2
  70 +struct i2c_pads_info i2c_pad_info1 = {
  71 + .scl = {
  72 + .i2c_mode = IMX8MM_PAD_I2C1_SCL_I2C1_SCL | PC,
  73 + .gpio_mode = IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 | PC,
  74 + .gp = IMX_GPIO_NR(5, 14),
  75 + },
  76 + .sda = {
  77 + .i2c_mode = IMX8MM_PAD_I2C1_SDA_I2C1_SDA | PC,
  78 + .gpio_mode = IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 | PC,
  79 + .gp = IMX_GPIO_NR(5, 15),
  80 + },
  81 +};
  82 +#endif
  83 +
  84 +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
  85 +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
  86 +
  87 +#ifdef CONFIG_TARGET_IMX8MM_AB2
  88 +static iomux_v3_cfg_t const usdhc3_pads[] = {
  89 + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  90 + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91 + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  92 + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93 + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94 + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95 + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96 + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97 + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98 + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99 +};
  100 +
  101 +static iomux_v3_cfg_t const usdhc2_pads[] = {
  102 + IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  103 + IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  104 + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  105 + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  106 + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  107 + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  108 + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
  109 + IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
  110 +};
  111 +#endif
  112 +
  113 +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  114 + {USDHC2_BASE_ADDR, 0, 4},
  115 + {USDHC3_BASE_ADDR, 0, 8},
  116 +};
  117 +
  118 +int board_mmc_init(bd_t *bis)
  119 +{
  120 + int i, ret;
  121 + /*
  122 + * According to the board_mmc_init() the following map is done:
  123 + * (U-Boot device node) (Physical Port)
  124 + * mmc0 USDHC1
  125 + * mmc1 USDHC2
  126 + */
  127 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  128 + switch (i) {
  129 + case 0:
  130 + init_clk_usdhc(1);
  131 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  132 + imx_iomux_v3_setup_multiple_pads(
  133 + usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  134 + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
  135 + gpio_direction_output(USDHC2_PWR_GPIO, 0);
  136 + udelay(500);
  137 + gpio_direction_output(USDHC2_PWR_GPIO, 1);
  138 + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
  139 + gpio_direction_input(USDHC2_CD_GPIO);
  140 + break;
  141 + case 1:
  142 + init_clk_usdhc(2);
  143 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  144 + imx_iomux_v3_setup_multiple_pads(
  145 + usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  146 + break;
  147 + default:
  148 + printf("Warning: you configured more USDHC controllers"
  149 + "(%d) than supported by the board\n", i + 1);
  150 + return -EINVAL;
  151 + }
  152 +
  153 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  154 + if (ret)
  155 + return ret;
  156 + }
  157 +
  158 + return 0;
  159 +}
  160 +
  161 +int board_mmc_getcd(struct mmc *mmc)
  162 +{
  163 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  164 + int ret = 0;
  165 +
  166 + switch (cfg->esdhc_base) {
  167 + case USDHC3_BASE_ADDR:
  168 + ret = 1;
  169 + break;
  170 + case USDHC2_BASE_ADDR:
  171 + ret = !gpio_get_value(USDHC2_CD_GPIO);
  172 + return ret;
  173 + }
  174 +
  175 + return 1;
  176 +}
  177 +
  178 +#ifdef CONFIG_POWER
  179 +#define I2C_PMIC 0
  180 +int power_init_board(void)
  181 +{
  182 + struct pmic *p;
  183 + int ret;
  184 +
  185 +#ifdef CONFIG_POWER_PCA9450
  186 + ret = power_pca9450b_init(I2C_PMIC);
  187 + if (ret)
  188 + printf("power init failed");
  189 + p = pmic_get("PCA9450");
  190 + pmic_probe(p);
  191 +
  192 + /* BUCKxOUT_DVS0/1 control BUCK123 output */
  193 + pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
  194 +
  195 + /*
  196 + * increase VDD_SOC to typical value 0.95V before first
  197 + * DRAM access, set DVS1 to 0.85v for suspend.
  198 + * Enable DVS control through PMIC_STBY_REQ and
  199 + * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
  200 + */
  201 + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
  202 + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
  203 + pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
  204 +
  205 + /* Kernel uses OD/OD freq for SOC */
  206 + /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
  207 + pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
  208 +
  209 + /* set WDOG_B_CFG to cold reset */
  210 + pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
  211 +
  212 +#else
  213 + ret = power_bd71837_init(I2C_PMIC);
  214 + if (ret)
  215 + printf("power init failed");
  216 + p = pmic_get("BD71837");
  217 + pmic_probe(p);
  218 +
  219 + /* decrease RESET key long push time from the default 10s to 10ms */
  220 + pmic_reg_write(p, BD71837_PWRONCONFIG1, 0x0);
  221 + /* unlock the PMIC regs */
  222 + pmic_reg_write(p, BD71837_REGLOCK, 0x1);
  223 + /* increase VDD_SOC to typical value 0.85v before first DRAM access */
  224 + pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x0f);
  225 + /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
  226 + pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x83);
  227 +#ifndef CONFIG_IMX8M_LPDDR4
  228 + /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
  229 + pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28);
  230 +#endif
  231 + /* lock the PMIC regs */
  232 + pmic_reg_write(p, BD71837_REGLOCK, 0x11);
  233 +#endif
  234 +
  235 + return 0;
  236 +}
  237 +#endif
  238 +
  239 +void spl_board_init(void)
  240 +{
  241 +#ifndef CONFIG_SPL_USB_SDP_SUPPORT
  242 +#ifdef CONFIG_TARGET_IMX8MM_AB2
  243 + /* Serial download mode */
  244 + if (is_usb_boot()) {
  245 + puts("Back to ROM, SDP\n");
  246 + restore_boot_params();
  247 + }
  248 +#endif
  249 +#endif
  250 + puts("Normal Boot\n");
  251 +}
  252 +
  253 +#ifdef CONFIG_SPL_LOAD_FIT
  254 +int board_fit_config_name_match(const char *name)
  255 +{
  256 + /* Just empty function now - can't decide what to choose */
  257 + debug("%s: %s\n", __func__, name);
  258 +
  259 + return 0;
  260 +}
  261 +#endif
  262 +
  263 +void board_init_f(ulong dummy)
  264 +{
  265 + int ret;
  266 +
  267 + /* Clear the BSS. */
  268 + memset(__bss_start, 0, __bss_end - __bss_start);
  269 +
  270 + arch_cpu_init();
  271 +
  272 + board_early_init_f();
  273 +
  274 + timer_init();
  275 +
  276 + preloader_console_init();
  277 +
  278 + ret = spl_init();
  279 + if (ret) {
  280 + debug("spl_init() failed: %d\n", ret);
  281 + hang();
  282 + }
  283 +
  284 + enable_tzc380();
  285 +
  286 + /* Adjust pmic voltage to 1.0V for 800M */
  287 + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  288 +
  289 + power_init_board();
  290 +
  291 + /* DDR initialization */
  292 + spl_dram_init();
  293 +
  294 + board_init_r(NULL, 0);
  295 +}
  296 +
  297 +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  298 +{
  299 + puts("resetting ...\n");
  300 +
  301 + reset_cpu(WDOG1_BASE_ADDR);
  302 +
  303 + return 0;
  304 +}
configs/imx8mm_ab2_defconfig
Diff comments   View file @ e384b64
  1 +CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_ICACHE_OFF=y
  3 +CONFIG_SPL_SYS_DCACHE_OFF=y
  4 +CONFIG_ARCH_IMX8M=y
  5 +CONFIG_SYS_TEXT_BASE=0x40200000
  6 +CONFIG_SPL_GPIO_SUPPORT=y
  7 +CONFIG_SPL_LIBCOMMON_SUPPORT=y
  8 +CONFIG_SPL_LIBGENERIC_SUPPORT=y
  9 +CONFIG_SYS_MALLOC_F_LEN=0x2000
  10 +CONFIG_SYS_I2C_MXC_I2C1=y
  11 +CONFIG_SYS_I2C_MXC_I2C2=y
  12 +CONFIG_SYS_I2C_MXC_I2C3=y
  13 +CONFIG_ENV_SIZE=0x1000
  14 +CONFIG_ENV_OFFSET=0x400000
  15 +CONFIG_DM_GPIO=y
  16 +CONFIG_TARGET_IMX8MM_AB2=y
  17 +CONFIG_ARCH_MISC_INIT=y
  18 +CONFIG_SPL_MMC_SUPPORT=y
  19 +CONFIG_SPL_SERIAL_SUPPORT=y
  20 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
  21 +CONFIG_SPL=y
  22 +CONFIG_CSF_SIZE=0x2000
  23 +CONFIG_SPL_TEXT_BASE=0x7E1000
  24 +CONFIG_FIT=y
  25 +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
  26 +CONFIG_SPL_LOAD_FIT=y
  27 +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
  28 +CONFIG_OF_SYSTEM_SETUP=y
  29 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
  30 +CONFIG_BOARD_LATE_INIT=y
  31 +CONFIG_BOARD_EARLY_INIT_F=y
  32 +CONFIG_SPL_BOARD_INIT=y
  33 +CONFIG_SPL_SEPARATE_BSS=y
  34 +CONFIG_SPL_I2C_SUPPORT=y
  35 +CONFIG_SPL_POWER_SUPPORT=y
  36 +CONFIG_NR_DRAM_BANKS=2
  37 +CONFIG_HUSH_PARSER=y
  38 +CONFIG_SYS_PROMPT="u-boot=> "
  39 +# CONFIG_CMD_EXPORTENV is not set
  40 +# CONFIG_CMD_IMPORTENV is not set
  41 +# CONFIG_CMD_CRC32 is not set
  42 +# CONFIG_BOOTM_NETBSD is not set
  43 +CONFIG_CMD_CLK=y
  44 +CONFIG_CMD_FUSE=y
  45 +CONFIG_CMD_GPIO=y
  46 +CONFIG_CMD_I2C=y
  47 +CONFIG_CMD_MMC=y
  48 +CONFIG_CMD_DHCP=y
  49 +CONFIG_CMD_MII=y
  50 +CONFIG_CMD_PING=y
  51 +CONFIG_CMD_CACHE=y
  52 +CONFIG_CMD_REGULATOR=y
  53 +CONFIG_CMD_MEMTEST=y
  54 +CONFIG_CMD_EXT2=y
  55 +CONFIG_CMD_EXT4=y
  56 +CONFIG_CMD_EXT4_WRITE=y
  57 +CONFIG_CMD_FAT=y
  58 +CONFIG_CMD_SF=y
  59 +CONFIG_OF_CONTROL=y
  60 +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-ab2"
  61 +CONFIG_DEFAULT_FDT_FILE="imx8mm-ab2.dtb"
  62 +CONFIG_ENV_IS_IN_MMC=y
  63 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  64 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
  65 +CONFIG_CLK_COMPOSITE_CCF=y
  66 +CONFIG_CLK_IMX8MM=y
  67 +CONFIG_MXC_GPIO=y
  68 +
  69 +CONFIG_DM_I2C=y
  70 +CONFIG_SYS_I2C_MXC=y
  71 +CONFIG_DM_MMC=y
  72 +CONFIG_MMC_IO_VOLTAGE=y
  73 +CONFIG_MMC_UHS_SUPPORT=y
  74 +CONFIG_MMC_HS400_SUPPORT=y
  75 +CONFIG_MMC_HS400_ES_SUPPORT=y
  76 +CONFIG_EFI_PARTITION=y
  77 +CONFIG_SUPPORT_EMMC_BOOT=y
  78 +CONFIG_FSL_ESDHC_IMX=y
  79 +CONFIG_DM_SPI_FLASH=y
  80 +CONFIG_DM_SPI=y
  81 +CONFIG_FSL_FSPI=y
  82 +CONFIG_SPI=y
  83 +CONFIG_SPI_FLASH=y
  84 +CONFIG_SPI_FLASH_BAR=y
  85 +CONFIG_SPI_FLASH_STMICRO=y
  86 +CONFIG_SF_DEFAULT_BUS=0
  87 +CONFIG_SF_DEFAULT_CS=0
  88 +CONFIG_SF_DEFAULT_SPEED=40000000
  89 +CONFIG_SF_DEFAULT_MODE=0
  90 +
  91 +CONFIG_PHYLIB=y
  92 +CONFIG_PHY_REALTEK=y
  93 +CONFIG_DM_ETH=y
  94 +CONFIG_PHY_GIGE=y
  95 +CONFIG_FEC_MXC=y
  96 +CONFIG_MII=y
  97 +CONFIG_PINCTRL=y
  98 +CONFIG_PINCTRL_IMX8M=y
  99 +CONFIG_DM_REGULATOR=y
  100 +CONFIG_DM_REGULATOR_FIXED=y
  101 +CONFIG_DM_REGULATOR_GPIO=y
  102 +CONFIG_MXC_UART=y
  103 +CONFIG_SYSRESET=y
  104 +CONFIG_SYSRESET_PSCI=y
  105 +CONFIG_DM_THERMAL=y
  106 +CONFIG_NXP_TMU=y
  107 +
  108 +CONFIG_OF_LIBFDT_OVERLAY=y
configs/imx8mm_ab2_fspi_defconfig
Diff comments   View file @ e384b64
  1 +CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_ICACHE_OFF=y
  3 +CONFIG_SPL_SYS_DCACHE_OFF=y
  4 +CONFIG_ARCH_IMX8M=y
  5 +CONFIG_SYS_TEXT_BASE=0x40200000
  6 +CONFIG_SPL_GPIO_SUPPORT=y
  7 +CONFIG_SPL_LIBCOMMON_SUPPORT=y
  8 +CONFIG_SPL_LIBGENERIC_SUPPORT=y
  9 +CONFIG_SYS_MALLOC_F_LEN=0x2000
  10 +CONFIG_SYS_I2C_MXC_I2C1=y
  11 +CONFIG_SYS_I2C_MXC_I2C2=y
  12 +CONFIG_SYS_I2C_MXC_I2C3=y
  13 +CONFIG_ENV_SIZE=0x1000
  14 +CONFIG_ENV_OFFSET=0x400000
  15 +CONFIG_DM_GPIO=y
  16 +CONFIG_TARGET_IMX8MM_AB2=y
  17 +CONFIG_ARCH_MISC_INIT=y
  18 +CONFIG_SPL_NOR_SUPPORT=y
  19 +CONFIG_SPL_SERIAL_SUPPORT=y
  20 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
  21 +CONFIG_SPL=y
  22 +CONFIG_CSF_SIZE=0x2000
  23 +CONFIG_SPL_TEXT_BASE=0x7E2000
  24 +CONFIG_FIT=y
  25 +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
  26 +CONFIG_SPL_LOAD_FIT=y
  27 +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
  28 +CONFIG_OF_SYSTEM_SETUP=y
  29 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4-fspi.cfg"
  30 +CONFIG_BOARD_LATE_INIT=y
  31 +CONFIG_BOARD_EARLY_INIT_F=y
  32 +CONFIG_SPL_BOARD_INIT=y
  33 +CONFIG_SPL_SEPARATE_BSS=y
  34 +CONFIG_SPL_I2C_SUPPORT=y
  35 +CONFIG_SPL_POWER_SUPPORT=y
  36 +CONFIG_NR_DRAM_BANKS=2
  37 +CONFIG_HUSH_PARSER=y
  38 +CONFIG_SYS_PROMPT="u-boot=> "
  39 +# CONFIG_CMD_EXPORTENV is not set
  40 +# CONFIG_CMD_IMPORTENV is not set
  41 +# CONFIG_CMD_CRC32 is not set
  42 +# CONFIG_BOOTM_NETBSD is not set
  43 +CONFIG_CMD_CLK=y
  44 +CONFIG_CMD_FUSE=y
  45 +CONFIG_CMD_GPIO=y
  46 +CONFIG_CMD_I2C=y
  47 +CONFIG_CMD_MMC=y
  48 +CONFIG_CMD_DHCP=y
  49 +CONFIG_CMD_MII=y
  50 +CONFIG_CMD_PING=y
  51 +CONFIG_CMD_CACHE=y
  52 +CONFIG_CMD_REGULATOR=y
  53 +CONFIG_CMD_MEMTEST=y
  54 +CONFIG_CMD_EXT2=y
  55 +CONFIG_CMD_EXT4=y
  56 +CONFIG_CMD_EXT4_WRITE=y
  57 +CONFIG_CMD_FAT=y
  58 +CONFIG_CMD_SF=y
  59 +CONFIG_OF_CONTROL=y
  60 +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-ab2"
  61 +CONFIG_DEFAULT_FDT_FILE="imx8mm-ab2.dtb"
  62 +CONFIG_ENV_IS_IN_SPI_FLASH=y
  63 +CONFIG_ENV_SECT_SIZE=0x10000
  64 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  65 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
  66 +CONFIG_CLK_COMPOSITE_CCF=y
  67 +CONFIG_CLK_IMX8MM=y
  68 +CONFIG_MXC_GPIO=y
  69 +
  70 +CONFIG_DM_I2C=y
  71 +CONFIG_SYS_I2C_MXC=y
  72 +CONFIG_DM_MMC=y
  73 +CONFIG_MMC_IO_VOLTAGE=y
  74 +CONFIG_MMC_UHS_SUPPORT=y
  75 +CONFIG_MMC_HS400_SUPPORT=y
  76 +CONFIG_MMC_HS400_ES_SUPPORT=y
  77 +CONFIG_EFI_PARTITION=y
  78 +CONFIG_SUPPORT_EMMC_BOOT=y
  79 +CONFIG_FSL_ESDHC_IMX=y
  80 +CONFIG_DM_SPI_FLASH=y
  81 +CONFIG_DM_SPI=y
  82 +CONFIG_FSL_FSPI=y
  83 +CONFIG_SPI=y
  84 +CONFIG_SPI_FLASH=y
  85 +CONFIG_SPI_FLASH_BAR=y
  86 +CONFIG_SPI_FLASH_STMICRO=y
  87 +CONFIG_SF_DEFAULT_BUS=0
  88 +CONFIG_SF_DEFAULT_CS=0
  89 +CONFIG_SF_DEFAULT_SPEED=40000000
  90 +CONFIG_SF_DEFAULT_MODE=0
  91 +
  92 +CONFIG_PHYLIB=y
  93 +CONFIG_PHY_REALTEK=y
  94 +CONFIG_DM_ETH=y
  95 +CONFIG_PHY_GIGE=y
  96 +CONFIG_FEC_MXC=y
  97 +CONFIG_MII=y
  98 +CONFIG_PINCTRL=y
  99 +CONFIG_PINCTRL_IMX8M=y
  100 +CONFIG_DM_REGULATOR=y
  101 +CONFIG_DM_REGULATOR_FIXED=y
  102 +CONFIG_DM_REGULATOR_GPIO=y
  103 +CONFIG_MXC_UART=y
  104 +CONFIG_SYSRESET=y
  105 +CONFIG_SYSRESET_PSCI=y
  106 +CONFIG_DM_THERMAL=y
  107 +CONFIG_NXP_TMU=y
  108 +
  109 +CONFIG_OF_LIBFDT_OVERLAY=y
include/configs/imx8mm_ab2.h
Diff comments   View file @ e384b64
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2020 NXP
  4 + */
  5 +
  6 +#ifndef __IMX8MM_AB2_H
  7 +#define __IMX8MM_AB2_H
  8 +
  9 +#include <linux/sizes.h>
  10 +#include <asm/arch/imx-regs.h>
  11 +#include "imx_env.h"
  12 +
  13 +#define CONFIG_SPL_MAX_SIZE (148 * 1024)
  14 +#define CONFIG_SYS_MONITOR_LEN SZ_512K
  15 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  16 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
  17 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  18 +#define CONFIG_SYS_UBOOT_BASE \
  19 + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
  20 +
  21 +#ifdef CONFIG_SPL_BUILD
  22 +#define CONFIG_SPL_STACK 0x920000
  23 +#define CONFIG_SPL_BSS_START_ADDR 0x910000
  24 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
  25 +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
  26 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
  27 +
  28 +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
  29 +#define CONFIG_MALLOC_F_ADDR 0x912000
  30 +/* For RAW image gives a error info not panic */
  31 +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  32 +
  33 +#define CONFIG_POWER
  34 +#define CONFIG_POWER_I2C
  35 +#define CONFIG_POWER_BD71837
  36 +
  37 +#define CONFIG_SYS_I2C
  38 +
  39 +#if defined(CONFIG_NAND_BOOT)
  40 +#define CONFIG_SPL_NAND_SUPPORT
  41 +#define CONFIG_SPL_DMA
  42 +#define CONFIG_SPL_NAND_MXS
  43 +#define CONFIG_SPL_NAND_BASE
  44 +#define CONFIG_SPL_NAND_IDENT
  45 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */
  46 +
  47 +/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */
  48 +#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
  49 + (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
  50 +#endif
  51 +
  52 +#endif
  53 +
  54 +#define CONFIG_CMD_READ
  55 +#define CONFIG_SERIAL_TAG
  56 +
  57 +#define CONFIG_REMAKE_ELF
  58 +/* ENET Config */
  59 +/* ENET1 */
  60 +#if defined(CONFIG_FEC_MXC)
  61 +#define CONFIG_ETHPRIME "eth0"
  62 +
  63 +#define CONFIG_FEC_XCV_TYPE RGMII
  64 +#define CONFIG_FEC_MXC_PHYADDR 1
  65 +#define FEC_QUIRK_ENET_MAC
  66 +
  67 +#define IMX_FEC_BASE 0x30BE0000
  68 +#endif
  69 +
  70 +#ifdef CONFIG_NAND_BOOT
  71 +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)"
  72 +#endif
  73 +
  74 +/*
  75 + * Another approach is add the clocks for inmates into clks_init_on
  76 + * in clk-imx8mm.c, then clk_ingore_unused could be removed.
  77 + */
  78 +#define JAILHOUSE_ENV \
  79 + "jh_clk= \0 " \
  80 + "jh_mmcboot=mw 0x303d0518 0xff; setenv fdt_file imx8mm-ab2-root.dtb;" \
  81 + "setenv jh_clk clk_ignore_unused; " \
  82 + "if run loadimage; then " \
  83 + "run mmcboot; " \
  84 + "else run jh_netboot; fi; \0" \
  85 + "jh_netboot=mw 0x303d0518 0xff; setenv fdt_file imx8mm-ab2-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 "
  86 +
  87 +
  88 +#define CONFIG_MFG_ENV_SETTINGS \
  89 + CONFIG_MFG_ENV_SETTINGS_DEFAULT \
  90 + "initrd_addr=0x43800000\0" \
  91 + "initrd_high=0xffffffffffffffff\0" \
  92 + "emmc_dev=2\0"\
  93 + "sd_dev=1\0" \
  94 +
  95 +/* Initial environment variables */
  96 +#if defined(CONFIG_NAND_BOOT)
  97 +#define CONFIG_EXTRA_ENV_SETTINGS \
  98 + CONFIG_MFG_ENV_SETTINGS \
  99 + "fdt_addr=0x43000000\0" \
  100 + "fdt_high=0xffffffffffffffff\0" \
  101 + "mtdparts=" MFG_NAND_PARTITION "\0" \
  102 + "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
  103 + "bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=nandrootfs " \
  104 + "root=ubi0:nandrootfs rootfstype=ubifs " \
  105 + MFG_NAND_PARTITION \
  106 + "\0" \
  107 + "bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\
  108 + "nand read ${fdt_addr} 0x7000000 0x100000;"\
  109 + "booti ${loadaddr} - ${fdt_addr}"
  110 +
  111 +#else
  112 +#define CONFIG_EXTRA_ENV_SETTINGS \
  113 + CONFIG_MFG_ENV_SETTINGS \
  114 + JAILHOUSE_ENV \
  115 + "script=boot.scr\0" \
  116 + "image=Image\0" \
  117 + "console=ttymxc1,115200\0" \
  118 + "fdt_addr=0x43000000\0" \
  119 + "fdt_high=0xffffffffffffffff\0" \
  120 + "boot_fit=no\0" \
  121 + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
  122 + "initrd_addr=0x43800000\0" \
  123 + "initrd_high=0xffffffffffffffff\0" \
  124 + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
  125 + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  126 + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  127 + "mmcautodetect=yes\0" \
  128 + "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
  129 + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  130 + "bootscript=echo Running bootscript from mmc ...; " \
  131 + "source\0" \
  132 + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  133 + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  134 + "mmcboot=echo Booting from mmc ...; " \
  135 + "run mmcargs; " \
  136 + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
  137 + "bootm ${loadaddr}; " \
  138 + "else " \
  139 + "if run loadfdt; then " \
  140 + "booti ${loadaddr} - ${fdt_addr}; " \
  141 + "else " \
  142 + "echo WARN: Cannot load the DT; " \
  143 + "fi; " \
  144 + "fi;\0" \
  145 + "netargs=setenv bootargs ${jh_clk} console=${console} " \
  146 + "root=/dev/nfs " \
  147 + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
  148 + "netboot=echo Booting from net ...; " \
  149 + "run netargs; " \
  150 + "if test ${ip_dyn} = yes; then " \
  151 + "setenv get_cmd dhcp; " \
  152 + "else " \
  153 + "setenv get_cmd tftp; " \
  154 + "fi; " \
  155 + "${get_cmd} ${loadaddr} ${image}; " \
  156 + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
  157 + "bootm ${loadaddr}; " \
  158 + "else " \
  159 + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
  160 + "booti ${loadaddr} - ${fdt_addr}; " \
  161 + "else " \
  162 + "echo WARN: Cannot load the DT; " \
  163 + "fi; " \
  164 + "fi;\0"
  165 +
  166 +#define CONFIG_BOOTCOMMAND \
  167 + "mmc dev ${mmcdev}; if mmc rescan; then " \
  168 + "if run loadbootscript; then " \
  169 + "run bootscript; " \
  170 + "else " \
  171 + "if run loadimage; then " \
  172 + "run mmcboot; " \
  173 + "else run netboot; " \
  174 + "fi; " \
  175 + "fi; " \
  176 + "fi;"
  177 +#endif
  178 +
  179 +/* Link Definitions */
  180 +#define CONFIG_LOADADDR 0x40480000
  181 +
  182 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  183 +
  184 +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
  185 +#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
  186 +#define CONFIG_SYS_INIT_SP_OFFSET \
  187 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  188 +#define CONFIG_SYS_INIT_SP_ADDR \
  189 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  190 +
  191 +#define CONFIG_ENV_OVERWRITE
  192 +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  193 +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
  194 +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
  195 +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
  196 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  197 +#endif
  198 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
  199 +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
  200 +
  201 +/* Size of malloc() pool */
  202 +#define CONFIG_SYS_MALLOC_LEN SZ_32M
  203 +
  204 +#define CONFIG_SYS_SDRAM_BASE 0x40000000
  205 +#define PHYS_SDRAM 0x40000000
  206 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
  207 +
  208 +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
  209 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
  210 +
  211 +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
  212 +
  213 +/* Monitor Command Prompt */
  214 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  215 +#define CONFIG_SYS_CBSIZE 2048
  216 +#define CONFIG_SYS_MAXARGS 64
  217 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  218 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  219 + sizeof(CONFIG_SYS_PROMPT) + 16)
  220 +
  221 +#define CONFIG_IMX_BOOTAUX
  222 +
  223 +/* USDHC */
  224 +#define CONFIG_FSL_USDHC
  225 +
  226 +#ifdef CONFIG_TARGET_IMX8MM_DDR4_EVK
  227 +#define CONFIG_SYS_FSL_USDHC_NUM 1
  228 +#else
  229 +#define CONFIG_SYS_FSL_USDHC_NUM 2
  230 +#endif
  231 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
  232 +
  233 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  234 +
  235 +#ifdef CONFIG_FSL_FSPI
  236 +#define FSL_FSPI_FLASH_SIZE SZ_32M
  237 +#define FSL_FSPI_FLASH_NUM 1
  238 +#define FSPI0_BASE_ADDR 0x30bb0000
  239 +#define FSPI0_AMBA_BASE 0x0
  240 +#define CONFIG_FSPI_QUAD_SUPPORT
  241 +
  242 +#define CONFIG_SYS_FSL_FSPI_AHB
  243 +#endif
  244 +
  245 +#ifdef CONFIG_NAND_MXS
  246 +#define CONFIG_CMD_NAND_TRIMFFS
  247 +
  248 +/* NAND stuff */
  249 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  250 +#define CONFIG_SYS_NAND_BASE 0x20000000
  251 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  252 +#define CONFIG_SYS_NAND_ONFI_DETECTION
  253 +#define CONFIG_SYS_NAND_USE_FLASH_BBT
  254 +#endif /* CONFIG_NAND_MXS */
  255 +
  256 +#define CONFIG_SYS_I2C_SPEED 100000
  257 +
  258 +#endif