imx: mx6sxsabreauto: enable more dm drivers

Enable MMC/I2C/GPIO/PMIC/REGULATOR/PCA953X DM drivers for mx6sxsabreauto board. Drop non-DM code. Note: The i.MX DM drivers has such dependency. MXC GPIO -> MXC I2C -> PFUZE/REGULATOR MXC GPIO -> PCA953X MXC GPIO -> FSL_USDHC So the drivers needs to be enabled all to avoid compiling error. The uboot dm tree log: => dm tree Class Probed Name ---------------------------------------- root [ + ] root_driver thermal [ ] |-- imx_thermal simple_bus [ + ] |-- soc simple_bus [ + ] | |-- aips-bus@02000000 simple_bus [ ] | | |-- spba-bus@02000000 gpio [ + ] | | |-- gpio@0209c000 gpio [ + ] | | |-- gpio@020a0000 gpio [ + ] | | |-- gpio@020a4000 gpio [ + ] | | |-- gpio@020a8000 gpio [ + ] | | |-- gpio@020ac000 gpio [ + ] | | |-- gpio@020b0000 gpio [ + ] | | |-- gpio@020b4000 simple_bus [ ] | | |-- anatop@020c8000 simple_bus [ ] | | |-- snvs@020cc000 pinctrl [ + ] | | `-- iomuxc@020e0000 pinconfig [ + ] | | `-- imx6x-sabreauto pinconfig [ + ] | | |-- i2c2grp-1 pinconfig [ + ] | | |-- i2c3grp-2 pinconfig [ ] | | |-- uart1grp pinconfig [ + ] | | |-- usdhc3grp pinconfig [ ] | | |-- usdhc3grp-100mhz pinconfig [ ] | | |-- usdhc3grp-200mhz pinconfig [ + ] | | |-- usdhc4grp pinconfig [ + ] | | `-- vccsd3grp simple_bus [ + ] | |-- aips-bus@02100000 mmc [ + ] | | |-- usdhc@02198000 mmc [ + ] | | |-- usdhc@0219c000 i2c [ + ] | | |-- i2c@021a4000 i2c_generic [ + ] | | | |-- generic_8 i2c_generic [ + ] | | | `-- generic_4e i2c [ + ] | | `-- i2c@021a8000 gpio [ + ] | | |-- gpio@30 gpio [ + ] | | `-- gpio@32 simple_bus [ ] | `-- aips-bus@02200000 simple_bus [ ] | `-- spba-bus@02200000 simple_bus [ + ] `-- regulators regulator [ + ] `-- regulator@0 Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>

imx: mx6sxsabreauto: enable more dm drivers
Enable MMC/I2C/GPIO/PMIC/REGULATOR/PCA953X DM drivers for mx6sxsabreauto board. Drop non-DM code. Note: The i.MX DM drivers has such dependency. MXC GPIO -> MXC I2C -> PFUZE/REGULATOR MXC GPIO -> PCA953X MXC GPIO -> FSL_USDHC So the drivers needs to be enabled all to avoid compiling error. The uboot dm tree log: => dm tree Class Probed Name ---------------------------------------- root [ + ] root_driver thermal [ ] |-- imx_thermal simple_bus [ + ] |-- soc simple_bus [ + ] | |-- aips-bus@02000000 simple_bus [ ] | | |-- spba-bus@02000000 gpio [ + ] | | |-- gpio@0209c000 gpio [ + ] | | |-- gpio@020a0000 gpio [ + ] | | |-- gpio@020a4000 gpio [ + ] | | |-- gpio@020a8000 gpio [ + ] | | |-- gpio@020ac000 gpio [ + ] | | |-- gpio@020b0000 gpio [ + ] | | |-- gpio@020b4000 simple_bus [ ] | | |-- anatop@020c8000 simple_bus [ ] | | |-- snvs@020cc000 pinctrl [ + ] | | `-- iomuxc@020e0000 pinconfig [ + ] | | `-- imx6x-sabreauto pinconfig [ + ] | | |-- i2c2grp-1 pinconfig [ + ] | | |-- i2c3grp-2 pinconfig [ ] | | |-- uart1grp pinconfig [ + ] | | |-- usdhc3grp pinconfig [ ] | | |-- usdhc3grp-100mhz pinconfig [ ] | | |-- usdhc3grp-200mhz pinconfig [ + ] | | |-- usdhc4grp pinconfig [ + ] | | `-- vccsd3grp simple_bus [ + ] | |-- aips-bus@02100000 mmc [ + ] | | |-- usdhc@02198000 mmc [ + ] | | |-- usdhc@0219c000 i2c [ + ] | | |-- i2c@021a4000 i2c_generic [ + ] | | | |-- generic_8 i2c_generic [ + ] | | | `-- generic_4e i2c [ + ] | | `-- i2c@021a8000 gpio [ + ] | | |-- gpio@30 gpio [ + ] | | `-- gpio@32 simple_bus [ ] | `-- aips-bus@02200000 simple_bus [ ] | `-- spba-bus@02200000 simple_bus [ + ] `-- regulators regulator [ + ] `-- regulator@0 Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
Peng Fan · Stefano Babic · Eric Lee · Eric Lee · Eric Lee · Eric Lee
1 parent caf2578f65
Showing 3 changed files with 69 additions and 209 deletions Side-by-side Diff
board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
configs/mx6sxsabreauto_defconfig
include/configs/mx6sxsabreauto.h
@@ -16,12 +16,9 @@
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/imx-common/boot_mode.h>
 #include <asm/io.h>
-#include <asm/imx-common/mxc_i2c.h>
 #include <linux/sizes.h>
 #include <common.h>
 #include <fsl_esdhc.h>
-#include <mmc.h>
-#include <i2c.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <power/pmic.h>
@@ -37,15 +34,6 @@
 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
-	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
-	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
-	PAD_CTL_ODE)
-
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
 	PAD_CTL_SPEED_HIGH   |                                   \
 	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
  
@@ -56,54 +44,11 @@
 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
 	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  
-#define I2C_PMIC	1
-
 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
 			PAD_CTL_SRE_FAST)
 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  
-/*Define for building port exp gpio, pin starts from 0*/
-#define PORTEXP_IO_NR(chip, pin) \
-	((chip << 5) + pin)
-
-/*Get the chip addr from a ioexp gpio*/
-#define PORTEXP_IO_TO_CHIP(gpio_nr) \
-	(gpio_nr >> 5)
-
-/*Get the pin number from a ioexp gpio*/
-#define PORTEXP_IO_TO_PIN(gpio_nr) \
-	(gpio_nr & 0x1f)
-
-#define CPU_PER_RST_B	PORTEXP_IO_NR(0x30, 4)
-#define STEER_ENET		PORTEXP_IO_NR(0x32, 2)
-
-static int port_exp_direction_output(unsigned gpio, int value)
-{
-	int ret;
-
-	i2c_set_bus_num(2);
-	ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
-	if (ret)
-		return ret;
-
-	ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
-		(1 << PORTEXP_IO_TO_PIN(gpio)),
-		(PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
-
-	if (ret)
-		return ret;
-
-	ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
-		(1 << PORTEXP_IO_TO_PIN(gpio)),
-		(value << PORTEXP_IO_TO_PIN(gpio)));
-
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
@@ -116,41 +61,6 @@
 	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
  
-static iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
-	/* CD pin */
-	MX6_PAD_USB_H_DATA__GPIO7_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
-
-	/* RST_B, used for power reset cycle */
-	MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc4_pads[] = {
-	MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
-	/* CD pin */
-	MX6_PAD_USB_H_STROBE__GPIO7_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
 static iomux_v3_cfg_t const fec2_pads[] = {
 	MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  
  
  
@@ -217,43 +127,44 @@
 	return 0;
 }
  
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* I2C2 for PMIC */
-struct i2c_pads_info i2c_pad_info2 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC,
-		.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
-		.gp = IMX_GPIO_NR(1, 2),
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC,
-		.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
-		.gp = IMX_GPIO_NR(1, 3),
-	},
-};
-
-/* I2C3 for IO Expander */
-struct i2c_pads_info i2c_pad_info3 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_KEY_COL4__I2C3_SCL | PC,
-		.gpio_mode = MX6_PAD_KEY_COL4__GPIO2_IO_14 | PC,
-		.gp = IMX_GPIO_NR(2, 14),
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_KEY_ROW4__I2C3_SDA | PC,
-		.gpio_mode = MX6_PAD_KEY_ROW4__GPIO2_IO_19 | PC,
-		.gp = IMX_GPIO_NR(2, 19),
-	},
-};
-
 int power_init_board(void)
 {
-	struct pmic *p;
+	struct udevice *dev;
+	int ret;
+	u32 dev_id, rev_id, i;
+	u32 switch_num = 6;
+	u32 offset = PFUZE100_SW1CMODE;
  
-	p = pfuze_common_init(I2C_PMIC);
-	if (!p)
-		return -ENODEV;
+	ret = pmic_get("pfuze100", &dev);
+	if (ret == -ENODEV)
+		return 0;
  
+	if (ret != 0)
+		return ret;
+
+	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
+	printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+
+	/* Init mode to APS_PFM */
+	pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
+
+	for (i = 0; i < switch_num - 1; i++)
+		pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
+
+	/* set SW1AB staby volatage 0.975V */
+	pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
+
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
+
+	/* set SW1C staby volatage 1.10V */
+	pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20);
+
+	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+	pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
+
 	return 0;
 }
  
@@ -307,78 +218,6 @@
 	return 0;
 }
  
-static struct fsl_esdhc_cfg usdhc_cfg[3] = {
-	{USDHC3_BASE_ADDR},
-	{USDHC4_BASE_ADDR},
-};
-
-#define USDHC3_CD_GPIO	IMX_GPIO_NR(7, 10)
-#define USDHC3_RST_GPIO	IMX_GPIO_NR(2, 11)
-#define USDHC4_CD_GPIO	IMX_GPIO_NR(7, 11)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret = 0;
-
-	switch (cfg->esdhc_base) {
-	case USDHC3_BASE_ADDR:
-		ret = !gpio_get_value(USDHC3_CD_GPIO);
-		break;
-	case USDHC4_BASE_ADDR:
-		ret = !gpio_get_value(USDHC4_CD_GPIO);
-		break;
-	}
-
-	return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	int i, ret;
-
-	/*
-	 * According to the board_mmc_init() the following map is done:
-	 * (U-Boot device node)    (Physical Port)
-	 * mmc0                    USDHC3
-	 * mmc1                    USDHC4
-	 */
-	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-		switch (i) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-			gpio_direction_input(USDHC3_CD_GPIO);
-
-			/* This starts a power cycle for UHS-I. Need to set steer to B0 to A*/
-			gpio_direction_output(USDHC3_RST_GPIO, 0);
-			udelay(1000); /* need 1ms at least */
-			gpio_direction_output(USDHC3_RST_GPIO, 1);
-
-			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-			break;
-		case 1:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
-			gpio_direction_input(USDHC4_CD_GPIO);
-			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers"
-				"(%d) than supported by the board\n", i + 1);
-			return -EINVAL;
-			}
-
-			ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-			if (ret) {
-				printf("Warning: failed to initialize mmc dev %d\n", i);
-				return ret;
-			}
-	}
-
-	return 0;
-}
-
 #ifdef CONFIG_FSL_QSPI
  
 #define QSPI_PAD_CTRL1	\
  
  
  
  
  
  
@@ -450,21 +289,36 @@
  
 int board_init(void)
 {
+	struct gpio_desc desc;
+	int ret;
+
 	/* Address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  
-#ifdef CONFIG_SYS_I2C_MXC
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
-#endif
+	ret = dm_gpio_lookup_name("gpio@30_4", &desc);
+	if (ret)
+		return ret;
  
+	ret = dm_gpio_request(&desc, "cpu_per_rst_b");
+	if (ret)
+		return ret;
 	/* Reset CPU_PER_RST_B signal for enet phy and PCIE */
-	port_exp_direction_output(CPU_PER_RST_B, 0);
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
 	udelay(500);
-	port_exp_direction_output(CPU_PER_RST_B, 1);
+	dm_gpio_set_value(&desc, 1);
  
+	ret = dm_gpio_lookup_name("gpio@32_2", &desc);
+	if (ret)
+		return ret;
+
+	ret = dm_gpio_request(&desc, "steer_enet");
+	if (ret)
+		return ret;
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+	udelay(500);
 	/* Set steering signal to L for selecting B0 */
-	port_exp_direction_output(STEER_ENET, 0);
+	dm_gpio_set_value(&desc, 0);
  
 #ifdef CONFIG_USB_EHCI_MX6
 	setup_usb();
@@ -19,17 +19,30 @@
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
+# CONFIG_BLK is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
@@ -114,18 +114,11 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC3_BASE_ADDR
  
 /* I2C Configs */
-#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		  100000
-
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE100
-#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
  
 /* NAND flash command */
 #define CONFIG_CMD_NAND
...	...	@@ -16,12 +16,9 @@
16	16	#include <asm/imx-common/iomux-v3.h>
17	17	#include <asm/imx-common/boot_mode.h>
18	18	#include <asm/io.h>
19		-#include <asm/imx-common/mxc_i2c.h>
20	19	#include <linux/sizes.h>
21	20	#include <common.h>
22	21	#include <fsl_esdhc.h>
23		-#include <mmc.h>
24		-#include <i2c.h>
25	22	#include <miiphy.h>
26	23	#include <netdev.h>
27	24	#include <power/pmic.h>
...	...	@@ -37,15 +34,6 @@
37	34	PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
38	35	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
39	36
40		-#define USDHC_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
41		- PAD_CTL_PUS_22K_UP \| PAD_CTL_SPEED_LOW \| \
42		- PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
43		-
44		-#define I2C_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
45		- PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
46		- PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \
47		- PAD_CTL_ODE)
48		-
49	37	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_PUE \| \
50	38	PAD_CTL_SPEED_HIGH \| \
51	39	PAD_CTL_DSE_48ohm \| PAD_CTL_SRE_FAST)
52	40
...	...	@@ -56,54 +44,11 @@
56	44	#define ENET_RX_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
57	45	PAD_CTL_SPEED_HIGH \| PAD_CTL_SRE_FAST)
58	46
59		-#define I2C_PMIC 1
60		-
61	47	#define GPMI_PAD_CTRL0 (PAD_CTL_PKE \| PAD_CTL_PUE \| PAD_CTL_PUS_100K_UP)
62	48	#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm \| PAD_CTL_SPEED_MED \| \
63	49	PAD_CTL_SRE_FAST)
64	50	#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 \| GPMI_PAD_CTRL1)
65	51
66		-/Define for building port exp gpio, pin starts from 0/
67		-#define PORTEXP_IO_NR(chip, pin) \
68		- ((chip << 5) + pin)
69		-
70		-/Get the chip addr from a ioexp gpio/
71		-#define PORTEXP_IO_TO_CHIP(gpio_nr) \
72		- (gpio_nr >> 5)
73		-
74		-/Get the pin number from a ioexp gpio/
75		-#define PORTEXP_IO_TO_PIN(gpio_nr) \
76		- (gpio_nr & 0x1f)
77		-
78		-#define CPU_PER_RST_B PORTEXP_IO_NR(0x30, 4)
79		-#define STEER_ENET PORTEXP_IO_NR(0x32, 2)
80		-
81		-static int port_exp_direction_output(unsigned gpio, int value)
82		-{
83		- int ret;
84		-
85		- i2c_set_bus_num(2);
86		- ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
87		- if (ret)
88		- return ret;
89		-
90		- ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
91		- (1 << PORTEXP_IO_TO_PIN(gpio)),
92		- (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
93		-
94		- if (ret)
95		- return ret;
96		-
97		- ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
98		- (1 << PORTEXP_IO_TO_PIN(gpio)),
99		- (value << PORTEXP_IO_TO_PIN(gpio)));
100		-
101		- if (ret)
102		- return ret;
103		-
104		- return 0;
105		-}
106		-
107	52	int dram_init(void)
108	53	{
109	54	gd->ram_size = imx_ddr_size();
...	...	@@ -116,41 +61,6 @@
116	61	MX6_PAD_GPIO1_IO05__UART1_RX \| MUX_PAD_CTRL(UART_PAD_CTRL),
117	62	};
118	63
119		-static iomux_v3_cfg_t const usdhc3_pads[] = {
120		- MX6_PAD_SD3_CLK__USDHC3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
121		- MX6_PAD_SD3_CMD__USDHC3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
122		- MX6_PAD_SD3_DATA0__USDHC3_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
123		- MX6_PAD_SD3_DATA1__USDHC3_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
124		- MX6_PAD_SD3_DATA2__USDHC3_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
125		- MX6_PAD_SD3_DATA3__USDHC3_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
126		- MX6_PAD_SD3_DATA4__USDHC3_DATA4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
127		- MX6_PAD_SD3_DATA5__USDHC3_DATA5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
128		- MX6_PAD_SD3_DATA6__USDHC3_DATA6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
129		- MX6_PAD_SD3_DATA7__USDHC3_DATA7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
130		-
131		- /* CD pin */
132		- MX6_PAD_USB_H_DATA__GPIO7_IO_10 \| MUX_PAD_CTRL(NO_PAD_CTRL),
133		-
134		- /* RST_B, used for power reset cycle */
135		- MX6_PAD_KEY_COL1__GPIO2_IO_11 \| MUX_PAD_CTRL(NO_PAD_CTRL),
136		-};
137		-
138		-static iomux_v3_cfg_t const usdhc4_pads[] = {
139		- MX6_PAD_SD4_CLK__USDHC4_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
140		- MX6_PAD_SD4_CMD__USDHC4_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
141		- MX6_PAD_SD4_DATA0__USDHC4_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
142		- MX6_PAD_SD4_DATA1__USDHC4_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
143		- MX6_PAD_SD4_DATA2__USDHC4_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
144		- MX6_PAD_SD4_DATA3__USDHC4_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
145		- MX6_PAD_SD4_DATA4__USDHC4_DATA4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
146		- MX6_PAD_SD4_DATA5__USDHC4_DATA5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
147		- MX6_PAD_SD4_DATA6__USDHC4_DATA6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
148		- MX6_PAD_SD4_DATA7__USDHC4_DATA7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
149		-
150		- /* CD pin */
151		- MX6_PAD_USB_H_STROBE__GPIO7_IO_11 \| MUX_PAD_CTRL(NO_PAD_CTRL),
152		-};
153		-
154	64	static iomux_v3_cfg_t const fec2_pads[] = {
155	65	MX6_PAD_ENET1_MDC__ENET2_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
156	66	MX6_PAD_ENET1_MDIO__ENET2_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL),
157	67
158	68
159	69
...	...	@@ -217,43 +127,44 @@
217	127	return 0;
218	128	}
219	129
220		-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
221		-/* I2C2 for PMIC */
222		-struct i2c_pads_info i2c_pad_info2 = {
223		- .scl = {
224		- .i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL \| PC,
225		- .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 \| PC,
226		- .gp = IMX_GPIO_NR(1, 2),
227		- },
228		- .sda = {
229		- .i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA \| PC,
230		- .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 \| PC,
231		- .gp = IMX_GPIO_NR(1, 3),
232		- },
233		-};
234		-
235		-/* I2C3 for IO Expander */
236		-struct i2c_pads_info i2c_pad_info3 = {
237		- .scl = {
238		- .i2c_mode = MX6_PAD_KEY_COL4__I2C3_SCL \| PC,
239		- .gpio_mode = MX6_PAD_KEY_COL4__GPIO2_IO_14 \| PC,
240		- .gp = IMX_GPIO_NR(2, 14),
241		- },
242		- .sda = {
243		- .i2c_mode = MX6_PAD_KEY_ROW4__I2C3_SDA \| PC,
244		- .gpio_mode = MX6_PAD_KEY_ROW4__GPIO2_IO_19 \| PC,
245		- .gp = IMX_GPIO_NR(2, 19),
246		- },
247		-};
248		-
249	130	int power_init_board(void)
250	131	{
251		- struct pmic *p;
	132	+ struct udevice *dev;
	133	+ int ret;
	134	+ u32 dev_id, rev_id, i;
	135	+ u32 switch_num = 6;
	136	+ u32 offset = PFUZE100_SW1CMODE;
252	137
253		- p = pfuze_common_init(I2C_PMIC);
254		- if (!p)
255		- return -ENODEV;
	138	+ ret = pmic_get("pfuze100", &dev);
	139	+ if (ret == -ENODEV)
	140	+ return 0;
256	141
	142	+ if (ret != 0)
	143	+ return ret;
	144	+
	145	+ dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
	146	+ rev_id = pmic_reg_read(dev, PFUZE100_REVID);
	147	+ printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
	148	+
	149	+
	150	+ /* Init mode to APS_PFM */
	151	+ pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
	152	+
	153	+ for (i = 0; i < switch_num - 1; i++)
	154	+ pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
	155	+
	156	+ /* set SW1AB staby volatage 0.975V */
	157	+ pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
	158	+
	159	+ /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
	160	+ pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
	161	+
	162	+ /* set SW1C staby volatage 1.10V */
	163	+ pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20);
	164	+
	165	+ /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
	166	+ pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
	167	+
257	168	return 0;
258	169	}
259	170
...	...	@@ -307,78 +218,6 @@
307	218	return 0;
308	219	}
309	220
310		-static struct fsl_esdhc_cfg usdhc_cfg[3] = {
311		- {USDHC3_BASE_ADDR},
312		- {USDHC4_BASE_ADDR},
313		-};
314		-
315		-#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 10)
316		-#define USDHC3_RST_GPIO IMX_GPIO_NR(2, 11)
317		-#define USDHC4_CD_GPIO IMX_GPIO_NR(7, 11)
318		-
319		-int board_mmc_getcd(struct mmc *mmc)
320		-{
321		- struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
322		- int ret = 0;
323		-
324		- switch (cfg->esdhc_base) {
325		- case USDHC3_BASE_ADDR:
326		- ret = !gpio_get_value(USDHC3_CD_GPIO);
327		- break;
328		- case USDHC4_BASE_ADDR:
329		- ret = !gpio_get_value(USDHC4_CD_GPIO);
330		- break;
331		- }
332		-
333		- return ret;
334		-}
335		-
336		-int board_mmc_init(bd_t *bis)
337		-{
338		- int i, ret;
339		-
340		- /*
341		- * According to the board_mmc_init() the following map is done:
342		- * (U-Boot device node) (Physical Port)
343		- * mmc0 USDHC3
344		- * mmc1 USDHC4
345		- */
346		- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
347		- switch (i) {
348		- case 0:
349		- imx_iomux_v3_setup_multiple_pads(
350		- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
351		- gpio_direction_input(USDHC3_CD_GPIO);
352		-
353		- /* This starts a power cycle for UHS-I. Need to set steer to B0 to A*/
354		- gpio_direction_output(USDHC3_RST_GPIO, 0);
355		- udelay(1000); /* need 1ms at least */
356		- gpio_direction_output(USDHC3_RST_GPIO, 1);
357		-
358		- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
359		- break;
360		- case 1:
361		- imx_iomux_v3_setup_multiple_pads(
362		- usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
363		- gpio_direction_input(USDHC4_CD_GPIO);
364		- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
365		- break;
366		- default:
367		- printf("Warning: you configured more USDHC controllers"
368		- "(%d) than supported by the board\n", i + 1);
369		- return -EINVAL;
370		- }
371		-
372		- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
373		- if (ret) {
374		- printf("Warning: failed to initialize mmc dev %d\n", i);
375		- return ret;
376		- }
377		- }
378		-
379		- return 0;
380		-}
381		-
382	221	#ifdef CONFIG_FSL_QSPI
383	222
384	223	#define QSPI_PAD_CTRL1 \
385	224
386	225
387	226
388	227
389	228
390	229
...	...	@@ -450,21 +289,36 @@
450	289
451	290	int board_init(void)
452	291	{
	292	+ struct gpio_desc desc;
	293	+ int ret;
	294	+
453	295	/* Address of boot parameters */
454	296	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
455	297
456		-#ifdef CONFIG_SYS_I2C_MXC
457		- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
458		- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
459		-#endif
	298	+ ret = dm_gpio_lookup_name("gpio@30_4", &desc);
	299	+ if (ret)
	300	+ return ret;
460	301
	302	+ ret = dm_gpio_request(&desc, "cpu_per_rst_b");
	303	+ if (ret)
	304	+ return ret;
461	305	/* Reset CPU_PER_RST_B signal for enet phy and PCIE */
462		- port_exp_direction_output(CPU_PER_RST_B, 0);
	306	+ dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
463	307	udelay(500);
464		- port_exp_direction_output(CPU_PER_RST_B, 1);
	308	+ dm_gpio_set_value(&desc, 1);
465	309
	310	+ ret = dm_gpio_lookup_name("gpio@32_2", &desc);
	311	+ if (ret)
	312	+ return ret;
	313	+
	314	+ ret = dm_gpio_request(&desc, "steer_enet");
	315	+ if (ret)
	316	+ return ret;
	317	+
	318	+ dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
	319	+ udelay(500);
466	320	/* Set steering signal to L for selecting B0 */
467		- port_exp_direction_output(STEER_ENET, 0);
	321	+ dm_gpio_set_value(&desc, 0);
468	322
469	323	#ifdef CONFIG_USB_EHCI_MX6
470	324	setup_usb();
...	...	@@ -19,17 +19,30 @@
19	19	CONFIG_CMD_PING=y
20	20	CONFIG_CMD_CACHE=y
21	21	CONFIG_CMD_TIME=y
	22	+CONFIG_CMD_REGULATOR=y
22	23	CONFIG_CMD_EXT2=y
23	24	CONFIG_CMD_EXT4=y
24	25	CONFIG_CMD_EXT4_WRITE=y
25	26	CONFIG_CMD_FAT=y
26	27	CONFIG_CMD_FS_GENERIC=y
27	28	CONFIG_OF_CONTROL=y
	29	+# CONFIG_BLK is not set
	30	+CONFIG_DM_GPIO=y
	31	+CONFIG_DM_PCA953X=y
	32	+CONFIG_DM_I2C=y
	33	+CONFIG_DM_MMC=y
	34	+# CONFIG_DM_MMC_OPS is not set
28	35	CONFIG_SPI_FLASH=y
29	36	CONFIG_SPI_FLASH_BAR=y
30	37	CONFIG_SPI_FLASH_STMICRO=y
31	38	CONFIG_PINCTRL=y
32	39	CONFIG_PINCTRL_IMX6=y
	40	+CONFIG_DM_PMIC=y
	41	+CONFIG_DM_PMIC_PFUZE100=y
	42	+CONFIG_DM_REGULATOR=y
	43	+CONFIG_DM_REGULATOR_PFUZE100=y
	44	+CONFIG_DM_REGULATOR_FIXED=y
	45	+CONFIG_DM_REGULATOR_GPIO=y
33	46	CONFIG_FSL_QSPI=y
34	47	CONFIG_USB=y
35	48	CONFIG_USB_STORAGE=y
...	...	@@ -114,18 +114,11 @@
114	114	#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
115	115
116	116	/* I2C Configs */
117		-#define CONFIG_SYS_I2C
118	117	#define CONFIG_SYS_I2C_MXC
119	118	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
120	119	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
121	120	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
122	121	#define CONFIG_SYS_I2C_SPEED 100000
123		-
124		-/* PMIC */
125		-#define CONFIG_POWER
126		-#define CONFIG_POWER_I2C
127		-#define CONFIG_POWER_PFUZE100
128		-#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
129	122
130	123	/* NAND flash command */
131	124	#define CONFIG_CMD_NAND