Eric Lee / smarc-uboot

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Commit e38b15b0619f9a8b869896229355808f494fb2ac

Authored by Tom Rini
2 parents 1ee30aeed4 c292adae17
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge branch 'master' of git://git.denx.de/u-boot-arm

Showing 48 changed files Side-by-side Diff

... ... @@ -426,6 +426,9 @@
426 426 config RMOBILE
427 427 bool "Renesas ARM SoCs"
428 428  
  429 +config TARGET_CM_FX6
  430 + bool "Support cm_fx6"
  431 +
429 432 config TARGET_S5P_GONI
430 433 bool "Support s5p_goni"
431 434  
... ... @@ -589,6 +592,7 @@
589 592 source "board/cm4008/Kconfig"
590 593 source "board/cm41xx/Kconfig"
591 594 source "board/compulab/cm_t335/Kconfig"
  595 +source "board/compulab/cm_fx6/Kconfig"
592 596 source "board/congatec/cgtqmx6eval/Kconfig"
593 597 source "board/creative/xfi3/Kconfig"
594 598 source "board/davedenx/qong/Kconfig"
arch/arm/cpu/armv7/mx6/clock.c
Diff comments   View file @ e38b15b
... ... @@ -36,6 +36,35 @@
36 36 }
37 37 #endif
38 38  
  39 +#ifdef CONFIG_NAND_MXS
  40 +void setup_gpmi_io_clk(u32 cfg)
  41 +{
  42 + /* Disable clocks per ERR007177 from MX6 errata */
  43 + clrbits_le32(&imx_ccm->CCGR4,
  44 + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  45 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  46 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  47 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  48 + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  49 +
  50 + clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  51 +
  52 + clrsetbits_le32(&imx_ccm->cs2cdr,
  53 + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  54 + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  55 + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  56 + cfg);
  57 +
  58 + setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  59 + setbits_le32(&imx_ccm->CCGR4,
  60 + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  61 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  62 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  63 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  64 + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  65 +}
  66 +#endif
  67 +
39 68 void enable_usboh3_clk(unsigned char enable)
40 69 {
41 70 u32 reg;
... ... @@ -49,6 +78,67 @@
49 78  
50 79 }
51 80  
  81 +#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
  82 +void enable_enet_clk(unsigned char enable)
  83 +{
  84 + u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
  85 +
  86 + if (enable)
  87 + setbits_le32(&imx_ccm->CCGR1, mask);
  88 + else
  89 + clrbits_le32(&imx_ccm->CCGR1, mask);
  90 +}
  91 +#endif
  92 +
  93 +#ifdef CONFIG_MXC_UART
  94 +void enable_uart_clk(unsigned char enable)
  95 +{
  96 + u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
  97 +
  98 + if (enable)
  99 + setbits_le32(&imx_ccm->CCGR5, mask);
  100 + else
  101 + clrbits_le32(&imx_ccm->CCGR5, mask);
  102 +}
  103 +#endif
  104 +
  105 +#ifdef CONFIG_SPI
  106 +/* spi_num can be from 0 - 4 */
  107 +int enable_cspi_clock(unsigned char enable, unsigned spi_num)
  108 +{
  109 + u32 mask;
  110 +
  111 + if (spi_num > 4)
  112 + return -EINVAL;
  113 +
  114 + mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2);
  115 + if (enable)
  116 + setbits_le32(&imx_ccm->CCGR1, mask);
  117 + else
  118 + clrbits_le32(&imx_ccm->CCGR1, mask);
  119 +
  120 + return 0;
  121 +}
  122 +#endif
  123 +
  124 +#ifdef CONFIG_MMC
  125 +int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
  126 +{
  127 + u32 mask;
  128 +
  129 + if (bus_num > 3)
  130 + return -EINVAL;
  131 +
  132 + mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
  133 + if (enable)
  134 + setbits_le32(&imx_ccm->CCGR6, mask);
  135 + else
  136 + clrbits_le32(&imx_ccm->CCGR6, mask);
  137 +
  138 + return 0;
  139 +}
  140 +#endif
  141 +
52 142 #ifdef CONFIG_SYS_I2C_MXC
53 143 /* i2c_num can be from 0 - 2 */
54 144 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
... ... @@ -509,6 +599,7 @@
509 599 struct anatop_regs *anatop_regs =
510 600 (struct anatop_regs *)ANATOP_BASE_ADDR;
511 601 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  602 + u32 lvds1_clk_sel;
512 603  
513 604 /*
514 605 * Here be dragons!
515 606  
516 607  
... ... @@ -518,17 +609,25 @@
518 609 * marked as ANATOP_MISC1 is actually documented in the PMU section
519 610 * of the datasheet as PMU_MISC1.
520 611 *
521   - * Switch LVDS clock source to SATA (0xb), disable clock INPUT and
522   - * enable clock OUTPUT. This is important for PCI express link that
523   - * is clocked from the i.MX6.
  612 + * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
  613 + * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
  614 + * for PCI express link that is clocked from the i.MX6.
524 615 */
525 616 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
526 617 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
527 618 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
  619 +#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
  620 +#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
  621 +
  622 + if (is_cpu_type(MXC_CPU_MX6SX))
  623 + lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
  624 + else
  625 + lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
  626 +
528 627 clrsetbits_le32(&anatop_regs->ana_misc1,
529 628 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
530 629 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
531   - ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);
  630 + ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
532 631  
533 632 /* PCIe reference clock sourced from AXI. */
534 633 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
arch/arm/cpu/armv7/mx6/ddr.c
Diff comments   View file @ e38b15b
... ... @@ -184,18 +184,18 @@
184 184 */
185 185 #define MR(val, ba, cmd, cs1) \
186 186 ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
187   -void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
188   - const struct mx6_mmdc_calibration *c,
189   - const struct mx6_ddr3_cfg *m)
  187 +void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
  188 + const struct mx6_mmdc_calibration *calib,
  189 + const struct mx6_ddr3_cfg *ddr3_cfg)
190 190 {
191 191 volatile struct mmdc_p_regs *mmdc0;
192 192 volatile struct mmdc_p_regs *mmdc1;
193   - u32 reg;
  193 + u32 val;
194 194 u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
195 195 u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
196 196 u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
197 197 u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
198   - u16 CS0_END;
  198 + u16 cs0_end;
199 199 u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
200 200 u8 coladdr;
201 201 int clkper; /* clock period in picoseconds */
202 202  
203 203  
... ... @@ -215,13 +215,12 @@
215 215 clock = 400;
216 216 tcwl = 3;
217 217 }
218   - clkper = (1000*1000)/clock; /* ps */
  218 + clkper = (1000 * 1000) / clock; /* pico seconds */
219 219 todtlon = tcwl;
220 220 taxpd = tcwl;
221 221 tanpd = tcwl;
222   - tcwl = tcwl;
223 222  
224   - switch (m->density) {
  223 + switch (ddr3_cfg->density) {
225 224 case 1: /* 1Gb per chip */
226 225 trfc = DIV_ROUND_UP(110000, clkper) - 1;
227 226 txs = DIV_ROUND_UP(120000, clkper) - 1;
228 227  
229 228  
230 229  
231 230  
232 231  
233 232  
234 233  
235 234  
236 235  
237 236  
238 237  
239 238  
240 239  
241 240  
242 241  
243 242  
244 243  
245 244  
246 245  
247 246  
... ... @@ -240,80 +239,82 @@
240 239 break;
241 240 default:
242 241 /* invalid density */
243   - printf("invalid chip density\n");
  242 + puts("invalid chip density\n");
244 243 hang();
245 244 break;
246 245 }
247 246 txpr = txs;
248 247  
249   - switch (m->mem_speed) {
  248 + switch (ddr3_cfg->mem_speed) {
250 249 case 800:
251   - txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
252   - tcke = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
253   - if (m->pagesz == 1) {
  250 + txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
  251 + tcke = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
  252 + if (ddr3_cfg->pagesz == 1) {
254 253 tfaw = DIV_ROUND_UP(40000, clkper) - 1;
255   - trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
  254 + trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
256 255 } else {
257 256 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
258   - trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
  257 + trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
259 258 }
260 259 break;
261 260 case 1066:
262   - txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
263   - tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
264   - if (m->pagesz == 1) {
  261 + txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
  262 + tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1;
  263 + if (ddr3_cfg->pagesz == 1) {
265 264 tfaw = DIV_ROUND_UP(37500, clkper) - 1;
266   - trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
  265 + trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
267 266 } else {
268 267 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
269   - trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
  268 + trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
270 269 }
271 270 break;
272 271 case 1333:
273   - txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
274   - tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
275   - if (m->pagesz == 1) {
  272 + txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1;
  273 + tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1;
  274 + if (ddr3_cfg->pagesz == 1) {
276 275 tfaw = DIV_ROUND_UP(30000, clkper) - 1;
277   - trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
  276 + trrd = DIV_ROUND_UP(MAX(4 * clkper, 6000), clkper) - 1;
278 277 } else {
279 278 tfaw = DIV_ROUND_UP(45000, clkper) - 1;
280   - trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
  279 + trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
281 280 }
282 281 break;
283 282 case 1600:
284   - txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
285   - tcke = DIV_ROUND_UP(MAX(3*clkper, 5000), clkper) - 1;
286   - if (m->pagesz == 1) {
  283 + txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1;
  284 + tcke = DIV_ROUND_UP(MAX(3 * clkper, 5000), clkper) - 1;
  285 + if (ddr3_cfg->pagesz == 1) {
287 286 tfaw = DIV_ROUND_UP(30000, clkper) - 1;
288   - trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
  287 + trrd = DIV_ROUND_UP(MAX(4 * clkper, 6000), clkper) - 1;
289 288 } else {
290 289 tfaw = DIV_ROUND_UP(40000, clkper) - 1;
291   - trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
  290 + trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
292 291 }
293 292 break;
294 293 default:
295   - printf("invalid memory speed\n");
  294 + puts("invalid memory speed\n");
296 295 hang();
297 296 break;
298 297 }
299   - txpdll = DIV_ROUND_UP(MAX(10*clkper, 24000), clkper) - 1;
300   - tcl = DIV_ROUND_UP(m->trcd, clkper/10) - 3;
301   - tcksre = DIV_ROUND_UP(MAX(5*clkper, 10000), clkper);
302   - tcksrx = tcksre;
  298 + txpdll = DIV_ROUND_UP(MAX(10 * clkper, 24000), clkper) - 1;
  299 + tcksre = DIV_ROUND_UP(MAX(5 * clkper, 10000), clkper);
303 300 taonpd = DIV_ROUND_UP(2000, clkper) - 1;
  301 + tcksrx = tcksre;
304 302 taofpd = taonpd;
305   - trp = DIV_ROUND_UP(m->trcd, clkper/10) - 1;
  303 + twr = DIV_ROUND_UP(15000, clkper) - 1;
  304 + tmrd = DIV_ROUND_UP(MAX(12 * clkper, 15000), clkper) - 1;
  305 + trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
  306 + tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
  307 + tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
  308 + trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
  309 + twtr = ROUND(MAX(4 * clkper, 7500) / clkper, 1) - 1;
306 310 trcd = trp;
307   - trc = DIV_ROUND_UP(m->trcmin, clkper/10) - 1;
308   - tras = DIV_ROUND_UP(m->trasmin, clkper/10) - 1;
309   - twr = DIV_ROUND_UP(15000, clkper) - 1;
310   - tmrd = DIV_ROUND_UP(MAX(12*clkper, 15000), clkper) - 1;
311   - twtr = ROUND(MAX(4*clkper, 7500)/clkper, 1) - 1;
312 311 trtp = twtr;
313   - CS0_END = ((4*i->cs_density) <= 120) ? (4*i->cs_density)+7 : 127;
314   - debug("density:%d Gb (%d Gb per chip)\n", i->cs_density, m->density);
  312 + cs0_end = 4 * sysinfo->cs_density - 1;
  313 +
  314 + debug("density:%d Gb (%d Gb per chip)\n",
  315 + sysinfo->cs_density, ddr3_cfg->density);
315 316 debug("clock: %dMHz (%d ps)\n", clock, clkper);
316   - debug("memspd:%d\n", m->mem_speed);
  317 + debug("memspd:%d\n", ddr3_cfg->mem_speed);
317 318 debug("tcke=%d\n", tcke);
318 319 debug("tcksrx=%d\n", tcksrx);
319 320 debug("tcksre=%d\n", tcksre);
... ... @@ -340,11 +341,11 @@
340 341 debug("twtr=%d\n", twtr);
341 342 debug("trrd=%d\n", trrd);
342 343 debug("txpr=%d\n", txpr);
343   - debug("CS0_END=%d\n", CS0_END);
344   - debug("ncs=%d\n", i->ncs);
345   - debug("Rtt_wr=%d\n", i->rtt_wr);
346   - debug("Rtt_nom=%d\n", i->rtt_nom);
347   - debug("SRT=%d\n", m->SRT);
  344 + debug("cs0_end=%d\n", cs0_end);
  345 + debug("ncs=%d\n", sysinfo->ncs);
  346 + debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
  347 + debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
  348 + debug("SRT=%d\n", ddr3_cfg->SRT);
348 349 debug("tcl=%d\n", tcl);
349 350 debug("twr=%d\n", twr);
350 351  
351 352  
352 353  
353 354  
354 355  
355 356  
356 357  
357 358  
358 359  
359 360  
360 361  
361 362  
362 363  
363 364  
364 365  
365 366  
366 367  
367 368  
368 369  
369 370  
370 371  
371 372  
372 373  
373 374  
... ... @@ -354,142 +355,136 @@
354 355 * see:
355 356 * appnote, ddr3 spreadsheet
356 357 */
357   - mmdc0->mpwldectrl0 = c->p0_mpwldectrl0;
358   - mmdc0->mpwldectrl1 = c->p0_mpwldectrl1;
359   - mmdc0->mpdgctrl0 = c->p0_mpdgctrl0;
360   - mmdc0->mpdgctrl1 = c->p0_mpdgctrl1;
361   - mmdc0->mprddlctl = c->p0_mprddlctl;
362   - mmdc0->mpwrdlctl = c->p0_mpwrdlctl;
363   - if (i->dsize > 1) {
364   - mmdc1->mpwldectrl0 = c->p1_mpwldectrl0;
365   - mmdc1->mpwldectrl1 = c->p1_mpwldectrl1;
366   - mmdc1->mpdgctrl0 = c->p1_mpdgctrl0;
367   - mmdc1->mpdgctrl1 = c->p1_mpdgctrl1;
368   - mmdc1->mprddlctl = c->p1_mprddlctl;
369   - mmdc1->mpwrdlctl = c->p1_mpwrdlctl;
  358 + mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
  359 + mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
  360 + mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
  361 + mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
  362 + mmdc0->mprddlctl = calib->p0_mprddlctl;
  363 + mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
  364 + if (sysinfo->dsize > 1) {
  365 + mmdc1->mpwldectrl0 = calib->p1_mpwldectrl0;
  366 + mmdc1->mpwldectrl1 = calib->p1_mpwldectrl1;
  367 + mmdc1->mpdgctrl0 = calib->p1_mpdgctrl0;
  368 + mmdc1->mpdgctrl1 = calib->p1_mpdgctrl1;
  369 + mmdc1->mprddlctl = calib->p1_mprddlctl;
  370 + mmdc1->mpwrdlctl = calib->p1_mpwrdlctl;
370 371 }
371 372  
372 373 /* Read data DQ Byte0-3 delay */
373   - mmdc0->mprddqby0dl = (u32)0x33333333;
374   - mmdc0->mprddqby1dl = (u32)0x33333333;
375   - if (i->dsize > 0) {
376   - mmdc0->mprddqby2dl = (u32)0x33333333;
377   - mmdc0->mprddqby3dl = (u32)0x33333333;
  374 + mmdc0->mprddqby0dl = 0x33333333;
  375 + mmdc0->mprddqby1dl = 0x33333333;
  376 + if (sysinfo->dsize > 0) {
  377 + mmdc0->mprddqby2dl = 0x33333333;
  378 + mmdc0->mprddqby3dl = 0x33333333;
378 379 }
379   - if (i->dsize > 1) {
380   - mmdc1->mprddqby0dl = (u32)0x33333333;
381   - mmdc1->mprddqby1dl = (u32)0x33333333;
382   - mmdc1->mprddqby2dl = (u32)0x33333333;
383   - mmdc1->mprddqby3dl = (u32)0x33333333;
  380 +
  381 + if (sysinfo->dsize > 1) {
  382 + mmdc1->mprddqby0dl = 0x33333333;
  383 + mmdc1->mprddqby1dl = 0x33333333;
  384 + mmdc1->mprddqby2dl = 0x33333333;
  385 + mmdc1->mprddqby3dl = 0x33333333;
384 386 }
385 387  
386 388 /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
387   - reg = (i->rtt_nom == 2) ? 0x00011117 : 0x00022227;
388   - mmdc0->mpodtctrl = reg;
389   - if (i->dsize > 1)
390   - mmdc1->mpodtctrl = reg;
  389 + val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
  390 + mmdc0->mpodtctrl = val;
  391 + if (sysinfo->dsize > 1)
  392 + mmdc1->mpodtctrl = val;
391 393  
392 394 /* complete calibration */
393   - reg = (1 << 11); /* Force measurement on delay-lines */
394   - mmdc0->mpmur0 = reg;
395   - if (i->dsize > 1)
396   - mmdc1->mpmur0 = reg;
  395 + val = (1 << 11); /* Force measurement on delay-lines */
  396 + mmdc0->mpmur0 = val;
  397 + if (sysinfo->dsize > 1)
  398 + mmdc1->mpmur0 = val;
397 399  
398 400 /* Step 1: configuration request */
399 401 mmdc0->mdscr = (u32)(1 << 15); /* config request */
400 402  
401 403 /* Step 2: Timing configuration */
402   - reg = (trfc << 24) | (txs << 16) | (txp << 13) | (txpdll << 9) |
403   - (tfaw << 4) | tcl;
404   - mmdc0->mdcfg0 = reg;
405   - reg = (trcd << 29) | (trp << 26) | (trc << 21) | (tras << 16) |
406   - (1 << 15) | /* trpa */
407   - (twr << 9) | (tmrd << 5) | tcwl;
408   - mmdc0->mdcfg1 = reg;
409   - reg = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
410   - mmdc0->mdcfg2 = reg;
411   - reg = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | (taxpd << 16) |
412   - (todtlon << 12) | (todt_idle_off << 4);
413   - mmdc0->mdotc = reg;
414   - mmdc0->mdasp = CS0_END; /* CS addressing */
  404 + mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
  405 + (txpdll << 9) | (tfaw << 4) | tcl;
  406 + mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
  407 + (tras << 16) | (1 << 15) /* trpa */ |
  408 + (twr << 9) | (tmrd << 5) | tcwl;
  409 + mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
  410 + mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
  411 + (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
  412 + mmdc0->mdasp = cs0_end; /* CS addressing */
415 413  
416 414 /* Step 3: Configure DDR type */
417   - reg = (i->cs1_mirror << 19) | (i->walat << 16) | (i->bi_on << 12) |
418   - (i->mif3_mode << 9) | (i->ralat << 6);
419   - mmdc0->mdmisc = reg;
  415 + mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
  416 + (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
  417 + (sysinfo->ralat << 6);
420 418  
421 419 /* Step 4: Configure delay while leaving reset */
422   - reg = (txpr << 16) | (i->sde_to_rst << 8) | (i->rst_to_cke << 0);
423   - mmdc0->mdor = reg;
  420 + mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
  421 + (sysinfo->rst_to_cke << 0);
424 422  
425 423 /* Step 5: Configure DDR physical parameters (density and burst len) */
426   - coladdr = m->coladdr;
427   - if (m->coladdr == 8) /* 8-bit COL is 0x3 */
  424 + coladdr = ddr3_cfg->coladdr;
  425 + if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
428 426 coladdr += 4;
429   - else if (m->coladdr == 12) /* 12-bit COL is 0x4 */
  427 + else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
430 428 coladdr += 1;
431   - reg = (m->rowaddr - 11) << 24 | /* ROW */
432   - (coladdr - 9) << 20 | /* COL */
433   - (1 << 19) | /* Burst Length = 8 for DDR3 */
434   - (i->dsize << 16); /* DDR data bus size */
435   - mmdc0->mdctl = reg;
  429 + mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
  430 + (coladdr - 9) << 20 | /* COL */
  431 + (1 << 19) | /* Burst Length = 8 for DDR3 */
  432 + (sysinfo->dsize << 16); /* DDR data bus size */
436 433  
437 434 /* Step 6: Perform ZQ calibration */
438   - reg = (u32)0xa1390001; /* one-time HW ZQ calib */
439   - mmdc0->mpzqhwctrl = reg;
440   - if (i->dsize > 1)
441   - mmdc1->mpzqhwctrl = reg;
  435 + val = 0xa1390001; /* one-time HW ZQ calib */
  436 + mmdc0->mpzqhwctrl = val;
  437 + if (sysinfo->dsize > 1)
  438 + mmdc1->mpzqhwctrl = val;
442 439  
443 440 /* Step 7: Enable MMDC with desired chip select */
444   - reg = mmdc0->mdctl |
445   - (1 << 31) | /* SDE_0 for CS0 */
446   - ((i->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
447   - mmdc0->mdctl = reg;
  441 + mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
  442 + ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
448 443  
449 444 /* Step 8: Write Mode Registers to Init DDR3 devices */
450   - for (cs = 0; cs < i->ncs; cs++) {
  445 + for (cs = 0; cs < sysinfo->ncs; cs++) {
451 446 /* MR2 */
452   - reg = (i->rtt_wr & 3) << 9 | (m->SRT & 1) << 7 |
  447 + val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
453 448 ((tcwl - 3) & 3) << 3;
454   - mmdc0->mdscr = (u32)MR(reg, 2, 3, cs);
  449 + mmdc0->mdscr = MR(val, 2, 3, cs);
455 450 /* MR3 */
456   - mmdc0->mdscr = (u32)MR(0, 3, 3, cs);
  451 + mmdc0->mdscr = MR(0, 3, 3, cs);
457 452 /* MR1 */
458   - reg = ((i->rtt_nom & 1) ? 1 : 0) << 2 |
459   - ((i->rtt_nom & 2) ? 1 : 0) << 6;
460   - mmdc0->mdscr = (u32)MR(reg, 1, 3, cs);
461   - reg = ((tcl - 1) << 4) | /* CAS */
  453 + val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
  454 + ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
  455 + mmdc0->mdscr = MR(val, 1, 3, cs);
  456 + /* MR0 */
  457 + val = ((tcl - 1) << 4) | /* CAS */
462 458 (1 << 8) | /* DLL Reset */
463 459 ((twr - 3) << 9); /* Write Recovery */
464   - /* MR0 */
465   - mmdc0->mdscr = (u32)MR(reg, 0, 3, cs);
  460 + mmdc0->mdscr = MR(val, 0, 3, cs);
466 461 /* ZQ calibration */
467   - reg = (1 << 10);
468   - mmdc0->mdscr = (u32)MR(reg, 0, 4, cs);
  462 + val = (1 << 10);
  463 + mmdc0->mdscr = MR(val, 0, 4, cs);
469 464 }
470 465  
471 466 /* Step 10: Power down control and self-refresh */
472   - reg = (tcke & 0x7) << 16 |
473   - 5 << 12 | /* PWDT_1: 256 cycles */
474   - 5 << 8 | /* PWDT_0: 256 cycles */
475   - 1 << 6 | /* BOTH_CS_PD */
476   - (tcksrx & 0x7) << 3 |
477   - (tcksre & 0x7);
478   - mmdc0->mdpdc = reg;
479   - mmdc0->mapsr = (u32)0x00011006; /* ADOPT power down enabled */
  467 + mmdc0->mdpdc = (tcke & 0x7) << 16 |
  468 + 5 << 12 | /* PWDT_1: 256 cycles */
  469 + 5 << 8 | /* PWDT_0: 256 cycles */
  470 + 1 << 7 | /* SLOW_PD */
  471 + 1 << 6 | /* BOTH_CS_PD */
  472 + (tcksrx & 0x7) << 3 |
  473 + (tcksre & 0x7);
  474 + mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
480 475  
481 476 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
482   - mmdc0->mpzqhwctrl = (u32)0xa1390003;
483   - if (i->dsize > 1)
484   - mmdc1->mpzqhwctrl = (u32)0xa1390003;
  477 + val = 0xa1390003;
  478 + mmdc0->mpzqhwctrl = val;
  479 + if (sysinfo->dsize > 1)
  480 + mmdc1->mpzqhwctrl = val;
485 481  
486 482 /* Step 12: Configure and activate periodic refresh */
487   - reg = (1 << 14) | /* REF_SEL: Periodic refresh cycles of 32kHz */
488   - (7 << 11); /* REFR: Refresh Rate - 8 refreshes */
489   - mmdc0->mdref = reg;
  483 + mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
  484 + (7 << 11); /* REFR: Refresh Rate - 8 refreshes */
490 485  
491 486 /* Step 13: Deassert config request - init complete */
492   - mmdc0->mdscr = (u32)0x00000000;
  487 + mmdc0->mdscr = 0x00000000;
493 488  
494 489 /* wait for auto-ZQ calibration to complete */
495 490 mdelay(1);
arch/arm/cpu/armv7/mx6/soc.c
Diff comments   View file @ e38b15b
... ... @@ -324,10 +324,10 @@
324 324 /* reserved value should start rom usb */
325 325 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
326 326 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
327   - {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
328   - {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
329   - {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
330   - {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
  327 + {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
  328 + {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
  329 + {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
  330 + {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
331 331 /* 4 bit bus width */
332 332 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
333 333 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
... ... @@ -429,6 +429,9 @@
429 429 writel(val, &iomux->gpr[11]);
430 430 }
431 431 #endif
  432 +
  433 + /* Must disable the L2 before changing the latency parameters */
  434 + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
432 435  
433 436 writel(0x132, &pl310->pl310_tag_latency_ctrl);
434 437 writel(0x132, &pl310->pl310_data_latency_ctrl);
arch/arm/dts/Makefile
Diff comments   View file @ e38b15b
... ... @@ -9,7 +9,6 @@
9 9 exynos5250-smdk5250.dtb \
10 10 exynos5420-smdk5420.dtb \
11 11 exynos5420-peach-pit.dtb
12   -dtb-$(CONFIG_MX6) += imx6q-sabreauto.dtb
13 12 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
14 13 tegra20-medcom-wide.dtb \
15 14 tegra20-paz00.dtb \
arch/arm/dts/imx6q-sabreauto.dts
View file @ e38b15b
1   -/*
2   - * Copyright 2012 Freescale Semiconductor, Inc.
3   - * Copyright 2011 Linaro Ltd.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -/dts-v1/;
9   -
10   -/ {
11   - model = "Freescale i.MX6 Quad SABRE Automotive Board";
12   - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
13   -};
arch/arm/include/asm/arch-mx6/clock.h
Diff comments   View file @ e38b15b
... ... @@ -52,13 +52,18 @@
52 52 u32 imx_get_uartclk(void);
53 53 u32 imx_get_fecclk(void);
54 54 unsigned int mxc_get_clock(enum mxc_clock clk);
  55 +void setup_gpmi_io_clk(u32 cfg);
55 56 void enable_ocotp_clk(unsigned char enable);
56 57 void enable_usboh3_clk(unsigned char enable);
  58 +void enable_uart_clk(unsigned char enable);
  59 +int enable_cspi_clock(unsigned char enable, unsigned spi_num);
  60 +int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
57 61 int enable_sata_clock(void);
58 62 int enable_pcie_clock(void);
59 63 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
60 64 int enable_spi_clk(unsigned char enable, unsigned spi_num);
61 65 void enable_ipu_clock(void);
62 66 int enable_fec_anatop_clock(enum enet_freq freq);
  67 +void enable_enet_clk(unsigned char enable);
63 68 #endif /* __ASM_ARCH_CLOCK_H */
arch/arm/include/asm/arch-mx6/imx-regs.h
Diff comments   View file @ e38b15b
... ... @@ -419,6 +419,19 @@
419 419 u32 gpr[14];
420 420 };
421 421  
  422 +struct gpc {
  423 + u32 cntr;
  424 + u32 pgr;
  425 + u32 imr1;
  426 + u32 imr2;
  427 + u32 imr3;
  428 + u32 imr4;
  429 + u32 isr1;
  430 + u32 isr2;
  431 + u32 isr3;
  432 + u32 isr4;
  433 +};
  434 +
422 435 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
423 436 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
424 437 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16
arch/arm/include/asm/arch-mx6/iomux.h
Diff comments   View file @ e38b15b
... ... @@ -19,6 +19,12 @@
19 19 #define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18)
20 20  
21 21 /*
  22 + * IOMUXC_GPR5 bit fields
  23 + */
  24 +#define IOMUXC_GPR5_PCIE_BTNRST (1 << 19)
  25 +#define IOMUXC_GPR5_PCIE_PERST (1 << 18)
  26 +
  27 +/*
22 28 * IOMUXC_GPR8 bit fields
23 29 */
24 30 #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK (0x3f << 0)
25 31  
... ... @@ -35,12 +41,15 @@
35 41 /*
36 42 * IOMUXC_GPR12 bit fields
37 43 */
  44 +#define IOMUXC_GPR12_RX_EQ_2 (0x2 << 0)
  45 +#define IOMUXC_GPR12_RX_EQ_MASK (0x7 << 0)
38 46 #define IOMUXC_GPR12_LOS_LEVEL_9 (0x9 << 4)
39 47 #define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4)
40 48 #define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10)
41 49 #define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12)
42 50 #define IOMUXC_GPR12_DEVICE_TYPE_RC (0x4 << 12)
43 51 #define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12)
  52 +#define IOMUXC_GPR12_TEST_POWERDOWN (1 << 30)
44 53  
45 54 /*
46 55 * IOMUXC_GPR13 bit fields
arch/arm/include/asm/arch-mx6/sys_proto.h
Diff comments   View file @ e38b15b
... ... @@ -20,8 +20,9 @@
20 20 /* returns MXC_CPU_ value */
21 21 #define cpu_type(rev) (((rev) >> 12)&0xff)
22 22  
23   -/* use with MXC_CPU_ constants */
24   -#define is_cpu_type(cpu) (cpu_type(get_cpu_rev()) == cpu)
  23 +/* both macros return/take MXC_CPU_ constants */
  24 +#define get_cpu_type() (cpu_type(get_cpu_rev()))
  25 +#define is_cpu_type(cpu) (get_cpu_type() == cpu)
25 26  
26 27 const char *get_imx_type(u32 imxtype);
27 28 unsigned imx_ddr_size(void);
arch/arm/include/asm/imx-common/mxc_i2c.h
Diff comments   View file @ e38b15b
... ... @@ -19,6 +19,39 @@
19 19 struct i2c_pin_ctrl sda;
20 20 };
21 21  
  22 +#if defined(CONFIG_MX6QDL)
  23 +#define I2C_PADS(name, scl_i2c, scl_gpio, scl_gp, sda_i2c, sda_gpio, sda_gp) \
  24 + struct i2c_pads_info mx6q_##name = { \
  25 + .scl = { \
  26 + .i2c_mode = MX6Q_##scl_i2c, \
  27 + .gpio_mode = MX6Q_##scl_gpio, \
  28 + .gp = scl_gp, \
  29 + }, \
  30 + .sda = { \
  31 + .i2c_mode = MX6Q_##sda_i2c, \
  32 + .gpio_mode = MX6Q_##sda_gpio, \
  33 + .gp = sda_gp, \
  34 + } \
  35 + }; \
  36 + struct i2c_pads_info mx6s_##name = { \
  37 + .scl = { \
  38 + .i2c_mode = MX6DL_##scl_i2c, \
  39 + .gpio_mode = MX6DL_##scl_gpio, \
  40 + .gp = scl_gp, \
  41 + }, \
  42 + .sda = { \
  43 + .i2c_mode = MX6DL_##sda_i2c, \
  44 + .gpio_mode = MX6DL_##sda_gpio, \
  45 + .gp = sda_gp, \
  46 + } \
  47 + };
  48 +
  49 +
  50 +#define I2C_PADS_INFO(name) \
  51 + (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) ? \
  52 + &mx6q_##name : &mx6s_##name
  53 +#endif
  54 +
22 55 void setup_i2c(unsigned i2c_index, int speed, int slave_addr,
23 56 struct i2c_pads_info *p);
24 57 void bus_i2c_init(void *base, int speed, int slave_addr,
board/compulab/cm_fx6/Kconfig
Diff comments   View file @ e38b15b
  1 +if TARGET_CM_FX6
  2 +
  3 +config SYS_CPU
  4 + string
  5 + default "armv7"
  6 +
  7 +config SYS_BOARD
  8 + string
  9 + default "cm_fx6"
  10 +
  11 +config SYS_VENDOR
  12 + string
  13 + default "compulab"
  14 +
  15 +config SYS_SOC
  16 + string
  17 + default "mx6"
  18 +
  19 +config SYS_CONFIG_NAME
  20 + string
  21 + default "cm_fx6"
  22 +
  23 +endif
board/compulab/cm_fx6/MAINTAINERS
Diff comments   View file @ e38b15b
  1 +CM_FX6 BOARD
  2 +M: Nikita Kiryanov <nikita@compulab.co.il>
  3 +S: Maintained
  4 +F: board/compulab/cm_fx6/
  5 +F: include/configs/cm_fx6.h
  6 +F: configs/cm_fx6_defconfig
board/compulab/cm_fx6/Makefile
Diff comments   View file @ e38b15b
  1 +#
  2 +# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
  3 +#
  4 +# Authors: Nikita Kiryanov <nikita@compulab.co.il>
  5 +#
  6 +# SPDX-License-Identifier: GPL-2.0+
  7 +#
  8 +ifdef CONFIG_SPL_BUILD
  9 +obj-y = common.o spl.o
  10 +else
  11 +obj-y = common.o cm_fx6.o
  12 +endif
board/compulab/cm_fx6/cm_fx6.c
Diff comments   View file @ e38b15b
  1 +/*
  2 + * Board functions for Compulab CM-FX6 board
  3 + *
  4 + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
  5 + *
  6 + * Author: Nikita Kiryanov <nikita@compulab.co.il>
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <fsl_esdhc.h>
  13 +#include <miiphy.h>
  14 +#include <netdev.h>
  15 +#include <fdt_support.h>
  16 +#include <sata.h>
  17 +#include <asm/arch/crm_regs.h>
  18 +#include <asm/arch/sys_proto.h>
  19 +#include <asm/arch/iomux.h>
  20 +#include <asm/imx-common/mxc_i2c.h>
  21 +#include <asm/imx-common/sata.h>
  22 +#include <asm/io.h>
  23 +#include <asm/gpio.h>
  24 +#include "common.h"
  25 +#include "../common/eeprom.h"
  26 +
  27 +DECLARE_GLOBAL_DATA_PTR;
  28 +
  29 +#ifdef CONFIG_DWC_AHSATA
  30 +static int cm_fx6_issd_gpios[] = {
  31 + /* The order of the GPIOs in the array is important! */
  32 + CM_FX6_SATA_PHY_SLP,
  33 + CM_FX6_SATA_NRSTDLY,
  34 + CM_FX6_SATA_PWREN,
  35 + CM_FX6_SATA_NSTANDBY1,
  36 + CM_FX6_SATA_NSTANDBY2,
  37 + CM_FX6_SATA_LDO_EN,
  38 +};
  39 +
  40 +static void cm_fx6_sata_power(int on)
  41 +{
  42 + int i;
  43 +
  44 + if (!on) { /* tell the iSSD that the power will be removed */
  45 + gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
  46 + mdelay(10);
  47 + }
  48 +
  49 + for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
  50 + gpio_direction_output(cm_fx6_issd_gpios[i], on);
  51 + udelay(100);
  52 + }
  53 +
  54 + if (!on) /* for compatibility lower the power loss interrupt */
  55 + gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
  56 +}
  57 +
  58 +static iomux_v3_cfg_t const sata_pads[] = {
  59 + /* SATA PWR */
  60 + IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  61 + IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  62 + IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  63 + IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  64 + /* SATA CTRL */
  65 + IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  66 + IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  67 + IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  68 + IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  69 + IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  70 +};
  71 +
  72 +static void cm_fx6_setup_issd(void)
  73 +{
  74 + SETUP_IOMUX_PADS(sata_pads);
  75 + /* Make sure this gpio has logical 0 value */
  76 + gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
  77 + udelay(100);
  78 +
  79 + cm_fx6_sata_power(0);
  80 + mdelay(250);
  81 + cm_fx6_sata_power(1);
  82 +}
  83 +
  84 +#define CM_FX6_SATA_INIT_RETRIES 10
  85 +int sata_initialize(void)
  86 +{
  87 + int err, i;
  88 +
  89 + cm_fx6_setup_issd();
  90 + for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
  91 + err = setup_sata();
  92 + if (err) {
  93 + printf("SATA setup failed: %d\n", err);
  94 + return err;
  95 + }
  96 +
  97 + udelay(100);
  98 +
  99 + err = __sata_initialize();
  100 + if (!err)
  101 + break;
  102 +
  103 + /* There is no device on the SATA port */
  104 + if (sata_port_status(0, 0) == 0)
  105 + break;
  106 +
  107 + /* There's a device, but link not established. Retry */
  108 + }
  109 +
  110 + return err;
  111 +}
  112 +#endif
  113 +
  114 +#ifdef CONFIG_SYS_I2C_MXC
  115 +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  116 + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  117 + PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  118 +
  119 +I2C_PADS(i2c0_pads,
  120 + PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
  121 + PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  122 + IMX_GPIO_NR(3, 21),
  123 + PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
  124 + PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  125 + IMX_GPIO_NR(3, 28));
  126 +
  127 +I2C_PADS(i2c1_pads,
  128 + PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
  129 + PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  130 + IMX_GPIO_NR(4, 12),
  131 + PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
  132 + PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  133 + IMX_GPIO_NR(4, 13));
  134 +
  135 +I2C_PADS(i2c2_pads,
  136 + PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
  137 + PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  138 + IMX_GPIO_NR(1, 3),
  139 + PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
  140 + PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  141 + IMX_GPIO_NR(1, 6));
  142 +
  143 +
  144 +static void cm_fx6_setup_i2c(void)
  145 +{
  146 + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c0_pads));
  147 + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c1_pads));
  148 + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c2_pads));
  149 +}
  150 +#else
  151 +static void cm_fx6_setup_i2c(void) { }
  152 +#endif
  153 +
  154 +#ifdef CONFIG_USB_EHCI_MX6
  155 +#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
  156 + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  157 + PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  158 +
  159 +static int cm_fx6_usb_hub_reset(void)
  160 +{
  161 + int err;
  162 +
  163 + err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
  164 + if (err) {
  165 + printf("USB hub rst gpio request failed: %d\n", err);
  166 + return -1;
  167 + }
  168 +
  169 + SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
  170 + gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
  171 + udelay(10);
  172 + gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
  173 + mdelay(1);
  174 +
  175 + return 0;
  176 +}
  177 +
  178 +static int cm_fx6_init_usb_otg(void)
  179 +{
  180 + int ret;
  181 + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  182 +
  183 + ret = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
  184 + if (ret) {
  185 + printf("USB OTG pwr gpio request failed: %d\n", ret);
  186 + return ret;
  187 + }
  188 +
  189 + SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
  190 + SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
  191 + MUX_PAD_CTRL(WEAK_PULLDOWN));
  192 + clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
  193 + /* disable ext. charger detect, or it'll affect signal quality at dp. */
  194 + return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
  195 +}
  196 +
  197 +#define MX6_USBNC_BASEADDR 0x2184800
  198 +#define USBNC_USB_H1_PWR_POL (1 << 9)
  199 +int board_ehci_hcd_init(int port)
  200 +{
  201 + u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
  202 +
  203 + switch (port) {
  204 + case 0:
  205 + return cm_fx6_init_usb_otg();
  206 + case 1:
  207 + SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR |
  208 + MUX_PAD_CTRL(NO_PAD_CTRL));
  209 +
  210 + /* Set PWR polarity to match power switch's enable polarity */
  211 + setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
  212 + return cm_fx6_usb_hub_reset();
  213 + default:
  214 + break;
  215 + }
  216 +
  217 + return 0;
  218 +}
  219 +
  220 +int board_ehci_power(int port, int on)
  221 +{
  222 + if (port == 0)
  223 + return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
  224 +
  225 + return 0;
  226 +}
  227 +#endif
  228 +
  229 +#ifdef CONFIG_FEC_MXC
  230 +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  231 + PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  232 +
  233 +static int mx6_rgmii_rework(struct phy_device *phydev)
  234 +{
  235 + unsigned short val;
  236 +
  237 + /* Ar8031 phy SmartEEE feature cause link status generates glitch,
  238 + * which cause ethernet link down/up issue, so disable SmartEEE
  239 + */
  240 + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
  241 + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
  242 + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
  243 + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  244 + val &= ~(0x1 << 8);
  245 + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  246 +
  247 + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
  248 + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  249 + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  250 + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  251 +
  252 + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  253 + val &= 0xffe3;
  254 + val |= 0x18;
  255 + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  256 +
  257 + /* introduce tx clock delay */
  258 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  259 + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  260 + val |= 0x0100;
  261 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  262 +
  263 + return 0;
  264 +}
  265 +
  266 +int board_phy_config(struct phy_device *phydev)
  267 +{
  268 + mx6_rgmii_rework(phydev);
  269 +
  270 + if (phydev->drv->config)
  271 + return phydev->drv->config(phydev);
  272 +
  273 + return 0;
  274 +}
  275 +
  276 +static iomux_v3_cfg_t const enet_pads[] = {
  277 + IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  278 + IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  279 + IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  280 + IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  281 + IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  282 + IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  283 + IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  284 + IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  285 + IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  286 + IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  287 + IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  288 + IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  289 + IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  290 + IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  291 + IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
  292 + IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  293 + MUX_PAD_CTRL(ENET_PAD_CTRL)),
  294 + IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  295 + MUX_PAD_CTRL(ENET_PAD_CTRL)),
  296 + IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  297 + MUX_PAD_CTRL(ENET_PAD_CTRL)),
  298 +};
  299 +
  300 +static int handle_mac_address(void)
  301 +{
  302 + unsigned char enetaddr[6];
  303 + int rc;
  304 +
  305 + rc = eth_getenv_enetaddr("ethaddr", enetaddr);
  306 + if (rc)
  307 + return 0;
  308 +
  309 + rc = cl_eeprom_read_mac_addr(enetaddr);
  310 + if (rc)
  311 + return rc;
  312 +
  313 + if (!is_valid_ether_addr(enetaddr))
  314 + return -1;
  315 +
  316 + return eth_setenv_enetaddr("ethaddr", enetaddr);
  317 +}
  318 +
  319 +int board_eth_init(bd_t *bis)
  320 +{
  321 + int res = handle_mac_address();
  322 + if (res)
  323 + puts("No MAC address found\n");
  324 +
  325 + SETUP_IOMUX_PADS(enet_pads);
  326 + /* phy reset */
  327 + gpio_direction_output(CM_FX6_ENET_NRST, 0);
  328 + udelay(500);
  329 + gpio_set_value(CM_FX6_ENET_NRST, 1);
  330 + enable_enet_clk(1);
  331 + return cpu_eth_init(bis);
  332 +}
  333 +#endif
  334 +
  335 +#ifdef CONFIG_NAND_MXS
  336 +static iomux_v3_cfg_t const nand_pads[] = {
  337 + IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
  338 + IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
  339 + IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  340 + IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  341 + IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  342 + IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  343 + IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  344 + IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  345 + IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  346 + IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  347 + IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  348 + IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  349 + IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  350 + IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  351 +};
  352 +
  353 +static void cm_fx6_setup_gpmi_nand(void)
  354 +{
  355 + SETUP_IOMUX_PADS(nand_pads);
  356 + /* Enable clock roots */
  357 + enable_usdhc_clk(1, 3);
  358 + enable_usdhc_clk(1, 4);
  359 +
  360 + setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
  361 + MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) |
  362 + MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
  363 +}
  364 +#else
  365 +static void cm_fx6_setup_gpmi_nand(void) {}
  366 +#endif
  367 +
  368 +#ifdef CONFIG_FSL_ESDHC
  369 +static struct fsl_esdhc_cfg usdhc_cfg[3] = {
  370 + {USDHC1_BASE_ADDR},
  371 + {USDHC2_BASE_ADDR},
  372 + {USDHC3_BASE_ADDR},
  373 +};
  374 +
  375 +static enum mxc_clock usdhc_clk[3] = {
  376 + MXC_ESDHC_CLK,
  377 + MXC_ESDHC2_CLK,
  378 + MXC_ESDHC3_CLK,
  379 +};
  380 +
  381 +int board_mmc_init(bd_t *bis)
  382 +{
  383 + int i;
  384 +
  385 + cm_fx6_set_usdhc_iomux();
  386 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  387 + usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
  388 + usdhc_cfg[i].max_bus_width = 4;
  389 + fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  390 + enable_usdhc_clk(1, i);
  391 + }
  392 +
  393 + return 0;
  394 +}
  395 +#endif
  396 +
  397 +#ifdef CONFIG_OF_BOARD_SETUP
  398 +void ft_board_setup(void *blob, bd_t *bd)
  399 +{
  400 + uint8_t enetaddr[6];
  401 +
  402 + /* MAC addr */
  403 + if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
  404 + fdt_find_and_setprop(blob, "/fec", "local-mac-address",
  405 + enetaddr, 6, 1);
  406 + }
  407 +}
  408 +#endif
  409 +
  410 +int board_init(void)
  411 +{
  412 + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  413 + cm_fx6_setup_gpmi_nand();
  414 + cm_fx6_setup_i2c();
  415 +
  416 + return 0;
  417 +}
  418 +
  419 +int checkboard(void)
  420 +{
  421 + puts("Board: CM-FX6\n");
  422 + return 0;
  423 +}
  424 +
  425 +void dram_init_banksize(void)
  426 +{
  427 + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  428 + gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  429 +
  430 + switch (gd->ram_size) {
  431 + case 0x10000000: /* DDR_16BIT_256MB */
  432 + gd->bd->bi_dram[0].size = 0x10000000;
  433 + gd->bd->bi_dram[1].size = 0;
  434 + break;
  435 + case 0x20000000: /* DDR_32BIT_512MB */
  436 + gd->bd->bi_dram[0].size = 0x20000000;
  437 + gd->bd->bi_dram[1].size = 0;
  438 + break;
  439 + case 0x40000000:
  440 + if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
  441 + gd->bd->bi_dram[0].size = 0x20000000;
  442 + gd->bd->bi_dram[1].size = 0x20000000;
  443 + } else { /* DDR_64BIT_1GB */
  444 + gd->bd->bi_dram[0].size = 0x40000000;
  445 + gd->bd->bi_dram[1].size = 0;
  446 + }
  447 + break;
  448 + case 0x80000000: /* DDR_64BIT_2GB */
  449 + gd->bd->bi_dram[0].size = 0x40000000;
  450 + gd->bd->bi_dram[1].size = 0x40000000;
  451 + break;
  452 + case 0xEFF00000: /* DDR_64BIT_4GB */
  453 + gd->bd->bi_dram[0].size = 0x70000000;
  454 + gd->bd->bi_dram[1].size = 0x7FF00000;
  455 + break;
  456 + }
  457 +}
  458 +
  459 +int dram_init(void)
  460 +{
  461 + gd->ram_size = imx_ddr_size();
  462 + switch (gd->ram_size) {
  463 + case 0x10000000:
  464 + case 0x20000000:
  465 + case 0x40000000:
  466 + case 0x80000000:
  467 + break;
  468 + case 0xF0000000:
  469 + gd->ram_size -= 0x100000;
  470 + break;
  471 + default:
  472 + printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
  473 + return -1;
  474 + }
  475 +
  476 + return 0;
  477 +}
  478 +
  479 +u32 get_board_rev(void)
  480 +{
  481 + return cl_eeprom_get_board_rev();
  482 +}
board/compulab/cm_fx6/common.c
Diff comments   View file @ e38b15b
  1 +/*
  2 + * Code used by both U-Boot and SPL for Compulab CM-FX6
  3 + *
  4 + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
  5 + *
  6 + * Author: Nikita Kiryanov <nikita@compulab.co.il>
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <asm/arch/sys_proto.h>
  13 +#include <asm/gpio.h>
  14 +#include <fsl_esdhc.h>
  15 +#include "common.h"
  16 +
  17 +DECLARE_GLOBAL_DATA_PTR;
  18 +
  19 +#ifdef CONFIG_FSL_ESDHC
  20 +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  21 + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  22 + PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  23 +
  24 +static iomux_v3_cfg_t const usdhc_pads[] = {
  25 + IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  26 + IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  27 + IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  28 + IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  29 + IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  30 + IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  31 +
  32 + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  33 + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  34 + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  35 + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  36 + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  37 + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  38 +
  39 + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  40 + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  41 + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  42 + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  43 + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  44 + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  45 + IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  46 + IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  47 + IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  48 + IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  49 +};
  50 +
  51 +void cm_fx6_set_usdhc_iomux(void)
  52 +{
  53 + SETUP_IOMUX_PADS(usdhc_pads);
  54 +}
  55 +
  56 +/* CINS bit doesn't work, so always try to access the MMC card */
  57 +int board_mmc_getcd(struct mmc *mmc)
  58 +{
  59 + return 1;
  60 +}
  61 +#endif
  62 +
  63 +#ifdef CONFIG_MXC_SPI
  64 +#define ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
  65 + PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  66 +
  67 +static iomux_v3_cfg_t const ecspi_pads[] = {
  68 + IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
  69 + IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
  70 + IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
  71 + IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
  72 + IOMUX_PADS(PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
  73 +};
  74 +
  75 +void cm_fx6_set_ecspi_iomux(void)
  76 +{
  77 + SETUP_IOMUX_PADS(ecspi_pads);
  78 +}
  79 +
  80 +int board_spi_cs_gpio(unsigned bus, unsigned cs)
  81 +{
  82 + return (bus == 0 && cs == 0) ? (CM_FX6_ECSPI_BUS0_CS0) : -1;
  83 +}
  84 +#endif
board/compulab/cm_fx6/common.h
Diff comments   View file @ e38b15b
  1 +/*
  2 + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
  3 + *
  4 + * Author: Nikita Kiryanov <nikita@compulab.co.il>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <asm/arch/mx6-pins.h>
  10 +#include <asm/arch/clock.h>
  11 +
  12 +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  13 + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  14 + PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  15 +
  16 +#define CM_FX6_ECSPI_BUS0_CS0 IMX_GPIO_NR(2, 30)
  17 +#define CM_FX6_GREEN_LED IMX_GPIO_NR(2, 31)
  18 +#define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8)
  19 +#define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8)
  20 +#define CM_FX6_USB_HUB_RST IMX_GPIO_NR(7, 8)
  21 +#define SB_FX6_USB_OTG_PWR IMX_GPIO_NR(3, 22)
  22 +#define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8)
  23 +#define CM_FX6_USB_HUB_RST IMX_GPIO_NR(7, 8)
  24 +#define SB_FX6_USB_OTG_PWR IMX_GPIO_NR(3, 22)
  25 +#define CM_FX6_SATA_PWREN IMX_GPIO_NR(1, 28)
  26 +#define CM_FX6_SATA_VDDC_CTRL IMX_GPIO_NR(1, 30)
  27 +#define CM_FX6_SATA_LDO_EN IMX_GPIO_NR(2, 16)
  28 +#define CM_FX6_SATA_NSTANDBY1 IMX_GPIO_NR(3, 20)
  29 +#define CM_FX6_SATA_PHY_SLP IMX_GPIO_NR(3, 23)
  30 +#define CM_FX6_SATA_STBY_REQ IMX_GPIO_NR(3, 29)
  31 +#define CM_FX6_SATA_NSTANDBY2 IMX_GPIO_NR(5, 2)
  32 +#define CM_FX6_SATA_NRSTDLY IMX_GPIO_NR(6, 6)
  33 +#define CM_FX6_SATA_PWLOSS_INT IMX_GPIO_NR(6, 31)
  34 +
  35 +
  36 +void cm_fx6_set_usdhc_iomux(void);
  37 +void cm_fx6_set_ecspi_iomux(void);
board/compulab/cm_fx6/imximage.cfg
Diff comments   View file @ e38b15b
  1 +/*
  2 + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +IMAGE_VERSION 2
  8 +BOOT_FROM sd
board/compulab/cm_fx6/spl.c
Diff comments   View file @ e38b15b
  1 +/*
  2 + * SPL specific code for Compulab CM-FX6 board
  3 + *
  4 + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
  5 + *
  6 + * Author: Nikita Kiryanov <nikita@compulab.co.il>
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <spl.h>
  13 +#include <asm/io.h>
  14 +#include <asm/gpio.h>
  15 +#include <asm/arch/mx6-ddr.h>
  16 +#include <asm/arch/clock.h>
  17 +#include <asm/arch/sys_proto.h>
  18 +#include <asm/arch/crm_regs.h>
  19 +#include <asm/imx-common/iomux-v3.h>
  20 +#include <fsl_esdhc.h>
  21 +#include "common.h"
  22 +
  23 +DECLARE_GLOBAL_DATA_PTR;
  24 +
  25 +enum ddr_config {
  26 + DDR_16BIT_256MB,
  27 + DDR_32BIT_512MB,
  28 + DDR_32BIT_1GB,
  29 + DDR_64BIT_1GB,
  30 + DDR_64BIT_2GB,
  31 + DDR_64BIT_4GB,
  32 + DDR_UNKNOWN,
  33 +};
  34 +
  35 +/*
  36 + * Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to
  37 + * Freescale QRM, but this is exactly the value used by the automatic
  38 + * calibration script and it works also in all our tests, so we leave
  39 + * it as is at this point.
  40 + */
  41 +#define CM_FX6_DDR_IOMUX_CFG \
  42 + .dram_sdqs0 = 0x00000038, \
  43 + .dram_sdqs1 = 0x00000038, \
  44 + .dram_sdqs2 = 0x00000038, \
  45 + .dram_sdqs3 = 0x00000038, \
  46 + .dram_sdqs4 = 0x00000038, \
  47 + .dram_sdqs5 = 0x00000038, \
  48 + .dram_sdqs6 = 0x00000038, \
  49 + .dram_sdqs7 = 0x00000038, \
  50 + .dram_dqm0 = 0x00000038, \
  51 + .dram_dqm1 = 0x00000038, \
  52 + .dram_dqm2 = 0x00000038, \
  53 + .dram_dqm3 = 0x00000038, \
  54 + .dram_dqm4 = 0x00000038, \
  55 + .dram_dqm5 = 0x00000038, \
  56 + .dram_dqm6 = 0x00000038, \
  57 + .dram_dqm7 = 0x00000038, \
  58 + .dram_cas = 0x00000038, \
  59 + .dram_ras = 0x00000038, \
  60 + .dram_sdclk_0 = 0x00000038, \
  61 + .dram_sdclk_1 = 0x00000038, \
  62 + .dram_sdcke0 = 0x00003000, \
  63 + .dram_sdcke1 = 0x00003000, \
  64 + .dram_reset = 0x00000038, \
  65 + .dram_sdba2 = 0x00000000, \
  66 + .dram_sdodt0 = 0x00000038, \
  67 + .dram_sdodt1 = 0x00000038,
  68 +
  69 +#define CM_FX6_GPR_IOMUX_CFG \
  70 + .grp_b0ds = 0x00000038, \
  71 + .grp_b1ds = 0x00000038, \
  72 + .grp_b2ds = 0x00000038, \
  73 + .grp_b3ds = 0x00000038, \
  74 + .grp_b4ds = 0x00000038, \
  75 + .grp_b5ds = 0x00000038, \
  76 + .grp_b6ds = 0x00000038, \
  77 + .grp_b7ds = 0x00000038, \
  78 + .grp_addds = 0x00000038, \
  79 + .grp_ddrmode_ctl = 0x00020000, \
  80 + .grp_ddrpke = 0x00000000, \
  81 + .grp_ddrmode = 0x00020000, \
  82 + .grp_ctlds = 0x00000038, \
  83 + .grp_ddr_type = 0x000C0000,
  84 +
  85 +static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { CM_FX6_DDR_IOMUX_CFG };
  86 +static struct mx6sdl_iomux_grp_regs grp_iomux_s = { CM_FX6_GPR_IOMUX_CFG };
  87 +static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { CM_FX6_DDR_IOMUX_CFG };
  88 +static struct mx6dq_iomux_grp_regs grp_iomux_q = { CM_FX6_GPR_IOMUX_CFG };
  89 +
  90 +static struct mx6_mmdc_calibration cm_fx6_calib_s = {
  91 + .p0_mpwldectrl0 = 0x005B0061,
  92 + .p0_mpwldectrl1 = 0x004F0055,
  93 + .p0_mpdgctrl0 = 0x0314030C,
  94 + .p0_mpdgctrl1 = 0x025C0268,
  95 + .p0_mprddlctl = 0x42464646,
  96 + .p0_mpwrdlctl = 0x36322C34,
  97 +};
  98 +
  99 +static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = {
  100 + .cs1_mirror = 1,
  101 + .cs_density = 16,
  102 + .bi_on = 1,
  103 + .rtt_nom = 1,
  104 + .rtt_wr = 0,
  105 + .ralat = 5,
  106 + .walat = 1,
  107 + .mif3_mode = 3,
  108 + .rst_to_cke = 0x23,
  109 + .sde_to_rst = 0x10,
  110 +};
  111 +
  112 +static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = {
  113 + .mem_speed = 800,
  114 + .density = 4,
  115 + .rowaddr = 14,
  116 + .coladdr = 10,
  117 + .pagesz = 2,
  118 + .trcd = 1800,
  119 + .trcmin = 5200,
  120 + .trasmin = 3600,
  121 + .SRT = 0,
  122 +};
  123 +
  124 +static void spl_mx6s_dram_init(enum ddr_config dram_config, bool reset)
  125 +{
  126 + if (reset)
  127 + ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
  128 +
  129 + switch (dram_config) {
  130 + case DDR_16BIT_256MB:
  131 + cm_fx6_sysinfo_s.dsize = 0;
  132 + cm_fx6_sysinfo_s.ncs = 1;
  133 + break;
  134 + case DDR_32BIT_512MB:
  135 + cm_fx6_sysinfo_s.dsize = 1;
  136 + cm_fx6_sysinfo_s.ncs = 1;
  137 + break;
  138 + case DDR_32BIT_1GB:
  139 + cm_fx6_sysinfo_s.dsize = 1;
  140 + cm_fx6_sysinfo_s.ncs = 2;
  141 + break;
  142 + default:
  143 + puts("Tried to setup invalid DDR configuration\n");
  144 + hang();
  145 + }
  146 +
  147 + mx6_dram_cfg(&cm_fx6_sysinfo_s, &cm_fx6_calib_s, &cm_fx6_ddr3_cfg_s);
  148 + udelay(100);
  149 +}
  150 +
  151 +static struct mx6_mmdc_calibration cm_fx6_calib_q = {
  152 + .p0_mpwldectrl0 = 0x00630068,
  153 + .p0_mpwldectrl1 = 0x0068005D,
  154 + .p0_mpdgctrl0 = 0x04140428,
  155 + .p0_mpdgctrl1 = 0x037C037C,
  156 + .p0_mprddlctl = 0x3C30303A,
  157 + .p0_mpwrdlctl = 0x3A344038,
  158 + .p1_mpwldectrl0 = 0x0035004C,
  159 + .p1_mpwldectrl1 = 0x00170026,
  160 + .p1_mpdgctrl0 = 0x0374037C,
  161 + .p1_mpdgctrl1 = 0x0350032C,
  162 + .p1_mprddlctl = 0x30322A3C,
  163 + .p1_mpwrdlctl = 0x48304A3E,
  164 +};
  165 +
  166 +static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = {
  167 + .cs_density = 16,
  168 + .cs1_mirror = 1,
  169 + .bi_on = 1,
  170 + .rtt_nom = 1,
  171 + .rtt_wr = 0,
  172 + .ralat = 5,
  173 + .walat = 1,
  174 + .mif3_mode = 3,
  175 + .rst_to_cke = 0x23,
  176 + .sde_to_rst = 0x10,
  177 +};
  178 +
  179 +static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = {
  180 + .mem_speed = 1066,
  181 + .density = 4,
  182 + .rowaddr = 14,
  183 + .coladdr = 10,
  184 + .pagesz = 2,
  185 + .trcd = 1324,
  186 + .trcmin = 59500,
  187 + .trasmin = 9750,
  188 + .SRT = 0,
  189 +};
  190 +
  191 +static void spl_mx6q_dram_init(enum ddr_config dram_config, bool reset)
  192 +{
  193 + if (reset)
  194 + ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
  195 +
  196 + cm_fx6_ddr3_cfg_q.rowaddr = 14;
  197 + switch (dram_config) {
  198 + case DDR_16BIT_256MB:
  199 + cm_fx6_sysinfo_q.dsize = 0;
  200 + cm_fx6_sysinfo_q.ncs = 1;
  201 + break;
  202 + case DDR_32BIT_512MB:
  203 + cm_fx6_sysinfo_q.dsize = 1;
  204 + cm_fx6_sysinfo_q.ncs = 1;
  205 + break;
  206 + case DDR_64BIT_1GB:
  207 + cm_fx6_sysinfo_q.dsize = 2;
  208 + cm_fx6_sysinfo_q.ncs = 1;
  209 + break;
  210 + case DDR_64BIT_2GB:
  211 + cm_fx6_sysinfo_q.dsize = 2;
  212 + cm_fx6_sysinfo_q.ncs = 2;
  213 + break;
  214 + case DDR_64BIT_4GB:
  215 + cm_fx6_sysinfo_q.dsize = 2;
  216 + cm_fx6_sysinfo_q.ncs = 2;
  217 + cm_fx6_ddr3_cfg_q.rowaddr = 15;
  218 + break;
  219 + default:
  220 + puts("Tried to setup invalid DDR configuration\n");
  221 + hang();
  222 + }
  223 +
  224 + mx6_dram_cfg(&cm_fx6_sysinfo_q, &cm_fx6_calib_q, &cm_fx6_ddr3_cfg_q);
  225 + udelay(100);
  226 +}
  227 +
  228 +static int cm_fx6_spl_dram_init(void)
  229 +{
  230 + unsigned long bank1_size, bank2_size;
  231 +
  232 + switch (get_cpu_type()) {
  233 + case MXC_CPU_MX6SOLO:
  234 + mx6sdl_dram_iocfg(64, &ddr_iomux_s, &grp_iomux_s);
  235 +
  236 + spl_mx6s_dram_init(DDR_32BIT_1GB, false);
  237 + bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
  238 + if (bank1_size == 0x40000000)
  239 + return 0;
  240 +
  241 + if (bank1_size == 0x20000000) {
  242 + spl_mx6s_dram_init(DDR_32BIT_512MB, true);
  243 + return 0;
  244 + }
  245 +
  246 + spl_mx6s_dram_init(DDR_16BIT_256MB, true);
  247 + bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
  248 + if (bank1_size == 0x10000000)
  249 + return 0;
  250 +
  251 + break;
  252 + case MXC_CPU_MX6D:
  253 + case MXC_CPU_MX6Q:
  254 + mx6dq_dram_iocfg(64, &ddr_iomux_q, &grp_iomux_q);
  255 +
  256 + spl_mx6q_dram_init(DDR_64BIT_4GB, false);
  257 + bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
  258 + if (bank1_size == 0x80000000)
  259 + return 0;
  260 +
  261 + if (bank1_size == 0x40000000) {
  262 + bank2_size = get_ram_size((long int *)PHYS_SDRAM_2,
  263 + 0x80000000);
  264 + if (bank2_size == 0x40000000) {
  265 + /* Don't do a full reset here */
  266 + spl_mx6q_dram_init(DDR_64BIT_2GB, false);
  267 + } else {
  268 + spl_mx6q_dram_init(DDR_64BIT_1GB, true);
  269 + }
  270 +
  271 + return 0;
  272 + }
  273 +
  274 + spl_mx6q_dram_init(DDR_32BIT_512MB, true);
  275 + bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
  276 + if (bank1_size == 0x20000000)
  277 + return 0;
  278 +
  279 + spl_mx6q_dram_init(DDR_16BIT_256MB, true);
  280 + bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
  281 + if (bank1_size == 0x10000000)
  282 + return 0;
  283 +
  284 + break;
  285 + }
  286 +
  287 + return -1;
  288 +}
  289 +
  290 +static iomux_v3_cfg_t const uart4_pads[] = {
  291 + IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  292 + IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  293 +};
  294 +
  295 +static void cm_fx6_setup_uart(void)
  296 +{
  297 + SETUP_IOMUX_PADS(uart4_pads);
  298 + enable_uart_clk(1);
  299 +}
  300 +
  301 +#ifdef CONFIG_SPL_SPI_SUPPORT
  302 +static void cm_fx6_setup_ecspi(void)
  303 +{
  304 + cm_fx6_set_ecspi_iomux();
  305 + enable_cspi_clock(1, 0);
  306 +}
  307 +#else
  308 +static void cm_fx6_setup_ecspi(void) { }
  309 +#endif
  310 +
  311 +void board_init_f(ulong dummy)
  312 +{
  313 + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  314 +
  315 + gd = &gdata;
  316 + /*
  317 + * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
  318 + * initializes DMA very early (before all board code), so the only
  319 + * opportunity we have to initialize APBHDMA clocks is in SPL.
  320 + */
  321 + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  322 + enable_usdhc_clk(1, 2);
  323 +
  324 + arch_cpu_init();
  325 + timer_init();
  326 + cm_fx6_setup_ecspi();
  327 + cm_fx6_setup_uart();
  328 + get_clocks();
  329 + preloader_console_init();
  330 + gpio_direction_output(CM_FX6_GREEN_LED, 1);
  331 + if (cm_fx6_spl_dram_init()) {
  332 + puts("!!!ERROR!!! DRAM detection failed!!!\n");
  333 + hang();
  334 + }
  335 +
  336 + memset(__bss_start, 0, __bss_end - __bss_start);
  337 + board_init_r(NULL, 0);
  338 +}
  339 +
  340 +void spl_board_init(void)
  341 +{
  342 + u32 boot_device = spl_boot_device();
  343 +
  344 + if (boot_device == BOOT_DEVICE_SPI)
  345 + puts("Booting from SPI flash\n");
  346 + else if (boot_device == BOOT_DEVICE_MMC1)
  347 + puts("Booting from MMC\n");
  348 + else
  349 + puts("Unknown boot device\n");
  350 +}
  351 +
  352 +#ifdef CONFIG_SPL_MMC_SUPPORT
  353 +static struct fsl_esdhc_cfg usdhc_cfg = {
  354 + .esdhc_base = USDHC3_BASE_ADDR,
  355 + .max_bus_width = 4,
  356 +};
  357 +
  358 +int board_mmc_init(bd_t *bis)
  359 +{
  360 + cm_fx6_set_usdhc_iomux();
  361 +
  362 + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  363 +
  364 + return fsl_esdhc_initialize(bis, &usdhc_cfg);
  365 +}
  366 +#endif
board/compulab/common/eeprom.c
Diff comments   View file @ e38b15b
... ... @@ -31,8 +31,19 @@
31 31  
32 32 static int cl_eeprom_read(uint offset, uchar *buf, int len)
33 33 {
34   - return i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset,
  34 + int res;
  35 + unsigned int current_i2c_bus = i2c_get_bus_num();
  36 +
  37 + res = i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
  38 + if (res < 0)
  39 + return res;
  40 +
  41 + res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset,
35 42 CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len);
  43 +
  44 + i2c_set_bus_num(current_i2c_bus);
  45 +
  46 + return res;
36 47 }
37 48  
38 49 static int cl_eeprom_setup_layout(void)
board/freescale/mx6sabresd/mx6dlsabresd.cfg
Diff comments   View file @ e38b15b
  1 +/*
  2 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +/* image version */
  13 +
  14 +IMAGE_VERSION 2
  15 +
  16 +/*
  17 + * Boot Device : one of
  18 + * spi, sd (the board has no nand neither onenand)
  19 + */
  20 +
  21 +BOOT_FROM sd
  22 +
  23 +/*
  24 + * Device Configuration Data (DCD)
  25 + *
  26 + * Each entry must have the format:
  27 + * Addr-type Address Value
  28 + *
  29 + * where:
  30 + * Addr-type register length (1,2 or 4 bytes)
  31 + * Address absolute address of the register
  32 + * value value to be stored in the register
  33 + */
  34 +DATA 4 0x020e0774 0x000C0000
  35 +DATA 4 0x020e0754 0x00000000
  36 +DATA 4 0x020e04ac 0x00000030
  37 +DATA 4 0x020e04b0 0x00000030
  38 +DATA 4 0x020e0464 0x00000030
  39 +DATA 4 0x020e0490 0x00000030
  40 +DATA 4 0x020e074c 0x00000030
  41 +DATA 4 0x020e0494 0x00000030
  42 +DATA 4 0x020e04a0 0x00000000
  43 +DATA 4 0x020e04b4 0x00000030
  44 +DATA 4 0x020e04b8 0x00000030
  45 +DATA 4 0x020e076c 0x00000030
  46 +DATA 4 0x020e0750 0x00020000
  47 +DATA 4 0x020e04bc 0x00000030
  48 +DATA 4 0x020e04c0 0x00000030
  49 +DATA 4 0x020e04c4 0x00000030
  50 +DATA 4 0x020e04c8 0x00000030
  51 +DATA 4 0x020e04cc 0x00000030
  52 +DATA 4 0x020e04d0 0x00000030
  53 +DATA 4 0x020e04d4 0x00000030
  54 +DATA 4 0x020e04d8 0x00000030
  55 +DATA 4 0x020e0760 0x00020000
  56 +DATA 4 0x020e0764 0x00000030
  57 +DATA 4 0x020e0770 0x00000030
  58 +DATA 4 0x020e0778 0x00000030
  59 +DATA 4 0x020e077c 0x00000030
  60 +DATA 4 0x020e0780 0x00000030
  61 +DATA 4 0x020e0784 0x00000030
  62 +DATA 4 0x020e078c 0x00000030
  63 +DATA 4 0x020e0748 0x00000030
  64 +DATA 4 0x020e0470 0x00000030
  65 +DATA 4 0x020e0474 0x00000030
  66 +DATA 4 0x020e0478 0x00000030
  67 +DATA 4 0x020e047c 0x00000030
  68 +DATA 4 0x020e0480 0x00000030
  69 +DATA 4 0x020e0484 0x00000030
  70 +DATA 4 0x020e0488 0x00000030
  71 +DATA 4 0x020e048c 0x00000030
  72 +DATA 4 0x021b0800 0xa1390003
  73 +DATA 4 0x021b080c 0x001F001F
  74 +DATA 4 0x021b0810 0x001F001F
  75 +DATA 4 0x021b480c 0x001F001F
  76 +DATA 4 0x021b4810 0x001F001F
  77 +DATA 4 0x021b083c 0x4220021F
  78 +DATA 4 0x021b0840 0x0207017E
  79 +DATA 4 0x021b483c 0x4201020C
  80 +DATA 4 0x021b4840 0x01660172
  81 +DATA 4 0x021b0848 0x4A4D4E4D
  82 +DATA 4 0x021b4848 0x4A4F5049
  83 +DATA 4 0x021b0850 0x3F3C3D31
  84 +DATA 4 0x021b4850 0x3238372B
  85 +DATA 4 0x021b081c 0x33333333
  86 +DATA 4 0x021b0820 0x33333333
  87 +DATA 4 0x021b0824 0x33333333
  88 +DATA 4 0x021b0828 0x33333333
  89 +DATA 4 0x021b481c 0x33333333
  90 +DATA 4 0x021b4820 0x33333333
  91 +DATA 4 0x021b4824 0x33333333
  92 +DATA 4 0x021b4828 0x33333333
  93 +DATA 4 0x021b08b8 0x00000800
  94 +DATA 4 0x021b48b8 0x00000800
  95 +DATA 4 0x021b0004 0x0002002D
  96 +DATA 4 0x021b0008 0x00333030
  97 +DATA 4 0x021b000c 0x3F435313
  98 +DATA 4 0x021b0010 0xB66E8B63
  99 +DATA 4 0x021b0014 0x01FF00DB
  100 +DATA 4 0x021b0018 0x00001740
  101 +DATA 4 0x021b001c 0x00008000
  102 +DATA 4 0x021b002c 0x000026d2
  103 +DATA 4 0x021b0030 0x00431023
  104 +DATA 4 0x021b0040 0x00000027
  105 +DATA 4 0x021b0000 0x831A0000
  106 +DATA 4 0x021b001c 0x04008032
  107 +DATA 4 0x021b001c 0x00008033
  108 +DATA 4 0x021b001c 0x00048031
  109 +DATA 4 0x021b001c 0x05208030
  110 +DATA 4 0x021b001c 0x04008040
  111 +DATA 4 0x021b0020 0x00005800
  112 +DATA 4 0x021b0818 0x00011117
  113 +DATA 4 0x021b4818 0x00011117
  114 +DATA 4 0x021b0004 0x0002556D
  115 +DATA 4 0x021b0404 0x00011006
  116 +DATA 4 0x021b001c 0x00000000
  117 +
  118 +/* set the default clock gate to save power */
  119 +DATA 4 0x020c4068 0x00C03F3F
  120 +DATA 4 0x020c406c 0x0030FC03
  121 +DATA 4 0x020c4070 0x0FFFC000
  122 +DATA 4 0x020c4074 0x3FF00000
  123 +DATA 4 0x020c4078 0x00FFF300
  124 +DATA 4 0x020c407c 0x0F0000C3
  125 +DATA 4 0x020c4080 0x000003FF
  126 +
  127 +/* enable AXI cache for VDOA/VPU/IPU */
  128 +DATA 4 0x020e0010 0xF00000CF
  129 +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  130 +DATA 4 0x020e0018 0x007F007F
  131 +DATA 4 0x020e001c 0x007F007F
board/gateworks/gw_ventana/eeprom.c
Diff comments   View file @ e38b15b
... ... @@ -80,6 +80,9 @@
80 80 case '4':
81 81 type = GW54xx;
82 82 break;
  83 + case '5':
  84 + type = GW552x;
  85 + break;
83 86 default:
84 87 printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
85 88 type = GW_UNKNOWN;
board/gateworks/gw_ventana/gsc.c
Diff comments   View file @ e38b15b
... ... @@ -117,6 +117,10 @@
117 117 read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1375, 10));
118 118 read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10));
119 119 break;
  120 + case '5': /* GW55xx */
  121 + read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10));
  122 + read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10));
  123 + break;
120 124 }
121 125 return 0;
122 126 }
board/gateworks/gw_ventana/gw_ventana.c
Diff comments   View file @ e38b15b
... ... @@ -31,6 +31,7 @@
31 31 #include <mmc.h>
32 32 #include <mtd_node.h>
33 33 #include <netdev.h>
  34 +#include <pci.h>
34 35 #include <power/pmic.h>
35 36 #include <power/ltc3676_pmic.h>
36 37 #include <power/pfuze100_pmic.h>
... ... @@ -299,6 +300,7 @@
299 300 /* Reset USB HUB (present on GW54xx/GW53xx) */
300 301 switch (info->model[3]) {
301 302 case '3': /* GW53xx */
  303 + case '5': /* GW552x */
302 304 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
303 305 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
304 306 mdelay(2);
... ... @@ -392,7 +394,8 @@
392 394 setup_iomux_enet();
393 395  
394 396 #ifdef CONFIG_FEC_MXC
395   - cpu_eth_init(bis);
  397 + if (board_type != GW552x)
  398 + cpu_eth_init(bis);
396 399 #endif
397 400  
398 401 #ifdef CONFIG_CI_UDC
399 402  
... ... @@ -614,15 +617,14 @@
614 617 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
615 618 /* PANLEDR# */
616 619 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
  620 + /* MX6_LOCLED# */
  621 + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
617 622 /* IOEXP_PWREN# */
618 623 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
619 624 /* IOEXP_IRQ# */
620 625 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
621 626 /* DIOI2C_DIS# */
622 627 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
623   -
624   - /* MX6_LOCLED# */
625   - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
626 628 /* GPS_SHDN */
627 629 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
628 630 /* VID_EN */
... ... @@ -660,6 +662,30 @@
660 662 IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
661 663 };
662 664  
  665 +static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
  666 + /* PANLEDG# */
  667 + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
  668 + /* PANLEDR# */
  669 + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
  670 + /* MX6_LOCLED# */
  671 + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
  672 + /* PCI_RST# */
  673 + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
  674 + /* MX6_DIO[4:9] */
  675 + IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG),
  676 + IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
  677 + IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG),
  678 + IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG),
  679 + IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG),
  680 + IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG),
  681 + /* PCIEGBE1_OFF# */
  682 + IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
  683 + /* PCIEGBE2_OFF# */
  684 + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
  685 + /* PCIESKT_WDIS# */
  686 + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
  687 +};
  688 +
663 689 /*
664 690 * each baseboard has 4 user configurable Digital IO lines which can
665 691 * be pinmuxed as a GPIO or in some cases a PWM
... ... @@ -908,6 +934,44 @@
908 934 .pcie_sson = IMX_GPIO_NR(1, 20),
909 935 .wdis = IMX_GPIO_NR(5, 17),
910 936 },
  937 +
  938 + /* GW552x */
  939 + {
  940 + .gpio_pads = gw552x_gpio_pads,
  941 + .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
  942 + .dio_cfg = {
  943 + {
  944 + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
  945 + IMX_GPIO_NR(1, 16),
  946 + { 0, 0 },
  947 + 0
  948 + },
  949 + {
  950 + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
  951 + IMX_GPIO_NR(1, 19),
  952 + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
  953 + 2
  954 + },
  955 + {
  956 + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
  957 + IMX_GPIO_NR(1, 17),
  958 + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
  959 + 3
  960 + },
  961 + {
  962 + { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
  963 + IMX_GPIO_NR(2, 10),
  964 + { 0, 0 },
  965 + 0
  966 + },
  967 + },
  968 + .leds = {
  969 + IMX_GPIO_NR(4, 6),
  970 + IMX_GPIO_NR(4, 7),
  971 + IMX_GPIO_NR(4, 15),
  972 + },
  973 + .pcie_rst = IMX_GPIO_NR(1, 29),
  974 + },
911 975 };
912 976  
913 977 /* setup board specific PMIC */
914 978  
... ... @@ -997,14 +1061,16 @@
997 1061 #endif
998 1062  
999 1063 /* turn off (active-high) user LED's */
1000   - for (i = 0; i < 4; i++) {
  1064 + for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) {
1001 1065 if (gpio_cfg[board].leds[i])
1002 1066 gpio_direction_output(gpio_cfg[board].leds[i], 1);
1003 1067 }
1004 1068  
1005 1069 /* Expansion Mezzanine IO */
1006   - gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
1007   - gpio_direction_input(gpio_cfg[board].mezz_irq);
  1070 + if (gpio_cfg[board].mezz_pwren)
  1071 + gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
  1072 + if (gpio_cfg[board].mezz_irq)
  1073 + gpio_direction_input(gpio_cfg[board].mezz_irq);
1008 1074  
1009 1075 /* RS485 Transmit Enable */
1010 1076 if (gpio_cfg[board].rs485en)
... ... @@ -1092,6 +1158,35 @@
1092 1158 }
1093 1159 return 0;
1094 1160 }
  1161 +
  1162 +/*
  1163 + * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
  1164 + * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
  1165 + * properly and assert reset for 100ms.
  1166 + */
  1167 +void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
  1168 + unsigned short vendor, unsigned short device,
  1169 + unsigned short class)
  1170 +{
  1171 + u32 dw;
  1172 +
  1173 + debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
  1174 + PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
  1175 + if (vendor == PCI_VENDOR_ID_PLX &&
  1176 + (device & 0xfff0) == 0x8600 &&
  1177 + PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
  1178 + debug("configuring PLX 860X downstream PERST#\n");
  1179 + pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
  1180 + dw |= 0xaaa8; /* GPIO1-7 outputs */
  1181 + pci_hose_write_config_dword(hose, dev, 0x62c, dw);
  1182 +
  1183 + pci_hose_read_config_dword(hose, dev, 0x644, &dw);
  1184 + dw |= 0xfe; /* GPIO1-7 output high */
  1185 + pci_hose_write_config_dword(hose, dev, 0x644, dw);
  1186 +
  1187 + mdelay(100);
  1188 + }
  1189 +}
1095 1190 #endif /* CONFIG_CMD_PCI */
1096 1191  
1097 1192 #ifdef CONFIG_SERIAL_TAG
... ... @@ -1283,6 +1378,7 @@
1283 1378 else if (is_cpu_type(MXC_CPU_MX6DL) ||
1284 1379 is_cpu_type(MXC_CPU_MX6SOLO))
1285 1380 cputype = "imx6dl";
  1381 + setenv("soctype", cputype);
1286 1382 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
1287 1383 setenv("flash_layout", "large");
1288 1384 else
... ... @@ -1305,7 +1401,8 @@
1305 1401 sprintf(fdt, "%s-%s.dtb", cputype, str);
1306 1402 setenv("fdt_file1", fdt);
1307 1403 }
1308   - str[4] = 'x';
  1404 + if (board_type != GW552x)
  1405 + str[4] = 'x';
1309 1406 str[5] = 'x';
1310 1407 str[6] = 0;
1311 1408 if (!getenv("fdt_file2")) {
1312 1409  
... ... @@ -1341,10 +1438,11 @@
1341 1438 * The Gateworks System Controller implements a boot
1342 1439 * watchdog (always enabled) as a workaround for IMX6 boot related
1343 1440 * errata such as:
1344   - * ERR005768 - no fix
1345   - * ERR006282 - fixed in silicon r1.3
  1441 + * ERR005768 - no fix scheduled
  1442 + * ERR006282 - fixed in silicon r1.2
1346 1443 * ERR007117 - fixed in silicon r1.3
1347 1444 * ERR007220 - fixed in silicon r1.3
  1445 + * ERR007926 - no fix scheduled
1348 1446 * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1349 1447 *
1350 1448 * Disable the boot watchdog and display/clear the timeout flag if set
board/gateworks/gw_ventana/gw_ventana_spl.c
Diff comments   View file @ e38b15b
... ... @@ -201,55 +201,79 @@
201 201 .trasmin = 3500,
202 202 };
203 203  
204   -/* GW54xx specific calibration */
205   -static struct mx6_mmdc_calibration gw54xxq_mmdc_calib = {
  204 +/* MT41K256M16HA-125 */
  205 +static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
  206 + .mem_speed = 1600,
  207 + .density = 4,
  208 + .width = 16,
  209 + .banks = 8,
  210 + .rowaddr = 15,
  211 + .coladdr = 10,
  212 + .pagesz = 2,
  213 + .trcd = 1375,
  214 + .trcmin = 4875,
  215 + .trasmin = 3500,
  216 +};
  217 +
  218 +/*
  219 + * calibration - these are the various CPU/DDR3 combinations we support
  220 + */
  221 +
  222 +static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
206 223 /* write leveling calibration determine */
207   - .p0_mpwldectrl0 = 0x00190018,
208   - .p0_mpwldectrl1 = 0x0021001D,
209   - .p1_mpwldectrl0 = 0x00160027,
210   - .p1_mpwldectrl1 = 0x0012001E,
  224 + .p0_mpwldectrl0 = 0x00190017,
  225 + .p0_mpwldectrl1 = 0x00140026,
211 226 /* Read DQS Gating calibration */
212   - .p0_mpdgctrl0 = 0x43370346,
213   - .p0_mpdgctrl1 = 0x032A0321,
214   - .p1_mpdgctrl0 = 0x433A034D,
215   - .p1_mpdgctrl1 = 0x032F0235,
  227 + .p0_mpdgctrl0 = 0x43380347,
  228 + .p0_mpdgctrl1 = 0x433C034D,
216 229 /* Read Calibration: DQS delay relative to DQ read access */
217 230 .p0_mprddlctl = 0x3C313539,
218   - .p1_mprddlctl = 0x37333140,
219 231 /* Write Calibration: DQ/DM delay relative to DQS write access */
220   - .p0_mpwrdlctl = 0x37393C38,
221   - .p1_mpwrdlctl = 0x42334538,
  232 + .p0_mpwrdlctl = 0x36393C39,
222 233 };
223 234  
224   -/* GW53xx specific calibration */
225   -static struct mx6_mmdc_calibration gw53xxq_mmdc_calib = {
  235 +static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
226 236 /* write leveling calibration determine */
227   - .p0_mpwldectrl0 = 0x00160013,
228   - .p0_mpwldectrl1 = 0x00090024,
229   - .p1_mpwldectrl0 = 0x001F0018,
230   - .p1_mpwldectrl1 = 0x000C001C,
  237 + .p0_mpwldectrl0 = 0x003C003C,
  238 + .p0_mpwldectrl1 = 0x001F002A,
231 239 /* Read DQS Gating calibration */
232   - .p0_mpdgctrl0 = 0x433A034C,
233   - .p0_mpdgctrl1 = 0x0336032F,
234   - .p1_mpdgctrl0 = 0x4343034A,
235   - .p1_mpdgctrl1 = 0x03370222,
  240 + .p0_mpdgctrl0 = 0x42410244,
  241 + .p0_mpdgctrl1 = 0x4234023A,
236 242 /* Read Calibration: DQS delay relative to DQ read access */
237   - .p0_mprddlctl = 0x3F343638,
238   - .p1_mprddlctl = 0x38373442,
  243 + .p0_mprddlctl = 0x484A4C4B,
239 244 /* Write Calibration: DQ/DM delay relative to DQS write access */
240   - .p0_mpwrdlctl = 0x343A3E39,
241   - .p1_mpwrdlctl = 0x44344239,
  245 + .p0_mpwrdlctl = 0x33342B32,
242 246 };
243   -static struct mx6_mmdc_calibration gw53xxdl_mmdc_calib = {
  247 +
  248 +static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
244 249 /* write leveling calibration determine */
  250 + .p0_mpwldectrl0 = 0x00190017,
  251 + .p0_mpwldectrl1 = 0x00140026,
  252 + .p1_mpwldectrl0 = 0x0021001C,
  253 + .p1_mpwldectrl1 = 0x0011001D,
  254 + /* Read DQS Gating calibration */
  255 + .p0_mpdgctrl0 = 0x43380347,
  256 + .p0_mpdgctrl1 = 0x433C034D,
  257 + .p1_mpdgctrl0 = 0x032C0324,
  258 + .p1_mpdgctrl1 = 0x03310232,
  259 + /* Read Calibration: DQS delay relative to DQ read access */
  260 + .p0_mprddlctl = 0x3C313539,
  261 + .p1_mprddlctl = 0x37343141,
  262 + /* Write Calibration: DQ/DM delay relative to DQS write access */
  263 + .p0_mpwrdlctl = 0x36393C39,
  264 + .p1_mpwrdlctl = 0x42344438,
  265 +};
  266 +
  267 +static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
  268 + /* write leveling calibration determine */
245 269 .p0_mpwldectrl0 = 0x003C003C,
246   - .p0_mpwldectrl1 = 0x00330038,
247   - .p1_mpwldectrl0 = 0x001F002A,
  270 + .p0_mpwldectrl1 = 0x001F002A,
  271 + .p1_mpwldectrl0 = 0x00330038,
248 272 .p1_mpwldectrl1 = 0x0022003F,
249 273 /* Read DQS Gating calibration */
250 274 .p0_mpdgctrl0 = 0x42410244,
251   - .p0_mpdgctrl1 = 0x022D022D,
252   - .p1_mpdgctrl0 = 0x4234023A,
  275 + .p0_mpdgctrl1 = 0x4234023A,
  276 + .p1_mpdgctrl0 = 0x022D022D,
253 277 .p1_mpdgctrl1 = 0x021C0228,
254 278 /* Read Calibration: DQS delay relative to DQ read access */
255 279 .p0_mprddlctl = 0x484A4C4B,
256 280  
257 281  
258 282  
259 283  
260 284  
261 285  
262 286  
263 287  
264 288  
265 289  
266 290  
... ... @@ -259,51 +283,42 @@
259 283 .p1_mpwrdlctl = 0x3933332B,
260 284 };
261 285  
262   -/* GW52xx specific calibration */
263   -static struct mx6_mmdc_calibration gw52xxdl_mmdc_calib = {
  286 +static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
264 287 /* write leveling calibration determine */
265   - .p0_mpwldectrl0 = 0x0040003F,
266   - .p0_mpwldectrl1 = 0x00370037,
  288 + .p0_mpwldectrl0 = 0x001E001A,
  289 + .p0_mpwldectrl1 = 0x0026001F,
267 290 /* Read DQS Gating calibration */
268   - .p0_mpdgctrl0 = 0x42420244,
269   - .p0_mpdgctrl1 = 0x022F022F,
  291 + .p0_mpdgctrl0 = 0x43370349,
  292 + .p0_mpdgctrl1 = 0x032D0327,
270 293 /* Read Calibration: DQS delay relative to DQ read access */
271   - .p0_mprddlctl = 0x49464B4A,
  294 + .p0_mprddlctl = 0x3D303639,
272 295 /* Write Calibration: DQ/DM delay relative to DQS write access */
273   - .p0_mpwrdlctl = 0x32362C32,
  296 + .p0_mpwrdlctl = 0x32363934,
274 297 };
275 298  
276   -/* GW51xx specific calibration */
277   -static struct mx6_mmdc_calibration gw51xxq_mmdc_calib = {
  299 +static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
278 300 /* write leveling calibration determine */
279   - .p0_mpwldectrl0 = 0x00150016,
280   - .p0_mpwldectrl1 = 0x001F0017,
  301 + .p0_mpwldectrl0 = 0X00220021,
  302 + .p0_mpwldectrl1 = 0X00200030,
  303 + .p1_mpwldectrl0 = 0X002D0027,
  304 + .p1_mpwldectrl1 = 0X00150026,
281 305 /* Read DQS Gating calibration */
282   - .p0_mpdgctrl0 = 0x433D034D,
283   - .p0_mpdgctrl1 = 0x033D032F,
  306 + .p0_mpdgctrl0 = 0x43330342,
  307 + .p0_mpdgctrl1 = 0x0339034A,
  308 + .p1_mpdgctrl0 = 0x032F0325,
  309 + .p1_mpdgctrl1 = 0x032F022E,
284 310 /* Read Calibration: DQS delay relative to DQ read access */
285   - .p0_mprddlctl = 0x3F313639,
  311 + .p0_mprddlctl = 0X3A2E3437,
  312 + .p1_mprddlctl = 0X35312F3F,
286 313 /* Write Calibration: DQ/DM delay relative to DQS write access */
287   - .p0_mpwrdlctl = 0x33393F36,
  314 + .p0_mpwrdlctl = 0X33363B37,
  315 + .p1_mpwrdlctl = 0X40304239,
288 316 };
289 317  
290   -static struct mx6_mmdc_calibration gw51xxdl_mmdc_calib = {
291   - /* write leveling calibration determine */
292   - .p0_mpwldectrl0 = 0x003D003F,
293   - .p0_mpwldectrl1 = 0x002F0038,
294   - /* Read DQS Gating calibration */
295   - .p0_mpdgctrl0 = 0x423A023A,
296   - .p0_mpdgctrl1 = 0x022A0228,
297   - /* Read Calibration: DQS delay relative to DQ read access */
298   - .p0_mprddlctl = 0x48494C4C,
299   - /* Write Calibration: DQ/DM delay relative to DQS write access */
300   - .p0_mpwrdlctl = 0x34352D31,
301   -};
302   -
303   -static void spl_dram_init(int width, int size, int board_model)
  318 +static void spl_dram_init(int width, int size_mb, int board_model)
304 319 {
305   - struct mx6_ddr3_cfg *mem = &mt41k128m16jt_125;
306   - struct mx6_mmdc_calibration *calib;
  320 + struct mx6_ddr3_cfg *mem = NULL;
  321 + struct mx6_mmdc_calibration *calib = NULL;
307 322 struct mx6_ddr_sysinfo sysinfo = {
308 323 /* width of data bus:0=16,1=32,2=64 */
309 324 .dsize = width/32,
310 325  
311 326  
312 327  
313 328  
314 329  
... ... @@ -329,29 +344,43 @@
329 344 /*
330 345 * MMDC Calibration requires the following data:
331 346 * mx6_mmdc_calibration - board-specific calibration (routing delays)
  347 + * these calibration values depend on board routing, SoC, and DDR
332 348 * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
333 349 * mx6_ddr_cfg - chip specific timing/layout details
334 350 */
335   - switch (board_model) {
336   - default:
337   - case GW51xx:
  351 + if (width == 32 && size_mb == 512) {
  352 + mem = &mt41k128m16jt_125;
338 353 if (is_cpu_type(MXC_CPU_MX6Q))
339   - calib = &gw51xxq_mmdc_calib;
  354 + calib = &mx6dq_128x32_mmdc_calib;
340 355 else
341   - calib = &gw51xxdl_mmdc_calib;
342   - break;
343   - case GW52xx:
344   - calib = &gw52xxdl_mmdc_calib;
345   - break;
346   - case GW53xx:
  356 + calib = &mx6sdl_128x32_mmdc_calib;
  357 + debug("2gB density\n");
  358 + } else if (width == 64 && size_mb == 1024) {
  359 + mem = &mt41k128m16jt_125;
347 360 if (is_cpu_type(MXC_CPU_MX6Q))
348   - calib = &gw53xxq_mmdc_calib;
  361 + calib = &mx6dq_128x64_mmdc_calib;
349 362 else
350   - calib = &gw53xxdl_mmdc_calib;
351   - break;
352   - case GW54xx:
353   - calib = &gw54xxq_mmdc_calib;
354   - break;
  363 + calib = &mx6sdl_128x64_mmdc_calib;
  364 + debug("2gB density\n");
  365 + } else if (width == 32 && size_mb == 1024) {
  366 + mem = &mt41k256m16ha_125;
  367 + if (is_cpu_type(MXC_CPU_MX6Q))
  368 + calib = &mx6dq_256x32_mmdc_calib;
  369 + debug("4gB density\n");
  370 + } else if (width == 64 && size_mb == 2048) {
  371 + mem = &mt41k256m16ha_125;
  372 + if (is_cpu_type(MXC_CPU_MX6Q))
  373 + calib = &mx6dq_256x64_mmdc_calib;
  374 + debug("4gB density\n");
  375 + }
  376 +
  377 + if (!mem) {
  378 + puts("Error: Invalid Memory Configuration\n");
  379 + hang();
  380 + }
  381 + if (!calib) {
  382 + puts("Error: Invalid Board Calibration Configuration\n");
  383 + hang();
355 384 }
356 385  
357 386 if (is_cpu_type(MXC_CPU_MX6Q))
board/gateworks/gw_ventana/ventana_eeprom.h
Diff comments   View file @ e38b15b
... ... @@ -109,6 +109,7 @@
109 109 GW52xx,
110 110 GW53xx,
111 111 GW54xx,
  112 + GW552x,
112 113 GW_UNKNOWN,
113 114 GW_BADCRC,
114 115 };
configs/cm_fx6_defconfig
Diff comments   View file @ e38b15b
  1 +CONFIG_SPL=y
  2 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/compulab/cm_fx6/imximage.cfg,MX6QDL,SPL"
  3 ++S:CONFIG_ARM=y
  4 ++S:CONFIG_TARGET_CM_FX6=y
configs/mx6dlsabresd_defconfig
Diff comments   View file @ e38b15b
1   -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL"
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL"
2 2 CONFIG_ARM=y
3 3 CONFIG_TARGET_MX6SABRESD=y
... ... @@ -120,7 +120,7 @@
120 120 DATA 4 0x73FA88a0 0x200
121 121  
122 122 The processor support up to 60 register programming commands for IMXIMAGE_VERSION 1
123   -and 121 register programming commands for IMXIMAGE_VERSION 2.
  123 +and 220 register programming commands for IMXIMAGE_VERSION 2.
124 124 An error is generated if more commands are found in the configuration file.
125 125  
126 126 3. All commands are optional to program.
drivers/block/dwc_ahsata.c
Diff comments   View file @ e38b15b
... ... @@ -864,6 +864,23 @@
864 864 return blkcnt;
865 865 }
866 866  
  867 +int sata_port_status(int dev, int port)
  868 +{
  869 + struct sata_port_regs *port_mmio;
  870 + struct ahci_probe_ent *probe_ent = NULL;
  871 +
  872 + if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
  873 + return -EINVAL;
  874 +
  875 + if (sata_dev_desc[dev].priv == NULL)
  876 + return -ENODEV;
  877 +
  878 + probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
  879 + port_mmio = (struct sata_port_regs *)probe_ent->port[port].port_mmio;
  880 +
  881 + return readl(&(port_mmio->ssts)) && SATA_PORT_SSTS_DET_MASK;
  882 +}
  883 +
867 884 /*
868 885 * SATA interface between low level driver and command layer
869 886 */
drivers/net/fec_mxc.c
Diff comments   View file @ e38b15b
... ... @@ -28,6 +28,14 @@
28 28 */
29 29 #define FEC_XFER_TIMEOUT 5000
30 30  
  31 +/*
  32 + * The standard 32-byte DMA alignment does not work on mx6solox, which requires
  33 + * 64-byte alignment in the DMA RX FEC buffer.
  34 + * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
  35 + * satisfies the alignment on other SoCs (32-bytes)
  36 + */
  37 +#define FEC_DMA_RX_MINALIGN 64
  38 +
31 39 #ifndef CONFIG_MII
32 40 #error "CONFIG_MII has to be defined!"
33 41 #endif
34 42  
35 43  
36 44  
... ... @@ -711,13 +719,37 @@
711 719 break;
712 720 }
713 721  
714   - if (!timeout)
  722 + if (!timeout) {
715 723 ret = -EINVAL;
  724 + goto out;
  725 + }
716 726  
717   - invalidate_dcache_range(addr, addr + size);
718   - if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY)
  727 + /*
  728 + * The TDAR bit is cleared when the descriptors are all out from TX
  729 + * but on mx6solox we noticed that the READY bit is still not cleared
  730 + * right after TDAR.
  731 + * These are two distinct signals, and in IC simulation, we found that
  732 + * TDAR always gets cleared prior than the READY bit of last BD becomes
  733 + * cleared.
  734 + * In mx6solox, we use a later version of FEC IP. It looks like that
  735 + * this intrinsic behaviour of TDAR bit has changed in this newer FEC
  736 + * version.
  737 + *
  738 + * Fix this by polling the READY bit of BD after the TDAR polling,
  739 + * which covers the mx6solox case and does not harm the other SoCs.
  740 + */
  741 + timeout = FEC_XFER_TIMEOUT;
  742 + while (--timeout) {
  743 + invalidate_dcache_range(addr, addr + size);
  744 + if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
  745 + FEC_TBD_READY))
  746 + break;
  747 + }
  748 +
  749 + if (!timeout)
719 750 ret = -EINVAL;
720 751  
  752 +out:
721 753 debug("fec_send: status 0x%x index %d ret %i\n",
722 754 readw(&fec->tbd_base[fec->tbd_index].status),
723 755 fec->tbd_index, ret);
724 756  
... ... @@ -881,9 +913,9 @@
881 913 /* Allocate RX buffers. */
882 914  
883 915 /* Maximum RX buffer size. */
884   - size = roundup(FEC_MAX_PKT_SIZE, ARCH_DMA_MINALIGN);
  916 + size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
885 917 for (i = 0; i < FEC_RBD_NUM; i++) {
886   - data = memalign(ARCH_DMA_MINALIGN, size);
  918 + data = memalign(FEC_DMA_RX_MINALIGN, size);
887 919 if (!data) {
888 920 printf("%s: error allocating rxbuf %d\n", __func__, i);
889 921 goto err_ring;
... ... @@ -648,6 +648,10 @@
648 648 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
649 649 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
650 650  
  651 +#ifdef CONFIG_PCI_FIXUP_DEV
  652 + board_pci_fixup_dev(hose, dev, vendor, device, class);
  653 +#endif
  654 +
651 655 #ifdef CONFIG_PCI_SCAN_SHOW
652 656 indent++;
653 657  
drivers/pci/pcie_imx.c
Diff comments   View file @ e38b15b
... ... @@ -23,13 +23,20 @@
23 23 #define PCI_ACCESS_READ 0
24 24 #define PCI_ACCESS_WRITE 1
25 25  
  26 +#ifdef CONFIG_MX6SX
  27 +#define MX6_DBI_ADDR 0x08ffc000
  28 +#define MX6_IO_ADDR 0x08000000
  29 +#define MX6_MEM_ADDR 0x08100000
  30 +#define MX6_ROOT_ADDR 0x08f00000
  31 +#else
26 32 #define MX6_DBI_ADDR 0x01ffc000
27   -#define MX6_DBI_SIZE 0x4000
28 33 #define MX6_IO_ADDR 0x01000000
29   -#define MX6_IO_SIZE 0x100000
30 34 #define MX6_MEM_ADDR 0x01100000
31   -#define MX6_MEM_SIZE 0xe00000
32 35 #define MX6_ROOT_ADDR 0x01f00000
  36 +#endif
  37 +#define MX6_DBI_SIZE 0x4000
  38 +#define MX6_IO_SIZE 0x100000
  39 +#define MX6_MEM_SIZE 0xe00000
33 40 #define MX6_ROOT_SIZE 0xfc000
34 41  
35 42 /* PCIe Port Logic registers (memory-mapped) */
... ... @@ -57,6 +64,8 @@
57 64 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
58 65 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
59 66  
  67 +#define PCIE_PHY_PUP_REQ (1 << 7)
  68 +
60 69 /* iATU registers */
61 70 #define PCIE_ATU_VIEWPORT 0x900
62 71 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
63 72  
64 73  
... ... @@ -421,9 +430,19 @@
421 430 static int imx6_pcie_assert_core_reset(void)
422 431 {
423 432 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  433 +#if defined(CONFIG_MX6SX)
  434 + struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
424 435  
  436 + /* SSP_EN is not used on MX6SX anymore */
  437 + setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
  438 + /* Force PCIe PHY reset */
  439 + setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
  440 + /* Power up PCIe PHY */
  441 + setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
  442 +#else
425 443 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
426 444 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
  445 +#endif
427 446  
428 447 return 0;
429 448 }
... ... @@ -441,6 +460,12 @@
441 460 IOMUXC_GPR12_LOS_LEVEL_MASK,
442 461 IOMUXC_GPR12_LOS_LEVEL_9);
443 462  
  463 +#ifdef CONFIG_MX6SX
  464 + clrsetbits_le32(&iomuxc_regs->gpr[12],
  465 + IOMUXC_GPR12_RX_EQ_MASK,
  466 + IOMUXC_GPR12_RX_EQ_2);
  467 +#endif
  468 +
444 469 writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
445 470 (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
446 471 (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
447 472  
... ... @@ -517,9 +542,16 @@
517 542 */
518 543 mdelay(50);
519 544  
  545 +#if defined(CONFIG_MX6SX)
  546 + /* SSP_EN is not used on MX6SX anymore */
  547 + clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
  548 + /* Clear PCIe PHY reset bit */
  549 + clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
  550 +#else
520 551 /* Enable PCIe */
521 552 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
522 553 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
  554 +#endif
523 555  
524 556 imx6_pcie_toggle_reset();
525 557  
drivers/serial/serial_lpuart.c
Diff comments   View file @ e38b15b
... ... @@ -14,8 +14,13 @@
14 14  
15 15 #define US1_TDRE (1 << 7)
16 16 #define US1_RDRF (1 << 5)
  17 +#define US1_OR (1 << 3)
17 18 #define UC2_TE (1 << 3)
18 19 #define UC2_RE (1 << 2)
  20 +#define CFIFO_TXFLUSH (1 << 7)
  21 +#define CFIFO_RXFLUSH (1 << 6)
  22 +#define SFIFO_RXOF (1 << 2)
  23 +#define SFIFO_RXUF (1 << 0)
19 24  
20 25 #define STAT_LBKDIF (1 << 31)
21 26 #define STAT_RXEDGIF (1 << 30)
22 27  
... ... @@ -62,14 +67,10 @@
62 67  
63 68 static int lpuart_serial_getc(void)
64 69 {
65   - u8 status;
66   -
67   - while (!(__raw_readb(&base->us1) & US1_RDRF))
  70 + while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
68 71 WATCHDOG_RESET();
69 72  
70   - status = __raw_readb(&base->us1);
71   - status |= US1_RDRF;
72   - __raw_writeb(status, &base->us1);
  73 + barrier();
73 74  
74 75 return __raw_readb(&base->ud);
75 76 }
... ... @@ -111,6 +112,12 @@
111 112  
112 113 __raw_writeb(0, &base->umodem);
113 114 __raw_writeb(0, &base->uc1);
  115 +
  116 + /* Disable FIFO and flush buffer */
  117 + __raw_writeb(0x0, &base->upfifo);
  118 + __raw_writeb(0x0, &base->utwfifo);
  119 + __raw_writeb(0x1, &base->urwfifo);
  120 + __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
114 121  
115 122 /* provide data bits, parity, stop bit, etc */
116 123  
include/configs/cm_fx6.h
Diff comments   View file @ e38b15b
  1 +/*
  2 + * Config file for Compulab CM-FX6 board
  3 + *
  4 + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
  5 + *
  6 + * Author: Nikita Kiryanov <nikita@compulab.co.il>
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#ifndef __CONFIG_CM_FX6_H
  12 +#define __CONFIG_CM_FX6_H
  13 +
  14 +#include <asm/arch/imx-regs.h>
  15 +#include <config_distro_defaults.h>
  16 +#include "mx6_common.h"
  17 +
  18 +/* Machine config */
  19 +#define CONFIG_MX6
  20 +#define CONFIG_SYS_LITTLE_ENDIAN
  21 +#define CONFIG_MACH_TYPE 4273
  22 +#define CONFIG_SYS_HZ 1000
  23 +
  24 +/* Display information on boot */
  25 +#define CONFIG_DISPLAY_CPUINFO
  26 +#define CONFIG_DISPLAY_BOARDINFO
  27 +#define CONFIG_TIMESTAMP
  28 +
  29 +/* CMD */
  30 +#include <config_cmd_default.h>
  31 +#define CONFIG_CMD_GREPENV
  32 +#undef CONFIG_CMD_FLASH
  33 +#undef CONFIG_CMD_LOADB
  34 +#undef CONFIG_CMD_LOADS
  35 +#undef CONFIG_CMD_XIMG
  36 +#undef CONFIG_CMD_FPGA
  37 +#undef CONFIG_CMD_IMLS
  38 +
  39 +/* MMC */
  40 +#define CONFIG_MMC
  41 +#define CONFIG_CMD_MMC
  42 +#define CONFIG_GENERIC_MMC
  43 +#define CONFIG_FSL_ESDHC
  44 +#define CONFIG_FSL_USDHC
  45 +#define CONFIG_SYS_FSL_USDHC_NUM 3
  46 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
  47 +
  48 +/* RAM */
  49 +#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
  50 +#define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR
  51 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  52 +#define CONFIG_NR_DRAM_BANKS 2
  53 +#define CONFIG_SYS_MEMTEST_START 0x10000000
  54 +#define CONFIG_SYS_MEMTEST_END 0x10010000
  55 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
  56 +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
  57 +#define CONFIG_SYS_INIT_SP_OFFSET \
  58 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  59 +#define CONFIG_SYS_INIT_SP_ADDR \
  60 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  61 +
  62 +/* Serial console */
  63 +#define CONFIG_MXC_UART
  64 +#define CONFIG_MXC_UART_BASE UART4_BASE
  65 +#define CONFIG_BAUDRATE 115200
  66 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
  67 +
  68 +/* Shell */
  69 +#define CONFIG_SYS_PROMPT "CM-FX6 # "
  70 +#define CONFIG_SYS_CBSIZE 1024
  71 +#define CONFIG_SYS_MAXARGS 16
  72 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  73 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  74 + sizeof(CONFIG_SYS_PROMPT) + 16)
  75 +
  76 +/* SPI flash */
  77 +#define CONFIG_SYS_NO_FLASH
  78 +#define CONFIG_CMD_SF
  79 +#define CONFIG_SF_DEFAULT_BUS 0
  80 +#define CONFIG_SF_DEFAULT_CS 0
  81 +#define CONFIG_SF_DEFAULT_SPEED 25000000
  82 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
  83 +
  84 +/* Environment */
  85 +#define CONFIG_ENV_OVERWRITE
  86 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  87 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  88 +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
  89 +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
  90 +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
  91 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
  92 +#define CONFIG_ENV_SIZE (8 * 1024)
  93 +#define CONFIG_ENV_OFFSET (768 * 1024)
  94 +
  95 +#define CONFIG_EXTRA_ENV_SETTINGS \
  96 + "kernel=uImage-cm-fx6\0" \
  97 + "autoload=no\0" \
  98 + "loadaddr=0x10800000\0" \
  99 + "fdtaddr=0x11000000\0" \
  100 + "console=ttymxc3,115200\0" \
  101 + "ethprime=FEC0\0" \
  102 + "bootscr=boot.scr\0" \
  103 + "bootm_low=18000000\0" \
  104 + "video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \
  105 + "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \
  106 + "fdtfile=cm-fx6.dtb\0" \
  107 + "doboot=bootm ${loadaddr}\0" \
  108 + "loadfdt=false\0" \
  109 + "setboottypez=setenv kernel zImage-cm-fx6;" \
  110 + "setenv doboot bootz ${loadaddr} - ${fdtaddr};" \
  111 + "setenv loadfdt true;\0" \
  112 + "setboottypem=setenv kernel uImage-cm-fx6;" \
  113 + "setenv doboot bootm ${loadaddr};" \
  114 + "setenv loadfdt false;\0"\
  115 + "run_eboot=echo Starting EBOOT ...; "\
  116 + "mmc dev ${mmcdev} && " \
  117 + "mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \
  118 + "mmcdev=2\0" \
  119 + "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
  120 + "loadmmcbootscript=load mmc ${mmcdev} ${loadaddr} ${bootscr}\0" \
  121 + "mmcbootscript=echo Running bootscript from mmc ...; "\
  122 + "source ${loadaddr}\0" \
  123 + "mmcargs=setenv bootargs console=${console} " \
  124 + "root=${mmcroot} " \
  125 + "${video}\0" \
  126 + "mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \
  127 + "mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
  128 + "mmcboot=echo Booting from mmc ...; " \
  129 + "run mmcargs; " \
  130 + "run doboot\0" \
  131 + "satadev=0\0" \
  132 + "sataroot=/dev/sda2 rw rootwait\0" \
  133 + "sataargs=setenv bootargs console=${console} " \
  134 + "root=${sataroot} " \
  135 + "${video}\0" \
  136 + "loadsatabootscript=load sata ${satadev} ${loadaddr} ${bootscr}\0" \
  137 + "satabootscript=echo Running bootscript from sata ...; " \
  138 + "source ${loadaddr}\0" \
  139 + "sataloadkernel=load sata ${satadev} ${loadaddr} ${kernel}\0" \
  140 + "sataloadfdt=load sata ${satadev} ${fdtaddr} ${fdtfile}\0" \
  141 + "sataboot=echo Booting from sata ...; "\
  142 + "run sataargs; " \
  143 + "run doboot\0" \
  144 + "nandroot=/dev/mtdblock4 rw\0" \
  145 + "nandrootfstype=ubifs\0" \
  146 + "nandargs=setenv bootargs console=${console} " \
  147 + "root=${nandroot} " \
  148 + "rootfstype=${nandrootfstype} " \
  149 + "${video}\0" \
  150 + "nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \
  151 + "nandboot=echo Booting from nand ...; " \
  152 + "run nandargs; " \
  153 + "nand read ${loadaddr} 0 780000; " \
  154 + "if ${loadfdt}; then " \
  155 + "run nandloadfdt;" \
  156 + "fi; " \
  157 + "run doboot\0" \
  158 + "boot=mmc dev ${mmcdev}; " \
  159 + "if mmc rescan; then " \
  160 + "if run loadmmcbootscript; then " \
  161 + "run mmcbootscript;" \
  162 + "else " \
  163 + "if run mmcloadkernel; then " \
  164 + "if ${loadfdt}; then " \
  165 + "run mmcloadfdt;" \
  166 + "fi;" \
  167 + "run mmcboot;" \
  168 + "fi;" \
  169 + "fi;" \
  170 + "fi;" \
  171 + "if sata init; then " \
  172 + "if run loadsatabootscript; then " \
  173 + "run satabootscript;" \
  174 + "else "\
  175 + "if run sataloadkernel; then " \
  176 + "if ${loadfdt}; then " \
  177 + "run sataloadfdt; " \
  178 + "fi;" \
  179 + "run sataboot;" \
  180 + "fi;" \
  181 + "fi;" \
  182 + "fi;" \
  183 + "run nandboot\0"
  184 +
  185 +#define CONFIG_BOOTCOMMAND \
  186 + "run setboottypem; run boot"
  187 +
  188 +/* SPI */
  189 +#define CONFIG_SPI
  190 +#define CONFIG_MXC_SPI
  191 +#define CONFIG_SPI_FLASH
  192 +#define CONFIG_SPI_FLASH_ATMEL
  193 +#define CONFIG_SPI_FLASH_EON
  194 +#define CONFIG_SPI_FLASH_GIGADEVICE
  195 +#define CONFIG_SPI_FLASH_MACRONIX
  196 +#define CONFIG_SPI_FLASH_SPANSION
  197 +#define CONFIG_SPI_FLASH_STMICRO
  198 +#define CONFIG_SPI_FLASH_SST
  199 +#define CONFIG_SPI_FLASH_WINBOND
  200 +
  201 +/* NAND */
  202 +#ifndef CONFIG_SPL_BUILD
  203 +#define CONFIG_CMD_NAND
  204 +#define CONFIG_SYS_NAND_BASE 0x40000000
  205 +#define CONFIG_SYS_NAND_MAX_CHIPS 1
  206 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  207 +#define CONFIG_NAND_MXS
  208 +#define CONFIG_SYS_NAND_ONFI_DETECTION
  209 +/* APBH DMA is required for NAND support */
  210 +#define CONFIG_APBH_DMA
  211 +#define CONFIG_APBH_DMA_BURST
  212 +#define CONFIG_APBH_DMA_BURST8
  213 +#endif
  214 +
  215 +/* Ethernet */
  216 +#define CONFIG_FEC_MXC
  217 +#define CONFIG_FEC_MXC_PHYADDR 0
  218 +#define CONFIG_FEC_XCV_TYPE RGMII
  219 +#define IMX_FEC_BASE ENET_BASE_ADDR
  220 +#define CONFIG_PHYLIB
  221 +#define CONFIG_PHY_ATHEROS
  222 +#define CONFIG_MII
  223 +#define CONFIG_ETHPRIME "FEC0"
  224 +#define CONFIG_ARP_TIMEOUT 200UL
  225 +#define CONFIG_NETMASK 255.255.255.0
  226 +#define CONFIG_NET_RETRY_COUNT 5
  227 +
  228 +/* USB */
  229 +#define CONFIG_CMD_USB
  230 +#define CONFIG_USB_EHCI
  231 +#define CONFIG_USB_EHCI_MX6
  232 +#define CONFIG_USB_STORAGE
  233 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
  234 +#define CONFIG_MXC_USB_FLAGS 0
  235 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  236 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
  237 +
  238 +/* I2C */
  239 +#define CONFIG_CMD_I2C
  240 +#define CONFIG_SYS_I2C
  241 +#define CONFIG_SYS_I2C_MXC
  242 +#define CONFIG_SYS_I2C_SPEED 100000
  243 +#define CONFIG_SYS_MXC_I2C3_SPEED 400000
  244 +
  245 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  246 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  247 +#define CONFIG_SYS_I2C_EEPROM_BUS 2
  248 +
  249 +/* SATA */
  250 +#define CONFIG_CMD_SATA
  251 +#define CONFIG_SYS_SATA_MAX_DEVICE 1
  252 +#define CONFIG_LIBATA
  253 +#define CONFIG_LBA48
  254 +#define CONFIG_DWC_AHSATA
  255 +#define CONFIG_DWC_AHSATA_PORT_ID 0
  256 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
  257 +
  258 +/* GPIO */
  259 +#define CONFIG_MXC_GPIO
  260 +
  261 +/* Boot */
  262 +#define CONFIG_ZERO_BOOTDELAY_CHECK
  263 +#define CONFIG_LOADADDR 0x10800000
  264 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  265 +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  266 +#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
  267 +#define CONFIG_SETUP_MEMORY_TAGS
  268 +#define CONFIG_INITRD_TAG
  269 +#define CONFIG_REVISION_TAG
  270 +#define CONFIG_SERIAL_TAG
  271 +
  272 +/* misc */
  273 +#define CONFIG_SYS_GENERIC_BOARD
  274 +#define CONFIG_STACKSIZE (128 * 1024)
  275 +#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
  276 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
  277 +#define CONFIG_OF_BOARD_SETUP
  278 +
  279 +/* SPL */
  280 +#include "imx6_spl.h"
  281 +#define CONFIG_SPL_BOARD_INIT
  282 +#define CONFIG_SPL_MMC_SUPPORT
  283 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 /* offset 64 kb */
  284 +#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS / 2 * 1024)
  285 +#define CONFIG_SPL_SPI_SUPPORT
  286 +#define CONFIG_SPL_SPI_FLASH_SUPPORT
  287 +#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
  288 +#define CONFIG_SPL_SPI_LOAD
  289 +
  290 +#endif /* __CONFIG_CM_FX6_H */
include/configs/cm_t335.h
Diff comments   View file @ e38b15b
... ... @@ -107,6 +107,7 @@
107 107 /* I2C Configuration */
108 108 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
109 109 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  110 +#define CONFIG_SYS_I2C_EEPROM_BUS 0
110 111  
111 112 /* SPL */
112 113 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
include/configs/cm_t35.h
Diff comments   View file @ e38b15b
... ... @@ -135,6 +135,7 @@
135 135 #define CONFIG_SYS_I2C_OMAP34XX
136 136 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
137 137 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  138 +#define CONFIG_SYS_I2C_EEPROM_BUS 0
138 139 #define CONFIG_I2C_MULTI_BUS
139 140  
140 141 /*
include/configs/cm_t54.h
Diff comments   View file @ e38b15b
... ... @@ -30,6 +30,7 @@
30 30 #define CONFIG_SYS_I2C_OMAP34XX
31 31 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
32 32 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  33 +#define CONFIG_SYS_I2C_EEPROM_BUS 0
33 34  
34 35 /* Enable SD/MMC CD and WP GPIOs */
35 36 #define OMAP_HSMMC_USE_GPIO
include/configs/gw_ventana.h
Diff comments   View file @ e38b15b
... ... @@ -141,6 +141,7 @@
141 141 #define CONFIG_PCI
142 142 #define CONFIG_PCI_PNP
143 143 #define CONFIG_PCI_SCAN_SHOW
  144 +#define CONFIG_PCI_FIXUP_DEV
144 145 #define CONFIG_PCIE_IMX
145 146 #endif
146 147  
include/configs/mx6qarm2.h
Diff comments   View file @ e38b15b
... ... @@ -23,6 +23,8 @@
23 23 #define CONFIG_SETUP_MEMORY_TAGS
24 24 #define CONFIG_INITRD_TAG
25 25  
  26 +#define CONFIG_SYS_GENERIC_BOARD
  27 +
26 28 /* Size of malloc() pool */
27 29 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
28 30  
include/configs/mx6qsabreauto.h
Diff comments   View file @ e38b15b
... ... @@ -45,8 +45,5 @@
45 45 #define CONFIG_SYS_I2C_MXC
46 46 #define CONFIG_SYS_I2C_SPEED 100000
47 47  
48   -#define CONFIG_OF_SEPARATE
49   -#define CONFIG_DEFAULT_DEVICE_TREE imx6q-sabreauto
50   -
51 48 #endif /* __MX6QSABREAUTO_CONFIG_H */
include/configs/mx6slevk.h
Diff comments   View file @ e38b15b
... ... @@ -26,6 +26,8 @@
26 26 #define CONFIG_INITRD_TAG
27 27 #define CONFIG_REVISION_TAG
28 28  
  29 +#define CONFIG_SYS_GENERIC_BOARD
  30 +
29 31 /* Size of malloc() pool */
30 32 #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
31 33  
include/configs/mx6sxsabresd.h
Diff comments   View file @ e38b15b
... ... @@ -198,6 +198,16 @@
198 198 #define CONFIG_PHYLIB
199 199 #define CONFIG_PHY_ATHEROS
200 200  
  201 +#define CONFIG_CMD_PCI
  202 +#ifdef CONFIG_CMD_PCI
  203 +#define CONFIG_PCI
  204 +#define CONFIG_PCI_PNP
  205 +#define CONFIG_PCI_SCAN_SHOW
  206 +#define CONFIG_PCIE_IMX
  207 +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 1)
  208 +#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 0)
  209 +#endif
  210 +
201 211 /* FLASH and environment organization */
202 212 #define CONFIG_SYS_NO_FLASH
203 213  
include/configs/nitrogen6x.h
Diff comments   View file @ e38b15b
... ... @@ -192,11 +192,11 @@
192 192 "mmcargs=setenv bootargs console=${console},${baudrate} " \
193 193 "root=${mmcroot}\0" \
194 194 "loadbootscript=" \
195   - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \" \
  195 + "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \" \
196 196 "bootscript=echo Running bootscript from mmc ...; " \
197 197 "source\0" \
198   - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
199   - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  198 + "loaduimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
  199 + "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
200 200 "mmcboot=echo Booting from mmc ...; " \
201 201 "run mmcargs; " \
202 202 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
... ... @@ -659,6 +659,13 @@
659 659 extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
660 660 int cap);
661 661  
  662 +#ifdef CONFIG_PCI_FIXUP_DEV
  663 +extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
  664 + unsigned short vendor,
  665 + unsigned short device,
  666 + unsigned short class);
  667 +#endif
  668 +
662 669 const char * pci_class_str(u8 class);
663 670 int pci_last_busno(void);
664 671  
... ... @@ -9,6 +9,7 @@
9 9  
10 10 int sata_initialize(void);
11 11 int __sata_initialize(void);
  12 +int sata_port_status(int dev, int port);
12 13  
13 14 extern block_dev_desc_t sata_dev_desc[];
14 15  
... ... @@ -568,6 +568,13 @@
568 568 /* Parse dcd configuration file */
569 569 dcd_len = parse_cfg_file(imxhdr, params->imagename);
570 570  
  571 + if (imximage_version == IMXIMAGE_V2) {
  572 + if (imximage_init_loadsize < imximage_ivt_offset +
  573 + sizeof(imx_header_v2_t))
  574 + imximage_init_loadsize = imximage_ivt_offset +
  575 + sizeof(imx_header_v2_t);
  576 + }
  577 +
571 578 /* Set the imx header */
572 579 (*set_imx_hdr)(imxhdr, dcd_len, params->ep, imximage_ivt_offset);
573 580  
... ... @@ -8,7 +8,7 @@
8 8 #ifndef _IMXIMAGE_H_
9 9 #define _IMXIMAGE_H_
10 10  
11   -#define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set for v2 */
  11 +#define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */
12 12 #define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */
13 13 #define APP_CODE_BARKER 0xB1
14 14 #define DCD_BARKER 0xB17219E9