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Commit e46fedfeb214d118b9983d11fcc929ed49f5ccd7

Authored by Timur Tabi
Committed by Kumar Gala
1 parent b6c3722dfa
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros 

Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW
macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS.
This is necessary for the assembly-language code that relocates CCSR, since
the assembler does not understand 64-bit constants.

CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the
CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it
should not be defined in a board header file.  Similarly,
CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so
it should also not be defined in the board header file.

CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that
CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT,
and so CCSR will not be relocated.

Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot
builds (e.g. NAND) are required to relocate CCSR only during the last stage
(i.e. the "real" U-Boot).  All other stages should define
CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated.

README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Showing 30 changed files with 170 additions and 277 deletions Side-by-side Diff

... ... @@ -2862,6 +2862,43 @@
2862 2862 and RPXsuper) to be able to adjust the position of
2863 2863 the IMMR register after a reset.
2864 2864  
  2865 +- CONFIG_SYS_CCSRBAR_DEFAULT:
  2866 + Default (power-on reset) physical address of CCSR on Freescale
  2867 + PowerPC SOCs.
  2868 +
  2869 +- CONFIG_SYS_CCSRBAR:
  2870 + Virtual address of CCSR. On a 32-bit build, this is typically
  2871 + the same value as CONFIG_SYS_CCSRBAR_DEFAULT.
  2872 +
  2873 + CONFIG_SYS_DEFAULT_IMMR must also be set to this value,
  2874 + for cross-platform code that uses that macro instead.
  2875 +
  2876 +- CONFIG_SYS_CCSRBAR_PHYS:
  2877 + Physical address of CCSR. CCSR can be relocated to a new
  2878 + physical address, if desired. In this case, this macro should
  2879 + be set to that address. Otherwise, it should be set to the
  2880 + same value as CONFIG_SYS_CCSRBAR_DEFAULT. For example, CCSR
  2881 + is typically relocated on 36-bit builds. It is recommended
  2882 + that this macro be defined via the _HIGH and _LOW macros:
  2883 +
  2884 + #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH
  2885 + * 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW)
  2886 +
  2887 +- CONFIG_SYS_CCSRBAR_PHYS_HIGH:
  2888 + Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS. This value is typically
  2889 + either 0 (32-bit build) or 0xF (36-bit build). This macro is
  2890 + used in assembly code, so it must not contain typecasts or
  2891 + integer size suffixes (e.g. "ULL").
  2892 +
  2893 +- CONFIG_SYS_CCSRBAR_PHYS_LOW:
  2894 + Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS. This macro is
  2895 + used in assembly code, so it must not contain typecasts or
  2896 + integer size suffixes (e.g. "ULL").
  2897 +
  2898 +- CONFIG_SYS_CCSR_DO_NOT_RELOCATE:
  2899 + If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be
  2900 + forced to a value that ensures that CCSR is not relocated.
  2901 +
2865 2902 - Floppy Disk Support:
2866 2903 CONFIG_SYS_FDC_DRIVE_NUMBER
2867 2904  
arch/powerpc/include/asm/config_mpc85xx.h
Diff comments   View file @ e46fedf
... ... @@ -23,6 +23,10 @@
23 23  
24 24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
25 25  
  26 +#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
  27 +#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
  28 +#endif
  29 +
26 30 /* Number of TLB CAM entries we have on FSL Book-E chips */
27 31 #if defined(CONFIG_E500MC)
28 32 #define CONFIG_SYS_NUM_TLBCAMS 64
29 33  
30 34  
31 35  
32 36  
33 37  
34 38  
... ... @@ -34,34 +38,41 @@
34 38 #define CONFIG_MAX_CPUS 1
35 39 #define CONFIG_SYS_FSL_NUM_LAWS 12
36 40 #define CONFIG_SYS_FSL_SEC_COMPAT 2
  41 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
37 42  
38 43 #elif defined(CONFIG_MPC8540)
39 44 #define CONFIG_MAX_CPUS 1
40 45 #define CONFIG_SYS_FSL_NUM_LAWS 8
  46 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
41 47  
42 48 #elif defined(CONFIG_MPC8541)
43 49 #define CONFIG_MAX_CPUS 1
44 50 #define CONFIG_SYS_FSL_NUM_LAWS 8
45 51 #define CONFIG_SYS_FSL_SEC_COMPAT 2
  52 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
46 53  
47 54 #elif defined(CONFIG_MPC8544)
48 55 #define CONFIG_MAX_CPUS 1
49 56 #define CONFIG_SYS_FSL_NUM_LAWS 10
50 57 #define CONFIG_SYS_FSL_SEC_COMPAT 2
  58 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
51 59  
52 60 #elif defined(CONFIG_MPC8548)
53 61 #define CONFIG_MAX_CPUS 1
54 62 #define CONFIG_SYS_FSL_NUM_LAWS 10
55 63 #define CONFIG_SYS_FSL_SEC_COMPAT 2
  64 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
56 65  
57 66 #elif defined(CONFIG_MPC8555)
58 67 #define CONFIG_MAX_CPUS 1
59 68 #define CONFIG_SYS_FSL_NUM_LAWS 8
60 69 #define CONFIG_SYS_FSL_SEC_COMPAT 2
  70 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
61 71  
62 72 #elif defined(CONFIG_MPC8560)
63 73 #define CONFIG_MAX_CPUS 1
64 74 #define CONFIG_SYS_FSL_NUM_LAWS 8
  75 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
65 76  
66 77 #elif defined(CONFIG_MPC8568)
67 78 #define CONFIG_MAX_CPUS 1
... ... @@ -70,6 +81,7 @@
70 81 #define QE_MURAM_SIZE 0x10000UL
71 82 #define MAX_QE_RISC 2
72 83 #define QE_NUM_OF_SNUM 28
  84 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
73 85  
74 86 #elif defined(CONFIG_MPC8569)
75 87 #define CONFIG_MAX_CPUS 1
76 88  
... ... @@ -78,11 +90,13 @@
78 90 #define QE_MURAM_SIZE 0x20000UL
79 91 #define MAX_QE_RISC 4
80 92 #define QE_NUM_OF_SNUM 46
  93 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
81 94  
82 95 #elif defined(CONFIG_MPC8572)
83 96 #define CONFIG_MAX_CPUS 2
84 97 #define CONFIG_SYS_FSL_NUM_LAWS 12
85 98 #define CONFIG_SYS_FSL_SEC_COMPAT 2
  99 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
86 100 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
87 101 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
88 102  
... ... @@ -106,6 +120,7 @@
106 120 #define CONFIG_TSECV2
107 121 #define CONFIG_FSL_PCIE_DISABLE_ASPM
108 122 #define CONFIG_SYS_FSL_SEC_COMPAT 2
  123 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
109 124 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
110 125 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
111 126  
... ... @@ -116,6 +131,7 @@
116 131 #define CONFIG_TSECV2
117 132 #define CONFIG_FSL_PCIE_DISABLE_ASPM
118 133 #define CONFIG_SYS_FSL_SEC_COMPAT 2
  134 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
119 135 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
120 136 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
121 137 #define QE_MURAM_SIZE 0x6000UL
... ... @@ -128,6 +144,7 @@
128 144 #define CONFIG_SYS_FSL_NUM_LAWS 12
129 145 #define CONFIG_TSECV2
130 146 #define CONFIG_SYS_FSL_SEC_COMPAT 2
  147 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
131 148 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
132 149 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
133 150 #define CONFIG_FSL_SATA_ERRATUM_A001
... ... @@ -151,6 +168,7 @@
151 168 #define CONFIG_TSECV2
152 169 #define CONFIG_FSL_PCIE_DISABLE_ASPM
153 170 #define CONFIG_SYS_FSL_SEC_COMPAT 2
  171 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
154 172 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
155 173 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
156 174  
... ... @@ -166,6 +184,7 @@
166 184 #define QE_MURAM_SIZE 0x6000UL
167 185 #define MAX_QE_RISC 1
168 186 #define QE_NUM_OF_SNUM 28
  187 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
169 188  
170 189 /* P1017 is single core version of P1023 */
171 190 #elif defined(CONFIG_P1017)
... ... @@ -179,6 +198,7 @@
179 198 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
180 199 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
181 200 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  201 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
182 202  
183 203 #elif defined(CONFIG_P1020)
184 204 #define CONFIG_MAX_CPUS 2
... ... @@ -186,6 +206,7 @@
186 206 #define CONFIG_TSECV2
187 207 #define CONFIG_FSL_PCIE_DISABLE_ASPM
188 208 #define CONFIG_SYS_FSL_SEC_COMPAT 2
  209 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
189 210 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
190 211 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
191 212  
... ... @@ -195,6 +216,7 @@
195 216 #define CONFIG_TSECV2
196 217 #define CONFIG_FSL_PCIE_DISABLE_ASPM
197 218 #define CONFIG_SYS_FSL_SEC_COMPAT 2
  219 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
198 220 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
199 221 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
200 222 #define QE_MURAM_SIZE 0x6000UL
... ... @@ -206,6 +228,7 @@
206 228 #define CONFIG_SYS_FSL_NUM_LAWS 12
207 229 #define CONFIG_TSECV2
208 230 #define CONFIG_SYS_FSL_SEC_COMPAT 2
  231 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
209 232 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
210 233 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
211 234 #define CONFIG_FSL_SATA_ERRATUM_A001
... ... @@ -221,6 +244,7 @@
221 244 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
222 245 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
223 246 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  247 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
224 248  
225 249 /* P1024 is lower end variant of P1020 */
226 250 #elif defined(CONFIG_P1024)
... ... @@ -229,6 +253,7 @@
229 253 #define CONFIG_TSECV2
230 254 #define CONFIG_FSL_PCIE_DISABLE_ASPM
231 255 #define CONFIG_SYS_FSL_SEC_COMPAT 2
  256 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
232 257 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
233 258 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
234 259  
... ... @@ -239,6 +264,7 @@
239 264 #define CONFIG_TSECV2
240 265 #define CONFIG_FSL_PCIE_DISABLE_ASPM
241 266 #define CONFIG_SYS_FSL_SEC_COMPAT 2
  267 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
242 268 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
243 269 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
244 270 #define QE_MURAM_SIZE 0x6000UL
... ... @@ -250,6 +276,7 @@
250 276 #define CONFIG_MAX_CPUS 1
251 277 #define CONFIG_SYS_FSL_NUM_LAWS 12
252 278 #define CONFIG_SYS_FSL_SEC_COMPAT 2
  279 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
253 280 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
254 281 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
255 282  
... ... @@ -257,6 +284,7 @@
257 284 #define CONFIG_MAX_CPUS 2
258 285 #define CONFIG_SYS_FSL_NUM_LAWS 12
259 286 #define CONFIG_SYS_FSL_SEC_COMPAT 2
  287 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
260 288 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
261 289 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
262 290  
... ... @@ -271,6 +299,7 @@
271 299 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
272 300 #define CONFIG_SYS_FSL_TBCLK_DIV 32
273 301 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  302 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
274 303 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
275 304 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
276 305 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
... ... @@ -288,6 +317,7 @@
288 317 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
289 318 #define CONFIG_SYS_FSL_TBCLK_DIV 32
290 319 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  320 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
291 321 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
292 322 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
293 323 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
... ... @@ -305,6 +335,7 @@
305 335 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
306 336 #define CONFIG_SYS_FSL_TBCLK_DIV 32
307 337 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  338 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
308 339 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
309 340 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
310 341 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
... ... @@ -318,6 +349,7 @@
318 349 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
319 350 #define CONFIG_SYS_FSL_TBCLK_DIV 16
320 351 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
  352 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
321 353  
322 354 #elif defined(CONFIG_PPC_P4080)
323 355 #define CONFIG_MAX_CPUS 8
... ... @@ -333,6 +365,7 @@
333 365 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
334 366 #define CONFIG_SYS_FSL_TBCLK_DIV 16
335 367 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
  368 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
336 369 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
337 370 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
338 371 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
... ... @@ -359,6 +392,7 @@
359 392 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
360 393 #define CONFIG_SYS_FSL_TBCLK_DIV 32
361 394 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  395 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
362 396 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
363 397 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
364 398 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
... ... @@ -376,6 +410,7 @@
376 410 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
377 411 #define CONFIG_SYS_FSL_TBCLK_DIV 32
378 412 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  413 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
379 414 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
380 415 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
381 416 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
... ... @@ -383,6 +418,10 @@
383 418  
384 419 #else
385 420 #error Processor type not defined for this platform
  421 +#endif
  422 +
  423 +#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
  424 +#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
386 425 #endif
387 426  
388 427 #endif /* _ASM_MPC85xx_CONFIG_H_ */
include/configs/MPC8536DS.h
Diff comments   View file @ e46fedf
... ... @@ -127,22 +127,11 @@
127 127 #define CONFIG_SYS_L2_SIZE (512 << 10)
128 128 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
129 129  
130   -/*
131   - * Base addresses -- Note these are effective addresses where the
132   - * actual resources get mapped (not physical addresses)
133   - */
134   -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
135   -#ifdef CONFIG_PHYS_64BIT
136   -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
137   -#else
138   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
139   -#endif
140   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  130 +#define CONFIG_SYS_CCSRBAR 0xffe00000
  131 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
141 132  
142 133 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
143   -#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
144   -#else
145   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  134 +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
146 135 #endif
147 136  
148 137 /* DDR Setup */
include/configs/MPC8540ADS.h
Diff comments   View file @ e46fedf
... ... @@ -89,15 +89,8 @@
89 89 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
90 90 #define CONFIG_SYS_MEMTEST_END 0x00400000
91 91  
92   -
93   -/*
94   - * Base addresses -- Note these are effective addresses where the
95   - * actual resources get mapped (not physical addresses)
96   - */
97   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
98   -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
99   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
100   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  92 +#define CONFIG_SYS_CCSRBAR 0xe0000000
  93 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
101 94  
102 95 /* DDR Setup */
103 96 #define CONFIG_FSL_DDR1
include/configs/MPC8541CDS.h
Diff comments   View file @ e46fedf
... ... @@ -62,14 +62,8 @@
62 62 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
63 63 #define CONFIG_SYS_MEMTEST_END 0x00400000
64 64  
65   -/*
66   - * Base addresses -- Note these are effective addresses where the
67   - * actual resources get mapped (not physical addresses)
68   - */
69   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
70   -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
71   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
72   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  65 +#define CONFIG_SYS_CCSRBAR 0xe0000000
  66 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
73 67  
74 68 /* DDR Setup */
75 69 #define CONFIG_FSL_DDR1
include/configs/MPC8544DS.h
Diff comments   View file @ e46fedf
... ... @@ -74,14 +74,8 @@
74 74 #define CONFIG_SYS_MEMTEST_END 0x00400000
75 75 #define CONFIG_PANIC_HANG /* do not reset board on panic */
76 76  
77   -/*
78   - * Base addresses -- Note these are effective addresses where the
79   - * actual resources get mapped (not physical addresses)
80   - */
81   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
82   -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
83   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
84   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  77 +#define CONFIG_SYS_CCSRBAR 0xe0000000
  78 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
85 79  
86 80 /* DDR Setup */
87 81 #define CONFIG_FSL_DDR2
include/configs/MPC8548CDS.h
Diff comments   View file @ e46fedf
... ... @@ -77,14 +77,8 @@
77 77 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
78 78 #define CONFIG_SYS_MEMTEST_END 0x00400000
79 79  
80   -/*
81   - * Base addresses -- Note these are effective addresses where the
82   - * actual resources get mapped (not physical addresses)
83   - */
84   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
85   -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
86   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
87   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  80 +#define CONFIG_SYS_CCSRBAR 0xe0000000
  81 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
88 82  
89 83 /* DDR Setup */
90 84 #define CONFIG_FSL_DDR2
include/configs/MPC8555CDS.h
Diff comments   View file @ e46fedf
... ... @@ -62,14 +62,8 @@
62 62 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
63 63 #define CONFIG_SYS_MEMTEST_END 0x00400000
64 64  
65   -/*
66   - * Base addresses -- Note these are effective addresses where the
67   - * actual resources get mapped (not physical addresses)
68   - */
69   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
70   -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
71   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
72   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  65 +#define CONFIG_SYS_CCSRBAR 0xe0000000
  66 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
73 67  
74 68 /* DDR Setup */
75 69 #define CONFIG_FSL_DDR1
include/configs/MPC8560ADS.h
Diff comments   View file @ e46fedf
... ... @@ -86,15 +86,8 @@
86 86 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
87 87 #define CONFIG_SYS_MEMTEST_END 0x00400000
88 88  
89   -
90   -/*
91   - * Base addresses -- Note these are effective addresses where the
92   - * actual resources get mapped (not physical addresses)
93   - */
94   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
95   -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
96   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
97   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  89 +#define CONFIG_SYS_CCSRBAR 0xe0000000
  90 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
98 91  
99 92 /* DDR Setup */
100 93 #define CONFIG_FSL_DDR1
include/configs/MPC8568MDS.h
Diff comments   View file @ e46fedf
... ... @@ -71,14 +71,8 @@
71 71 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
72 72 #define CONFIG_SYS_MEMTEST_END 0x00400000
73 73  
74   -/*
75   - * Base addresses -- Note these are effective addresses where the
76   - * actual resources get mapped (not physical addresses)
77   - */
78   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
79   -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
80   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
81   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  74 +#define CONFIG_SYS_CCSRBAR 0xe0000000
  75 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
82 76  
83 77 /* DDR Setup */
84 78 #define CONFIG_FSL_DDR2
include/configs/MPC8569MDS.h
Diff comments   View file @ e46fedf
... ... @@ -105,20 +105,11 @@
105 105 #define CONFIG_SYS_L2_SIZE (512 << 10)
106 106 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
107 107  
108   -/*
109   - * Base addresses -- Note these are effective addresses where the
110   - * actual resources get mapped (not physical addresses)
111   - */
112   -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
113   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
114   - /* physical addr of CCSRBAR */
115   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
116   - /* PQII uses CONFIG_SYS_IMMR */
  108 +#define CONFIG_SYS_CCSRBAR 0xe0000000
  109 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
117 110  
118 111 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
119   -#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
120   -#else
121   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  112 +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
122 113 #endif
123 114  
124 115 /* DDR Setup */
include/configs/MPC8572DS.h
Diff comments   View file @ e46fedf
... ... @@ -112,22 +112,11 @@
112 112 #define CONFIG_SYS_L2_SIZE (512 << 10)
113 113 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
114 114  
115   -/*
116   - * Base addresses -- Note these are effective addresses where the
117   - * actual resources get mapped (not physical addresses)
118   - */
119   -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
120   -#ifdef CONFIG_PHYS_64BIT
121   -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
122   -#else
123   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
124   -#endif
125   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  115 +#define CONFIG_SYS_CCSRBAR 0xffe00000
  116 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
126 117  
127 118 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
128   -#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
129   -#else
130   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  119 +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
131 120 #endif
132 121  
133 122 /* DDR Setup */
include/configs/P1022DS.h
Diff comments   View file @ e46fedf
... ... @@ -64,18 +64,8 @@
64 64 #define CONFIG_SYS_MEMTEST_START 0x00000000
65 65 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
66 66  
67   -/*
68   - * Base addresses -- Note these are effective addresses where the
69   - * actual resources get mapped (not physical addresses)
70   - */
71   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
72   -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
73   -#ifdef CONFIG_PHYS_64BIT
74   -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull
75   -#else
76   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
77   -#endif
78   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
  67 +#define CONFIG_SYS_CCSRBAR 0xffe00000
  68 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
79 69  
80 70 /* DDR Setup */
81 71 #define CONFIG_DDR_SPD
include/configs/P1023RDS.h
Diff comments   View file @ e46fedf
... ... @@ -99,15 +99,6 @@
99 99  
100 100 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* Implement conversion of
101 101 addresses in the LBC */
102   -/*
103   - * Base addresses -- Note these are effective addresses where the
104   - * actual resources get mapped (not physical addresses)
105   - */
106   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 /* CCSRBAR Default */
107   -#define CONFIG_SYS_CCSRBAR 0xff600000 /* relocated CCSRBAR */
108   -/* physical addr of CCSRBAR */
109   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
110   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
111 102  
112 103 /* DDR Setup */
113 104 #define CONFIG_VERY_BIG_RAM
include/configs/P1_P2_RDB.h
Diff comments   View file @ e46fedf
... ... @@ -148,24 +148,11 @@
148 148 #define CONFIG_SYS_L2_SIZE (512 << 10)
149 149 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
150 150  
151   -/*
152   - * Base addresses -- Note these are effective addresses where the
153   - * actual resources get mapped (not physical addresses)
154   - */
155   -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
156   -#ifdef CONFIG_PHYS_64BIT
157   -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull
158   -#else
159   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
160   -#endif
161   - /* CCSRBAR */
162   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
163   - /* CONFIG_SYS_IMMR */
  151 +#define CONFIG_SYS_CCSRBAR 0xffe00000
  152 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
164 153  
165 154 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
166   -#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
167   -#else
168   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  155 +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
169 156 #endif
170 157  
171 158 /* DDR Setup */
include/configs/P2020DS.h
Diff comments   View file @ e46fedf
... ... @@ -118,18 +118,8 @@
118 118 #define CONFIG_SYS_L2_SIZE (512 << 10)
119 119 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
120 120  
121   -/*
122   - * Base addresses -- Note these are effective addresses where the
123   - * actual resources get mapped (not physical addresses)
124   - */
125   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
126   -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
127   -#ifdef CONFIG_PHYS_64BIT
128   -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
129   -#else
130   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
131   -#endif
132   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  121 +#define CONFIG_SYS_CCSRBAR 0xffe00000
  122 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
133 123  
134 124 /* DDR Setup */
135 125 #define CONFIG_VERY_BIG_RAM
include/configs/P2041RDB.h
Diff comments   View file @ e46fedf
... ... @@ -138,20 +138,6 @@
138 138 #define CONFIG_SYS_L3_SIZE (1024 << 10)
139 139 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
140 140  
141   -/*
142   - * Base addresses -- Note these are effective addresses where the
143   - * actual resources get mapped (not physical addresses)
144   - */
145   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */
146   -#define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */
147   -#ifdef CONFIG_PHYS_64BIT
148   -#define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull
149   -#else
150   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
151   -#endif
152   -/* PQII uses CONFIG_SYS_IMMR */
153   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
154   -
155 141 #ifdef CONFIG_PHYS_64BIT
156 142 #define CONFIG_SYS_DCSRBAR 0xf0000000
157 143 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
include/configs/SBC8540.h
Diff comments   View file @ e46fedf
... ... @@ -94,20 +94,6 @@
94 94 #error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
95 95 #endif
96 96  
97   -/*
98   - * Base addresses -- Note these are effective addresses where the
99   - * actual resources get mapped (not physical addresses)
100   - */
101   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
102   -
103   -#if XXX
104   - #define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
105   -#else
106   - #define CONFIG_SYS_CCSRBAR 0xff700000 /* default CCSRBAR */
107   -#endif
108   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
109   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
110   -
111 97 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
112 98  
113 99 /* DDR Setup */
include/configs/TQM85xx.h
Diff comments   View file @ e46fedf
... ... @@ -130,18 +130,12 @@
130 130 #define CONFIG_SYS_MEMTEST_START 0x00000000
131 131 #define CONFIG_SYS_MEMTEST_END 0x10000000
132 132  
133   -/*
134   - * Base addresses -- Note these are effective addresses where the
135   - * actual resources get mapped (not physical addresses)
136   - */
137   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
138 133 #ifdef CONFIG_TQM_BIGFLASH
139   -#define CONFIG_SYS_CCSRBAR 0xA0000000 /* relocated CCSRBAR */
140   -#else /* !CONFIG_TQM_BIGFLASH */
141   -#define CONFIG_SYS_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
142   -#endif /* CONFIG_TQM_BIGFLASH */
143   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
144   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  134 +#define CONFIG_SYS_CCSRBAR 0xA0000000
  135 +#else
  136 +#define CONFIG_SYS_CCSRBAR 0xE0000000
  137 +#endif
  138 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
145 139  
146 140 /*
147 141 * DDR Setup
include/configs/corenet_ds.h
Diff comments   View file @ e46fedf
... ... @@ -144,19 +144,6 @@
144 144 #define CONFIG_SYS_L3_SIZE (1024 << 10)
145 145 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
146 146  
147   -/*
148   - * Base addresses -- Note these are effective addresses where the
149   - * actual resources get mapped (not physical addresses)
150   - */
151   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */
152   -#define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */
153   -#ifdef CONFIG_PHYS_64BIT
154   -#define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull /* physical addr of CCSRBAR */
155   -#else
156   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
157   -#endif
158   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
159   -
160 147 #ifdef CONFIG_PHYS_64BIT
161 148 #define CONFIG_SYS_DCSRBAR 0xf0000000
162 149 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
include/configs/mpq101.h
Diff comments   View file @ e46fedf
... ... @@ -64,20 +64,8 @@
64 64  
65 65 #define CONFIG_SYS_CLK_FREQ 33000000 /* sysclk for MPC85xx */
66 66  
67   -/*
68   - * Base addresses -- Note these are effective addresses where the
69   - * actual resources get mapped (not physical addresses)
70   - */
71   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
72   -#define CONFIG_SYS_CCSRBAR 0xe0000000
73   -
74   -#ifdef CONFIG_PHYS_64BIT
75   -# define CONFIG_SYS_CCSRBAR_PHYS 0xfe0000000ull
76   -#else
77   -# define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
78   -#endif
79   -
80   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
  67 +#define CONFIG_SYS_CCSRBAR 0xe0000000
  68 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
81 69  
82 70 /* DDR Setup */
83 71 #define CONFIG_FSL_DDR2
include/configs/sbc8548.h
Diff comments   View file @ e46fedf
... ... @@ -103,14 +103,8 @@
103 103 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
104 104 #define CONFIG_SYS_MEMTEST_END 0x00400000
105 105  
106   -/*
107   - * Base addresses -- Note these are effective addresses where the
108   - * actual resources get mapped (not physical addresses)
109   - */
110   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
111   -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
112   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
113   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  106 +#define CONFIG_SYS_CCSRBAR 0xe0000000
  107 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
114 108  
115 109 /* DDR Setup */
116 110 #define CONFIG_FSL_DDR2
include/configs/sbc8560.h
Diff comments   View file @ e46fedf
... ... @@ -92,20 +92,6 @@
92 92 #error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
93 93 #endif
94 94  
95   -/*
96   - * Base addresses -- Note these are effective addresses where the
97   - * actual resources get mapped (not physical addresses)
98   - */
99   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
100   -
101   -#if XXX
102   - #define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
103   -#else
104   - #define CONFIG_SYS_CCSRBAR 0xff700000 /* default CCSRBAR */
105   -#endif
106   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
107   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
108   -
109 95 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
110 96  
111 97 /* DDR Setup */
include/configs/socrates.h
Diff comments   View file @ e46fedf
... ... @@ -91,14 +91,8 @@
91 91 #define CONFIG_SYS_MEMTEST_START 0x00400000
92 92 #define CONFIG_SYS_MEMTEST_END 0x00C00000
93 93  
94   -/*
95   - * Base addresses -- Note these are effective addresses where the
96   - * actual resources get mapped (not physical addresses)
97   - */
98   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
99   -#define CONFIG_SYS_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
100   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
101   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  94 +#define CONFIG_SYS_CCSRBAR 0xE0000000
  95 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
102 96  
103 97 /* DDR Setup */
104 98 #define CONFIG_FSL_DDR2
include/configs/stxgp3.h
Diff comments   View file @ e46fedf
... ... @@ -109,12 +109,9 @@
109 109  
110 110 #ifdef CONFIG_SYS_RAMBOOT
111 111 #define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
112   -#else
113   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
114 112 #endif
115   -#define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
116   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
117   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  113 +#define CONFIG_SYS_CCSRBAR 0xfdf00000
  114 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
118 115  
119 116 /* DDR Setup */
120 117 #define CONFIG_FSL_DDR1
include/configs/stxssa.h
Diff comments   View file @ e46fedf
... ... @@ -121,12 +121,10 @@
121 121  
122 122 #ifdef CONFIG_SYS_RAMBOOT
123 123 #define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
124   -#else
125   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
126 124 #endif
127   -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
128   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
129   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  125 +
  126 +#define CONFIG_SYS_CCSRBAR 0xe0000000
  127 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
130 128  
131 129 /* DDR Setup */
132 130 #define CONFIG_FSL_DDR1
include/configs/xpedite520x.h
Diff comments   View file @ e46fedf
... ... @@ -78,14 +78,8 @@
78 78 #define CONFIG_BTB /* toggle branch predition */
79 79 #define CONFIG_ENABLE_36BIT_PHYS 1
80 80  
81   -/*
82   - * Base addresses -- Note these are effective addresses where the
83   - * actual resources get mapped (not physical addresses)
84   - */
85   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
86   -#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
87   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
88   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  81 +#define CONFIG_SYS_CCSRBAR 0xef000000
  82 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
89 83  
90 84 /*
91 85 * Diagnostics
include/configs/xpedite537x.h
Diff comments   View file @ e46fedf
... ... @@ -96,14 +96,8 @@
96 96 #define CONFIG_BTB /* toggle branch predition */
97 97 #define CONFIG_ENABLE_36BIT_PHYS 1
98 98  
99   -/*
100   - * Base addresses -- Note these are effective addresses where the
101   - * actual resources get mapped (not physical addresses)
102   - */
103   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
104   -#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
105   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
106   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  99 +#define CONFIG_SYS_CCSRBAR 0xef000000
  100 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
107 101  
108 102 /*
109 103 * Diagnostics
include/configs/xpedite550x.h
Diff comments   View file @ e46fedf
... ... @@ -93,14 +93,8 @@
93 93 #define CONFIG_BTB /* toggle branch predition */
94 94 #define CONFIG_ENABLE_36BIT_PHYS 1
95 95  
96   -/*
97   - * Base addresses -- Note these are effective addresses where the
98   - * actual resources get mapped (not physical addresses)
99   - */
100   -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
101   -#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
102   -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
103   -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  96 +#define CONFIG_SYS_CCSRBAR 0xef000000
  97 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
104 98  
105 99 /*
106 100 * Diagnostics
... ... @@ -26,5 +26,47 @@
26 26 #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
27 27 #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
28 28  
  29 +/*
  30 + * Define default values for some CCSR macros to make header files cleaner*
  31 + *
  32 + * To completely disable CCSR relocation in a board header file, define
  33 + * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
  34 + * to a value that is the same as CONFIG_SYS_CCSRBAR.
  35 + */
  36 +
  37 +#ifdef CONFIG_SYS_CCSRBAR_PHYS
  38 +#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \
  39 +CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
  40 +#endif
  41 +
  42 +#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  43 +#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
  44 +#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
  45 +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
  46 +#endif
  47 +
  48 +#ifndef CONFIG_SYS_CCSRBAR
  49 +#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
  50 +#endif
  51 +
  52 +#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
  53 +#ifdef CONFIG_PHYS_64BIT
  54 +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
  55 +#else
  56 +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
  57 +#endif
  58 +#endif
  59 +
  60 +#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
  61 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
  62 +#endif
  63 +
  64 +#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
  65 + CONFIG_SYS_CCSRBAR_PHYS_LOW)
  66 +
  67 +#ifndef CONFIG_SYS_IMMR
  68 +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
  69 +#endif
  70 +
29 71 #endif /* __MPC85xx_H__ */