Eric Lee / smarc-uboot

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Commit e54205486e21f4d2af8391420c204613b4dbe3d1

Authored by Ye Li
1 parent 72549efa3c
Exists in smarc_8mq-imx_v2020.04_5.4.24_2.1.0 and in 3 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, smarc-8m-android-10.0.0_2.6.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0

MLK-23574-2 spi: Add FlexSPI Driver for i.MX8 

Port fsl_fspi driver for flexspi controller from imx_v2019.04.
This driver supports:
1. DDR Quad output
2. Prefetch function for improve read performance.
3. Fast read and Quad read for one line read mode.
4. Read flash FSR register.
5. DM driver and SPI-MEM supported

Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit ae4e80b7b0debd2ad868781aaeb28ca4f2d9a8aa)
(cherry picked from commit dcd5504f6493d9aed415f397f1c13611fc202605)
(cherry picked from commit 902fba8f72e98d6c742674d305c855f3595c48b6)

Showing 5 changed files with 1901 additions and 0 deletions Side-by-side Diff

... ... @@ -398,6 +398,13 @@
398 398 access the SPI interface and SPI NOR flash on platforms embedding
399 399 this Freescale eSPI IP core.
400 400  
  401 +config FSL_FSPI
  402 + bool "Freescale FlexSPI driver"
  403 + help
  404 + Enable the Freescale FlexSPI (FSPI) driver. This driver can be
  405 + used to access the SPI NOR flash on platforms embedding this
  406 + Freescale IP core.
  407 +
401 408 config FSL_QSPI
402 409 bool "Freescale QSPI driver"
403 410 imply SPI_FLASH_BAR
drivers/spi/Makefile
Diff comments   View file @ e542054
... ... @@ -30,6 +30,7 @@
30 30 obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
31 31 obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
32 32 obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
  33 +obj-$(CONFIG_FSL_FSPI) += fsl_fspi.o
33 34 obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
34 35 obj-$(CONFIG_ICH_SPI) += ich.o
35 36 obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
drivers/spi/fsl_fspi.c
Diff comments   View file @ e542054
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright 2017-2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <malloc.h>
  9 +#include <spi.h>
  10 +#include <asm/io.h>
  11 +#include <linux/sizes.h>
  12 +#include <dm.h>
  13 +#include <errno.h>
  14 +#include <watchdog.h>
  15 +#include <clk.h>
  16 +#include "fsl_fspi.h"
  17 +#include <spi-mem.h>
  18 +
  19 +DECLARE_GLOBAL_DATA_PTR;
  20 +
  21 +#define RX_BUFFER_SIZE 0x200
  22 +#define TX_BUFFER_SIZE 0x400
  23 +#define AHB_BUFFER_SIZE 0x800
  24 +
  25 +#define OFFSET_BITS_MASK_4B GENMASK(31, 0)
  26 +#define OFFSET_BITS_MASK GENMASK(23, 0)
  27 +
  28 +#define FLASH_STATUS_WEL 0x02
  29 +
  30 +/* SEQID */
  31 +enum fspi_lut_id {
  32 + SEQID_READ = 0,
  33 + SEQID_WREN = 1,
  34 + SEQID_FAST_READ = 2,
  35 + SEQID_FAST_READ_4B = 3,
  36 + SEQID_RDSR = 4,
  37 + SEQID_SE = 5,
  38 + SEQID_SE_4B = 6,
  39 + SEQID_CHIP_ERASE = 7,
  40 + SEQID_PP = 8,
  41 + SEQID_PP_4B = 9,
  42 + SEQID_RDID = 10,
  43 + SEQID_BE_4K = 11,
  44 + SEQID_BE_4K_4B = 12,
  45 + SEQID_BRRD = 13,
  46 + SEQID_BRWR = 14,
  47 + SEQID_RDEAR = 15,
  48 + SEQID_WREAR = 16,
  49 + SEQID_RDEVCR = 17,
  50 + SEQID_WREVCR = 18,
  51 + SEQID_QUAD_OUTPUT = 19,
  52 + SEQID_DDR_QUAD_OUTPUT = 20,
  53 + SEQID_RDFSR = 21,
  54 + SEQID_EN4B = 22,
  55 + SEQID_WRDI = 23,
  56 + SEQID_QUAD_PP = 24,
  57 + SEQID_END,
  58 +};
  59 +
  60 +/* FSPI CMD */
  61 +#define FSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */
  62 +#define FSPI_CMD_RDSR 0x05 /* Read status register */
  63 +#define FSPI_CMD_WRDI 0x04 /* Write disable */
  64 +#define FSPI_CMD_WREN 0x06 /* Write enable */
  65 +#define FSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */
  66 +#define FSPI_CMD_READ 0x03 /* Read data bytes */
  67 +#define FSPI_CMD_BE_4K 0x20 /* 4K erase */
  68 +#define FSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */
  69 +#define FSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */
  70 +#define FSPI_CMD_RDID 0x9f /* Read JEDEC ID */
  71 +
  72 +/* Used for Micron, winbond and Macronix flashes */
  73 +#define FSPI_CMD_WREAR 0xc5 /* EAR register write */
  74 +#define FSPI_CMD_RDEAR 0xc8 /* EAR reigster read */
  75 +
  76 +/* Used for Spansion flashes only. */
  77 +#define FSPI_CMD_BRRD 0x16 /* Bank register read */
  78 +#define FSPI_CMD_BRWR 0x17 /* Bank register write */
  79 +
  80 +/* 4-byte address FSPI CMD - used on Spansion and some Macronix flashes */
  81 +#define FSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
  82 +#define FSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */
  83 +#define FSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */
  84 +#define FSPI_CMD_BE_4K_4B 0x21 /* 4K erase */
  85 +
  86 +#define FSPI_CMD_RD_EVCR 0x65 /* Read EVCR register */
  87 +#define FSPI_CMD_WR_EVCR 0x61 /* Write EVCR register */
  88 +
  89 +#define FSPI_CMD_EN4B 0xB7
  90 +
  91 +/* 1-1-4 READ CMD */
  92 +#define FSPI_CMD_QUAD_OUTPUT 0x6b
  93 +#define FSPI_CMD_DDR_QUAD_OUTPUT 0x6d
  94 +
  95 +#define FSPI_CMD_QUAD_PP 0x32
  96 +
  97 +/* read flag status register */
  98 +#define FSPI_CMD_RDFSR 0x70
  99 +
  100 +/* fsl_fspi_platdata flags */
  101 +#define FSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
  102 +
  103 +/* default SCK frequency, unit: HZ */
  104 +#define FSL_FSPI_DEFAULT_SCK_FREQ 50000000
  105 +
  106 +/* FSPI max chipselect signals number */
  107 +#define FSL_FSPI_MAX_CHIPSELECT_NUM 4
  108 +
  109 +#ifdef CONFIG_DM_SPI
  110 +/**
  111 + * struct fsl_fspi_platdata - platform data for NXP FSPI
  112 + *
  113 + * @flags: Flags for FSPI FSPI_FLAG_...
  114 + * @speed_hz: Default SCK frequency
  115 + * @reg_base: Base address of FSPI registers
  116 + * @amba_base: Base address of FSPI memory mapping
  117 + * @amba_total_size: size of FSPI memory mapping
  118 + * @flash_num: Number of active slave devices
  119 + * @num_chipselect: Number of FSPI chipselect signals
  120 + */
  121 +struct fsl_fspi_platdata {
  122 + u32 flags;
  123 + u32 speed_hz;
  124 + u32 reg_base;
  125 + u32 amba_base;
  126 + u32 amba_total_size;
  127 + u32 flash_num;
  128 + u32 num_chipselect;
  129 +};
  130 +#endif
  131 +
  132 +/**
  133 + * struct fsl_fspi_priv - private data for NXP FSPI
  134 + *
  135 + * @flags: Flags for FSPI FSPI_FLAG_...
  136 + * @bus_clk: FSPI input clk frequency
  137 + * @speed_hz: Default SCK frequency
  138 + * @cur_seqid: current LUT table sequence id
  139 + * @sf_addr: flash access offset
  140 + * @amba_base: Base address of FSPI memory mapping of every CS
  141 + * @amba_total_size: size of FSPI memory mapping
  142 + * @cur_amba_base: Base address of FSPI memory mapping of current CS
  143 + * @flash_num: Number of active slave devices
  144 + * @num_chipselect: Number of FSPI chipselect signals
  145 + * @regs: Point to FSPI register structure for I/O access
  146 + */
  147 +struct fsl_fspi_priv {
  148 + u32 flags;
  149 + u32 bus_clk;
  150 + u32 speed_hz;
  151 + u32 cur_seqid;
  152 + u32 sf_addr;
  153 + u32 amba_base[FSL_FSPI_MAX_CHIPSELECT_NUM];
  154 + u32 amba_total_size;
  155 + u32 cur_amba_base;
  156 + u32 flash_num;
  157 + u32 num_chipselect;
  158 + u32 read_dummy;
  159 + struct fsl_fspi_regs *regs;
  160 +};
  161 +
  162 +struct fspi_cmd_func_pair {
  163 + u8 cmd;
  164 + bool ahb_invalid;
  165 + int (*fspi_op_func)(struct fsl_fspi_priv *priv, u32 seqid, u8 *buf, u32 len);
  166 +};
  167 +
  168 +#ifndef CONFIG_DM_SPI
  169 +struct fsl_fspi {
  170 + struct spi_slave slave;
  171 + struct fsl_fspi_priv priv;
  172 +};
  173 +#endif
  174 +
  175 +static u32 fspi_read32(u32 flags, u32 *addr)
  176 +{
  177 + return flags & FSPI_FLAG_REGMAP_ENDIAN_BIG ?
  178 + in_be32(addr) : in_le32(addr);
  179 +}
  180 +
  181 +static void fspi_write32(u32 flags, u32 *addr, u32 val)
  182 +{
  183 + flags & FSPI_FLAG_REGMAP_ENDIAN_BIG ?
  184 + out_be32(addr, val) : out_le32(addr, val);
  185 +}
  186 +
  187 +/* FSPI support swapping the flash read/write data
  188 + * in hardware
  189 + */
  190 +static inline u32 fspi_endian_xchg(u32 data)
  191 +{
  192 + return data;
  193 +}
  194 +
  195 +static void fspi_set_lut(struct fsl_fspi_priv *priv)
  196 +{
  197 + struct fsl_fspi_regs *regs = priv->regs;
  198 + u32 lut_base;
  199 +
  200 + /* Unlock the LUT */
  201 + fspi_write32(priv->flags, &regs->lutkey, FLEXSPI_LUTKEY_VALUE);
  202 + fspi_write32(priv->flags, &regs->lutcr, FLEXSPI_LCKER_UNLOCK);
  203 +
  204 + /* READ */
  205 + lut_base = SEQID_READ * 4;
  206 + fspi_write32(priv->flags, &regs->lut[lut_base],
  207 + OPRND0(FSPI_CMD_READ) | PAD0(LUT_PAD1) |
  208 + INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
  209 + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
  210 + fspi_write32(priv->flags, &regs->lut[lut_base + 1],
  211 + OPRND0(0) | PAD0(LUT_PAD1) |
  212 + INSTR0(LUT_READ));
  213 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  214 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  215 +
  216 + /* Write Enable */
  217 + lut_base = SEQID_WREN * 4;
  218 + fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_WREN) |
  219 + PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
  220 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  221 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  222 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  223 +
  224 + /* Fast Read */
  225 + lut_base = SEQID_FAST_READ * 4;
  226 + fspi_write32(priv->flags, &regs->lut[lut_base],
  227 + OPRND0(FSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
  228 + INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
  229 + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
  230 + fspi_write32(priv->flags, &regs->lut[lut_base + 1],
  231 + OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
  232 + OPRND1(0) | PAD1(LUT_PAD1) |
  233 + INSTR1(LUT_READ));
  234 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  235 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  236 +
  237 + lut_base = SEQID_FAST_READ_4B * 4;
  238 + fspi_write32(priv->flags, &regs->lut[lut_base],
  239 + OPRND0(FSPI_CMD_FAST_READ_4B) |
  240 + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
  241 + OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
  242 + INSTR1(LUT_ADDR));
  243 + fspi_write32(priv->flags, &regs->lut[lut_base + 1],
  244 + OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
  245 + OPRND1(0) | PAD1(LUT_PAD1) |
  246 + INSTR1(LUT_READ));
  247 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  248 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  249 +
  250 + /* Read Status */
  251 + lut_base = SEQID_RDSR * 4;
  252 + fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_RDSR) |
  253 + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
  254 + PAD1(LUT_PAD1) | INSTR1(LUT_READ));
  255 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  256 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  257 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  258 +
  259 + /* Erase a sector */
  260 + lut_base = SEQID_SE * 4;
  261 + fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_SE) |
  262 + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
  263 + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
  264 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  265 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  266 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  267 +
  268 + lut_base = SEQID_SE_4B * 4;
  269 + fspi_write32(priv->flags, &regs->lut[lut_base],
  270 + OPRND0(FSPI_CMD_SE_4B) | PAD0(LUT_PAD1) |
  271 + INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
  272 + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
  273 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  274 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  275 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  276 +
  277 + /* Erase the whole chip */
  278 + lut_base = SEQID_CHIP_ERASE * 4;
  279 + fspi_write32(priv->flags, &regs->lut[lut_base],
  280 + OPRND0(FSPI_CMD_CHIP_ERASE) |
  281 + PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
  282 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  283 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  284 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  285 +
  286 + /* Page Program */
  287 + lut_base = SEQID_PP * 4;
  288 + fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_PP) |
  289 + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
  290 + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
  291 + fspi_write32(priv->flags, &regs->lut[lut_base + 1],
  292 + OPRND0(0) |
  293 + PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
  294 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  295 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  296 +
  297 + lut_base = SEQID_PP_4B * 4;
  298 + fspi_write32(priv->flags, &regs->lut[lut_base],
  299 + OPRND0(FSPI_CMD_PP_4B) | PAD0(LUT_PAD1) |
  300 + INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
  301 + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
  302 + fspi_write32(priv->flags, &regs->lut[lut_base + 1],
  303 + OPRND0(0) |
  304 + PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
  305 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  306 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  307 +
  308 + /* READ ID */
  309 + lut_base = SEQID_RDID * 4;
  310 + fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_RDID) |
  311 + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
  312 + PAD1(LUT_PAD1) | INSTR1(LUT_READ));
  313 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  314 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  315 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  316 +
  317 + /* SUB SECTOR 4K ERASE */
  318 + lut_base = SEQID_BE_4K * 4;
  319 + fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_BE_4K) |
  320 + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
  321 + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
  322 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  323 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  324 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  325 +
  326 + lut_base = SEQID_BE_4K_4B * 4;
  327 + fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_BE_4K_4B) |
  328 + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
  329 + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
  330 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  331 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  332 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  333 +
  334 + /*
  335 + * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
  336 + * dynamically check whether to set BRRD BRWR or RDEAR WREAR during
  337 + * initialization.
  338 + */
  339 + lut_base = SEQID_BRRD * 4;
  340 + fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_BRRD) |
  341 + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
  342 + PAD1(LUT_PAD1) | INSTR1(LUT_READ));
  343 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  344 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  345 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  346 +
  347 + lut_base = SEQID_BRWR * 4;
  348 + fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_BRWR) |
  349 + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
  350 + PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
  351 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  352 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  353 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  354 +
  355 + lut_base = SEQID_RDEAR * 4;
  356 + fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_RDEAR) |
  357 + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
  358 + PAD1(LUT_PAD1) | INSTR1(LUT_READ));
  359 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  360 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  361 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  362 +
  363 + lut_base = SEQID_WREAR * 4;
  364 + fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_WREAR) |
  365 + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
  366 + PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
  367 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  368 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  369 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  370 +
  371 + lut_base = SEQID_RDEVCR * 4;
  372 + fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_RD_EVCR) |
  373 + PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
  374 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  375 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  376 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  377 +
  378 + lut_base = SEQID_WREVCR * 4;
  379 + fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_WR_EVCR) |
  380 + PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
  381 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  382 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  383 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  384 +
  385 + /* QUAD OUTPUT READ */
  386 + lut_base = SEQID_QUAD_OUTPUT * 4;
  387 + fspi_write32(priv->flags, &regs->lut[lut_base],
  388 + OPRND0(FSPI_CMD_QUAD_OUTPUT) | PAD0(LUT_PAD1) |
  389 + INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
  390 + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
  391 + fspi_write32(priv->flags, &regs->lut[lut_base + 1],
  392 + OPRND0(0x8) | PAD0(LUT_PAD4) |
  393 + INSTR0(LUT_DUMMY) | OPRND1(0) |
  394 + PAD1(LUT_PAD4) | INSTR1(LUT_READ));
  395 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  396 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  397 +
  398 + /* DDR QUAD OUTPUT READ */
  399 + lut_base = SEQID_DDR_QUAD_OUTPUT * 4;
  400 + fspi_write32(priv->flags, &regs->lut[lut_base],
  401 + OPRND0(FSPI_CMD_DDR_QUAD_OUTPUT) | PAD0(LUT_PAD1) |
  402 + INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
  403 + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR_DDR));
  404 + fspi_write32(priv->flags, &regs->lut[lut_base + 1],
  405 + OPRND0(0xc) | PAD0(LUT_PAD4) |
  406 + INSTR0(LUT_DUMMY_DDR) | OPRND1(0) |
  407 + PAD1(LUT_PAD4) | INSTR1(LUT_READ_DDR));
  408 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  409 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  410 +
  411 + /* Read Flag Status */
  412 + lut_base = SEQID_RDFSR * 4;
  413 + fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_RDFSR) |
  414 + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
  415 + PAD1(LUT_PAD1) | INSTR1(LUT_READ));
  416 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  417 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  418 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  419 +
  420 + /* Enter 4 bytes address mode */
  421 + lut_base = SEQID_EN4B * 4;
  422 + fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_EN4B) |
  423 + PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
  424 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  425 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  426 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  427 +
  428 + /* Write Disable */
  429 + lut_base = SEQID_WRDI * 4;
  430 + fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_WRDI) |
  431 + PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
  432 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  433 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  434 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  435 +
  436 + /* QUAD PP */
  437 + lut_base = SEQID_QUAD_PP * 4;
  438 + fspi_write32(priv->flags, &regs->lut[lut_base],
  439 + OPRND0(FSPI_CMD_QUAD_PP) | PAD0(LUT_PAD1) |
  440 + INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
  441 + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
  442 + fspi_write32(priv->flags, &regs->lut[lut_base + 1],
  443 + OPRND0(0) | PAD0(LUT_PAD4) |
  444 + INSTR0(LUT_WRITE));
  445 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  446 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  447 +
  448 + /* Lock the LUT */
  449 + fspi_write32(priv->flags, &regs->lutkey, FLEXSPI_LUTKEY_VALUE);
  450 + fspi_write32(priv->flags, &regs->lutcr, FLEXSPI_LCKER_LOCK);
  451 +}
  452 +
  453 +static int fspi_mem_op_cmd(struct fsl_fspi_priv *priv, u32 seqid, u8 *buf, u32 len)
  454 +{
  455 + struct fsl_fspi_regs *regs = priv->regs;
  456 + u32 to_or_from = 0;
  457 +
  458 + debug("%s, seqid %u\n", __func__, seqid);
  459 +
  460 + to_or_from = priv->sf_addr + priv->cur_amba_base;
  461 +
  462 + /* invalid the TXFIFO first */
  463 + fspi_write32(priv->flags, &regs->iptxfcr, FLEXSPI_IPTXFCR_CLR_MASK);
  464 +
  465 + fspi_write32(priv->flags, &regs->ipcr0, to_or_from);
  466 +
  467 + fspi_write32(priv->flags, &regs->ipcr1,
  468 + (seqid << FLEXSPI_IPCR1_SEQID_SHIFT) | 0);
  469 +
  470 + /* Trigger the command */
  471 + fspi_write32(priv->flags, &regs->ipcmd, 1);
  472 +
  473 + /* Wait for command done */
  474 + while (!(fspi_read32(priv->flags, &regs->intr)
  475 + & FLEXSPI_INTR_IPCMDDONE_MASK))
  476 + ;
  477 +
  478 + fspi_write32(priv->flags, &regs->intr, FLEXSPI_INTR_IPCMDDONE_MASK);
  479 +
  480 + return 0;
  481 +}
  482 +
  483 +static int fspi_mem_op_read_reg(struct fsl_fspi_priv *priv, u32 seqid, u8 *rxbuf, u32 len)
  484 +{
  485 + struct fsl_fspi_regs *regs = priv->regs;
  486 + u32 data, size;
  487 + int i;
  488 +
  489 + debug("%s, seqid %u, len %u\n", __func__, seqid, len);
  490 +
  491 + /* invalid the RXFIFO first */
  492 + fspi_write32(priv->flags, &regs->iprxfcr, FLEXSPI_IPRXFCR_CLR_MASK);
  493 +
  494 + /* Does not support register read with register address */
  495 + fspi_write32(priv->flags, &regs->ipcr0, priv->cur_amba_base);
  496 +
  497 + fspi_write32(priv->flags, &regs->ipcr1,
  498 + (seqid << FLEXSPI_IPCR1_SEQID_SHIFT) | len);
  499 + /* Trigger the command */
  500 + fspi_write32(priv->flags, &regs->ipcmd, 1);
  501 +
  502 + /* Wait for command done */
  503 + while (!(fspi_read32(priv->flags, &regs->intr)
  504 + & FLEXSPI_INTR_IPCMDDONE_MASK))
  505 + ;
  506 +
  507 + i = 0;
  508 + while ((RX_BUFFER_SIZE >= len) && (len > 0)) {
  509 + data = fspi_read32(priv->flags, &regs->rfdr[i]);
  510 + size = (len < 4) ? len : 4;
  511 + memcpy(rxbuf, &data, size);
  512 + len -= size;
  513 + rxbuf += size;
  514 + i++;
  515 + }
  516 + fspi_write32(priv->flags, &regs->intr, FLEXSPI_INTR_IPRXWA_MASK);
  517 +
  518 + fspi_write32(priv->flags, &regs->iprxfcr, FLEXSPI_IPRXFCR_CLR_MASK);
  519 + fspi_write32(priv->flags, &regs->intr, FLEXSPI_INTR_IPCMDDONE_MASK);
  520 +
  521 + return 0;
  522 +}
  523 +
  524 +static int fspi_mem_op_write(struct fsl_fspi_priv *priv, u32 seqid, u8 *txbuf, u32 len)
  525 +{
  526 + struct fsl_fspi_regs *regs = priv->regs;
  527 + int i, size, tx_size;
  528 + u32 to_or_from = 0;
  529 +
  530 + debug("%s, seqid %u, len %u\n", __func__, seqid, len);
  531 +
  532 + /* invalid the TXFIFO first */
  533 + fspi_write32(priv->flags, &regs->iptxfcr, FLEXSPI_IPTXFCR_CLR_MASK);
  534 +
  535 + fspi_write32(priv->flags, &regs->ipcr0, priv->cur_amba_base);
  536 +
  537 + fspi_write32(priv->flags, &regs->ipcr1,
  538 + (SEQID_WREN << FLEXSPI_IPCR1_SEQID_SHIFT) | 0);
  539 +
  540 + /* Trigger the command */
  541 + fspi_write32(priv->flags, &regs->ipcmd, 1);
  542 +
  543 + /* Wait for command done */
  544 + while (!(fspi_read32(priv->flags, &regs->intr)
  545 + & FLEXSPI_INTR_IPCMDDONE_MASK))
  546 + ;
  547 +
  548 + fspi_write32(priv->flags, &regs->intr, FLEXSPI_INTR_IPCMDDONE_MASK);
  549 +
  550 + /* invalid the TXFIFO first */
  551 + fspi_write32(priv->flags, &regs->iptxfcr, FLEXSPI_IPTXFCR_CLR_MASK);
  552 +
  553 + to_or_from = priv->sf_addr + priv->cur_amba_base;
  554 +
  555 + while (len > 0) {
  556 + fspi_write32(priv->flags, &regs->ipcr0, to_or_from);
  557 +
  558 + tx_size = (len > TX_BUFFER_SIZE) ?
  559 + TX_BUFFER_SIZE : len;
  560 +
  561 + to_or_from += tx_size;
  562 + len -= tx_size;
  563 +
  564 + size = tx_size / 8;
  565 + for (i = 0; i < size; i++) {
  566 + /* Wait for TXFIFO empty*/
  567 + while (!(fspi_read32(priv->flags, &regs->intr)
  568 + & FLEXSPI_INTR_IPTXWE_MASK))
  569 + ;
  570 +
  571 + memcpy(&regs->tfdr, txbuf, 8);
  572 + txbuf += 8;
  573 + fspi_write32(priv->flags, &regs->intr,
  574 + FLEXSPI_INTR_IPTXWE_MASK);
  575 + }
  576 +
  577 + size = tx_size % 8;
  578 + if (size) {
  579 + /* Wait for TXFIFO empty*/
  580 + while (!(fspi_read32(priv->flags, &regs->intr)
  581 + & FLEXSPI_INTR_IPTXWE_MASK))
  582 + ;
  583 +
  584 + memcpy(&regs->tfdr, txbuf, size);
  585 + fspi_write32(priv->flags, &regs->intr,
  586 + FLEXSPI_INTR_IPTXWE_MASK);
  587 + }
  588 +
  589 + fspi_write32(priv->flags, &regs->ipcr1,
  590 + (seqid << FLEXSPI_IPCR1_SEQID_SHIFT) | tx_size);
  591 +
  592 +
  593 + /* Trigger the command */
  594 + fspi_write32(priv->flags, &regs->ipcmd, 1);
  595 +
  596 + /* Wait for command done */
  597 + while (!(fspi_read32(priv->flags, &regs->intr)
  598 + & FLEXSPI_INTR_IPCMDDONE_MASK))
  599 + ;
  600 +
  601 + /* invalid the TXFIFO first */
  602 + fspi_write32(priv->flags, &regs->iptxfcr,
  603 + FLEXSPI_IPTXFCR_CLR_MASK);
  604 + fspi_write32(priv->flags, &regs->intr,
  605 + FLEXSPI_INTR_IPCMDDONE_MASK);
  606 + }
  607 +
  608 + return 0;
  609 +}
  610 +
  611 +#ifndef CONFIG_SYS_FSL_FSPI_AHB
  612 +static void fspi_mem_op_read_data_fifo(struct fsl_fspi_priv *priv, u32 seqid, u8 *rxbuf, u32 len)
  613 +{
  614 + struct fsl_fspi_regs *regs = priv->regs;
  615 + int i, size, rx_size;
  616 + u32 to_or_from;
  617 +
  618 + to_or_from = priv->sf_addr + priv->cur_amba_base;
  619 +
  620 + /* invalid the RXFIFO */
  621 + fspi_write32(priv->flags, &regs->iprxfcr, FLEXSPI_IPRXFCR_CLR_MASK);
  622 +
  623 + while (len > 0) {
  624 + WATCHDOG_RESET();
  625 +
  626 + fspi_write32(priv->flags, &regs->ipcr0, to_or_from);
  627 +
  628 + rx_size = (len > RX_BUFFER_SIZE) ?
  629 + RX_BUFFER_SIZE : len;
  630 +
  631 + fspi_write32(priv->flags, &regs->ipcr1,
  632 + (seqid << FLEXSPI_IPCR1_SEQID_SHIFT) |
  633 + rx_size);
  634 +
  635 + to_or_from += rx_size;
  636 + len -= rx_size;
  637 +
  638 + /* Trigger the command */
  639 + fspi_write32(priv->flags, &regs->ipcmd, 1);
  640 +
  641 + size = rx_size / 8;
  642 + for (i = 0; i < size; ++i) {
  643 + /* Wait for RXFIFO available*/
  644 + while (!(fspi_read32(priv->flags, &regs->intr)
  645 + & FLEXSPI_INTR_IPRXWA_MASK))
  646 + ;
  647 +
  648 + memcpy(rxbuf, &regs->rfdr, 8);
  649 + rxbuf += 8;
  650 +
  651 + /* move the FIFO pointer */
  652 + fspi_write32(priv->flags, &regs->intr,
  653 + FLEXSPI_INTR_IPRXWA_MASK);
  654 + }
  655 +
  656 + size = rx_size % 8;
  657 +
  658 + if (size) {
  659 + /* Wait for data filled*/
  660 + while (!(fspi_read32(priv->flags, &regs->iprxfsts)
  661 + & FLEXSPI_IPRXFSTS_FILL_MASK))
  662 + ;
  663 + memcpy(rxbuf, &regs->rfdr, size);
  664 + }
  665 +
  666 + /* invalid the RXFIFO */
  667 + fspi_write32(priv->flags, &regs->iprxfcr,
  668 + FLEXSPI_IPRXFCR_CLR_MASK);
  669 + fspi_write32(priv->flags, &regs->intr,
  670 + FLEXSPI_INTR_IPCMDDONE_MASK);
  671 + }
  672 +
  673 +}
  674 +
  675 +/* If not use AHB read, read data from ip interface */
  676 +static void fspi_op_read(struct fsl_fspi_priv *priv, u32 *rxbuf, u32 len)
  677 +{
  678 +#ifdef CONFIG_FSPI_QUAD_SUPPORT
  679 + fspi_mem_op_read_data_fifo(priv, SEQID_QUAD_OUTPUT, rxbuf, len);
  680 +#else
  681 + fspi_mem_op_read_data_fifo(priv, SEQID_FAST_READ, rxbuf, len);
  682 +#endif
  683 +}
  684 +#endif
  685 +
  686 +static void fspi_mem_update_read_dummy(struct fsl_fspi_priv *priv, u32 seqid, u8 dm_cycle)
  687 +{
  688 + struct fsl_fspi_regs *regs = priv->regs;
  689 + u32 lut_base, val, instr;
  690 +
  691 + debug("set seqid %u dummy cycle %u\n", seqid, dm_cycle);
  692 +
  693 + /* Unlock the LUT */
  694 + fspi_write32(priv->flags, &regs->lutkey, FLEXSPI_LUTKEY_VALUE);
  695 + fspi_write32(priv->flags, &regs->lutcr, FLEXSPI_LCKER_UNLOCK);
  696 +
  697 + lut_base = seqid * 4;
  698 + val = fspi_read32(priv->flags, &regs->lut[lut_base + 1]);
  699 + instr = (val & INSTR0(0x3f)) >> INSTR0_SHIFT;
  700 +
  701 + if (instr == LUT_DUMMY_DDR || instr == LUT_DUMMY) {
  702 +
  703 + /* for DDR read, the SCLK is half of serial root clock, but dummy cycle in LUT is calculated by serial clock */
  704 + if (instr == LUT_DUMMY_DDR)
  705 + dm_cycle = dm_cycle * 2;
  706 +
  707 + val &= ~(OPRND0(0xff));
  708 + fspi_write32(priv->flags, &regs->lut[lut_base + 1],
  709 + val | OPRND0(dm_cycle));
  710 + } else {
  711 + printf("Fail to update read dummy, no dummy opcode in LUT, seqid %u\n", seqid);
  712 + }
  713 +
  714 + /* Lock the LUT */
  715 + fspi_write32(priv->flags, &regs->lutkey, FLEXSPI_LUTKEY_VALUE);
  716 + fspi_write32(priv->flags, &regs->lutcr, FLEXSPI_LCKER_LOCK);
  717 +}
  718 +
  719 +static int fspi_mem_op_read_data(struct fsl_fspi_priv *priv, u32 seqid, u8 *rxbuf, u32 len)
  720 +{
  721 + debug("%s, seqid %u, len %u\n", __func__, seqid, len);
  722 +
  723 +#if defined(CONFIG_SYS_FSL_FSPI_AHB)
  724 + struct fsl_fspi_regs *regs = priv->regs;
  725 + fspi_write32(priv->flags, &regs->flsha1cr2, seqid);
  726 +
  727 + /* Read out the data directly from the AHB buffer. */
  728 + memcpy(rxbuf, (u8 *)(0x08000000 + (uintptr_t)priv->sf_addr) , len);
  729 +#else
  730 + fspi_mem_op_read_data_fifo(priv, seqid, rxbuf, len);
  731 +#endif
  732 +
  733 + return 0;
  734 +}
  735 +
  736 +#if defined(CONFIG_SYS_FSL_FSPI_AHB)
  737 +/*
  738 + * If we have changed the content of the flash by writing or erasing,
  739 + * we need to invalidate the AHB buffer. If we do not do so, we may read out
  740 + * the wrong data. The spec tells us reset the AHB domain and Serial Flash
  741 + * domain at the same time.
  742 + */
  743 +static inline void fspi_ahb_invalid(struct fsl_fspi_priv *priv)
  744 +{
  745 + struct fsl_fspi_regs *regs = priv->regs;
  746 + u32 reg;
  747 +
  748 + reg = fspi_read32(priv->flags, &regs->mcr0);
  749 + reg |= FLEXSPI_MCR0_SWRST_MASK;
  750 + fspi_write32(priv->flags, &regs->mcr0, reg);
  751 +
  752 + /*
  753 + * The minimum delay : 1 AHB + 2 SFCK clocks.
  754 + * Delay 1 us is enough.
  755 + */
  756 + while ((fspi_read32(priv->flags, &regs->mcr0) & 1))
  757 + ;
  758 +}
  759 +
  760 +#define FSPI_AHB_BASE_ADDR 0x08000000
  761 +/* Read out the data from the AHB buffer. */
  762 +static inline void fspi_ahb_read(struct fsl_fspi_priv *priv, u8 *rxbuf, int len)
  763 +{
  764 + /* Read out the data directly from the AHB buffer. */
  765 + memcpy(rxbuf, (u8 *)(0x08000000 + (uintptr_t)priv->sf_addr) , len);
  766 +
  767 +}
  768 +
  769 +/*
  770 + * There are two different ways to read out the data from the flash:
  771 + * the "IP Command Read" and the "AHB Command Read".
  772 + *
  773 + * The IC guy suggests we use the "AHB Command Read" which is faster
  774 + * then the "IP Command Read". (What's more is that there is a bug in
  775 + * the "IP Command Read" in the Vybrid.)
  776 + *
  777 + * After we set up the registers for the "AHB Command Read", we can use
  778 + * the memcpy to read the data directly. A "missed" access to the buffer
  779 + * causes the controller to clear the buffer, and use the sequence pointed
  780 + * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
  781 + */
  782 +static void fspi_init_ahb_read(struct fsl_fspi_priv *priv)
  783 +{
  784 + struct fsl_fspi_regs *regs = priv->regs;
  785 + int i;
  786 +
  787 + /* AHB configuration for access buffer 0~7 .*/
  788 + for (i = 0; i < 7; i++)
  789 + fspi_write32(priv->flags, &regs->ahbrxbuf0cr0 + i, 0);
  790 +
  791 + /*
  792 + * Set ADATSZ with the maximum AHB buffer size to improve the read
  793 + * performance
  794 + */
  795 + fspi_write32(priv->flags, &regs->ahbrxbuf7cr0, AHB_BUFFER_SIZE / 8 |
  796 + FLEXSPI_AHBRXBUF0CR7_PREF_MASK);
  797 +
  798 + fspi_write32(priv->flags, &regs->ahbcr, FLEXSPI_AHBCR_PREF_EN_MASK);
  799 + /*
  800 + * Set the default lut sequence for AHB Read.
  801 + * Parallel mode is disabled.
  802 + */
  803 +#ifdef CONFIG_FSPI_QUAD_SUPPORT
  804 + fspi_write32(priv->flags, &regs->flsha1cr2, SEQID_QUAD_OUTPUT);
  805 +#else
  806 + fspi_write32(priv->flags, &regs->flsha1cr2, SEQID_FAST_READ);
  807 +#endif
  808 +
  809 +}
  810 +#endif
  811 +
  812 +#ifdef CONFIG_SPI_FLASH_BAR
  813 +/* Bank register read/write, EAR register read/write */
  814 +static void fspi_op_rdbank(struct fsl_fspi_priv *priv, u8 *rxbuf, u32 len)
  815 +{
  816 + if (priv->cur_seqid == FSPI_CMD_BRRD)
  817 + fspi_mem_op_read_reg(priv, SEQID_BRRD, rxbuf, len);
  818 + else
  819 + fspi_mem_op_read_reg(priv, SEQID_RDEAR, rxbuf, len);
  820 +}
  821 +#endif
  822 +
  823 +static void fspi_op_rdevcr(struct fsl_fspi_priv *priv, u8 *rxbuf, u32 len)
  824 +{
  825 + fspi_mem_op_read_reg(priv, SEQID_RDEVCR, rxbuf, len);
  826 +}
  827 +
  828 +static void fspi_op_wrevcr(struct fsl_fspi_priv *priv, u8 *txbuf, u32 len)
  829 +{
  830 + fspi_mem_op_write(priv, SEQID_WREVCR, txbuf, len);
  831 +}
  832 +
  833 +static void fspi_op_rdid(struct fsl_fspi_priv *priv, u32 *rxbuf, u32 len)
  834 +{
  835 + fspi_mem_op_read_reg(priv, SEQID_RDID, (u8 *)rxbuf, len);
  836 +}
  837 +
  838 +static void fspi_op_write(struct fsl_fspi_priv *priv, u8 *txbuf, u32 len)
  839 +{
  840 + if (priv->cur_seqid == FSPI_CMD_BRWR)
  841 + fspi_mem_op_write(priv, SEQID_BRWR, txbuf, len);
  842 + else if (priv->cur_seqid == FSPI_CMD_WREAR)
  843 + fspi_mem_op_write(priv, SEQID_WREAR, txbuf, len);
  844 + else if (priv->cur_seqid == FSPI_CMD_PP)
  845 + fspi_mem_op_write(priv, SEQID_PP, txbuf, len);
  846 + else if (priv->cur_seqid == FSPI_CMD_PP_4B)
  847 + fspi_mem_op_write(priv, SEQID_PP_4B, txbuf, len);
  848 +}
  849 +
  850 +static void fspi_op_rdsr(struct fsl_fspi_priv *priv, void *rxbuf, u32 len)
  851 +{
  852 + fspi_mem_op_read_reg(priv, SEQID_RDSR, rxbuf, len);
  853 +}
  854 +
  855 +static void fspi_op_rdfsr(struct fsl_fspi_priv *priv, void *rxbuf, u32 len)
  856 +{
  857 + fspi_mem_op_read_reg(priv, SEQID_RDFSR, rxbuf, len);
  858 +}
  859 +
  860 +static void fspi_op_erase(struct fsl_fspi_priv *priv)
  861 +{
  862 + fspi_mem_op_cmd(priv, SEQID_WREN, NULL, 0);
  863 +
  864 + if (priv->cur_seqid == FSPI_CMD_SE) {
  865 + fspi_mem_op_cmd(priv, SEQID_SE, NULL, 0);
  866 + } else if (priv->cur_seqid == FSPI_CMD_SE_4B) {
  867 + fspi_mem_op_cmd(priv, SEQID_SE_4B, NULL, 0);
  868 + } else if (priv->cur_seqid == FSPI_CMD_BE_4K) {
  869 + fspi_mem_op_cmd(priv, SEQID_BE_4K, NULL, 0);
  870 + } else if (priv->cur_seqid == FSPI_CMD_BE_4K_4B) {
  871 + fspi_mem_op_cmd(priv, SEQID_BE_4K_4B, NULL, 0);
  872 + }
  873 +}
  874 +
  875 +static void fspi_op_enter_4bytes(struct fsl_fspi_priv *priv)
  876 +{
  877 + fspi_mem_op_cmd(priv, SEQID_EN4B, NULL, 0);
  878 +}
  879 +
  880 +static bool fspi_4bytes_addr_cmd(struct fsl_fspi_priv *priv)
  881 +{
  882 + if (priv->cur_seqid == FSPI_CMD_SE_4B || priv->cur_seqid == FSPI_CMD_BE_4K_4B
  883 + || priv->cur_seqid == FSPI_CMD_FAST_READ_4B || priv->cur_seqid == FSPI_CMD_PP_4B)
  884 + return true;
  885 +
  886 + return false;
  887 +}
  888 +
  889 +int fspi_xfer(struct fsl_fspi_priv *priv, unsigned int bitlen,
  890 + const void *dout, void *din, unsigned long flags)
  891 +{
  892 + u32 bytes = DIV_ROUND_UP(bitlen, 8);
  893 + static u32 wr_sfaddr;
  894 + u32 txbuf = 0;
  895 +
  896 + if (dout) {
  897 + if (flags & SPI_XFER_BEGIN) {
  898 + priv->cur_seqid = *(u8 *)dout;
  899 + if (bytes > 1) {
  900 + int i, addr_bytes;
  901 +
  902 + if (fspi_4bytes_addr_cmd(priv))
  903 + addr_bytes = 4;
  904 + else
  905 + addr_bytes = 3;
  906 +
  907 + dout = (u8 *)dout + 1;
  908 + txbuf = *(u8 *)dout;
  909 + for (i = 1; i < addr_bytes; i++) {
  910 + txbuf <<= 8;
  911 + txbuf |= *(((u8 *)dout) + i);
  912 + }
  913 +
  914 + debug("seqid 0x%x addr 0x%x\n", priv->cur_seqid, txbuf);
  915 + }
  916 + }
  917 +
  918 + if (flags == SPI_XFER_END) {
  919 + if (priv->cur_seqid == FSPI_CMD_WR_EVCR) {
  920 + fspi_op_wrevcr(priv, (u8 *)dout, bytes);
  921 + return 0;
  922 + } else if ((priv->cur_seqid == FSPI_CMD_SE) ||
  923 + (priv->cur_seqid == FSPI_CMD_BE_4K) ||
  924 + (priv->cur_seqid == FSPI_CMD_SE_4B) ||
  925 + (priv->cur_seqid == FSPI_CMD_BE_4K_4B)) {
  926 + int i;
  927 + txbuf = *(u8 *)dout;
  928 + for (i = 1; i < bytes; i++) {
  929 + txbuf <<= 8;
  930 + txbuf |= *(((u8 *)dout) + i);
  931 + }
  932 +
  933 + priv->sf_addr = txbuf;
  934 + fspi_op_erase(priv);
  935 +#ifdef CONFIG_SYS_FSL_FSPI_AHB
  936 + fspi_ahb_invalid(priv);
  937 +#endif
  938 + return 0;
  939 + }
  940 + priv->sf_addr = wr_sfaddr;
  941 + fspi_op_write(priv, (u8 *)dout, bytes);
  942 + return 0;
  943 + }
  944 +
  945 + if (priv->cur_seqid == FSPI_CMD_QUAD_OUTPUT ||
  946 + priv->cur_seqid == FSPI_CMD_FAST_READ ||
  947 + priv->cur_seqid == FSPI_CMD_FAST_READ_4B) {
  948 + priv->sf_addr = txbuf;
  949 + } else if (priv->cur_seqid == FSPI_CMD_PP ||
  950 + priv->cur_seqid == FSPI_CMD_PP_4B) {
  951 + wr_sfaddr = txbuf;
  952 + } else if (priv->cur_seqid == FSPI_CMD_WR_EVCR) {
  953 + wr_sfaddr = 0;
  954 + } else if ((priv->cur_seqid == FSPI_CMD_BRWR) ||
  955 + (priv->cur_seqid == FSPI_CMD_WREAR)) {
  956 +#ifdef CONFIG_SPI_FLASH_BAR
  957 + wr_sfaddr = 0;
  958 +#endif
  959 + } else if (priv->cur_seqid == FSPI_CMD_EN4B) {
  960 + fspi_op_enter_4bytes(priv);
  961 + }
  962 + }
  963 +
  964 + if (din) {
  965 + if (priv->cur_seqid == FSPI_CMD_QUAD_OUTPUT ||
  966 + priv->cur_seqid == FSPI_CMD_FAST_READ ||
  967 + priv->cur_seqid == FSPI_CMD_FAST_READ_4B) {
  968 +#ifdef CONFIG_SYS_FSL_FSPI_AHB
  969 + fspi_ahb_read(priv, din, bytes);
  970 +#else
  971 + fspi_op_read(priv, din, bytes);
  972 +#endif
  973 + } else if (priv->cur_seqid == FSPI_CMD_RDID)
  974 + fspi_op_rdid(priv, din, bytes);
  975 + else if (priv->cur_seqid == FSPI_CMD_RDSR)
  976 + fspi_op_rdsr(priv, din, bytes);
  977 + else if (priv->cur_seqid == FSPI_CMD_RDFSR)
  978 + fspi_op_rdfsr(priv, din, bytes);
  979 + else if (priv->cur_seqid == FSPI_CMD_RD_EVCR)
  980 + fspi_op_rdevcr(priv, din, bytes);
  981 +#ifdef CONFIG_SPI_FLASH_BAR
  982 + else if ((priv->cur_seqid == FSPI_CMD_BRRD) ||
  983 + (priv->cur_seqid == FSPI_CMD_RDEAR)) {
  984 + priv->sf_addr = 0;
  985 + fspi_op_rdbank(priv, din, bytes);
  986 + }
  987 +#endif
  988 + }
  989 +
  990 +#ifdef CONFIG_SYS_FSL_FSPI_AHB
  991 + if ((priv->cur_seqid == FSPI_CMD_SE) ||
  992 + (priv->cur_seqid == FSPI_CMD_SE_4B) ||
  993 + (priv->cur_seqid == FSPI_CMD_PP) ||
  994 + (priv->cur_seqid == FSPI_CMD_PP_4B) ||
  995 + (priv->cur_seqid == FSPI_CMD_BE_4K) ||
  996 + (priv->cur_seqid == FSPI_CMD_BE_4K_4B) ||
  997 + (priv->cur_seqid == FSPI_CMD_WREAR) ||
  998 + (priv->cur_seqid == FSPI_CMD_BRWR))
  999 + fspi_ahb_invalid(priv);
  1000 +#endif
  1001 +
  1002 + return 0;
  1003 +}
  1004 +
  1005 +void fspi_module_disable(struct fsl_fspi_priv *priv, u8 disable)
  1006 +{
  1007 + u32 mcr_val;
  1008 +
  1009 + mcr_val = fspi_read32(priv->flags, &priv->regs->mcr0);
  1010 + if (disable)
  1011 + mcr_val |= FLEXSPI_MCR0_MDIS_MASK;
  1012 + else
  1013 + mcr_val &= ~FLEXSPI_MCR0_MDIS_MASK;
  1014 + fspi_write32(priv->flags, &priv->regs->mcr0, mcr_val);
  1015 +}
  1016 +
  1017 +void fspi_cfg_smpr(struct fsl_fspi_priv *priv, u32 clear_bits, u32 set_bits)
  1018 +{
  1019 + return;
  1020 +#if 0
  1021 + u32 smpr_val;
  1022 +
  1023 + smpr_val = fspi_read32(priv->flags, &priv->regs->smpr);
  1024 + smpr_val &= ~clear_bits;
  1025 + smpr_val |= set_bits;
  1026 + fspi_write32(priv->flags, &priv->regs->smpr, smpr_val);
  1027 +#endif
  1028 +}
  1029 +
  1030 +__weak void init_clk_fspi(int index)
  1031 +{
  1032 +}
  1033 +
  1034 +#ifndef CONFIG_DM_SPI
  1035 +static unsigned long spi_bases[] = {
  1036 + FSPI0_BASE_ADDR,
  1037 +};
  1038 +
  1039 +static unsigned long amba_bases[] = {
  1040 + FSPI0_AMBA_BASE,
  1041 +};
  1042 +
  1043 +static inline struct fsl_fspi *to_fspi_spi(struct spi_slave *slave)
  1044 +{
  1045 + return container_of(slave, struct fsl_fspi, slave);
  1046 +}
  1047 +
  1048 +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  1049 + unsigned int max_hz, unsigned int mode)
  1050 +{
  1051 + struct fsl_fspi *fspi;
  1052 + struct fsl_fspi_regs *regs;
  1053 + u32 total_size;
  1054 +
  1055 + if (bus >= ARRAY_SIZE(spi_bases))
  1056 + return NULL;
  1057 +
  1058 + if (cs >= FSL_FSPI_FLASH_NUM)
  1059 + return NULL;
  1060 +
  1061 + fspi = spi_alloc_slave(struct fsl_fspi, bus, cs);
  1062 + if (!fspi)
  1063 + return NULL;
  1064 +
  1065 +#ifdef CONFIG_SYS_FSL_FSPI_BE
  1066 + fspi->priv.flags |= FSPI_FLAG_REGMAP_ENDIAN_BIG;
  1067 +#endif
  1068 +
  1069 + init_clk_fspi(bus);
  1070 +
  1071 + regs = (struct fsl_fspi_regs *)spi_bases[bus];
  1072 + fspi->priv.regs = regs;
  1073 + /*
  1074 + * According cs, use different amba_base to choose the
  1075 + * corresponding flash devices.
  1076 + *
  1077 + * If not, only one flash device is used even if passing
  1078 + * different cs using `sf probe`
  1079 + */
  1080 + fspi->priv.cur_amba_base = amba_bases[bus] + cs * FSL_FSPI_FLASH_SIZE;
  1081 +
  1082 + fspi->slave.max_write_size = TX_BUFFER_SIZE;
  1083 +
  1084 +#ifdef CONFIG_FSPI_QUAD_SUPPORT
  1085 + fspi->slave.mode |= SPI_RX_QUAD;
  1086 +#endif
  1087 +
  1088 + fspi_write32(fspi->priv.flags, &regs->mcr0,
  1089 + FLEXSPI_MCR0_SWRST_MASK);
  1090 + do {
  1091 + udelay(1);
  1092 + } while (0x1 & fspi_read32(fspi->priv.flags, &regs->mcr0));
  1093 +
  1094 + /* Disable the module */
  1095 + fspi_module_disable(&fspi->priv, 1);
  1096 +
  1097 + /* Enable the module and set to proper value*/
  1098 +#ifdef CONFIG_FSPI_DQS_LOOPBACK
  1099 + fspi_write32(fspi->priv.flags, &regs->mcr0,
  1100 + 0xFFFF0010);
  1101 +#else
  1102 + fspi_write32(fspi->priv.flags, &regs->mcr0,
  1103 + 0xFFFF0000);
  1104 +#endif
  1105 +
  1106 + total_size = FSL_FSPI_FLASH_SIZE * FSL_FSPI_FLASH_NUM >> 10;
  1107 + /*
  1108 + * Any read access to non-implemented addresses will provide
  1109 + * undefined results.
  1110 + *
  1111 + * In case single die flash devices, TOP_ADDR_MEMA2 and
  1112 + * TOP_ADDR_MEMB2 should be initialized/programmed to
  1113 + * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
  1114 + * setting the size of these devices to 0. This would ensure
  1115 + * that the complete memory map is assigned to only one flash device.
  1116 + */
  1117 + fspi_write32(fspi->priv.flags, &regs->flsha1cr0,
  1118 + total_size);
  1119 + fspi_write32(fspi->priv.flags, &regs->flsha2cr0,
  1120 + 0);
  1121 + fspi_write32(fspi->priv.flags, &regs->flshb1cr0,
  1122 + 0);
  1123 + fspi_write32(fspi->priv.flags, &regs->flshb2cr0,
  1124 + 0);
  1125 +
  1126 + fspi_set_lut(&fspi->priv);
  1127 +
  1128 +#ifdef CONFIG_SYS_FSL_FSPI_AHB
  1129 + fspi_init_ahb_read(&fspi->priv);
  1130 +#endif
  1131 +
  1132 + fspi_module_disable(&fspi->priv, 0);
  1133 +
  1134 + return &fspi->slave;
  1135 +}
  1136 +
  1137 +void spi_free_slave(struct spi_slave *slave)
  1138 +{
  1139 + struct fsl_fspi *fspi = to_fspi_spi(slave);
  1140 +
  1141 + free(fspi);
  1142 +}
  1143 +
  1144 +int spi_claim_bus(struct spi_slave *slave)
  1145 +{
  1146 + return 0;
  1147 +}
  1148 +
  1149 +void spi_release_bus(struct spi_slave *slave)
  1150 +{
  1151 + /* Nothing to do */
  1152 +}
  1153 +
  1154 +int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
  1155 + const void *dout, void *din, unsigned long flags)
  1156 +{
  1157 + struct fsl_fspi *fspi = to_fspi_spi(slave);
  1158 +
  1159 + return fspi_xfer(&fspi->priv, bitlen, dout, din, flags);
  1160 +}
  1161 +
  1162 +void spi_init(void)
  1163 +{
  1164 + /* Nothing to do */
  1165 +}
  1166 +#else
  1167 +
  1168 +struct fspi_cmd_func_pair fspi_supported_cmds[SEQID_END] = {
  1169 + {FSPI_CMD_READ, false, &fspi_mem_op_read_data},
  1170 + {FSPI_CMD_WREN, false, &fspi_mem_op_cmd},
  1171 + {FSPI_CMD_FAST_READ, false, &fspi_mem_op_read_data},
  1172 + {FSPI_CMD_FAST_READ_4B, false, &fspi_mem_op_read_data},
  1173 + {FSPI_CMD_RDSR, false, &fspi_mem_op_read_reg},
  1174 + {FSPI_CMD_SE, true, &fspi_mem_op_cmd},
  1175 + {FSPI_CMD_SE_4B, true, &fspi_mem_op_cmd},
  1176 + {FSPI_CMD_CHIP_ERASE, true, &fspi_mem_op_cmd},
  1177 + {FSPI_CMD_PP, true, &fspi_mem_op_write},
  1178 + {FSPI_CMD_PP_4B, true, &fspi_mem_op_write},
  1179 + {FSPI_CMD_RDID, false, &fspi_mem_op_read_reg},
  1180 + {FSPI_CMD_BE_4K, true, &fspi_mem_op_cmd},
  1181 + {FSPI_CMD_BE_4K_4B, true, &fspi_mem_op_cmd},
  1182 + {FSPI_CMD_BRRD, false, &fspi_mem_op_read_reg},
  1183 + {FSPI_CMD_BRWR, true, &fspi_mem_op_write},
  1184 + {FSPI_CMD_RDEAR, false, &fspi_mem_op_read_reg},
  1185 + {FSPI_CMD_WREAR, true, &fspi_mem_op_write},
  1186 + {FSPI_CMD_RD_EVCR, false, &fspi_mem_op_read_reg},
  1187 + {FSPI_CMD_WR_EVCR, false, &fspi_mem_op_write},
  1188 + {FSPI_CMD_QUAD_OUTPUT, false, &fspi_mem_op_read_data},
  1189 + {FSPI_CMD_DDR_QUAD_OUTPUT, false, &fspi_mem_op_read_data},
  1190 + {FSPI_CMD_RDFSR, false, &fspi_mem_op_read_reg},
  1191 + {FSPI_CMD_EN4B, false, &fspi_mem_op_cmd},
  1192 + {FSPI_CMD_WRDI, false, &fspi_mem_op_cmd},
  1193 + {FSPI_CMD_QUAD_PP, true, &fspi_mem_op_write},
  1194 +};
  1195 +
  1196 +static int fsl_fspi_child_pre_probe(struct udevice *dev)
  1197 +{
  1198 + struct spi_slave *slave = dev_get_parent_priv(dev);
  1199 +
  1200 + slave->max_write_size = TX_BUFFER_SIZE;
  1201 +
  1202 +#ifdef CONFIG_FSPI_QUAD_SUPPORT
  1203 + slave->mode |= SPI_RX_QUAD;
  1204 +#endif
  1205 +
  1206 + return 0;
  1207 +}
  1208 +
  1209 +static int fsl_fspi_probe(struct udevice *bus)
  1210 +{
  1211 + u32 total_size;
  1212 + struct fsl_fspi_platdata *plat = dev_get_platdata(bus);
  1213 + struct fsl_fspi_priv *priv = dev_get_priv(bus);
  1214 + struct dm_spi_bus *dm_spi_bus;
  1215 +
  1216 + if (CONFIG_IS_ENABLED(CLK)) {
  1217 + /* Assigned clock already set clock */
  1218 + struct clk fspi_clk;
  1219 + int ret;
  1220 +
  1221 + ret = clk_get_by_name(bus, "fspi", &fspi_clk);
  1222 + if (ret < 0) {
  1223 + printf("Can't get fspi clk: %d\n", ret);
  1224 + return ret;
  1225 + }
  1226 +
  1227 + ret = clk_enable(&fspi_clk);
  1228 + if (ret < 0) {
  1229 + printf("Can't enable fspi clk: %d\n", ret);
  1230 + return ret;
  1231 + }
  1232 + } else {
  1233 + init_clk_fspi(bus->seq);
  1234 + }
  1235 + dm_spi_bus = bus->uclass_priv;
  1236 +
  1237 + dm_spi_bus->max_hz = plat->speed_hz;
  1238 +
  1239 + priv->regs = (struct fsl_fspi_regs *)(uintptr_t)plat->reg_base;
  1240 + priv->flags = plat->flags;
  1241 +
  1242 + priv->speed_hz = plat->speed_hz;
  1243 + priv->amba_base[0] = plat->amba_base;
  1244 + priv->amba_total_size = plat->amba_total_size;
  1245 + priv->flash_num = plat->flash_num;
  1246 + priv->num_chipselect = plat->num_chipselect;
  1247 + priv->read_dummy = 0;
  1248 +
  1249 + fspi_write32(priv->flags, &priv->regs->mcr0,
  1250 + FLEXSPI_MCR0_SWRST_MASK);
  1251 + do {
  1252 + udelay(1);
  1253 + } while (0x1 & fspi_read32(priv->flags, &priv->regs->mcr0));
  1254 +
  1255 + /* Disable the module */
  1256 + fspi_module_disable(priv, 1);
  1257 +
  1258 + /* Enable the module and set to proper value*/
  1259 +#ifdef CONFIG_FSPI_DQS_LOOPBACK
  1260 + fspi_write32(priv->flags, &priv->regs->mcr0,
  1261 + 0xFFFF0010);
  1262 +#else
  1263 + fspi_write32(priv->flags, &priv->regs->mcr0,
  1264 + 0xFFFF0000);
  1265 +#endif
  1266 +
  1267 + /* Reset the DLL register to default value */
  1268 + fspi_write32(priv->flags, &priv->regs->dllacr, 0x0100);
  1269 + fspi_write32(priv->flags, &priv->regs->dllbcr, 0x0100);
  1270 +
  1271 + /* Flash Size in KByte */
  1272 + total_size = FSL_FSPI_FLASH_SIZE * FSL_FSPI_FLASH_NUM >> 10;
  1273 +
  1274 + /*
  1275 + * Any read access to non-implemented addresses will provide
  1276 + * undefined results.
  1277 + *
  1278 + * In case single die flash devices, TOP_ADDR_MEMA2 and
  1279 + * TOP_ADDR_MEMB2 should be initialized/programmed to
  1280 + * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
  1281 + * setting the size of these devices to 0. This would ensure
  1282 + * that the complete memory map is assigned to only one flash device.
  1283 + */
  1284 +
  1285 + fspi_write32(priv->flags, &priv->regs->flsha1cr0,
  1286 + total_size);
  1287 + fspi_write32(priv->flags, &priv->regs->flsha2cr0,
  1288 + 0);
  1289 + fspi_write32(priv->flags, &priv->regs->flshb1cr0,
  1290 + 0);
  1291 + fspi_write32(priv->flags, &priv->regs->flshb2cr0,
  1292 + 0);
  1293 +
  1294 + fspi_set_lut(priv);
  1295 +
  1296 +#ifdef CONFIG_SYS_FSL_FSPI_AHB
  1297 + fspi_init_ahb_read(priv);
  1298 +#endif
  1299 +
  1300 + fspi_module_disable(priv, 0);
  1301 +
  1302 + return 0;
  1303 +}
  1304 +
  1305 +static int fsl_fspi_ofdata_to_platdata(struct udevice *bus)
  1306 +{
  1307 + struct fdt_resource res_regs, res_mem;
  1308 + struct fsl_fspi_platdata *plat = bus->platdata;
  1309 + const void *blob = gd->fdt_blob;
  1310 + int node = ofnode_to_offset(bus->node);
  1311 + int ret, flash_num = 0, subnode;
  1312 +
  1313 + if (fdtdec_get_bool(blob, node, "big-endian"))
  1314 + plat->flags |= FSPI_FLAG_REGMAP_ENDIAN_BIG;
  1315 +
  1316 + ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
  1317 + "FlexSPI", &res_regs);
  1318 + if (ret) {
  1319 + debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
  1320 + return -ENOMEM;
  1321 + }
  1322 + ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
  1323 + "FlexSPI-memory", &res_mem);
  1324 + if (ret) {
  1325 + debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
  1326 + return -ENOMEM;
  1327 + }
  1328 +
  1329 + /* Count flash numbers */
  1330 + fdt_for_each_subnode(subnode, blob, node)
  1331 + ++flash_num;
  1332 +
  1333 + if (flash_num == 0) {
  1334 + debug("Error: Missing flashes!\n");
  1335 + return -ENODEV;
  1336 + }
  1337 +
  1338 + plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
  1339 + FSL_FSPI_DEFAULT_SCK_FREQ);
  1340 + plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
  1341 + FSL_FSPI_MAX_CHIPSELECT_NUM);
  1342 +
  1343 + plat->reg_base = res_regs.start;
  1344 + plat->amba_base = 0;
  1345 + plat->amba_total_size = res_mem.end - res_mem.start + 1;
  1346 + plat->flash_num = flash_num;
  1347 +
  1348 + debug("%s: regs=<0x%x> <0x%x, 0x%x>, max-frequency=%d, endianess=%s\n",
  1349 + __func__,
  1350 + plat->reg_base,
  1351 + plat->amba_base,
  1352 + plat->amba_total_size,
  1353 + plat->speed_hz,
  1354 + plat->flags & FSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
  1355 + );
  1356 +
  1357 + return 0;
  1358 +}
  1359 +
  1360 +static int fsl_fspi_xfer(struct udevice *dev, unsigned int bitlen,
  1361 + const void *dout, void *din, unsigned long flags)
  1362 +{
  1363 + struct fsl_fspi_priv *priv;
  1364 + struct udevice *bus;
  1365 +
  1366 + bus = dev->parent;
  1367 + priv = dev_get_priv(bus);
  1368 +
  1369 + return fspi_xfer(priv, bitlen, dout, din, flags);
  1370 +}
  1371 +
  1372 +static int fsl_fspi_claim_bus(struct udevice *dev)
  1373 +{
  1374 + struct fsl_fspi_priv *priv;
  1375 + struct udevice *bus;
  1376 + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  1377 +
  1378 + bus = dev->parent;
  1379 + priv = dev_get_priv(bus);
  1380 +
  1381 + priv->cur_amba_base =
  1382 + priv->amba_base[0] + FSL_FSPI_FLASH_SIZE * slave_plat->cs;
  1383 +
  1384 + return 0;
  1385 +}
  1386 +
  1387 +static int fsl_fspi_release_bus(struct udevice *dev)
  1388 +{
  1389 + return 0;
  1390 +}
  1391 +
  1392 +static int fsl_fspi_set_speed(struct udevice *bus, uint speed)
  1393 +{
  1394 + /* Nothing to do */
  1395 + return 0;
  1396 +}
  1397 +
  1398 +static int fsl_fspi_set_mode(struct udevice *bus, uint mode)
  1399 +{
  1400 + /* Nothing to do */
  1401 + return 0;
  1402 +}
  1403 +
  1404 +static int fsl_fspi_get_lut_index(const struct spi_mem_op *op)
  1405 +{
  1406 + int i;
  1407 +
  1408 + for (i = 0; i < SEQID_END; i++) {
  1409 + if (fspi_supported_cmds[i].cmd == op->cmd.opcode)
  1410 + break;
  1411 + }
  1412 +
  1413 + return i;
  1414 +}
  1415 +
  1416 +bool fsl_fspi_supports_op(struct spi_slave *slave, const struct spi_mem_op *op)
  1417 +{
  1418 + int i;
  1419 +
  1420 + if (!op || !slave)
  1421 + return false;
  1422 +
  1423 + i = fsl_fspi_get_lut_index(op);
  1424 + if (i == SEQID_END) {
  1425 + printf("fsl_fspi_nor: fail to find cmd 0x%x from lut\n", op->cmd.opcode);
  1426 + return false;
  1427 + }
  1428 +
  1429 + debug("fsl_fspi_nor: find seqid %d for cmd 0x%x from lut\n", i, op->cmd.opcode);
  1430 +
  1431 + return true;
  1432 +}
  1433 +
  1434 +int fsl_fspi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
  1435 +{
  1436 + int i, j, ret;
  1437 + struct fsl_fspi_priv *priv;
  1438 + struct udevice *bus;
  1439 +
  1440 + bus = slave->dev->parent;
  1441 + priv = dev_get_priv(bus);
  1442 +
  1443 + if (!op || !slave)
  1444 + return -EINVAL;
  1445 +
  1446 + i = fsl_fspi_get_lut_index(op);
  1447 + if (i == SEQID_END) {
  1448 + printf("fsl_fspi_nor: fail to find cmd 0x%x from lut\n", op->cmd.opcode);
  1449 + return -EPERM;
  1450 + }
  1451 +
  1452 + if (op->addr.nbytes)
  1453 + priv->sf_addr = op->addr.val;
  1454 + else
  1455 + priv->sf_addr = 0;
  1456 +
  1457 + if (op->data.nbytes) {
  1458 + if (op->data.dir == SPI_MEM_DATA_IN) {
  1459 + if (op->dummy.nbytes && priv->read_dummy != op->dummy.nbytes * 8) {
  1460 + priv->read_dummy = op->dummy.nbytes * 8;
  1461 + fspi_mem_update_read_dummy(priv, i, priv->read_dummy);
  1462 + }
  1463 +
  1464 + ret = fspi_supported_cmds[i].fspi_op_func(priv, i, op->data.buf.in, op->data.nbytes);
  1465 + } else if (fspi_supported_cmds[i].fspi_op_func == &fspi_mem_op_cmd) {
  1466 + /* Erase command set address in data component */
  1467 + u8 *buf = (u8 *)op->data.buf.out;
  1468 + priv->sf_addr = 0;
  1469 + for (j = 0; j < op->data.nbytes; j++) {
  1470 + priv->sf_addr |= *buf << ((op->data.nbytes - j - 1) * 8);
  1471 + buf++;
  1472 + }
  1473 + ret = fspi_supported_cmds[i].fspi_op_func(priv, i, NULL, 0);
  1474 + } else {
  1475 + ret = fspi_supported_cmds[i].fspi_op_func(priv, i, (void *)op->data.buf.out, op->data.nbytes);
  1476 + }
  1477 + } else {
  1478 + ret = fspi_supported_cmds[i].fspi_op_func(priv, i, NULL, 0);
  1479 + }
  1480 +
  1481 +#if defined(CONFIG_SYS_FSL_FSPI_AHB)
  1482 + if (fspi_supported_cmds[i].ahb_invalid)
  1483 + fspi_ahb_invalid(priv);
  1484 +#endif
  1485 +
  1486 + return ret;
  1487 +}
  1488 +
  1489 +int fsl_fspi_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op)
  1490 +{
  1491 + if (op->data.nbytes > 0) {
  1492 + if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes > RX_BUFFER_SIZE)
  1493 + op->data.nbytes = RX_BUFFER_SIZE;
  1494 + else if (op->data.dir == SPI_MEM_DATA_OUT && op->data.nbytes > TX_BUFFER_SIZE)
  1495 + op->data.nbytes = TX_BUFFER_SIZE;
  1496 + }
  1497 +
  1498 + return 0;
  1499 +}
  1500 +
  1501 +static struct spi_controller_mem_ops fsl_fspi_mem_ops = {
  1502 + .adjust_op_size = fsl_fspi_adjust_op_size,
  1503 + .supports_op = fsl_fspi_supports_op,
  1504 + .exec_op = fsl_fspi_exec_op,
  1505 +};
  1506 +
  1507 +static const struct dm_spi_ops fsl_fspi_ops = {
  1508 + .claim_bus = fsl_fspi_claim_bus,
  1509 + .release_bus = fsl_fspi_release_bus,
  1510 + .xfer = fsl_fspi_xfer,
  1511 + .set_speed = fsl_fspi_set_speed,
  1512 + .set_mode = fsl_fspi_set_mode,
  1513 + .mem_ops = &fsl_fspi_mem_ops,
  1514 +};
  1515 +
  1516 +static const struct udevice_id fsl_fspi_ids[] = {
  1517 + { .compatible = "fsl,imx8qm-flexspi" },
  1518 + { .compatible = "fsl,imx8qxp-flexspi" },
  1519 + { .compatible = "fsl,imx8mm-flexspi" },
  1520 + { }
  1521 +};
  1522 +
  1523 +U_BOOT_DRIVER(fsl_fspi) = {
  1524 + .name = "fsl_fspi",
  1525 + .id = UCLASS_SPI,
  1526 + .of_match = fsl_fspi_ids,
  1527 + .ops = &fsl_fspi_ops,
  1528 + .ofdata_to_platdata = fsl_fspi_ofdata_to_platdata,
  1529 + .platdata_auto_alloc_size = sizeof(struct fsl_fspi_platdata),
  1530 + .priv_auto_alloc_size = sizeof(struct fsl_fspi_priv),
  1531 + .probe = fsl_fspi_probe,
  1532 + .child_pre_probe = fsl_fspi_child_pre_probe,
  1533 +};
  1534 +#endif
drivers/spi/fsl_fspi.h
Diff comments   View file @ e542054
  1 +/*
  2 + * Copyright 2017 NXP
  3 + *
  4 + * Register definitions for NXP FLEXSPI
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef _FSL_FSPI_H_
  10 +#define _FSL_FSPI_H_
  11 +
  12 +struct fsl_fspi_regs {
  13 + u32 mcr0;
  14 + u32 mcr1;
  15 + u32 mcr2;
  16 + u32 ahbcr;
  17 + u32 inten;
  18 + u32 intr;
  19 + u32 lutkey;
  20 + u32 lutcr;
  21 + u32 ahbrxbuf0cr0;
  22 + u32 ahbrxbuf1cr0;
  23 + u32 ahbrxbuf2cr0;
  24 + u32 ahbrxbuf3cr0;
  25 + u32 ahbrxbuf4cr0;
  26 + u32 ahbrxbuf5cr0;
  27 + u32 ahbrxbuf6cr0;
  28 + u32 ahbrxbuf7cr0;
  29 + u32 ahbrxbuf0cr1;
  30 + u32 ahbrxbuf1cr1;
  31 + u32 ahbrxbuf2cr1;
  32 + u32 ahbrxbuf3cr1;
  33 + u32 ahbrxbuf4cr1;
  34 + u32 ahbrxbuf5cr1;
  35 + u32 ahbrxbuf6cr1;
  36 + u32 ahbrxbuf7cr1;
  37 + u32 flsha1cr0;
  38 + u32 flsha2cr0;
  39 + u32 flshb1cr0;
  40 + u32 flshb2cr0;
  41 + u32 flsha1cr1;
  42 + u32 flsha2cr1;
  43 + u32 flshb1cr1;
  44 + u32 flshb2cr1;
  45 + u32 flsha1cr2;
  46 + u32 flsha2cr2;
  47 + u32 flshb1cr2;
  48 + u32 flshb2cr2;
  49 + u32 flshcr3;
  50 + u32 flshcr4;
  51 + u32 flshcr5;
  52 + u32 flshcr6;
  53 + u32 ipcr0;
  54 + u32 ipcr1;
  55 + u32 ipcr2;
  56 + u32 ipcr3;
  57 + u32 ipcmd;
  58 + u32 dlpr;
  59 + u32 iprxfcr;
  60 + u32 iptxfcr;
  61 + u32 dllacr;
  62 + u32 dllbcr;
  63 + u32 soccr;
  64 + u32 misccr2;
  65 + u32 misccr3;
  66 + u32 misccr4;
  67 + u32 misccr5;
  68 + u32 misccr6;
  69 + u32 sts0;
  70 + u32 sts1;
  71 + u32 sts2;
  72 + u32 ahbspndsts;
  73 + u32 iprxfsts;
  74 + u32 iptxfsts;
  75 + u32 rsvd[2];
  76 + u32 rfdr[32];
  77 + u32 tfdr[32];
  78 + u32 lut[128];
  79 +};
  80 +
  81 +/* The registers */
  82 +#define FLEXSPI_MCR0_AHB_TIMEOUT_SHIFT 24
  83 +#define FLEXSPI_MCR0_AHB_TIMEOUT_MASK (0xFF << FLEXSPI_MCR0_IP_TIMOUT_SHIFT)
  84 +#define FLEXSPI_MCR0_IP_TIMOEUT_SHIFT 16
  85 +#define FLEXSPI_MCR0_IP_TIMOEUT_MASK (0xFF << FLEXSPI_MCR0_IP_TIMOUT_SHIFT)
  86 +#define FLEXSPI_MCR0_TSTMD_SHIFT 15
  87 +#define FLEXSPI_MCR0_TSTMD_MASK (1 << FLEXSPI_MCR0_TSTMD_SHIFT)
  88 +#define FLEXSPI_MCR0_LEARN_EN_SHIFT 14
  89 +#define FLEXSPI_MCR0_LEARN_EN_MASK (1 << FLEXSPI_MCR0_DDR_EN_SHIFT)
  90 +#define FLEXSPI_MCR0_SCRFRUN_EN_SHIFT 13
  91 +#define FLEXSPI_MCR0_SCRFRUN_EN_MASK (1 << FLEXSPI_MCR0_DDR_EN_SHIFT)
  92 +#define FLEXSPI_MCR0_COTCOMB_EN_SHIFT 12
  93 +#define FLEXSPI_MCR0_OCTCOMB_EN_MASK (1 << FLEXSPI_MCR0_OCTCOMB_EN_SHIFT)
  94 +#define FLEXSPI_MCR0_HSEN_SHIFT 11
  95 +#define FLEXSPI_MCR0_HSEN_MASK (1 << FLEXSPI_HSEN_SHIFT)
  96 +#define FLEXSPI_MCR0_SERCLKDIV_SHIFT 8
  97 +#define FLEXSPI_MCR0_SERCLKDIV_MASK (7 << FLEXSPI_MCR0_SERCLKDIV_SHIFT)
  98 +#define FLEXSPI_MCR0_ATDF_EN_SHIFT 7
  99 +#define FLEXSPI_MCR0_ATDF_EN_MASK (1 << FLEXSPI_MCR0_ATDF_EN_SHIFT)
  100 +#define FLEXSPI_MCR0_ARDF_EN_SHIFT 6
  101 +#define FLEXSPI_MCR0_ARDF_EN_MASK (1 << FLEXSPI_MCR0_ARDF_EN_SHIFT)
  102 +#define FLEXSPI_MCR0_RXCLKSRC_SHIFT 4
  103 +#define FLEXSPI_MCR0_RXCLKSRC_MASK (3 << FLEXSPI_MCR0_RXCLKSRC_SHIFT)
  104 +#define FLEXSPI_MCR0_END_CFG_SHIFT 2
  105 +#define FLEXSPI_MCR0_END_CFG_MASK (3 << FLEXSPI_MCR0_END_CFG_SHIFT)
  106 +#define FLEXSPI_MCR0_MDIS_SHIFT 1
  107 +#define FLEXSPI_MCR0_MDIS_MASK (1 << FLEXSPI_MCR0_MDIS_SHIFT)
  108 +#define FLEXSPI_MCR0_SWRST_SHIFT 0
  109 +#define FLEXSPI_MCR0_SWRST_MASK (1 << FLEXSPI_MCR0_SWRST_SHIFT)
  110 +
  111 +#define FLEXSPI_MCR1_SEQ_TIMEOUT_SHIFT 16
  112 +#define FLEXSPI_MCR1_SEQ_TIMEOUT_MASK (0xFFFF << FLEXSPI_MCR1_SEQ_TIMEOUT_SHIFT)
  113 +#define FLEXSPI_MCR1_AHB_TIMEOUT_SHIFT 0
  114 +#define FLEXSPI_MCR1_AHB_TIMEOUT_MASK (0xFFFF << FLEXSPI_MCR1_SEQ_TIMEOUT_SHIFT)
  115 +
  116 +#define FLEXSPI_MCR2_IDLE_WAIT_SHIFT 24
  117 +#define FLEXSPI_MCR2_IDLE_WAIT_MASK (0xFF << FLEXSPI_MCR2_IDLE_WAIT_SHIFT)
  118 +#define FLEXSPI_MCR2_SAMEFLASH_SHIFT 15
  119 +#define FLEXSPI_MCR2_SAMEFLASH_MASK (1 << FLEXSPI_MCR2_SAMEFLASH_SHIFT)
  120 +#define FLEXSPI_MCR2_CLRLRPHS_SHIFT 14
  121 +#define FLEXSPI_MCR2_CLRLRPHS_MASK (1 << FLEXSPI_MCR2_CLRLRPHS_SHIFT)
  122 +#define FLEXSPI_MCR2_ABRDATSZ_SHIFT 8
  123 +#define FLEXSPI_MCR2_ABRDATSZ_MASK (1 << FLEXSPI_MCR2_ABRDATSZ_SHIFT)
  124 +#define FLEXSPI_MCR2_ABRLEARN_SHIFT 7
  125 +#define FLEXSPI_MCR2_ABRLEARN_MASK (1 << FLEXSPI_MCR2_ABRLEARN_SHIFT)
  126 +#define FLEXSPI_MCR2_ABR_READ_SHIFT 6
  127 +#define FLEXSPI_MCR2_ABR_READ_MASK (1 << FLEXSPI_MCR2_ABR_READ_SHIFT)
  128 +#define FLEXSPI_MCR2_ABRWRITE_SHIFT 5
  129 +#define FLEXSPI_MCR2_ABRWRITE_MASK (1 << FLEXSPI_MCR2_ABRWRITE_SHIFT)
  130 +#define FLEXSPI_MCR2_ABRDUMMY_SHIFT 4
  131 +#define FLEXSPI_MCR2_ABRDUMMY_MASK (1 << FLEXSPI_MCR2_ABRDUMMY_SHIFT)
  132 +#define FLEXSPI_MCR2_ABR_MODE_SHIFT 3
  133 +#define FLEXSPI_MCR2_ABR_MODE_MASK (1 << FLEXSPI_MCR2_ABR_MODE_SHIFT)
  134 +#define FLEXSPI_MCR2_ABRCADDR_SHIFT 2
  135 +#define FLEXSPI_MCR2_ABRCADDR_MASK (1 << FLEXSPI_MCR2_ABRCADDR_SHIFT)
  136 +#define FLEXSPI_MCR2_ABRRADDR_SHIFT 1
  137 +#define FLEXSPI_MCR2_ABRRADDR_MASK (1 << FLEXSPI_MCR2_ABRRADDR_SHIFT)
  138 +#define FLEXSPI_MCR2_ABR_CMD_SHIFT 0
  139 +#define FLEXSPI_MCR2_ABR_CMD_MASK (1 << FLEXSPI_MCR2_ABR_CMD_SHIFT)
  140 +
  141 +#define FLEXSPI_AHBCR_PREF_EN_SHIFT 5
  142 +#define FLEXSPI_AHBCR_PREF_EN_MASK (1 << FLEXSPI_AHBCR_PREF_EN_SHIFT)
  143 +#define FLEXSPI_AHBCR_BUFF_EN_SHIFT 4
  144 +#define FLEXSPI_AHBCR_BUFF_EN_MASK (1 << FLEXSPI_AHBCR_BUFF_EN_SHIFT)
  145 +#define FLEXSPI_AHBCR_CACH_EN_SHIFT 3
  146 +#define FLEXSPI_AHBCR_CACH_EN_MASK (1 << FLEXSPI_AHBCR_CACH_EN_SHIFT)
  147 +#define FLEXSPI_AHBCR_CLRTXBUF_SHIFT 2
  148 +#define FLEXSPI_AHBCR_CLRTXBUF_MASK (1 << FLEXSPI_AHBCR_CLRTXBUF_SHIFT)
  149 +#define FLEXSPI_AHBCR_CLRRXBUF_SHIFT 1
  150 +#define FLEXSPI_AHBCR_CLRRXBUF_MASK (1 << FLEXSPI_AHBCR_CLRRXBUF_SHIFT)
  151 +#define FLEXSPI_AHBCR_PAR_EN_SHIFT 0
  152 +#define FLEXSPI_AHBCR_PAR_EN_MASK (1 << FLEXSPI_AHBCR_PAR_EN_SHIFT)
  153 +
  154 +#define FLEXSPI_INTEN_SCLKSBWR_SHIFT 9
  155 +#define FLEXSPI_INTEN_SCLKSBWR_MASK (1 << FLEXSPI_INTEN_SCLKSBWR_SHIFT)
  156 +#define FLEXSPI_INTEN_SCLKSBRD_SHIFT 8
  157 +#define FLEXSPI_INTEN_SCLKSBRD_MASK (1 << FLEXSPI_INTEN_SCLKSBRD_SHIFT)
  158 +#define FLEXSPI_INTEN_DATALRNFL_SHIFT 7
  159 +#define FLEXSPI_INTEN_DATALRNFL_MASK (1 << FLEXSPI_INTEN_DATALRNFL_SHIFT)
  160 +#define FLEXSPI_INTEN_IPTXWE_SHIFT 6
  161 +#define FLEXSPI_INTEN_IPTXWE_MASK (1 << FLEXSPI_INTEN_IPTXWE_SHIFT)
  162 +#define FLEXSPI_INTEN_IPRXWA_SHIFT 5
  163 +#define FLEXSPI_INTEN_IPRXWA_MASK (1 << FLEXSPI_INTEN_IPRXWA_SHIFT)
  164 +#define FLEXSPI_INTEN_AHBCMDERR_SHIFT 4
  165 +#define FLEXSPI_INTEN_AHBCMDERR_MASK (1 << FLEXSPI_INTEN_AHBCMDERR_SHIFT)
  166 +#define FLEXSPI_INTEN_IPCMDERR_SHIFT 3
  167 +#define FLEXSPI_INTEN_IPCMDERR_MASK (1 << FLEXSPI_INTEN_IPCMDERR_SHIFT)
  168 +#define FLEXSPI_INTEN_AHBCMDGE_SHIFT 2
  169 +#define FLEXSPI_INTEN_AHBCMDGE_MASK (1 << FLEXSPI_INTEN_AHBCMDGE_SHIFT)
  170 +#define FLEXSPI_INTEN_IPCMDGE_SHIFT 1
  171 +#define FLEXSPI_INTEN_IPCMDGE_MASK (1 << FLEXSPI_INTEN_IPCMDGE_SHIFT)
  172 +#define FLEXSPI_INTEN_IPCMDDONE_SHIFT 0
  173 +#define FLEXSPI_INTEN_IPCMDDONE_MASK (1 << FLEXSPI_INTEN_IPCMDDONE_SHIFT)
  174 +
  175 +#define FLEXSPI_INTR_SCLKSBWR_SHIFT 9
  176 +#define FLEXSPI_INTR_SCLKSBWR_MASK (1 << FLEXSPI_INTR_SCLKSBWR_SHIFT)
  177 +#define FLEXSPI_INTR_SCLKSBRD_SHIFT 8
  178 +#define FLEXSPI_INTR_SCLKSBRD_MASK (1 << FLEXSPI_INTR_SCLKSBRD_SHIFT)
  179 +#define FLEXSPI_INTR_DATALRNFL_SHIFT 7
  180 +#define FLEXSPI_INTR_DATALRNFL_MASK (1 << FLEXSPI_INTR_DATALRNFL_SHIFT)
  181 +#define FLEXSPI_INTR_IPTXWE_SHIFT 6
  182 +#define FLEXSPI_INTR_IPTXWE_MASK (1 << FLEXSPI_INTR_IPTXWE_SHIFT)
  183 +#define FLEXSPI_INTR_IPRXWA_SHIFT 5
  184 +#define FLEXSPI_INTR_IPRXWA_MASK (1 << FLEXSPI_INTR_IPRXWA_SHIFT)
  185 +#define FLEXSPI_INTR_AHBCMDERR_SHIFT 4
  186 +#define FLEXSPI_INTR_AHBCMDERR_MASK (1 << FLEXSPI_INTR_AHBCMDERR_SHIFT)
  187 +#define FLEXSPI_INTR_IPCMDERR_SHIFT 3
  188 +#define FLEXSPI_INTR_IPCMDERR_MASK (1 << FLEXSPI_INTR_IPCMDERR_SHIFT)
  189 +#define FLEXSPI_INTR_AHBCMDGE_SHIFT 2
  190 +#define FLEXSPI_INTR_AHBCMDGE_MASK (1 << FLEXSPI_INTR_AHBCMDGE_SHIFT)
  191 +#define FLEXSPI_INTR_IPCMDGE_SHIFT 1
  192 +#define FLEXSPI_INTR_IPCMDGE_MASK (1 << FLEXSPI_INTR_IPCMDGE_SHIFT)
  193 +#define FLEXSPI_INTR_IPCMDDONE_SHIFT 0
  194 +#define FLEXSPI_INTR_IPCMDDONE_MASK (1 << FLEXSPI_INTR_IPCMDDONE_SHIFT)
  195 +
  196 +#define FLEXSPI_LUTKEY_VALUE 0x5AF05AF0
  197 +
  198 +#define FLEXSPI_LCKER_LOCK 0x1
  199 +#define FLEXSPI_LCKER_UNLOCK 0x2
  200 +
  201 +#define FLEXSPI_BUFXCR_INVALID_MSTRID 0xe
  202 +#define FLEXSPI_AHBRXBUF0CR7_PREF_SHIFT 31
  203 +#define FLEXSPI_AHBRXBUF0CR7_PREF_MASK (1 << FLEXSPI_AHBRXBUF0CR7_PREF_SHIFT)
  204 +
  205 +#define FLEXSPI_BUFXCR1_MSID_SHIFT 0
  206 +#define FLEXSPI_BUFXCR1_MSID_MASK (0xF << FLEXSPI_BUFXCR1_MSID_SHIFT)
  207 +#define FLEXSPI_BUFXCR1_PRIO_SHIFT 8
  208 +#define FLEXSPI_BUFXCR1_PRIO_MASK (0x7 << FLEXSPI_BUFXCR1_PRIO_SHIFT)
  209 +
  210 +#define FLEXSPI_FLSHXCR0_SZ_SHIFT 10
  211 +#define FLEXSPI_FLSHXCR0_SZ_MASK (0x3FFFFF << FLEXSPI_FLSHXCR0_SZ_SHIFT)
  212 +
  213 +#define FLEXSPI_FLSHXCR1_CSINTR_SHIFT 16
  214 +#define FLEXSPI_FLSHXCR1_CSINTR_MASK (0xFFFF << FLEXSPI_FLSHXCR1_CSINTR_SHIFT)
  215 +#define FLEXSPI_FLSHXCR1_CAS_SHIFT 11
  216 +#define FLEXSPI_FLSHXCR1_CAS_MASK (0xF << FLEXSPI_FLSHXCR1_CAS_SHIFT)
  217 +#define FLEXSPI_FLSHXCR1_WA_SHIFT 10
  218 +#define FLEXSPI_FLSHXCR1_WA_MASK (1 << FLEXSPI_FLSHXCR1_WA_SHIFT)
  219 +#define FLEXSPI_FLSHXCR1_TCSH_SHIFT 5
  220 +#define FLEXSPI_FLSHXCR1_TCSH_MASK (0x1F << FLEXSPI_FLSHXCR1_TCSH_SHIFT)
  221 +#define FLEXSPI_FLSHXCR1_TCSS_SHIFT 0
  222 +#define FLEXSPI_FLSHXCR1_TCSS_MASK (0x1F << FLEXSPI_FLSHXCR1_TCSS_SHIFT)
  223 +
  224 +#define FLEXSPI_FLSHXCR2_CLRINSP_SHIFT 24
  225 +#define FLEXSPI_FLSHXCR2_CLRINSP_MASK (1 << FLEXSPI_FLSHXCR2_CLRINSP_SHIFT)
  226 +#define FLEXSPI_FLSHXCR2_AWRWAIT_SHIFT 16
  227 +#define FLEXSPI_FLSHXCR2_AWRWAIT_MASK (0xFF << FLEXSPI_FLSHXCR2_AWRWAIT_SHIFT)
  228 +#define FLEXSPI_FLSHXCR2_AWRSEQN_SHIFT 13
  229 +#define FLEXSPI_FLSHXCR2_AWRSEQN_MASK (0x7 << FLEXSPI_FLSHXCR2_AWRSEQN_SHIFT)
  230 +#define FLEXSPI_FLSHXCR2_AWRSEQI_SHIFT 8
  231 +#define FLEXSPI_FLSHXCR2_AWRSEQI_MASK (0xF << FLEXSPI_FLSHXCR2_AWRSEQI_SHIFT)
  232 +#define FLEXSPI_FLSHXCR2_ARDSEQN_SHIFT 5
  233 +#define FLEXSPI_FLSHXCR2_ARDSEQN_MASK (0x7 << FLEXSPI_FLSHXCR2_ARDSEQN_SHIFT)
  234 +#define FLEXSPI_FLSHXCR2_ARDSEQI_SHIFT 0
  235 +#define FLEXSPI_FLSHXCR2_ARDSEQI_MASK (0xF << FLEXSPI_FLSHXCR2_ARDSEQI_SHIFT)
  236 +
  237 +
  238 +#define FLEXSPI_IPCR1_IPAREN_SHIFT 31
  239 +#define FLEXSPI_IPCR1_IPAREN_MASK (1 << FLEXSPI_IPCR1_IPAREN_SHIFT)
  240 +#define FLEXSPI_IPCR1_SEQNUM_SHIFT 24
  241 +#define FLEXSPI_IPCR1_SEQNUM_MASK (0xF << FLEXSPI_IPCR1_SEQNUM_SHIFT)
  242 +#define FLEXSPI_IPCR1_SEQID_SHIFT 16
  243 +#define FLEXSPI_IPCR1_SEQID_MASK (0xF << FLEXSPI_IPCR1_SEQID_SHIFT)
  244 +#define FLEXSPI_IPCR1_IDATSZ_SHIFT 0
  245 +#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFF << FLEXSPI_IPCR1_IDATSZ_SHIFT)
  246 +
  247 +#define FLEXSPI_IPCMD_TRG_SHIFT 0
  248 +#define FLEXSPI_IPCMD_TRG_MASK (1 << FLEXSPI_IPCMD_TRG_SHIFT)
  249 +
  250 +#define FLEXSPI_IPRXFCR_CLR_SHIFT 0
  251 +#define FLEXSPI_IPRXFCR_CLR_MASK (1 << FLEXSPI_IPRXFCR_CLR_SHIFT)
  252 +#define FLEXSPI_IPRXFCR_DMA_EN_SHIFT 1
  253 +#define FLEXSPI_IPRXFCR_DMA_EN_MASK (1 << FLEXSPI_IPRXFCR_DMA_EN_SHIFT)
  254 +#define FLEXSPI_IPRXFCR_WMRK_SHIFT 2
  255 +#define FLEXSPI_IPRXFCR_WMRK_MASK (0x1F << FLEXSPI_IPRXFCR_WMRK_SHIFT)
  256 +
  257 +#define FLEXSPI_IPTXFCR_CLR_SHIFT 0
  258 +#define FLEXSPI_IPTXFCR_CLR_MASK (1 << FLEXSPI_IPTXFCR_CLR_SHIFT)
  259 +#define FLEXSPI_IPTXFCR_DMA_EN_SHIFT 1
  260 +#define FLEXSPI_IPTXFCR_DMA_EN_MASK (1 << FLEXSPI_IPTXFCR_DMA_EN_SHIFT)
  261 +#define FLEXSPI_IPTXFCR_WMRK_SHIFT 2
  262 +#define FLEXSPI_IPTXFCR_WMRK_MASK (0x1F << FLEXSPI_IPTXFCR_WMRK_SHIFT)
  263 +
  264 +#define FLEXSPI_STS0_DLPHA_SHIFT 9
  265 +#define FLEXSPI_STS0_DLPHA_MASK (0x1F << FLEXSPI_STS0_DLPHA_SHIFT)
  266 +#define FLEXSPI_STS0_DLPHB_SHIFT 4
  267 +#define FLEXSPI_STS0_DLPHB_MASK (0x1F << FLEXSPI_STS0_DLPHB_SHIFT)
  268 +#define FLEXSPI_STS0_CMD_SRC_SHIFT 2
  269 +#define FLEXSPI_STS0_CMD_SRC_MASK (3 << FLEXSPI_STS0_CMD_SRC_SHIFT)
  270 +#define FLEXSPI_STS0_ARB_BUSY_SHIFT 1
  271 +#define FLEXSPI_STS0_ARB_BUSY_MASK (1 << FLEXSPI_STS0_ARB_BUSY_SHIFT)
  272 +#define FLEXSPI_STS0_SEQ_BUSY_SHIFT 0
  273 +#define FLEXSPI_STS0_SEQ_BUSY_MASK (1 << FLEXSPI_STS0_SEQ_BUSY_SHIFT)
  274 +
  275 +#define FLEXSPI_STS1_IP_ERRCD_SHIFT 24
  276 +#define FLEXSPI_STS1_IP_ERRCD_MASK (0xF << FLEXSPI_STS1_IP_ERRCD_SHIFT)
  277 +#define FLEXSPI_STS1_IP_ERRID_SHIFT 16
  278 +#define FLEXSPI_STS1_IP_ERRID_MASK (0xF << FLEXSPI_STS1_IP_ERRID_SHIFT)
  279 +#define FLEXSPI_STS1_AHB_ERRCD_SHIFT 8
  280 +#define FLEXSPI_STS1_AHB_ERRCD_MASK (0xF << FLEXSPI_STS1_AHB_ERRCD_SHIFT)
  281 +#define FLEXSPI_STS1_AHB_ERRID_SHIFT 0
  282 +#define FLEXSPI_STS1_AHB_ERRID_MASK (0xF << FLEXSPI_STS1_AHB_ERRID_SHIFT)
  283 +
  284 +#define FLEXSPI_AHBSPNST_DATLFT_SHIFT 16
  285 +#define FLEXSPI_AHBSPNST_DATLFT_MASK (0xFFFF << FLEXSPI_AHBSPNST_DATLFT_SHIFT)
  286 +#define FLEXSPI_AHBSPNST_BUFID_SHIFT 1
  287 +#define FLEXSPI_AHBSPNST_BUFID_MASK (7 << FLEXSPI_AHBSPNST_BUFID_SHIFT)
  288 +#define FLEXSPI_AHBSPNST_ACTIVE_SHIFT 0
  289 +#define FLEXSPI_AHBSPNST_ACTIVE_MASK (1 << FLEXSPI_AHBSPNST_ACTIVE_SHIFT)
  290 +
  291 +#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT 16
  292 +#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)
  293 +#define FLEXSPI_IPRXFSTS_FILL_SHIFT 0
  294 +#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFF << FLEXSPI_IPRXFSTS_FILL_SHIFT)
  295 +
  296 +#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT 16
  297 +#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)
  298 +#define FLEXSPI_IPTXFSTS_FILL_SHIFT 0
  299 +#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFF << FLEXSPI_IPTXFSTS_FILL_SHIFT)
  300 +
  301 +/* register map end */
  302 +
  303 +#define OPRND0_SHIFT 0
  304 +#define OPRND0(x) ((x) << OPRND0_SHIFT)
  305 +#define PAD0_SHIFT 8
  306 +#define PAD0(x) ((x) << PAD0_SHIFT)
  307 +#define INSTR0_SHIFT 10
  308 +#define INSTR0(x) ((x) << INSTR0_SHIFT)
  309 +#define OPRND1_SHIFT 16
  310 +#define OPRND1(x) ((x) << OPRND1_SHIFT)
  311 +#define PAD1_SHIFT 24
  312 +#define PAD1(x) ((x) << PAD1_SHIFT)
  313 +#define INSTR1_SHIFT 26
  314 +#define INSTR1(x) ((x) << INSTR1_SHIFT)
  315 +
  316 +#define LUT_STOP 0x00
  317 +#define LUT_CMD 0x01
  318 +#define LUT_ADDR 0x02
  319 +#define LUT_CADDR_SDR 0x03
  320 +#define LUT_MODE 0x04
  321 +#define LUT_MODE2 0x05
  322 +#define LUT_MODE4 0x06
  323 +#define LUT_MODE8 0x07
  324 +#define LUT_WRITE 0x08
  325 +#define LUT_READ 0x09
  326 +#define LUT_LEARN_SDR 0x0A
  327 +#define LUT_DATSZ_SDR 0x0B
  328 +#define LUT_DUMMY 0x0C
  329 +#define LUT_DUMMY_RWDS_SDR 0x0D
  330 +#define LUT_JMP_ON_CS 0x1F
  331 +#define LUT_CMD_DDR 0x21
  332 +#define LUT_ADDR_DDR 0x22
  333 +#define LUT_CADDR_DDR 0x23
  334 +#define LUT_MODE_DDR 0x24
  335 +#define LUT_MODE2_DDR 0x25
  336 +#define LUT_MODE4_DDR 0x26
  337 +#define LUT_MODE8_DDR 0x27
  338 +#define LUT_WRITE_DDR 0x28
  339 +#define LUT_READ_DDR 0x29
  340 +#define LUT_LEARN_DDR 0x2A
  341 +#define LUT_DATSZ_DDR 0x2B
  342 +#define LUT_DUMMY_DDR 0x2C
  343 +#define LUT_DUMMY_RWDS_DDR 0x2D
  344 +
  345 +#define LUT_PAD1 0
  346 +#define LUT_PAD2 1
  347 +#define LUT_PAD4 2
  348 +#define LUT_PAD8 3
  349 +
  350 +#define ADDR8BIT 0x8
  351 +#define ADDR12BIT 0xC
  352 +#define ADDR16BIT 0x10
  353 +#define ADDR24BIT 0x18
  354 +#define ADDR32BIT 0x20
  355 +
  356 +#endif /* _FSL_FSPI_H_ */
scripts/config_whitelist.txt
Diff comments   View file @ e542054
... ... @@ -601,6 +601,7 @@
601 601 CONFIG_FSMC_NAND_BASE
602 602 CONFIG_FSMTDBLK
603 603 CONFIG_FSNOTIFY
  604 +CONFIG_FSPI_QUAD_SUPPORT
604 605 CONFIG_FS_POSIX_ACL
605 606 CONFIG_FTAHBC020S
606 607 CONFIG_FTAHBC020S_BASE
... ... @@ -2527,6 +2528,8 @@
2527 2528 CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET
2528 2529 CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET
2529 2530 CONFIG_SYS_FSL_FMAN_ADDR
  2531 +CONFIG_SYS_FSL_FSPI_AHB
  2532 +CONFIG_SYS_FSL_FSPI_BE
2530 2533 CONFIG_SYS_FSL_GUTS_ADDR
2531 2534 CONFIG_SYS_FSL_I2C
2532 2535 CONFIG_SYS_FSL_I2C2_OFFSET