vexpress64: Add MMU tables

There's no good excuse for running with caches disabled on AArch64, so let's just move the vexpress64 target to enable the MMU and run with caches on. Signed-off-by: Alexander Graf <agraf@suse.de>

vexpress64: Add MMU tables
There's no good excuse for running with caches disabled on AArch64, so let's just move the vexpress64 target to enable the MMU and run with caches on. Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf · Tom Rini
1 parent b30291a3b2
Showing 2 changed files with 24 additions and 3 deletions Side-by-side Diff
board/armltd/vexpress64/vexpress64.c
include/configs/vexpress_aemv8a.h
@@ -14,6 +14,7 @@
 #include <dm/platdata.h>
 #include <dm/platform_data/serial_pl01x.h>
 #include "pcie.h"
+#include <asm/armv8/mmu.h>
  
 DECLARE_GLOBAL_DATA_PTR;
  
@@ -27,6 +28,26 @@
 	.name = "serial_pl01x",
 	.platdata = &serial_platdata,
 };
+
+static struct mm_region vexpress64_mem_map[] = {
+	{
+		.base = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.base = 0x80000000UL,
+		.size = 0xff80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = vexpress64_mem_map;
  
 /* This function gets replaced by platforms supporting PCIe.
  * The replacement function, eg. on Juno, initialises the PCIe bus.
@@ -19,9 +19,9 @@
  
 #define CONFIG_SUPPORT_RAW_INITRD
  
-/* Cache Definitions */
-#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_ICACHE_OFF
+/* MMU Definitions */
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#define CONFIG_SYS_FULL_VA
  
 #define CONFIG_IDENT_STRING		" vexpress_aemv8a"
 #define CONFIG_BOOTP_VCI_STRING		"U-Boot.armv8.vexpress_aemv8a"
...	...	@@ -14,6 +14,7 @@
14	14	#include <dm/platdata.h>
15	15	#include <dm/platform_data/serial_pl01x.h>
16	16	#include "pcie.h"
	17	+#include <asm/armv8/mmu.h>
17	18
18	19	DECLARE_GLOBAL_DATA_PTR;
19	20
...	...	@@ -27,6 +28,26 @@
27	28	.name = "serial_pl01x",
28	29	.platdata = &serial_platdata,
29	30	};
	31	+
	32	+static struct mm_region vexpress64_mem_map[] = {
	33	+ {
	34	+ .base = 0x0UL,
	35	+ .size = 0x80000000UL,
	36	+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	37	+ PTE_BLOCK_NON_SHARE \|
	38	+ PTE_BLOCK_PXN \| PTE_BLOCK_UXN
	39	+ }, {
	40	+ .base = 0x80000000UL,
	41	+ .size = 0xff80000000UL,
	42	+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \|
	43	+ PTE_BLOCK_INNER_SHARE
	44	+ }, {
	45	+ /* List terminator */
	46	+ 0,
	47	+ }
	48	+};
	49	+
	50	+struct mm_region *mem_map = vexpress64_mem_map;
30	51
31	52	/* This function gets replaced by platforms supporting PCIe.
32	53	* The replacement function, eg. on Juno, initialises the PCIe bus.
...	...	@@ -19,9 +19,9 @@
19	19
20	20	#define CONFIG_SUPPORT_RAW_INITRD
21	21
22		-/* Cache Definitions */
23		-#define CONFIG_SYS_DCACHE_OFF
24		-#define CONFIG_SYS_ICACHE_OFF
	22	+/* MMU Definitions */
	23	+#define CONFIG_SYS_CACHELINE_SIZE 64
	24	+#define CONFIG_SYS_FULL_VA
25	25
26	26	#define CONFIG_IDENT_STRING " vexpress_aemv8a"
27	27	#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv8.vexpress_aemv8a"