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Commit e595107ebbdeb3e50351e703cce08eb07f70c614

Authored by Hao Zhang
Committed by Tom Rini
1 parent 0bedbb8135
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: keystone2: move K2HK board files to common KS2 board directory 

This patch moves K2HK board directory to a common Keystone II board
directory. The Board related common functions are moved to a common
keystone board file.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>

Showing 12 changed files with 838 additions and 799 deletions Side-by-side Diff

board/ti/k2hk_evm/Makefile
View file @ e595107
1   -#
2   -# K2HK-EVM: board Makefile
3   -# (C) Copyright 2012-2014
4   -# Texas Instruments Incorporated, <www.ti.com>
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y += board.o
9   -obj-y += ddr3.o
board/ti/k2hk_evm/README
View file @ e595107
1   -U-Boot port for Texas Instruments XTCIEVMK2X
2   -============================================
3   -
4   -Author: Murali Karicheri <m-karicheri2@ti.com>
5   -
6   -This README has information on the u-boot port for XTCIEVMK2X EVM board.
7   -Documentation for this board can be found at
8   - http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx
9   -
10   -The board is based on Texas Instruments Keystone2 family of SoCs : K2H, K2K.
11   -More details on these SoCs are available at company websites
12   - K2K: http://www.ti.com/product/tci6638k2k
13   - K2H: http://www.ti.com/product/tci6638k2h
14   -
15   -Board configuration:
16   -====================
17   -
18   -Some of the peripherals that are configured by u-boot are:-
19   -
20   -1. 2GB DDR3 (can support 8GB SO DIMM as well)
21   -2. 512M NAND (over ti emif16 bus)
22   -3. 6MB MSM SRAM (part of the SoC)
23   -4. two 1GBit Ethernet ports (SoC supports upto 4)
24   -5. two UART ports
25   -6. three i2c interfaces
26   -7. three spi interfaces (only 1 interface supported in driver)
27   -
28   -There are seperate PLLs to drive clocks to Tetris ARM and Peripherals.
29   -To bring up SMP Linux on this board, there is a boot monitor
30   -code that will be installed in MSMC SRAM. There is command available
31   -to install this image from u-boot.
32   -
33   -The port related files can be found at following folders
34   - keystone2 SoC related files: arch/arm/cpu/armv7/keystone/
35   - K2HK evm board files: board/ti/k2hk_evm/
36   -
37   -board configuration file: include/configs/k2hk_evm.h
38   -
39   -Supported boot modes:
40   - - SPI NOR boot
41   - - AEMIF NAND boot
42   -
43   -Supported image formats:-
44   - - u-boot.bin: for loading and running u-boot.bin through Texas instruments
45   - code composure studio (CCS)
46   - - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot
47   - - u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot
48   -
49   -Build instructions:
50   -===================
51   -
52   -To build u-boot.bin
53   - >make k2hk_evm_config
54   - >make u-boot-spi.gph
55   -
56   -To build u-boot-spi.gph
57   - >make k2hk_evm_config
58   - >make u-boot-spi.gph
59   -
60   -To build u-boot-nand.gph
61   - >make k2hk_evm_config
62   - >make u-boot-nand.gph
63   -
64   -Load and Run U-Boot on K2HK EVM using CCS
65   -=========================================
66   -
67   -Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin
68   -on EVM. See instructions at below link for installing CCS on a Windows PC.
69   -http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started#
70   -Installing_Code_Composer_Studio
71   -Use u-boot.bin from the build folder for loading annd running u-boot binary
72   -on EVM. Follow instructions at
73   -http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup
74   -to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode"
75   -and Power ON the EVM. Follow instructions to connect serial port of EVM to
76   -PC and start TeraTerm or Hyper Terminal.
77   -
78   -Start CCS on a Windows machine and Launch Target
79   -configuration as instructed at http://processors.wiki.ti.com/index.php/
80   -MCSDK_UG_Chapter_Exploring#Loading_and_Running_U-Boot_on_EVM_through_CCS.
81   -The instructions provided in the above link uses a script for
82   -loading the u-boot binary on the target EVM. Instead do the following:-
83   -
84   -1. Right click to "Texas Instruments XDS2xx USB Emulator_0/CortexA15_1 core (D
85   - isconnected: Unknown)" at the debug window (This is created once Target
86   - configuration is launched) and select "Connect Target".
87   -2. Once target connect is successful, choose Tools->Load Memory option from the
88   - top level menu. At the Load Memory window, choose the file u-boot.bin
89   - through "Browse" button and click "next >" button. In the next window, enter
90   - Start address as 0xc001000, choose Type-size "32 bits" and click "Finish"
91   - button.
92   -3. Click View -> Registers from the top level menu to view registers window.
93   -4. From Registers, window expand "Core Registers" to view PC. Edit PC value
94   - to be 0xc001000. From the "Run" top level menu, select "Free Run"
95   -5. The U-Boot prompt is shown at the Tera Term/ Hyper terminal console as
96   - below and type any key to stop autoboot as instructed :=
97   -
98   -U-Boot 2014.04-rc1-00201-gc215b5a (Mar 21 2014 - 12:47:59)
99   -
100   -I2C: ready
101   -Detected SO-DIMM [SQR-SD3T-2G1333SED]
102   -DRAM: 1.1 GiB
103   -NAND: 512 MiB
104   -Net: K2HK_EMAC
105   -Warning: K2HK_EMAC using MAC address from net device
106   -, K2HK_EMAC1, K2HK_EMAC2, K2HK_EMAC3
107   -Hit any key to stop autoboot: 0
108   -
109   -SPI NOR Flash programming instructions
110   -======================================
111   -U-Boot image can be flashed to first 512KB of the NOR flash using following
112   -instructions:-
113   -
114   -1. Start CCS and run U-boot as described above.
115   -2. Suspend Target. Select Run -> Suspend from top level menu
116   - CortexA15_1 (Free Running)"
117   -3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000
118   - through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM
119   - using CCS", but using address 0x87000000.
120   -4. Free Run the target as desribed earlier (step 4) to get u-boot prompt
121   -5. At the U-Boot console type following to setup u-boot environment variables.
122   - setenv addr_uboot 0x87000000
123   - setenv filesize <size in hex of u-boot-spi.gph rounded to hex 0x10000>
124   - run burn_uboot_spi
125   - Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
126   - to "SPI Little Endian Boot mode" as per instruction at
127   - http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup.
128   -6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash.
129   -
130   -AEMIF NAND Flash programming instructions
131   -======================================
132   -U-Boot image can be flashed to first 1024KB of the NAND flash using following
133   -instructions:-
134   -
135   -1. Start CCS and run U-boot as described above.
136   -2. Suspend Target. Select Run -> Suspend from top level menu
137   - CortexA15_1 (Free Running)"
138   -3. Load u-boot-nand.gph binary from build folder on to DDR address 0x87000000
139   - through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM
140   - using CCS", but using address 0x87000000.
141   -4. Free Run the target as desribed earlier (step 4) to get u-boot prompt
142   -5. At the U-Boot console type following to setup u-boot environment variables.
143   - setenv filesize <size in hex of u-boot-nand.gph rounded to hex 0x10000>
144   - run burn_uboot_nand
145   - Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
146   - to "ARM NAND Boot mode" as per instruction at
147   - http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup.
148   -6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash.
board/ti/k2hk_evm/board.c
View file @ e595107
1   -/*
2   - * K2HK EVM : Board initialization
3   - *
4   - * (C) Copyright 2012-2014
5   - * Texas Instruments Incorporated, <www.ti.com>
6   - *
7   - * SPDX-License-Identifier: GPL-2.0+
8   - */
9   -
10   -#include <common.h>
11   -#include <exports.h>
12   -#include <fdt_support.h>
13   -#include <libfdt.h>
14   -
15   -#include <asm/arch/ddr3.h>
16   -#include <asm/arch/hardware.h>
17   -#include <asm/arch/clock.h>
18   -#include <asm/io.h>
19   -#include <asm/mach-types.h>
20   -#include <asm/arch/emac_defs.h>
21   -#include <asm/arch/psc_defs.h>
22   -#include <asm/ti-common/ti-aemif.h>
23   -
24   -DECLARE_GLOBAL_DATA_PTR;
25   -
26   -unsigned int external_clk[ext_clk_count] = {
27   - [sys_clk] = 122880000,
28   - [alt_core_clk] = 125000000,
29   - [pa_clk] = 122880000,
30   - [tetris_clk] = 125000000,
31   - [ddr3a_clk] = 100000000,
32   - [ddr3b_clk] = 100000000,
33   - [mcm_clk] = 312500000,
34   - [pcie_clk] = 100000000,
35   - [sgmii_srio_clk] = 156250000,
36   - [xgmii_clk] = 156250000,
37   - [usb_clk] = 100000000,
38   - [rp1_clk] = 123456789 /* TODO: cannot find
39   - what is that */
40   -};
41   -
42   -static struct aemif_config aemif_configs[] = {
43   - { /* CS0 */
44   - .mode = AEMIF_MODE_NAND,
45   - .wr_setup = 0xf,
46   - .wr_strobe = 0x3f,
47   - .wr_hold = 7,
48   - .rd_setup = 0xf,
49   - .rd_strobe = 0x3f,
50   - .rd_hold = 7,
51   - .turn_around = 3,
52   - .width = AEMIF_WIDTH_8,
53   - },
54   -
55   -};
56   -
57   -static struct pll_init_data pll_config[] = {
58   - CORE_PLL_1228,
59   - PASS_PLL_983,
60   - TETRIS_PLL_1200,
61   -};
62   -
63   -int dram_init(void)
64   -{
65   - ddr3_init();
66   -
67   - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
68   - CONFIG_MAX_RAM_BANK_SIZE);
69   - aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
70   - return 0;
71   -}
72   -
73   -#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
74   -struct eth_priv_t eth_priv_cfg[] = {
75   - {
76   - .int_name = "K2HK_EMAC",
77   - .rx_flow = 22,
78   - .phy_addr = 0,
79   - .slave_port = 1,
80   - .sgmii_link_type = SGMII_LINK_MAC_PHY,
81   - },
82   - {
83   - .int_name = "K2HK_EMAC1",
84   - .rx_flow = 23,
85   - .phy_addr = 1,
86   - .slave_port = 2,
87   - .sgmii_link_type = SGMII_LINK_MAC_PHY,
88   - },
89   - {
90   - .int_name = "K2HK_EMAC2",
91   - .rx_flow = 24,
92   - .phy_addr = 2,
93   - .slave_port = 3,
94   - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
95   - },
96   - {
97   - .int_name = "K2HK_EMAC3",
98   - .rx_flow = 25,
99   - .phy_addr = 3,
100   - .slave_port = 4,
101   - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
102   - },
103   -};
104   -
105   -int get_eth_env_param(char *env_name)
106   -{
107   - char *env;
108   - int res = -1;
109   -
110   - env = getenv(env_name);
111   - if (env)
112   - res = simple_strtol(env, NULL, 0);
113   -
114   - return res;
115   -}
116   -
117   -int board_eth_init(bd_t *bis)
118   -{
119   - int j;
120   - int res;
121   - char link_type_name[32];
122   -
123   - for (j = 0; j < (sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t));
124   - j++) {
125   - sprintf(link_type_name, "sgmii%d_link_type", j);
126   - res = get_eth_env_param(link_type_name);
127   - if (res >= 0)
128   - eth_priv_cfg[j].sgmii_link_type = res;
129   -
130   - keystone2_emac_initialize(&eth_priv_cfg[j]);
131   - }
132   -
133   - return 0;
134   -}
135   -#endif
136   -
137   -#if defined(CONFIG_BOARD_EARLY_INIT_F)
138   -int board_early_init_f(void)
139   -{
140   - init_plls(ARRAY_SIZE(pll_config), pll_config);
141   - return 0;
142   -}
143   -#endif
144   -
145   -int board_init(void)
146   -{
147   - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
148   -
149   - return 0;
150   -}
151   -
152   -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
153   -#define K2_DDR3_START_ADDR 0x80000000
154   -void ft_board_setup(void *blob, bd_t *bd)
155   -{
156   - u64 start[2];
157   - u64 size[2];
158   - char name[32], *env, *endp;
159   - int lpae, nodeoffset;
160   - int unitrd_fixup = 0;
161   - u32 ddr3a_size;
162   - int nbanks;
163   -
164   - env = getenv("mem_lpae");
165   - lpae = env && simple_strtol(env, NULL, 0);
166   - env = getenv("uinitrd_fixup");
167   - unitrd_fixup = env && simple_strtol(env, NULL, 0);
168   -
169   - ddr3a_size = 0;
170   - if (lpae) {
171   - env = getenv("ddr3a_size");
172   - if (env)
173   - ddr3a_size = simple_strtol(env, NULL, 10);
174   - if ((ddr3a_size != 8) && (ddr3a_size != 4))
175   - ddr3a_size = 0;
176   - }
177   -
178   - nbanks = 1;
179   - start[0] = bd->bi_dram[0].start;
180   - size[0] = bd->bi_dram[0].size;
181   -
182   - /* adjust memory start address for LPAE */
183   - if (lpae) {
184   - start[0] -= K2_DDR3_START_ADDR;
185   - start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
186   - }
187   -
188   - if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
189   - size[1] = ((u64)ddr3a_size - 2) << 30;
190   - start[1] = 0x880000000;
191   - nbanks++;
192   - }
193   -
194   - /* reserve memory at start of bank */
195   - sprintf(name, "mem_reserve_head");
196   - env = getenv(name);
197   - if (env) {
198   - start[0] += ustrtoul(env, &endp, 0);
199   - size[0] -= ustrtoul(env, &endp, 0);
200   - }
201   -
202   - sprintf(name, "mem_reserve");
203   - env = getenv(name);
204   - if (env)
205   - size[0] -= ustrtoul(env, &endp, 0);
206   -
207   - fdt_fixup_memory_banks(blob, start, size, nbanks);
208   -
209   - /* Fix up the initrd */
210   - if (lpae && unitrd_fixup) {
211   - u64 initrd_start, initrd_end;
212   - u32 *prop1, *prop2;
213   - int err;
214   -
215   - nodeoffset = fdt_path_offset(blob, "/chosen");
216   - if (nodeoffset >= 0) {
217   - prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
218   - "linux,initrd-start", NULL);
219   - prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
220   - "linux,initrd-end", NULL);
221   - if (prop1 && prop2) {
222   - initrd_start = __be32_to_cpu(*prop1);
223   - initrd_start -= K2_DDR3_START_ADDR;
224   - initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
225   - initrd_start = __cpu_to_be64(initrd_start);
226   - initrd_end = __be32_to_cpu(*prop2);
227   - initrd_end -= K2_DDR3_START_ADDR;
228   - initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
229   - initrd_end = __cpu_to_be64(initrd_end);
230   -
231   - err = fdt_delprop(blob, nodeoffset,
232   - "linux,initrd-start");
233   - if (err < 0)
234   - puts("error deleting initrd-start\n");
235   -
236   - err = fdt_delprop(blob, nodeoffset,
237   - "linux,initrd-end");
238   - if (err < 0)
239   - puts("error deleting initrd-end\n");
240   -
241   - err = fdt_setprop(blob, nodeoffset,
242   - "linux,initrd-start",
243   - &initrd_start,
244   - sizeof(initrd_start));
245   - if (err < 0)
246   - puts("error adding initrd-start\n");
247   -
248   - err = fdt_setprop(blob, nodeoffset,
249   - "linux,initrd-end",
250   - &initrd_end,
251   - sizeof(initrd_end));
252   - if (err < 0)
253   - puts("error adding linux,initrd-end\n");
254   - }
255   - }
256   - }
257   -}
258   -
259   -void ft_board_setup_ex(void *blob, bd_t *bd)
260   -{
261   - int lpae;
262   - char *env;
263   - u64 *reserve_start, size;
264   -
265   - env = getenv("mem_lpae");
266   - lpae = env && simple_strtol(env, NULL, 0);
267   -
268   - if (lpae) {
269   - /*
270   - * the initrd and other reserved memory areas are
271   - * embedded in in the DTB itslef. fix up these addresses
272   - * to 36 bit format
273   - */
274   - reserve_start = (u64 *)((char *)blob +
275   - fdt_off_mem_rsvmap(blob));
276   - while (1) {
277   - *reserve_start = __cpu_to_be64(*reserve_start);
278   - size = __cpu_to_be64(*(reserve_start + 1));
279   - if (size) {
280   - *reserve_start -= K2_DDR3_START_ADDR;
281   - *reserve_start +=
282   - CONFIG_SYS_LPAE_SDRAM_BASE;
283   - *reserve_start =
284   - __cpu_to_be64(*reserve_start);
285   - } else {
286   - break;
287   - }
288   - reserve_start += 2;
289   - }
290   - }
291   -}
292   -#endif
board/ti/k2hk_evm/ddr3.c
View file @ e595107
1   -/*
2   - * Keystone2: DDR3 initialization
3   - *
4   - * (C) Copyright 2012-2014
5   - * Texas Instruments Incorporated, <www.ti.com>
6   - *
7   - * SPDX-License-Identifier: GPL-2.0+
8   - */
9   -
10   -#include <common.h>
11   -#include <asm/arch/ddr3.h>
12   -#include <asm/arch/hardware.h>
13   -#include <asm/io.h>
14   -#include <i2c.h>
15   -
16   -/************************* *****************************/
17   -static struct ddr3_phy_config ddr3phy_1600_64A = {
18   - .pllcr = 0x0001C000ul,
19   - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
20   - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
21   - .ptr0 = 0x42C21590ul,
22   - .ptr1 = 0xD05612C0ul,
23   - .ptr2 = 0, /* not set in gel */
24   - .ptr3 = 0x0D861A80ul,
25   - .ptr4 = 0x0C827100ul,
26   - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
27   - .dcr_val = ((1 << 10) | (1 << 27)),
28   - .dtpr0 = 0xA19DBB66ul,
29   - .dtpr1 = 0x12868300ul,
30   - .dtpr2 = 0x50035200ul,
31   - .mr0 = 0x00001C70ul,
32   - .mr1 = 0x00000006ul,
33   - .mr2 = 0x00000018ul,
34   - .dtcr = 0x730035C7ul,
35   - .pgcr2 = 0x00F07A12ul,
36   - .zq0cr1 = 0x0000005Dul,
37   - .zq1cr1 = 0x0000005Bul,
38   - .zq2cr1 = 0x0000005Bul,
39   - .pir_v1 = 0x00000033ul,
40   - .pir_v2 = 0x0000FF81ul,
41   -};
42   -
43   -static struct ddr3_emif_config ddr3_1600_64 = {
44   - .sdcfg = 0x6200CE6aul,
45   - .sdtim1 = 0x16709C55ul,
46   - .sdtim2 = 0x00001D4Aul,
47   - .sdtim3 = 0x435DFF54ul,
48   - .sdtim4 = 0x553F0CFFul,
49   - .zqcfg = 0xF0073200ul,
50   - .sdrfc = 0x00001869ul,
51   -};
52   -
53   -static struct ddr3_phy_config ddr3phy_1600_32 = {
54   - .pllcr = 0x0001C000ul,
55   - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
56   - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
57   - .ptr0 = 0x42C21590ul,
58   - .ptr1 = 0xD05612C0ul,
59   - .ptr2 = 0, /* not set in gel */
60   - .ptr3 = 0x0D861A80ul,
61   - .ptr4 = 0x0C827100ul,
62   - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
63   - .dcr_val = ((1 << 10) | (1 << 27)),
64   - .dtpr0 = 0xA19DBB66ul,
65   - .dtpr1 = 0x12868300ul,
66   - .dtpr2 = 0x50035200ul,
67   - .mr0 = 0x00001C70ul,
68   - .mr1 = 0x00000006ul,
69   - .mr2 = 0x00000018ul,
70   - .dtcr = 0x730035C7ul,
71   - .pgcr2 = 0x00F07A12ul,
72   - .zq0cr1 = 0x0000005Dul,
73   - .zq1cr1 = 0x0000005Bul,
74   - .zq2cr1 = 0x0000005Bul,
75   - .pir_v1 = 0x00000033ul,
76   - .pir_v2 = 0x0000FF81ul,
77   -};
78   -
79   -static struct ddr3_emif_config ddr3_1600_32 = {
80   - .sdcfg = 0x6200DE6aul,
81   - .sdtim1 = 0x16709C55ul,
82   - .sdtim2 = 0x00001D4Aul,
83   - .sdtim3 = 0x435DFF54ul,
84   - .sdtim4 = 0x553F0CFFul,
85   - .zqcfg = 0x70073200ul,
86   - .sdrfc = 0x00001869ul,
87   -};
88   -
89   -/************************* *****************************/
90   -static struct ddr3_phy_config ddr3phy_1333_64A = {
91   - .pllcr = 0x0005C000ul,
92   - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
93   - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
94   - .ptr0 = 0x42C21590ul,
95   - .ptr1 = 0xD05612C0ul,
96   - .ptr2 = 0, /* not set in gel */
97   - .ptr3 = 0x0B4515C2ul,
98   - .ptr4 = 0x0A6E08B4ul,
99   - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
100   - NOSRA_MASK | UDIMM_MASK),
101   - .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)),
102   - .dtpr0 = 0x8558AA55ul,
103   - .dtpr1 = 0x12857280ul,
104   - .dtpr2 = 0x5002C200ul,
105   - .mr0 = 0x00001A60ul,
106   - .mr1 = 0x00000006ul,
107   - .mr2 = 0x00000010ul,
108   - .dtcr = 0x710035C7ul,
109   - .pgcr2 = 0x00F065B8ul,
110   - .zq0cr1 = 0x0000005Dul,
111   - .zq1cr1 = 0x0000005Bul,
112   - .zq2cr1 = 0x0000005Bul,
113   - .pir_v1 = 0x00000033ul,
114   - .pir_v2 = 0x0000FF81ul,
115   -};
116   -
117   -static struct ddr3_emif_config ddr3_1333_64 = {
118   - .sdcfg = 0x62008C62ul,
119   - .sdtim1 = 0x125C8044ul,
120   - .sdtim2 = 0x00001D29ul,
121   - .sdtim3 = 0x32CDFF43ul,
122   - .sdtim4 = 0x543F0ADFul,
123   - .zqcfg = 0xF0073200ul,
124   - .sdrfc = 0x00001457ul,
125   -};
126   -
127   -static struct ddr3_phy_config ddr3phy_1333_32 = {
128   - .pllcr = 0x0005C000ul,
129   - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
130   - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
131   - .ptr0 = 0x42C21590ul,
132   - .ptr1 = 0xD05612C0ul,
133   - .ptr2 = 0, /* not set in gel */
134   - .ptr3 = 0x0B4515C2ul,
135   - .ptr4 = 0x0A6E08B4ul,
136   - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
137   - NOSRA_MASK | UDIMM_MASK),
138   - .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)),
139   - .dtpr0 = 0x8558AA55ul,
140   - .dtpr1 = 0x12857280ul,
141   - .dtpr2 = 0x5002C200ul,
142   - .mr0 = 0x00001A60ul,
143   - .mr1 = 0x00000006ul,
144   - .mr2 = 0x00000010ul,
145   - .dtcr = 0x710035C7ul,
146   - .pgcr2 = 0x00F065B8ul,
147   - .zq0cr1 = 0x0000005Dul,
148   - .zq1cr1 = 0x0000005Bul,
149   - .zq2cr1 = 0x0000005Bul,
150   - .pir_v1 = 0x00000033ul,
151   - .pir_v2 = 0x0000FF81ul,
152   -};
153   -
154   -static struct ddr3_emif_config ddr3_1333_32 = {
155   - .sdcfg = 0x62009C62ul,
156   - .sdtim1 = 0x125C8044ul,
157   - .sdtim2 = 0x00001D29ul,
158   - .sdtim3 = 0x32CDFF43ul,
159   - .sdtim4 = 0x543F0ADFul,
160   - .zqcfg = 0xf0073200ul,
161   - .sdrfc = 0x00001457ul,
162   -};
163   -
164   -/************************* *****************************/
165   -static struct ddr3_phy_config ddr3phy_1333_64 = {
166   - .pllcr = 0x0005C000ul,
167   - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
168   - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
169   - .ptr0 = 0x42C21590ul,
170   - .ptr1 = 0xD05612C0ul,
171   - .ptr2 = 0, /* not set in gel */
172   - .ptr3 = 0x0B4515C2ul,
173   - .ptr4 = 0x0A6E08B4ul,
174   - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
175   - .dcr_val = ((1 << 10) | (1 << 27)),
176   - .dtpr0 = 0x8558AA55ul,
177   - .dtpr1 = 0x12857280ul,
178   - .dtpr2 = 0x5002C200ul,
179   - .mr0 = 0x00001A60ul,
180   - .mr1 = 0x00000006ul,
181   - .mr2 = 0x00000010ul,
182   - .dtcr = 0x710035C7ul,
183   - .pgcr2 = 0x00F065B8ul,
184   - .zq0cr1 = 0x0000005Dul,
185   - .zq1cr1 = 0x0000005Bul,
186   - .zq2cr1 = 0x0000005Bul,
187   - .pir_v1 = 0x00000033ul,
188   - .pir_v2 = 0x0000FF81ul,
189   -};
190   -/******************************************************/
191   -
192   -/* DDR PHY Configs Updated for PG 2.0
193   - * zq0,1,2cr1 are updated for PG 2.0 specific configs *_pg2 */
194   -static struct ddr3_phy_config ddr3phy_1600_64A_pg2 = {
195   - .pllcr = 0x0001C000ul,
196   - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
197   - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
198   - .ptr0 = 0x42C21590ul,
199   - .ptr1 = 0xD05612C0ul,
200   - .ptr2 = 0, /* not set in gel */
201   - .ptr3 = 0x0D861A80ul,
202   - .ptr4 = 0x0C827100ul,
203   - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
204   - .dcr_val = ((1 << 10)),
205   - .dtpr0 = 0xA19DBB66ul,
206   - .dtpr1 = 0x32868300ul,
207   - .dtpr2 = 0x50035200ul,
208   - .mr0 = 0x00001C70ul,
209   - .mr1 = 0x00000006ul,
210   - .mr2 = 0x00000018ul,
211   - .dtcr = 0x730035C7ul,
212   - .pgcr2 = 0x00F07A12ul,
213   - .zq0cr1 = 0x0001005Dul,
214   - .zq1cr1 = 0x0001005Bul,
215   - .zq2cr1 = 0x0001005Bul,
216   - .pir_v1 = 0x00000033ul,
217   - .pir_v2 = 0x0000FF81ul,
218   -};
219   -
220   -static struct ddr3_phy_config ddr3phy_1333_64A_pg2 = {
221   - .pllcr = 0x0005C000ul,
222   - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
223   - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
224   - .ptr0 = 0x42C21590ul,
225   - .ptr1 = 0xD05612C0ul,
226   - .ptr2 = 0, /* not set in gel */
227   - .ptr3 = 0x0B4515C2ul,
228   - .ptr4 = 0x0A6E08B4ul,
229   - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
230   - .dcr_val = ((1 << 10)),
231   - .dtpr0 = 0x8558AA55ul,
232   - .dtpr1 = 0x32857280ul,
233   - .dtpr2 = 0x5002C200ul,
234   - .mr0 = 0x00001A60ul,
235   - .mr1 = 0x00000006ul,
236   - .mr2 = 0x00000010ul,
237   - .dtcr = 0x710035C7ul,
238   - .pgcr2 = 0x00F065B8ul,
239   - .zq0cr1 = 0x0001005Dul,
240   - .zq1cr1 = 0x0001005Bul,
241   - .zq2cr1 = 0x0001005Bul,
242   - .pir_v1 = 0x00000033ul,
243   - .pir_v2 = 0x0000FF81ul,
244   -};
245   -
246   -int get_dimm_params(char *dimm_name)
247   -{
248   - u8 spd_params[256];
249   - int ret;
250   - int old_bus;
251   -
252   - i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
253   -
254   - old_bus = i2c_get_bus_num();
255   - i2c_set_bus_num(1);
256   -
257   - ret = i2c_read(0x53, 0, 1, spd_params, 256);
258   -
259   - i2c_set_bus_num(old_bus);
260   -
261   - dimm_name[0] = '\0';
262   -
263   - if (ret) {
264   - puts("Cannot read DIMM params\n");
265   - return 1;
266   - }
267   -
268   - /*
269   - * We need to convert spd data to dimm parameters
270   - * and to DDR3 EMIF and PHY regirsters values.
271   - * For now we just return DIMM type string value.
272   - * Caller may use this value to choose appropriate
273   - * a pre-set DDR3 configuration
274   - */
275   -
276   - strncpy(dimm_name, (char *)&spd_params[0x80], 18);
277   - dimm_name[18] = '\0';
278   -
279   - return 0;
280   -}
281   -
282   -struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
283   -struct pll_init_data ddr3b_333 = DDR3_PLL_333(B);
284   -struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
285   -struct pll_init_data ddr3b_400 = DDR3_PLL_400(B);
286   -
287   -void ddr3_init(void)
288   -{
289   - char dimm_name[32];
290   -
291   - get_dimm_params(dimm_name);
292   -
293   - printf("Detected SO-DIMM [%s]\n", dimm_name);
294   -
295   - if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
296   - init_pll(&ddr3a_400);
297   - if (cpu_revision() > 0) {
298   - if (cpu_revision() > 1) {
299   - /* PG 2.0 */
300   - /* Reset DDR3A PHY after PLL enabled */
301   - ddr3_reset_ddrphy();
302   - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
303   - &ddr3phy_1600_64A_pg2);
304   - } else {
305   - /* PG 1.1 */
306   - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
307   - &ddr3phy_1600_64A);
308   - }
309   -
310   - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
311   - &ddr3_1600_64);
312   - printf("DRAM: Capacity 8 GiB (includes reported below)\n");
313   - } else {
314   - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_32);
315   - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
316   - &ddr3_1600_32);
317   - printf("DRAM: Capacity 4 GiB (includes reported below)\n");
318   - }
319   - } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
320   - init_pll(&ddr3a_333);
321   - if (cpu_revision() > 0) {
322   - if (cpu_revision() > 1) {
323   - /* PG 2.0 */
324   - /* Reset DDR3A PHY after PLL enabled */
325   - ddr3_reset_ddrphy();
326   - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
327   - &ddr3phy_1333_64A_pg2);
328   - } else {
329   - /* PG 1.1 */
330   - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
331   - &ddr3phy_1333_64A);
332   - }
333   - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
334   - &ddr3_1333_64);
335   - } else {
336   - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_32);
337   - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
338   - &ddr3_1333_32);
339   - }
340   - } else {
341   - printf("Unknown SO-DIMM. Cannot configure DDR3\n");
342   - while (1)
343   - ;
344   - }
345   -
346   - init_pll(&ddr3b_333);
347   - ddr3_init_ddrphy(KS2_DDR3B_DDRPHYC, &ddr3phy_1333_64);
348   - ddr3_init_ddremif(KS2_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64);
349   -}
board/ti/ks2_evm/Makefile
Diff comments   View file @ e595107
  1 +#
  2 +# KS2-EVM: board Makefile
  3 +# (C) Copyright 2012-2014
  4 +# Texas Instruments Incorporated, <www.ti.com>
  5 +# SPDX-License-Identifier: GPL-2.0+
  6 +#
  7 +
  8 +obj-y += board.o
  9 +obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
  10 +obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
board/ti/ks2_evm/README_K2HK
Diff comments   View file @ e595107
  1 +U-Boot port for Texas Instruments XTCIEVMK2X
  2 +============================================
  3 +
  4 +Author: Murali Karicheri <m-karicheri2@ti.com>
  5 +
  6 +This README has information on the u-boot port for XTCIEVMK2X EVM board.
  7 +Documentation for this board can be found at
  8 + http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx
  9 +
  10 +The board is based on Texas Instruments Keystone2 family of SoCs : K2H, K2K.
  11 +More details on these SoCs are available at company websites
  12 + K2K: http://www.ti.com/product/tci6638k2k
  13 + K2H: http://www.ti.com/product/tci6638k2h
  14 +
  15 +Board configuration:
  16 +====================
  17 +
  18 +Some of the peripherals that are configured by u-boot are:-
  19 +
  20 +1. 2GB DDR3 (can support 8GB SO DIMM as well)
  21 +2. 512M NAND (over ti emif16 bus)
  22 +3. 6MB MSM SRAM (part of the SoC)
  23 +4. two 1GBit Ethernet ports (SoC supports upto 4)
  24 +5. two UART ports
  25 +6. three i2c interfaces
  26 +7. three spi interfaces (only 1 interface supported in driver)
  27 +
  28 +There are seperate PLLs to drive clocks to Tetris ARM and Peripherals.
  29 +To bring up SMP Linux on this board, there is a boot monitor
  30 +code that will be installed in MSMC SRAM. There is command available
  31 +to install this image from u-boot.
  32 +
  33 +The port related files can be found at following folders
  34 + keystone2 SoC related files: arch/arm/cpu/armv7/keystone/
  35 + K2HK evm board files: board/ti/k2hk_evm/
  36 +
  37 +board configuration file: include/configs/k2hk_evm.h
  38 +
  39 +Supported boot modes:
  40 + - SPI NOR boot
  41 + - AEMIF NAND boot
  42 +
  43 +Supported image formats:-
  44 + - u-boot.bin: for loading and running u-boot.bin through Texas instruments
  45 + code composure studio (CCS)
  46 + - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot
  47 + - u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot
  48 +
  49 +Build instructions:
  50 +===================
  51 +
  52 +To build u-boot.bin
  53 + >make k2hk_evm_config
  54 + >make u-boot-spi.gph
  55 +
  56 +To build u-boot-spi.gph
  57 + >make k2hk_evm_config
  58 + >make u-boot-spi.gph
  59 +
  60 +To build u-boot-nand.gph
  61 + >make k2hk_evm_config
  62 + >make u-boot-nand.gph
  63 +
  64 +Load and Run U-Boot on K2HK EVM using CCS
  65 +=========================================
  66 +
  67 +Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin
  68 +on EVM. See instructions at below link for installing CCS on a Windows PC.
  69 +http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started#
  70 +Installing_Code_Composer_Studio
  71 +Use u-boot.bin from the build folder for loading annd running u-boot binary
  72 +on EVM. Follow instructions at
  73 +http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup
  74 +to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode"
  75 +and Power ON the EVM. Follow instructions to connect serial port of EVM to
  76 +PC and start TeraTerm or Hyper Terminal.
  77 +
  78 +Start CCS on a Windows machine and Launch Target
  79 +configuration as instructed at http://processors.wiki.ti.com/index.php/
  80 +MCSDK_UG_Chapter_Exploring#Loading_and_Running_U-Boot_on_EVM_through_CCS.
  81 +The instructions provided in the above link uses a script for
  82 +loading the u-boot binary on the target EVM. Instead do the following:-
  83 +
  84 +1. Right click to "Texas Instruments XDS2xx USB Emulator_0/CortexA15_1 core (D
  85 + isconnected: Unknown)" at the debug window (This is created once Target
  86 + configuration is launched) and select "Connect Target".
  87 +2. Once target connect is successful, choose Tools->Load Memory option from the
  88 + top level menu. At the Load Memory window, choose the file u-boot.bin
  89 + through "Browse" button and click "next >" button. In the next window, enter
  90 + Start address as 0xc001000, choose Type-size "32 bits" and click "Finish"
  91 + button.
  92 +3. Click View -> Registers from the top level menu to view registers window.
  93 +4. From Registers, window expand "Core Registers" to view PC. Edit PC value
  94 + to be 0xc001000. From the "Run" top level menu, select "Free Run"
  95 +5. The U-Boot prompt is shown at the Tera Term/ Hyper terminal console as
  96 + below and type any key to stop autoboot as instructed :=
  97 +
  98 +U-Boot 2014.04-rc1-00201-gc215b5a (Mar 21 2014 - 12:47:59)
  99 +
  100 +I2C: ready
  101 +Detected SO-DIMM [SQR-SD3T-2G1333SED]
  102 +DRAM: 1.1 GiB
  103 +NAND: 512 MiB
  104 +Net: K2HK_EMAC
  105 +Warning: K2HK_EMAC using MAC address from net device
  106 +, K2HK_EMAC1, K2HK_EMAC2, K2HK_EMAC3
  107 +Hit any key to stop autoboot: 0
  108 +
  109 +SPI NOR Flash programming instructions
  110 +======================================
  111 +U-Boot image can be flashed to first 512KB of the NOR flash using following
  112 +instructions:-
  113 +
  114 +1. Start CCS and run U-boot as described above.
  115 +2. Suspend Target. Select Run -> Suspend from top level menu
  116 + CortexA15_1 (Free Running)"
  117 +3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000
  118 + through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM
  119 + using CCS", but using address 0x87000000.
  120 +4. Free Run the target as desribed earlier (step 4) to get u-boot prompt
  121 +5. At the U-Boot console type following to setup u-boot environment variables.
  122 + setenv addr_uboot 0x87000000
  123 + setenv filesize <size in hex of u-boot-spi.gph rounded to hex 0x10000>
  124 + run burn_uboot_spi
  125 + Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
  126 + to "SPI Little Endian Boot mode" as per instruction at
  127 + http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup.
  128 +6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash.
  129 +
  130 +AEMIF NAND Flash programming instructions
  131 +======================================
  132 +U-Boot image can be flashed to first 1024KB of the NAND flash using following
  133 +instructions:-
  134 +
  135 +1. Start CCS and run U-boot as described above.
  136 +2. Suspend Target. Select Run -> Suspend from top level menu
  137 + CortexA15_1 (Free Running)"
  138 +3. Load u-boot-nand.gph binary from build folder on to DDR address 0x87000000
  139 + through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM
  140 + using CCS", but using address 0x87000000.
  141 +4. Free Run the target as desribed earlier (step 4) to get u-boot prompt
  142 +5. At the U-Boot console type following to setup u-boot environment variables.
  143 + setenv filesize <size in hex of u-boot-nand.gph rounded to hex 0x10000>
  144 + run burn_uboot_nand
  145 + Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
  146 + to "ARM NAND Boot mode" as per instruction at
  147 + http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup.
  148 +6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash.
board/ti/ks2_evm/board.c
Diff comments   View file @ e595107
  1 +/*
  2 + * Keystone : Board initialization
  3 + *
  4 + * (C) Copyright 2014
  5 + * Texas Instruments Incorporated, <www.ti.com>
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 + */
  9 +
  10 +#include "board.h"
  11 +#include <common.h>
  12 +#include <exports.h>
  13 +#include <fdt_support.h>
  14 +#include <asm/arch/ddr3.h>
  15 +#include <asm/arch/emac_defs.h>
  16 +#include <asm/ti-common/ti-aemif.h>
  17 +
  18 +DECLARE_GLOBAL_DATA_PTR;
  19 +
  20 +static struct aemif_config aemif_configs[] = {
  21 + { /* CS0 */
  22 + .mode = AEMIF_MODE_NAND,
  23 + .wr_setup = 0xf,
  24 + .wr_strobe = 0x3f,
  25 + .wr_hold = 7,
  26 + .rd_setup = 0xf,
  27 + .rd_strobe = 0x3f,
  28 + .rd_hold = 7,
  29 + .turn_around = 3,
  30 + .width = AEMIF_WIDTH_8,
  31 + },
  32 +};
  33 +
  34 +int dram_init(void)
  35 +{
  36 + ddr3_init();
  37 +
  38 + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
  39 + CONFIG_MAX_RAM_BANK_SIZE);
  40 + aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
  41 + return 0;
  42 +}
  43 +
  44 +int board_init(void)
  45 +{
  46 + gd->bd->bi_boot_params = CONFIG_LINUX_BOOT_PARAM_ADDR;
  47 +
  48 + return 0;
  49 +}
  50 +
  51 +#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
  52 +int get_eth_env_param(char *env_name)
  53 +{
  54 + char *env;
  55 + int res = -1;
  56 +
  57 + env = getenv(env_name);
  58 + if (env)
  59 + res = simple_strtol(env, NULL, 0);
  60 +
  61 + return res;
  62 +}
  63 +
  64 +int board_eth_init(bd_t *bis)
  65 +{
  66 + int j;
  67 + int res;
  68 + int port_num;
  69 + char link_type_name[32];
  70 +
  71 + port_num = get_num_eth_ports();
  72 +
  73 + for (j = 0; j < port_num; j++) {
  74 + sprintf(link_type_name, "sgmii%d_link_type", j);
  75 + res = get_eth_env_param(link_type_name);
  76 + if (res >= 0)
  77 + eth_priv_cfg[j].sgmii_link_type = res;
  78 +
  79 + keystone2_emac_initialize(&eth_priv_cfg[j]);
  80 + }
  81 +
  82 + return 0;
  83 +}
  84 +#endif
  85 +
  86 +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  87 +void ft_board_setup(void *blob, bd_t *bd)
  88 +{
  89 + int lpae;
  90 + char *env;
  91 + char *endp;
  92 + int nbanks;
  93 + u64 size[2];
  94 + u64 start[2];
  95 + char name[32];
  96 + int nodeoffset;
  97 + u32 ddr3a_size;
  98 + int unitrd_fixup = 0;
  99 +
  100 + env = getenv("mem_lpae");
  101 + lpae = env && simple_strtol(env, NULL, 0);
  102 + env = getenv("uinitrd_fixup");
  103 + unitrd_fixup = env && simple_strtol(env, NULL, 0);
  104 +
  105 + ddr3a_size = 0;
  106 + if (lpae) {
  107 + env = getenv("ddr3a_size");
  108 + if (env)
  109 + ddr3a_size = simple_strtol(env, NULL, 10);
  110 + if ((ddr3a_size != 8) && (ddr3a_size != 4))
  111 + ddr3a_size = 0;
  112 + }
  113 +
  114 + nbanks = 1;
  115 + start[0] = bd->bi_dram[0].start;
  116 + size[0] = bd->bi_dram[0].size;
  117 +
  118 + /* adjust memory start address for LPAE */
  119 + if (lpae) {
  120 + start[0] -= CONFIG_SYS_SDRAM_BASE;
  121 + start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
  122 + }
  123 +
  124 + if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
  125 + size[1] = ((u64)ddr3a_size - 2) << 30;
  126 + start[1] = 0x880000000;
  127 + nbanks++;
  128 + }
  129 +
  130 + /* reserve memory at start of bank */
  131 + sprintf(name, "mem_reserve_head");
  132 + env = getenv(name);
  133 + if (env) {
  134 + start[0] += ustrtoul(env, &endp, 0);
  135 + size[0] -= ustrtoul(env, &endp, 0);
  136 + }
  137 +
  138 + sprintf(name, "mem_reserve");
  139 + env = getenv(name);
  140 + if (env)
  141 + size[0] -= ustrtoul(env, &endp, 0);
  142 +
  143 + fdt_fixup_memory_banks(blob, start, size, nbanks);
  144 +
  145 + /* Fix up the initrd */
  146 + if (lpae && unitrd_fixup) {
  147 + int err;
  148 + u32 *prop1, *prop2;
  149 + u64 initrd_start, initrd_end;
  150 +
  151 + nodeoffset = fdt_path_offset(blob, "/chosen");
  152 + if (nodeoffset >= 0) {
  153 + prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
  154 + "linux,initrd-start", NULL);
  155 + prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
  156 + "linux,initrd-end", NULL);
  157 + if (prop1 && prop2) {
  158 + initrd_start = __be32_to_cpu(*prop1);
  159 + initrd_start -= CONFIG_SYS_SDRAM_BASE;
  160 + initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
  161 + initrd_start = __cpu_to_be64(initrd_start);
  162 + initrd_end = __be32_to_cpu(*prop2);
  163 + initrd_end -= CONFIG_SYS_SDRAM_BASE;
  164 + initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
  165 + initrd_end = __cpu_to_be64(initrd_end);
  166 +
  167 + err = fdt_delprop(blob, nodeoffset,
  168 + "linux,initrd-start");
  169 + if (err < 0)
  170 + puts("error deleting initrd-start\n");
  171 +
  172 + err = fdt_delprop(blob, nodeoffset,
  173 + "linux,initrd-end");
  174 + if (err < 0)
  175 + puts("error deleting initrd-end\n");
  176 +
  177 + err = fdt_setprop(blob, nodeoffset,
  178 + "linux,initrd-start",
  179 + &initrd_start,
  180 + sizeof(initrd_start));
  181 + if (err < 0)
  182 + puts("error adding initrd-start\n");
  183 +
  184 + err = fdt_setprop(blob, nodeoffset,
  185 + "linux,initrd-end",
  186 + &initrd_end,
  187 + sizeof(initrd_end));
  188 + if (err < 0)
  189 + puts("error adding linux,initrd-end\n");
  190 + }
  191 + }
  192 + }
  193 +}
  194 +
  195 +void ft_board_setup_ex(void *blob, bd_t *bd)
  196 +{
  197 + int lpae;
  198 + u64 size;
  199 + char *env;
  200 + u64 *reserve_start;
  201 +
  202 + env = getenv("mem_lpae");
  203 + lpae = env && simple_strtol(env, NULL, 0);
  204 +
  205 + if (lpae) {
  206 + /*
  207 + * the initrd and other reserved memory areas are
  208 + * embedded in in the DTB itslef. fix up these addresses
  209 + * to 36 bit format
  210 + */
  211 + reserve_start = (u64 *)((char *)blob +
  212 + fdt_off_mem_rsvmap(blob));
  213 + while (1) {
  214 + *reserve_start = __cpu_to_be64(*reserve_start);
  215 + size = __cpu_to_be64(*(reserve_start + 1));
  216 + if (size) {
  217 + *reserve_start -= CONFIG_SYS_SDRAM_BASE;
  218 + *reserve_start +=
  219 + CONFIG_SYS_LPAE_SDRAM_BASE;
  220 + *reserve_start =
  221 + __cpu_to_be64(*reserve_start);
  222 + } else {
  223 + break;
  224 + }
  225 + reserve_start += 2;
  226 + }
  227 + }
  228 +}
  229 +#endif
board/ti/ks2_evm/board.h
Diff comments   View file @ e595107
  1 +/*
  2 + * K2HK EVM : Board common header
  3 + *
  4 + * (C) Copyright 2014
  5 + * Texas Instruments Incorporated, <www.ti.com>
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 + */
  9 +
  10 +#ifndef _KS2_BOARD
  11 +#define _KS2_BOARD
  12 +
  13 +#include <asm/arch/emac_defs.h>
  14 +
  15 +extern struct eth_priv_t eth_priv_cfg[];
  16 +
  17 +int get_num_eth_ports(void);
  18 +
  19 +#endif
board/ti/ks2_evm/board_k2hk.c
Diff comments   View file @ e595107
  1 +/*
  2 + * K2HK EVM : Board initialization
  3 + *
  4 + * (C) Copyright 2012-2014
  5 + * Texas Instruments Incorporated, <www.ti.com>
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 + */
  9 +
  10 +#include <common.h>
  11 +#include <asm/arch/hardware.h>
  12 +#include <asm/arch/emac_defs.h>
  13 +
  14 +DECLARE_GLOBAL_DATA_PTR;
  15 +
  16 +unsigned int external_clk[ext_clk_count] = {
  17 + [sys_clk] = 122880000,
  18 + [alt_core_clk] = 125000000,
  19 + [pa_clk] = 122880000,
  20 + [tetris_clk] = 125000000,
  21 + [ddr3a_clk] = 100000000,
  22 + [ddr3b_clk] = 100000000,
  23 + [mcm_clk] = 312500000,
  24 + [pcie_clk] = 100000000,
  25 + [sgmii_srio_clk] = 156250000,
  26 + [xgmii_clk] = 156250000,
  27 + [usb_clk] = 100000000,
  28 + [rp1_clk] = 123456789
  29 +};
  30 +
  31 +static struct pll_init_data pll_config[] = {
  32 + CORE_PLL_1228,
  33 + PASS_PLL_983,
  34 + TETRIS_PLL_1200,
  35 +};
  36 +
  37 +#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
  38 +struct eth_priv_t eth_priv_cfg[] = {
  39 + {
  40 + .int_name = "K2HK_EMAC",
  41 + .rx_flow = 22,
  42 + .phy_addr = 0,
  43 + .slave_port = 1,
  44 + .sgmii_link_type = SGMII_LINK_MAC_PHY,
  45 + },
  46 + {
  47 + .int_name = "K2HK_EMAC1",
  48 + .rx_flow = 23,
  49 + .phy_addr = 1,
  50 + .slave_port = 2,
  51 + .sgmii_link_type = SGMII_LINK_MAC_PHY,
  52 + },
  53 + {
  54 + .int_name = "K2HK_EMAC2",
  55 + .rx_flow = 24,
  56 + .phy_addr = 2,
  57 + .slave_port = 3,
  58 + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
  59 + },
  60 + {
  61 + .int_name = "K2HK_EMAC3",
  62 + .rx_flow = 25,
  63 + .phy_addr = 3,
  64 + .slave_port = 4,
  65 + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
  66 + },
  67 +};
  68 +
  69 +int get_num_eth_ports(void)
  70 +{
  71 + return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
  72 +}
  73 +#endif
  74 +
  75 +#ifdef CONFIG_BOARD_EARLY_INIT_F
  76 +int board_early_init_f(void)
  77 +{
  78 + init_plls(ARRAY_SIZE(pll_config), pll_config);
  79 + return 0;
  80 +}
  81 +#endif
board/ti/ks2_evm/ddr3_k2hk.c
Diff comments   View file @ e595107
  1 +/*
  2 + * Keystone2: DDR3 initialization
  3 + *
  4 + * (C) Copyright 2012-2014
  5 + * Texas Instruments Incorporated, <www.ti.com>
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 + */
  9 +
  10 +#include <common.h>
  11 +#include <asm/arch/ddr3.h>
  12 +#include <asm/arch/hardware.h>
  13 +#include <asm/io.h>
  14 +#include <i2c.h>
  15 +
  16 +/************************* *****************************/
  17 +static struct ddr3_phy_config ddr3phy_1600_64A = {
  18 + .pllcr = 0x0001C000ul,
  19 + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
  20 + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
  21 + .ptr0 = 0x42C21590ul,
  22 + .ptr1 = 0xD05612C0ul,
  23 + .ptr2 = 0, /* not set in gel */
  24 + .ptr3 = 0x0D861A80ul,
  25 + .ptr4 = 0x0C827100ul,
  26 + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
  27 + .dcr_val = ((1 << 10) | (1 << 27)),
  28 + .dtpr0 = 0xA19DBB66ul,
  29 + .dtpr1 = 0x12868300ul,
  30 + .dtpr2 = 0x50035200ul,
  31 + .mr0 = 0x00001C70ul,
  32 + .mr1 = 0x00000006ul,
  33 + .mr2 = 0x00000018ul,
  34 + .dtcr = 0x730035C7ul,
  35 + .pgcr2 = 0x00F07A12ul,
  36 + .zq0cr1 = 0x0000005Dul,
  37 + .zq1cr1 = 0x0000005Bul,
  38 + .zq2cr1 = 0x0000005Bul,
  39 + .pir_v1 = 0x00000033ul,
  40 + .pir_v2 = 0x0000FF81ul,
  41 +};
  42 +
  43 +static struct ddr3_emif_config ddr3_1600_64 = {
  44 + .sdcfg = 0x6200CE6aul,
  45 + .sdtim1 = 0x16709C55ul,
  46 + .sdtim2 = 0x00001D4Aul,
  47 + .sdtim3 = 0x435DFF54ul,
  48 + .sdtim4 = 0x553F0CFFul,
  49 + .zqcfg = 0xF0073200ul,
  50 + .sdrfc = 0x00001869ul,
  51 +};
  52 +
  53 +static struct ddr3_phy_config ddr3phy_1600_32 = {
  54 + .pllcr = 0x0001C000ul,
  55 + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
  56 + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
  57 + .ptr0 = 0x42C21590ul,
  58 + .ptr1 = 0xD05612C0ul,
  59 + .ptr2 = 0, /* not set in gel */
  60 + .ptr3 = 0x0D861A80ul,
  61 + .ptr4 = 0x0C827100ul,
  62 + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
  63 + .dcr_val = ((1 << 10) | (1 << 27)),
  64 + .dtpr0 = 0xA19DBB66ul,
  65 + .dtpr1 = 0x12868300ul,
  66 + .dtpr2 = 0x50035200ul,
  67 + .mr0 = 0x00001C70ul,
  68 + .mr1 = 0x00000006ul,
  69 + .mr2 = 0x00000018ul,
  70 + .dtcr = 0x730035C7ul,
  71 + .pgcr2 = 0x00F07A12ul,
  72 + .zq0cr1 = 0x0000005Dul,
  73 + .zq1cr1 = 0x0000005Bul,
  74 + .zq2cr1 = 0x0000005Bul,
  75 + .pir_v1 = 0x00000033ul,
  76 + .pir_v2 = 0x0000FF81ul,
  77 +};
  78 +
  79 +static struct ddr3_emif_config ddr3_1600_32 = {
  80 + .sdcfg = 0x6200DE6aul,
  81 + .sdtim1 = 0x16709C55ul,
  82 + .sdtim2 = 0x00001D4Aul,
  83 + .sdtim3 = 0x435DFF54ul,
  84 + .sdtim4 = 0x553F0CFFul,
  85 + .zqcfg = 0x70073200ul,
  86 + .sdrfc = 0x00001869ul,
  87 +};
  88 +
  89 +/************************* *****************************/
  90 +static struct ddr3_phy_config ddr3phy_1333_64A = {
  91 + .pllcr = 0x0005C000ul,
  92 + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
  93 + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
  94 + .ptr0 = 0x42C21590ul,
  95 + .ptr1 = 0xD05612C0ul,
  96 + .ptr2 = 0, /* not set in gel */
  97 + .ptr3 = 0x0B4515C2ul,
  98 + .ptr4 = 0x0A6E08B4ul,
  99 + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
  100 + NOSRA_MASK | UDIMM_MASK),
  101 + .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)),
  102 + .dtpr0 = 0x8558AA55ul,
  103 + .dtpr1 = 0x12857280ul,
  104 + .dtpr2 = 0x5002C200ul,
  105 + .mr0 = 0x00001A60ul,
  106 + .mr1 = 0x00000006ul,
  107 + .mr2 = 0x00000010ul,
  108 + .dtcr = 0x710035C7ul,
  109 + .pgcr2 = 0x00F065B8ul,
  110 + .zq0cr1 = 0x0000005Dul,
  111 + .zq1cr1 = 0x0000005Bul,
  112 + .zq2cr1 = 0x0000005Bul,
  113 + .pir_v1 = 0x00000033ul,
  114 + .pir_v2 = 0x0000FF81ul,
  115 +};
  116 +
  117 +static struct ddr3_emif_config ddr3_1333_64 = {
  118 + .sdcfg = 0x62008C62ul,
  119 + .sdtim1 = 0x125C8044ul,
  120 + .sdtim2 = 0x00001D29ul,
  121 + .sdtim3 = 0x32CDFF43ul,
  122 + .sdtim4 = 0x543F0ADFul,
  123 + .zqcfg = 0xF0073200ul,
  124 + .sdrfc = 0x00001457ul,
  125 +};
  126 +
  127 +static struct ddr3_phy_config ddr3phy_1333_32 = {
  128 + .pllcr = 0x0005C000ul,
  129 + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
  130 + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
  131 + .ptr0 = 0x42C21590ul,
  132 + .ptr1 = 0xD05612C0ul,
  133 + .ptr2 = 0, /* not set in gel */
  134 + .ptr3 = 0x0B4515C2ul,
  135 + .ptr4 = 0x0A6E08B4ul,
  136 + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
  137 + NOSRA_MASK | UDIMM_MASK),
  138 + .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)),
  139 + .dtpr0 = 0x8558AA55ul,
  140 + .dtpr1 = 0x12857280ul,
  141 + .dtpr2 = 0x5002C200ul,
  142 + .mr0 = 0x00001A60ul,
  143 + .mr1 = 0x00000006ul,
  144 + .mr2 = 0x00000010ul,
  145 + .dtcr = 0x710035C7ul,
  146 + .pgcr2 = 0x00F065B8ul,
  147 + .zq0cr1 = 0x0000005Dul,
  148 + .zq1cr1 = 0x0000005Bul,
  149 + .zq2cr1 = 0x0000005Bul,
  150 + .pir_v1 = 0x00000033ul,
  151 + .pir_v2 = 0x0000FF81ul,
  152 +};
  153 +
  154 +static struct ddr3_emif_config ddr3_1333_32 = {
  155 + .sdcfg = 0x62009C62ul,
  156 + .sdtim1 = 0x125C8044ul,
  157 + .sdtim2 = 0x00001D29ul,
  158 + .sdtim3 = 0x32CDFF43ul,
  159 + .sdtim4 = 0x543F0ADFul,
  160 + .zqcfg = 0xf0073200ul,
  161 + .sdrfc = 0x00001457ul,
  162 +};
  163 +
  164 +/************************* *****************************/
  165 +static struct ddr3_phy_config ddr3phy_1333_64 = {
  166 + .pllcr = 0x0005C000ul,
  167 + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
  168 + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
  169 + .ptr0 = 0x42C21590ul,
  170 + .ptr1 = 0xD05612C0ul,
  171 + .ptr2 = 0, /* not set in gel */
  172 + .ptr3 = 0x0B4515C2ul,
  173 + .ptr4 = 0x0A6E08B4ul,
  174 + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
  175 + .dcr_val = ((1 << 10) | (1 << 27)),
  176 + .dtpr0 = 0x8558AA55ul,
  177 + .dtpr1 = 0x12857280ul,
  178 + .dtpr2 = 0x5002C200ul,
  179 + .mr0 = 0x00001A60ul,
  180 + .mr1 = 0x00000006ul,
  181 + .mr2 = 0x00000010ul,
  182 + .dtcr = 0x710035C7ul,
  183 + .pgcr2 = 0x00F065B8ul,
  184 + .zq0cr1 = 0x0000005Dul,
  185 + .zq1cr1 = 0x0000005Bul,
  186 + .zq2cr1 = 0x0000005Bul,
  187 + .pir_v1 = 0x00000033ul,
  188 + .pir_v2 = 0x0000FF81ul,
  189 +};
  190 +/******************************************************/
  191 +
  192 +/* DDR PHY Configs Updated for PG 2.0
  193 + * zq0,1,2cr1 are updated for PG 2.0 specific configs *_pg2 */
  194 +static struct ddr3_phy_config ddr3phy_1600_64A_pg2 = {
  195 + .pllcr = 0x0001C000ul,
  196 + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
  197 + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
  198 + .ptr0 = 0x42C21590ul,
  199 + .ptr1 = 0xD05612C0ul,
  200 + .ptr2 = 0, /* not set in gel */
  201 + .ptr3 = 0x0D861A80ul,
  202 + .ptr4 = 0x0C827100ul,
  203 + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
  204 + .dcr_val = ((1 << 10)),
  205 + .dtpr0 = 0xA19DBB66ul,
  206 + .dtpr1 = 0x32868300ul,
  207 + .dtpr2 = 0x50035200ul,
  208 + .mr0 = 0x00001C70ul,
  209 + .mr1 = 0x00000006ul,
  210 + .mr2 = 0x00000018ul,
  211 + .dtcr = 0x730035C7ul,
  212 + .pgcr2 = 0x00F07A12ul,
  213 + .zq0cr1 = 0x0001005Dul,
  214 + .zq1cr1 = 0x0001005Bul,
  215 + .zq2cr1 = 0x0001005Bul,
  216 + .pir_v1 = 0x00000033ul,
  217 + .pir_v2 = 0x0000FF81ul,
  218 +};
  219 +
  220 +static struct ddr3_phy_config ddr3phy_1333_64A_pg2 = {
  221 + .pllcr = 0x0005C000ul,
  222 + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
  223 + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
  224 + .ptr0 = 0x42C21590ul,
  225 + .ptr1 = 0xD05612C0ul,
  226 + .ptr2 = 0, /* not set in gel */
  227 + .ptr3 = 0x0B4515C2ul,
  228 + .ptr4 = 0x0A6E08B4ul,
  229 + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
  230 + .dcr_val = ((1 << 10)),
  231 + .dtpr0 = 0x8558AA55ul,
  232 + .dtpr1 = 0x32857280ul,
  233 + .dtpr2 = 0x5002C200ul,
  234 + .mr0 = 0x00001A60ul,
  235 + .mr1 = 0x00000006ul,
  236 + .mr2 = 0x00000010ul,
  237 + .dtcr = 0x710035C7ul,
  238 + .pgcr2 = 0x00F065B8ul,
  239 + .zq0cr1 = 0x0001005Dul,
  240 + .zq1cr1 = 0x0001005Bul,
  241 + .zq2cr1 = 0x0001005Bul,
  242 + .pir_v1 = 0x00000033ul,
  243 + .pir_v2 = 0x0000FF81ul,
  244 +};
  245 +
  246 +int get_dimm_params(char *dimm_name)
  247 +{
  248 + u8 spd_params[256];
  249 + int ret;
  250 + int old_bus;
  251 +
  252 + i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
  253 +
  254 + old_bus = i2c_get_bus_num();
  255 + i2c_set_bus_num(1);
  256 +
  257 + ret = i2c_read(0x53, 0, 1, spd_params, 256);
  258 +
  259 + i2c_set_bus_num(old_bus);
  260 +
  261 + dimm_name[0] = '\0';
  262 +
  263 + if (ret) {
  264 + puts("Cannot read DIMM params\n");
  265 + return 1;
  266 + }
  267 +
  268 + /*
  269 + * We need to convert spd data to dimm parameters
  270 + * and to DDR3 EMIF and PHY regirsters values.
  271 + * For now we just return DIMM type string value.
  272 + * Caller may use this value to choose appropriate
  273 + * a pre-set DDR3 configuration
  274 + */
  275 +
  276 + strncpy(dimm_name, (char *)&spd_params[0x80], 18);
  277 + dimm_name[18] = '\0';
  278 +
  279 + return 0;
  280 +}
  281 +
  282 +struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
  283 +struct pll_init_data ddr3b_333 = DDR3_PLL_333(B);
  284 +struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
  285 +struct pll_init_data ddr3b_400 = DDR3_PLL_400(B);
  286 +
  287 +void ddr3_init(void)
  288 +{
  289 + char dimm_name[32];
  290 +
  291 + get_dimm_params(dimm_name);
  292 +
  293 + printf("Detected SO-DIMM [%s]\n", dimm_name);
  294 +
  295 + if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
  296 + init_pll(&ddr3a_400);
  297 + if (cpu_revision() > 0) {
  298 + if (cpu_revision() > 1) {
  299 + /* PG 2.0 */
  300 + /* Reset DDR3A PHY after PLL enabled */
  301 + ddr3_reset_ddrphy();
  302 + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
  303 + &ddr3phy_1600_64A_pg2);
  304 + } else {
  305 + /* PG 1.1 */
  306 + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
  307 + &ddr3phy_1600_64A);
  308 + }
  309 +
  310 + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
  311 + &ddr3_1600_64);
  312 + printf("DRAM: Capacity 8 GiB (includes reported below)\n");
  313 + } else {
  314 + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_32);
  315 + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
  316 + &ddr3_1600_32);
  317 + printf("DRAM: Capacity 4 GiB (includes reported below)\n");
  318 + }
  319 + } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
  320 + init_pll(&ddr3a_333);
  321 + if (cpu_revision() > 0) {
  322 + if (cpu_revision() > 1) {
  323 + /* PG 2.0 */
  324 + /* Reset DDR3A PHY after PLL enabled */
  325 + ddr3_reset_ddrphy();
  326 + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
  327 + &ddr3phy_1333_64A_pg2);
  328 + } else {
  329 + /* PG 1.1 */
  330 + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
  331 + &ddr3phy_1333_64A);
  332 + }
  333 + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
  334 + &ddr3_1333_64);
  335 + } else {
  336 + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_32);
  337 + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
  338 + &ddr3_1333_32);
  339 + }
  340 + } else {
  341 + printf("Unknown SO-DIMM. Cannot configure DDR3\n");
  342 + while (1)
  343 + ;
  344 + }
  345 +
  346 + init_pll(&ddr3b_333);
  347 + ddr3_init_ddrphy(KS2_DDR3B_DDRPHYC, &ddr3phy_1333_64);
  348 + ddr3_init_ddremif(KS2_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64);
  349 +}
... ... @@ -300,7 +300,7 @@
300 300 Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek <p.wilczek@samsung.com>
301 301 Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Przemyslaw Marczak <p.marczak@samsung.com>
302 302 Active arm armv7 highbank - highbank highbank - Rob Herring <robh@kernel.org>
303   -Active arm armv7 keystone ti k2hk_evm k2hk_evm - Vitaly Andrianov <vitalya@ti.com>
  303 +Active arm armv7 keystone ti ks2_evm k2hk_evm - Vitaly Andrianov <vitalya@ti.com>
304 304 Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut <marek.vasut@gmail.com>
305 305 Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg -
306 306 Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic <sbabic@denx.de>
include/configs/k2hk_evm.h
Diff comments   View file @ e595107
... ... @@ -258,6 +258,7 @@
258 258 #define CONFIG_OF_BOARD_SETUP
259 259 #define CONFIG_SYS_BARGSIZE 1024
260 260 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000)
  261 +#define CONFIG_LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100)
261 262  
262 263 #define CONFIG_SUPPORT_RAW_INITRD
263 264