Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit e634c9dc7a9f2c5a868128e14d8dbc382706e21f

Authored by Matthias Fuchs
Committed by Stefan Roese
1 parent adcdeacc3e
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ppc4xx: add support for new PMC440 revision with cleanup 

This patch adds support for the new PMC440 hardware revision 1.4.
The board now uses Micrel KSZ9031 phys.

Add missing i2c initialization before reading bootstrap eeprom.

Fix a couple of coding style issues.

Make local functions static.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>

Showing 1 changed file with 101 additions and 64 deletions Side-by-side Diff

board/esd/pmc440/pmc440.c
Diff comments   View file @ e634c9d
... ... @@ -12,7 +12,6 @@
12 12 *
13 13 * SPDX-License-Identifier: GPL-2.0+
14 14 */
15   -
16 15 #include <common.h>
17 16 #include <libfdt.h>
18 17 #include <fdt_support.h>
19 18  
20 19  
... ... @@ -34,14 +33,14 @@
34 33  
35 34 DECLARE_GLOBAL_DATA_PTR;
36 35  
37   -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
  36 +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
38 37 extern void __ft_board_setup(void *blob, bd_t *bd);
39 38  
40 39 ulong flash_get_size(ulong base, int banknum);
41   -int pci_is_66mhz(void);
  40 +static int pci_is_66mhz(void);
42 41 int is_monarch(void);
43   -int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
44   - uchar *buffer, unsigned cnt);
  42 +static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
  43 + uchar *buffer, unsigned cnt);
45 44  
46 45 struct serial_device *default_serial_console(void)
47 46 {
48 47  
49 48  
50 49  
51 50  
... ... @@ -58,23 +57,24 @@
58 57 if (((val & 0xf0000000) >> 29) != 7)
59 58 return &eserial2_device;
60 59  
61   - ulong scratchreg = in_be32((void*)GPIO0_ISR3L);
  60 + ulong scratchreg = in_be32((void *)GPIO0_ISR3L);
62 61 if (!(scratchreg & 0x80)) {
63 62 /* mark scratchreg valid */
64 63 scratchreg = (scratchreg & 0xffffff00) | 0x80;
65 64  
  65 + i2c_init_all();
  66 +
66 67 i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
67 68 0x10, buf, 4);
68 69 if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
69 70 scratchreg |= buf[2];
70 71  
71 72 /* bringup delay for console */
72   - for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) {
  73 + for (delay = 0; delay < (1000 * (ulong)buf[3]); delay++)
73 74 udelay(1000);
74   - }
75 75 } else
76 76 scratchreg |= 0x01;
77   - out_be32((void*)GPIO0_ISR3L, scratchreg);
  77 + out_be32((void *)GPIO0_ISR3L, scratchreg);
78 78 }
79 79  
80 80 if (scratchreg & 0x01)
... ... @@ -93,10 +93,7 @@
93 93 mtdcr(EBC0_CFGADDR, EBC0_CFG);
94 94 mtdcr(EBC0_CFGDATA, 0xf8400000);
95 95  
96   - /*
97   - * Setup the GPIO pins
98   - * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file
99   - */
  96 + /* Setup the GPIO pins */
100 97 out_be32((void *)GPIO0_OR, 0x40000102);
101 98 out_be32((void *)GPIO0_TCR, 0x4c90011f);
102 99 out_be32((void *)GPIO0_OSRL, 0x28051400);
... ... @@ -259,7 +256,7 @@
259 256 * USB suff...
260 257 */
261 258 if ((act == NULL || strcmp(act, "host") == 0) &&
262   - !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){
  259 + !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
263 260 /* SDR Setting */
264 261 mfsdr(SDR0_PFC1, sdr0_pfc1);
265 262 mfsdr(SDR0_USB2D0CR, usb2d0cr);
266 263  
267 264  
... ... @@ -326,16 +323,16 @@
326 323 mtsdr(SDR0_SRST1, 0x00000000);
327 324 mtsdr(SDR0_SRST0, 0x00000000);
328 325  
329   - if (!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
  326 + if (!(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
330 327 /* enable power on USB socket */
331   - out_be32((void*)GPIO1_OR,
332   - in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
  328 + out_be32((void *)GPIO1_OR,
  329 + in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N);
333 330 }
334 331  
335 332 printf("USB: Host\n");
336 333  
337 334 } else if ((strcmp(act, "dev") == 0) ||
338   - (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
  335 + (in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
339 336 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
340 337  
341 338 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
342 339  
343 340  
344 341  
345 342  
346 343  
347 344  
... ... @@ -414,30 +411,31 @@
414 411 #endif
415 412  
416 413 /* turn off POST LED */
417   - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N);
  414 + out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) & ~GPIO1_POST_N);
418 415 /* turn on RUN LED */
419   - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N);
  416 + out_be32((void *)GPIO0_OR,
  417 + in_be32((void *)GPIO0_OR) & ~GPIO0_LED_RUN_N);
420 418 return 0;
421 419 }
422 420  
423 421 int is_monarch(void)
424 422 {
425   - if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH)
  423 + if (in_be32((void *)GPIO1_IR) & GPIO1_NONMONARCH)
426 424 return 0;
427 425  
428 426 return 1;
429 427 }
430 428  
431   -int pci_is_66mhz(void)
  429 +static int pci_is_66mhz(void)
432 430 {
433   - if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN)
  431 + if (in_be32((void *)GPIO1_IR) & GPIO1_M66EN)
434 432 return 1;
435 433 return 0;
436 434 }
437 435  
438   -int board_revision(void)
  436 +static int board_revision(void)
439 437 {
440   - return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
  438 + return (int)((in_be32((void *)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
441 439 }
442 440  
443 441 int checkboard(void)
... ... @@ -495,7 +493,7 @@
495 493 out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
496 494 /* - disabled b4 setting */
497 495 out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
498   - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
  496 + out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Addr */
499 497 out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
500 498 out32r(PCIL0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */
501 499 /* and enable region */
... ... @@ -532,7 +530,8 @@
532 530  
533 531 if (is_monarch()) {
534 532 /* BAR2: map FPGA registers behind system memory at 1GB */
535   - pci_hose_write_config_dword(hose, 0, PCI_BASE_ADDRESS_2, 0x40000008);
  533 + pci_hose_write_config_dword(hose, 0,
  534 + PCI_BASE_ADDRESS_2, 0x40000008);
536 535 }
537 536  
538 537 /*
... ... @@ -562,10 +561,10 @@
562 561 CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
563 562  
564 563 /* PCI configuration done: release ERREADY */
565   - out_be32((void*)GPIO1_OR,
566   - in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY);
567   - out_be32((void*)GPIO1_TCR,
568   - in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
  564 + out_be32((void *)GPIO1_OR,
  565 + in_be32((void *)GPIO1_OR) | GPIO1_PPC_EREADY);
  566 + out_be32((void *)GPIO1_TCR,
  567 + in_be32((void *)GPIO1_TCR) | GPIO1_PPC_EREADY);
569 568 } else {
570 569 /* Program the board's subsystem id/classcode */
571 570 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
572 571  
... ... @@ -595,14 +594,14 @@
595 594  
596 595 static void wait_for_pci_ready(void)
597 596 {
598   - if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) {
  597 + if (!(in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY)) {
599 598 printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
600 599 while (1) {
601 600 if (ctrlc()) {
602 601 puts("abort\n");
603 602 break;
604 603 }
605   - if (in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY) {
  604 + if (in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY) {
606 605 printf("done\n");
607 606 break;
608 607 }
609 608  
610 609  
611 610  
... ... @@ -641,35 +640,74 @@
641 640 #endif /* defined(CONFIG_PCI) */
642 641  
643 642 #ifdef CONFIG_RESET_PHY_R
  643 +static int pmc440_setup_vsc8601(char *devname, int phy_addr,
  644 + unsigned short behavior, unsigned short method)
  645 +{
  646 + /* adjust LED behavior */
  647 + if (miiphy_write(devname, phy_addr, 0x1f, 0x0001) != 0) {
  648 + printf("Phy%d: register write access failed\n", phy_addr);
  649 + return -1;
  650 + }
  651 +
  652 + miiphy_write(devname, phy_addr, 0x11, 0x0010);
  653 + miiphy_write(devname, phy_addr, 0x11, behavior);
  654 + miiphy_write(devname, phy_addr, 0x10, method);
  655 + miiphy_write(devname, phy_addr, 0x1f, 0x0000);
  656 +
  657 + return 0;
  658 +}
  659 +
  660 +static int pmc440_setup_ksz9031(char *devname, int phy_addr)
  661 +{
  662 + unsigned short id1, id2;
  663 +
  664 + if (miiphy_read(devname, phy_addr, 2, &id1) ||
  665 + miiphy_read(devname, phy_addr, 3, &id2)) {
  666 + printf("Phy%d: cannot read id\n", phy_addr);
  667 + return -1;
  668 + }
  669 +
  670 + if ((id1 != 0x0022) || ((id2 & 0xfff0) != 0x1620)) {
  671 + printf("Phy%d: unexpected id\n", phy_addr);
  672 + return -1;
  673 + }
  674 +
  675 + /* MMD 2.08: adjust tx_clk pad skew */
  676 + miiphy_write(devname, phy_addr, 0x0d, 2);
  677 + miiphy_write(devname, phy_addr, 0x0e, 8);
  678 + miiphy_write(devname, phy_addr, 0x0d, 0x4002);
  679 + miiphy_write(devname, phy_addr, 0x0e, 0xf | (0x17 << 5));
  680 +
  681 + return 0;
  682 +}
  683 +
644 684 void reset_phy(void)
645 685 {
646 686 char *s;
647 687 unsigned short val_method, val_behavior;
648 688  
649   - /* special LED setup for NGCC/CANDES */
650   - if ((s = getenv("bd_type")) &&
651   - ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
652   - val_method = 0x0e0a;
653   - val_behavior = 0x0cf2;
  689 + if (gd->board_type < 4) {
  690 + /* special LED setup for NGCC/CANDES */
  691 + s = getenv("bd_type");
  692 + if (s && ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
  693 + val_method = 0x0e0a;
  694 + val_behavior = 0x0cf2;
  695 + } else {
  696 + /* PMC440 standard type */
  697 + val_method = 0x0e10;
  698 + val_behavior = 0x0cf0;
  699 + }
  700 +
  701 + /* boards up to rev. 1.3 use Vitesse VSC8601 phys */
  702 + pmc440_setup_vsc8601("ppc_4xx_eth0", CONFIG_PHY_ADDR,
  703 + val_method, val_behavior);
  704 + pmc440_setup_vsc8601("ppc_4xx_eth1", CONFIG_PHY1_ADDR,
  705 + val_method, val_behavior);
654 706 } else {
655   - /* PMC440 standard type */
656   - val_method = 0x0e10;
657   - val_behavior = 0x0cf0;
  707 + /* rev. 1.4 uses a Micrel KSZ9031 */
  708 + pmc440_setup_ksz9031("ppc_4xx_eth0", CONFIG_PHY_ADDR);
  709 + pmc440_setup_ksz9031("ppc_4xx_eth1", CONFIG_PHY1_ADDR);
658 710 }
659   -
660   - if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
661   - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
662   - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior);
663   - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method);
664   - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
665   - }
666   -
667   - if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
668   - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
669   - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior);
670   - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method);
671   - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
672   - }
673 711 }
674 712 #endif
675 713  
... ... @@ -729,7 +767,6 @@
729 767 * We must write the address again when changing pages
730 768 * because the address counter only increments within a page.
731 769 */
732   -
733 770 while (offset < end) {
734 771 unsigned alen, len;
735 772 unsigned maxlen;
... ... @@ -771,8 +808,8 @@
771 808 return rcode;
772 809 }
773 810  
774   -int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset,
775   - uchar *buffer, unsigned cnt)
  811 +static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
  812 + uchar *buffer, unsigned cnt)
776 813 {
777 814 unsigned end = offset + cnt;
778 815 unsigned blk_off;
779 816  
... ... @@ -820,10 +857,10 @@
820 857 int i;
821 858  
822 859 if ((act == NULL || strcmp(act, "host") == 0) &&
823   - !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT))
  860 + !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT))
824 861 /* enable power on USB socket */
825   - out_be32((void*)GPIO1_OR,
826   - in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
  862 + out_be32((void *)GPIO1_OR,
  863 + in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N);
827 864  
828 865 for (i=0; i<1000; i++)
829 866 udelay(1000);
... ... @@ -834,7 +871,7 @@
834 871 int usb_board_stop(void)
835 872 {
836 873 /* disable power on USB socket */
837   - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_USB_PWR_N);
  874 + out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) | GPIO1_USB_PWR_N);
838 875 return 0;
839 876 }
840 877  
... ... @@ -858,8 +895,8 @@
858 895 rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status",
859 896 "disabled", sizeof("disabled"), 1);
860 897 if (rc) {
861   - printf("Unable to update property status in PCI node, err=%s\n",
862   - fdt_strerror(rc));
  898 + printf("Unable to update property status in PCI node, ");
  899 + printf("err=%s\n", fdt_strerror(rc));
863 900 }
864 901 }
865 902 }