Merge branch 'master' of git://git.denx.de/u-boot-video

Tom Rini
2 parents 6071cd62d5 535cce0f90
Showing 3 changed files Side-by-side Diff
drivers/video/da8xx-fb.c
drivers/video/exynos_dp.c
drivers/video/exynos_dp_lowlevel.c
@@ -379,7 +379,7 @@
 {
 	u32 reg;
  
-	/* Set the AC Bias Period and Number of Transisitons per Interrupt */
+	/* Set the AC Bias Period and Number of Transitions per Interrupt */
 	reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
 	reg |= LCD_AC_BIAS_FREQUENCY(period) |
 		LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
@@ -487,7 +487,7 @@
 	/* Pixels per line = (PPL + 1)*16 */
 	if (lcd_revision == LCD_VERSION_1) {
 		/*
-		 * 0x3F in bits 4..9 gives max horisontal resolution = 1024
+		 * 0x3F in bits 4..9 gives max horizontal resolution = 1024
 		 * pixels
 		 */
 		width &= 0x3f0;
@@ -695,7 +695,7 @@
 	lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
 	lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
  
-	/* Configure for disply */
+	/* Configure for display */
 	ret = lcd_cfg_display(cfg);
 	if (ret < 0)
 		return ret;
@@ -761,7 +761,7 @@
  
 		lcdc_write(stat, &da8xx_fb_reg_base->stat);
  
-		/* Disable PL completion inerrupt */
+		/* Disable PL completion interrupt */
 		reg_ras  = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
 		reg_ras &= ~LCD_V1_PL_INT_ENA;
 		lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
@@ -810,7 +810,7 @@
  
 		lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
  
-		/* Disable PL completion inerrupt */
+		/* Disable PL completion interrupt */
 		reg_int  = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) |
 			(LCD_V2_PL_INT_ENA);
 		lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr);
@@ -207,7 +207,7 @@
 		return -EINVAL;
 	}
  
-	/*Refer VESA Display Port Stnadard Ver1.1a Page 120 */
+	/* Refer VESA Display Port Standard Ver1.1a Page 120 */
 	if (edp_info->dpcd_rev == DP_DPCD_REV_11) {
 		temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f;
 		if (buf[DPCD_MAX_LANE_COUNT] & 0x80)
@@ -270,7 +270,7 @@
 		return ret;
 	}
  
-	/* Set link rate and count as you want to establish*/
+	/* Set link rate and count as you want to establish */
 	exynos_dp_set_link_bandwidth(edp_info->lane_bw);
 	exynos_dp_set_lane_count(edp_info->lane_cnt);
  
@@ -322,7 +322,7 @@
 	ret = exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
 			DPCD_TRAINING_PATTERN_DISABLED);
 	if (ret != EXYNOS_DP_SUCCESS) {
-		printf("DP requst_link_traninig_req failed\n");
+		printf("DP request_link_training_req failed\n");
 		return -EAGAIN;
 	}
  
@@ -412,7 +412,7 @@
 	unsigned int dpcd_addr;
 	unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
  
-	/*lane_num value is used as arry index, so this range 0 ~ 3 */
+	/* lane_num value is used as array index, so this range 0 ~ 3 */
 	dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
  
 	ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf);
@@ -433,7 +433,7 @@
  
 	ret = exynos_dp_training_pattern_dis();
 	if (ret != EXYNOS_DP_SUCCESS) {
-		printf("DP training_patter_disable() failed\n");
+		printf("DP training_pattern_disable() failed\n");
 		edp_info->lt_info.lt_status = DP_LT_FAIL;
 	}
  
@@ -523,7 +523,7 @@
 		ret = exynos_dp_write_bytes_to_dpcd(
 				DPCD_TRAINING_PATTERN_SET, 5, buf);
 		if (ret != EXYNOS_DP_SUCCESS) {
-			printf("DP write traning pattern1 failed\n");
+			printf("DP write training pattern1 failed\n");
 			edp_info->lt_info.lt_status = DP_LT_FAIL;
 			return ret;
 		} else
@@ -567,7 +567,7 @@
 		ret = exynos_dp_write_bytes_to_dpcd(
 				DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val);
 		if (ret != EXYNOS_DP_SUCCESS) {
-			printf("DP write traning pattern2 failed\n");
+			printf("DP write training pattern2 failed\n");
 			edp_info->lt_info.lt_status = DP_LT_FAIL;
 			return ret;
 		}
@@ -738,7 +738,7 @@
  
 	ret = exynos_dp_sw_link_training(edp_info);
 	if (ret != EXYNOS_DP_SUCCESS)
-		printf("DP dp_sw_link_traning() failed\n");
+		printf("DP dp_sw_link_training() failed\n");
  
 	return ret;
 }
@@ -44,7 +44,7 @@
 	reg = readl(&dp_regs->video_ctl1);
 	reg &= ~VIDEO_EN_MASK;
  
-	/* enable video input*/
+	/* enable video input */
 	if (enable)
 		reg |= VIDEO_EN_MASK;
  
  
@@ -55,13 +55,13 @@
  
 void exynos_dp_enable_video_bist(unsigned int enable)
 {
-	/*enable video bist*/
+	/* enable video bist */
 	unsigned int reg;
  
 	reg = readl(&dp_regs->video_ctl4);
 	reg &= ~VIDEO_BIST_MASK;
  
-	/*enable video bist*/
+	/* enable video bist */
 	if (enable)
 		reg |= VIDEO_BIST_MASK;
  
@@ -112,7 +112,7 @@
 	/*
 	 * Set AUX TX terminal resistor to 102 ohm
 	 * Set AUX channel amplitude control
-	*/
+	 */
 	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA;
 	writel(reg, &dp_regs->pll_filter_ctl1);
  
@@ -146,7 +146,7 @@
 	 */
 	writel(INT_POL, &dp_regs->int_ctl);
  
-	/* Clear pending regisers */
+	/* Clear pending registers */
 	writel(0xff, &dp_regs->common_int_sta1);
 	writel(0xff, &dp_regs->common_int_sta2);
 	writel(0xff, &dp_regs->common_int_sta3);
@@ -165,7 +165,7 @@
 {
 	unsigned int reg_func_1;
  
-	/*dp tx sw reset*/
+	/* dp tx sw reset */
 	writel(RESET_DP_TX, &dp_regs->tx_sw_reset);
  
 	exynos_dp_enable_video_input(DP_DISABLE);
@@ -287,7 +287,7 @@
 	unsigned int retry_cnt = 10;
 	unsigned int reg;
  
-	/*Power On All Analog block */
+	/* Power On All Analog block */
 	exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE);
  
 	reg = PLL_LOCK_CHG;
  
@@ -297,14 +297,14 @@
 	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
 	writel(reg, &dp_regs->debug_ctl);
  
-	/*Assert DP PLL Reset*/
+	/* Assert DP PLL Reset */
 	reg = readl(&dp_regs->pll_ctl);
 	reg |= DP_PLL_RESET;
 	writel(reg, &dp_regs->pll_ctl);
  
 	mdelay(1);
  
-	/*Deassert DP PLL Reset*/
+	/* Deassert DP PLL Reset */
 	reg = readl(&dp_regs->pll_ctl);
 	reg &= ~(DP_PLL_RESET);
 	writel(reg, &dp_regs->pll_ctl);
@@ -336,7 +336,7 @@
 {
 	unsigned int reg;
  
-	/* Clear interrupts releated to Hot Plug Dectect */
+	/* Clear interrupts related to Hot Plug Detect */
 	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
 	writel(reg, &dp_regs->common_int_sta4);
  
@@ -366,7 +366,7 @@
 {
 	unsigned int reg;
  
-	/* Clear inerrupts related to AUX channel */
+	/* Clear interrupts related to AUX channel */
 	reg = RPLY_RECEIV | AUX_ERR;
 	writel(reg, &dp_regs->int_sta);
  
@@ -377,7 +377,7 @@
 		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 	writel(reg, &dp_regs->aux_hw_retry_ctl);
  
-	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
+	/* Receive AUX Channel DEFER commands equal to DEFER_COUNT*64 */
 	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
 	writel(reg, &dp_regs->aux_ch_defer_ctl);
  
@@ -1040,7 +1040,7 @@
 	reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
 	writel(reg, &dp_regs->video_ctl10);
  
-	/*Set video mode to slave mode */
+	/* Set video mode to slave mode */
 	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
 	writel(reg, &dp_regs->soc_general_ctl);
 }
...	...	@@ -379,7 +379,7 @@
379	379	{
380	380	u32 reg;
381	381
382		- /* Set the AC Bias Period and Number of Transisitons per Interrupt */
	382	+ /* Set the AC Bias Period and Number of Transitions per Interrupt */
383	383	reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
384	384	reg \|= LCD_AC_BIAS_FREQUENCY(period) \|
385	385	LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
...	...	@@ -487,7 +487,7 @@
487	487	/* Pixels per line = (PPL + 1)16 /
488	488	if (lcd_revision == LCD_VERSION_1) {
489	489	/*
490		- * 0x3F in bits 4..9 gives max horisontal resolution = 1024
	490	+ * 0x3F in bits 4..9 gives max horizontal resolution = 1024
491	491	* pixels
492	492	*/
493	493	width &= 0x3f0;
...	...	@@ -695,7 +695,7 @@
695	695	lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
696	696	lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
697	697
698		- /* Configure for disply */
	698	+ /* Configure for display */
699	699	ret = lcd_cfg_display(cfg);
700	700	if (ret < 0)
701	701	return ret;
...	...	@@ -761,7 +761,7 @@
761	761
762	762	lcdc_write(stat, &da8xx_fb_reg_base->stat);
763	763
764		- /* Disable PL completion inerrupt */
	764	+ /* Disable PL completion interrupt */
765	765	reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
766	766	reg_ras &= ~LCD_V1_PL_INT_ENA;
767	767	lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
...	...	@@ -810,7 +810,7 @@
810	810
811	811	lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
812	812
813		- /* Disable PL completion inerrupt */
	813	+ /* Disable PL completion interrupt */
814	814	reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) \|
815	815	(LCD_V2_PL_INT_ENA);
816	816	lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr);
...	...	@@ -207,7 +207,7 @@
207	207	return -EINVAL;
208	208	}
209	209
210		- /Refer VESA Display Port Stnadard Ver1.1a Page 120 /
	210	+ /* Refer VESA Display Port Standard Ver1.1a Page 120 */
211	211	if (edp_info->dpcd_rev == DP_DPCD_REV_11) {
212	212	temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f;
213	213	if (buf[DPCD_MAX_LANE_COUNT] & 0x80)
...	...	@@ -270,7 +270,7 @@
270	270	return ret;
271	271	}
272	272
273		- /* Set link rate and count as you want to establish*/
	273	+ /* Set link rate and count as you want to establish */
274	274	exynos_dp_set_link_bandwidth(edp_info->lane_bw);
275	275	exynos_dp_set_lane_count(edp_info->lane_cnt);
276	276
...	...	@@ -322,7 +322,7 @@
322	322	ret = exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
323	323	DPCD_TRAINING_PATTERN_DISABLED);
324	324	if (ret != EXYNOS_DP_SUCCESS) {
325		- printf("DP requst_link_traninig_req failed\n");
	325	+ printf("DP request_link_training_req failed\n");
326	326	return -EAGAIN;
327	327	}
328	328
...	...	@@ -412,7 +412,7 @@
412	412	unsigned int dpcd_addr;
413	413	unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
414	414
415		- /lane_num value is used as arry index, so this range 0 ~ 3 /
	415	+ /* lane_num value is used as array index, so this range 0 ~ 3 */
416	416	dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
417	417
418	418	ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf);
...	...	@@ -433,7 +433,7 @@
433	433
434	434	ret = exynos_dp_training_pattern_dis();
435	435	if (ret != EXYNOS_DP_SUCCESS) {
436		- printf("DP training_patter_disable() failed\n");
	436	+ printf("DP training_pattern_disable() failed\n");
437	437	edp_info->lt_info.lt_status = DP_LT_FAIL;
438	438	}
439	439
...	...	@@ -523,7 +523,7 @@
523	523	ret = exynos_dp_write_bytes_to_dpcd(
524	524	DPCD_TRAINING_PATTERN_SET, 5, buf);
525	525	if (ret != EXYNOS_DP_SUCCESS) {
526		- printf("DP write traning pattern1 failed\n");
	526	+ printf("DP write training pattern1 failed\n");
527	527	edp_info->lt_info.lt_status = DP_LT_FAIL;
528	528	return ret;
529	529	} else
...	...	@@ -567,7 +567,7 @@
567	567	ret = exynos_dp_write_bytes_to_dpcd(
568	568	DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val);
569	569	if (ret != EXYNOS_DP_SUCCESS) {
570		- printf("DP write traning pattern2 failed\n");
	570	+ printf("DP write training pattern2 failed\n");
571	571	edp_info->lt_info.lt_status = DP_LT_FAIL;
572	572	return ret;
573	573	}
...	...	@@ -738,7 +738,7 @@
738	738
739	739	ret = exynos_dp_sw_link_training(edp_info);
740	740	if (ret != EXYNOS_DP_SUCCESS)
741		- printf("DP dp_sw_link_traning() failed\n");
	741	+ printf("DP dp_sw_link_training() failed\n");
742	742
743	743	return ret;
744	744	}
...	...	@@ -44,7 +44,7 @@
44	44	reg = readl(&dp_regs->video_ctl1);
45	45	reg &= ~VIDEO_EN_MASK;
46	46
47		- /* enable video input*/
	47	+ /* enable video input */
48	48	if (enable)
49	49	reg \|= VIDEO_EN_MASK;
50	50
51	51
...	...	@@ -55,13 +55,13 @@
55	55
56	56	void exynos_dp_enable_video_bist(unsigned int enable)
57	57	{
58		- /enable video bist/
	58	+ /* enable video bist */
59	59	unsigned int reg;
60	60
61	61	reg = readl(&dp_regs->video_ctl4);
62	62	reg &= ~VIDEO_BIST_MASK;
63	63
64		- /enable video bist/
	64	+ /* enable video bist */
65	65	if (enable)
66	66	reg \|= VIDEO_BIST_MASK;
67	67
...	...	@@ -112,7 +112,7 @@
112	112	/*
113	113	* Set AUX TX terminal resistor to 102 ohm
114	114	* Set AUX channel amplitude control
115		- */
	115	+ */
116	116	reg = PD_RING_OSC \| AUX_TERMINAL_CTRL_52_OHM \| TX_CUR1_2X \| TX_CUR_4_MA;
117	117	writel(reg, &dp_regs->pll_filter_ctl1);
118	118
...	...	@@ -146,7 +146,7 @@
146	146	*/
147	147	writel(INT_POL, &dp_regs->int_ctl);
148	148
149		- /* Clear pending regisers */
	149	+ /* Clear pending registers */
150	150	writel(0xff, &dp_regs->common_int_sta1);
151	151	writel(0xff, &dp_regs->common_int_sta2);
152	152	writel(0xff, &dp_regs->common_int_sta3);
...	...	@@ -165,7 +165,7 @@
165	165	{
166	166	unsigned int reg_func_1;
167	167
168		- /dp tx sw reset/
	168	+ /* dp tx sw reset */
169	169	writel(RESET_DP_TX, &dp_regs->tx_sw_reset);
170	170
171	171	exynos_dp_enable_video_input(DP_DISABLE);
...	...	@@ -287,7 +287,7 @@
287	287	unsigned int retry_cnt = 10;
288	288	unsigned int reg;
289	289
290		- /Power On All Analog block /
	290	+ /* Power On All Analog block */
291	291	exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE);
292	292
293	293	reg = PLL_LOCK_CHG;
294	294
...	...	@@ -297,14 +297,14 @@
297	297	reg &= ~(F_PLL_LOCK \| PLL_LOCK_CTRL);
298	298	writel(reg, &dp_regs->debug_ctl);
299	299
300		- /Assert DP PLL Reset/
	300	+ /* Assert DP PLL Reset */
301	301	reg = readl(&dp_regs->pll_ctl);
302	302	reg \|= DP_PLL_RESET;
303	303	writel(reg, &dp_regs->pll_ctl);
304	304
305	305	mdelay(1);
306	306
307		- /Deassert DP PLL Reset/
	307	+ /* Deassert DP PLL Reset */
308	308	reg = readl(&dp_regs->pll_ctl);
309	309	reg &= ~(DP_PLL_RESET);
310	310	writel(reg, &dp_regs->pll_ctl);
...	...	@@ -336,7 +336,7 @@
336	336	{
337	337	unsigned int reg;
338	338
339		- /* Clear interrupts releated to Hot Plug Dectect */
	339	+ /* Clear interrupts related to Hot Plug Detect */
340	340	reg = HOTPLUG_CHG \| HPD_LOST \| PLUG;
341	341	writel(reg, &dp_regs->common_int_sta4);
342	342
...	...	@@ -366,7 +366,7 @@
366	366	{
367	367	unsigned int reg;
368	368
369		- /* Clear inerrupts related to AUX channel */
	369	+ /* Clear interrupts related to AUX channel */
370	370	reg = RPLY_RECEIV \| AUX_ERR;
371	371	writel(reg, &dp_regs->int_sta);
372	372
...	...	@@ -377,7 +377,7 @@
377	377	AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
378	378	writel(reg, &dp_regs->aux_hw_retry_ctl);
379	379
380		- /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT64 /
	380	+ /* Receive AUX Channel DEFER commands equal to DEFER_COUNT64 /
381	381	reg = DEFER_CTRL_EN \| DEFER_COUNT(1);
382	382	writel(reg, &dp_regs->aux_ch_defer_ctl);
383	383
...	...	@@ -1040,7 +1040,7 @@
1040	1040	reg \|= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
1041	1041	writel(reg, &dp_regs->video_ctl10);
1042	1042
1043		- /Set video mode to slave mode /
	1043	+ /* Set video mode to slave mode */
1044	1044	reg = AUDIO_MODE_SPDIF_MODE \| VIDEO_MODE_SLAVE_MODE;
1045	1045	writel(reg, &dp_regs->soc_general_ctl);
1046	1046	}