Eric Lee / smarc-uboot

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Commit e6b6d16de73de6a76e2ec4338291e828b860f040

Authored by Wolfgang Denk
2 parents a9e642e2f8 81a3170b15
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Merge with /home/sr/git/u-boot

Showing 3 changed files Side-by-side Diff

... ... @@ -2,6 +2,13 @@
2 2 Changes for U-Boot 1.1.4:
3 3 ======================================================================
4 4  
  5 +* Changes to Yellowstone & Yosemite 440EP/GR eval boards:
  6 + - Changed GPIO setup to enable another address line in order to
  7 + address 64M of FLASH.
  8 + - Added function sdram_tr1_set to auto calculate the tr1 value for
  9 + the DDR.
  10 + Patch by Steven Blakeslee, 12 Dec 2005
  11 +
5 12 * MPC5200: Set PCI retry counter to 0 = infinite retry;
6 13 The default of 255 is too short for slow devices.
7 14 Patch by Martin Nykodym, 12 Dec 2005
board/amcc/yellowstone/yellowstone.c
Diff comments   View file @ e6b6d16
... ... @@ -59,10 +59,10 @@
59 59 * Setup the GPIO pins
60 60 *-------------------------------------------------------------------*/
61 61 /*CPLD cs */
62   - /*setup Address lines for flash sizes larger than 16Meg. */
63   - out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
64   - out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
65   - out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
  62 + /*setup Address lines for flash size 64Meg. */
  63 + out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
  64 + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
  65 + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
66 66  
67 67 /*setup emac */
68 68 out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
... ... @@ -129,7 +129,7 @@
129 129 #endif
130 130  
131 131 /*get rid of flash write protect */
132   - *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
  132 + *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
133 133  
134 134 return 0;
135 135 }
136 136  
... ... @@ -207,9 +207,85 @@
207 207 * PLB @ 133 MHz
208 208 *
209 209 ************************************************************************/
  210 +#define NUM_TRIES 64
  211 +#define NUM_READS 10
  212 +
  213 +void sdram_tr1_set(int ram_address, int* tr1_value)
  214 +{
  215 + int i;
  216 + int j, k;
  217 + volatile unsigned int* ram_pointer = (unsigned int*)ram_address;
  218 + int first_good = -1, last_bad = 0x1ff;
  219 +
  220 + unsigned long test[NUM_TRIES] = {
  221 + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
  222 + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
  223 + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
  224 + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
  225 + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
  226 + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
  227 + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
  228 + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
  229 + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
  230 + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
  231 + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
  232 + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
  233 + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
  234 + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
  235 + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
  236 + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
  237 +
  238 + /* go through all possible SDRAM0_TR1[RDCT] values */
  239 + for (i=0; i<=0x1ff; i++) {
  240 + /* set the current value for TR1 */
  241 + mtsdram(mem_tr1, (0x80800800 | i));
  242 +
  243 + /* write values */
  244 + for (j=0; j<NUM_TRIES; j++) {
  245 + ram_pointer[j] = test[j];
  246 +
  247 + /* clear any cache at ram location */
  248 + __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
  249 + }
  250 +
  251 + /* read values back */
  252 + for (j=0; j<NUM_TRIES; j++) {
  253 + for (k=0; k<NUM_READS; k++) {
  254 + /* clear any cache at ram location */
  255 + __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
  256 +
  257 + if (ram_pointer[j] != test[j])
  258 + break;
  259 + }
  260 +
  261 + /* read error */
  262 + if (k != NUM_READS) {
  263 + break;
  264 + }
  265 + }
  266 +
  267 + /* we have a SDRAM0_TR1[RDCT] that is part of the window */
  268 + if (j == NUM_TRIES) {
  269 + if (first_good == -1)
  270 + first_good = i; /* found beginning of window */
  271 + } else { /* bad read */
  272 + /* if we have not had a good read then don't care */
  273 + if(first_good != -1) {
  274 + /* first failure after a good read */
  275 + last_bad = i-1;
  276 + break;
  277 + }
  278 + }
  279 + }
  280 +
  281 + /* return the current value for TR1 */
  282 + *tr1_value = (first_good + last_bad) / 2;
  283 +}
  284 +
210 285 void sdram_init(void)
211 286 {
212 287 register uint reg;
  288 + int tr1_bank1, tr1_bank2;
213 289  
214 290 /*--------------------------------------------------------------------
215 291 * Setup some default
... ... @@ -221,7 +297,7 @@
221 297 mtsdram(mem_wddctr, 0x40000000); /* ?? */
222 298  
223 299 /*clear this first, if the DDR is enabled by a debugger
224   - then you can not make changes. */
  300 + then you can not make changes. */
225 301 mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
226 302  
227 303 /*--------------------------------------------------------------------
... ... @@ -234,7 +310,6 @@
234 310 mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
235 311  
236 312 mtsdram(mem_tr0, 0x410a4012); /* ?? */
237   - mtsdram(mem_tr1, 0x8080080b); /* ?? */
238 313 mtsdram(mem_rtr, 0x04080000); /* ?? */
239 314 mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
240 315 mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
... ... @@ -250,6 +325,10 @@
250 325 if (reg & 0x80000000)
251 326 break;
252 327 }
  328 +
  329 + sdram_tr1_set(0x00000000, &tr1_bank1);
  330 + sdram_tr1_set(0x08000000, &tr1_bank2);
  331 + mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
253 332 }
254 333  
255 334 /*************************************************************************
board/amcc/yosemite/yosemite.c
Diff comments   View file @ e6b6d16
... ... @@ -59,10 +59,10 @@
59 59 * Setup the GPIO pins
60 60 *-------------------------------------------------------------------*/
61 61 /*CPLD cs */
62   - /*setup Address lines for flash sizes larger than 16Meg. */
63   - out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
64   - out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
65   - out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
  62 + /*setup Address lines for flash size 64Meg. */
  63 + out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
  64 + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
  65 + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
66 66  
67 67 /*setup emac */
68 68 out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
... ... @@ -125,7 +125,7 @@
125 125 *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
126 126  
127 127 /*get rid of flash write protect */
128   - *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
  128 + *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
129 129  
130 130 return 0;
131 131 }
132 132  
... ... @@ -203,9 +203,85 @@
203 203 * PLB @ 133 MHz
204 204 *
205 205 ************************************************************************/
  206 +#define NUM_TRIES 64
  207 +#define NUM_READS 10
  208 +
  209 +void sdram_tr1_set(int ram_address, int* tr1_value)
  210 +{
  211 + int i;
  212 + int j, k;
  213 + volatile unsigned int* ram_pointer = (unsigned int*)ram_address;
  214 + int first_good = -1, last_bad = 0x1ff;
  215 +
  216 + unsigned long test[NUM_TRIES] = {
  217 + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
  218 + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
  219 + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
  220 + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
  221 + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
  222 + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
  223 + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
  224 + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
  225 + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
  226 + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
  227 + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
  228 + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
  229 + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
  230 + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
  231 + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
  232 + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
  233 +
  234 + /* go through all possible SDRAM0_TR1[RDCT] values */
  235 + for (i=0; i<=0x1ff; i++) {
  236 + /* set the current value for TR1 */
  237 + mtsdram(mem_tr1, (0x80800800 | i));
  238 +
  239 + /* write values */
  240 + for (j=0; j<NUM_TRIES; j++) {
  241 + ram_pointer[j] = test[j];
  242 +
  243 + /* clear any cache at ram location */
  244 + __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
  245 + }
  246 +
  247 + /* read values back */
  248 + for (j=0; j<NUM_TRIES; j++) {
  249 + for (k=0; k<NUM_READS; k++) {
  250 + /* clear any cache at ram location */
  251 + __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
  252 +
  253 + if (ram_pointer[j] != test[j])
  254 + break;
  255 + }
  256 +
  257 + /* read error */
  258 + if (k != NUM_READS) {
  259 + break;
  260 + }
  261 + }
  262 +
  263 + /* we have a SDRAM0_TR1[RDCT] that is part of the window */
  264 + if (j == NUM_TRIES) {
  265 + if (first_good == -1)
  266 + first_good = i; /* found beginning of window */
  267 + } else { /* bad read */
  268 + /* if we have not had a good read then don't care */
  269 + if(first_good != -1) {
  270 + /* first failure after a good read */
  271 + last_bad = i-1;
  272 + break;
  273 + }
  274 + }
  275 + }
  276 +
  277 + /* return the current value for TR1 */
  278 + *tr1_value = (first_good + last_bad) / 2;
  279 +}
  280 +
206 281 void sdram_init(void)
207 282 {
208 283 register uint reg;
  284 + int tr1_bank1, tr1_bank2;
209 285  
210 286 /*--------------------------------------------------------------------
211 287 * Setup some default
... ... @@ -217,7 +293,7 @@
217 293 mtsdram(mem_wddctr, 0x40000000); /* ?? */
218 294  
219 295 /*clear this first, if the DDR is enabled by a debugger
220   - then you can not make changes. */
  296 + then you can not make changes. */
221 297 mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
222 298  
223 299 /*--------------------------------------------------------------------
... ... @@ -230,7 +306,6 @@
230 306 mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
231 307  
232 308 mtsdram(mem_tr0, 0x410a4012); /* ?? */
233   - mtsdram(mem_tr1, 0x8080080b); /* ?? */
234 309 mtsdram(mem_rtr, 0x04080000); /* ?? */
235 310 mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
236 311 mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
... ... @@ -246,6 +321,10 @@
246 321 if (reg & 0x80000000)
247 322 break;
248 323 }
  324 +
  325 + sdram_tr1_set(0x00000000, &tr1_bank1);
  326 + sdram_tr1_set(0x08000000, &tr1_bank2);
  327 + mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
249 328 }
250 329  
251 330 /*************************************************************************