Eric Lee / smarc-uboot

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Commit e6f2e902334d5ee65bab9cf8292cf668243531e9

Authored by Marian Balakowicz
1 parent 3df5bea0b0
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Added support for TQM834x boards.

Showing 25 changed files with 1282 additions and 140 deletions Side-by-side Diff

... ... @@ -114,7 +114,7 @@
114 114 #########################################################################
115 115  
116 116 LIST_83xx=" \
117   - MPC8349ADS \
  117 + MPC8349ADS TQM834x\
118 118 "
119 119  
120 120  
... ... @@ -1241,6 +1241,9 @@
1241 1241 MPC8349ADS_config: unconfig
1242 1242 @./mkconfig $(@:_config=) ppc mpc83xx mpc8349ads
1243 1243  
  1244 +TQM834x_config: unconfig
  1245 + @./mkconfig $(@:_config=) ppc mpc83xx tqm834x
  1246 +
1244 1247 #########################################################################
1245 1248 ## MPC85xx Systems
1246 1249 #########################################################################
board/tqm834x/Makefile
Diff comments   View file @ e6f2e90
  1 +#
  2 +# Copyright 2004 Freescale Semiconductor, Inc.
  3 +#
  4 +# See file CREDITS for list of people who contributed to this
  5 +# project.
  6 +#
  7 +# This program is free software; you can redistribute it and/or
  8 +# modify it under the terms of the GNU General Public License as
  9 +# published by the Free Software Foundation; either version 2 of
  10 +# the License, or (at your option) any later version.
  11 +#
  12 +# This program is distributed in the hope that it will be useful,
  13 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 +# GNU General Public License for more details.
  16 +#
  17 +# You should have received a copy of the GNU General Public License
  18 +# along with this program; if not, write to the Free Software
  19 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 +# MA 02111-1307 USA
  21 +#
  22 +
  23 +include $(TOPDIR)/config.mk
  24 +
  25 +LIB = lib$(BOARD).a
  26 +
  27 +OBJS := $(BOARD).o
  28 +
  29 +$(LIB): $(OBJS) $(SOBJS)
  30 + $(AR) crv $@ $(OBJS)
  31 +
  32 +clean:
  33 + rm -f $(SOBJS) $(OBJS)
  34 +
  35 +distclean: clean
  36 + rm -f $(LIB) core *.bak .depend
  37 +
  38 +#########################################################################
  39 +
  40 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
  41 + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
  42 +
  43 +-include .depend
  44 +
  45 +#########################################################################
board/tqm834x/config.mk
Diff comments   View file @ e6f2e90
  1 +#
  2 +# Copyright 2004 Freescale Semiconductor, Inc.
  3 +#
  4 +# See file CREDITS for list of people who contributed to this
  5 +# project.
  6 +#
  7 +# This program is free software; you can redistribute it and/or
  8 +# modify it under the terms of the GNU General Public License as
  9 +# published by the Free Software Foundation; either version 2 of
  10 +# the License, or (at your option) any later version.
  11 +#
  12 +# This program is distributed in the hope that it will be useful,
  13 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 +# GNU General Public License for more details.
  16 +#
  17 +# You should have received a copy of the GNU General Public License
  18 +# along with this program; if not, write to the Free Software
  19 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 +# MA 02111-1307 USA
  21 +#
  22 +
  23 +TEXT_BASE = 0x80000000
board/tqm834x/tqm834x.c
Diff comments   View file @ e6f2e90
  1 +/*
  2 + * (C) Copyright 2005
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + *
  23 + */
  24 +
  25 +#include <common.h>
  26 +#include <ioports.h>
  27 +#include <mpc83xx.h>
  28 +#include <asm/mpc8349_pci.h>
  29 +#include <i2c.h>
  30 +#include <spd.h>
  31 +#include <miiphy.h>
  32 +#include <asm-ppc/mmu.h>
  33 +
  34 +#if defined(CONFIG_PCI)
  35 +#include <pci.h>
  36 +#endif
  37 +
  38 +#define IOSYNC asm("eieio")
  39 +#define ISYNC asm("isync")
  40 +#define SYNC asm("sync")
  41 +#define FPW FLASH_PORT_WIDTH
  42 +#define FPWV FLASH_PORT_WIDTHV
  43 +
  44 +#define DDR_MAX_SIZE_PER_CS 0x20000000
  45 +
  46 +#if defined(DDR_CASLAT_20)
  47 +#define TIMING_CASLAT TIMING_CFG1_CASLAT_20
  48 +#define MODE_CASLAT DDR_MODE_CASLAT_20
  49 +#else
  50 +#define TIMING_CASLAT TIMING_CFG1_CASLAT_25
  51 +#define MODE_CASLAT DDR_MODE_CASLAT_25
  52 +#endif
  53 +
  54 +#define INITIAL_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \
  55 + CSCONFIG_COL_BIT_9)
  56 +
  57 +/* Global variable used to store detected number of banks */
  58 +int tqm834x_num_flash_banks;
  59 +
  60 +/* External definitions */
  61 +ulong flash_get_size (ulong base, int banknum);
  62 +extern flash_info_t flash_info[];
  63 +extern long spd_sdram (void);
  64 +
  65 +/* Local functions */
  66 +static int detect_num_flash_banks(void);
  67 +static long int get_ddr_bank_size(short cs, volatile long *base);
  68 +static void set_cs_bounds(short cs, long base, long size);
  69 +static void set_cs_config(short cs, long config);
  70 +static void set_ddr_config(void);
  71 +
  72 +/* Local variable */
  73 +static volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
  74 +
  75 +/**************************************************************************
  76 + * Board initialzation after relocation to RAM. Used to detect the number
  77 + * of Flash banks on TQM834x.
  78 + */
  79 +int board_early_init_r (void) {
  80 + /* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */
  81 + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
  82 + return 0;
  83 +
  84 + /* detect the number of Flash banks */
  85 + return detect_num_flash_banks();
  86 +}
  87 +
  88 +/**************************************************************************
  89 + * DRAM initalization and size detection
  90 + */
  91 +long int initdram (int board_type)
  92 +{
  93 + long bank_size;
  94 + long size;
  95 + int cs;
  96 +
  97 + /* during size detection, set up the max DDRLAW size */
  98 + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE;
  99 + im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
  100 +
  101 + /* set CS bounds to maximum size */
  102 + for(cs = 0; cs < 4; ++cs) {
  103 + set_cs_bounds(cs,
  104 + CFG_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),
  105 + DDR_MAX_SIZE_PER_CS);
  106 +
  107 + set_cs_config(cs, INITIAL_CS_CONFIG);
  108 + }
  109 +
  110 + /* configure ddr controller */
  111 + set_ddr_config();
  112 +
  113 + udelay(200);
  114 +
  115 + /* enable DDR controller */
  116 + im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
  117 + SDRAM_CFG_SREN |
  118 + SDRAM_CFG_SDRAM_TYPE_DDR);
  119 + SYNC;
  120 +
  121 + /* size detection */
  122 + debug("\n");
  123 + size = 0;
  124 + for(cs = 0; cs < 4; ++cs) {
  125 + debug("\nDetecting Bank%d\n", cs);
  126 +
  127 + bank_size = get_ddr_bank_size(cs,
  128 + (volatile long*)(CFG_DDR_BASE + size));
  129 + size += bank_size;
  130 +
  131 + debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20);
  132 +
  133 + /* exit if less than one bank */
  134 + if(size < DDR_MAX_SIZE_PER_CS) break;
  135 + }
  136 +
  137 + return size;
  138 +}
  139 +
  140 +/**************************************************************************
  141 + * checkboard()
  142 + */
  143 +int checkboard (void)
  144 +{
  145 + puts("Board: TQM834x\n");
  146 +
  147 +#ifdef CONFIG_PCI
  148 + printf("PCI1: 32 bit, %d MHz (compiled)\n",
  149 + CONFIG_SYS_CLK_FREQ / 1000000);
  150 +#else
  151 + printf("PCI1: disabled\n");
  152 +#endif
  153 +
  154 + return 0;
  155 +}
  156 +
  157 +#if defined(CONFIG_PCI)
  158 +/*
  159 + * Initialize PCI Devices, report devices found
  160 + */
  161 +
  162 +/* FIXME: No PCI support */
  163 +
  164 +#endif /* CONFIG_PCI */
  165 +
  166 +/**************************************************************************
  167 + * pci_init_board()
  168 + */
  169 +void
  170 +pci_init_board(void)
  171 +{
  172 +#ifdef CONFIG_PCI
  173 + extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
  174 +
  175 + pci_mpc83xx_init(hose);
  176 +#endif /* CONFIG_PCI */
  177 +}
  178 +
  179 +/**************************************************************************
  180 + *
  181 + * Local functions
  182 + *
  183 + *************************************************************************/
  184 +
  185 +/**************************************************************************
  186 + * Detect the number of flash banks (1 or 2). Store it in
  187 + * a global variable tqm834x_num_flash_banks.
  188 + * Bank detection code based on the Monitor code.
  189 + */
  190 +static int detect_num_flash_banks(void)
  191 +{
  192 + typedef unsigned long FLASH_PORT_WIDTH;
  193 + typedef volatile unsigned long FLASH_PORT_WIDTHV;
  194 + FPWV *bank1_base;
  195 + FPWV *bank2_base;
  196 + FPW bank1_read;
  197 + FPW bank2_read;
  198 + ulong bank1_size;
  199 + ulong bank2_size;
  200 + ulong total_size;
  201 +
  202 + tqm834x_num_flash_banks = 2; /* assume two banks */
  203 +
  204 + /* Get bank 1 and 2 information */
  205 + bank1_size = flash_get_size(CFG_FLASH_BASE, 0);
  206 + debug("Bank1 size: %lu\n", bank1_size);
  207 + bank2_size = flash_get_size(CFG_FLASH_BASE + bank1_size, 1);
  208 + debug("Bank2 size: %lu\n", bank2_size);
  209 + total_size = bank1_size + bank2_size;
  210 +
  211 + if (bank2_size > 0) {
  212 + /* Seems like we've got bank 2, but maybe it's mirrored 1 */
  213 +
  214 + /* Set the base addresses */
  215 + bank1_base = (FPWV *) (CFG_FLASH_BASE);
  216 + bank2_base = (FPWV *) (CFG_FLASH_BASE + bank1_size);
  217 +
  218 + /* Put bank 2 into CFI command mode and read */
  219 + bank2_base[0x55] = 0x00980098;
  220 + IOSYNC;
  221 + ISYNC;
  222 + bank2_read = bank2_base[0x10];
  223 +
  224 + /* Read from bank 1 (it's in read mode) */
  225 + bank1_read = bank1_base[0x10];
  226 +
  227 + /* Reset Flash */
  228 + bank1_base[0] = 0x00F000F0;
  229 + bank2_base[0] = 0x00F000F0;
  230 +
  231 + if (bank2_read == bank1_read) {
  232 + /*
  233 + * Looks like just one bank, but not sure yet. Let's
  234 + * read from bank 2 in autosoelect mode.
  235 + */
  236 + bank2_base[0x0555] = 0x00AA00AA;
  237 + bank2_base[0x02AA] = 0x00550055;
  238 + bank2_base[0x0555] = 0x00900090;
  239 + IOSYNC;
  240 + ISYNC;
  241 + bank2_read = bank2_base[0x10];
  242 +
  243 + /* Read from bank 1 (it's in read mode) */
  244 + bank1_read = bank1_base[0x10];
  245 +
  246 + /* Reset Flash */
  247 + bank1_base[0] = 0x00F000F0;
  248 + bank2_base[0] = 0x00F000F0;
  249 +
  250 + if (bank2_read == bank1_read) {
  251 + /*
  252 + * In both CFI command and autoselect modes,
  253 + * we got the some data reading from Flash.
  254 + * There is only one mirrored bank.
  255 + */
  256 + tqm834x_num_flash_banks = 1;
  257 + total_size = bank1_size;
  258 + }
  259 + }
  260 + }
  261 +
  262 + debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks);
  263 +
  264 + /* set OR0 and BR0 */
  265 + im->lbus.bank[0].or = CFG_OR_TIMING_FLASH |
  266 + (-(total_size) & OR_GPCM_AM);
  267 + im->lbus.bank[0].br = (CFG_FLASH_BASE & BR_BA) |
  268 + (BR_MS_GPCM | BR_PS_32 | BR_V);
  269 +
  270 + return (0);
  271 +}
  272 +
  273 +/*************************************************************************
  274 + * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
  275 + */
  276 +static long int get_ddr_bank_size(short cs, volatile long *base)
  277 +{
  278 + /* This array lists all valid DDR SDRAM configurations, with
  279 + * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
  280 + * The last entry has to to have size equal 0 and is igonred during
  281 + * autodection. Bank sizes must be in increasing order of size
  282 + */
  283 + struct {
  284 + long row;
  285 + long col;
  286 + long size;
  287 + } conf[] = {
  288 + {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_8, 32 << 20},
  289 + {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_9, 64 << 20},
  290 + {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_10, 128 << 20},
  291 + {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_9, 128 << 20},
  292 + {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_10, 256 << 20},
  293 + {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_11, 512 << 20},
  294 + {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_10, 512 << 20},
  295 + {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_11, 1024 << 20},
  296 + {0, 0, 0}
  297 + };
  298 +
  299 + int i;
  300 + int detected;
  301 + long size;
  302 +
  303 + detected = -1;
  304 + for(i = 0; conf[i].size != 0; ++i) {
  305 +
  306 + /* set sdram bank configuration */
  307 + set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row);
  308 +
  309 + debug("Getting RAM size...\n");
  310 + size = get_ram_size(base, DDR_MAX_SIZE_PER_CS);
  311 +
  312 + if((size == conf[i].size) && (i == detected + 1))
  313 + detected = i;
  314 +
  315 + debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n",
  316 + conf[i].row,
  317 + conf[i].col,
  318 + conf[i].size >> 20,
  319 + base,
  320 + size >> 20);
  321 + }
  322 +
  323 + if(detected == -1){
  324 + /* disable empty cs */
  325 + debug("\nNo valid configurations for CS%d, disabling...\n", cs);
  326 + set_cs_config(cs, 0);
  327 + return 0;
  328 + }
  329 +
  330 + debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
  331 + conf[detected].row, conf[detected].col, conf[detected].size >> 20, base);
  332 +
  333 + /* configure cs ro detected params */
  334 + set_cs_config(cs, CSCONFIG_EN | conf[detected].row |
  335 + conf[detected].col);
  336 +
  337 + set_cs_bounds(cs, (long)base, conf[detected].size);
  338 +
  339 + return(conf[detected].size);
  340 +}
  341 +
  342 +/**************************************************************************
  343 + * Sets DDR bank CS bounds.
  344 + */
  345 +static void set_cs_bounds(short cs, long base, long size)
  346 +{
  347 + debug("Setting bounds %08x, %08x for cs %d\n", base, size, cs);
  348 + if(size == 0){
  349 + im->ddr.csbnds[cs].csbnds = 0x00000000;
  350 + } else {
  351 + im->ddr.csbnds[cs].csbnds =
  352 + ((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  353 + (((base + size - 1) >> CSBNDS_EA_SHIFT) &
  354 + CSBNDS_EA);
  355 + }
  356 + SYNC;
  357 +}
  358 +
  359 +/**************************************************************************
  360 + * Sets DDR banks CS configuration.
  361 + * config == 0x00000000 disables the CS.
  362 + */
  363 +static void set_cs_config(short cs, long config)
  364 +{
  365 + debug("Setting config %08x for cs %d\n", config, cs);
  366 + im->ddr.cs_config[cs] = config;
  367 + SYNC;
  368 +}
  369 +
  370 +/**************************************************************************
  371 + * Sets DDR clocks, timings and configuration.
  372 + */
  373 +static void set_ddr_config(void) {
  374 + /* clock control */
  375 + im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |
  376 + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
  377 + SYNC;
  378 +
  379 + /* timing configuration */
  380 + im->ddr.timing_cfg_1 =
  381 + (4 << TIMING_CFG1_PRETOACT_SHIFT) |
  382 + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) |
  383 + (4 << TIMING_CFG1_ACTTORW_SHIFT) |
  384 + (5 << TIMING_CFG1_REFREC_SHIFT) |
  385 + (3 << TIMING_CFG1_WRREC_SHIFT) |
  386 + (3 << TIMING_CFG1_ACTTOACT_SHIFT) |
  387 + (1 << TIMING_CFG1_WRTORD_SHIFT) |
  388 + (TIMING_CFG1_CASLAT & TIMING_CASLAT);
  389 +
  390 + im->ddr.timing_cfg_2 =
  391 + TIMING_CFG2_CPO_DEF |
  392 + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT);
  393 + SYNC;
  394 +
  395 + /* don't enable DDR controller yet */
  396 + im->ddr.sdram_cfg =
  397 + SDRAM_CFG_SREN |
  398 + SDRAM_CFG_SDRAM_TYPE_DDR;
  399 + SYNC;
  400 +
  401 + /* Set SDRAM mode */
  402 + im->ddr.sdram_mode =
  403 + ((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) <<
  404 + SDRAM_MODE_ESD_SHIFT) |
  405 + ((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) <<
  406 + SDRAM_MODE_SD_SHIFT) |
  407 + ((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) &
  408 + MODE_CASLAT);
  409 + SYNC;
  410 +
  411 + /* Set fast SDRAM refresh rate */
  412 + im->ddr.sdram_interval =
  413 + (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
  414 + (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);
  415 + SYNC;
  416 +}
board/tqm834x/u-boot.lds
Diff comments   View file @ e6f2e90
  1 +/*
  2 + * Copyright 2004 Freescale Semiconductor, Inc.
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +OUTPUT_ARCH(powerpc)
  24 +SECTIONS
  25 +{
  26 + /* Read-only sections, merged into text segment: */
  27 + . = + SIZEOF_HEADERS;
  28 + .interp : { *(.interp) }
  29 + .hash : { *(.hash) }
  30 + .dynsym : { *(.dynsym) }
  31 + .dynstr : { *(.dynstr) }
  32 + .rel.text : { *(.rel.text) }
  33 + .rela.text : { *(.rela.text) }
  34 + .rel.data : { *(.rel.data) }
  35 + .rela.data : { *(.rela.data) }
  36 + .rel.rodata : { *(.rel.rodata) }
  37 + .rela.rodata : { *(.rela.rodata) }
  38 + .rel.got : { *(.rel.got) }
  39 + .rela.got : { *(.rela.got) }
  40 + .rel.ctors : { *(.rel.ctors) }
  41 + .rela.ctors : { *(.rela.ctors) }
  42 + .rel.dtors : { *(.rel.dtors) }
  43 + .rela.dtors : { *(.rela.dtors) }
  44 + .rel.bss : { *(.rel.bss) }
  45 + .rela.bss : { *(.rela.bss) }
  46 + .rel.plt : { *(.rel.plt) }
  47 + .rela.plt : { *(.rela.plt) }
  48 + .init : { *(.init) }
  49 + .plt : { *(.plt) }
  50 + .text :
  51 + {
  52 + cpu/mpc83xx/start.o (.text)
  53 + *(.text)
  54 + *(.fixup)
  55 + *(.got1)
  56 + . = ALIGN(16);
  57 + *(.rodata)
  58 + *(.rodata1)
  59 + *(.rodata.str1.4)
  60 + }
  61 + .fini : { *(.fini) } =0
  62 + .ctors : { *(.ctors) }
  63 + .dtors : { *(.dtors) }
  64 +
  65 + /* Read-write section, merged into data segment: */
  66 + . = (. + 0x0FFF) & 0xFFFFF000;
  67 + _erotext = .;
  68 + PROVIDE (erotext = .);
  69 + .reloc :
  70 + {
  71 + *(.got)
  72 + _GOT2_TABLE_ = .;
  73 + *(.got2)
  74 + _FIXUP_TABLE_ = .;
  75 + *(.fixup)
  76 + }
  77 + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
  78 + __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
  79 +
  80 + .data :
  81 + {
  82 + *(.data)
  83 + *(.data1)
  84 + *(.sdata)
  85 + *(.sdata2)
  86 + *(.dynamic)
  87 + CONSTRUCTORS
  88 + }
  89 + _edata = .;
  90 + PROVIDE (edata = .);
  91 +
  92 + . = .;
  93 + __u_boot_cmd_start = .;
  94 + .u_boot_cmd : { *(.u_boot_cmd) }
  95 + __u_boot_cmd_end = .;
  96 +
  97 +
  98 + . = .;
  99 + __start___ex_table = .;
  100 + __ex_table : { *(__ex_table) }
  101 + __stop___ex_table = .;
  102 +
  103 + . = ALIGN(4096);
  104 + __init_begin = .;
  105 + .text.init : { *(.text.init) }
  106 + .data.init : { *(.data.init) }
  107 + . = ALIGN(4096);
  108 + __init_end = .;
  109 +
  110 + __bss_start = .;
  111 + .bss :
  112 + {
  113 + *(.sbss) *(.scommon)
  114 + *(.dynbss)
  115 + *(.bss)
  116 + *(COMMON)
  117 + }
  118 + _end = . ;
  119 + PROVIDE (end = .);
  120 +}
  121 +ENTRY(_start)
... ... @@ -84,7 +84,7 @@
84 84  
85 85 #if (CONFIG_COMMANDS & CFG_CMD_IMLS)
86 86 #include <flash.h>
87   -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  87 +extern flash_info_t flash_info[]; /* info for FLASH chips */
88 88 static int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
89 89 #endif
90 90  
... ... @@ -1082,7 +1082,7 @@
1082 1082 for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) {
1083 1083 if (info->flash_id == FLASH_UNKNOWN)
1084 1084 goto next_bank;
1085   - for (j=0; j<CFG_MAX_FLASH_SECT; ++j) {
  1085 + for (j=0; j<info->sector_count; ++j) {
1086 1086  
1087 1087 if (!(hdr=(image_header_t *)info->start[j]) ||
1088 1088 (ntohl(hdr->ih_magic) != IH_MAGIC))
... ... @@ -404,7 +404,11 @@
404 404 {
405 405 flash_info_t *info;
406 406 ulong bank;
  407 +#ifdef CFG_MAX_FLASH_BANKS_DETECT
  408 + int s_first[CFG_MAX_FLASH_BANKS_DETECT], s_last[CFG_MAX_FLASH_BANKS_DETECT];
  409 +#else
407 410 int s_first[CFG_MAX_FLASH_BANKS], s_last[CFG_MAX_FLASH_BANKS];
  411 +#endif
408 412 int erased = 0;
409 413 int planned;
410 414 int rcode = 0;
411 415  
... ... @@ -617,7 +621,11 @@
617 621 {
618 622 flash_info_t *info;
619 623 ulong bank;
  624 +#ifdef CFG_MAX_FLASH_BANKS_DETECT
  625 + int s_first[CFG_MAX_FLASH_BANKS_DETECT], s_last[CFG_MAX_FLASH_BANKS_DETECT];
  626 +#else
620 627 int s_first[CFG_MAX_FLASH_BANKS], s_last[CFG_MAX_FLASH_BANKS];
  628 +#endif
621 629 int protected, i;
622 630 int planned;
623 631 int rcode;
... ... @@ -316,7 +316,7 @@
316 316 {
317 317 #if (CONFIG_COMMANDS & CFG_CMD_FLASH)
318 318 /* info for FLASH chips */
319   - extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
  319 + extern flash_info_t flash_info[];
320 320 flash_info_t *flash;
321 321 int offset_aligned;
322 322 u32 end_offset;
... ... @@ -711,7 +711,7 @@
711 711 if (type == MTD_DEV_TYPE_NOR) {
712 712 #if (CONFIG_COMMANDS & CFG_CMD_FLASH)
713 713 if (num < CFG_MAX_FLASH_BANKS) {
714   - extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
  714 + extern flash_info_t flash_info[];
715 715 *size = flash_info[num].size;
716 716 return 0;
717 717 }
... ... @@ -91,7 +91,7 @@
91 91 * Look for any and all PHYs. Valid addresses are 0..31.
92 92 */
93 93 if (argc >= 3) {
94   - start = addr; end = addr + 1;
  94 + start = addrlo; end = addrhi + 1;
95 95 } else {
96 96 start = 0; end = 32;
97 97 }
... ... @@ -28,7 +28,7 @@
28 28  
29 29 #if !defined(CFG_NO_FLASH)
30 30  
31   -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  31 +extern flash_info_t flash_info[]; /* info for FLASH chips */
32 32  
33 33 /*-----------------------------------------------------------------------
34 34 * Functions
... ... @@ -50,7 +50,7 @@
50 50 return -1;
51 51 }
52 52  
53   - puts("CPU: MPC83xx, ");
  53 + puts("CPU: MPC83xx, ");
54 54 switch(pvr) {
55 55 case PVR_8349_REV10:
56 56 break;
... ... @@ -41,7 +41,7 @@
41 41 #include <i2c.h>
42 42 #include <asm/i2c.h>
43 43  
44   -#ifdef CONFIG_MPC8349ADS
  44 +#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
45 45 i2c_t * mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET);
46 46 #endif
47 47  
48 48  
... ... @@ -109,7 +109,9 @@
109 109  
110 110 return 0;
111 111 } while (get_timer (timeval) < I2C_TIMEOUT);
  112 +
112 113 debug("i2c_wait: timed out\n");
  114 + return -1;
113 115 }
114 116  
115 117 static __inline__ int
... ... @@ -35,7 +35,7 @@
35 35 #include <common.h>
36 36 #include <pci.h>
37 37  
38   -#ifdef CONFIG_MPC8349ADS
  38 +#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
39 39 #include <asm/i2c.h>
40 40 #endif
41 41  
... ... @@ -114,7 +114,7 @@
114 114 /*
115 115 * Assign PIB PMC slot to desired PCI bus
116 116 */
117   -#ifdef CONFIG_MPC8349ADS
  117 +#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
118 118 mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
119 119 i2c_init(CFG_I2C_SPEED,CFG_I2C_SLAVE);
120 120 #endif
... ... @@ -118,41 +118,50 @@
118 118 return -1;
119 119  
120 120 #ifndef CFG_HRCW_HIGH
121   -# error "CFG_HRCW_HIGH must be defined in include/configs/MCP83XXADS.h"
  121 +# error "CFG_HRCW_HIGH must be defined in board config file"
122 122 #endif /* CFG_HCWD_HIGH */
123 123  
124 124 #if (CFG_HRCW_HIGH & HRCWH_PCI_HOST)
  125 +
125 126 # ifndef CONFIG_83XX_CLKIN
126   -# error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in include/configs/MCP83XXADS.h"
  127 +# error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in board config file"
127 128 # endif /* CONFIG_83XX_CLKIN */
128 129 # ifdef CONFIG_83XX_PCICLK
129   -# warning "In PCI Host Mode, CONFIG_83XX_PCICLK in include/configs/MCP83XXADS.h is igonred."
  130 +# warning "In PCI Host Mode, CONFIG_83XX_PCICLK in board config file is igonred"
130 131 # endif /* CONFIG_83XX_PCICLK */
131   -/* PCI Host Mode */
  132 +
  133 + /* PCI Host Mode */
132 134 if (!(im->reset.rcwh & RCWH_PCIHOST)) {
133   - /* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is disabled */
134   - /* FIXME: findout if there is a way to issue some warning */
  135 + /* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH
  136 + * the im->reset.rcwhr PCI Host Mode is disabled
  137 + * FIXME: findout if there is a way to issue some warning */
135 138 return -2;
136 139 }
137 140 if (im->clk.spmr & SPMR_CKID) {
138   - pci_sync_in = CONFIG_83XX_CLKIN / 2; /* PCI Clock is half CONFIG_83XX_CLKIN */
  141 + /* PCI Clock is half CONFIG_83XX_CLKIN */
  142 + pci_sync_in = CONFIG_83XX_CLKIN / 2;
139 143 }
140 144 else {
141 145 pci_sync_in = CONFIG_83XX_CLKIN;
142 146 }
143   -#else
  147 +
  148 +#else /* (CFG_HRCW_HIGH & HRCWH_PCI_HOST) */
  149 +
144 150 # ifdef CONFIG_83XX_CLKIN
145   -# warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in include/configs/MCP83XXADS.h is igonred."
  151 +# warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in board config file is igonred"
146 152 # endif /* CONFIG_83XX_CLKIN */
147 153 # ifndef CONFIG_83XX_PCICLK
148   -# error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in include/configs/MCP83XXADS.h"
  154 +# error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in board config file"
149 155 # endif /* CONFIG_83XX_PCICLK */
150   -/* PCI Agent Mode */
  156 +
  157 + /* PCI Agent Mode */
151 158 if (im->reset.rcwh & RCWH_PCIHOST) {
152   - /* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is enabled */
  159 + /* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH
  160 + * the im->reset.rcwhr PCI Host Mode is enabled */
153 161 return -3;
154 162 }
155 163 pci_sync_in = CONFIG_83XX_PCICLK;
  164 +
156 165 #endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */
157 166  
158 167 /* we have up to date pci_sync_in */
159 168  
160 169  
... ... @@ -343,80 +352,15 @@
343 352 printf("Clock configuration:\n");
344 353 printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000);
345 354 printf(" Core: %4d MHz\n",gd->core_clk/1000000);
346   - printf(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
  355 + debug(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
347 356 printf(" Local Bus: %4d MHz\n",gd->lclk_clk/1000000);
348   - printf(" DDR: %4d MHz\n",gd->ddr_clk/1000000);
349   - printf(" I2C: %4d MHz\n",gd->i2c_clk/1000000);
350   - printf(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000);
351   - printf(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000);
352   - printf(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000);
353   - printf(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000);
  357 + debug(" DDR: %4d MHz\n",gd->ddr_clk/1000000);
  358 + debug(" I2C: %4d MHz\n",gd->i2c_clk/1000000);
  359 + debug(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000);
  360 + debug(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000);
  361 + debug(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000);
  362 + debug(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000);
354 363  
355   -#if 0
356   - DECLARE_GLOBAL_DATA_PTR;
357   -
358   - volatile immap_t *immap = (immap_t *) CFG_IMMR;
359   - ulong sccr, dfbrg;
360   - ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf;
361   - corecnf_t *cp;
362   -
363   - sccr = immap->im_clkrst.car_sccr;
364   - dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
365   -
366   - scmr = immap->im_clkrst.car_scmr;
367   - corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
368   - busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
369   - cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
370   - plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
371   - pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
372   -
373   - cp = &corecnf_tab[corecnf];
374   -
375   - puts (CPU_ID_STR " Clock Configuration\n - Bus-to-Core Mult ");
376   -
377   - switch (cp->b2c_mult) {
378   - case _byp:
379   - puts ("BYPASS");
380   - break;
381   -
382   - case _off:
383   - puts ("OFF");
384   - break;
385   -
386   - case _unk:
387   - puts ("UNKNOWN");
388   - break;
389   -
390   - default:
391   - printf ("%d%sx",
392   - cp->b2c_mult / 2,
393   - (cp->b2c_mult % 2) ? ".5" : "");
394   - break;
395   - }
396   -
397   - printf (", VCO Div %d, 60x Bus Freq %s, Core Freq %s\n",
398   - cp->vco_div, cp->freq_60x, cp->freq_core);
399   -
400   - printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, "
401   - "plldf %ld, pllmf %ld\n", dfbrg, corecnf, busdf, cpmdf, plldf,
402   - pllmf);
403   -
404   - printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
405   - gd->vco_out, gd->scc_clk, gd->brg_clk);
406   -
407   - printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n",
408   - gd->cpu_clk, gd->cpm_clk, gd->bus_clk);
409   -
410   - if (sccr & SCCR_PCI_MODE) {
411   - uint pci_div;
412   -
413   - pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
414   - ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
415   -
416   - printf (" - pci_clk %10ld\n", (gd->cpm_clk * 2) / pci_div);
417   - }
418   - putc ('\n');
419   -#endif
420 364 return 0;
421 365 }
... ... @@ -166,9 +166,15 @@
166 166  
167 167 #define NUM_ERASE_REGIONS 4
168 168  
  169 +/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
  170 +#ifdef CFG_MAX_FLASH_BANKS_DETECT
  171 +static ulong bank_base[CFG_MAX_FLASH_BANKS_DETECT] = CFG_FLASH_BANKS_LIST;
  172 +flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */
  173 +#else
169 174 static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
  175 +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* FLASH chips info */
  176 +#endif
170 177  
171   -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
172 178  
173 179 /*-----------------------------------------------------------------------
174 180 * Functions
... ... @@ -184,7 +190,7 @@
184 190 static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
185 191 static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
186 192 static int flash_detect_cfi (flash_info_t * info);
187   -static ulong flash_get_size (ulong base, int banknum);
  193 +ulong flash_get_size (ulong base, int banknum);
188 194 static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
189 195 static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
190 196 ulong tout, char *prompt);
... ... @@ -371,7 +377,7 @@
371 377 static flash_info_t *flash_get_info(ulong base)
372 378 {
373 379 int i;
374   - flash_info_t * info;
  380 + flash_info_t * info = 0;
375 381  
376 382 for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
377 383 info = & flash_info[i];
... ... @@ -1007,7 +1013,7 @@
1007 1013 * The following code cannot be run from FLASH!
1008 1014 *
1009 1015 */
1010   -static ulong flash_get_size (ulong base, int banknum)
  1016 +ulong flash_get_size (ulong base, int banknum)
1011 1017 {
1012 1018 flash_info_t *info = &flash_info[banknum];
1013 1019 int i, j;
... ... @@ -44,7 +44,7 @@
44 44  
45 45 /* CPU address space offset calculation macro, struct part_info offset is
46 46 * device address space offset, so we need to shift it by a device start address. */
47   -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
  47 +extern flash_info_t flash_info[];
48 48 #define PART_OFFSET(x) (x->offset + flash_info[x->dev->id->num].start[0])
49 49  
50 50 static int cramfs_read_super (struct part_info *info)
fs/jffs2/jffs2_1pass.c
Diff comments   View file @ e6f2e90
... ... @@ -263,7 +263,7 @@
263 263 u32 addr = off;
264 264 struct mtdids *id = current_part->dev->id;
265 265  
266   - extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
  266 + extern flash_info_t flash_info[];
267 267 flash_info_t *flash = &flash_info[id->num];
268 268  
269 269 addr += flash->start[0];
include/asm-ppc/i2c.h
Diff comments   View file @ e6f2e90
... ... @@ -87,7 +87,7 @@
87 87 #error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h
88 88 #endif
89 89  
90   -#ifdef CONFIG_MPC8349ADS
  90 +#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
91 91 /*
92 92 * MPC8349 have two i2c bus
93 93 */
include/asm-ppc/immap_83xx.h
Diff comments   View file @ e6f2e90
... ... @@ -613,9 +613,9 @@
613 613 typedef struct ddr_cs_bnds{
614 614 u32 csbnds;
615 615 #define CSBNDS_SA 0x00FF0000
616   -#define CSBNDS_SA_SHIFT 16
  616 +#define CSBNDS_SA_SHIFT 8
617 617 #define CSBNDS_EA 0x000000FF
618   -#define CSBNDS_EA_SHIFT 0
  618 +#define CSBNDS_EA_SHIFT 24
619 619 u8 res0[4];
620 620 } ddr_cs_bnds_t;
621 621  
... ... @@ -652,6 +652,8 @@
652 652 #define TIMING_CFG1_ACTTOACT_SHIFT 4
653 653 #define TIMING_CFG1_WRTORD 0x00000007
654 654 #define TIMING_CFG1_WRTORD_SHIFT 0
  655 +#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
  656 +#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
655 657  
656 658 u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */
657 659 #define TIMING_CFG2_CPO 0x0F000000
... ... @@ -659,6 +661,7 @@
659 661 #define TIMING_CFG2_ACSM 0x00080000
660 662 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
661 663 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
  664 +#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */
662 665  
663 666 u32 sdram_cfg; /**< SDRAM Control Configuration */
664 667 #define SDRAM_CFG_MEM_EN 0x80000000
... ... @@ -672,6 +675,7 @@
672 675 #define SDRAM_CFG_8_BE 0x00040000
673 676 #define SDRAM_CFG_NCAP 0x00020000
674 677 #define SDRAM_CFG_2T_EN 0x00008000
  678 +#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
675 679  
676 680 u8 res2[4];
677 681 u32 sdram_mode; /**< SDRAM Mode Configuration */
... ... @@ -679,6 +683,25 @@
679 683 #define SDRAM_MODE_ESD_SHIFT 16
680 684 #define SDRAM_MODE_SD 0x0000FFFF
681 685 #define SDRAM_MODE_SD_SHIFT 0
  686 +#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */
  687 +#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */
  688 +#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
  689 +#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */
  690 +#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */
  691 +#define DDR_MODE_WEAK 0x0002 /* weak drivers */
  692 +#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */
  693 +#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */
  694 +#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
  695 +#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
  696 +#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
  697 +#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
  698 +#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */
  699 +#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */
  700 +#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
  701 +#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
  702 +#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125 ยตs */
  703 +#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */
  704 +#define DDR_MODE_MODEREG 0x0000 /* select mode register */
682 705  
683 706 u8 res3[8];
684 707 u32 sdram_interval; /**< SDRAM Interval Configuration */
... ... @@ -688,6 +711,9 @@
688 711 #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
689 712 u8 res9[8];
690 713 u32 sdram_clk_cntl;
  714 +#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
  715 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
  716 +
691 717 u8 res4[0xCCC];
692 718 u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
693 719 u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
include/configs/TQM834x.h
Diff comments   View file @ e6f2e90
  1 +/*
  2 + * (C) Copyright 2005
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +/*
  25 + * TQM8349 board configuration file
  26 + */
  27 +
  28 +#ifndef __CONFIG_H
  29 +#define __CONFIG_H
  30 +
  31 +#define DEBUG
  32 +#undef DEBUG
  33 +
  34 +/*
  35 + * High Level Configuration Options
  36 + */
  37 +#define CONFIG_E300 1 /* E300 Family */
  38 +#define CONFIG_MPC83XX 1 /* MPC83XX family */
  39 +#define CONFIG_MPC834X 1 /* MPC834X specific */
  40 +#define CONFIG_TQM834X 1 /* TQM834X board specific */
  41 +
  42 +/* IMMR Base Addres Register, use Freescale default: 0xff400000 */
  43 +#define CFG_IMMRBAR IMMRBAR_BASE_ADDR
  44 +
  45 +/* System clock. Primary input clock when in PCI host mode */
  46 +#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
  47 +
  48 +/*
  49 + * Local Bus LCRR
  50 + * LCRR: DLL bypass, Clock divider is 8
  51 + *
  52 + * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
  53 + *
  54 + * External Local Bus rate is
  55 + * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  56 + */
  57 +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
  58 +
  59 +/* board pre init: do not call, nothing to do */
  60 +#undef CONFIG_BOARD_EARLY_INIT_F
  61 +
  62 +/* detect the number of flash banks */
  63 +#define CONFIG_BOARD_EARLY_INIT_R
  64 +
  65 +/*
  66 + * DDR Setup
  67 + */
  68 +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
  69 +#define CFG_SDRAM_BASE CFG_DDR_BASE
  70 +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
  71 +#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
  72 +#undef CONFIG_DDR_ECC /* only for ECC DDR module */
  73 +#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
  74 +
  75 +#undef CFG_DRAM_TEST /* memory test, takes time */
  76 +#define CFG_MEMTEST_START 0x00000000 /* memtest region */
  77 +#define CFG_MEMTEST_END 0x00100000
  78 +
  79 +/*
  80 + * FLASH on the Local Bus
  81 + */
  82 +#define CFG_FLASH_CFI /* use the Common Flash Interface */
  83 +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
  84 +#undef CFG_FLASH_CHECKSUM
  85 +#define CFG_FLASH_BASE 0x80000000 /* start of FLASH */
  86 +
  87 +/* buffered writes in the AMD chip set is not supported yet */
  88 +#undef CFG_FLASH_USE_BUFFER_WRITE
  89 +
  90 +/*
  91 + * FLASH bank number detection
  92 + */
  93 +
  94 +/*
  95 + * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
  96 + * banks has to be determined at runtime and stored in a gloabl variable
  97 + * tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only
  98 + * used insted of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and
  99 + * should be made sufficiently large to accomodate the number of banks that
  100 + * might acutally be detected. Since most (all?) Flash related functions use
  101 + * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is
  102 + * defined as tqm834x_num_flash_banks.
  103 + */
  104 +#define CFG_MAX_FLASH_BANKS_DETECT 2
  105 +#ifndef __ASSEMBLY__
  106 +extern int tqm834x_num_flash_banks;
  107 +#endif
  108 +#define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks)
  109 +
  110 +#define CFG_MAX_FLASH_SECT 512 /* max sectors per device */
  111 +
  112 +/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
  113 +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA) | \
  114 + BR_MS_GPCM | BR_PS_32 | BR_V)
  115 +
  116 +/* FLASH timing (0x0000_0c54) */
  117 +#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \
  118 + OR_GPCM_SCY_5 | OR_GPCM_TRLX)
  119 +
  120 +#define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */
  121 +
  122 +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
  123 +
  124 +#define CFG_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */
  125 +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
  126 +
  127 +/* disable remaining mappings */
  128 +#define CFG_BR1_PRELIM 0x00000000
  129 +#define CFG_OR1_PRELIM 0x00000000
  130 +#define CFG_LBLAWBAR1_PRELIM 0x00000000
  131 +#define CFG_LBLAWAR1_PRELIM 0x00000000
  132 +
  133 +#define CFG_BR2_PRELIM 0x00000000
  134 +#define CFG_OR2_PRELIM 0x00000000
  135 +#define CFG_LBLAWBAR2_PRELIM 0x00000000
  136 +#define CFG_LBLAWAR2_PRELIM 0x00000000
  137 +
  138 +#define CFG_BR3_PRELIM 0x00000000
  139 +#define CFG_OR3_PRELIM 0x00000000
  140 +#define CFG_LBLAWBAR3_PRELIM 0x00000000
  141 +#define CFG_LBLAWAR3_PRELIM 0x00000000
  142 +
  143 +#define CFG_BR4_PRELIM 0x00000000
  144 +#define CFG_OR4_PRELIM 0x00000000
  145 +#define CFG_LBLAWBAR4_PRELIM 0x00000000
  146 +#define CFG_LBLAWAR4_PRELIM 0x00000000
  147 +
  148 +#define CFG_BR5_PRELIM 0x00000000
  149 +#define CFG_OR5_PRELIM 0x00000000
  150 +#define CFG_LBLAWBAR5_PRELIM 0x00000000
  151 +#define CFG_LBLAWAR5_PRELIM 0x00000000
  152 +
  153 +#define CFG_BR6_PRELIM 0x00000000
  154 +#define CFG_OR6_PRELIM 0x00000000
  155 +#define CFG_LBLAWBAR6_PRELIM 0x00000000
  156 +#define CFG_LBLAWAR6_PRELIM 0x00000000
  157 +
  158 +#define CFG_BR7_PRELIM 0x00000000
  159 +#define CFG_OR7_PRELIM 0x00000000
  160 +#define CFG_LBLAWBAR7_PRELIM 0x00000000
  161 +#define CFG_LBLAWAR7_PRELIM 0x00000000
  162 +
  163 +/*
  164 + * Monitor config
  165 + */
  166 +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
  167 +
  168 +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
  169 +#define CFG_RAMBOOT
  170 +#else
  171 +#undef CFG_RAMBOOT
  172 +#endif
  173 +
  174 +#define CONFIG_L1_INIT_RAM
  175 +#define CFG_INIT_RAM_LOCK 1
  176 +#define CFG_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
  177 +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
  178 +
  179 +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
  180 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  181 +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  182 +
  183 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  184 +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  185 +
  186 +/*
  187 + * Serial Port
  188 + */
  189 +#define CONFIG_CONS_INDEX 1
  190 +#undef CONFIG_SERIAL_SOFTWARE_FIFO
  191 +#define CFG_NS16550
  192 +#define CFG_NS16550_SERIAL
  193 +#define CFG_NS16550_REG_SIZE 1
  194 +#define CFG_NS16550_CLK get_bus_freq(0)
  195 +
  196 +#define CFG_BAUDRATE_TABLE \
  197 + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  198 +
  199 +#define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500)
  200 +#define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600)
  201 +
  202 +/*
  203 + * I2C
  204 + */
  205 +#define CONFIG_HARD_I2C /* I2C with hardware support */
  206 +#undef CONFIG_SOFT_I2C /* I2C bit-banged */
  207 +#define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */
  208 +#define CFG_I2C_SLAVE 0x7F /* slave address */
  209 +#define CFG_I2C_OFFSET 0x3000
  210 +
  211 +/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
  212 +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
  213 +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
  214 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */
  215 +#define CFG_EEPROM_PAGE_WRITE_ENABLE
  216 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
  217 +#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
  218 +
  219 +/* I2C RTC */
  220 +#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
  221 +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  222 +
  223 +/* I2C SYSMON (LM75) */
  224 +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
  225 +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
  226 +#define CFG_DTT_MAX_TEMP 70
  227 +#define CFG_DTT_LOW_TEMP -30
  228 +#define CFG_DTT_HYSTERESIS 3
  229 +
  230 +/*
  231 + * TSEC
  232 + */
  233 +#define CONFIG_TSEC_ENET /* tsec ethernet support */
  234 +#define CONFIG_MII
  235 +
  236 +#define CFG_TSEC1_OFFSET 0x24000
  237 +#define CFG_TSEC1 (CFG_IMMRBAR + CFG_TSEC1_OFFSET)
  238 +#define CFG_TSEC2_OFFSET 0x25000
  239 +#define CFG_TSEC2 (CFG_IMMRBAR + CFG_TSEC2_OFFSET)
  240 +
  241 +#if defined(CONFIG_TSEC_ENET)
  242 +
  243 +#ifndef CONFIG_NET_MULTI
  244 +#define CONFIG_NET_MULTI 1
  245 +#endif
  246 +
  247 +#define CONFIG_MPC83XX_TSEC1 1
  248 +#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
  249 +#define CONFIG_MPC83XX_TSEC2 1
  250 +#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
  251 +#define TSEC1_PHY_ADDR 0
  252 +#define TSEC2_PHY_ADDR 1
  253 +#define TSEC1_PHYIDX 0
  254 +#define TSEC2_PHYIDX 0
  255 +
  256 +/* Options are: TSEC[0-1] */
  257 +#define CONFIG_ETHPRIME "TSEC0"
  258 +
  259 +#endif /* CONFIG_TSEC_ENET */
  260 +
  261 +/*
  262 + * General PCI
  263 + * Addresses are mapped 1-1.
  264 + */
  265 +/* FIXME: Real PCI support will come in a follow-up update. */
  266 +#undef CONFIG_PCI
  267 +
  268 +#define CFG_PCI1_MEM_BASE 0x80000000
  269 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
  270 +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
  271 +#define CFG_PCI1_IO_BASE 0x00000000
  272 +#define CFG_PCI1_IO_PHYS 0xe2000000
  273 +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
  274 +
  275 +#define CFG_PCI2_MEM_BASE 0xA0000000
  276 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
  277 +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
  278 +#define CFG_PCI2_IO_BASE 0x00000000
  279 +#define CFG_PCI2_IO_PHYS 0xe3000000
  280 +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
  281 +#if defined(CONFIG_PCI)
  282 +
  283 +#define PCI_ALL_PCI1
  284 +#if defined(PCI_64BIT)
  285 +#undef PCI_ALL_PCI1
  286 +#undef PCI_TWO_PCI1
  287 +#undef PCI_ONE_PCI1
  288 +#endif
  289 +
  290 +#define CONFIG_NET_MULTI
  291 +#define CONFIG_PCI_PNP /* do pci plug-and-play */
  292 +
  293 +#undef CONFIG_EEPRO100
  294 +#undef CONFIG_TULIP
  295 +
  296 +#if !defined(CONFIG_PCI_PNP)
  297 + #define PCI_ENET0_IOADDR 0xFIXME
  298 + #define PCI_ENET0_MEMADDR 0xFIXME
  299 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
  300 +#endif
  301 +
  302 +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  303 +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  304 +
  305 +#endif /* CONFIG_PCI */
  306 +
  307 +/*
  308 + * Environment
  309 + */
  310 +#define CONFIG_ENV_OVERWRITE
  311 +
  312 +#ifndef CFG_RAMBOOT
  313 + #define CFG_ENV_IS_IN_FLASH 1
  314 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
  315 + #define CFG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */
  316 + #define CFG_ENV_SIZE 0x2000
  317 +#else
  318 + #define CFG_NO_FLASH 1 /* Flash is not usable now */
  319 + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
  320 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
  321 + #define CFG_ENV_SIZE 0x2000
  322 +#endif
  323 +
  324 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  325 +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  326 +
  327 +/* Common commands */
  328 +#define CFG_CMD_TQM8349_COMMON CFG_CMD_DATE | CFG_CMD_I2C | CFG_CMD_DTT\
  329 + | CFG_CMD_PING | CFG_CMD_EEPROM \
  330 + | CFG_CMD_MII | CFG_CMD_JFFS2
  331 +
  332 +#if defined(CFG_RAMBOOT)
  333 +
  334 +#if defined(CONFIG_PCI)
  335 +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI \
  336 + | CFG_CMD_TQM8349_COMMON) \
  337 + & \
  338 + ~(CFG_CMD_ENV | CFG_CMD_LOADS))
  339 +#else
  340 +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
  341 + | CFG_CMD_TQM8349_COMMON) \
  342 + & \
  343 + ~(CFG_CMD_ENV | CFG_CMD_LOADS))
  344 +#endif
  345 +
  346 +#else /* CFG_RAMBOOT */
  347 +
  348 +#if defined(CONFIG_PCI)
  349 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \
  350 + | CFG_CMD_TQM8349_COMMON)
  351 +#else
  352 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
  353 + | CFG_CMD_TQM8349_COMMON)
  354 +#endif
  355 +
  356 +#endif /* CFG_RAMBOOT */
  357 +
  358 +#include <cmd_confdefs.h>
  359 +
  360 +/*
  361 + * Miscellaneous configurable options
  362 + */
  363 +#define CFG_LONGHELP /* undef to save memory */
  364 +#define CFG_LOAD_ADDR 0x2000000 /* default load address */
  365 +#define CFG_PROMPT "=> " /* Monitor Command Prompt */
  366 +
  367 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  368 + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  369 +#else
  370 + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  371 +#endif
  372 +
  373 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  374 +#define CFG_MAXARGS 16 /* max number of command args */
  375 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  376 +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
  377 +
  378 +#undef CONFIG_WATCHDOG /* watchdog disabled */
  379 +
  380 +/*
  381 + * For booting Linux, the board info and command line data
  382 + * have to be in the first 8 MB of memory, since this is
  383 + * the maximum mapped by the Linux kernel during initialization.
  384 + */
  385 +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
  386 +
  387 +/*
  388 + * Cache Configuration
  389 + */
  390 +#define CFG_DCACHE_SIZE 32768
  391 +#define CFG_CACHELINE_SIZE 32
  392 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  393 +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
  394 +#endif
  395 +
  396 +#define CFG_HRCW_LOW (\
  397 + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  398 + HRCWL_DDR_TO_SCB_CLK_1X1 |\
  399 + HRCWL_CSB_TO_CLKIN_4X1 |\
  400 + HRCWL_VCO_1X2 |\
  401 + HRCWL_CORE_TO_CSB_2X1)
  402 +
  403 +#if defined(PCI_64BIT)
  404 +#define CFG_HRCW_HIGH (\
  405 + HRCWH_PCI_HOST |\
  406 + HRCWH_64_BIT_PCI |\
  407 + HRCWH_PCI1_ARBITER_ENABLE |\
  408 + HRCWH_PCI2_ARBITER_DISABLE |\
  409 + HRCWH_CORE_ENABLE |\
  410 + HRCWH_FROM_0X00000100 |\
  411 + HRCWH_BOOTSEQ_DISABLE |\
  412 + HRCWH_SW_WATCHDOG_DISABLE |\
  413 + HRCWH_ROM_LOC_LOCAL_16BIT |\
  414 + HRCWH_TSEC1M_IN_GMII |\
  415 + HRCWH_TSEC2M_IN_GMII )
  416 +#else
  417 +#define CFG_HRCW_HIGH (\
  418 + HRCWH_PCI_HOST |\
  419 + HRCWH_32_BIT_PCI |\
  420 + HRCWH_PCI1_ARBITER_ENABLE |\
  421 + HRCWH_PCI2_ARBITER_ENABLE |\
  422 + HRCWH_CORE_ENABLE |\
  423 + HRCWH_FROM_0X00000100 |\
  424 + HRCWH_BOOTSEQ_DISABLE |\
  425 + HRCWH_SW_WATCHDOG_DISABLE |\
  426 + HRCWH_ROM_LOC_LOCAL_16BIT |\
  427 + HRCWH_TSEC1M_IN_GMII |\
  428 + HRCWH_TSEC2M_IN_GMII )
  429 +#endif
  430 +
  431 +/* i-cache and d-cache disabled */
  432 +#define CFG_HID0_INIT 0x000000000
  433 +#define CFG_HID0_FINAL CFG_HID0_INIT
  434 +#define CFG_HID2 0x000000000
  435 +
  436 +/*
  437 + * Internal Definitions
  438 + *
  439 + * Boot Flags
  440 + */
  441 +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  442 +#define BOOTFLAG_WARM 0x02 /* Software reboot */
  443 +
  444 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  445 +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  446 +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  447 +#endif
  448 +
  449 +/*
  450 + * Environment Configuration
  451 + */
  452 +
  453 +#if defined(CONFIG_TSEC_ENET)
  454 +#define CONFIG_ETHADDR D2:DA:5E:44:BC:29
  455 +#define CONFIG_HAS_ETH1
  456 +#define CONFIG_ETH1ADDR 1E:F3:40:21:92:53
  457 +#endif
  458 +
  459 +#define CONFIG_IPADDR 192.168.205.1
  460 +
  461 +#define CONFIG_HOSTNAME tqm8349
  462 +#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
  463 +#define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage
  464 +
  465 +#define CONFIG_SERVERIP 192.168.1.1
  466 +#define CONFIG_GATEWAYIP 192.168.1.1
  467 +#define CONFIG_NETMASK 255.255.255.0
  468 +
  469 +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
  470 +
  471 +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
  472 +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
  473 +
  474 +#define CONFIG_BAUDRATE 115200
  475 +
  476 +#define CONFIG_PREBOOT "echo;" \
  477 + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
  478 + "echo"
  479 +
  480 +#undef CONFIG_BOOTARGS
  481 +
  482 +#define CONFIG_EXTRA_ENV_SETTINGS \
  483 + "netdev=eth0\0" \
  484 + "hostname=tqm83xx\0" \
  485 + "nfsargs=setenv bootargs root=/dev/nfs rw " \
  486 + "nfsroot=$(serverip):$(rootpath)\0" \
  487 + "ramargs=setenv bootargs root=/dev/ram rw\0" \
  488 + "addip=setenv bootargs $(bootargs) " \
  489 + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
  490 + ":$(hostname):$(netdev):off panic=1\0" \
  491 + "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
  492 + "flash_nfs=run nfsargs addip addtty;" \
  493 + "bootm $(kernel_addr)\0" \
  494 + "flash_self=run ramargs addip addtty;" \
  495 + "bootm $(kernel_addr) $(ramdisk_addr)\0" \
  496 + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
  497 + "bootm\0" \
  498 + "rootpath=/opt/eldk/ppc_6xx\0" \
  499 + "bootfile=/tftpboot/tqm83xx/uImage\0" \
  500 + "kernel_addr=80060000\0" \
  501 + "ramdisk_addr=80160000\0" \
  502 + "load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0" \
  503 + "update=protect off 80000000 8003ffff; " \
  504 + "era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \
  505 + "upd=run load;run update\0" \
  506 + ""
  507 +
  508 +#define CONFIG_BOOTCOMMAND "run flash_self"
  509 +
  510 +/*
  511 + * JFFS2 partitions
  512 + */
  513 +/* mtdparts command line support */
  514 +#define CONFIG_JFFS2_CMDLINE
  515 +#define MTDIDS_DEFAULT "nor0=TQM834x-0"
  516 +
  517 +/* default mtd partition table */
  518 +#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),128k(env),"\
  519 + "1m(kernel),2m(initrd),"\
  520 + "-(user);"\
  521 +
  522 +#endif /* __CONFIG_H */
... ... @@ -98,19 +98,27 @@
98 98 #define BR6 0x5030
99 99 #define BR7 0x5038
100 100  
101   -#define BR_BA 0xFFFF8000
102   -#define BR_BA_SHIFT 15
103   -#define BR_PS 0x00001800
104   -#define BR_PS_SHIFT 11
105   -#define BR_DECC 0x00000600
106   -#define BR_DECC_SHIFT 9
107   -#define BR_WP 0x00000100
108   -#define BR_WP_SHIFT 8
109   -#define BR_MSEL 0x000000E0
110   -#define BR_MSEL_SHIFT 5
111   -#define BR_V 0x00000001
112   -#define BR_V_SHIFT 0
113   -#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
  101 +#define BR_BA 0xFFFF8000
  102 +#define BR_BA_SHIFT 15
  103 +#define BR_PS 0x00001800
  104 +#define BR_PS_SHIFT 11
  105 +#define BR_PS_8 0x00000800 /* Port Size 8 bit */
  106 +#define BR_PS_16 0x00001000 /* Port Size 16 bit */
  107 +#define BR_PS_32 0x00001800 /* Port Size 32 bit */
  108 +#define BR_DECC 0x00000600
  109 +#define BR_DECC_SHIFT 9
  110 +#define BR_WP 0x00000100
  111 +#define BR_WP_SHIFT 8
  112 +#define BR_MSEL 0x000000E0
  113 +#define BR_MSEL_SHIFT 5
  114 +#define BR_MS_GPCM 0x00000000 /* GPCM */
  115 +#define BR_MS_SDRAM 0x00000060 /* SDRAM */
  116 +#define BR_MS_UPMA 0x00000080 /* UPMA */
  117 +#define BR_MS_UPMB 0x000000A0 /* UPMB */
  118 +#define BR_MS_UPMC 0x000000C0 /* UPMC */
  119 +#define BR_V 0x00000001
  120 +#define BR_V_SHIFT 0
  121 +#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
114 122  
115 123 #define OR0 0x5004
116 124 #define OR1 0x500C
... ... @@ -121,26 +129,43 @@
121 129 #define OR6 0x5034
122 130 #define OR7 0x503C
123 131  
124   -#define OR_GPCM_AM 0xFFFF8000
125   -#define OR_GPCM_AM_SHIFT 15
126   -#define OR_GPCM_BCTLD 0x00001000
127   -#define OR_GPCM_BCTLD_SHIFT 12
128   -#define OR_GPCM_CSNT 0x00000800
129   -#define OR_GPCM_CSNT_SHIFT 11
130   -#define OR_GPCM_ACS 0x00000600
131   -#define OR_GPCM_ACS_SHIFT 9
132   -#define OR_GPCM_XACS 0x00000100
133   -#define OR_GPCM_XACS_SHIFT 8
134   -#define OR_GPCM_SCY 0x000000F0
135   -#define OR_GPCM_SCY_SHIFT 4
136   -#define OR_GPCM_SETA 0x00000008
137   -#define OR_GPCM_SETA_SHIFT 3
138   -#define OR_GPCM_TRLX 0x00000004
139   -#define OR_GPCM_TRLX_SHIFT 2
140   -#define OR_GPCM_EHTR 0x00000002
141   -#define OR_GPCM_EHTR_SHIFT 1
142   -#define OR_GPCM_EAD 0x00000001
143   -#define OR_GPCM_EAD_SHIFT 0
  132 +#define OR_GPCM_AM 0xFFFF8000
  133 +#define OR_GPCM_AM_SHIFT 15
  134 +#define OR_GPCM_BCTLD 0x00001000
  135 +#define OR_GPCM_BCTLD_SHIFT 12
  136 +#define OR_GPCM_CSNT 0x00000800
  137 +#define OR_GPCM_CSNT_SHIFT 11
  138 +#define OR_GPCM_ACS 0x00000600
  139 +#define OR_GPCM_ACS_SHIFT 9
  140 +#define OR_GPCM_ACS_0b10 0x00000400
  141 +#define OR_GPCM_ACS_0b11 0x00000600
  142 +#define OR_GPCM_XACS 0x00000100
  143 +#define OR_GPCM_XACS_SHIFT 8
  144 +#define OR_GPCM_SCY 0x000000F0
  145 +#define OR_GPCM_SCY_SHIFT 4
  146 +#define OR_GPCM_SCY_1 0x00000010
  147 +#define OR_GPCM_SCY_2 0x00000020
  148 +#define OR_GPCM_SCY_3 0x00000030
  149 +#define OR_GPCM_SCY_4 0x00000040
  150 +#define OR_GPCM_SCY_5 0x00000050
  151 +#define OR_GPCM_SCY_6 0x00000060
  152 +#define OR_GPCM_SCY_7 0x00000070
  153 +#define OR_GPCM_SCY_8 0x00000080
  154 +#define OR_GPCM_SCY_9 0x00000090
  155 +#define OR_GPCM_SCY_10 0x000000a0
  156 +#define OR_GPCM_SCY_11 0x000000b0
  157 +#define OR_GPCM_SCY_12 0x000000c0
  158 +#define OR_GPCM_SCY_13 0x000000d0
  159 +#define OR_GPCM_SCY_14 0x000000e0
  160 +#define OR_GPCM_SCY_15 0x000000f0
  161 +#define OR_GPCM_SETA 0x00000008
  162 +#define OR_GPCM_SETA_SHIFT 3
  163 +#define OR_GPCM_TRLX 0x00000004
  164 +#define OR_GPCM_TRLX_SHIFT 2
  165 +#define OR_GPCM_EHTR 0x00000002
  166 +#define OR_GPCM_EHTR_SHIFT 1
  167 +#define OR_GPCM_EAD 0x00000001
  168 +#define OR_GPCM_EAD_SHIFT 0
144 169  
145 170 #define OR_UPM_AM 0xFFFF8000
146 171 #define OR_UPM_AM_SHIFT 15
... ... @@ -58,7 +58,7 @@
58 58 static char *tftp_filename;
59 59  
60 60 #ifdef CFG_DIRECT_FLASH_TFTP
61   -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
  61 +extern flash_info_t flash_info[];
62 62 #endif
63 63  
64 64 static __inline__ void
tools/updater/flash.c
Diff comments   View file @ e6f2e90
... ... @@ -24,7 +24,7 @@
24 24 #include <common.h>
25 25 #include <flash.h>
26 26  
27   -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  27 +extern flash_info_t flash_info[]; /* info for FLASH chips */
28 28  
29 29 /*-----------------------------------------------------------------------
30 30 * Functions
tools/updater/flash_hw.c
Diff comments   View file @ e6f2e90
... ... @@ -39,7 +39,7 @@
39 39 #endif
40 40 /*---------------------------------------------------------------------*/
41 41  
42   -flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
  42 +flash_info_t flash_info[];
43 43  
44 44 static ulong flash_get_size (ulong addr, flash_info_t *info);
45 45 static int flash_get_offsets (ulong base, flash_info_t *info);