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Commit e6f61622d32327907f824154c7f88ddce3c700cc

Authored by Chris Packham
Committed by Stefan Roese
1 parent 2b4ffbf6b4
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

ARM: mvebu: a38x: restore support for setting timing 

This restores support for configuring the timing mode based on the
ddr_topology. This was originally implemented in commit 90bcc3d38d2b
("driver/ddr: Add support for setting timing in hws_topology_map") but
was removed as part of the upstream sync.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Showing 9 changed files with 29 additions and 11 deletions Side-by-side Diff

board/CZ.NIC/turris_omnia/turris_omnia.c
Diff comments   View file @ e6f6162
... ... @@ -214,7 +214,8 @@
214 214 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
215 215 DDR_FREQ_800, /* frequency */
216 216 0, 0, /* cas_wl cas_l */
217   - MV_DDR_TEMP_NORMAL} }, /* temperature */
  217 + MV_DDR_TEMP_NORMAL, /* temperature */
  218 + MV_DDR_TIM_2T} }, /* timing */
218 219 BUS_MASK_32BIT, /* Busses mask */
219 220 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
220 221 { {0} }, /* raw spd data */
... ... @@ -235,7 +236,8 @@
235 236 MV_DDR_DIE_CAP_8GBIT, /* mem_size */
236 237 DDR_FREQ_800, /* frequency */
237 238 0, 0, /* cas_wl cas_l */
238   - MV_DDR_TEMP_NORMAL} }, /* temperature */
  239 + MV_DDR_TEMP_NORMAL, /* temperature */
  240 + MV_DDR_TIM_2T} }, /* timing */
239 241 BUS_MASK_32BIT, /* Busses mask */
240 242 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
241 243 { {0} }, /* raw spd data */
board/Marvell/db-88f6820-amc/db-88f6820-amc.c
Diff comments   View file @ e6f6162
... ... @@ -69,7 +69,8 @@
69 69 MV_DDR_DIE_CAP_2GBIT, /* mem_size */
70 70 DDR_FREQ_800, /* frequency */
71 71 0, 0, /* cas_wl cas_l */
72   - MV_DDR_TEMP_LOW} }, /* temperature */
  72 + MV_DDR_TEMP_LOW, /* temperature */
  73 + MV_DDR_TIM_DEFAULT} }, /* timing */
73 74 BUS_MASK_32BIT, /* Busses mask */
74 75 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
75 76 { {0} }, /* raw spd data */
board/Marvell/db-88f6820-gp/db-88f6820-gp.c
Diff comments   View file @ e6f6162
... ... @@ -90,7 +90,8 @@
90 90 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
91 91 DDR_FREQ_800, /* frequency */
92 92 0, 0, /* cas_wl cas_l */
93   - MV_DDR_TEMP_LOW} }, /* temperature */
  93 + MV_DDR_TEMP_LOW, /* temperature */
  94 + MV_DDR_TIM_DEFAULT} }, /* timing */
94 95 BUS_MASK_32BIT, /* Busses mask */
95 96 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
96 97 { {0} }, /* raw spd data */
board/gdsys/a38x/controlcenterdc.c
Diff comments   View file @ e6f6162
... ... @@ -53,7 +53,8 @@
53 53 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
54 54 DDR_FREQ_533, /* frequency */
55 55 0, 0, /* cas_wl cas_l */
56   - MV_DDR_TEMP_LOW} }, /* temperature */
  56 + MV_DDR_TEMP_LOW, /* temperature */
  57 + MV_DDR_TIM_DEFAULT} }, /* timing */
57 58 BUS_MASK_32BIT, /* Busses mask */
58 59 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
59 60 { {0} }, /* raw spd data */
board/solidrun/clearfog/clearfog.c
Diff comments   View file @ e6f6162
... ... @@ -83,7 +83,8 @@
83 83 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
84 84 DDR_FREQ_800, /* frequency */
85 85 0, 0, /* cas_wl cas_l */
86   - MV_DDR_TEMP_LOW} }, /* temperature */
  86 + MV_DDR_TEMP_LOW, /* temperature */
  87 + MV_DDR_TIM_DEFAULT} }, /* timing */
87 88 BUS_MASK_32BIT, /* Busses mask */
88 89 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
89 90 { {0} }, /* raw spd data */
drivers/ddr/marvell/a38x/ddr3_training.c
Diff comments   View file @ e6f6162
... ... @@ -365,6 +365,7 @@
365 365 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
366 366 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
367 367 enum hws_ddr_freq freq = tm->interface_params[0].memory_freq;
  368 + enum mv_ddr_timing timing;
368 369  
369 370 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
370 371 ("Init_controller, do_mrs_phy=%d, is_ctrl64_bit=%d\n",
371 372  
... ... @@ -603,8 +604,12 @@
603 604 DUNIT_CTRL_HIGH_REG,
604 605 (init_cntr_prm->msys_init << 7), (1 << 7)));
605 606  
  607 + timing = tm->interface_params[if_id].timing;
  608 +
606 609 if (mode_2t != 0xff) {
607 610 t2t = mode_2t;
  611 + } else if (timing != MV_DDR_TIM_DEFAULT) {
  612 + t2t = (timing == MV_DDR_TIM_2T) ? 1 : 0;
608 613 } else {
609 614 /* calculate number of CS (per interface) */
610 615 CHECK_STATUS(calc_cs_num
... ... @@ -1268,6 +1273,7 @@
1268 1273 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
1269 1274 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1270 1275 unsigned int tclk;
  1276 + enum mv_ddr_timing timing = tm->interface_params[if_id].timing;
1271 1277  
1272 1278 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
1273 1279 ("dev %d access %d IF %d freq %d\n", dev_num,
... ... @@ -1410,6 +1416,8 @@
1410 1416 /* Calculate 2T mode */
1411 1417 if (mode_2t != 0xff) {
1412 1418 t2t = mode_2t;
  1419 + } else if (timing != MV_DDR_TIM_DEFAULT) {
  1420 + t2t = (timing == MV_DDR_TIM_2T) ? 1 : 0;
1413 1421 } else {
1414 1422 /* Calculate number of CS per interface */
1415 1423 CHECK_STATUS(calc_cs_num(dev_num, if_id, &cs_num));
drivers/ddr/marvell/a38x/ddr_topology_def.h
Diff comments   View file @ e6f6162
... ... @@ -64,6 +64,9 @@
64 64  
65 65 /* operation temperature */
66 66 enum mv_ddr_temperature interface_temp;
  67 +
  68 + /* 2T vs 1T mode (by default computed from number of CSs) */
  69 + enum mv_ddr_timing timing;
67 70 };
68 71  
69 72 struct mv_ddr_topology_map {
drivers/ddr/marvell/a38x/mv_ddr_plat.c
Diff comments   View file @ e6f6162
... ... @@ -674,11 +674,6 @@
674 674 dfs_low_freq = DFS_LOW_FREQ_VALUE;
675 675 calibration_update_control = 1;
676 676  
677   -#ifdef CONFIG_ARMADA_38X
678   - /* For a38x only, change to 2T mode to resolve low freq instability */
679   - mode_2t = 1;
680   -#endif
681   -
682 677 ddr3_tip_a38x_get_medium_freq(dev_num, &medium_freq);
683 678  
684 679 return MV_OK;
drivers/ddr/marvell/a38x/mv_ddr_topology.h
Diff comments   View file @ e6f6162
... ... @@ -36,6 +36,12 @@
36 36 MV_DDR_TEMP_HIGH
37 37 };
38 38  
  39 +enum mv_ddr_timing {
  40 + MV_DDR_TIM_DEFAULT,
  41 + MV_DDR_TIM_1T,
  42 + MV_DDR_TIM_2T
  43 +};
  44 +
39 45 enum mv_ddr_timing_data {
40 46 MV_DDR_TCK_AVG_MIN, /* sdram min cycle time (t ck avg min) */
41 47 MV_DDR_TAA_MIN, /* min cas latency time (t aa min) */