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Commit e717fc6d1a2b459ae8352f7af5945cc0c216ab1e

Authored by Naveen Krishna Ch
Committed by Heiko Schocher
1 parent 92c23c9226
Exists in master and in 50 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

i2c: samsung: register i2c busses for Exynso5420 and Exynos5250 

This patch adds the U_BOOT_I2C_ADAP_COMPLETE defines for channels
on Exynos5420 and Exynos5250 and also adds support for init function
for hsi2c channels

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>

Showing 2 changed files with 182 additions and 48 deletions Side-by-side Diff

... ... @@ -2125,6 +2125,12 @@
2125 2125 - set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting
2126 2126 - set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr
2127 2127  
  2128 + - drivers/i2c/s3c24x0_i2c.c:
  2129 + - activate this driver with CONFIG_SYS_I2C_S3C24X0
  2130 + - This driver adds i2c buses (11 for Exynos5250, Exynos5420
  2131 + 9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
  2132 + with a fix speed from 100000 and the slave addr 0!
  2133 +
2128 2134 additional defines:
2129 2135  
2130 2136 CONFIG_SYS_NUM_I2C_BUSES
drivers/i2c/s3c24x0_i2c.c
Diff comments   View file @ e717fc6
... ... @@ -721,6 +721,17 @@
721 721 return 0;
722 722 }
723 723  
  724 +#ifdef CONFIG_EXYNOS5
  725 +static void exynos_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
  726 +{
  727 + /* This will override the speed selected in the fdt for that port */
  728 + debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
  729 + if (i2c_set_bus_speed(speed))
  730 + printf("i2c_init: failed to init bus %d for speed = %d\n",
  731 + adap->hwadapnr, speed);
  732 +}
  733 +#endif
  734 +
724 735 /*
725 736 * cmd_type is 0 for write, 1 for read.
726 737 *
... ... @@ -1071,52 +1082,169 @@
1071 1082 /*
1072 1083 * Register s3c24x0 i2c adapters
1073 1084 */
1074   -U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_0, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1075   - s3c24x0_i2c_read, s3c24x0_i2c_write,
1076   - s3c24x0_i2c_set_bus_speed,
1077   - CONFIG_SYS_I2C_S3C24X0_SPEED,
1078   - CONFIG_SYS_I2C_S3C24X0_SLAVE,
1079   - 0)
1080   -U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_1, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1081   - s3c24x0_i2c_read, s3c24x0_i2c_write,
1082   - s3c24x0_i2c_set_bus_speed,
1083   - CONFIG_SYS_I2C_S3C24X0_SPEED,
1084   - CONFIG_SYS_I2C_S3C24X0_SLAVE,
1085   - 1)
1086   -U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_2, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1087   - s3c24x0_i2c_read, s3c24x0_i2c_write,
1088   - s3c24x0_i2c_set_bus_speed,
1089   - CONFIG_SYS_I2C_S3C24X0_SPEED,
1090   - CONFIG_SYS_I2C_S3C24X0_SLAVE,
1091   - 2)
1092   -U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_3, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1093   - s3c24x0_i2c_read, s3c24x0_i2c_write,
1094   - s3c24x0_i2c_set_bus_speed,
1095   - CONFIG_SYS_I2C_S3C24X0_SPEED,
1096   - CONFIG_SYS_I2C_S3C24X0_SLAVE,
1097   - 3)
1098   -U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_4, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1099   - s3c24x0_i2c_read, s3c24x0_i2c_write,
1100   - s3c24x0_i2c_set_bus_speed,
1101   - CONFIG_SYS_I2C_S3C24X0_SPEED,
1102   - CONFIG_SYS_I2C_S3C24X0_SLAVE,
1103   - 4)
1104   -U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_5, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1105   - s3c24x0_i2c_read, s3c24x0_i2c_write,
1106   - s3c24x0_i2c_set_bus_speed,
1107   - CONFIG_SYS_I2C_S3C24X0_SPEED,
1108   - CONFIG_SYS_I2C_S3C24X0_SLAVE,
1109   - 5)
1110   -U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_6, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1111   - s3c24x0_i2c_read, s3c24x0_i2c_write,
1112   - s3c24x0_i2c_set_bus_speed,
1113   - CONFIG_SYS_I2C_S3C24X0_SPEED,
1114   - CONFIG_SYS_I2C_S3C24X0_SLAVE,
1115   - 6)
1116   -U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_7, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1117   - s3c24x0_i2c_read, s3c24x0_i2c_write,
1118   - s3c24x0_i2c_set_bus_speed,
1119   - CONFIG_SYS_I2C_S3C24X0_SPEED,
1120   - CONFIG_SYS_I2C_S3C24X0_SLAVE,
1121   - 7)
  1085 +#if defined(CONFIG_EXYNOS5420)
  1086 +U_BOOT_I2C_ADAP_COMPLETE(i2c00, s3c24x0_i2c_init, s3c24x0_i2c_probe,
  1087 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1088 + s3c24x0_i2c_set_bus_speed,
  1089 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1090 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
  1091 +U_BOOT_I2C_ADAP_COMPLETE(i2c01, s3c24x0_i2c_init, s3c24x0_i2c_probe,
  1092 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1093 + s3c24x0_i2c_set_bus_speed,
  1094 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1095 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
  1096 +U_BOOT_I2C_ADAP_COMPLETE(i2c02, s3c24x0_i2c_init, s3c24x0_i2c_probe,
  1097 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1098 + s3c24x0_i2c_set_bus_speed,
  1099 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1100 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
  1101 +U_BOOT_I2C_ADAP_COMPLETE(i2c03, exynos_i2c_init, s3c24x0_i2c_probe,
  1102 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1103 + s3c24x0_i2c_set_bus_speed,
  1104 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1105 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
  1106 +U_BOOT_I2C_ADAP_COMPLETE(i2c04, exynos_i2c_init, s3c24x0_i2c_probe,
  1107 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1108 + s3c24x0_i2c_set_bus_speed,
  1109 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1110 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
  1111 +U_BOOT_I2C_ADAP_COMPLETE(i2c05, exynos_i2c_init, s3c24x0_i2c_probe,
  1112 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1113 + s3c24x0_i2c_set_bus_speed,
  1114 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1115 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
  1116 +U_BOOT_I2C_ADAP_COMPLETE(i2c06, exynos_i2c_init, s3c24x0_i2c_probe,
  1117 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1118 + s3c24x0_i2c_set_bus_speed,
  1119 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1120 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
  1121 +U_BOOT_I2C_ADAP_COMPLETE(i2c07, exynos_i2c_init, s3c24x0_i2c_probe,
  1122 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1123 + s3c24x0_i2c_set_bus_speed,
  1124 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1125 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
  1126 +U_BOOT_I2C_ADAP_COMPLETE(i2c08, exynos_i2c_init, s3c24x0_i2c_probe,
  1127 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1128 + s3c24x0_i2c_set_bus_speed,
  1129 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1130 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
  1131 +U_BOOT_I2C_ADAP_COMPLETE(i2c09, exynos_i2c_init, s3c24x0_i2c_probe,
  1132 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1133 + s3c24x0_i2c_set_bus_speed,
  1134 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1135 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 9)
  1136 +U_BOOT_I2C_ADAP_COMPLETE(i2c10, exynos_i2c_init, s3c24x0_i2c_probe,
  1137 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1138 + s3c24x0_i2c_set_bus_speed,
  1139 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1140 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 10)
  1141 +#elif defined(CONFIG_EXYNOS5250)
  1142 +U_BOOT_I2C_ADAP_COMPLETE(i2c00, exynos_i2c_init, s3c24x0_i2c_probe,
  1143 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1144 + s3c24x0_i2c_set_bus_speed,
  1145 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1146 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
  1147 +U_BOOT_I2C_ADAP_COMPLETE(i2c01, exynos_i2c_init, s3c24x0_i2c_probe,
  1148 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1149 + s3c24x0_i2c_set_bus_speed,
  1150 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1151 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
  1152 +U_BOOT_I2C_ADAP_COMPLETE(i2c02, exynos_i2c_init, s3c24x0_i2c_probe,
  1153 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1154 + s3c24x0_i2c_set_bus_speed,
  1155 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1156 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
  1157 +U_BOOT_I2C_ADAP_COMPLETE(i2c03, exynos_i2c_init, s3c24x0_i2c_probe,
  1158 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1159 + s3c24x0_i2c_set_bus_speed,
  1160 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1161 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
  1162 +U_BOOT_I2C_ADAP_COMPLETE(i2c04, s3c24x0_i2c_init, s3c24x0_i2c_probe,
  1163 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1164 + s3c24x0_i2c_set_bus_speed,
  1165 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1166 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
  1167 +U_BOOT_I2C_ADAP_COMPLETE(i2c05, s3c24x0_i2c_init, s3c24x0_i2c_probe,
  1168 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1169 + s3c24x0_i2c_set_bus_speed,
  1170 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1171 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
  1172 +U_BOOT_I2C_ADAP_COMPLETE(i2c06, s3c24x0_i2c_init, s3c24x0_i2c_probe,
  1173 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1174 + s3c24x0_i2c_set_bus_speed,
  1175 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1176 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
  1177 +U_BOOT_I2C_ADAP_COMPLETE(i2c07, s3c24x0_i2c_init, s3c24x0_i2c_probe,
  1178 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1179 + s3c24x0_i2c_set_bus_speed,
  1180 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1181 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
  1182 +U_BOOT_I2C_ADAP_COMPLETE(i2c08, s3c24x0_i2c_init, s3c24x0_i2c_probe,
  1183 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1184 + s3c24x0_i2c_set_bus_speed,
  1185 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1186 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
  1187 +U_BOOT_I2C_ADAP_COMPLETE(i2c09, s3c24x0_i2c_init, s3c24x0_i2c_probe,
  1188 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1189 + s3c24x0_i2c_set_bus_speed,
  1190 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1191 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 9)
  1192 +U_BOOT_I2C_ADAP_COMPLETE(s3c10, s3c24x0_i2c_init, s3c24x0_i2c_probe,
  1193 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1194 + s3c24x0_i2c_set_bus_speed,
  1195 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1196 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 10)
  1197 +#elif defined(CONFIG_EXYNOS4)
  1198 +U_BOOT_I2C_ADAP_COMPLETE(i2c00, s3c24x0_i2c_init, s3c24x0_i2c_probe,
  1199 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1200 + s3c24x0_i2c_set_bus_speed,
  1201 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1202 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
  1203 +U_BOOT_I2C_ADAP_COMPLETE(i2c01, s3c24x0_i2c_init, s3c24x0_i2c_probe,
  1204 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1205 + s3c24x0_i2c_set_bus_speed,
  1206 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1207 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
  1208 +U_BOOT_I2C_ADAP_COMPLETE(i2c02, s3c24x0_i2c_init, s3c24x0_i2c_probe,
  1209 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1210 + s3c24x0_i2c_set_bus_speed,
  1211 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1212 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
  1213 +U_BOOT_I2C_ADAP_COMPLETE(i2c03, s3c24x0_i2c_init, s3c24x0_i2c_probe,
  1214 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1215 + s3c24x0_i2c_set_bus_speed,
  1216 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1217 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
  1218 +U_BOOT_I2C_ADAP_COMPLETE(i2c04, s3c24x0_i2c_init, s3c24x0_i2c_probe,
  1219 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1220 + s3c24x0_i2c_set_bus_speed,
  1221 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1222 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
  1223 +U_BOOT_I2C_ADAP_COMPLETE(i2c05, s3c24x0_i2c_init, s3c24x0_i2c_probe,
  1224 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1225 + s3c24x0_i2c_set_bus_speed,
  1226 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1227 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
  1228 +U_BOOT_I2C_ADAP_COMPLETE(i2c06, s3c24x0_i2c_init, s3c24x0_i2c_probe,
  1229 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1230 + s3c24x0_i2c_set_bus_speed,
  1231 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1232 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
  1233 +U_BOOT_I2C_ADAP_COMPLETE(i2c07, s3c24x0_i2c_init, s3c24x0_i2c_probe,
  1234 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1235 + s3c24x0_i2c_set_bus_speed,
  1236 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1237 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
  1238 +U_BOOT_I2C_ADAP_COMPLETE(i2c08, s3c24x0_i2c_init, s3c24x0_i2c_probe,
  1239 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1240 + s3c24x0_i2c_set_bus_speed,
  1241 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1242 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
  1243 +#else
  1244 +U_BOOT_I2C_ADAP_COMPLETE(s3c0, s3c24x0_i2c_init, s3c24x0_i2c_probe,
  1245 + s3c24x0_i2c_read, s3c24x0_i2c_write,
  1246 + s3c24x0_i2c_set_bus_speed,
  1247 + CONFIG_SYS_I2C_S3C24X0_SPEED,
  1248 + CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
  1249 +#endif