armv8/ls2085aqds: DSPI pin muxing configure through QIXIS

DSPI has pin muxing with SDHC and other IPs, this patch check the value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check the "hwconfig" variable. If those pins are configured to DSPI and "hwconfig" enable DSPI, set the BRDCFG5 of QIXIS FPGA to configure the routing to on-board SPI memory. Otherwise will configure to SDHC. DSPI is enabled in "hwconfig" by appending "dspi", eg. setenv hwconfig "$hwconfig;dspi" Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>

armv8/ls2085aqds: DSPI pin muxing configure through QIXIS
DSPI has pin muxing with SDHC and other IPs, this patch check the value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check the "hwconfig" variable. If those pins are configured to DSPI and "hwconfig" enable DSPI, set the BRDCFG5 of QIXIS FPGA to configure the routing to on-board SPI memory. Otherwise will configure to SDHC. DSPI is enabled in "hwconfig" by appending "dspi", eg. setenv hwconfig "$hwconfig;dspi" Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Haikun Wang · York Sun
1 parent b0e209dc63
Showing 2 changed files with 50 additions and 0 deletions Side-by-side Diff
arch/arm/include/asm/arch-fsl-lsch3/config.h
board/freescale/ls2085aqds/ls2085aqds.c
@@ -137,6 +137,8 @@
 #define DCFG_PORSR1			0x000
 #define DCFG_PORSR1_RCW_SRC		0xff800000
 #define DCFG_PORSR1_RCW_SRC_NOR		0x12f00000
+#define DCFG_RCWSR13			0x130
+#define DCFG_RCWSR13_DSPI		(0 << 8)
  
 #define DCFG_DCSR_BASE		0X700100000ULL
 #define DCFG_DCSR_PORCR1		0x000
@@ -17,12 +17,23 @@
 #include <environment.h>
 #include <i2c.h>
 #include <asm/arch-fsl-lsch3/soc.h>
+#include <hwconfig.h>
  
 #include "../common/qixis.h"
 #include "ls2085aqds_qixis.h"
  
+#define PIN_MUX_SEL_SDHC	0x00
+#define PIN_MUX_SEL_DSPI	0x0a
+
+#define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
+
 DECLARE_GLOBAL_DATA_PTR;
  
+enum {
+	MUX_TYPE_SDHC,
+	MUX_TYPE_DSPI,
+};
+
 unsigned long long get_qixis_addr(void)
 {
 	unsigned long long addr;
  
  
@@ -153,9 +164,46 @@
 	return 0;
 }
  
+int config_board_mux(int ctrl_type)
+{
+	u8 reg5;
+
+	reg5 = QIXIS_READ(brdcfg[5]);
+
+	switch (ctrl_type) {
+	case MUX_TYPE_SDHC:
+		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
+		break;
+	case MUX_TYPE_DSPI:
+		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
+		break;
+	default:
+		printf("Wrong mux interface type\n");
+		return -1;
+	}
+
+	QIXIS_WRITE(brdcfg[5], reg5);
+
+	return 0;
+}
+
 int board_init(void)
 {
+	char *env_hwconfig;
+	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+	u32 val;
+
 	init_final_memctl_regs();
+
+	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
+
+	env_hwconfig = getenv("hwconfig");
+
+	if (hwconfig_f("dspi", env_hwconfig) &&
+	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
+		config_board_mux(MUX_TYPE_DSPI);
+	else
+		config_board_mux(MUX_TYPE_SDHC);
  
 #ifdef CONFIG_ENV_IS_NOWHERE
 	gd->env_addr = (ulong)&default_environment[0];
...	...	@@ -137,6 +137,8 @@
137	137	#define DCFG_PORSR1 0x000
138	138	#define DCFG_PORSR1_RCW_SRC 0xff800000
139	139	#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
	140	+#define DCFG_RCWSR13 0x130
	141	+#define DCFG_RCWSR13_DSPI (0 << 8)
140	142
141	143	#define DCFG_DCSR_BASE 0X700100000ULL
142	144	#define DCFG_DCSR_PORCR1 0x000
...	...	@@ -17,12 +17,23 @@
17	17	#include <environment.h>
18	18	#include <i2c.h>
19	19	#include <asm/arch-fsl-lsch3/soc.h>
	20	+#include <hwconfig.h>
20	21
21	22	#include "../common/qixis.h"
22	23	#include "ls2085aqds_qixis.h"
23	24
	25	+#define PIN_MUX_SEL_SDHC 0x00
	26	+#define PIN_MUX_SEL_DSPI 0x0a
	27	+
	28	+#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) \| value)
	29	+
24	30	DECLARE_GLOBAL_DATA_PTR;
25	31
	32	+enum {
	33	+ MUX_TYPE_SDHC,
	34	+ MUX_TYPE_DSPI,
	35	+};
	36	+
26	37	unsigned long long get_qixis_addr(void)
27	38	{
28	39	unsigned long long addr;
29	40
30	41
...	...	@@ -153,9 +164,46 @@
153	164	return 0;
154	165	}
155	166
	167	+int config_board_mux(int ctrl_type)
	168	+{
	169	+ u8 reg5;
	170	+
	171	+ reg5 = QIXIS_READ(brdcfg[5]);
	172	+
	173	+ switch (ctrl_type) {
	174	+ case MUX_TYPE_SDHC:
	175	+ reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
	176	+ break;
	177	+ case MUX_TYPE_DSPI:
	178	+ reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
	179	+ break;
	180	+ default:
	181	+ printf("Wrong mux interface type\n");
	182	+ return -1;
	183	+ }
	184	+
	185	+ QIXIS_WRITE(brdcfg[5], reg5);
	186	+
	187	+ return 0;
	188	+}
	189	+
156	190	int board_init(void)
157	191	{
	192	+ char *env_hwconfig;
	193	+ u32 __iomem dcfg_ccsr = (u32 __iomem )DCFG_BASE;
	194	+ u32 val;
	195	+
158	196	init_final_memctl_regs();
	197	+
	198	+ val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
	199	+
	200	+ env_hwconfig = getenv("hwconfig");
	201	+
	202	+ if (hwconfig_f("dspi", env_hwconfig) &&
	203	+ DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
	204	+ config_board_mux(MUX_TYPE_DSPI);
	205	+ else
	206	+ config_board_mux(MUX_TYPE_SDHC);
159	207
160	208	#ifdef CONFIG_ENV_IS_NOWHERE
161	209	gd->env_addr = (ulong)&default_environment[0];