Commit e74b74c52876d776dda7a7ee5e2a8d555eaa5c4f
Committed by
Tom Rini
Tom Rini
1 parent
8d6310aa0b
Exists in
smarc_8mq_lf_v2020.04
and in
11 other branches
dts: stm32mp1: clock tree update
- Add st,digbypass on clk_hse node (needed for board rev.C) - MLAHB/AHB max frequency increased from 200 to 209MHz, with: - PLL3P set to 208.8MHz for MCU sub-system - PLL3Q set to 24.57MHz for 48kHz SAI/SPI2S - PLL3R set to 11.29MHz for 44.1kHz SAI/SPI2S - PLL4P set to 99MHz for SDMMC and SPDIFRX - PLL4Q set to 74.25MHz for EVAL board Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Showing 2 changed files with 15 additions and 15 deletions Side-by-side Diff
arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
| ... | ... | @@ -39,6 +39,10 @@ |
| 39 | 39 | }; |
| 40 | 40 | }; |
| 41 | 41 | |
| 42 | +&clk_hse { | |
| 43 | + st,digbypass; | |
| 44 | +}; | |
| 45 | + | |
| 42 | 46 | &uart4_pins_a { |
| 43 | 47 | u-boot,dm-pre-reloc; |
| 44 | 48 | pins1 { |
| ... | ... | @@ -68,7 +72,6 @@ |
| 68 | 72 | u-boot,dm-pre-reloc; |
| 69 | 73 | }; |
| 70 | 74 | |
| 71 | -/* CLOCK init */ | |
| 72 | 75 | &rcc { |
| 73 | 76 | st,clksrc = < |
| 74 | 77 | CLK_MPU_PLL1P |
| ... | ... | @@ -101,7 +104,7 @@ |
| 101 | 104 | CLK_FMC_ACLK |
| 102 | 105 | CLK_QSPI_ACLK |
| 103 | 106 | CLK_ETH_DISABLED |
| 104 | - CLK_SDMMC12_PLL3R | |
| 107 | + CLK_SDMMC12_PLL4P | |
| 105 | 108 | CLK_DSI_DSIPLL |
| 106 | 109 | CLK_STGEN_HSE |
| 107 | 110 | CLK_USBPHY_HSE |
| ... | ... | @@ -110,7 +113,7 @@ |
| 110 | 113 | CLK_SPI45_HSI |
| 111 | 114 | CLK_SPI6_HSI |
| 112 | 115 | CLK_I2C46_HSI |
| 113 | - CLK_SDMMC3_PLL3R | |
| 116 | + CLK_SDMMC3_PLL4P | |
| 114 | 117 | CLK_USBO_USBPHY |
| 115 | 118 | CLK_ADC_CKPER |
| 116 | 119 | CLK_CEC_LSE |
| 117 | 120 | |
| 118 | 121 | |
| ... | ... | @@ -121,17 +124,17 @@ |
| 121 | 124 | CLK_UART35_HSI |
| 122 | 125 | CLK_UART6_HSI |
| 123 | 126 | CLK_UART78_HSI |
| 124 | - CLK_SPDIF_PLL3Q | |
| 127 | + CLK_SPDIF_PLL4P | |
| 125 | 128 | CLK_FDCAN_PLL4Q |
| 126 | 129 | CLK_SAI1_PLL3Q |
| 127 | 130 | CLK_SAI2_PLL3Q |
| 128 | 131 | CLK_SAI3_PLL3Q |
| 129 | 132 | CLK_SAI4_PLL3Q |
| 130 | - CLK_RNG1_CSI | |
| 131 | - CLK_RNG2_CSI | |
| 133 | + CLK_RNG1_LSI | |
| 134 | + CLK_RNG2_LSI | |
| 132 | 135 | CLK_LPTIM1_PCLK1 |
| 133 | 136 | CLK_LPTIM23_PCLK3 |
| 134 | - CLK_LPTIM45_PCLK3 | |
| 137 | + CLK_LPTIM45_LSE | |
| 135 | 138 | >; |
| 136 | 139 | |
| 137 | 140 | /* VCO = 1300.0 MHz => P = 650 (CPU) */ |
| 138 | 141 | |
| 139 | 142 | |
| 140 | 143 | |
| ... | ... | @@ -148,16 +151,16 @@ |
| 148 | 151 | u-boot,dm-pre-reloc; |
| 149 | 152 | }; |
| 150 | 153 | |
| 151 | - /* VCO = 786.4 MHz => P = 197, Q = 49, R = 98 */ | |
| 154 | + /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ | |
| 152 | 155 | pll3: st,pll@2 { |
| 153 | - cfg = < 2 97 3 15 7 PQR(1,1,1) >; | |
| 154 | - frac = < 0x9ba >; | |
| 156 | + cfg = < 1 33 1 16 36 PQR(1,1,1) >; | |
| 157 | + frac = < 0x1a04 >; | |
| 155 | 158 | u-boot,dm-pre-reloc; |
| 156 | 159 | }; |
| 157 | 160 | |
| 158 | - /* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */ | |
| 161 | + /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ | |
| 159 | 162 | pll4: st,pll@3 { |
| 160 | - cfg = < 5 126 8 8 8 PQR(1,1,1) >; | |
| 163 | + cfg = < 3 98 5 7 7 PQR(1,1,1) >; | |
| 161 | 164 | u-boot,dm-pre-reloc; |
| 162 | 165 | }; |
| 163 | 166 | }; |