Eric Lee / smarc-uboot | Embedian Git Server

Commit e7a565638a7a727f1a4074c0b39e7de22ff3d6c9

Authored by Masahiro Yamada 2014-09-29 00:38:00 +0800

Committed by Tom Rini 2014-10-10 21:44:43 +0800

Exists in v2017.01-smarct4x and in 37 other branches

powerpc: mpc83xx: remove board support for MERGERBOX and MVBLM7

These boards have been orphaned for more than 6 months.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Showing 27 changed files with 2 additions and 2495 deletions Inline Diff

arch/powerpc/cpu/mpc83xx/Kconfig
board/matrix_vision/mergerbox/Kconfig
board/matrix_vision/mergerbox/MAINTAINERS
board/matrix_vision/mergerbox/Makefile
board/matrix_vision/mergerbox/README
board/matrix_vision/mergerbox/fpga.c
board/matrix_vision/mergerbox/fpga.h
board/matrix_vision/mergerbox/mergerbox.c
board/matrix_vision/mergerbox/mergerbox.h
board/matrix_vision/mergerbox/pci.c
board/matrix_vision/mergerbox/sm107.c
board/matrix_vision/mvblm7/.gitignore
board/matrix_vision/mvblm7/Kconfig
board/matrix_vision/mvblm7/MAINTAINERS
board/matrix_vision/mvblm7/Makefile
board/matrix_vision/mvblm7/README.mvblm7
board/matrix_vision/mvblm7/bootscript
board/matrix_vision/mvblm7/fpga.c
board/matrix_vision/mvblm7/fpga.h
board/matrix_vision/mvblm7/mvblm7.c
board/matrix_vision/mvblm7/mvblm7.h
board/matrix_vision/mvblm7/pci.c
configs/MERGERBOX_defconfig
configs/MVBLM7_defconfig
doc/README.scrapyard
include/configs/MERGERBOX.h
include/configs/MVBLM7.h

arch/powerpc/cpu/mpc83xx/Kconfig

Diff comments View file @ e7a5656

 menu "mpc83xx CPU"
 	depends on MPC83xx
 config SYS_CPU
 	default "mpc83xx"
 choice
 	prompt "Target select"
 config TARGET_MPC8308_P1M
 	bool "Support mpc8308_p1m"
 config TARGET_SBC8349
 	bool "Support sbc8349"
 config TARGET_VE8313
 	bool "Support ve8313"
 config TARGET_VME8349
 	bool "Support vme8349"
 config TARGET_MPC8308RDB
 	bool "Support MPC8308RDB"
 config TARGET_MPC8313ERDB
 	bool "Support MPC8313ERDB"
 config TARGET_MPC8315ERDB
 	bool "Support MPC8315ERDB"
 config TARGET_MPC8323ERDB
 	bool "Support MPC8323ERDB"
 config TARGET_MPC832XEMDS
 	bool "Support MPC832XEMDS"
 config TARGET_MPC8349EMDS
 	bool "Support MPC8349EMDS"
 config TARGET_MPC8349ITX
 	bool "Support MPC8349ITX"
 config TARGET_MPC8360EMDS
 	bool "Support MPC8360EMDS"
 config TARGET_MPC8360ERDK
 	bool "Support MPC8360ERDK"
 config TARGET_MPC837XEMDS
 	bool "Support MPC837XEMDS"
 config TARGET_MPC837XERDB
 	bool "Support MPC837XERDB"
 config TARGET_IDS8313
 	bool "Support ids8313"
 config TARGET_KM8360
 	bool "Support km8360"
 config TARGET_SUVD3
 	bool "Support suvd3"
 config TARGET_TUXX1
 	bool "Support tuxx1"
-config TARGET_MERGERBOX
-	bool "Support MERGERBOX"
-config TARGET_MVBLM7
-	bool "Support MVBLM7"
 config TARGET_TQM834X
 	bool "Support TQM834x"
 endchoice
 source "board/esd/vme8349/Kconfig"
 source "board/freescale/mpc8308rdb/Kconfig"
 source "board/freescale/mpc8313erdb/Kconfig"
 source "board/freescale/mpc8315erdb/Kconfig"
 source "board/freescale/mpc8323erdb/Kconfig"
 source "board/freescale/mpc832xemds/Kconfig"
 source "board/freescale/mpc8349emds/Kconfig"
 source "board/freescale/mpc8349itx/Kconfig"
 source "board/freescale/mpc8360emds/Kconfig"
 source "board/freescale/mpc8360erdk/Kconfig"
 source "board/freescale/mpc837xemds/Kconfig"
 source "board/freescale/mpc837xerdb/Kconfig"
 source "board/ids/ids8313/Kconfig"
 source "board/keymile/km83xx/Kconfig"
-source "board/matrix_vision/mergerbox/Kconfig"
-source "board/matrix_vision/mvblm7/Kconfig"
 source "board/mpc8308_p1m/Kconfig"
 source "board/sbc8349/Kconfig"
 source "board/tqc/tqm834x/Kconfig"
 source "board/ve8313/Kconfig"
 endmenu

board/matrix_vision/mergerbox/Kconfig

View file @ e7a5656

1	if TARGET_MERGERBOX		File was deleted
2
3	config SYS_BOARD
4	default "mergerbox"
5
6	config SYS_VENDOR
7	default "matrix_vision"
8
9	config SYS_CONFIG_NAME
10	default "MERGERBOX"
11
12	endif
13		1	if TARGET_MERGERBOX

board/matrix_vision/mergerbox/MAINTAINERS

View file @ e7a5656

1	MERGERBOX BOARD		File was deleted
2	#M: Andre Schwarz <andre.schwarz@matrix-vision.de>
3	S: Orphan (since 2014-03)
4	F: board/matrix_vision/mergerbox/
5	F: include/configs/MERGERBOX.h
6	F: configs/MERGERBOX_defconfig
7		1	MERGERBOX BOARD

board/matrix_vision/mergerbox/Makefile

View file @ e7a5656

1	#		File was deleted
2	# (C) Copyright 2006
3	# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	#
5	# SPDX-License-Identifier: GPL-2.0+
6	#
7
8	obj-y += mergerbox.o pci.o fpga.o sm107.o
9		1	#

board/matrix_vision/mergerbox/README

View file @ e7a5656

1	Matrix Vision MergerBox		File was deleted
2	-----------------------
3
4	1. Board Description
5
6	The MergerBox is a 120x160mm single board computing platform
7	for 3D Full-HD digital video processing.
8
9	Power Supply is 10-32VDC.
10
11	2 System Components
12
13	2.1 CPU
14	Freescale MPC8377 CPU running at 800MHz core and 333MHz csb.
15	256 MByte DDR-II memory @ 333MHz data rate.
16	64 MByte Nor Flash on local bus.
17	1 GByte Nand Flash on FCM.
18	1 Vitesse VSC8601 RGMII ethernet Phys.
19	1 USB host controller over ULPI I/F with 4-Port hub.
20	2 serial ports. Console running on ttyS0 @ 115200 8N1.
21	1 mPCIe expansion slot (PCIe x1 + USB) used for Wifi/Bt.
22	2 PCIe x1 busses on local mPCIe and cutom expansion connector.
23	2 SATA host ports.
24	System configuration (HRCW) is taken from I2C EEPROM.
25
26	2.2 Graphics
27	SM107 emebedded video controller driving a 5" 800x480 TFT panel.
28	Connected over 32-Bit/66MHz PCI utilizing 4 MByte embedded memory.
29
30	2.3 FPGA
31	Altera Cyclone-IV EP4C115 with several PCI DMA engines.
32	Connects to 7x Gennum 3G-SDI transceivers as video interconnect
33	as well as a HDMI v1.4 compliant output for 3D monitoring.
34	Utilizes two more DDR-II controllers providing 256MB memory.
35
36	2.4 I2C
37	Bus1:
38	AD7418 @ 0x50 for voltage/temp. monitoring.
39	SX8650 @ 0x90 touch controller for HMI.
40	EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
41	Bus2:
42	mPCIe SMBus
43	SiI9022A @ 0x72/0xC0 HDMI transmitter.
44	TCA6416A @ 0x40 + 0x42 16-Bit I/O expander.
45	LMH1983 @ 0xCA video PLL.
46	DS1338C @ 0xD0 real-time clock with embedded crystal.
47	9FG104 @ 0xDC 4x 100MHz LVDS SerDes reference clock.
48
49	3 Flash layout.
50
51	reset vector is 0x00000100, i.e. low boot.
52
53	00000000 u-boot binary.
54	00100000 FPGA raw bit file.
55	00300000 FIT image holding kernel, dtb and rescue squashfs.
56	03d00000 u-boot environment.
57	03e00000 splash image
58
59	mtd partitions are propagated to linux kernel via device tree blob.
60		1	Matrix Vision MergerBox

board/matrix_vision/mergerbox/fpga.c

View file @ e7a5656

1	/*		File was deleted
2	* (C) Copyright 2002
3	* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4	* Keith Outwater, keith_outwater@mvis.com.
5	*
6	* (C) Copyright 2011
7	* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
8	*
9	* SPDX-License-Identifier: GPL-2.0+
10	*/
11
12	#include <common.h>
13	#include <ACEX1K.h>
14	#include <command.h>
15	#include "mergerbox.h"
16	#include "fpga.h"
17
18	Altera_CYC2_Passive_Serial_fns altera_fns = {
19	fpga_null_fn,
20	fpga_config_fn,
21	fpga_status_fn,
22	fpga_done_fn,
23	fpga_wr_fn,
24	fpga_null_fn,
25	fpga_null_fn,
26	};
27
28	Altera_desc cyclone2 = {
29	Altera_CYC2,
30	passive_serial,
31	Altera_EP2C20_SIZE,
32	(void *) &altera_fns,
33	NULL,
34	0
35	};
36
37	DECLARE_GLOBAL_DATA_PTR;
38
39	int mergerbox_init_fpga(void)
40	{
41	debug("Initialize FPGA interface\n");
42	fpga_init();
43	fpga_add(fpga_altera, &cyclone2);
44
45	return 1;
46	}
47
48	int fpga_null_fn(int cookie)
49	{
50	return 0;
51	}
52
53	int fpga_config_fn(int assert, int flush, int cookie)
54	{
55	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
56	volatile gpio83xx_t gpio = (gpio83xx_t )&im->gpio[0];
57	u32 dvo = gpio->dat;
58
59	dvo &= ~FPGA_CONFIG;
60	gpio->dat = dvo;
61	udelay(5);
62	dvo \|= FPGA_CONFIG;
63	gpio->dat = dvo;
64
65	return assert;
66	}
67
68	int fpga_done_fn(int cookie)
69	{
70	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
71	volatile gpio83xx_t gpio = (gpio83xx_t )&im->gpio[0];
72	int result = 0;
73
74	udelay(10);
75	debug("CONF_DONE check ... ");
76	if (gpio->dat & FPGA_CONF_DONE) {
77	debug("high\n");
78	result = 1;
79	} else
80	debug("low\n");
81
82	return result;
83	}
84
85	int fpga_status_fn(int cookie)
86	{
87	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
88	volatile gpio83xx_t gpio = (gpio83xx_t )&im->gpio[0];
89	int result = 0;
90
91	debug("STATUS check ... ");
92	if (gpio->dat & FPGA_STATUS) {
93	debug("high\n");
94	result = 1;
95	} else
96	debug("low\n");
97
98	return result;
99	}
100
101	int fpga_clk_fn(int assert_clk, int flush, int cookie)
102	{
103	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
104	volatile gpio83xx_t gpio = (gpio83xx_t )&im->gpio[0];
105	u32 dvo = gpio->dat;
106
107	debug("CLOCK %s\n", assert_clk ? "high" : "low");
108	if (assert_clk)
109	dvo \|= FPGA_CCLK;
110	else
111	dvo &= ~FPGA_CCLK;
112
113	if (flush)
114	gpio->dat = dvo;
115
116	return assert_clk;
117	}
118
119	static inline int _write_fpga(u8 val, int dump)
120	{
121	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
122	volatile gpio83xx_t gpio = (gpio83xx_t )&im->gpio[0];
123	int i;
124	u32 dvo = gpio->dat;
125
126	if (dump)
127	debug(" %02x -> ", val);
128	for (i = 0; i < 8; i++) {
129	dvo &= ~FPGA_CCLK;
130	gpio->dat = dvo;
131	dvo &= ~FPGA_DIN;
132	if (dump)
133	debug("%d ", val&1);
134	if (val & 1)
135	dvo \|= FPGA_DIN;
136	gpio->dat = dvo;
137	dvo \|= FPGA_CCLK;
138	gpio->dat = dvo;
139	val >>= 1;
140	}
141	if (dump)
142	debug("\n");
143
144	return 0;
145	}
146
147	int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
148	{
149	unsigned char data = (unsigned char ) buf;
150	int i;
151
152	debug("fpga_wr: buf %p / size %d\n", buf, len);
153	for (i = 0; i < len; i++)
154	_write_fpga(data[i], 0);
155	debug("\n");
156
157	return FPGA_SUCCESS;
158	}
159		1	/*

board/matrix_vision/mergerbox/fpga.h

View file @ e7a5656

1	/*		File was deleted
2	* SPDX-License-Identifier: GPL-2.0+
3	*/
4
5	extern int mergerbox_init_fpga(void);
6
7	extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
8	extern int fpga_status_fn(int cookie);
9	extern int fpga_config_fn(int assert, int flush, int cookie);
10	extern int fpga_done_fn(int cookie);
11	extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
12	extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
13	extern int fpga_null_fn(int cookie);
14		1	/*

board/matrix_vision/mergerbox/mergerbox.c

View file @ e7a5656

1	/*		File was deleted
2	* Copyright (C) 2007 Freescale Semiconductor, Inc.
3	*
4	* Copyright (C) 2011 Matrix Vision GmbH
5	* Andre Schwarz <andre.schwarz@matrix-vision.de>
6	*
7	* SPDX-License-Identifier: GPL-2.0+
8	*/
9
10	#include <common.h>
11	#include <hwconfig.h>
12	#include <i2c.h>
13	#include <spi.h>
14	#include <asm/io.h>
15	#include <asm/fsl_mpc83xx_serdes.h>
16	#include <fdt_support.h>
17	#include <spd_sdram.h>
18	#include "mergerbox.h"
19	#include "fpga.h"
20	#include "../common/mv_common.h"
21
22	static void setup_serdes(void)
23	{
24	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
25	FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
26	fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
27	FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
28	}
29
30	#if defined(CONFIG_SYS_DRAM_TEST)
31	int testdram(void)
32	{
33	uint pstart = (uint ) CONFIG_SYS_MEMTEST_START;
34	uint pend = (uint ) CONFIG_SYS_MEMTEST_END;
35	uint *p;
36
37	printf("Testing DRAM from 0x%08x to 0x%08x\n",
38	CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
39
40	printf("DRAM test phase 1:\n");
41	for (p = pstart; p < pend; p++)
42	*p = 0xaaaaaaaa;
43
44	for (p = pstart; p < pend; p++) {
45	if (*p != 0xaaaaaaaa) {
46	printf("DRAM test fails at: %08x\n", (uint) p);
47	return 1;
48	}
49	}
50
51	printf("DRAM test phase 2:\n");
52	for (p = pstart; p < pend; p++)
53	*p = 0x55555555;
54
55	for (p = pstart; p < pend; p++) {
56	if (*p != 0x55555555) {
57	printf("DRAM test fails at: %08x\n", (uint) p);
58	return 1;
59	}
60	}
61
62	printf("DRAM test passed.\n");
63	return 0;
64	}
65	#endif
66
67	phys_size_t initdram(int board_type)
68	{
69	u32 msize;
70
71	volatile immap_t immr = (immap_t )CONFIG_SYS_IMMR;
72	volatile clk83xx_t clk = (clk83xx_t )&immr->clk;
73
74	/* Enable PCI_CLK[0:1] */
75	clk->occr \|= 0xc0000000;
76	udelay(2000);
77
78	#if defined(CONFIG_SPD_EEPROM)
79	msize = spd_sdram();
80	#else
81	immap_t im = (immap_t ) CONFIG_SYS_IMMR;
82	u32 msize_log2;
83
84	msize = CONFIG_SYS_DDR_SIZE;
85	msize_log2 = __ilog2(msize);
86
87	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
88	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN \| (msize_log2 - 1);
89
90	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
91	udelay(50000);
92
93	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
94	udelay(1000);
95
96	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
97	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
98	udelay(1000);
99
100	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
101	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
102	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
103	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
104	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
105	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
106	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
107	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
108	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
109	__asm__ __volatile__("sync");
110	udelay(1000);
111
112	im->ddr.sdram_cfg \|= SDRAM_CFG_MEM_EN;
113	udelay(2000);
114	#endif
115	setup_serdes();
116
117	return msize << 20;
118	}
119
120	int checkboard(void)
121	{
122	puts("Board: Matrix Vision MergerBox\n");
123
124	return 0;
125	}
126
127	int misc_init_r(void)
128	{
129	u16 dim;
130	int result;
131	volatile immap_t immr = (immap_t )CONFIG_SYS_IMMR;
132	volatile gpio83xx_t gpio = (gpio83xx_t )&immr->gpio[1];
133	unsigned char mac[6], mac_verify[6];
134	char *s = getenv("reset_env");
135
136	for (dim = 10; dim < 180; dim += 5) {
137	mergerbox_tft_dim(dim);
138	udelay(100000);
139	}
140
141	if (s)
142	mv_reset_environment();
143
144	i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac, sizeof(mac));
145
146	/* check if Matrix Vision prefix present and export to env */
147	if (mac[0] == 0x00 && mac[1] == 0x0c && mac[2] == 0x8d) {
148	printf("valid MAC found in eeprom: %pM\n", mac);
149	eth_setenv_enetaddr("ethaddr", mac);
150	} else {
151	printf("no valid MAC found in eeprom.\n");
152
153	/* no: check the env */
154	if (!eth_getenv_enetaddr("ethaddr", mac)) {
155	printf("no valid MAC found in env either.\n");
156	/* TODO: ask for valid MAC */
157	} else {
158	printf("valid MAC found in env: %pM\n", mac);
159	printf("updating MAC in eeprom.\n");
160
161	do {
162	result = test_and_clear_bit(20, &gpio->dat);
163	if (result)
164	printf("unprotect EEPROM failed !\n");
165	udelay(20000);
166	} while(result);
167
168	i2c_write(SPD_EEPROM_ADDRESS, 0x80, 2, mac, 6);
169	udelay(20000);
170
171	do {
172	result = test_and_set_bit(20, &gpio->dat);
173	if (result)
174	printf("protect EEPROM failed !\n");
175	udelay(20000);
176	} while(result);
177
178	printf("verify MAC %pM ... ", mac);
179	i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac_verify, 6);
180
181	if (!strncmp((char )mac, (char )mac_verify, 6))
182	printf("ok.\n");
183	else
184	/* TODO: retry or do something useful */
185	printf("FAILED (got %pM) !\n", mac_verify);
186	}
187	}
188
189	return 0;
190	}
191
192	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
193	{
194	return bus == 0 && cs == 0;
195	}
196
197	void spi_cs_activate(struct spi_slave *slave)
198	{
199	volatile gpio83xx_t iopd = &((immap_t )CONFIG_SYS_IMMR)->gpio[0];
200
201	iopd->dat &= ~TFT_SPI_CPLD_CS;
202	}
203
204	void spi_cs_deactivate(struct spi_slave *slave)
205	{
206	volatile gpio83xx_t iopd = &((immap_t )CONFIG_SYS_IMMR)->gpio[0];
207
208	iopd->dat \|= TFT_SPI_CPLD_CS;
209	}
210
211	/* control backlight pwm (display brightness).
212	* allow values 0-250 with 0 = turn off and 250 = max brightness
213	*/
214	void mergerbox_tft_dim(u16 value)
215	{
216	struct spi_slave *slave;
217	u16 din;
218	u16 dout = 0;
219
220	if (value > 0 && value < 250)
221	dout = 0x4000 \| value;
222
223	slave = spi_setup_slave(0, 0, 1000000, SPI_MODE_0 \| SPI_CS_HIGH);
224	spi_claim_bus(slave);
225	spi_xfer(slave, 16, &dout, &din, SPI_XFER_BEGIN \| SPI_XFER_END);
226	spi_release_bus(slave);
227	spi_free_slave(slave);
228	}
229
230	void ft_board_setup(void blob, bd_t bd)
231	{
232	ft_cpu_setup(blob, bd);
233	fdt_fixup_dr_usb(blob, bd);
234	ft_pci_setup(blob, bd);
235	}
236		1	/*

board/matrix_vision/mergerbox/mergerbox.h

View file @ e7a5656

1	/*		File was deleted
2	* Copyright (C) 2011 Matrix Vision GmbH
3	* Andre Schwarz <andre.schwarz@matrix-vision.de>
4	*
5	* SPDX-License-Identifier: GPL-2.0+
6	*/
7
8	#ifndef __MERGERBOX_H__
9	#define __MERGERBOX_H__
10
11	#define MV_GPIO
12
13	/*
14	* GPIO Bank 1
15	*/
16	#define TFT_SPI_EN (0x80000000>>0)
17	#define FPGA_CONFIG (0x80000000>>1)
18	#define FPGA_STATUS (0x80000000>>2)
19	#define FPGA_CONF_DONE (0x80000000>>3)
20	#define FPGA_DIN (0x80000000>>4)
21	#define FPGA_CCLK (0x80000000>>5)
22	#define MAN_RST (0x80000000>>6)
23	#define FPGA_SYS_RST (0x80000000>>7)
24	#define WD_WDI (0x80000000>>8)
25	#define TFT_RST (0x80000000>>9)
26	#define HISCON_GPIO1 (0x80000000>>10)
27	#define HISCON_GPIO2 (0x80000000>>11)
28	#define B2B_GPIO2 (0x80000000>>12)
29	#define CCU_GPIN (0x80000000>>13)
30	#define CCU_GPOUT (0x80000000>>14)
31	#define TFT_GPIO0 (0x80000000>>15)
32	#define TFT_GPIO1 (0x80000000>>16)
33	#define TFT_GPIO2 (0x80000000>>17)
34	#define TFT_GPIO3 (0x80000000>>18)
35	#define B2B_GPIO0 (0x80000000>>19)
36	#define B2B_GPIO1 (0x80000000>>20)
37	#define TFT_SPI_CPLD_CS (0x80000000>>21)
38	#define TFT_SPI_CS (0x80000000>>22)
39	#define CCU_PWR_EN (0x80000000>>23)
40	#define B2B_GPIO3 (0x80000000>>24)
41	#define CCU_PWR_STAT (0x80000000>>25)
42
43	#define MV_GPIO1_DAT (FPGA_CONFIG\|CCU_PWR_EN\|TFT_SPI_CPLD_CS)
44	#define MV_GPIO1_OUT (TFT_SPI_EN\|FPGA_CONFIG\|FPGA_DIN\|FPGA_CCLK\|CCU_PWR_EN\| \
45	TFT_SPI_CPLD_CS)
46	#define MV_GPIO1_ODE (FPGA_CONFIG\|MAN_RST)
47
48	/*
49	* GPIO Bank 2
50	*/
51	#define SPI_FLASH_WP (0x80000000>>10)
52	#define SYS_EEPROM_WP (0x80000000>>11)
53	#define SPI_FLASH_CS (0x80000000>>22)
54
55	#define MV_GPIO2_DAT (SYS_EEPROM_WP\|SPI_FLASH_CS)
56	#define MV_GPIO2_OUT (SPI_FLASH_WP\|SYS_EEPROM_WP\|SPI_FLASH_CS)
57	#define MV_GPIO2_ODE 0
58
59	void mergerbox_tft_dim(u16 value);
60
61	#endif
62		1	/*

board/matrix_vision/mergerbox/pci.c

View file @ e7a5656

1	/*		File was deleted
2	* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
3	*
4	* Copyright (C) 2011 Matrix Vision GmbH
5	* Andre Schwarz <andre.schwarz@matrix-vision.de>
6	*
7	* SPDX-License-Identifier: GPL-2.0+
8	*/
9
10	#include <common.h>
11	#include <mpc83xx.h>
12	#include <pci.h>
13	#include <asm/io.h>
14	#include <asm/fsl_mpc83xx_serdes.h>
15	#include "mergerbox.h"
16	#include "fpga.h"
17	#include "../common/mv_common.h"
18
19	static struct pci_region pci_regions[] = {
20	{
21	.bus_start = CONFIG_SYS_PCI_MEM_BASE,
22	.phys_start = CONFIG_SYS_PCI_MEM_PHYS,
23	.size = CONFIG_SYS_PCI_MEM_SIZE,
24	.flags = PCI_REGION_MEM \| PCI_REGION_PREFETCH
25	},
26	{
27	.bus_start = CONFIG_SYS_PCI_MMIO_BASE,
28	.phys_start = CONFIG_SYS_PCI_MMIO_PHYS,
29	.size = CONFIG_SYS_PCI_MMIO_SIZE,
30	.flags = PCI_REGION_MEM
31	},
32	{
33	.bus_start = CONFIG_SYS_PCI_IO_BASE,
34	.phys_start = CONFIG_SYS_PCI_IO_PHYS,
35	.size = CONFIG_SYS_PCI_IO_SIZE,
36	.flags = PCI_REGION_IO
37	}
38	};
39
40	static struct pci_region pcie_regions_0[] = {
41	{
42	.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
43	.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
44	.size = CONFIG_SYS_PCIE1_MEM_SIZE,
45	.flags = PCI_REGION_MEM,
46	},
47	{
48	.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
49	.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
50	.size = CONFIG_SYS_PCIE1_IO_SIZE,
51	.flags = PCI_REGION_IO,
52	},
53	};
54
55	static struct pci_region pcie_regions_1[] = {
56	{
57	.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
58	.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
59	.size = CONFIG_SYS_PCIE2_MEM_SIZE,
60	.flags = PCI_REGION_MEM,
61	},
62	{
63	.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
64	.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
65	.size = CONFIG_SYS_PCIE2_IO_SIZE,
66	.flags = PCI_REGION_IO,
67	},
68	};
69
70	void pci_init_board(void)
71	{
72	volatile immap_t immr = (immap_t )CONFIG_SYS_IMMR;
73	volatile sysconf83xx_t *sysconf = &immr->sysconf;
74	volatile clk83xx_t clk = (clk83xx_t )&immr->clk;
75	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
76	volatile law83xx_t *pcie_law = sysconf->pcielaw;
77	struct pci_region *reg[] = { pci_regions };
78	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
79
80	volatile gpio83xx_t *gpio;
81	gpio = (gpio83xx_t *)&immr->gpio[0];
82
83	gpio->dat = MV_GPIO1_DAT;
84	gpio->odr = MV_GPIO1_ODE;
85	gpio->dir = MV_GPIO1_OUT;
86
87	gpio = (gpio83xx_t *)&immr->gpio[1];
88
89	gpio->dat = MV_GPIO2_DAT;
90	gpio->odr = MV_GPIO2_ODE;
91	gpio->dir = MV_GPIO2_OUT;
92
93	printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
94	immr->sysconf.sicrl);
95
96	/* Enable PCI_CLK[0:1] */
97	clk->occr \|= 0xc0000000;
98	udelay(2000);
99
100	mergerbox_init_fpga();
101	mv_load_fpga();
102
103	mergerbox_tft_dim(0);
104
105	/* Configure PCI Local Access Windows */
106	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
107	pci_law[0].ar = LBLAWAR_EN \| LBLAWAR_512MB;
108
109	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
110	pci_law[1].ar = LBLAWAR_EN \| LBLAWAR_1MB;
111
112	udelay(2000);
113
114	mpc83xx_pci_init(1, reg);
115
116	/* Deassert the resets in the control register */
117	out_be32(&sysconf->pecr1, 0xE0008000);
118	out_be32(&sysconf->pecr2, 0xE0008000);
119	udelay(2000);
120
121	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
122	out_be32(&pcie_law[0].ar, LBLAWAR_EN \| LBLAWAR_512MB);
123
124	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
125	out_be32(&pcie_law[1].ar, LBLAWAR_EN \| LBLAWAR_512MB);
126
127	mpc83xx_pcie_init(2, pcie_reg);
128	}
129		1	/*

board/matrix_vision/mergerbox/sm107.c

View file @ e7a5656

1	/*		File was deleted
2	* Copyright (C) 2011 Matrix Vision GmbH
3	* Andre Schwarz <andre.schwarz@matrix-vision.de>
4	*
5	* SPDX-License-Identifier: GPL-2.0+
6	*/
7
8	#include <common.h>
9	#include <asm/io.h>
10	#include <ns16550.h>
11	#include <netdev.h>
12	#include <sm501.h>
13	#include <pci.h>
14	#include "../common/mv_common.h"
15
16	#ifdef CONFIG_VIDEO
17	static const SMI_REGS init_regs_800x480[] = {
18	/* set endianess to little endian */
19	{0x0005c, 0x00000000},
20	/* PCI drive 12mA */
21	{0x00004, 0x42401001},
22	/* current clock */
23	{0x0003c, 0x310a1818},
24	/* clocks for pm0... */
25	{0x00040, 0x0002184f},
26	{0x00044, 0x2a1a0a01},
27	/* GPIO */
28	{0x10008, 0x00000000},
29	{0x1000C, 0x00000000},
30	/* panel control regs */
31	{0x80000, 0x0f017106},
32	{0x80004, 0x0},
33	{0x80008, 0x0},
34	{0x8000C, 0x00000000},
35	{0x80010, 0x0c800c80},
36	/* width 0x320 */
37	{0x80014, 0x03200000},
38	/* height 0x1e0 */
39	{0x80018, 0x01E00000},
40	{0x8001C, 0x0},
41	{0x80020, 0x01df031f},
42	{0x80024, 0x041f031f},
43	{0x80028, 0x00800347},
44	{0x8002C, 0x020c01df},
45	{0x80030, 0x000201e9},
46	{0x80200, 0x00000000},
47	/* ZV[0:7] */
48	{0x00008, 0x00ff0000},
49	/* 24-Bit TFT */
50	{0x0000c, 0x3f000000},
51	{0, 0}
52	};
53
54	/*
55	* Returns SM107 register base address. First thing called in the driver.
56	*/
57	unsigned int board_video_init(void)
58	{
59	pci_dev_t devbusfn;
60	u32 addr;
61
62	devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
63	if (devbusfn != -1) {
64	pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1,
65	(u32 *)&addr);
66	return addr & 0xfffffffe;
67	}
68
69	return 0;
70	}
71
72	/*
73	* Called after initializing the SM501 and before clearing the screen.
74	*/
75	void board_validate_screen(unsigned int base)
76	{
77	}
78
79	/*
80	* Returns SM107 framebuffer address
81	*/
82	unsigned int board_video_get_fb(void)
83	{
84	pci_dev_t devbusfn;
85	u32 addr;
86
87	devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
88	if (devbusfn != -1) {
89	pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0,
90	(u32 *)&addr);
91	addr &= 0xfffffffe;
92	#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
93	addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
94	#endif
95	return addr;
96	}
97
98	printf("board_video_get_fb(): FAILED\n");
99
100	return 0;
101	}
102
103	/*
104	* Return a pointer to the initialization sequence.
105	*/
106	const SMI_REGS *board_get_regs(void)
107	{
108	return init_regs_800x480;
109	}
110
111	int board_get_width(void)
112	{
113	return 800;
114	}
115
116	int board_get_height(void)
117	{
118	return 480;
119	}
120	#endif
121		1	/*

board/matrix_vision/mvblm7/.gitignore

View file @ e7a5656

1	bootscript.img		File was deleted
2		1	bootscript.img

board/matrix_vision/mvblm7/Kconfig

View file @ e7a5656

1	if TARGET_MVBLM7		File was deleted
2
3	config SYS_BOARD
4	default "mvblm7"
5
6	config SYS_VENDOR
7	default "matrix_vision"
8
9	config SYS_CONFIG_NAME
10	default "MVBLM7"
11
12	endif
13		1	if TARGET_MVBLM7

board/matrix_vision/mvblm7/MAINTAINERS

View file @ e7a5656

1	MVBLM7 BOARD		File was deleted
2	#M: Andre Schwarz <andre.schwarz@matrix-vision.de>
3	S: Orphan (since 2014-03)
4	F: board/matrix_vision/mvblm7/
5	F: include/configs/MVBLM7.h
6	F: configs/MVBLM7_defconfig
7		1	MVBLM7 BOARD

board/matrix_vision/mvblm7/Makefile

View file @ e7a5656

1	#		File was deleted
2	# Copyright (C) Freescale Semiconductor, Inc. 2006.
3	#
4	# SPDX-License-Identifier: GPL-2.0+
5	#
6
7	obj-y := mvblm7.o pci.o fpga.o
8
9	extra-y := bootscript.img
10
11	MKIMAGEFLAGS_bootscript.image := -T script -C none -n M7_script
12
13	$(obj)/bootscript.img: $(src)/bootscript
14	$(call cmd,mkimage)
15		1	#

board/matrix_vision/mvblm7/README.mvblm7

View file @ e7a5656

1	Matrix Vision mvBlueLYNX-M7 (mvBL-M7)		File was deleted
2	-------------------------------------
3
4	1. Board Description
5
6	The mvBL-M7 is a 120x120mm single board computing platform
7	with strong focus on stereo image processing applications.
8
9	Power Supply is either VDC 12-48V or Pover over Ethernet (PoE)
10	on any port (requires add-on board).
11
12	2 System Components
13
14	2.1 CPU
15	Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb.
16	512MByte DDR-II memory @ 133MHz.
17	8 MByte Nor Flash on local bus.
18	2 Vitesse VSC8601 RGMII ethernet Phys.
19	1 USB host controller over ULPI I/F.
20	2 serial ports. Console running on ttyS0 @ 115200 8N1.
21	1 SD-Card slot connected to SPI.
22	System configuration (HRCW) is taken from I2C EEPROM.
23
24	2.2 PCI
25	A miniPCI Type-III socket is present. PCI clock fixed at 66MHz.
26
27	2.3 FPGA
28	Altera Cyclone-II EP2C20/35 with PCI DMA engines.
29	Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces.
30	Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash.
31
32	2.3.1 I/O @ FPGA
33	2x8 Outputs : Infineon High-Side Switches to Main Supply.
34	2x8 Inputs : Programmable input threshold + trigger capabilities
35	2 dedicated flash interfaces for illuminator boards.
36	Cross trigger for chaining several boards.
37
38	2.4 I2C
39	Bus1:
40	MAX5381 DAC @ 0x60 for 1st digital input threshold.
41	LM75 @ 0x90 for temperature monitoring.
42	EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
43	1st image sensor interface (slave addresses depend on sensor)
44	Bus2:
45	MAX5381 DAC @ 0x60 for 2nd digital input threshold.
46	2nd image sensor interface (slave addresses depend on sensor)
47
48	3 Flash layout.
49
50	reset vector is 0xFFF00100, i.e. "HIGHBOOT".
51
52	FF800000 environment
53	FF802000 redundant environment
54	FF804000 u-boot script image
55	FF806000 redundant u-boot script image
56	FF808000 device tree blob
57	FF80A000 redundant device tree blob
58	FF80C000 tbd.
59	FF80E000 tbd.
60	FF810000 kernel
61	FFC00000 root FS
62	FFF00000 u-boot
63	FFF80000 FPGA raw bit file
64
65	mtd partitions are propagated to linux kernel via device tree blob.
66
67	4 Booting
68
69	On startup the bootscript @ FF804000 is executed. This script can be
70	exchanged easily. Default boot mode is "boot from flash", i.e. system
71	works stand-alone.
72
73	This behaviour depends on some environment variables :
74
75	"netboot" : yes ->try dhcp/bootp and boot from network.
76	A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
77	DHCP server configuration, e.g. to provide different images to
78	different devices.
79
80	During netboot the system tries to get 3 image files:
81	1. Kernel - name + data is given during BOOTP.
82	2. Initrd - name is stored in "initrd_name"
83	3. device tree blob - name is stored in "dtb_name"
84	Fallback files are the flash versions.
85		1	Matrix Vision mvBlueLYNX-M7 (mvBL-M7)

board/matrix_vision/mvblm7/bootscript

View file @ e7a5656

1	echo		File was deleted
2	echo "==== running autoscript ===="
3	echo
4	setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
5	setenv ramkernel setenv kernel_boot \${loadaddr}
6	setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
7	setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
8	setenv bootfromflash run flashkernel cpird ramparam addcons bootdtb
9	setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
10	setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
11	setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
12	setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
13	if test ${console} = yes;
14	then
15	setenv addcons setenv bootargs \${bootargs} console=ttyS\${console_nr},\${baudrate}N8
16	else
17	setenv addcons setenv bootargs \${bootargs} console=tty0
18	fi
19	setenv set_static_ip setenv ipaddr \${static_ipaddr}
20	setenv set_static_nm setenv netmask \${static_netmask}
21	setenv set_static_gw setenv gatewayip \${static_gateway}
22	setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
23	setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
24	if test ${autoscript_boot} != no;
25	then
26	if test ${netboot} = yes;
27	then
28	bootp
29	if test $? = 0;
30	then
31	echo "=== bootp succeeded -> netboot ==="
32	run set_ip
33	run getdtb rundtb bootfromnet ramparam addcons bootdtb
34	else
35	echo "=== netboot failed ==="
36	fi
37	fi
38	run set_static_ip set_static_nm set_static_gw set_ip
39	echo "=== bootfromflash ==="
40	run cpdtb rundtb bootfromflash
41	else
42	echo "=== boot stopped with autoscript_boot no ==="
43	fi
44		1	echo

board/matrix_vision/mvblm7/fpga.c

View file @ e7a5656

1	/*		File was deleted
2	* (C) Copyright 2002
3	* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4	* Keith Outwater, keith_outwater@mvis.com.
5	*
6	* (C) Copyright 2008
7	* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
8	*
9	* SPDX-License-Identifier: GPL-2.0+
10	*/
11
12	#include <common.h>
13	#include <ACEX1K.h>
14	#include <command.h>
15	#include "fpga.h"
16	#include "mvblm7.h"
17
18	#ifdef FPGA_DEBUG
19	#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
20	#else
21	#define fpga_debug(fmt, args...)
22	#endif
23
24	Altera_CYC2_Passive_Serial_fns altera_fns = {
25	fpga_null_fn,
26	fpga_config_fn,
27	fpga_status_fn,
28	fpga_done_fn,
29	fpga_wr_fn,
30	fpga_null_fn,
31	fpga_null_fn,
32	};
33
34	Altera_desc cyclone2 = {
35	Altera_CYC2,
36	passive_serial,
37	Altera_EP2C20_SIZE,
38	(void *) &altera_fns,
39	NULL,
40	0
41	};
42
43	DECLARE_GLOBAL_DATA_PTR;
44
45	int mvblm7_init_fpga(void)
46	{
47	fpga_debug("Initialize FPGA interface\n");
48	fpga_init();
49	fpga_add(fpga_altera, &cyclone2);
50	fpga_config_fn(0, 1, 0);
51	udelay(60);
52
53	return 1;
54	}
55
56	int fpga_null_fn(int cookie)
57	{
58	return 0;
59	}
60
61	int fpga_config_fn(int assert, int flush, int cookie)
62	{
63	volatile immap_t im = (volatile immap_t )CONFIG_SYS_IMMR;
64	volatile gpio83xx_t gpio = (volatile gpio83xx_t )&im->gpio[0];
65	u32 dvo = gpio->dat;
66
67	fpga_debug("SET config : %s\n", assert ? "low" : "high");
68	if (assert)
69	dvo \|= FPGA_CONFIG;
70	else
71	dvo &= ~FPGA_CONFIG;
72
73	if (flush)
74	gpio->dat = dvo;
75
76	return assert;
77	}
78
79	int fpga_done_fn(int cookie)
80	{
81	volatile immap_t im = (volatile immap_t )CONFIG_SYS_IMMR;
82	volatile gpio83xx_t gpio = (volatile gpio83xx_t )&im->gpio[0];
83	int result = 0;
84
85	udelay(10);
86	fpga_debug("CONF_DONE check ... ");
87	if (gpio->dat & FPGA_CONF_DONE) {
88	fpga_debug("high\n");
89	result = 1;
90	} else
91	fpga_debug("low\n");
92
93	return result;
94	}
95
96	int fpga_status_fn(int cookie)
97	{
98	volatile immap_t im = (volatile immap_t )CONFIG_SYS_IMMR;
99	volatile gpio83xx_t gpio = (volatile gpio83xx_t )&im->gpio[0];
100	int result = 0;
101
102	fpga_debug("STATUS check ... ");
103	if (gpio->dat & FPGA_STATUS) {
104	fpga_debug("high\n");
105	result = 1;
106	} else
107	fpga_debug("low\n");
108
109	return result;
110	}
111
112	int fpga_clk_fn(int assert_clk, int flush, int cookie)
113	{
114	volatile immap_t im = (volatile immap_t )CONFIG_SYS_IMMR;
115	volatile gpio83xx_t gpio = (volatile gpio83xx_t )&im->gpio[0];
116	u32 dvo = gpio->dat;
117
118	fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
119	if (assert_clk)
120	dvo \|= FPGA_CCLK;
121	else
122	dvo &= ~FPGA_CCLK;
123
124	if (flush)
125	gpio->dat = dvo;
126
127	return assert_clk;
128	}
129
130	static inline int _write_fpga(u8 val, int dump)
131	{
132	volatile immap_t im = (volatile immap_t )CONFIG_SYS_IMMR;
133	volatile gpio83xx_t gpio = (volatile gpio83xx_t )&im->gpio[0];
134	int i;
135	u32 dvo = gpio->dat;
136
137	if (dump)
138	fpga_debug(" %02x -> ", val);
139	for (i = 0; i < 8; i++) {
140	dvo &= ~FPGA_CCLK;
141	gpio->dat = dvo;
142	dvo &= ~FPGA_DIN;
143	if (dump)
144	fpga_debug("%d ", val&1);
145	if (val & 1)
146	dvo \|= FPGA_DIN;
147	gpio->dat = dvo;
148	dvo \|= FPGA_CCLK;
149	gpio->dat = dvo;
150	val >>= 1;
151	}
152	if (dump)
153	fpga_debug("\n");
154
155	return 0;
156	}
157
158	int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
159	{
160	unsigned char data = (unsigned char ) buf;
161	int i;
162
163	fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
164	for (i = 0; i < len; i++)
165	_write_fpga(data[i], 0);
166	fpga_debug("\n");
167
168	return FPGA_SUCCESS;
169	}
170		1	/*

board/matrix_vision/mvblm7/fpga.h

View file @ e7a5656

1	/*		File was deleted
2	* (C) Copyright 2002
3	* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4	* Keith Outwater, keith_outwater@mvis.com.
5	*
6	* SPDX-License-Identifier: GPL-2.0+
7	*/
8
9	extern int mvblm7_init_fpga(void);
10
11	extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
12	extern int fpga_status_fn(int cookie);
13	extern int fpga_config_fn(int assert, int flush, int cookie);
14	extern int fpga_done_fn(int cookie);
15	extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
16	extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
17	extern int fpga_null_fn(int cookie);
18		1	/*

board/matrix_vision/mvblm7/mvblm7.c

View file @ e7a5656

1	/*		File was deleted
2	* Copyright (C) Freescale Semiconductor, Inc. 2006.
3	*
4	* (C) Copyright 2008
5	* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
6	*
7	* SPDX-License-Identifier: GPL-2.0+
8	*/
9
10	#include <common.h>
11	#include <ioports.h>
12	#include <mpc83xx.h>
13	#include <asm/mpc8349_pci.h>
14	#include <pci.h>
15	#include <spi.h>
16	#include <asm/mmu.h>
17	#if defined(CONFIG_OF_LIBFDT)
18	#include <libfdt.h>
19	#endif
20
21	#include "../common/mv_common.h"
22	#include "mvblm7.h"
23
24	int fixed_sdram(void)
25	{
26	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
27	u32 msize = 0;
28	u32 ddr_size;
29	u32 ddr_size_log2;
30	char *s = getenv("ddr_size");
31
32	msize = CONFIG_SYS_DDR_SIZE;
33	if (s) {
34	u32 env_ddr_size = simple_strtoul(s, NULL, 10);
35	if (env_ddr_size == 512)
36	msize = 512;
37	}
38
39	for (ddr_size = msize << 20, ddr_size_log2 = 0;
40	(ddr_size > 1);
41	ddr_size = ddr_size >> 1, ddr_size_log2++) {
42	if (ddr_size & 1)
43	return -1;
44	}
45	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
46	im->sysconf.ddrlaw[0].ar = LAWAR_EN \| ((ddr_size_log2 - 1) &
47	LAWAR_SIZE);
48
49	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
50	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
51	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
52	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
53	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
54	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
55	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
56	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
57	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
58	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
59	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
60	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
61
62	asm("sync;isync");
63	udelay(600);
64
65	im->ddr.sdram_cfg \|= SDRAM_CFG_MEM_EN;
66
67	asm("sync;isync");
68	udelay(500);
69
70	return msize;
71	}
72
73	phys_size_t initdram(int board_type)
74	{
75	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
76	u32 msize = 0;
77
78	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
79	return -1;
80
81	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
82	msize = fixed_sdram();
83
84	/* return total bus RAM size(bytes) */
85	return msize * 1024 * 1024;
86	}
87
88	int misc_init_r(void)
89	{
90	char *s = getenv("reset_env");
91
92	if (s) {
93	mv_reset_environment();
94	}
95
96	return 0;
97	}
98
99	int checkboard(void)
100	{
101	puts("Board: Matrix Vision mvBlueLYNX-M7\n");
102
103	return 0;
104	}
105
106	#ifdef CONFIG_HARD_SPI
107	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
108	{
109	return bus == 0 && cs == 0;
110	}
111
112	void spi_cs_activate(struct spi_slave *slave)
113	{
114	volatile gpio83xx_t iopd = &((immap_t )CONFIG_SYS_IMMR)->gpio[0];
115
116	iopd->dat &= ~MVBLM7_MMC_CS;
117	}
118
119	void spi_cs_deactivate(struct spi_slave *slave)
120	{
121	volatile gpio83xx_t iopd = &((immap_t )CONFIG_SYS_IMMR)->gpio[0];
122
123	iopd->dat \|= ~MVBLM7_MMC_CS;
124	}
125	#endif
126
127	#if defined(CONFIG_OF_BOARD_SETUP)
128	void ft_board_setup(void blob, bd_t bd)
129	{
130	ft_cpu_setup(blob, bd);
131	#ifdef CONFIG_PCI
132	ft_pci_setup(blob, bd);
133	#endif
134	}
135
136	#endif
137		1	/*

board/matrix_vision/mvblm7/mvblm7.h

View file @ e7a5656

1	#ifndef __MVBC_H__		File was deleted
2	#define __MVBC_H__
3
4	#define MV_GPIO
5
6	#define FPGA_CONFIG 0x80000000
7	#define FPGA_CCLK 0x40000000
8	#define FPGA_DIN 0x20000000
9	#define FPGA_STATUS 0x10000000
10	#define FPGA_CONF_DONE 0x08000000
11
12	#define WD_WDI 0x00400000
13	#define WD_TS 0x00200000
14	#define MAN_RST 0x00100000
15
16	#define MV_GPIO_DAT (WD_TS)
17	#define MV_GPIO_OUT (FPGA_CONFIG\|FPGA_DIN\|FPGA_CCLK\|MVBLM7_MMC_CS)
18	#define MV_GPIO_ODE (FPGA_CONFIG\|MAN_RST)
19
20	#endif
21		1	#ifndef __MVBC_H__

board/matrix_vision/mvblm7/pci.c

View file @ e7a5656

1	/*		File was deleted
2	* Copyright (C) Freescale Semiconductor, Inc. 2006.
3	*
4	* (C) Copyright 2008
5	* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
6	*
7	* SPDX-License-Identifier: GPL-2.0+
8	*/
9
10	#include <common.h>
11	#if defined(CONFIG_OF_LIBFDT)
12	#include <libfdt.h>
13	#endif
14	#include <pci.h>
15	#include <mpc83xx.h>
16	#include <fpga.h>
17	#include "mvblm7.h"
18	#include "fpga.h"
19	#include "../common/mv_common.h"
20
21	DECLARE_GLOBAL_DATA_PTR;
22
23	static struct pci_region pci_regions[] = {
24	{
25	bus_start: CONFIG_SYS_PCI1_MEM_BASE,
26	phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
27	size: CONFIG_SYS_PCI1_MEM_SIZE,
28	flags: PCI_REGION_MEM \| PCI_REGION_PREFETCH
29	},
30	{
31	bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
32	phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
33	size: CONFIG_SYS_PCI1_MMIO_SIZE,
34	flags: PCI_REGION_MEM
35	},
36	{
37	bus_start: CONFIG_SYS_PCI1_IO_BASE,
38	phys_start: CONFIG_SYS_PCI1_IO_PHYS,
39	size: CONFIG_SYS_PCI1_IO_SIZE,
40	flags: PCI_REGION_IO
41	}
42	};
43
44	void pci_init_board(void)
45	{
46	int i;
47	volatile immap_t *immr;
48	volatile pcictrl83xx_t *pci_ctrl;
49	volatile gpio83xx_t *gpio;
50	volatile clk83xx_t *clk;
51	volatile law83xx_t *pci_law;
52	struct pci_region *reg[] = { pci_regions };
53
54	immr = (immap_t *) CONFIG_SYS_IMMR;
55	clk = (clk83xx_t *) &immr->clk;
56	pci_ctrl = immr->pci_ctrl;
57	pci_law = immr->sysconf.pcilaw;
58	gpio = (volatile gpio83xx_t *)&immr->gpio[0];
59
60	gpio->dat = MV_GPIO_DAT;
61	gpio->odr = MV_GPIO_ODE;
62	gpio->dir = MV_GPIO_OUT;
63
64	printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
65	immr->sysconf.sicrl);
66
67	mvblm7_init_fpga();
68	mv_load_fpga();
69
70	gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN\|FPGA_CCLK);
71
72	/* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */
73	clk->occr = 0xc0000000;
74
75	pci_ctrl[0].gcr = 0;
76	udelay(2000);
77	pci_ctrl[0].gcr = 1;
78
79	for (i = 0; i < 1000; ++i)
80	udelay(1000);
81
82	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
83	pci_law[0].ar = LBLAWAR_EN \| LBLAWAR_1GB;
84
85	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
86	pci_law[1].ar = LBLAWAR_EN \| LBLAWAR_1MB;
87
88	mpc83xx_pci_init(1, reg);
89	}
90		1	/*

configs/MERGERBOX_defconfig

View file @ e7a5656

1	CONFIG_PPC=y		File was deleted
2	CONFIG_MPC83xx=y
3	CONFIG_TARGET_MERGERBOX=y
4		1	CONFIG_PPC=y

configs/MVBLM7_defconfig

View file @ e7a5656

1	CONFIG_PPC=y		File was deleted
2	CONFIG_MPC83xx=y
3	CONFIG_TARGET_MVBLM7=y
4		1	CONFIG_PPC=y

doc/README.scrapyard

Diff comments View file @ e7a5656

 Over time, support for more and more boards gets added to U-Boot -
 while other board support code dies a silent death caused by
 negligence in combination with ordinary bitrot.  Sometimes this goes
 by unnoticed, but often build errors will result.  If nobody cares any
 more to resolve such problems, then the code is really dead and will
 be removed from the U-Boot source tree.  The remainders rest in piece
 in the imperishable depths of the git history.  This document tries to
 maintain a list of such former fellows, so archaeologists can check
 easily if there is something they might want to dig for...
 The list should be sorted in reverse chronological order.
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+MERGERBOX        powerpc     mpc83xx        -           -           Andre Schwarz <andre.schwarz@matrix-vision.de>
+MVBLM7           powerpc     mpc83xx        -           -           Andre Schwarz <andre.schwarz@matrix-vision.de>
 bluestone        powerpc     ppc4xx         -           -           Tirumala Marri <tmarri@apm.com>
 CRAYL1           powerpc     ppc4xx         -           -           David Updegraff <dave@cray.com>
 KAREF            powerpc     ppc4xx         -           -           Travis Sawyer <travis.sawyer@sandburst.com>
 METROBOX         powerpc     ppc4xx         -           -           Travis Sawyer <travis.sawyer@sandburst.com>
 PK1C20           nios2       -              70fbc461    2014-08-24  Scott McNutt <smcnutt@psyent.com>
 PCI5441          nios2       -              70fbc461    2014-08-24  Scott McNutt <smcnutt@psyent.com>
 flagadm          powerpc     mpc8xx         aec6f8c5    2014-08-22  Kári Davíðsson <kd@flaga.is>
 gen860t          powerpc     mpc8xx         6bde1ec1    2014-08-22  Keith Outwater <Keith_Outwater@mvis.com>
 sixnet           powerpc     mpc8xx         4723ce49    2014-08-22  Dave Ellis <DGE@sixnetio.com>
 svm_sc8xx        powerpc     mpc8xx         d1a4aafd    2014-08-22  John Zhan <zhanz@sinovee.com>
 stxxtc           powerpc     mpc8xx         0ace4d9d    2014-08-22  Dan Malek <dan@embeddedalley.com>
 omap5912osk      arm         arm926ejs      62d636aa    2014-08-22  Rishi Bhattacharya <rishi@ti.com>
 p1023rds         powerpc     mpc85xx        d0bc5140    2014-07-22  Roy Zang <tie-fei.zang@freescale.com>
 spc1920          powerpc     mpc8xx         98ad54be    2014-07-07
 v37              powerpc     mpc8xx         b8c1438a    2014-07-07
 fads             powerpc     mpc8xx         03f9d7d1    2014-07-07
 netphone         powerpc     mpc8xx         c51c1c9a    2014-07-07
 netta2           powerpc     mpc8xx         c51c1c9a    2014-07-07
 netta            powerpc     mpc8xx         c51c1c9a    2014-07-07
 rbc823           powerpc     mpc8xx         c750b9c0    2014-07-07
 quantum          powerpc     mpc8xx         0657e46e    2014-07-07
 RPXlite_dw       powerpc     mpc8xx         0657e46e    2014-07-07
 qs850            powerpc     mpc8xx         dab0f762    2014-07-07
 qs860t           powerpc     mpc8xx         dab0f762    2014-07-07
 simpc8313        powerpc     mpc83xx        7445207f    2014-06-05  Ron Madrid <info@sheldoninst.com>
 hidden_dragon    powerpc     mpc824x        3fe1a854    2014-05-30  Yusdi Santoso <yusdi_santoso@adaptec.com>
 debris           powerpc     mpc824x        7edb1f7b    2014-05-30  Sangmoon Kim <dogoil@etinsys.com>
 kvme080          powerpc     mpc824x        2868f862    2014-05-30  Sangmoon Kim <dogoil@etinsys.com>
 ep8248           powerpc     mpc8260        49ad566d    2014-05-30  Yuli Barcohen <yuli@arabellasw.com>
 ispan            powerpc     mpc8260        80bae39a    2014-05-30  Yuli Barcohen <yuli@arabellasw.com>
 rattler          powerpc     mpc8260        d0664db4    2014-05-30  Yuli Barcohen <yuli@arabellasw.com>
 zpc1900          powerpc     mpc8260        6f80bb48    2014-05-30  Yuli Barcohen <yuli@arabellasw.com>
 mpc8260ads       powerpc     mpc8260        facb6725    2014-05-30  Yuli Barcohen <yuli@arabellasw.com>
 adder            powerpc     mpc8xx         373a9788    2014-05-30  Yuli Barcohen <yuli@arabellasw.com>
 quad100hd        powerpc     ppc405ep       3569571d    2014-05-30  Gary Jennejohn <gljennjohn@googlemail.com>
 incaip           mips        mips32         538cf92c    2014-04-20  Wolfgang Denk <wd@denx.de>
 lubbock          arm         pxa            36bf57b     2014-04-18  Kyle Harris <kharris@nexus-tech.net>
 EVB64260	 powerpc     mpc824x        bb3aef9	2014-04-18
 MOUSSE           powerpc     mpc824x        03f2ecc     2014-04-18
 rsdproto         powerpc     mpc8260        8b043e6     2014-04-18
 RPXsuper         powerpc     mpc8260        0ebf5f5     2014-04-18
 RPXClassic       powerpc     mpc8xx         4fb3925     2014-04-18
 RPXlite          powerpc     mpc8xx         4fb3925     2014-04-18
 FADS		 powerpc     mpc8xx	    aa6e1e4	2014-04-18
 genietv          powerpc     mpc8xx         b8a49bd     2014-04-18
 mbx8xx           powerpc     mpc8xx         d6b11fd     2014-04-18
 nx823            powerpc     mpc8xx         a146e8b     2014-04-18
 idmr             m68k        mcf52x2        ba650e9b    2014-01-28
 M5271EVB         m68k        mcf52x2        ba650e9b    2014-01-28
 dvl_host         arm         ixp            e317de6b    2014-01-28  Michael Schwingen <michael@schwingen.org>
 actux4           arm         ixp            6ff7aafa    2014-01-28  Michael Schwingen <michael@schwingen.org>
 actux3           arm         ixp            38da33f3    2014-01-28  Michael Schwingen <michael@schwingen.org>
 actux2           arm         ixp            13e0ee7f    2014-01-28  Michael Schwingen <michael@schwingen.org>
 actux1           arm         ixp            373ee048    2014-01-28  Michael Schwingen <michael@schwingen.org>
 mx1ads           arm         arm920t        e570aca9    2014-01-13
 mini2440         arm         arm920t        af5b9b1f    2014-01-13  Gabriel Huau <contact@huau-gabriel.fr>
 omap730p2        arm         arm926ejs      79c5c08d    2013-11-11
 pn62             powerpc     mpc824x        649acfe1    2013-11-11  Wolfgang Grandegger <wg@grandegger.com>
 pdnb3            arm         ixp            304db0b     2013-09-24  Stefan Roese <sr@denx.de>
 scpu             arm         ixp            304db0b     2013-09-24  Stefan Roese <sr@denx.de>
 omap1510inn      arm         arm925t        0610a16     2013-09-23  Kshitij Gupta <kshitij@ti.com>
 CANBT            powerpc     405CR          fb8f4fd     2013-08-07  Matthias Fuchs <matthias.fuchs@esd.eu>
 omap2420h4       arm         omap24xx       7f5eef9     2013-06-04  Richard Woodruff <r-woodruff2@ti.com>
 Alaska8220       powerpc     mpc8220        d6ed322     2013-05-11
 Yukon8220        powerpc     mpc8220        d6ed322     2013-05-11
 sorcery          powerpc     mpc8220        d6ed322     2013-05-11
 smdk6400         arm         arm1176        52587f1     2013-04-12  Zhong Hongbo <bocui107@gmail.com>
 ns9750dev        arm         arm926ejs      4cfc611     2013-02-28  Markus Pietrek <mpietrek@fsforth.de>
 eNET             x86         x86            7e8c53d     2013-02-14  Graeme Russ <graeme.russ@gmail.com>
 PCIPPC2          powerpc     MPC740/MPC750  7c9e89b     2013-02-07  Wolfgang Denk <wd@denx.de>
 PCIPPC6          powerpc     MPC740/MPC750  7c9e89b     2013-02-07  Wolfgang Denk <wd@denx.de>
 AMX860           powerpc     mpc860         1b0757e     2012-10-28  Wolfgang Denk <wd@denx.de>
 c2mon            powerpc     mpc855         1b0757e     2012-10-28  Wolfgang Denk <wd@denx.de>
 EP88x            powerpc     mpc885         1b0757e     2012-10-28
 ETX094           powerpc     mpc850         1b0757e     2012-10-28  Wolfgang Denk <wd@denx.de>
 IAD210           powerpc     mpc860         1b0757e     2012-10-28  -
 LANTEC           powerpc     mpc850         1b0757e     2012-10-28  Wolfgang Denk <wd@denx.de>
 SCM              powerpc     mpc8260        1b0757e     2012-10-28  Wolfgang Grandegger <wg@denx.de>
 SX1              arm         arm925t        53c4154     2012-10-26
 TQM85xx          powerpc     MPC85xx        d923a5d     2012-10-04  Stefan Roese <sr@denx.de>
 ADCIOP           powerpc     ppc4xx         99bcad1     2012-09-19  Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 DASA_SIM         powerpc     ppc4xx         99bcad1     2012-09-19  Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 apollon          arm         omap24xx       535c74f     2012-09-18  Kyungmin Park <kyungmin.park@samsung.com>
 tb0229           mips        mips32         3f3110d     2011-12-12
 rmu              powerpc     MPC850         fb82fd7     2011-12-07  Wolfgang Denk <wd@denx.de>
 OXC              powerpc     MPC8240        309a292     2011-12-07
 BAB7xx           powerpc     MPC740/MPC750  c53043b     2011-12-07  Frank Gottschling <fgottschling@eltec.de>
 xm250            arm         pxa            c477d72     2011-11-25
 pleb2            arm         pxa            d299173     2011-11-25
 cradle           arm         pxa            00c4aca     2011-11-25  Kyle Harris <kharris@nexus-tech.net>
 cerf250          arm         pxa            f13eba6     2011-11-25  Prakash Kumar <prakash@embedx.com>
 mpq101           powerpc     mpc85xx        e877fab     2011-10-23  Alex Dubov <oakad@yahoo.com>
 ixdpg425         arm         ixp            0ca8eb7     2011-09-22  Stefan Roese <sr@denx.de>
 ixdp425          arm         ixp            0ca8eb7     2011-09-22  Kyle Harris <kharris@nexus-tech.net>
 zylonite         arm         pxa            b66521a     2011-09-05
 shannon          arm         sa1100         5df092d     2011-09-05  Rolf Offermanns <rof@sysgo.de>
 modnet50         arm         arm720t        9c62815     2011-09-05  Thomas Elste <info@elste.org>
 lpc2292sodimm    arm         arm720t        d1a067a     2011-09-05
 lart             arm         sa1100         3d57573     2011-09-05  Alex Züpke <azu@sysgo.de>
 impa7            arm         arm720t        c1f8750     2011-09-05  Marius Gröger <mag@sysgo.de>
 gcplus           arm         sa1100         2c650e2     2011-09-05  George G. Davis <gdavis@mvista.com>
 evb4510          arm         arm720t        26e670e     2011-09-05  Curt Brune <curt@cucy.com>
 ep7312           arm         arm720t        c8f63b4     2011-09-05  Marius Gröger <mag@sysgo.de>
 dnp1110          arm         sa1100         fc5e5ce     2011-09-05  Alex Züpke <azu@sysgo.de>
 SMN42            arm         arm720t        6aac646     2011-09-05
 at91rm9200dk     arm         arm920t        1c85752     2011-07-17
 m501sk           arm         arm920t        b1a2bd4     2011-07-17
 kb9202           arm         arm920t        5bd3814     2011-07-17
 csb637           arm         arm920t        d14af08     2011-07-17
 cmc_pu2          arm         arm920t        37a9b4d     2011-07-17
 at91cap9adk      arm         arm926ejs      b550834     2011-07-17  Stelian Pop <stelian@popies.net>
 voiceblue        arm         arm925t        1b793a4     2011-07-17
 smdk2400         arm         arm920t        ad218a8     2011-07-17  Gary Jennejohn <garyj@denx.de>
 sbc2410x         arm         arm920t        1f7f0ed     2011-07-17
 netstar          arm         arm925t        6ea2405     2011-07-17
 mx1fs2           arm         arm920t        6962419     2011-07-17
 lpd7a404         arm         lh7a40x        957731e     2011-07-17
 edb9301          arm         arm920t        716f7ad     2011-07-17
 edb9302          arm         arm920t        716f7ad     2011-07-17
 edb9302a         arm         arm920t        716f7ad     2011-07-17
 edb9307          arm         arm920t        716f7ad     2011-07-17
 edb9307a         arm         arm920t        716f7ad     2011-07-17
 edb9312          arm         arm920t        716f7ad     2011-07-17
 edb9315          arm         arm920t        716f7ad     2011-07-17
 edb9315a         arm         arm920t        716f7ad     2011-07-17
 B2               arm         s3c44b0        5dcf536     2011-07-16  Andrea Scian <andrea.scian@dave-tech.it>
 armadillo        arm         arm720t        be28857     2011-07-16  Rowel Atienza <rowel@diwalabs.com>
 assabet          arm         sa1100         c91e90d     2011-07-16  George G. Davis <gdavis@mvista.com>
 trab             arm         S3C2400        566e5cf     2011-05-01  Gary Jennejohn <garyj@denx.de>
 mp2usb           ARM         AT91RM2900     ee986e2     2011-01-25  Eric Bénard <eric@eukrea.com>
 barco            powerpc     MPC8245        afaa27b     2010-11-23  Marc Leeman <marc.leeman@barco.com>
 ERIC             powerpc     405GP          d9ba451     2010-11-21  Swen Anderson <sand@peppercon.de>
 VoVPN-GW_100MHz  powerpc     MPC8260        26fe3d2     2010-10-24  Juergen Selent <j.selent@elmeg.de>
 xsengine         ARM         PXA2xx         4262a7c     2010-10-20
 wepep250         ARM         PXA2xx         7369478     2010-10-20  Peter Figuli <peposh@etc.sk>
 delta            ARM         PXA2xx         75e2035     2010-10-20
 NC650            powerpc     MPC852         333d86d     2010-10-19  Wolfgang Denk <wd@denx.de>
 CP850            powerpc     MPC852         333d86d     2010-10-19  Wolfgang Denk <wd@denx.de>
 logodl           ARM         PXA2xx         059e778     2010-10-18  August Hoeraendl <august.hoerandl@gmx.at>
 CCM              powerpc     MPC860         dff07e1     2010-10-06  Wolfgang Grandegger <wg@denx.de>
 PCU_E            powerpc     MPC860T        544d97e     2010-10-06  Wolfgang Denk <wd@denx.de>
 spieval          powerpc     MPC5200        69434e4     2010-09-19
 smmaco4          powerpc     MPC5200        9ddc3af     2010-09-19
 HMI10            powerpc     MPC823         77efe35     2010-09-19  Wolfgang Denk <wd@denx.de>
 GTH              powerpc     MPC860         0fe247b     2010-07-17  Thomas Lange <thomas@corelatus.se>
 AmigaOneG3SE     powerpc     74xx_7xx       953b7e6     2010-06-23
 suzaku           microblaze  -              4f18060     2009-10-03  Yasushi Shoji <yashi@atmark-techno.com>
 XUPV2P           microblaze  -              8fab49e     2008-12-10  Michal Simek <monstr@monstr.eu>
 MVS1             powerpc     MPC823         306620b     2008-08-26  Andre Schwarz <andre.schwarz@matrix-vision.de>
 adsvix           ARM         PXA27x         7610db1     2008-07-30  Adrian Filipi <adrian.filipi@eurotech.com>
 R5200            ColdFire    -              48ead7a     2008-03-31  Zachary P. Landau <zachary.landau@labxtechnologies.com>
 CPCI440          powerpc     440GP          b568fd2     2007-12-27  Matthias Fuchs <matthias.fuchs@esd-electronics.com>

include/configs/MERGERBOX.h

View file @ e7a5656

1	/*		File was deleted
2	* Copyright (C) 2007 Freescale Semiconductor, Inc.
3	*
4	* Copyright (C) 2011 Matrix Vision GmbH
5	* Andre Schwarz <andre.schwarz@matrix-vision.de>
6	*
7	* SPDX-License-Identifier: GPL-2.0+
8	*/
9
10	#ifndef __CONFIG_H
11	#define __CONFIG_H
12
13	#include <version.h>
14
15	/*
16	* High Level Configuration Options
17	*/
18	#define CONFIG_E300 1
19	#define CONFIG_MPC837x 1
20	#define CONFIG_MPC8377 1
21
22	#define CONFIG_SYS_TEXT_BASE 0xFC000000
23
24	#define CONFIG_PCI 1
25	#define CONFIG_PCI_INDIRECT_BRIDGE 1
26
27	#define CONFIG_MASK_AER_AO
28	#define CONFIG_DISPLAY_AER_FULL
29
30	#define CONFIG_MISC_INIT_R
31
32	/*
33	* On-board devices
34	*/
35	#define CONFIG_TSEC_ENET
36
37	/*
38	* System Clock Setup
39	*/
40	#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
41	#define CONFIG_PCIE
42	#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
43	#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
44
45	/*
46	* Hardware Reset Configuration Word stored in EEPROM.
47	*/
48	#define CONFIG_SYS_HRCW_LOW 0
49	#define CONFIG_SYS_HRCW_HIGH 0
50
51	/* Arbiter Configuration Register */
52	#define CONFIG_SYS_ACR_PIPE_DEP 3
53	#define CONFIG_SYS_ACR_RPTCNT 3
54
55	/* System Priority Control Regsiter */
56	#define CONFIG_SYS_SPCR_TSECEP 3
57
58	/* System Clock Configuration Register */
59	#define CONFIG_SYS_SCCR_TSEC1CM 3
60	#define CONFIG_SYS_SCCR_TSEC2CM 0
61	#define CONFIG_SYS_SCCR_SDHCCM 3
62	#define CONFIG_SYS_SCCR_ENCCM 3 /* also clock for I2C-1 */
63	#define CONFIG_SYS_SCCR_USBDRCM CONFIG_SYS_SCCR_ENCCM /* must match */
64	#define CONFIG_SYS_SCCR_PCIEXP1CM 3
65	#define CONFIG_SYS_SCCR_PCIEXP2CM 3
66	#define CONFIG_SYS_SCCR_PCICM 1
67	#define CONFIG_SYS_SCCR_SATACM 0xFF
68
69	/*
70	* System IO Config
71	*/
72	#define CONFIG_SYS_SICRH 0x087c0000
73	#define CONFIG_SYS_SICRL 0x40000000
74
75	/*
76	* Output Buffer Impedance
77	*/
78	#define CONFIG_SYS_OBIR 0x30000000
79
80	/*
81	* IMMR new address
82	*/
83	#define CONFIG_SYS_IMMR 0xE0000000
84
85	/*
86	* DDR Setup
87	*/
88	#define CONFIG_SYS_DDR_BASE 0x00000000
89	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
90	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
91	#define CONFIG_SYS_83XX_DDR_USES_CS0
92
93	#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \| DDRCDR_PZ_HIZ \|\
94	DDRCDR_NZ_HIZ \| DDRCDR_ODT \|\
95	DDRCDR_Q_DRN)
96
97	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
98
99	#define CONFIG_SYS_DDR_MODE_WEAK
100	#define CONFIG_SYS_DDR_WRITE_DATA_DELAY 2
101	#define CONFIG_SYS_DDR_CPO 0x1f
102
103	/* SPD table located at offset 0x20 in extended adressing ROM
104	* used for HRCW fetch after power-on reset
105	*/
106	#define CONFIG_SPD_EEPROM
107	#define SPD_EEPROM_ADDRESS 0x50
108	#define SPD_EEPROM_OFFSET 0x20
109	#define SPD_EEPROM_ADDR_LEN 2
110
111	/*
112	* The reserved memory
113	*/
114	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
115	#define CONFIG_SYS_MONITOR_LEN (512*1024)
116	#define CONFIG_SYS_MALLOC_LEN (512*1024)
117
118	/*
119	* Initial RAM Base Address Setup
120	*/
121	#define CONFIG_SYS_INIT_RAM_LOCK 1
122	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
123	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
124	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\
125	GENERATED_GBL_DATA_SIZE)
126
127	/*
128	* Local Bus Configuration & Clock Setup
129	*/
130	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
131	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
132	#define CONFIG_SYS_LBC_LBCR 0x00000000
133	#define CONFIG_FSL_ELBC 1
134
135	/*
136	* FLASH on the Local Bus
137	*/
138	#define CONFIG_SYS_FLASH_CFI
139	#define CONFIG_FLASH_CFI_DRIVER
140	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
141
142	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
143	#define CONFIG_SYS_FLASH_SIZE 64
144
145	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
146	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_64MB)
147
148	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| BR_PS_16 \|\
149	BR_MS_GPCM \| BR_V)
150	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE \| OR_UPM_XAM \|\
151	OR_GPCM_CSNT \| OR_GPCM_ACS_DIV2 \|\
152	OR_GPCM_XACS \| OR_GPCM_SCY_15 \|\
153	OR_GPCM_TRLX_SET \| OR_GPCM_EHTR_SET \|\
154	OR_GPCM_EAD)
155
156	#define CONFIG_SYS_MAX_FLASH_BANKS 1
157	#define CONFIG_SYS_MAX_FLASH_SECT 512
158
159	#undef CONFIG_SYS_FLASH_CHECKSUM
160	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (ms) */
161	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
162
163	/*
164	* NAND Flash on the Local Bus
165	*/
166	#define CONFIG_MTD_NAND_VERIFY_WRITE 1
167	#define CONFIG_SYS_MAX_NAND_DEVICE 1
168	#define CONFIG_NAND_FSL_ELBC 1
169
170	#define CONFIG_SYS_NAND_BASE 0xE0600000
171	#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \| BR_DECC_CHK_GEN \|\
172	BR_PS_8 \| BR_MS_FCM \| BR_V)
173	#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \| OR_FCM_BCTLD \| OR_FCM_CST \|\
174	OR_FCM_CHT \| OR_FCM_SCY_1 \| OR_FCM_RST \|\
175	OR_FCM_TRLX \| OR_FCM_EHTR)
176
177	#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
178	#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN \| LBLAWAR_32KB)
179
180	/*
181	* Serial Port
182	*/
183	#define CONFIG_CONS_INDEX 1
184	#define CONFIG_SYS_NS16550
185	#define CONFIG_SYS_NS16550_SERIAL
186	#define CONFIG_SYS_NS16550_REG_SIZE 1
187	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
188
189	#define CONFIG_SYS_BAUDRATE_TABLE \
190	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
191
192	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
193	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
194
195	#define CONFIG_CONSOLE ttyS0
196	#define CONFIG_BAUDRATE 115200
197
198	/* SERDES */
199	#define CONFIG_FSL_SERDES
200	#define CONFIG_FSL_SERDES1 0xe3000
201	#define CONFIG_FSL_SERDES2 0xe3100
202
203	/* Use the HUSH parser */
204	#define CONFIG_SYS_HUSH_PARSER
205
206	/* Pass open firmware flat tree */
207	#define CONFIG_OF_LIBFDT 1
208	#define CONFIG_OF_BOARD_SETUP 1
209	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
210
211	/* I2C */
212	#define CONFIG_SYS_I2C
213	#define CONFIG_SYS_I2C_FSL
214	#define CONFIG_SYS_FSL_I2C_SPEED 400000
215	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
216	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
217	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
218	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
219	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
220
221	/*
222	* General PCI
223	* Addresses are mapped 1-1.
224	*/
225	#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
226	#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
227	#define CONFIG_SYS_PCI_MEM_SIZE (256 << 20)
228	#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
229	#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
230	#define CONFIG_SYS_PCI_MMIO_SIZE (256 << 20)
231	#define CONFIG_SYS_PCI_IO_BASE 0x00000000
232	#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
233	#define CONFIG_SYS_PCI_IO_SIZE (1 << 20)
234
235	#ifdef CONFIG_PCIE
236	#define CONFIG_SYS_PCIE1_BASE 0xA0000000
237	#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
238	#define CONFIG_SYS_PCIE1_CFG_SIZE (128 << 20)
239	#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
240	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
241	#define CONFIG_SYS_PCIE1_MEM_SIZE (256 << 20)
242	#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
243	#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
244	#define CONFIG_SYS_PCIE1_IO_SIZE (8 << 20)
245
246	#define CONFIG_SYS_PCIE2_BASE 0xC0000000
247	#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
248	#define CONFIG_SYS_PCIE2_CFG_SIZE (128 << 20)
249	#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
250	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
251	#define CONFIG_SYS_PCIE2_MEM_SIZE (256 << 20)
252	#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
253	#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
254	#define CONFIG_SYS_PCIE2_IO_SIZE (8 << 20)
255	#endif
256
257	#define CONFIG_PCI_PNP
258	#define CONFIG_PCI_SCAN_SHOW
259	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
260
261	/*
262	* TSEC
263	*/
264	#define CONFIG_GMII /* MII PHY management */
265	#define CONFIG_SYS_VSC8601_SKEWFIX
266	#define CONFIG_SYS_VSC8601_SKEW_TX 3
267	#define CONFIG_SYS_VSC8601_SKEW_RX 3
268
269	#define CONFIG_TSEC1
270	#define CONFIG_HAS_ETH0
271	#define CONFIG_TSEC1_NAME "TSEC0"
272	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
273	#define TSEC1_PHY_ADDR 0x10
274	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
275	#define TSEC1_PHYIDX 0
276
277	#define CONFIG_ETHPRIME "TSEC0"
278	#define CONFIG_HAS_ETH0
279
280	/*
281	* SATA
282	*/
283	#define CONFIG_LIBATA
284	#define CONFIG_FSL_SATA
285
286	#define CONFIG_SYS_SATA_MAX_DEVICE 2
287	#define CONFIG_SATA1
288	#define CONFIG_SYS_SATA1_OFFSET 0x18000
289	#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
290	#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
291	#define CONFIG_SATA2
292	#define CONFIG_SYS_SATA2_OFFSET 0x19000
293	#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
294	#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
295
296	#define CONFIG_LBA48
297	#define CONFIG_CMD_SATA
298	#define CONFIG_DOS_PARTITION
299	#define CONFIG_CMD_EXT2
300
301	/*
302	* BOOTP options
303	*/
304	#define CONFIG_BOOTP_BOOTFILESIZE
305	#define CONFIG_BOOTP_BOOTPATH
306	#define CONFIG_BOOTP_GATEWAY
307	#define CONFIG_BOOTP_HOSTNAME
308	#define CONFIG_BOOTP_VENDOREX
309	#define CONFIG_BOOTP_SUBNETMASK
310	#define CONFIG_BOOTP_DNS
311	#define CONFIG_BOOTP_DNS2
312	#define CONFIG_BOOTP_NTPSERVER
313	#define CONFIG_BOOTP_RANDOM_DELAY
314	#define CONFIG_BOOTP_SEND_HOSTNAME
315	#define CONFIG_LIB_RAND
316
317	/*
318	* Command line configuration.
319	*/
320	#include <config_cmd_default.h>
321
322	#define CONFIG_CMD_ASKENV
323	#define CONFIG_CMD_NAND
324	#define CONFIG_CMD_PING
325	#define CONFIG_CMD_EEPROM
326	#define CONFIG_CMD_I2C
327	#define CONFIG_CMD_MII
328	#define CONFIG_CMD_PCI
329	#define CONFIG_CMD_USB
330	#define CONFIG_CMD_SPI
331	#define CONFIG_CMD_DHCP
332	#define CONFIG_CMD_UBI
333	#define CONFIG_CMD_UBIFS
334	#define CONFIG_CMD_MTDPARTS
335	#define CONFIG_CMD_SATA
336
337	#define CONFIG_CMD_EXT2
338	#define CONFIG_CMD_FAT
339	#define CONFIG_CMD_JFFS2
340
341	#define CONFIG_RBTREE
342	#define CONFIG_LZO
343
344	#define CONFIG_MTD_DEVICE
345	#define CONFIG_MTD_PARTITIONS
346
347	#define CONFIG_FLASH_CFI_MTD
348	#define MTDIDS_DEFAULT "nor0=NOR,nand0=NAND"
349	#define MTDPARTS_DEFAULT "mtdparts=NOR:1M(u-boot),2M(FPGA);NAND:-(root)"
350
351	#define CONFIG_FIT
352	#define CONFIG_FIT_VERBOSE 1
353
354	#define CONFIG_CMDLINE_EDITING 1
355	#define CONFIG_AUTO_COMPLETE
356
357	/*
358	* Miscellaneous configurable options
359	*/
360	#define CONFIG_SYS_LONGHELP
361	#define CONFIG_SYS_LOAD_ADDR 0x2000000
362	#define CONFIG_LOADADDR 0x4000000
363	#define CONFIG_SYS_CBSIZE 256
364
365	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
366	#define CONFIG_SYS_MAXARGS 16
367	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
368
369	#define CONFIG_LOADS_ECHO 1
370	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
371
372	#define CONFIG_SYS_MEMTEST_START (60<<20)
373	#define CONFIG_SYS_MEMTEST_END (70<<20)
374
375	/*
376	* For booting Linux, the board info and command line data
377	* have to be in the first 256 MB of memory, since this is
378	* the maximum mapped by the Linux kernel during initialization.
379	*/
380	#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
381
382	/*
383	* Core HID Setup
384	*/
385	#define CONFIG_SYS_HID0_INIT 0x000000000
386	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
387	HID0_ENABLE_INSTRUCTION_CACHE)
388	#define CONFIG_SYS_HID2 HID2_HBE
389
390	/*
391	* MMU Setup
392	*/
393	#define CONFIG_HIGH_BATS 1
394
395	/* DDR: cache cacheable */
396	#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE
397
398	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM \| BATL_PP_RW \|\
399	BATL_MEMCOHERENCE)
400	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM \| BATU_BL_256M \| BATU_VS \|\
401	BATU_VP)
402	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
403	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
404
405	/* unused */
406	#define CONFIG_SYS_IBAT1L (0)
407	#define CONFIG_SYS_IBAT1U (0)
408	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
409	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
410
411	/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
412	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \| BATL_PP_RW \|\
413	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
414	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \| BATU_BL_8M \| BATU_VS \|\
415	BATU_VP)
416	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
417	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
418
419	/* unused */
420	#define CONFIG_SYS_IBAT3L (0)
421	#define CONFIG_SYS_IBAT3U (0)
422	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
423	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
424
425	/* FLASH: icache cacheable, but dcache-inhibit and guarded */
426	#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \|\
427	BATL_MEMCOHERENCE)
428	#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \| BATU_BL_64M \|\
429	BATU_VS \| BATU_VP)
430	#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \| \
431	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
432	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
433
434	/* Stack in dcache: cacheable, no memory coherence */
435	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW)
436	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \|\
437	BATU_VS \| BATU_VP)
438	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
439	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
440
441	/* PCI MEM space: cacheable */
442	#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \| BATL_PP_RW \|\
443	BATL_MEMCOHERENCE)
444	#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \| BATU_BL_256M \|\
445	BATU_VS \| BATU_VP)
446	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
447	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
448
449	/* PCI MMIO space: cache-inhibit and guarded */
450	#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \| BATL_PP_RW \| \
451	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
452	#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \| BATU_BL_256M \|\
453	BATU_VS \| BATU_VP)
454	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
455	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
456
457	/*
458	* I2C EEPROM settings
459	*/
460	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
461	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
462	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
463	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
464	#define CONFIG_SYS_EEPROM_SIZE 0x4000
465
466	/*
467	* Environment Configuration
468	*/
469	#define CONFIG_SYS_FLASH_PROTECTION
470	#define CONFIG_ENV_OVERWRITE
471	#define CONFIG_ENV_IS_IN_FLASH 1
472	#define CONFIG_ENV_ADDR 0xFFD00000
473	#define CONFIG_ENV_SECT_SIZE 0x20000
474	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
475
476	/*
477	* Video
478	*/
479	#define CONFIG_VIDEO
480	#define CONFIG_VIDEO_SM501_PCI
481	#define VIDEO_FB_LITTLE_ENDIAN
482	#define CONFIG_CMD_BMP
483	#define CONFIG_VIDEO_SM501
484	#define CONFIG_VIDEO_SM501_32BPP
485	#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
486	#define CONFIG_CFB_CONSOLE
487	#define CONFIG_VIDEO_LOGO
488	#define CONFIG_VIDEO_BMP_LOGO
489	#define CONFIG_VGA_AS_SINGLE_DEVICE
490	#define CONFIG_SPLASH_SCREEN
491	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
492	#define CONFIG_VIDEO_BMP_GZIP
493	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
494
495	/*
496	* SPI
497	*/
498	#define CONFIG_MPC8XXX_SPI
499
500	/*
501	* USB
502	*/
503	#define CONFIG_SYS_USB_HOST
504	#define CONFIG_USB_EHCI
505	#define CONFIG_USB_EHCI_FSL
506	#define CONFIG_HAS_FSL_DR_USB
507	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
508
509	#define CONFIG_USB_STORAGE
510	#define CONFIG_USB_KEYBOARD
511	/*
512	*
513	*/
514	#define CONFIG_BOOTDELAY 5
515	#define CONFIG_AUTOBOOT_KEYED
516	#define CONFIG_AUTOBOOT_STOP_STR "s"
517	#define CONFIG_ZERO_BOOTDELAY_CHECK
518	#define CONFIG_RESET_TO_RETRY 1000
519
520	#define MV_CI "MergerBox"
521	#define MV_VCI "MergerBox"
522	#define MV_FPGA_DATA 0xfc100000
523	#define MV_FPGA_SIZE 0x00200000
524
525	#define CONFIG_SHOW_BOOT_PROGRESS 1
526
527	#define MV_KERNEL_ADDR_RAM 0x02800000
528	#define MV_DTB_ADDR_RAM 0x00600000
529	#define MV_INITRD_ADDR_RAM 0x01000000
530	#define MV_FITADDR 0xfc300000
531	#define MV_SPLAH_ADDR 0xffe00000
532
533	#define CONFIG_BOOTCOMMAND "run i2c_init;if test ${boot_sqfs} -eq 1;"\
534	"then; run fitboot;else;run ubiboot;fi;"
535	#define CONFIG_BOOTARGS "console=ttyS0,115200n8"
536
537	#define CONFIG_EXTRA_ENV_SETTINGS \
538	"console_nr=0\0"\
539	"stdin=serial\0"\
540	"stdout=serial\0"\
541	"stderr=serial\0"\
542	"boot_sqfs=1\0"\
543	"usb_dr_mode=host\0"\
544	"bootfile=MergerBox.fit\0"\
545	"baudrate=" __stringify(CONFIG_BAUDRATE) "\0"\
546	"fpga=0\0"\
547	"fpgadata=" __stringify(MV_FPGA_DATA) "\0"\
548	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"\
549	"mv_kernel_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"\
550	"mv_initrd_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"\
551	"mv_dtb_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"\
552	"uboota=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"\
553	"fitaddr=" __stringify(MV_FITADDR) "\0"\
554	"mv_version=" U_BOOT_VERSION "\0"\
555	"mtdids=" MTDIDS_DEFAULT "\0"\
556	"mtdparts=" MTDPARTS_DEFAULT "\0"\
557	"dhcp_client_id=" MV_CI "\0"\
558	"dhcp_vendor-class-identifier=" MV_VCI "\0"\
559	"upd_uboot=dhcp;tftp bdi2000/u-boot-mergerbox-xp.bin;"\
560	"protect off all;erase $uboota +0xC0000;"\
561	"cp.b $loadaddr $uboota $filesize\0"\
562	"upd_fpga=dhcp;tftp MergerBox.rbf;erase $fpgadata +$fpgadatasize;"\
563	"cp.b $loadaddr $fpgadata $filesize\0"\
564	"upd_fit=dhcp;tftp MergerBox.fit;erase $fitaddr +0x1000000;"\
565	"cp.b $loadaddr $fitaddr $filesize\0"\
566	"addsqshrfs=set bootargs $bootargs root=/dev/ram ro "\
567	"rootfstype=squashfs\0"\
568	"addubirfs=set bootargs $bootargs ubi.mtd=9 root=ubi0:rootfs rw "\
569	"rootfstype=ubifs\0"\
570	"addusbrfs=set bootargs $bootargs root=/dev/sda1 rw "\
571	"rootfstype=ext3 usb-storage.delay_use=1 rootdelay=3\0"\
572	"netusbboot=bootp;run fpganetload fitnetload addusbrfs doboot\0"\
573	"netubiboot= bootp;run fpganetload fitnetload addubirfs doboot\0"\
574	"ubiboot=run fitprep addubirfs;set mv_initrd_ram -;run doboot\0"\
575	"doboot=bootm $mv_kernel_ram $mv_initrd_ram $mv_dtb_ram\0"\
576	"fitprep=imxtract $fitaddr kernel $mv_kernel_ram;"\
577	"imxtract $fitaddr ramdisk $mv_initrd_ram;"\
578	"imxtract $fitaddr fdt $mv_dtb_ram\0"\
579	"fdtprep=fdt addr $mv_dtb_ram;fdt boardsetup\0"\
580	"fitboot=run fitprep fdtprep addsqshrfs doboot\0"\
581	"i2c_init=run i2c_speed init_sdi_tx i2c_init_pll\0"\
582	"i2c_init_pll=i2c mw 65 9 2;i2c mw 65 9 0;i2c mw 65 5 2b;"\
583	"i2c mw 65 7 f;i2c mw 65 8 f;i2c mw 65 11 40;i2c mw 65 12 40;"\
584	"i2c mw 65 13 40; i2c mw 65 14 40; i2c mw 65 a 0\0"\
585	"i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\
586	"init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\
587	"i2c mw 21 2 ff;i2c mw 21 3 3c\0"\
588	"splashimage=" __stringify(MV_SPLAH_ADDR) "\0"\
589	""
590
591	/*
592	* FPGA
593	*/
594	#define CONFIG_FPGA_COUNT 1
595	#define CONFIG_FPGA
596	#define CONFIG_FPGA_ALTERA
597	#define CONFIG_FPGA_CYCLON2
598
599	#endif
600		1	/*

include/configs/MVBLM7.h

View file @ e7a5656

1	/*		File was deleted
2	* Copyright (C) Matrix Vision GmbH 2008
3	*
4	* Matrix Vision mvBlueLYNX-M7 configuration file
5	* based on Freescale's MPC8349ITX.
6	*
7	* SPDX-License-Identifier: GPL-2.0+
8	*/
9
10
11	#ifndef __CONFIG_H
12	#define __CONFIG_H
13
14	#include <version.h>
15
16	/*
17	* High Level Configuration Options
18	*/
19	#define CONFIG_E300 1
20	#define CONFIG_MPC834x 1
21	#define CONFIG_MPC8343 1
22
23	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
24
25	#define CONFIG_SYS_IMMR 0xE0000000
26
27	#define CONFIG_PCI
28	#define CONFIG_PCI_INDIRECT_BRIDGE
29	#define CONFIG_PCI_SKIP_HOST_BRIDGE
30	#define CONFIG_TSEC_ENET
31	#define CONFIG_MPC8XXX_SPI
32	#define CONFIG_HARD_SPI
33	#define MVBLM7_MMC_CS 0x04000000
34	#define CONFIG_MISC_INIT_R
35
36	/* I2C */
37	#define CONFIG_SYS_I2C
38	#define CONFIG_SYS_I2C_FSL
39	#define CONFIG_SYS_FSL_I2C_SPEED 100000
40	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
41	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
42	#define CONFIG_SYS_FSL_I2C2_SPEED 100000
43	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
44	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
45
46	/*
47	* DDR Setup
48	*/
49	#undef CONFIG_SPD_EEPROM
50
51	#define CONFIG_SYS_DDR_BASE 0x00000000
52	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
53	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
54	#define CONFIG_SYS_83XX_DDR_USES_CS0 1
55	#define CONFIG_SYS_MEMTEST_START (60<<20)
56	#define CONFIG_SYS_MEMTEST_END (70<<20)
57	#define CONFIG_VERY_BIG_RAM
58
59	#define CONFIG_SYS_DDRCDR (DDRCDR_PZ_HIZ \
60	\| DDRCDR_NZ_HIZ \
61	\| DDRCDR_Q_DRN)
62	/* 0x22000001 */
63	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
64
65	#define CONFIG_SYS_DDR_SIZE 512
66
67	#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
68
69	#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
70
71	#define CONFIG_SYS_DDR_TIMING_0 0x00260802
72	#define CONFIG_SYS_DDR_TIMING_1 0x3837c322
73	#define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6
74	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
75
76	#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008
77	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
78	#define CONFIG_SYS_DDR_INTERVAL 0x02000100
79
80	#define CONFIG_SYS_DDR_MODE 0x04040242
81	#define CONFIG_SYS_DDR_MODE2 0x00800000
82
83	/* Flash */
84	#define CONFIG_SYS_FLASH_CFI
85	#define CONFIG_FLASH_CFI_DRIVER
86	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
87
88	#define CONFIG_SYS_FLASH_BASE 0xFF800000
89	#define CONFIG_SYS_FLASH_SIZE 8
90	#define CONFIG_SYS_FLASH_EMPTY_INFO
91	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
92	#define CONFIG_SYS_FLASH_WRITE_TOUT 500
93	#define CONFIG_SYS_MAX_FLASH_BANKS 1
94	#define CONFIG_SYS_MAX_FLASH_SECT 256
95
96	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
97	\| BR_PS_16 \
98	\| BR_MS_GPCM \
99	\| BR_V)
100	#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
101	\| OR_UPM_XAM \
102	\| OR_GPCM_CSNT \
103	\| OR_GPCM_ACS_DIV2 \
104	\| OR_GPCM_XACS \
105	\| OR_GPCM_SCY_15 \
106	\| OR_GPCM_TRLX_SET \
107	\| OR_GPCM_EHTR_SET \
108	\| OR_GPCM_EAD)
109	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
110	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_8MB)
111
112	/*
113	* U-Boot memory configuration
114	*/
115	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
116	#undef CONFIG_SYS_RAMBOOT
117
118	#define CONFIG_SYS_INIT_RAM_LOCK
119	#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
120	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
121
122	#define CONFIG_SYS_GBL_DATA_OFFSET \
123	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
124	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
125
126	/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
127	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
128	#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
129
130	/*
131	* Local Bus LCRR and LBCR regs
132	* LCRR: DLL bypass, Clock divider is 4
133	* External Local Bus rate is
134	* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
135	*/
136	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
137	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
138	#define CONFIG_SYS_LBC_LBCR 0x00000000
139
140	/* LB sdram refresh timer, about 6us */
141	#define CONFIG_SYS_LBC_LSRT 0x32000000
142	/* LB refresh timer prescal, 266MHz/32*/
143	#define CONFIG_SYS_LBC_MRTPR 0x20000000
144
145	/*
146	* Serial Port
147	*/
148	#define CONFIG_CONS_INDEX 1
149	#define CONFIG_SYS_NS16550
150	#define CONFIG_SYS_NS16550_SERIAL
151	#define CONFIG_SYS_NS16550_REG_SIZE 1
152	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
153
154	#define CONFIG_SYS_BAUDRATE_TABLE \
155	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
156
157	#define CONFIG_CONSOLE ttyS0
158	#define CONFIG_BAUDRATE 115200
159
160	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
161	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
162
163	/* pass open firmware flat tree */
164	#define CONFIG_OF_LIBFDT 1
165	#define CONFIG_OF_BOARD_SETUP 1
166	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
167	#define MV_DTB_NAME "mvblm7.dtb"
168
169	/*
170	* PCI
171	*/
172	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
173	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
174	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
175	#define CONFIG_SYS_PCI1_MMIO_BASE \
176	(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
177	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
178	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
179	#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
180	#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
181	#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
182
183	#define CONFIG_NET_RETRY_COUNT 3
184
185	#define CONFIG_PCI_66M
186	#define CONFIG_83XX_CLKIN 66666667
187	#define CONFIG_PCI_PNP
188	#define CONFIG_PCI_SCAN_SHOW
189
190	/* TSEC */
191	#define CONFIG_GMII
192	#define CONFIG_SYS_VSC8601_SKEWFIX
193	#define CONFIG_SYS_VSC8601_SKEW_TX 3
194	#define CONFIG_SYS_VSC8601_SKEW_RX 3
195
196	#define CONFIG_TSEC1
197	#define CONFIG_TSEC2
198
199	#define CONFIG_HAS_ETH0
200	#define CONFIG_TSEC1_NAME "TSEC0"
201	#define CONFIG_FEC1_PHY_NORXERR
202	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
203	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
204	#define TSEC1_PHY_ADDR 0x10
205	#define TSEC1_PHYIDX 0
206	#define TSEC1_FLAGS (TSEC_GIGABIT\|TSEC_REDUCED)
207
208	#define CONFIG_HAS_ETH1
209	#define CONFIG_TSEC2_NAME "TSEC1"
210	#define CONFIG_FEC2_PHY_NORXERR
211	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
212	#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
213	#define TSEC2_PHY_ADDR 0x11
214	#define TSEC2_PHYIDX 0
215	#define TSEC2_FLAGS (TSEC_GIGABIT\|TSEC_REDUCED)
216
217	#define CONFIG_ETHPRIME "TSEC0"
218
219	#define CONFIG_BOOTP_VENDOREX
220	#define CONFIG_BOOTP_SUBNETMASK
221	#define CONFIG_BOOTP_GATEWAY
222	#define CONFIG_BOOTP_DNS
223	#define CONFIG_BOOTP_DNS2
224	#define CONFIG_BOOTP_HOSTNAME
225	#define CONFIG_BOOTP_BOOTFILESIZE
226	#define CONFIG_BOOTP_BOOTPATH
227	#define CONFIG_BOOTP_NTPSERVER
228	#define CONFIG_BOOTP_RANDOM_DELAY
229	#define CONFIG_BOOTP_SEND_HOSTNAME
230	#define CONFIG_LIB_RAND
231
232	/* USB */
233	#define CONFIG_SYS_USB_HOST
234	#define CONFIG_USB_EHCI
235	#define CONFIG_USB_EHCI_FSL
236	#define CONFIG_HAS_FSL_DR_USB
237	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
238
239	/*
240	* Environment
241	*/
242	#undef CONFIG_SYS_FLASH_PROTECTION
243	#define CONFIG_ENV_OVERWRITE
244
245	#define CONFIG_ENV_IS_IN_FLASH 1
246	#define CONFIG_ENV_ADDR 0xFF800000
247	#define CONFIG_ENV_SIZE 0x2000
248	#define CONFIG_ENV_SECT_SIZE 0x2000
249	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
250	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
251
252	#define CONFIG_LOADS_ECHO
253	#define CONFIG_SYS_LOADS_BAUD_CHANGE
254
255	/*
256	* Command line configuration.
257	*/
258	#include <config_cmd_default.h>
259
260	#define CONFIG_CMD_CACHE
261	#define CONFIG_CMD_IRQ
262	#define CONFIG_CMD_NET
263	#define CONFIG_CMD_MII
264	#define CONFIG_CMD_PING
265	#define CONFIG_CMD_DHCP
266	#define CONFIG_CMD_SDRAM
267	#define CONFIG_CMD_PCI
268	#define CONFIG_CMD_I2C
269	#define CONFIG_CMD_FPGA
270	#define CONFIG_CMD_FPGA_LOADMK
271	#define CONFIG_CMD_USB
272	#define CONFIG_DOS_PARTITION
273
274	#undef CONFIG_WATCHDOG
275
276	/*
277	* Miscellaneous configurable options
278	*/
279	#define CONFIG_SYS_LONGHELP
280	#define CONFIG_CMDLINE_EDITING
281	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
282	#define CONFIG_SYS_HUSH_PARSER
283
284	/* default load address */
285	#define CONFIG_SYS_LOAD_ADDR 0x2000000
286	/* default location for tftp and bootm */
287	#define CONFIG_LOADADDR 0x200000
288
289	#define CONFIG_SYS_PROMPT "mvBL-M7> "
290	#define CONFIG_SYS_CBSIZE 256
291
292	#define CONFIG_SYS_PBSIZE \
293	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
294	#define CONFIG_SYS_MAXARGS 16
295	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
296
297	/*
298	* For booting Linux, the board info and command line data
299	* have to be in the first 256 MB of memory, since this is
300	* the maximum mapped by the Linux kernel during initialization.
301	*/
302	/* Initial Memory map for Linux*/
303	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
304
305	#define CONFIG_SYS_HRCW_LOW 0x0
306	#define CONFIG_SYS_HRCW_HIGH 0x0
307
308	/*
309	* System performance
310	*/
311	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
312	#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
313	#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
314	#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
315
316	/* clocking */
317	#define CONFIG_SYS_SCCR_ENCCM 0
318	#define CONFIG_SYS_SCCR_USBMPHCM 0
319	#define CONFIG_SYS_SCCR_USBDRCM 2
320	#define CONFIG_SYS_SCCR_TSEC1CM 1
321	#define CONFIG_SYS_SCCR_TSEC2CM 1
322
323	#define CONFIG_SYS_SICRH 0x1fef0003
324	#define CONFIG_SYS_SICRL (SICRL_LDP_A \| SICRL_USB1 \| SICRL_USB0)
325
326	#define CONFIG_SYS_HID0_INIT 0x000000000
327	#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT \| \
328	HID0_ENABLE_INSTRUCTION_CACHE)
329
330	#define CONFIG_SYS_HID2 HID2_HBE
331	#define CONFIG_HIGH_BATS 1
332
333	/* DDR */
334	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
335	\| BATL_PP_RW \
336	\| BATL_MEMCOHERENCE)
337	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
338	\| BATU_BL_256M \
339	\| BATU_VS \
340	\| BATU_VP)
341
342	/* PCI */
343	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
344	\| BATL_PP_RW \
345	\| BATL_MEMCOHERENCE)
346	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
347	\| BATU_BL_256M \
348	\| BATU_VS \
349	\| BATU_VP)
350	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
351	\| BATL_PP_RW \
352	\| BATL_CACHEINHIBIT \
353	\| BATL_GUARDEDSTORAGE)
354	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
355	\| BATU_BL_256M \
356	\| BATU_VS \
357	\| BATU_VP)
358
359	/* no PCI2 */
360	#define CONFIG_SYS_IBAT3L 0
361	#define CONFIG_SYS_IBAT3U 0
362	#define CONFIG_SYS_IBAT4L 0
363	#define CONFIG_SYS_IBAT4U 0
364
365	/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
366	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
367	\| BATL_PP_RW \
368	\| BATL_CACHEINHIBIT \
369	\| BATL_GUARDEDSTORAGE)
370	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
371	\| BATU_BL_256M \
372	\| BATU_VS \
373	\| BATU_VP)
374
375	/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
376	#define CONFIG_SYS_IBAT6L (0xF0000000 \
377	\| BATL_PP_RW \
378	\| BATL_MEMCOHERENCE \
379	\| BATL_GUARDEDSTORAGE)
380	#define CONFIG_SYS_IBAT6U (0xF0000000 \
381	\| BATU_BL_256M \
382	\| BATU_VS \
383	\| BATU_VP)
384	#define CONFIG_SYS_IBAT7L 0
385	#define CONFIG_SYS_IBAT7U 0
386
387	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
388	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
389	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
390	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
391	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
392	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
393	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
394	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
395	#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
396	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
397	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
398	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
399	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
400	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
401	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
402	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
403
404	/*
405	* Environment Configuration
406	*/
407	#define CONFIG_ENV_OVERWRITE
408
409	#define CONFIG_NETDEV eth0
410
411	/* Default path and filenames */
412	#define CONFIG_BOOTDELAY 5
413	#define CONFIG_AUTOBOOT_KEYED
414	#define CONFIG_AUTOBOOT_STOP_STR "s"
415	#define CONFIG_ZERO_BOOTDELAY_CHECK
416	#define CONFIG_RESET_TO_RETRY 1000
417
418	#define MV_CI "mvBL-M7"
419	#define MV_VCI "mvBL-M7"
420	#define MV_FPGA_DATA 0xfff40000
421	#define MV_FPGA_SIZE 0
422	#define MV_KERNEL_ADDR 0xff810000
423	#define MV_INITRD_ADDR 0xffb00000
424	#define MV_SCRIPT_ADDR 0xff804000
425	#define MV_SCRIPT_ADDR2 0xff806000
426	#define MV_DTB_ADDR 0xff808000
427	#define MV_INITRD_LENGTH 0x00400000
428
429	#define CONFIG_SHOW_BOOT_PROGRESS 1
430
431	#define MV_KERNEL_ADDR_RAM 0x00100000
432	#define MV_DTB_ADDR_RAM 0x00600000
433	#define MV_INITRD_ADDR_RAM 0x01000000
434
435	#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; " \
436	"then source ${script_addr}; " \
437	"else source ${script_addr2}; " \
438	"fi;"
439	#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
440
441	#define CONFIG_EXTRA_ENV_SETTINGS \
442	"console_nr=0\0" \
443	"baudrate=" __stringify(CONFIG_BAUDRATE) "\0" \
444	"stdin=serial\0" \
445	"stdout=serial\0" \
446	"stderr=serial\0" \
447	"fpga=0\0" \
448	"fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
449	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
450	"script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
451	"script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \
452	"mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
453	"mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
454	"mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
455	"mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
456	"mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
457	"mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \
458	"mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \
459	"dtb_name=" __stringify(MV_DTB_NAME) "\0" \
460	"mv_version=" U_BOOT_VERSION "\0" \
461	"dhcp_client_id=" MV_CI "\0" \
462	"dhcp_vendor-class-identifier=" MV_VCI "\0" \
463	"netretry=no\0" \
464	"use_static_ipaddr=no\0" \
465	"static_ipaddr=192.168.90.10\0" \
466	"static_netmask=255.255.255.0\0" \
467	"static_gateway=0.0.0.0\0" \
468	"initrd_name=uInitrd.mvBL-M7-rfs\0" \
469	"zcip=no\0" \
470	"netboot=yes\0" \
471	"mvtest=Ff\0" \
472	"tried_bootfromflash=no\0" \
473	"tried_bootfromnet=no\0" \
474	"bootfile=mvblm72625.boot\0" \
475	"use_dhcp=yes\0" \
476	"gev_start=yes\0" \
477	"mvbcdma_debug=0\0" \
478	"mvbcia_debug=0\0" \
479	"propdev_debug=0\0" \
480	"gevss_debug=0\0" \
481	"watchdog=0\0" \
482	"usb_dr_mode=host\0" \
483	"sensor_cnt=2\0" \
484	""
485
486	#define CONFIG_FPGA_COUNT 1
487	#define CONFIG_FPGA
488	#define CONFIG_FPGA_ALTERA
489	#define CONFIG_FPGA_CYCLON2
490
491	#endif
492		1	/*

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