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Commit 9ed3246e19a42392bf0fd676dcbbe3539cc46ec1

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent 1521cdc530
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

powerpc: ppc4xx: remove board support for bluestone 

This board has been orphaned for more than 6 months.

It is the last board defining CONFIG_APM821XX.
The code inside #ifdef CONFIG_APM821XX should be removed too.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Showing 20 changed files with 19 additions and 540 deletions Side-by-side Diff

arch/powerpc/cpu/ppc4xx/Kconfig
Diff comments   View file @ 9ed3246
... ... @@ -52,9 +52,6 @@
52 52 config TARGET_BAMBOO
53 53 bool "Support bamboo"
54 54  
55   -config TARGET_BLUESTONE
56   - bool "Support bluestone"
57   -
58 55 config TARGET_BUBINGA
59 56 bool "Support bubinga"
60 57  
... ... @@ -239,7 +236,6 @@
239 236  
240 237 source "board/amcc/acadia/Kconfig"
241 238 source "board/amcc/bamboo/Kconfig"
242   -source "board/amcc/bluestone/Kconfig"
243 239 source "board/amcc/bubinga/Kconfig"
244 240 source "board/amcc/canyonlands/Kconfig"
245 241 source "board/amcc/ebony/Kconfig"
arch/powerpc/cpu/ppc4xx/cpu.c
Diff comments   View file @ 9ed3246
... ... @@ -234,20 +234,6 @@
234 234 };
235 235 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
236 236 #endif
237   -#if defined(CONFIG_APM821XX)
238   -#define SDR0_PINSTP_SHIFT 29
239   -static char *bootstrap_str[] = {
240   - "RESERVED",
241   - "RESERVED",
242   - "RESERVED",
243   - "NAND (8 bits)",
244   - "NOR (8 bits)",
245   - "NOR (8 bits) w/PLL Bypassed",
246   - "I2C (Addr 0x54)",
247   - "I2C (Addr 0x52)",
248   -};
249   -static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
250   -#endif
251 237  
252 238 #if defined(SDR0_PINSTP_SHIFT)
253 239 static int bootstrap_option(void)
arch/powerpc/cpu/ppc4xx/cpu_init.c
Diff comments   View file @ 9ed3246
... ... @@ -284,7 +284,7 @@
284 284 reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
285 285  
286 286 #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \
287   - !defined(CONFIG_APM821XX) &&!defined(CONFIG_SYS_4xx_GPIO_TABLE)
  287 + !defined(CONFIG_SYS_4xx_GPIO_TABLE)
288 288 /*
289 289 * GPIO0 setup (select GPIO or alternate function)
290 290 */
... ... @@ -440,7 +440,7 @@
440 440 #if defined(CONFIG_405EX) || \
441 441 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
442 442 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
443   - defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
  443 + defined(CONFIG_460SX)
444 444 /*
445 445 * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
446 446 */
arch/powerpc/cpu/ppc4xx/speed.c
Diff comments   View file @ 9ed3246
... ... @@ -171,7 +171,7 @@
171 171 #elif defined(CONFIG_440)
172 172  
173 173 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
174   - defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
  174 + defined(CONFIG_460SX)
175 175 static u8 pll_fwdv_multi_bits[] = {
176 176 /* values for: 1 - 16 */
177 177 0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c,
... ... @@ -232,78 +232,6 @@
232 232 return 0;
233 233 }
234 234  
235   -#if defined(CONFIG_APM821XX)
236   -
237   -void get_sys_info(sys_info_t *sysInfo)
238   -{
239   - unsigned long plld;
240   - unsigned long temp;
241   - unsigned long mul;
242   - unsigned long cpudv;
243   - unsigned long plb2dv;
244   - unsigned long ddr2dv;
245   -
246   - /* Calculate Forward divisor A and Feeback divisor */
247   - mfcpr(CPR0_PLLD, plld);
248   -
249   - temp = CPR0_PLLD_FWDVA(plld);
250   - sysInfo->pllFwdDivA = get_cpr0_fwdv(temp);
251   -
252   - temp = CPR0_PLLD_FDV(plld);
253   - sysInfo->pllFbkDiv = get_cpr0_fbdv(temp);
254   -
255   - /* Calculate OPB clock divisor */
256   - mfcpr(CPR0_OPBD, temp);
257   - temp = CPR0_OPBD_OPBDV(temp);
258   - sysInfo->pllOpbDiv = temp ? temp : 4;
259   -
260   - /* Calculate Peripheral clock divisor */
261   - mfcpr(CPR0_PERD, temp);
262   - temp = CPR0_PERD_PERDV(temp);
263   - sysInfo->pllExtBusDiv = temp ? temp : 4;
264   -
265   - /* Calculate CPU clock divisor */
266   - mfcpr(CPR0_CPUD, temp);
267   - temp = CPR0_CPUD_CPUDV(temp);
268   - cpudv = temp ? temp : 8;
269   -
270   - /* Calculate PLB2 clock divisor */
271   - mfcpr(CPR0_PLB2D, temp);
272   - temp = CPR0_PLB2D_PLB2DV(temp);
273   - plb2dv = temp ? temp : 4;
274   -
275   - /* Calculate DDR2 clock divisor */
276   - mfcpr(CPR0_DDR2D, temp);
277   - temp = CPR0_DDR2D_DDR2DV(temp);
278   - ddr2dv = temp ? temp : 4;
279   -
280   - /* Calculate 'M' based on feedback source */
281   - mfcpr(CPR0_PLLC, temp);
282   - temp = CPR0_PLLC_SEL(temp);
283   - if (temp == 0) {
284   - /* PLL internal feedback */
285   - mul = sysInfo->pllFbkDiv;
286   - } else {
287   - /* PLL PerClk feedback */
288   - mul = sysInfo->pllFwdDivA * sysInfo->pllFbkDiv * cpudv
289   - * plb2dv * 2 * sysInfo->pllOpbDiv *
290   - sysInfo->pllExtBusDiv;
291   - }
292   -
293   - /* Now calculate the individual clocks */
294   - sysInfo->freqVCOMhz = (mul * CONFIG_SYS_CLK_FREQ) + (mul >> 1);
295   - sysInfo->freqProcessor = sysInfo->freqVCOMhz /
296   - sysInfo->pllFwdDivA / cpudv;
297   - sysInfo->freqPLB = sysInfo->freqVCOMhz /
298   - sysInfo->pllFwdDivA / cpudv / plb2dv / 2;
299   - sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv;
300   - sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv;
301   - sysInfo->freqDDR = sysInfo->freqVCOMhz /
302   - sysInfo->pllFwdDivA / cpudv / ddr2dv / 2;
303   - sysInfo->freqUART = sysInfo->freqPLB;
304   -}
305   -
306   -#else
307 235 /*
308 236 * AMCC_TODO: verify this routine against latest EAS, cause stuff changed
309 237 * with latest EAS
... ... @@ -361,7 +289,6 @@
361 289  
362 290 return;
363 291 }
364   -#endif
365 292  
366 293 #elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
367 294 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
arch/powerpc/cpu/ppc4xx/start.S
Diff comments   View file @ 9ed3246
... ... @@ -664,8 +664,7 @@
664 664 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
665 665 defined(CONFIG_460SX)
666 666 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
667   -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
668   - defined(CONFIG_APM821XX)
  667 +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
669 668 lis r1, 0x0000
670 669 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
671 670 mtdcr L2_CACHE_CFG,r1
... ... @@ -694,7 +693,7 @@
694 693 ori r1,r1, 0x0980 /* fourth 64k */
695 694 mtdcr ISRAM0_SB3CR,r1
696 695 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
697   - defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
  696 + defined(CONFIG_460GT)
698 697 lis r1,0x0000 /* BAS = X_0000_0000 */
699 698 ori r1,r1,0x0984 /* first 64k */
700 699 mtdcr ISRAM0_SB0CR,r1
... ... @@ -707,8 +706,7 @@
707 706 lis r1, 0x0003
708 707 ori r1,r1, 0x0984 /* fourth 64k */
709 708 mtdcr ISRAM0_SB3CR,r1
710   -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
711   - defined(CONFIG_APM821XX)
  709 +#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
712 710 lis r2,0x7fff
713 711 ori r2,r2,0xffff
714 712 mfdcr r1,ISRAM1_DPC
arch/powerpc/include/asm/apm821xx.h
View file @ 9ed3246
1   -/*
2   - * Copyright (c) 2010, Applied Micro Circuits Corporation
3   - * Author: Tirumala R Marri <tmarri@apm.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#ifndef _APM821XX_H_
9   -#define _APM821XX_H_
10   -
11   -#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
12   -
13   -/* Memory mapped registers */
14   -#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000
15   -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
16   -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
17   -
18   -#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
19   -
20   -#define SDR0_SRST0_DMC 0x00200000
21   -#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */
22   -
23   -/* AHB config. */
24   -#define AHB_TOP 0xA4
25   -#define AHB_BOT 0xA5
26   -
27   -/* clk divisors */
28   -#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */
29   -#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */
30   -#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */
31   -#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */
32   -#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */
33   -#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */
34   -#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000/* PLB Early Clk Div*/
35   -#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
36   -#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */
37   -
38   -/*
39   - + * Clocking Controller
40   - + */
41   -#define CPR0_CLKUPD 0x0020
42   -#define CPR0_PLLC 0x0040
43   -#define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24)
44   -#define CPR0_PLLD 0x0060
45   -#define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24)
46   -#define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16)
47   -#define CPR0_CPUD 0x0080
48   -#define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24)
49   -#define CPR0_PLB2D 0x00a0
50   -#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25)
51   -#define CPR0_OPBD 0x00c0
52   -#define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24)
53   -#define CPR0_PERD 0x00e0
54   -#define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24)
55   -#define CPR0_DDR2D 0x0100
56   -#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25)
57   -#define CLK_ICFG 0x0140
58   -
59   -#endif /* _APM821XX_H_ */
arch/powerpc/include/asm/ppc4xx-ebc.h
Diff comments   View file @ 9ed3246
... ... @@ -53,8 +53,7 @@
53 53 #define EBC_NUM_BANKS 6
54 54 #endif
55 55  
56   -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
57   - defined(CONFIG_APM821XX)
  56 +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
58 57 #define EBC_NUM_BANKS 3
59 58 #endif
60 59  
arch/powerpc/include/asm/ppc4xx-isram.h
Diff comments   View file @ 9ed3246
... ... @@ -8,8 +8,7 @@
8 8 /*
9 9 * Internal SRAM
10 10 */
11   -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
12   - defined(CONFIG_APM821XX)
  11 +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
13 12 #define ISRAM0_DCR_BASE 0x380
14 13 #else
15 14 #define ISRAM0_DCR_BASE 0x020
... ... @@ -26,8 +25,7 @@
26 25 #define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
27 26 #define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
28 27  
29   -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
30   - defined(CONFIG_APM821XX)
  28 +#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
31 29 #define ISRAM1_DCR_BASE 0x0B0
32 30 #define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/
33 31 #define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */
... ... @@ -41,8 +39,6 @@
41 39  
42 40 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
43 41 #define ISRAM1_SIZE 0x0984 /* OCM size 64k */
44   -#elif defined(CONFIG_APM821XX)
45   -#define ISRAM1_SIZE 0x0784 /* OCM size 32k */
46 42 #endif
47 43  
48 44 /*
... ... @@ -51,7 +47,7 @@
51 47 #if defined (CONFIG_440GX) || \
52 48 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
53 49 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
54   - defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
  50 + defined(CONFIG_460SX)
55 51 #define L2_CACHE_BASE 0x030
56 52 #define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */
57 53 #define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */
arch/powerpc/include/asm/ppc4xx-sdram.h
Diff comments   View file @ 9ed3246
... ... @@ -276,7 +276,7 @@
276 276 */
277 277 #if defined(CONFIG_440SPE) || \
278 278 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
279   - defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
  279 + defined(CONFIG_460SX)
280 280 #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
281 281 #define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000))
282 282 #define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2)
... ... @@ -349,7 +349,7 @@
349 349 /*
350 350 * Memory controller registers
351 351 */
352   -#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX)
  352 +#if defined(CONFIG_405EX)
353 353 #define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */
354 354 #define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */
355 355 #define SDRAM_BEARL 0x02 /* PLB bus error address low */
356 356  
... ... @@ -359,9 +359,9 @@
359 359 #define SDRAM_PLBOPT 0x08 /* PLB slave options */
360 360 #define SDRAM_PUABA 0x09 /* PLB upper address base */
361 361 #define SDRAM_MCSTAT 0x1F /* memory controller status */
362   -#else /* CONFIG_405EX || CONFIG_APM821XX */
  362 +#else /* CONFIG_405EX */
363 363 #define SDRAM_MCSTAT 0x14 /* memory controller status */
364   -#endif /* CONFIG_405EX || CONFIG_APM821XX */
  364 +#endif /* CONFIG_405EX */
365 365 #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
366 366 #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
367 367 #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
368 368  
... ... @@ -407,12 +407,12 @@
407 407 #define SDRAM_MEMODE 0x89 /* memory extended mode */
408 408 #define SDRAM_ECCES 0x98 /* ECC error status */
409 409 #define SDRAM_CID 0xA4 /* core ID */
410   -#if !defined(CONFIG_405EX) && !defined(CONFIG_APM821XX)
  410 +#if !defined(CONFIG_405EX)
411 411 #define SDRAM_RID 0xA8 /* revision ID */
412 412 #endif
413 413 #define SDRAM_FCSR 0xB0 /* feedback calibration status */
414 414 #define SDRAM_RTSR 0xB1 /* run time status tracking */
415   -#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX)
  415 +#if defined(CONFIG_405EX)
416 416 #define SDRAM_RID 0xF8 /* revision ID */
417 417 #endif
418 418  
arch/powerpc/include/asm/ppc4xx-uic.h
Diff comments   View file @ 9ed3246
... ... @@ -15,7 +15,7 @@
15 15 */
16 16 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
17 17 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
18   - defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
  18 + defined(CONFIG_460SX)
19 19 #define UIC_MAX 4
20 20 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
21 21 defined(CONFIG_405EX)
... ... @@ -236,8 +236,7 @@
236 236 #define VECNUM_ETH0 (32 + 28)
237 237 #endif /* CONFIG_440SPE */
238 238  
239   -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
240   - defined(CONFIG_APM821XX)
  239 +#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
241 240 /* UIC 0 */
242 241 #define VECNUM_UIC2NCI 10
243 242 #define VECNUM_UIC2CI 11
arch/powerpc/include/asm/ppc4xx.h
Diff comments   View file @ 9ed3246
... ... @@ -56,10 +56,6 @@
56 56 #include <asm/ppc460sx.h>
57 57 #endif
58 58  
59   -#if defined(CONFIG_APM821XX)
60   -#include <asm/apm821xx.h>
61   -#endif
62   -
63 59 /*
64 60 * Common registers for all SoC's
65 61 */
board/amcc/bluestone/Kconfig
View file @ 9ed3246
1   -if TARGET_BLUESTONE
2   -
3   -config SYS_BOARD
4   - default "bluestone"
5   -
6   -config SYS_VENDOR
7   - default "amcc"
8   -
9   -config SYS_CONFIG_NAME
10   - default "bluestone"
11   -
12   -endif
board/amcc/bluestone/MAINTAINERS
View file @ 9ed3246
1   -BLUESTONE BOARD
2   -#M: Tirumala Marri <tmarri@apm.com>
3   -S: Orphan (since 2014-03)
4   -F: board/amcc/bluestone/
5   -F: include/configs/bluestone.h
6   -F: configs/bluestone_defconfig
board/amcc/bluestone/Makefile
View file @ 9ed3246
1   -#
2   -# Copyright (c) 2010, Applied Micro Circuits Corporation
3   -# Author: Tirumala R Marri <tmarri@apm.com>
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y := bluestone.o
9   -extra-y += init.o
board/amcc/bluestone/bluestone.c
View file @ 9ed3246
1   -/*
2   - * Bluestone board support
3   - *
4   - * Copyright (c) 2010, Applied Micro Circuits Corporation
5   - * Author: Tirumala R Marri <tmarri@apm.com>
6   - *
7   - * SPDX-License-Identifier: GPL-2.0+
8   - */
9   -
10   -#include <common.h>
11   -#include <asm/apm821xx.h>
12   -#include <libfdt.h>
13   -#include <fdt_support.h>
14   -#include <i2c.h>
15   -#include <asm/processor.h>
16   -#include <asm/io.h>
17   -#include <asm/mmu.h>
18   -#include <asm/ppc4xx-gpio.h>
19   -
20   -int board_early_init_f(void)
21   -{
22   - /*
23   - * Setup the interrupt controller polarities, triggers, etc.
24   - */
25   - mtdcr(UIC0SR, 0xffffffff); /* clear all */
26   - mtdcr(UIC0ER, 0x00000000); /* disable all */
27   - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
28   - mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
29   - mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
30   - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
31   - mtdcr(UIC0SR, 0xffffffff); /* clear all */
32   -
33   - mtdcr(UIC1SR, 0xffffffff); /* clear all */
34   - mtdcr(UIC1ER, 0x00000000); /* disable all */
35   - mtdcr(UIC1CR, 0x00000000); /* all non-critical */
36   - mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
37   - mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
38   - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
39   - mtdcr(UIC1SR, 0xffffffff); /* clear all */
40   -
41   - mtdcr(UIC2SR, 0xffffffff); /* clear all */
42   - mtdcr(UIC2ER, 0x00000000); /* disable all */
43   - mtdcr(UIC2CR, 0x00000000); /* all non-critical */
44   - mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
45   - mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
46   - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
47   - mtdcr(UIC2SR, 0xffffffff); /* clear all */
48   -
49   - mtdcr(UIC3SR, 0xffffffff); /* clear all */
50   - mtdcr(UIC3ER, 0x00000000); /* disable all */
51   - mtdcr(UIC3CR, 0x00000000); /* all non-critical */
52   - mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
53   - mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
54   - mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
55   - mtdcr(UIC3SR, 0xffffffff); /* clear all */
56   -
57   - /*
58   - * Configure PFC (Pin Function Control) registers
59   - * UART0: 2 pins
60   - */
61   - mtsdr(SDR0_PFC1, 0x0000000);
62   -
63   - return 0;
64   -}
65   -
66   -int checkboard(void)
67   -{
68   - char buf[64];
69   - int i = getenv_f("serial#", buf, sizeof(buf));
70   -
71   - puts("Board: Bluestone Evaluation Board");
72   -
73   - if (i > 0) {
74   - puts(", serial# ");
75   - puts(buf);
76   - }
77   - putc('\n');
78   -
79   - return 0;
80   -}
81   -
82   -int misc_init_r(void)
83   -{
84   - u32 sdr0_srst1 = 0;
85   -
86   - /* Setup PLB4-AHB bridge based on the system address map */
87   - mtdcr(AHB_TOP, 0x8000004B);
88   - mtdcr(AHB_BOT, 0x8000004B);
89   -
90   - /*
91   - * The AHB Bridge core is held in reset after power-on or reset
92   - * so enable it now
93   - */
94   - mfsdr(SDR0_SRST1, sdr0_srst1);
95   - sdr0_srst1 &= ~SDR0_SRST1_AHB;
96   - mtsdr(SDR0_SRST1, sdr0_srst1);
97   -
98   - return 0;
99   -}
board/amcc/bluestone/config.mk
View file @ 9ed3246
1   -#
2   -# Copyright (c) 2010, Applied Micro Circuits Corporation
3   -# Author: Tirumala R Marri <tmarri@apm.com>
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -# Applied Micro APM821XX Evaluation board.
8   -#
9   -
10   -PLATFORM_CPPFLAGS += -DCONFIG_440=1
11   -
12   -ifeq ($(debug),1)
13   -PLATFORM_CPPFLAGS += -DDEBUG
14   -endif
15   -
16   -ifeq ($(dbcr),1)
17   -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
18   -endif
board/amcc/bluestone/init.S
View file @ 9ed3246
1   -/*
2   - * Copyright (c) 2010, Applied Micro Circuits Corporation
3   - * Author: Tirumala R Marri <tmarri@apm.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <asm-offsets.h>
9   -#include <ppc_asm.tmpl>
10   -#include <config.h>
11   -#include <asm/mmu.h>
12   -#include <asm/ppc4xx.h>
13   -
14   -/**************************************************************************
15   - * TLB TABLE
16   - *
17   - * This table is used by the cpu boot code to setup the initial tlb
18   - * entries. Rather than make broad assumptions in the cpu source tree,
19   - * this table lets each board set things up however they like.
20   - *
21   - * Pointer to the table is returned in r1
22   - *
23   - *************************************************************************/
24   - .section .bootpg,"ax"
25   - .globl tlbtab
26   -
27   -tlbtab:
28   - tlbtab_start
29   -
30   - /* TLB 0 */
31   - tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
32   - 4, AC_RWX | SA_G)
33   -
34   - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
35   - tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
36   - 0, AC_RWX | SA_G)
37   -
38   - /* TLB-entry for OCM */
39   - tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4,
40   - AC_RWX | SA_I)
41   -
42   - /* TLB-entry for Local Configuration registers => peripherals */
43   - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K,
44   - CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX | SA_IG)
45   - tlbtab_end
configs/bluestone_defconfig
View file @ 9ed3246
1   -CONFIG_PPC=y
2   -CONFIG_4xx=y
3   -CONFIG_TARGET_BLUESTONE=y
doc/README.scrapyard
Diff comments   View file @ 9ed3246
... ... @@ -12,6 +12,7 @@
12 12  
13 13 Board Arch CPU Commit Removed Last known maintainer/contact
14 14 =================================================================================================
  15 +bluestone powerpc ppc4xx - - Tirumala Marri <tmarri@apm.com>
15 16 CRAYL1 powerpc ppc4xx - - David Updegraff <dave@cray.com>
16 17 KAREF powerpc ppc4xx - - Travis Sawyer <travis.sawyer@sandburst.com>
17 18 METROBOX powerpc ppc4xx - - Travis Sawyer <travis.sawyer@sandburst.com>
include/configs/bluestone.h
View file @ 9ed3246
1   -/*
2   - * bluestone.h - configuration for Bluestone (APM821XX)
3   - *
4   - * Copyright (c) 2010, Applied Micro Circuits Corporation
5   - * Author: Tirumala R Marri <tmarri@apm.com>
6   - *
7   - * SPDX-License-Identifier: GPL-2.0+
8   - */
9   -
10   -#ifndef __CONFIG_H
11   -#define __CONFIG_H
12   -
13   -/*
14   - * High Level Configuration Options
15   - */
16   -#define CONFIG_APM821XX 1 /* APM821XX series */
17   -#define CONFIG_HOSTNAME bluestone
18   -
19   -#define CONFIG_440 1
20   -
21   -#ifndef CONFIG_SYS_TEXT_BASE
22   -#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
23   -#endif
24   -
25   -/*
26   - * Include common defines/options for all AMCC eval boards
27   - */
28   -#include "amcc-common.h"
29   -#define CONFIG_SYS_CLK_FREQ 50000000
30   -
31   -#define CONFIG_BOARD_TYPES 1 /* support board types */
32   -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
33   -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
34   -
35   -/*
36   - * Base addresses -- Note these are effective addresses where the
37   - * actual resources get mapped (not physical addresses)
38   - */
39   -/* EBC stuff */
40   -/* later mapped to this addr */
41   -#define CONFIG_SYS_FLASH_BASE 0xFFF00000
42   -#define CONFIG_SYS_FLASH_SIZE (4 << 20) /* 1MB usable */
43   -
44   -/* EBC Boot Space: 0xFF000000 */
45   -#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000
46   -#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 32k */
47   -#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
48   -#define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals*/
49   -
50   -#define CONFIG_SYS_SRAM_SIZE (256 << 10)
51   -/*
52   - * Initial RAM & stack pointer (placed in OCM)
53   - */
54   -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
55   -#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
56   -#define CONFIG_SYS_GBL_DATA_OFFSET \
57   - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
58   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
59   -
60   -/*
61   - * Environment
62   - */
63   -/*
64   - * Define here the location of the environment variables (FLASH).
65   - */
66   -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
67   -
68   -/*
69   - * FLASH related
70   - */
71   -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
72   -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
73   -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
74   -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
75   -/* max number of memory banks */
76   -#define CONFIG_SYS_MAX_FLASH_BANKS 1
77   -/* max number of sectors on one chip */
78   -#define CONFIG_SYS_MAX_FLASH_SECT 80
79   -/* Timeout for Flash Erase (in ms) */
80   -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
81   -/* Timeout for Flash Write (in ms) */
82   -#define CONFIG_SYS_FLASH_WRITE_TOUT 500
83   -/* use buffered writes (20x faster) */
84   -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
85   -/* print 'E' for empty sector on flinfo */
86   -#define CONFIG_SYS_FLASH_EMPTY_INFO
87   -#ifdef CONFIG_ENV_IS_IN_FLASH
88   -#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
89   -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
90   -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
91   -/* Address and size of Redundant Environment Sector */
92   -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
93   -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
94   -#endif /* CONFIG_ENV_IS_IN_FLASH */
95   -
96   -/* SDRAM */
97   -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
98   -#define SPD_EEPROM_ADDRESS {0x53, 0x51} /* SPD i2c spd addresses */
99   -#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
100   -#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
101   -#define CONFIG_DDR_ECC 1 /* with ECC support */
102   -
103   -/*
104   - * Serial Port
105   - */
106   -#define CONFIG_CONS_INDEX 1 /* Use UART0 */
107   -
108   -/*
109   - * I2C
110   - */
111   -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
112   -#define CONFIG_SYS_I2C_MULTI_EEPROMS
113   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
114   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
115   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
116   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Data sheet */
117   -
118   -/* I2C bootstrap EEPROM */
119   -#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
120   -#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
121   -#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
122   -
123   -/*
124   - * Ethernet
125   - */
126   -#define CONFIG_IBM_EMAC4_V4 1
127   -#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_NONE_RGMII
128   -#define CONFIG_HAS_ETH0
129   -/* PHY address, See schematics */
130   -#define CONFIG_PHY_ADDR 0x1f
131   -/* reset phy upon startup */
132   -#define CONFIG_PHY_RESET 1
133   -/* Include GbE speed/duplex detection */
134   -#define CONFIG_PHY_GIGE 1
135   -#define CONFIG_PHY_DYNAMIC_ANEG 1
136   -
137   -/*
138   - * External Bus Controller (EBC) Setup
139   - **/
140   -#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_LOCK | \
141   - EBC_CFG_PTD_ENABLE | \
142   - EBC_CFG_RTC_2048PERCLK | \
143   - EBC_CFG_ATC_HI | \
144   - EBC_CFG_DTC_HI | \
145   - EBC_CFG_CTC_HI | \
146   - EBC_CFG_OEO_PREVIOUS)
147   -/* NOR Flash */
148   -#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
149   - EBC_BXAP_TWT_ENCODE(64) | \
150   - EBC_BXAP_BCE_DISABLE | \
151   - EBC_BXAP_BCT_2TRANS | \
152   - EBC_BXAP_CSN_ENCODE(1) | \
153   - EBC_BXAP_OEN_ENCODE(2) | \
154   - EBC_BXAP_WBN_ENCODE(2) | \
155   - EBC_BXAP_WBF_ENCODE(2) | \
156   - EBC_BXAP_TH_ENCODE(7) | \
157   - EBC_BXAP_SOR_DELAYED | \
158   - EBC_BXAP_BEM_WRITEONLY | \
159   - EBC_BXAP_PEN_DISABLED)
160   -/* Peripheral Bank Configuration Register - EBC_BxCR */
161   -#define CONFIG_SYS_EBC_PB0CR \
162   - (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
163   - EBC_BXCR_BS_1MB | \
164   - EBC_BXCR_BU_RW | \
165   - EBC_BXCR_BW_8BIT)
166   -
167   -
168   -#endif /* __CONFIG_H */