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Commit e7be18225fbea76d1f0034b224f0d1e60f07cfcf

Authored by Tom Rini 2014-01-07 03:07:08 +0800

2 parents 895ec893a9 8c618dd66a

Exists in master and in 50 other branches

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

Showing 18 changed files Inline Diff

README
arch/powerpc/cpu/mpc85xx/speed.c
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/immap_85xx.h
board/freescale/b4860qds/b4_rcw.cfg
board/freescale/bsc9131rdb/tlb.c
board/freescale/bsc9132qds/tlb.c
board/freescale/p1010rdb/tlb.c
board/freescale/t1040qds/t1040_pbi.cfg
board/freescale/t1040qds/t1040qds.c
boards.cfg
include/configs/B4860QDS.h
include/configs/BSC9131RDB.h
include/configs/BSC9132QDS.h
include/configs/CMS700.h
include/configs/P1010RDB.h
include/configs/P1022DS.h
include/configs/T1040QDS.h

README

Diff comments View file @ e7be182

 #
 # (C) Copyright 2000 - 2013
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
 Summary:
 ========
 This directory contains the source code for U-Boot, a boot loader for
 Embedded boards based on PowerPC, ARM, MIPS and several other
 processors, which can be installed in a boot ROM and used to
 initialize and test the hardware or to download and run application
 code.
 The development of U-Boot is closely related to Linux: some parts of
 the source code originate in the Linux source tree, we have some
 header files in common, and special provision has been made to
 support booting of Linux images.
 Some attention has been paid to make this software easily
 configurable and extendable. For instance, all monitor commands are
 implemented with the same call interface, so that it's very easy to
 add new commands. Also, instead of permanently adding rarely used
 code (for instance hardware test utilities) to the monitor, you can
 load and run it dynamically.
 Status:
 =======
 In general, all boards for which a configuration option exists in the
 Makefile have been tested to some extent and can be considered
 "working". In fact, many of them are used in production systems.
 In case of problems see the CHANGELOG and CREDITS files to find out
 who contributed the specific port. The boards.cfg file lists board
 maintainers.
 Note: There is no CHANGELOG file in the actual U-Boot source tree;
 it can be created dynamically from the Git log using:
 	make CHANGELOG
 Where to get help:
 ==================
 In case you have questions about, problems with or contributions for
 U-Boot you should send a message to the U-Boot mailing list at
 <u-boot@lists.denx.de>. There is also an archive of previous traffic
 on the mailing list - please search the archive before asking FAQ's.
 Please see http://lists.denx.de/pipermail/u-boot and
 http://dir.gmane.org/gmane.comp.boot-loaders.u-boot
 Where to get source code:
 =========================
 The U-Boot source code is maintained in the git repository at
 git://www.denx.de/git/u-boot.git ; you can browse it online at
 http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=summary
 The "snapshot" links on this page allow you to download tarballs of
 any version you might be interested in. Official releases are also
 available for FTP download from the ftp://ftp.denx.de/pub/u-boot/
 directory.
 Pre-built (and tested) images are available from
 ftp://ftp.denx.de/pub/u-boot/images/
 Where we come from:
 ===================
 - start from 8xxrom sources
 - create PPCBoot project (http://sourceforge.net/projects/ppcboot)
 - clean up code
 - make it easier to add custom boards
 - make it possible to add other [PowerPC] CPUs
 - extend functions, especially:
   * Provide extended interface to Linux boot loader
   * S-Record download
   * network boot
   * PCMCIA / CompactFlash / ATA disk / SCSI ... boot
 - create ARMBoot project (http://sourceforge.net/projects/armboot)
 - add other CPU families (starting with ARM)
 - create U-Boot project (http://sourceforge.net/projects/u-boot)
 - current project page: see http://www.denx.de/wiki/U-Boot
 Names and Spelling:
 ===================
 The "official" name of this project is "Das U-Boot". The spelling
 "U-Boot" shall be used in all written text (documentation, comments
 in source files etc.). Example:
 	This is the README file for the U-Boot project.
 File names etc. shall be based on the string "u-boot". Examples:
 	include/asm-ppc/u-boot.h
 	#include <asm/u-boot.h>
 Variable names, preprocessor constants etc. shall be either based on
 the string "u_boot" or on "U_BOOT". Example:
 	U_BOOT_VERSION		u_boot_logo
 	IH_OS_U_BOOT		u_boot_hush_start
 Versioning:
 ===========
 Starting with the release in October 2008, the names of the releases
 were changed from numerical release numbers without deeper meaning
 into a time stamp based numbering. Regular releases are identified by
 names consisting of the calendar year and month of the release date.
 Additional fields (if present) indicate release candidates or bug fix
 releases in "stable" maintenance trees.
 Examples:
 	U-Boot v2009.11	    - Release November 2009
 	U-Boot v2009.11.1   - Release 1 in version November 2009 stable tree
 	U-Boot v2010.09-rc1 - Release candiate 1 for September 2010 release
 Directory Hierarchy:
 ====================
 /arch			Architecture specific files
   /arm			Files generic to ARM architecture
     /cpu		CPU specific files
       /arm720t		Files specific to ARM 720 CPUs
       /arm920t		Files specific to ARM 920 CPUs
 	/at91		Files specific to Atmel AT91RM9200 CPU
 	/imx		Files specific to Freescale MC9328 i.MX CPUs
 	/s3c24x0	Files specific to Samsung S3C24X0 CPUs
       /arm926ejs	Files specific to ARM 926 CPUs
       /arm1136		Files specific to ARM 1136 CPUs
       /ixp		Files specific to Intel XScale IXP CPUs
       /pxa		Files specific to Intel XScale PXA CPUs
       /sa1100		Files specific to Intel StrongARM SA1100 CPUs
     /lib		Architecture specific library files
   /avr32		Files generic to AVR32 architecture
     /cpu		CPU specific files
     /lib		Architecture specific library files
   /blackfin		Files generic to Analog Devices Blackfin architecture
     /cpu		CPU specific files
     /lib		Architecture specific library files
   /m68k			Files generic to m68k architecture
     /cpu		CPU specific files
       /mcf52x2		Files specific to Freescale ColdFire MCF52x2 CPUs
       /mcf5227x		Files specific to Freescale ColdFire MCF5227x CPUs
       /mcf532x		Files specific to Freescale ColdFire MCF5329 CPUs
       /mcf5445x		Files specific to Freescale ColdFire MCF5445x CPUs
       /mcf547x_8x	Files specific to Freescale ColdFire MCF547x_8x CPUs
     /lib		Architecture specific library files
   /microblaze		Files generic to microblaze architecture
     /cpu		CPU specific files
     /lib		Architecture specific library files
   /mips			Files generic to MIPS architecture
     /cpu		CPU specific files
       /mips32		Files specific to MIPS32 CPUs
       /xburst		Files specific to Ingenic XBurst CPUs
     /lib		Architecture specific library files
   /nds32		Files generic to NDS32 architecture
     /cpu		CPU specific files
       /n1213		Files specific to Andes Technology N1213 CPUs
     /lib		Architecture specific library files
   /nios2		Files generic to Altera NIOS2 architecture
     /cpu		CPU specific files
     /lib		Architecture specific library files
   /openrisc		Files generic to OpenRISC architecture
     /cpu		CPU specific files
     /lib		Architecture specific library files
   /powerpc		Files generic to PowerPC architecture
     /cpu		CPU specific files
       /74xx_7xx		Files specific to Freescale MPC74xx and 7xx CPUs
       /mpc5xx		Files specific to Freescale MPC5xx CPUs
       /mpc5xxx		Files specific to Freescale MPC5xxx CPUs
       /mpc8xx		Files specific to Freescale MPC8xx CPUs
       /mpc824x		Files specific to Freescale MPC824x CPUs
       /mpc8260		Files specific to Freescale MPC8260 CPUs
       /mpc85xx		Files specific to Freescale MPC85xx CPUs
       /ppc4xx		Files specific to AMCC PowerPC 4xx CPUs
     /lib		Architecture specific library files
   /sh			Files generic to SH architecture
     /cpu		CPU specific files
       /sh2		Files specific to sh2 CPUs
       /sh3		Files specific to sh3 CPUs
       /sh4		Files specific to sh4 CPUs
     /lib		Architecture specific library files
   /sparc		Files generic to SPARC architecture
     /cpu		CPU specific files
       /leon2		Files specific to Gaisler LEON2 SPARC CPU
       /leon3		Files specific to Gaisler LEON3 SPARC CPU
     /lib		Architecture specific library files
   /x86			Files generic to x86 architecture
     /cpu		CPU specific files
     /lib		Architecture specific library files
 /api			Machine/arch independent API for external apps
 /board			Board dependent files
 /common			Misc architecture independent functions
 /disk			Code for disk drive partition handling
 /doc			Documentation (don't expect too much)
 /drivers		Commonly used device drivers
 /dts			Contains Makefile for building internal U-Boot fdt.
 /examples		Example code for standalone applications, etc.
 /fs			Filesystem code (cramfs, ext2, jffs2, etc.)
 /include		Header Files
 /lib			Files generic to all architectures
   /libfdt		Library files to support flattened device trees
   /lzma			Library files to support LZMA decompression
   /lzo			Library files to support LZO decompression
 /net			Networking code
 /post			Power On Self Test
 /spl			Secondary Program Loader framework
 /tools			Tools to build S-Record or U-Boot images, etc.
 Software Configuration:
 =======================
 Configuration is usually done using C preprocessor defines; the
 rationale behind that is to avoid dead code whenever possible.
 There are two classes of configuration variables:
 * Configuration _OPTIONS_:
   These are selectable by the user and have names beginning with
   "CONFIG_".
 * Configuration _SETTINGS_:
   These depend on the hardware etc. and should not be meddled with if
   you don't know what you're doing; they have names beginning with
   "CONFIG_SYS_".
 Later we will add a configuration tool - probably similar to or even
 identical to what's used for the Linux kernel. Right now, we have to
 do the configuration by hand, which means creating some symbolic
 links and editing some configuration files. We use the TQM8xxL boards
 as an example here.
 Selection of Processor Architecture and Board Type:
 ---------------------------------------------------
 For all supported boards there are ready-to-use default
 configurations available; just type "make <board_name>_config".
 Example: For a TQM823L module type:
 	cd u-boot
 	make TQM823L_config
 For the Cogent platform, you need to specify the CPU type as well;
 e.g. "make cogent_mpc8xx_config". And also configure the cogent
 directory according to the instructions in cogent/README.
 Configuration Options:
 ----------------------
 Configuration depends on the combination of board and CPU type; all
 such information is kept in a configuration file
 "include/configs/<board_name>.h".
 Example: For a TQM823L module, all configuration settings are in
 "include/configs/TQM823L.h".
 Many of the options are named exactly as the corresponding Linux
 kernel configuration options. The intention is to make it easier to
 build a config tool - later.
 The following options need to be configured:
 - CPU Type:	Define exactly one, e.g. CONFIG_MPC85XX.
 - Board Type:	Define exactly one, e.g. CONFIG_MPC8540ADS.
 - CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
 		Define exactly one, e.g. CONFIG_ATSTK1002
 - CPU Module Type: (if CONFIG_COGENT is defined)
 		Define exactly one of
 		CONFIG_CMA286_60_OLD
 --- FIXME --- not tested yet:
 		CONFIG_CMA286_60, CONFIG_CMA286_21, CONFIG_CMA286_60P,
 		CONFIG_CMA287_23, CONFIG_CMA287_50
 - Motherboard Type: (if CONFIG_COGENT is defined)
 		Define exactly one of
 		CONFIG_CMA101, CONFIG_CMA102
 - Motherboard I/O Modules: (if CONFIG_COGENT is defined)
 		Define one or more of
 		CONFIG_CMA302
 - Motherboard Options: (if CONFIG_CMA101 or CONFIG_CMA102 are defined)
 		Define one or more of
 		CONFIG_LCD_HEARTBEAT	- update a character position on
 					  the LCD display every second with
 					  a "rotator" |\-/|\-/
 - Board flavour: (if CONFIG_MPC8260ADS is defined)
 		CONFIG_ADSTYPE
 		Possible values are:
 			CONFIG_SYS_8260ADS	- original MPC8260ADS
 			CONFIG_SYS_8266ADS	- MPC8266ADS
 			CONFIG_SYS_PQ2FADS	- PQ2FADS-ZU or PQ2FADS-VR
 			CONFIG_SYS_8272ADS	- MPC8272ADS
 - Marvell Family Member
 		CONFIG_SYS_MVFS		- define it if you want to enable
 					  multiple fs option at one time
 					  for marvell soc family
 - MPC824X Family Member (if CONFIG_MPC824X is defined)
 		Define exactly one of
 		CONFIG_MPC8240, CONFIG_MPC8245
 - 8xx CPU Options: (if using an MPC8xx CPU)
 		CONFIG_8xx_GCLK_FREQ	- deprecated: CPU clock if
 					  get_gclk_freq() cannot work
 					  e.g. if there is no 32KHz
 					  reference PIT/RTC clock
 		CONFIG_8xx_OSCLK	- PLL input clock (either EXTCLK
 					  or XTAL/EXTAL)
 - 859/866/885 CPU options: (if using a MPC859 or MPC866 or MPC885 CPU):
 		CONFIG_SYS_8xx_CPUCLK_MIN
 		CONFIG_SYS_8xx_CPUCLK_MAX
 		CONFIG_8xx_CPUCLK_DEFAULT
 			See doc/README.MPC866
 		CONFIG_SYS_MEASURE_CPUCLK
 		Define this to measure the actual CPU clock instead
 		of relying on the correctness of the configured
 		values. Mostly useful for board bringup to make sure
 		the PLL is locked at the intended frequency. Note
 		that this requires a (stable) reference clock (32 kHz
 		RTC clock or CONFIG_SYS_8XX_XIN)
 		CONFIG_SYS_DELAYED_ICACHE
 		Define this option if you want to enable the
 		ICache only when Code runs from RAM.
 - 85xx CPU Options:
 		CONFIG_SYS_PPC64
 		Specifies that the core is a 64-bit PowerPC implementation (implements
 		the "64" category of the Power ISA). This is necessary for ePAPR
 		compliance, among other possible reasons.
 		CONFIG_SYS_FSL_TBCLK_DIV
 		Defines the core time base clock divider ratio compared to the
 		system clock.  On most PQ3 devices this is 8, on newer QorIQ
 		devices it can be 16 or 32.  The ratio varies from SoC to Soc.
 		CONFIG_SYS_FSL_PCIE_COMPAT
 		Defines the string to utilize when trying to match PCIe device
 		tree nodes for the given platform.
 		CONFIG_SYS_PPC_E500_DEBUG_TLB
 		Enables a temporary TLB entry to be used during boot to work
 		around limitations in e500v1 and e500v2 external debugger
 		support. This reduces the portions of the boot code where
 		breakpoints and single stepping do not work.  The value of this
 		symbol should be set to the TLB1 entry to be used for this
 		purpose.
 		CONFIG_SYS_FSL_ERRATUM_A004510
 		Enables a workaround for erratum A004510.  If set,
 		then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and
 		CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
 		CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
 		CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional)
 		Defines one or two SoC revisions (low 8 bits of SVR)
 		for which the A004510 workaround should be applied.
 		The rest of SVR is either not relevant to the decision
 		of whether the erratum is present (e.g. p2040 versus
 		p2041) or is implied by the build target, which controls
 		whether CONFIG_SYS_FSL_ERRATUM_A004510 is set.
 		See Freescale App Note 4493 for more information about
 		this erratum.
 		CONFIG_A003399_NOR_WORKAROUND
 		Enables a workaround for IFC erratum A003399. It is only
 		requred during NOR boot.
 		CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
 		This is the value to write into CCSR offset 0x18600
 		according to the A004510 workaround.
 		CONFIG_SYS_FSL_DSP_DDR_ADDR
 		This value denotes start offset of DDR memory which is
 		connected exclusively to the DSP cores.
 		CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
 		This value denotes start offset of M2 memory
 		which is directly connected to the DSP core.
 		CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
 		This value denotes start offset of M3 memory which is directly
 		connected to the DSP core.
 		CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
 		This value denotes start offset of DSP CCSR space.
+		CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+		Single Source Clock is clocking mode present in some of FSL SoC's.
+		In this mode, a single differential clock is used to supply
+		clocks to the sysclock, ddrclock and usbclock.
 - Generic CPU options:
 		CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 		Defines the endianess of the CPU. Implementation of those
 		values is arch specific.
 		CONFIG_SYS_FSL_DDR
 		Freescale DDR driver in use. This type of DDR controller is
 		found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
 		SoCs.
 		CONFIG_SYS_FSL_DDR_ADDR
 		Freescale DDR memory-mapped register base.
 		CONFIG_SYS_FSL_DDR_EMU
 		Specify emulator support for DDR. Some DDR features such as
 		deskew training are not available.
 		CONFIG_SYS_FSL_DDRC_GEN1
 		Freescale DDR1 controller.
 		CONFIG_SYS_FSL_DDRC_GEN2
 		Freescale DDR2 controller.
 		CONFIG_SYS_FSL_DDRC_GEN3
 		Freescale DDR3 controller.
 		CONFIG_SYS_FSL_DDRC_ARM_GEN3
 		Freescale DDR3 controller for ARM-based SoCs.
 		CONFIG_SYS_FSL_DDR1
 		Board config to use DDR1. It can be enabled for SoCs with
 		Freescale DDR1 or DDR2 controllers, depending on the board
 		implemetation.
 		CONFIG_SYS_FSL_DDR2
 		Board config to use DDR2. It can be eanbeld for SoCs with
 		Freescale DDR2 or DDR3 controllers, depending on the board
 		implementation.
 		CONFIG_SYS_FSL_DDR3
 		Board config to use DDR3. It can be enabled for SoCs with
 		Freescale DDR3 controllers.
 - Intel Monahans options:
 		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 		Defines the Monahans run mode to oscillator
 		ratio. Valid values are 8, 16, 24, 31. The core
 		frequency is this value multiplied by 13 MHz.
 		CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
 		Defines the Monahans turbo mode to oscillator
 		ratio. Valid values are 1 (default if undefined) and
 		2. The core frequency as calculated above is multiplied
 		by this value.
 - MIPS CPU options:
 		CONFIG_SYS_INIT_SP_OFFSET
 		Offset relative to CONFIG_SYS_SDRAM_BASE for initial stack
 		pointer. This is needed for the temporary stack before
 		relocation.
 		CONFIG_SYS_MIPS_CACHE_MODE
 		Cache operation mode for the MIPS CPU.
 		See also arch/mips/include/asm/mipsregs.h.
 		Possible values are:
 			CONF_CM_CACHABLE_NO_WA
 			CONF_CM_CACHABLE_WA
 			CONF_CM_UNCACHED
 			CONF_CM_CACHABLE_NONCOHERENT
 			CONF_CM_CACHABLE_CE
 			CONF_CM_CACHABLE_COW
 			CONF_CM_CACHABLE_CUW
 			CONF_CM_CACHABLE_ACCELERATED
 		CONFIG_SYS_XWAY_EBU_BOOTCFG
 		Special option for Lantiq XWAY SoCs for booting from NOR flash.
 		See also arch/mips/cpu/mips32/start.S.
 		CONFIG_XWAY_SWAP_BYTES
 		Enable compilation of tools/xway-swap-bytes needed for Lantiq
 		XWAY SoCs for booting from NOR flash. The U-Boot image needs to
 		be swapped if a flash programmer is used.
 - ARM options:
 		CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 		Select high exception vectors of the ARM core, e.g., do not
 		clear the V bit of the c1 register of CP15.
 		CONFIG_SYS_THUMB_BUILD
 		Use this flag to build U-Boot using the Thumb instruction
 		set for ARM architectures. Thumb instruction set provides
 		better code density. For ARM architectures that support
 		Thumb2 this flag will result in Thumb2 code generated by
 		GCC.
 		CONFIG_ARM_ERRATA_716044
 		CONFIG_ARM_ERRATA_742230
 		CONFIG_ARM_ERRATA_743622
 		CONFIG_ARM_ERRATA_751472
 		If set, the workarounds for these ARM errata are applied early
 		during U-Boot startup. Note that these options force the
 		workarounds to be applied; no CPU-type/version detection
 		exists, unlike the similar options in the Linux kernel. Do not
 		set these options unless they apply!
 - CPU timer options:
 		CONFIG_SYS_HZ
 		The frequency of the timer returned by get_timer().
 		get_timer() must operate in milliseconds and this CONFIG
 		option must be set to 1000.
 - Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ
 		U-Boot stores all clock information in Hz
 		internally. For binary compatibility with older Linux
 		kernels (which expect the clocks passed in the
 		bd_info data to be in MHz) the environment variable
 		"clocks_in_mhz" can be defined so that U-Boot
 		converts clock data to MHZ before passing it to the
 		Linux kernel.
 		When CONFIG_CLOCKS_IN_MHZ is defined, a definition of
 		"clocks_in_mhz=1" is automatically included in the
 		default environment.
 		CONFIG_MEMSIZE_IN_BYTES		[relevant for MIPS only]
 		When transferring memsize parameter to linux, some versions
 		expect it to be in bytes, others in MB.
 		Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
 		CONFIG_OF_LIBFDT
 		New kernel versions are expecting firmware settings to be
 		passed using flattened device trees (based on open firmware
 		concepts).
 		CONFIG_OF_LIBFDT
 		 * New libfdt-based support
 		 * Adds the "fdt" command
 		 * The bootm command automatically updates the fdt
 		OF_CPU - The proper name of the cpus node (only required for
 			MPC512X and MPC5xxx based boards).
 		OF_SOC - The proper name of the soc node (only required for
 			MPC512X and MPC5xxx based boards).
 		OF_TBCLK - The timebase frequency.
 		OF_STDOUT_PATH - The path to the console device
 		boards with QUICC Engines require OF_QE to set UCC MAC
 		addresses
 		CONFIG_OF_BOARD_SETUP
 		Board code has addition modification that it wants to make
 		to the flat device tree before handing it off to the kernel
 		CONFIG_OF_BOOT_CPU
 		This define fills in the correct boot CPU in the boot
 		param header, the default value is zero if undefined.
 		CONFIG_OF_IDE_FIXUP
 		U-Boot can detect if an IDE device is present or not.
 		If not, and this new config option is activated, U-Boot
 		removes the ATA node from the DTS before booting Linux,
 		so the Linux IDE driver does not probe the device and
 		crash. This is needed for buggy hardware (uc101) where
 		no pull down resistor is connected to the signal IDE5V_DD7.
 		CONFIG_MACH_TYPE	[relevant for ARM only][mandatory]
 		This setting is mandatory for all boards that have only one
 		machine type and must be used to specify the machine type
 		number as it appears in the ARM machine registry
 		(see http://www.arm.linux.org.uk/developer/machines/).
 		Only boards that have multiple machine types supported
 		in a single configuration file and the machine type is
 		runtime discoverable, do not have to use this setting.
 - vxWorks boot parameters:
 		bootvx constructs a valid bootline using the following
 		environments variables: bootfile, ipaddr, serverip, hostname.
 		It loads the vxWorks image pointed bootfile.
 		CONFIG_SYS_VXWORKS_BOOT_DEVICE - The vxworks device name
 		CONFIG_SYS_VXWORKS_MAC_PTR - Ethernet 6 byte MA -address
 		CONFIG_SYS_VXWORKS_SERVERNAME - Name of the server
 		CONFIG_SYS_VXWORKS_BOOT_ADDR - Address of boot parameters
 		CONFIG_SYS_VXWORKS_ADD_PARAMS
 		Add it at the end of the bootline. E.g "u=username pw=secret"
 		Note: If a "bootargs" environment is defined, it will overwride
 		the defaults discussed just above.
 - Cache Configuration:
 		CONFIG_SYS_ICACHE_OFF - Do not enable instruction cache in U-Boot
 		CONFIG_SYS_DCACHE_OFF - Do not enable data cache in U-Boot
 		CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot
 - Cache Configuration for ARM:
 		CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache
 				      controller
 		CONFIG_SYS_PL310_BASE - Physical base address of PL310
 					controller register space
 - Serial Ports:
 		CONFIG_PL010_SERIAL
 		Define this if you want support for Amba PrimeCell PL010 UARTs.
 		CONFIG_PL011_SERIAL
 		Define this if you want support for Amba PrimeCell PL011 UARTs.
 		CONFIG_PL011_CLOCK
 		If you have Amba PrimeCell PL011 UARTs, set this variable to
 		the clock speed of the UARTs.
 		CONFIG_PL01x_PORTS
 		If you have Amba PrimeCell PL010 or PL011 UARTs on your board,
 		define this to a list of base addresses for each (supported)
 		port. See e.g. include/configs/versatile.h
 		CONFIG_PL011_SERIAL_RLCR
 		Some vendor versions of PL011 serial ports (e.g. ST-Ericsson U8500)
 		have separate receive and transmit line control registers.  Set
 		this variable to initialize the extra register.
 		CONFIG_PL011_SERIAL_FLUSH_ON_INIT
 		On some platforms (e.g. U8500) U-Boot is loaded by a second stage
 		boot loader that has already initialized the UART.  Define this
 		variable to flush the UART at init time.
 - Console Interface:
 		Depending on board, define exactly one serial port
 		(like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2,
 		CONFIG_8xx_CONS_SCC1, ...), or switch off the serial
 		console by defining CONFIG_8xx_CONS_NONE
 		Note: if CONFIG_8xx_CONS_NONE is defined, the serial
 		port routines must be defined elsewhere
 		(i.e. serial_init(), serial_getc(), ...)
 		CONFIG_CFB_CONSOLE
 		Enables console device for a color framebuffer. Needs following
 		defines (cf. smiLynxEM, i8042)
 			VIDEO_FB_LITTLE_ENDIAN	graphic memory organisation
 						(default big endian)
 			VIDEO_HW_RECTFILL	graphic chip supports
 						rectangle fill
 						(cf. smiLynxEM)
 			VIDEO_HW_BITBLT		graphic chip supports
 						bit-blit (cf. smiLynxEM)
 			VIDEO_VISIBLE_COLS	visible pixel columns
 						(cols=pitch)
 			VIDEO_VISIBLE_ROWS	visible pixel rows
 			VIDEO_PIXEL_SIZE	bytes per pixel
 			VIDEO_DATA_FORMAT	graphic data format
 						(0-5, cf. cfb_console.c)
 			VIDEO_FB_ADRS		framebuffer address
 			VIDEO_KBD_INIT_FCT	keyboard int fct
 						(i.e. i8042_kbd_init())
 			VIDEO_TSTC_FCT		test char fct
 						(i.e. i8042_tstc)
 			VIDEO_GETC_FCT		get char fct
 						(i.e. i8042_getc)
 			CONFIG_CONSOLE_CURSOR	cursor drawing on/off
 						(requires blink timer
 						cf. i8042.c)
 			CONFIG_SYS_CONSOLE_BLINK_COUNT blink interval (cf. i8042.c)
 			CONFIG_CONSOLE_TIME	display time/date info in
 						upper right corner
 						(requires CONFIG_CMD_DATE)
 			CONFIG_VIDEO_LOGO	display Linux logo in
 						upper left corner
 			CONFIG_VIDEO_BMP_LOGO	use bmp_logo.h instead of
 						linux_logo.h for logo.
 						Requires CONFIG_VIDEO_LOGO
 			CONFIG_CONSOLE_EXTRA_INFO
 						additional board info beside
 						the logo
 		When CONFIG_CFB_CONSOLE_ANSI is defined, console will support
 		a limited number of ANSI escape sequences (cursor control,
 		erase functions and limited graphics rendition control).
 		When CONFIG_CFB_CONSOLE is defined, video console is
 		default i/o. Serial console can be forced with
 		environment 'console=serial'.
 		When CONFIG_SILENT_CONSOLE is defined, all console
 		messages (by U-Boot and Linux!) can be silenced with
 		the "silent" environment variable. See
 		doc/README.silent for more information.
 		CONFIG_SYS_CONSOLE_BG_COL: define the backgroundcolor, default
 			is 0x00.
 		CONFIG_SYS_CONSOLE_FG_COL: define the foregroundcolor, default
 			is 0xa0.
 - Console Baudrate:
 		CONFIG_BAUDRATE - in bps
 		Select one of the baudrates listed in
 		CONFIG_SYS_BAUDRATE_TABLE, see below.
 		CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale
 - Console Rx buffer length
 		With CONFIG_SYS_SMC_RXBUFLEN it is possible to define
 		the maximum receive buffer length for the SMC.
 		This option is actual only for 82xx and 8xx possible.
 		If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE
 		must be defined, to setup the maximum idle timeout for
 		the SMC.
 - Pre-Console Buffer:
 		Prior to the console being initialised (i.e. serial UART
 		initialised etc) all console output is silently discarded.
 		Defining CONFIG_PRE_CONSOLE_BUFFER will cause U-Boot to
 		buffer any console messages prior to the console being
 		initialised to a buffer of size CONFIG_PRE_CON_BUF_SZ
 		bytes located at CONFIG_PRE_CON_BUF_ADDR. The buffer is
 		a circular buffer, so if more than CONFIG_PRE_CON_BUF_SZ
 		bytes are output before the console is initialised, the
 		earlier bytes are discarded.
 		'Sane' compilers will generate smaller code if
 		CONFIG_PRE_CON_BUF_SZ is a power of 2
 - Safe printf() functions
 		Define CONFIG_SYS_VSNPRINTF to compile in safe versions of
 		the printf() functions. These are defined in
 		include/vsprintf.h and include snprintf(), vsnprintf() and
 		so on. Code size increase is approximately 300-500 bytes.
 		If this option is not given then these functions will
 		silently discard their buffer size argument - this means
 		you are not getting any overflow checking in this case.
 - Boot Delay:	CONFIG_BOOTDELAY - in seconds
 		Delay before automatically booting the default image;
 		set to -1 to disable autoboot.
 		set to -2 to autoboot with no delay and not check for abort
 		(even when CONFIG_ZERO_BOOTDELAY_CHECK is defined).
 		See doc/README.autoboot for these options that
 		work with CONFIG_BOOTDELAY. None are required.
 		CONFIG_BOOT_RETRY_TIME
 		CONFIG_BOOT_RETRY_MIN
 		CONFIG_AUTOBOOT_KEYED
 		CONFIG_AUTOBOOT_PROMPT
 		CONFIG_AUTOBOOT_DELAY_STR
 		CONFIG_AUTOBOOT_STOP_STR
 		CONFIG_AUTOBOOT_DELAY_STR2
 		CONFIG_AUTOBOOT_STOP_STR2
 		CONFIG_ZERO_BOOTDELAY_CHECK
 		CONFIG_RESET_TO_RETRY
 - Autoboot Command:
 		CONFIG_BOOTCOMMAND
 		Only needed when CONFIG_BOOTDELAY is enabled;
 		define a command string that is automatically executed
 		when no character is read on the console interface
 		within "Boot Delay" after reset.
 		CONFIG_BOOTARGS
 		This can be used to pass arguments to the bootm
 		command. The value of CONFIG_BOOTARGS goes into the
 		environment value "bootargs".
 		CONFIG_RAMBOOT and CONFIG_NFSBOOT
 		The value of these goes into the environment as
 		"ramboot" and "nfsboot" respectively, and can be used
 		as a convenience, when switching between booting from
 		RAM and NFS.
 - Bootcount:
 		CONFIG_BOOTCOUNT_LIMIT
 		Implements a mechanism for detecting a repeating reboot
 		cycle, see:
 		http://www.denx.de/wiki/view/DULG/UBootBootCountLimit
 		CONFIG_BOOTCOUNT_ENV
 		If no softreset save registers are found on the hardware
 		"bootcount" is stored in the environment. To prevent a
 		saveenv on all reboots, the environment variable
 		"upgrade_available" is used. If "upgrade_available" is
 		0, "bootcount" is always 0, if "upgrade_available" is
 		1 "bootcount" is incremented in the environment.
 		So the Userspace Applikation must set the "upgrade_available"
 		and "bootcount" variable to 0, if a boot was successfully.
 - Pre-Boot Commands:
 		CONFIG_PREBOOT
 		When this option is #defined, the existence of the
 		environment variable "preboot" will be checked
 		immediately before starting the CONFIG_BOOTDELAY
 		countdown and/or running the auto-boot command resp.
 		entering interactive mode.
 		This feature is especially useful when "preboot" is
 		automatically generated or modified. For an example
 		see the LWMON board specific code: here "preboot" is
 		modified when the user holds down a certain
 		combination of keys on the (special) keyboard when
 		booting the systems
 - Serial Download Echo Mode:
 		CONFIG_LOADS_ECHO
 		If defined to 1, all characters received during a
 		serial download (using the "loads" command) are
 		echoed back. This might be needed by some terminal
 		emulations (like "cu"), but may as well just take
 		time on others. This setting #define's the initial
 		value of the "loads_echo" environment variable.
 - Kgdb Serial Baudrate: (if CONFIG_CMD_KGDB is defined)
 		CONFIG_KGDB_BAUDRATE
 		Select one of the baudrates listed in
 		CONFIG_SYS_BAUDRATE_TABLE, see below.
 - Monitor Functions:
 		Monitor commands can be included or excluded
 		from the build by using the #include files
 		<config_cmd_all.h> and #undef'ing unwanted
 		commands, or using <config_cmd_default.h>
 		and augmenting with additional #define's
 		for wanted commands.
 		The default command configuration includes all commands
 		except those marked below with a "*".
 		CONFIG_CMD_ASKENV	* ask for env variable
 		CONFIG_CMD_BDI		  bdinfo
 		CONFIG_CMD_BEDBUG	* Include BedBug Debugger
 		CONFIG_CMD_BMP		* BMP support
 		CONFIG_CMD_BSP		* Board specific commands
 		CONFIG_CMD_BOOTD	  bootd
 		CONFIG_CMD_CACHE	* icache, dcache
 		CONFIG_CMD_CONSOLE	  coninfo
 		CONFIG_CMD_CRC32	* crc32
 		CONFIG_CMD_DATE		* support for RTC, date/time...
 		CONFIG_CMD_DHCP		* DHCP support
 		CONFIG_CMD_DIAG		* Diagnostics
 		CONFIG_CMD_DS4510	* ds4510 I2C gpio commands
 		CONFIG_CMD_DS4510_INFO	* ds4510 I2C info command
 		CONFIG_CMD_DS4510_MEM	* ds4510 I2C eeprom/sram commansd
 		CONFIG_CMD_DS4510_RST	* ds4510 I2C rst command
 		CONFIG_CMD_DTT		* Digital Therm and Thermostat
 		CONFIG_CMD_ECHO		  echo arguments
 		CONFIG_CMD_EDITENV	  edit env variable
 		CONFIG_CMD_EEPROM	* EEPROM read/write support
 		CONFIG_CMD_ELF		* bootelf, bootvx
 		CONFIG_CMD_ENV_CALLBACK	* display details about env callbacks
 		CONFIG_CMD_ENV_FLAGS	* display details about env flags
 		CONFIG_CMD_ENV_EXISTS	* check existence of env variable
 		CONFIG_CMD_EXPORTENV	* export the environment
 		CONFIG_CMD_EXT2		* ext2 command support
 		CONFIG_CMD_EXT4		* ext4 command support
 		CONFIG_CMD_SAVEENV	  saveenv
 		CONFIG_CMD_FDC		* Floppy Disk Support
 		CONFIG_CMD_FAT		* FAT command support
 		CONFIG_CMD_FDOS		* Dos diskette Support
 		CONFIG_CMD_FLASH	  flinfo, erase, protect
 		CONFIG_CMD_FPGA		  FPGA device initialization support
 		CONFIG_CMD_FUSE		* Device fuse support
 		CONFIG_CMD_GETTIME	* Get time since boot
 		CONFIG_CMD_GO		* the 'go' command (exec code)
 		CONFIG_CMD_GREPENV	* search environment
 		CONFIG_CMD_HASH		* calculate hash / digest
 		CONFIG_CMD_HWFLOW	* RTS/CTS hw flow control
 		CONFIG_CMD_I2C		* I2C serial bus support
 		CONFIG_CMD_IDE		* IDE harddisk support
 		CONFIG_CMD_IMI		  iminfo
 		CONFIG_CMD_IMLS		  List all images found in NOR flash
 		CONFIG_CMD_IMLS_NAND	* List all images found in NAND flash
 		CONFIG_CMD_IMMAP	* IMMR dump support
 		CONFIG_CMD_IMPORTENV	* import an environment
 		CONFIG_CMD_INI		* import data from an ini file into the env
 		CONFIG_CMD_IRQ		* irqinfo
 		CONFIG_CMD_ITEST	  Integer/string test of 2 values
 		CONFIG_CMD_JFFS2	* JFFS2 Support
 		CONFIG_CMD_KGDB		* kgdb
 		CONFIG_CMD_LDRINFO	* ldrinfo (display Blackfin loader)
 		CONFIG_CMD_LINK_LOCAL	* link-local IP address auto-configuration
 					  (169.254.*.*)
 		CONFIG_CMD_LOADB	  loadb
 		CONFIG_CMD_LOADS	  loads
 		CONFIG_CMD_MD5SUM	* print md5 message digest
 					  (requires CONFIG_CMD_MEMORY and CONFIG_MD5)
 		CONFIG_CMD_MEMINFO	* Display detailed memory information
 		CONFIG_CMD_MEMORY	  md, mm, nm, mw, cp, cmp, crc, base,
 					  loop, loopw
 		CONFIG_CMD_MEMTEST	* mtest
 		CONFIG_CMD_MISC		  Misc functions like sleep etc
 		CONFIG_CMD_MMC		* MMC memory mapped support
 		CONFIG_CMD_MII		* MII utility commands
 		CONFIG_CMD_MTDPARTS	* MTD partition support
 		CONFIG_CMD_NAND		* NAND support
 		CONFIG_CMD_NET		  bootp, tftpboot, rarpboot
 		CONFIG_CMD_NFS		  NFS support
 		CONFIG_CMD_PCA953X	* PCA953x I2C gpio commands
 		CONFIG_CMD_PCA953X_INFO * PCA953x I2C gpio info command
 		CONFIG_CMD_PCI		* pciinfo
 		CONFIG_CMD_PCMCIA		* PCMCIA support
 		CONFIG_CMD_PING		* send ICMP ECHO_REQUEST to network
 					  host
 		CONFIG_CMD_PORTIO	* Port I/O
 		CONFIG_CMD_READ		* Read raw data from partition
 		CONFIG_CMD_REGINFO	* Register dump
 		CONFIG_CMD_RUN		  run command in env variable
 		CONFIG_CMD_SANDBOX	* sb command to access sandbox features
 		CONFIG_CMD_SAVES	* save S record dump
 		CONFIG_CMD_SCSI		* SCSI Support
 		CONFIG_CMD_SDRAM	* print SDRAM configuration information
 					  (requires CONFIG_CMD_I2C)
 		CONFIG_CMD_SETGETDCR	  Support for DCR Register access
 					  (4xx only)
 		CONFIG_CMD_SF		* Read/write/erase SPI NOR flash
 		CONFIG_CMD_SHA1SUM	* print sha1 memory digest
 					  (requires CONFIG_CMD_MEMORY)
 		CONFIG_CMD_SOFTSWITCH	* Soft switch setting command for BF60x
 		CONFIG_CMD_SOURCE	  "source" command Support
 		CONFIG_CMD_SPI		* SPI serial bus support
 		CONFIG_CMD_TFTPSRV	* TFTP transfer in server mode
 		CONFIG_CMD_TFTPPUT	* TFTP put command (upload)
 		CONFIG_CMD_TIME		* run command and report execution time (ARM specific)
 		CONFIG_CMD_TIMER	* access to the system tick timer
 		CONFIG_CMD_USB		* USB support
 		CONFIG_CMD_CDP		* Cisco Discover Protocol support
 		CONFIG_CMD_MFSL		* Microblaze FSL support
 		CONFIG_CMD_XIMG		  Load part of Multi Image
 		EXAMPLE: If you want all functions except of network
 		support you can write:
 		#include "config_cmd_all.h"
 		#undef CONFIG_CMD_NET
 	Other Commands:
 		fdt (flattened device tree) command: CONFIG_OF_LIBFDT
 	Note:	Don't enable the "icache" and "dcache" commands
 		(configuration option CONFIG_CMD_CACHE) unless you know
 		what you (and your U-Boot users) are doing. Data
 		cache cannot be enabled on systems like the 8xx or
 		8260 (where accesses to the IMMR region must be
 		uncached), and it cannot be disabled on all other
 		systems where we (mis-) use the data cache to hold an
 		initial stack and some data.
 		XXX - this list needs to get updated!
 - Regular expression support:
 		CONFIG_REGEX
 		If this variable is defined, U-Boot is linked against
 		the SLRE (Super Light Regular Expression) library,
 		which adds regex support to some commands, as for
 		example "env grep" and "setexpr".
 - Device tree:
 		CONFIG_OF_CONTROL
 		If this variable is defined, U-Boot will use a device tree
 		to configure its devices, instead of relying on statically
 		compiled #defines in the board file. This option is
 		experimental and only available on a few boards. The device
 		tree is available in the global data as gd->fdt_blob.
 		U-Boot needs to get its device tree from somewhere. This can
 		be done using one of the two options below:
 		CONFIG_OF_EMBED
 		If this variable is defined, U-Boot will embed a device tree
 		binary in its image. This device tree file should be in the
 		board directory and called <soc>-<board>.dts. The binary file
 		is then picked up in board_init_f() and made available through
 		the global data structure as gd->blob.
 		CONFIG_OF_SEPARATE
 		If this variable is defined, U-Boot will build a device tree
 		binary. It will be called u-boot.dtb. Architecture-specific
 		code will locate it at run-time. Generally this works by:
 			cat u-boot.bin u-boot.dtb >image.bin
 		and in fact, U-Boot does this for you, creating a file called
 		u-boot-dtb.bin which is useful in the common case. You can
 		still use the individual files if you need something more
 		exotic.
 - Watchdog:
 		CONFIG_WATCHDOG
 		If this variable is defined, it enables watchdog
 		support for the SoC. There must be support in the SoC
 		specific code for a watchdog. For the 8xx and 8260
 		CPUs, the SIU Watchdog feature is enabled in the SYPCR
 		register.  When supported for a specific SoC is
 		available, then no further board specific code should
 		be needed to use it.
 		CONFIG_HW_WATCHDOG
 		When using a watchdog circuitry external to the used
 		SoC, then define this variable and provide board
 		specific code for the "hw_watchdog_reset" function.
 - U-Boot Version:
 		CONFIG_VERSION_VARIABLE
 		If this variable is defined, an environment variable
 		named "ver" is created by U-Boot showing the U-Boot
 		version as printed by the "version" command.
 		Any change to this variable will be reverted at the
 		next reset.
 - Real-Time Clock:
 		When CONFIG_CMD_DATE is selected, the type of the RTC
 		has to be selected, too. Define exactly one of the
 		following options:
 		CONFIG_RTC_MPC8xx	- use internal RTC of MPC8xx
 		CONFIG_RTC_PCF8563	- use Philips PCF8563 RTC
 		CONFIG_RTC_MC13XXX	- use MC13783 or MC13892 RTC
 		CONFIG_RTC_MC146818	- use MC146818 RTC
 		CONFIG_RTC_DS1307	- use Maxim, Inc. DS1307 RTC
 		CONFIG_RTC_DS1337	- use Maxim, Inc. DS1337 RTC
 		CONFIG_RTC_DS1338	- use Maxim, Inc. DS1338 RTC
 		CONFIG_RTC_DS164x	- use Dallas DS164x RTC
 		CONFIG_RTC_ISL1208	- use Intersil ISL1208 RTC
 		CONFIG_RTC_MAX6900	- use Maxim, Inc. MAX6900 RTC
 		CONFIG_SYS_RTC_DS1337_NOOSC	- Turn off the OSC output for DS1337
 		CONFIG_SYS_RV3029_TCR	- enable trickle charger on
 					  RV3029 RTC.
 		Note that if the RTC uses I2C, then the I2C interface
 		must also be configured. See I2C Support, below.
 - GPIO Support:
 		CONFIG_PCA953X		- use NXP's PCA953X series I2C GPIO
 		The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of
 		chip-ngpio pairs that tell the PCA953X driver the number of
 		pins supported by a particular chip.
 		Note that if the GPIO device uses I2C, then the I2C interface
 		must also be configured. See I2C Support, below.
 - Timestamp Support:
 		When CONFIG_TIMESTAMP is selected, the timestamp
 		(date and time) of an image is printed by image
 		commands like bootm or iminfo. This option is
 		automatically enabled when you select CONFIG_CMD_DATE .
 - Partition Labels (disklabels) Supported:
 		Zero or more of the following:
 		CONFIG_MAC_PARTITION   Apple's MacOS partition table.
 		CONFIG_DOS_PARTITION   MS Dos partition table, traditional on the
 				       Intel architecture, USB sticks, etc.
 		CONFIG_ISO_PARTITION   ISO partition table, used on CDROM etc.
 		CONFIG_EFI_PARTITION   GPT partition table, common when EFI is the
 				       bootloader.  Note 2TB partition limit; see
 				       disk/part_efi.c
 		CONFIG_MTD_PARTITIONS  Memory Technology Device partition table.
 		If IDE or SCSI support is enabled (CONFIG_CMD_IDE or
 		CONFIG_CMD_SCSI) you must configure support for at
 		least one non-MTD partition type as well.
 - IDE Reset method:
 		CONFIG_IDE_RESET_ROUTINE - this is defined in several
 		board configurations files but used nowhere!
 		CONFIG_IDE_RESET - is this is defined, IDE Reset will
 		be performed by calling the function
 			ide_set_reset(int reset)
 		which has to be defined in a board specific file
 - ATAPI Support:
 		CONFIG_ATAPI
 		Set this to enable ATAPI support.
 - LBA48 Support
 		CONFIG_LBA48
 		Set this to enable support for disks larger than 137GB
 		Also look at CONFIG_SYS_64BIT_LBA.
 		Whithout these , LBA48 support uses 32bit variables and will 'only'
 		support disks up to 2.1TB.
 		CONFIG_SYS_64BIT_LBA:
 			When enabled, makes the IDE subsystem use 64bit sector addresses.
 			Default is 32bit.
 - SCSI Support:
 		At the moment only there is only support for the
 		SYM53C8XX SCSI controller; define
 		CONFIG_SCSI_SYM53C8XX to enable it.
 		CONFIG_SYS_SCSI_MAX_LUN [8], CONFIG_SYS_SCSI_MAX_SCSI_ID [7] and
 		CONFIG_SYS_SCSI_MAX_DEVICE [CONFIG_SYS_SCSI_MAX_SCSI_ID *
 		CONFIG_SYS_SCSI_MAX_LUN] can be adjusted to define the
 		maximum numbers of LUNs, SCSI ID's and target
 		devices.
 		CONFIG_SYS_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)
 		The environment variable 'scsidevs' is set to the number of
 		SCSI devices found during the last scan.
 - NETWORK Support (PCI):
 		CONFIG_E1000
 		Support for Intel 8254x/8257x gigabit chips.
 		CONFIG_E1000_SPI
 		Utility code for direct access to the SPI bus on Intel 8257x.
 		This does not do anything useful unless you set at least one
 		of CONFIG_CMD_E1000 or CONFIG_E1000_SPI_GENERIC.
 		CONFIG_E1000_SPI_GENERIC
 		Allow generic access to the SPI bus on the Intel 8257x, for
 		example with the "sspi" command.
 		CONFIG_CMD_E1000
 		Management command for E1000 devices.  When used on devices
 		with SPI support you can reprogram the EEPROM from U-Boot.
 		CONFIG_E1000_FALLBACK_MAC
 		default MAC for empty EEPROM after production.
 		CONFIG_EEPRO100
 		Support for Intel 82557/82559/82559ER chips.
 		Optional CONFIG_EEPRO100_SROM_WRITE enables EEPROM
 		write routine for first time initialisation.
 		CONFIG_TULIP
 		Support for Digital 2114x chips.
 		Optional CONFIG_TULIP_SELECT_MEDIA for board specific
 		modem chip initialisation (KS8761/QS6611).
 		CONFIG_NATSEMI
 		Support for National dp83815 chips.
 		CONFIG_NS8382X
 		Support for National dp8382[01] gigabit chips.
 - NETWORK Support (other):
 		CONFIG_DRIVER_AT91EMAC
 		Support for AT91RM9200 EMAC.
 			CONFIG_RMII
 			Define this to use reduced MII inteface
 			CONFIG_DRIVER_AT91EMAC_QUIET
 			If this defined, the driver is quiet.
 			The driver doen't show link status messages.
 		CONFIG_CALXEDA_XGMAC
 		Support for the Calxeda XGMAC device
 		CONFIG_LAN91C96
 		Support for SMSC's LAN91C96 chips.
 			CONFIG_LAN91C96_BASE
 			Define this to hold the physical address
 			of the LAN91C96's I/O space
 			CONFIG_LAN91C96_USE_32_BIT
 			Define this to enable 32 bit addressing
 		CONFIG_SMC91111
 		Support for SMSC's LAN91C111 chip
 			CONFIG_SMC91111_BASE
 			Define this to hold the physical address
 			of the device (I/O space)
 			CONFIG_SMC_USE_32_BIT
 			Define this if data bus is 32 bits
 			CONFIG_SMC_USE_IOFUNCS
 			Define this to use i/o functions instead of macros
 			(some hardware wont work with macros)
 		CONFIG_DRIVER_TI_EMAC
 		Support for davinci emac
 			CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
 			Define this if you have more then 3 PHYs.
 		CONFIG_FTGMAC100
 		Support for Faraday's FTGMAC100 Gigabit SoC Ethernet
 			CONFIG_FTGMAC100_EGIGA
 			Define this to use GE link update with gigabit PHY.
 			Define this if FTGMAC100 is connected to gigabit PHY.
 			If your system has 10/100 PHY only, it might not occur
 			wrong behavior. Because PHY usually return timeout or
 			useless data when polling gigabit status and gigabit
 			control registers. This behavior won't affect the
 			correctnessof 10/100 link speed update.
 		CONFIG_SMC911X
 		Support for SMSC's LAN911x and LAN921x chips
 			CONFIG_SMC911X_BASE
 			Define this to hold the physical address
 			of the device (I/O space)
 			CONFIG_SMC911X_32_BIT
 			Define this if data bus is 32 bits
 			CONFIG_SMC911X_16_BIT
 			Define this if data bus is 16 bits. If your processor
 			automatically converts one 32 bit word to two 16 bit
 			words you may also try CONFIG_SMC911X_32_BIT.
 		CONFIG_SH_ETHER
 		Support for Renesas on-chip Ethernet controller
 			CONFIG_SH_ETHER_USE_PORT
 			Define the number of ports to be used
 			CONFIG_SH_ETHER_PHY_ADDR
 			Define the ETH PHY's address
 			CONFIG_SH_ETHER_CACHE_WRITEBACK
 			If this option is set, the driver enables cache flush.
 - TPM Support:
 		CONFIG_TPM
 		Support TPM devices.
 		CONFIG_TPM_TIS_I2C
 		Support for i2c bus TPM devices. Only one device
 		per system is supported at this time.
 			CONFIG_TPM_TIS_I2C_BUS_NUMBER
 			Define the the i2c bus number for the TPM device
 			CONFIG_TPM_TIS_I2C_SLAVE_ADDRESS
 			Define the TPM's address on the i2c bus
 			CONFIG_TPM_TIS_I2C_BURST_LIMITATION
 			Define the burst count bytes upper limit
 		CONFIG_TPM_ATMEL_TWI
 		Support for Atmel TWI TPM device. Requires I2C support.
 		CONFIG_TPM_TIS_LPC
 		Support for generic parallel port TPM devices. Only one device
 		per system is supported at this time.
 			CONFIG_TPM_TIS_BASE_ADDRESS
 			Base address where the generic TPM device is mapped
 			to. Contemporary x86 systems usually map it at
 			0xfed40000.
 		CONFIG_CMD_TPM
 		Add tpm monitor functions.
 		Requires CONFIG_TPM. If CONFIG_TPM_AUTH_SESSIONS is set, also
 		provides monitor access to authorized functions.
 		CONFIG_TPM
 		Define this to enable the TPM support library which provides
 		functional interfaces to some TPM commands.
 		Requires support for a TPM device.
 		CONFIG_TPM_AUTH_SESSIONS
 		Define this to enable authorized functions in the TPM library.
 		Requires CONFIG_TPM and CONFIG_SHA1.
 - USB Support:
 		At the moment only the UHCI host controller is
 		supported (PIP405, MIP405, MPC5200); define
 		CONFIG_USB_UHCI to enable it.
 		define CONFIG_USB_KEYBOARD to enable the USB Keyboard
 		and define CONFIG_USB_STORAGE to enable the USB
 		storage devices.
 		Note:
 		Supported are USB Keyboards and USB Floppy drives
 		(TEAC FD-05PUB).
 		MPC5200 USB requires additional defines:
 			CONFIG_USB_CLOCK
 				for 528 MHz Clock: 0x0001bbbb
 			CONFIG_PSC3_USB
 				for USB on PSC3
 			CONFIG_USB_CONFIG
 				for differential drivers: 0x00001000
 				for single ended drivers: 0x00005000
 				for differential drivers on PSC3: 0x00000100
 				for single ended drivers on PSC3: 0x00004100
 			CONFIG_SYS_USB_EVENT_POLL
 				May be defined to allow interrupt polling
 				instead of using asynchronous interrupts
 		CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
 		txfilltuning field in the EHCI controller on reset.
 		CONFIG_USB_HUB_MIN_POWER_ON_DELAY defines the minimum
 		interval for usb hub power-on delay.(minimum 100msec)
 - USB Device:
 		Define the below if you wish to use the USB console.
 		Once firmware is rebuilt from a serial console issue the
 		command "setenv stdin usbtty; setenv stdout usbtty" and
 		attach your USB cable. The Unix command "dmesg" should print
 		it has found a new device. The environment variable usbtty
 		can be set to gserial or cdc_acm to enable your device to
 		appear to a USB host as a Linux gserial device or a
 		Common Device Class Abstract Control Model serial device.
 		If you select usbtty = gserial you should be able to enumerate
 		a Linux host by
 		# modprobe usbserial vendor=0xVendorID product=0xProductID
 		else if using cdc_acm, simply setting the environment
 		variable usbtty to be cdc_acm should suffice. The following
 		might be defined in YourBoardName.h
 			CONFIG_USB_DEVICE
 			Define this to build a UDC device
 			CONFIG_USB_TTY
 			Define this to have a tty type of device available to
 			talk to the UDC device
 			CONFIG_USBD_HS
 			Define this to enable the high speed support for usb
 			device and usbtty. If this feature is enabled, a routine
 			int is_usbd_high_speed(void)
 			also needs to be defined by the driver to dynamically poll
 			whether the enumeration has succeded at high speed or full
 			speed.
 			CONFIG_SYS_CONSOLE_IS_IN_ENV
 			Define this if you want stdin, stdout &/or stderr to
 			be set to usbtty.
 			mpc8xx:
 				CONFIG_SYS_USB_EXTC_CLK 0xBLAH
 				Derive USB clock from external clock "blah"
 				- CONFIG_SYS_USB_EXTC_CLK 0x02
 				CONFIG_SYS_USB_BRG_CLK 0xBLAH
 				Derive USB clock from brgclk
 				- CONFIG_SYS_USB_BRG_CLK 0x04
 		If you have a USB-IF assigned VendorID then you may wish to
 		define your own vendor specific values either in BoardName.h
 		or directly in usbd_vendor_info.h. If you don't define
 		CONFIG_USBD_MANUFACTURER, CONFIG_USBD_PRODUCT_NAME,
 		CONFIG_USBD_VENDORID and CONFIG_USBD_PRODUCTID, then U-Boot
 		should pretend to be a Linux device to it's target host.
 			CONFIG_USBD_MANUFACTURER
 			Define this string as the name of your company for
 			- CONFIG_USBD_MANUFACTURER "my company"
 			CONFIG_USBD_PRODUCT_NAME
 			Define this string as the name of your product
 			- CONFIG_USBD_PRODUCT_NAME "acme usb device"
 			CONFIG_USBD_VENDORID
 			Define this as your assigned Vendor ID from the USB
 			Implementors Forum. This *must* be a genuine Vendor ID
 			to avoid polluting the USB namespace.
 			- CONFIG_USBD_VENDORID 0xFFFF
 			CONFIG_USBD_PRODUCTID
 			Define this as the unique Product ID
 			for your device
 			- CONFIG_USBD_PRODUCTID 0xFFFF
 		Some USB device drivers may need to check USB cable attachment.
 		In this case you can enable following config in BoardName.h:
 			CONFIG_USB_CABLE_CHECK
 			This enables function definition:
 			- usb_cable_connected() in include/usb.h
 			Implementation of this function is board-specific.
 - ULPI Layer Support:
 		The ULPI (UTMI Low Pin (count) Interface) PHYs are supported via
 		the generic ULPI layer. The generic layer accesses the ULPI PHY
 		via the platform viewport, so you need both the genric layer and
 		the viewport enabled. Currently only Chipidea/ARC based
 		viewport is supported.
 		To enable the ULPI layer support, define CONFIG_USB_ULPI and
 		CONFIG_USB_ULPI_VIEWPORT in your board configuration file.
 		If your ULPI phy needs a different reference clock than the
 		standard 24 MHz then you have to define CONFIG_ULPI_REF_CLK to
 		the appropriate value in Hz.
 - MMC Support:
 		The MMC controller on the Intel PXA is supported. To
 		enable this define CONFIG_MMC. The MMC can be
 		accessed from the boot prompt by mapping the device
 		to physical memory similar to flash. Command line is
 		enabled with CONFIG_CMD_MMC. The MMC driver also works with
 		the FAT fs. This is enabled with CONFIG_CMD_FAT.
 		CONFIG_SH_MMCIF
 		Support for Renesas on-chip MMCIF controller
 			CONFIG_SH_MMCIF_ADDR
 			Define the base address of MMCIF registers
 			CONFIG_SH_MMCIF_CLK
 			Define the clock frequency for MMCIF
 - USB Device Firmware Update (DFU) class support:
 		CONFIG_DFU_FUNCTION
 		This enables the USB portion of the DFU USB class
 		CONFIG_CMD_DFU
 		This enables the command "dfu" which is used to have
 		U-Boot create a DFU class device via USB.  This command
 		requires that the "dfu_alt_info" environment variable be
 		set and define the alt settings to expose to the host.
 		CONFIG_DFU_MMC
 		This enables support for exposing (e)MMC devices via DFU.
 		CONFIG_DFU_NAND
 		This enables support for exposing NAND devices via DFU.
 		CONFIG_DFU_RAM
 		This enables support for exposing RAM via DFU.
 		Note: DFU spec refer to non-volatile memory usage, but
 		allow usages beyond the scope of spec - here RAM usage,
 		one that would help mostly the developer.
 		CONFIG_SYS_DFU_DATA_BUF_SIZE
 		Dfu transfer uses a buffer before writing data to the
 		raw storage device. Make the size (in bytes) of this buffer
 		configurable. The size of this buffer is also configurable
 		through the "dfu_bufsiz" environment variable.
 		CONFIG_SYS_DFU_MAX_FILE_SIZE
 		When updating files rather than the raw storage device,
 		we use a static buffer to copy the file into and then write
 		the buffer once we've been given the whole file.  Define
 		this to the maximum filesize (in bytes) for the buffer.
 		Default is 4 MiB if undefined.
 - Journaling Flash filesystem support:
 		CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
 		CONFIG_JFFS2_NAND_DEV
 		Define these for a default partition on a NAND device
 		CONFIG_SYS_JFFS2_FIRST_SECTOR,
 		CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
 		Define these for a default partition on a NOR device
 		CONFIG_SYS_JFFS_CUSTOM_PART
 		Define this to create an own partition. You have to provide a
 		function struct part_info* jffs2_part_info(int part_num)
 		If you define only one JFFS2 partition you may also want to
 		#define CONFIG_SYS_JFFS_SINGLE_PART	1
 		to disable the command chpart. This is the default when you
 		have not defined a custom partition
 - FAT(File Allocation Table) filesystem write function support:
 		CONFIG_FAT_WRITE
 		Define this to enable support for saving memory data as a
 		file in FAT formatted partition.
 		This will also enable the command "fatwrite" enabling the
 		user to write files to FAT.
 CBFS (Coreboot Filesystem) support
 		CONFIG_CMD_CBFS
 		Define this to enable support for reading from a Coreboot
 		filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls
 		and cbfsload.
 - Keyboard Support:
 		CONFIG_ISA_KEYBOARD
 		Define this to enable standard (PC-Style) keyboard
 		support
 		CONFIG_I8042_KBD
 		Standard PC keyboard driver with US (is default) and
 		GERMAN key layout (switch via environment 'keymap=de') support.
 		Export function i8042_kbd_init, i8042_tstc and i8042_getc
 		for cfb_console. Supports cursor blinking.
 		CONFIG_CROS_EC_KEYB
 		Enables a Chrome OS keyboard using the CROS_EC interface.
 		This uses CROS_EC to communicate with a second microcontroller
 		which provides key scans on request.
 - Video support:
 		CONFIG_VIDEO
 		Define this to enable video support (for output to
 		video).
 		CONFIG_VIDEO_CT69000
 		Enable Chips & Technologies 69000 Video chip
 		CONFIG_VIDEO_SMI_LYNXEM
 		Enable Silicon Motion SMI 712/710/810 Video chip. The
 		video output is selected via environment 'videoout'
 		(1 = LCD and 2 = CRT). If videoout is undefined, CRT is
 		assumed.
 		For the CT69000 and SMI_LYNXEM drivers, videomode is
 		selected via environment 'videomode'. Two different ways
 		are possible:
 		- "videomode=num"   'num' is a standard LiLo mode numbers.
 		Following standard modes are supported	(* is default):
 		      Colors	640x480 800x600 1024x768 1152x864 1280x1024
 		-------------+---------------------------------------------
 		      8 bits |	0x301*	0x303	 0x305	  0x161	    0x307
 		     15 bits |	0x310	0x313	 0x316	  0x162	    0x319
 		     16 bits |	0x311	0x314	 0x317	  0x163	    0x31A
 		     24 bits |	0x312	0x315	 0x318	    ?	    0x31B
 		-------------+---------------------------------------------
 		(i.e. setenv videomode 317; saveenv; reset;)
 		- "videomode=bootargs" all the video parameters are parsed
 		from the bootargs. (See drivers/video/videomodes.c)
 		CONFIG_VIDEO_SED13806
 		Enable Epson SED13806 driver. This driver supports 8bpp
 		and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP
 		or CONFIG_VIDEO_SED13806_16BPP
 		CONFIG_FSL_DIU_FB
 		Enable the Freescale DIU video driver.	Reference boards for
 		SOCs that have a DIU should define this macro to enable DIU
 		support, and should also define these other macros:
 			CONFIG_SYS_DIU_ADDR
 			CONFIG_VIDEO
 			CONFIG_CMD_BMP
 			CONFIG_CFB_CONSOLE
 			CONFIG_VIDEO_SW_CURSOR
 			CONFIG_VGA_AS_SINGLE_DEVICE
 			CONFIG_VIDEO_LOGO
 			CONFIG_VIDEO_BMP_LOGO
 		The DIU driver will look for the 'video-mode' environment
 		variable, and if defined, enable the DIU as a console during
 		boot.  See the documentation file README.video for a
 		description of this variable.
 		CONFIG_VIDEO_VGA
 		Enable the VGA video / BIOS for x86. The alternative if you
 		are using coreboot is to use the coreboot frame buffer
 		driver.
 - Keyboard Support:
 		CONFIG_KEYBOARD
 		Define this to enable a custom keyboard support.
 		This simply calls drv_keyboard_init() which must be
 		defined in your board-specific files.
 		The only board using this so far is RBC823.
 - LCD Support:	CONFIG_LCD
 		Define this to enable LCD support (for output to LCD
 		display); also select one of the supported displays
 		by defining one of these:
 		CONFIG_ATMEL_LCD:
 			HITACHI TX09D70VM1CCA, 3.5", 240x320.
 		CONFIG_NEC_NL6448AC33:
 			NEC NL6448AC33-18. Active, color, single scan.
 		CONFIG_NEC_NL6448BC20
 			NEC NL6448BC20-08. 6.5", 640x480.
 			Active, color, single scan.
 		CONFIG_NEC_NL6448BC33_54
 			NEC NL6448BC33-54. 10.4", 640x480.
 			Active, color, single scan.
 		CONFIG_SHARP_16x9
 			Sharp 320x240. Active, color, single scan.
 			It isn't 16x9, and I am not sure what it is.
 		CONFIG_SHARP_LQ64D341
 			Sharp LQ64D341 display, 640x480.
 			Active, color, single scan.
 		CONFIG_HLD1045
 			HLD1045 display, 640x480.
 			Active, color, single scan.
 		CONFIG_OPTREX_BW
 			Optrex	 CBL50840-2 NF-FW 99 22 M5
 			or
 			Hitachi	 LMG6912RPFC-00T
 			or
 			Hitachi	 SP14Q002
 			320x240. Black & white.
 		Normally display is black on white background; define
 		CONFIG_SYS_WHITE_ON_BLACK to get it inverted.
 		CONFIG_LCD_ALIGNMENT
 		Normally the LCD is page-aligned (tyically 4KB). If this is
 		defined then the LCD will be aligned to this value instead.
 		For ARM it is sometimes useful to use MMU_SECTION_SIZE
 		here, since it is cheaper to change data cache settings on
 		a per-section basis.
 		CONFIG_CONSOLE_SCROLL_LINES
 		When the console need to be scrolled, this is the number of
 		lines to scroll by. It defaults to 1. Increasing this makes
 		the console jump but can help speed up operation when scrolling
 		is slow.
 		CONFIG_LCD_BMP_RLE8
 		Support drawing of RLE8-compressed bitmaps on the LCD.
 		CONFIG_I2C_EDID
 		Enables an 'i2c edid' command which can read EDID
 		information over I2C from an attached LCD display.
 - Splash Screen Support: CONFIG_SPLASH_SCREEN
 		If this option is set, the environment is checked for
 		a variable "splashimage". If found, the usual display
 		of logo, copyright and system information on the LCD
 		is suppressed and the BMP image at the address
 		specified in "splashimage" is loaded instead. The
 		console is redirected to the "nulldev", too. This
 		allows for a "silent" boot where a splash screen is
 		loaded very quickly after power-on.
 		CONFIG_SPLASHIMAGE_GUARD
 		If this option is set, then U-Boot will prevent the environment
 		variable "splashimage" from being set to a problematic address
 		(see README.displaying-bmps and README.arm-unaligned-accesses).
 		This option is useful for targets where, due to alignment
 		restrictions, an improperly aligned BMP image will cause a data
 		abort. If you think you will not have problems with unaligned
 		accesses (for example because your toolchain prevents them)
 		there is no need to set this option.
 		CONFIG_SPLASH_SCREEN_ALIGN
 		If this option is set the splash image can be freely positioned
 		on the screen. Environment variable "splashpos" specifies the
 		position as "x,y". If a positive number is given it is used as
 		number of pixel from left/top. If a negative number is given it
 		is used as number of pixel from right/bottom. You can also
 		specify 'm' for centering the image.
 		Example:
 		setenv splashpos m,m
 			=> image at center of screen
 		setenv splashpos 30,20
 			=> image at x = 30 and y = 20
 		setenv splashpos -10,m
 			=> vertically centered image
 			   at x = dspWidth - bmpWidth - 9
 - Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP
 		If this option is set, additionally to standard BMP
 		images, gzipped BMP images can be displayed via the
 		splashscreen support or the bmp command.
 - Run length encoded BMP image (RLE8) support: CONFIG_VIDEO_BMP_RLE8
 		If this option is set, 8-bit RLE compressed BMP images
 		can be displayed via the splashscreen support or the
 		bmp command.
 - Do compresssing for memory range:
 		CONFIG_CMD_ZIP
 		If this option is set, it would use zlib deflate method
 		to compress the specified memory at its best effort.
 - Compression support:
 		CONFIG_GZIP
 		Enabled by default to support gzip compressed images.
 		CONFIG_BZIP2
 		If this option is set, support for bzip2 compressed
 		images is included. If not, only uncompressed and gzip
 		compressed images are supported.
 		NOTE: the bzip2 algorithm requires a lot of RAM, so
 		the malloc area (as defined by CONFIG_SYS_MALLOC_LEN) should
 		be at least 4MB.
 		CONFIG_LZMA
 		If this option is set, support for lzma compressed
 		images is included.
 		Note: The LZMA algorithm adds between 2 and 4KB of code and it
 		requires an amount of dynamic memory that is given by the
 		formula:
 			(1846 + 768 << (lc + lp)) * sizeof(uint16)
 		Where lc and lp stand for, respectively, Literal context bits
 		and Literal pos bits.
 		This value is upper-bounded by 14MB in the worst case. Anyway,
 		for a ~4MB large kernel image, we have lc=3 and lp=0 for a
 		total amount of (1846 + 768 << (3 + 0)) * 2 = ~41KB... that is
 		a very small buffer.
 		Use the lzmainfo tool to determinate the lc and lp values and
 		then calculate the amount of needed dynamic memory (ensuring
 		the appropriate CONFIG_SYS_MALLOC_LEN value).
 		CONFIG_LZO
 		If this option is set, support for LZO compressed images
 		is included.
 - MII/PHY support:
 		CONFIG_PHY_ADDR
 		The address of PHY on MII bus.
 		CONFIG_PHY_CLOCK_FREQ (ppc4xx)
 		The clock frequency of the MII bus
 		CONFIG_PHY_GIGE
 		If this option is set, support for speed/duplex
 		detection of gigabit PHY is included.
 		CONFIG_PHY_RESET_DELAY
 		Some PHY like Intel LXT971A need extra delay after
 		reset before any MII register access is possible.
 		For such PHY, set this option to the usec delay
 		required. (minimum 300usec for LXT971A)
 		CONFIG_PHY_CMD_DELAY (ppc4xx)
 		Some PHY like Intel LXT971A need extra delay after
 		command issued before MII status register can be read
 - Ethernet address:
 		CONFIG_ETHADDR
 		CONFIG_ETH1ADDR
 		CONFIG_ETH2ADDR
 		CONFIG_ETH3ADDR
 		CONFIG_ETH4ADDR
 		CONFIG_ETH5ADDR
 		Define a default value for Ethernet address to use
 		for the respective Ethernet interface, in case this
 		is not determined automatically.
 - IP address:
 		CONFIG_IPADDR
 		Define a default value for the IP address to use for
 		the default Ethernet interface, in case this is not
 		determined through e.g. bootp.
 		(Environment variable "ipaddr")
 - Server IP address:
 		CONFIG_SERVERIP
 		Defines a default value for the IP address of a TFTP
 		server to contact when using the "tftboot" command.
 		(Environment variable "serverip")
 		CONFIG_KEEP_SERVERADDR
 		Keeps the server's MAC address, in the env 'serveraddr'
 		for passing to bootargs (like Linux's netconsole option)
 - Gateway IP address:
 		CONFIG_GATEWAYIP
 		Defines a default value for the IP address of the
 		default router where packets to other networks are
 		sent to.
 		(Environment variable "gatewayip")
 - Subnet mask:
 		CONFIG_NETMASK
 		Defines a default value for the subnet mask (or
 		routing prefix) which is used to determine if an IP
 		address belongs to the local subnet or needs to be
 		forwarded through a router.
 		(Environment variable "netmask")
 - Multicast TFTP Mode:
 		CONFIG_MCAST_TFTP
 		Defines whether you want to support multicast TFTP as per
 		rfc-2090; for example to work with atftp.  Lets lots of targets
 		tftp down the same boot image concurrently.  Note: the Ethernet
 		driver in use must provide a function: mcast() to join/leave a
 		multicast group.
 - BOOTP Recovery Mode:
 		CONFIG_BOOTP_RANDOM_DELAY
 		If you have many targets in a network that try to
 		boot using BOOTP, you may want to avoid that all
 		systems send out BOOTP requests at precisely the same
 		moment (which would happen for instance at recovery
 		from a power failure, when all systems will try to
 		boot, thus flooding the BOOTP server. Defining
 		CONFIG_BOOTP_RANDOM_DELAY causes a random delay to be
 		inserted before sending out BOOTP requests. The
 		following delays are inserted then:
 		1st BOOTP request:	delay 0 ... 1 sec
 		2nd BOOTP request:	delay 0 ... 2 sec
 		3rd BOOTP request:	delay 0 ... 4 sec
 		4th and following
 		BOOTP requests:		delay 0 ... 8 sec
 - DHCP Advanced Options:
 		You can fine tune the DHCP functionality by defining
 		CONFIG_BOOTP_* symbols:
 		CONFIG_BOOTP_SUBNETMASK
 		CONFIG_BOOTP_GATEWAY
 		CONFIG_BOOTP_HOSTNAME
 		CONFIG_BOOTP_NISDOMAIN
 		CONFIG_BOOTP_BOOTPATH
 		CONFIG_BOOTP_BOOTFILESIZE
 		CONFIG_BOOTP_DNS
 		CONFIG_BOOTP_DNS2
 		CONFIG_BOOTP_SEND_HOSTNAME
 		CONFIG_BOOTP_NTPSERVER
 		CONFIG_BOOTP_TIMEOFFSET
 		CONFIG_BOOTP_VENDOREX
 		CONFIG_BOOTP_MAY_FAIL
 		CONFIG_BOOTP_SERVERIP - TFTP server will be the serverip
 		environment variable, not the BOOTP server.
 		CONFIG_BOOTP_MAY_FAIL - If the DHCP server is not found
 		after the configured retry count, the call will fail
 		instead of starting over.  This can be used to fail over
 		to Link-local IP address configuration if the DHCP server
 		is not available.
 		CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS
 		serverip from a DHCP server, it is possible that more
 		than one DNS serverip is offered to the client.
 		If CONFIG_BOOTP_DNS2 is enabled, the secondary DNS
 		serverip will be stored in the additional environment
 		variable "dnsip2". The first DNS serverip is always
 		stored in the variable "dnsip", when CONFIG_BOOTP_DNS
 		is defined.
 		CONFIG_BOOTP_SEND_HOSTNAME - Some DHCP servers are capable
 		to do a dynamic update of a DNS server. To do this, they
 		need the hostname of the DHCP requester.
 		If CONFIG_BOOTP_SEND_HOSTNAME is defined, the content
 		of the "hostname" environment variable is passed as
 		option 12 to the DHCP server.
 		CONFIG_BOOTP_DHCP_REQUEST_DELAY
 		A 32bit value in microseconds for a delay between
 		receiving a "DHCP Offer" and sending the "DHCP Request".
 		This fixes a problem with certain DHCP servers that don't
 		respond 100% of the time to a "DHCP request". E.g. On an
 		AT91RM9200 processor running at 180MHz, this delay needed
 		to be *at least* 15,000 usec before a Windows Server 2003
 		DHCP server would reply 100% of the time. I recommend at
 		least 50,000 usec to be safe. The alternative is to hope
 		that one of the retries will be successful but note that
 		the DHCP timeout and retry process takes a longer than
 		this delay.
  - Link-local IP address negotiation:
 		Negotiate with other link-local clients on the local network
 		for an address that doesn't require explicit configuration.
 		This is especially useful if a DHCP server cannot be guaranteed
 		to exist in all environments that the device must operate.
 		See doc/README.link-local for more information.
  - CDP Options:
 		CONFIG_CDP_DEVICE_ID
 		The device id used in CDP trigger frames.
 		CONFIG_CDP_DEVICE_ID_PREFIX
 		A two character string which is prefixed to the MAC address
 		of the device.
 		CONFIG_CDP_PORT_ID
 		A printf format string which contains the ascii name of
 		the port. Normally is set to "eth%d" which sets
 		eth0 for the first Ethernet, eth1 for the second etc.
 		CONFIG_CDP_CAPABILITIES
 		A 32bit integer which indicates the device capabilities;
 		0x00000010 for a normal host which does not forwards.
 		CONFIG_CDP_VERSION
 		An ascii string containing the version of the software.
 		CONFIG_CDP_PLATFORM
 		An ascii string containing the name of the platform.
 		CONFIG_CDP_TRIGGER
 		A 32bit integer sent on the trigger.
 		CONFIG_CDP_POWER_CONSUMPTION
 		A 16bit integer containing the power consumption of the
 		device in .1 of milliwatts.
 		CONFIG_CDP_APPLIANCE_VLAN_TYPE
 		A byte containing the id of the VLAN.
 - Status LED:	CONFIG_STATUS_LED
 		Several configurations allow to display the current
 		status using a LED. For instance, the LED will blink
 		fast while running U-Boot code, stop blinking as
 		soon as a reply to a BOOTP request was received, and
 		start blinking slow once the Linux kernel is running
 		(supported by a status LED driver in the Linux
 		kernel). Defining CONFIG_STATUS_LED enables this
 		feature in U-Boot.
 		Additional options:
 		CONFIG_GPIO_LED
 		The status LED can be connected to a GPIO pin.
 		In such cases, the gpio_led driver can be used as a
 		status LED backend implementation. Define CONFIG_GPIO_LED
 		to include the gpio_led driver in the U-Boot binary.
 		CONFIG_GPIO_LED_INVERTED_TABLE
 		Some GPIO connected LEDs may have inverted polarity in which
 		case the GPIO high value corresponds to LED off state and
 		GPIO low value corresponds to LED on state.
 		In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
 		with a list of GPIO LEDs that have inverted polarity.
 - CAN Support:	CONFIG_CAN_DRIVER
 		Defining CONFIG_CAN_DRIVER enables CAN driver support
 		on those systems that support this (optional)
 		feature, like the TQM8xxL modules.
 - I2C Support:	CONFIG_SYS_I2C
 		This enable the NEW i2c subsystem, and will allow you to use
 		i2c commands at the u-boot command line (as long as you set
 		CONFIG_CMD_I2C in CONFIG_COMMANDS) and communicate with i2c
 		based realtime clock chips or other i2c devices. See
 		common/cmd_i2c.c for a description of the command line
 		interface.
 		ported i2c driver to the new framework:
 		- drivers/i2c/soft_i2c.c:
 		  - activate first bus with CONFIG_SYS_I2C_SOFT define
 		    CONFIG_SYS_I2C_SOFT_SPEED and CONFIG_SYS_I2C_SOFT_SLAVE
 		    for defining speed and slave address
 		  - activate second bus with I2C_SOFT_DECLARATIONS2 define
 		    CONFIG_SYS_I2C_SOFT_SPEED_2 and CONFIG_SYS_I2C_SOFT_SLAVE_2
 		    for defining speed and slave address
 		  - activate third bus with I2C_SOFT_DECLARATIONS3 define
 		    CONFIG_SYS_I2C_SOFT_SPEED_3 and CONFIG_SYS_I2C_SOFT_SLAVE_3
 		    for defining speed and slave address
 		  - activate fourth bus with I2C_SOFT_DECLARATIONS4 define
 		    CONFIG_SYS_I2C_SOFT_SPEED_4 and CONFIG_SYS_I2C_SOFT_SLAVE_4
 		    for defining speed and slave address
 		- drivers/i2c/fsl_i2c.c:
 		  - activate i2c driver with CONFIG_SYS_I2C_FSL
 		    define CONFIG_SYS_FSL_I2C_OFFSET for setting the register
 		    offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and
 		    CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first
 		    bus.
 		  - If your board supports a second fsl i2c bus, define
 		    CONFIG_SYS_FSL_I2C2_OFFSET for the register offset
 		    CONFIG_SYS_FSL_I2C2_SPEED for the speed and
 		    CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the
 		    second bus.
 		- drivers/i2c/tegra_i2c.c:
 		  - activate this driver with CONFIG_SYS_I2C_TEGRA
 		  - This driver adds 4 i2c buses with a fix speed from
 		    100000 and the slave addr 0!
 		- drivers/i2c/ppc4xx_i2c.c
 		  - activate this driver with CONFIG_SYS_I2C_PPC4XX
 		  - CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0
 		  - CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1
 		- drivers/i2c/i2c_mxc.c
 		  - activate this driver with CONFIG_SYS_I2C_MXC
 		  - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
 		  - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
 		  - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
 		  - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
 		  - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
 		  - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
 		If thoses defines are not set, default value is 100000
 		for speed, and 0 for slave.
 		- drivers/i2c/rcar_i2c.c:
 		  - activate this driver with CONFIG_SYS_I2C_RCAR
 		  - This driver adds 4 i2c buses
 		  - CONFIG_SYS_RCAR_I2C0_BASE for setting the register channel 0
 		  - CONFIG_SYS_RCAR_I2C0_SPEED for for the speed channel 0
 		  - CONFIG_SYS_RCAR_I2C1_BASE for setting the register channel 1
 		  - CONFIG_SYS_RCAR_I2C1_SPEED for for the speed channel 1
 		  - CONFIG_SYS_RCAR_I2C2_BASE for setting the register channel 2
 		  - CONFIG_SYS_RCAR_I2C2_SPEED for for the speed channel 2
 		  - CONFIG_SYS_RCAR_I2C3_BASE for setting the register channel 3
 		  - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
 		  - CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
 		- drivers/i2c/sh_i2c.c:
 		  - activate this driver with CONFIG_SYS_I2C_SH
 		  - This driver adds from 2 to 5 i2c buses
 		  - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0
 		  - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0
 		  - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1
 		  - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1
 		  - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2
 		  - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2
 		  - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3
 		  - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
 		  - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
 		  - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
 		  - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5
 		  - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
 		  - CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses
 		- drivers/i2c/omap24xx_i2c.c
 		  - activate this driver with CONFIG_SYS_I2C_OMAP24XX
 		  - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0
 		  - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0
 		  - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1
 		  - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1
 		  - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2
 		  - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2
 		  - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3
 		  - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3
 		  - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
 		  - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4
 		- drivers/i2c/zynq_i2c.c
 		  - activate this driver with CONFIG_SYS_I2C_ZYNQ
 		  - set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting
 		  - set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr
 		- drivers/i2c/s3c24x0_i2c.c:
 		  - activate this driver with CONFIG_SYS_I2C_S3C24X0
 		  - This driver adds i2c buses (11 for Exynos5250, Exynos5420
 		    9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
 		    with a fix speed from 100000 and the slave addr 0!
 		additional defines:
 		CONFIG_SYS_NUM_I2C_BUSES
 		Hold the number of i2c busses you want to use. If you
 		don't use/have i2c muxes on your i2c bus, this
 		is equal to CONFIG_SYS_NUM_I2C_ADAPTERS, and you can
 		omit this define.
 		CONFIG_SYS_I2C_DIRECT_BUS
 		define this, if you don't use i2c muxes on your hardware.
 		if CONFIG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
 		omit this define.
 		CONFIG_SYS_I2C_MAX_HOPS
 		define how many muxes are maximal consecutively connected
 		on one i2c bus. If you not use i2c muxes, omit this
 		define.
 		CONFIG_SYS_I2C_BUSES
 		hold a list of busses you want to use, only used if
 		CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example
 		a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and
 		CONFIG_SYS_NUM_I2C_BUSES = 9:
 		 CONFIG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 4}}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 5}}}, \
 					{1, {I2C_NULL_HOP}}, \
 					{1, {{I2C_MUX_PCA9544, 0x72, 1}}}, \
 					{1, {{I2C_MUX_PCA9544, 0x72, 2}}}, \
 					}
 		which defines
 			bus 0 on adapter 0 without a mux
 			bus 1 on adapter 0 with a PCA9547 on address 0x70 port 1
 			bus 2 on adapter 0 with a PCA9547 on address 0x70 port 2
 			bus 3 on adapter 0 with a PCA9547 on address 0x70 port 3
 			bus 4 on adapter 0 with a PCA9547 on address 0x70 port 4
 			bus 5 on adapter 0 with a PCA9547 on address 0x70 port 5
 			bus 6 on adapter 1 without a mux
 			bus 7 on adapter 1 with a PCA9544 on address 0x72 port 1
 			bus 8 on adapter 1 with a PCA9544 on address 0x72 port 2
 		If you do not have i2c muxes on your board, omit this define.
 - Legacy I2C Support:	CONFIG_HARD_I2C
 		NOTE: It is intended to move drivers to CONFIG_SYS_I2C which
 		provides the following compelling advantages:
 		- more than one i2c adapter is usable
 		- approved multibus support
 		- better i2c mux support
 		** Please consider updating your I2C driver now. **
 		These enable legacy I2C serial bus commands. Defining
 		CONFIG_HARD_I2C will include the appropriate I2C driver
 		for the selected CPU.
 		This will allow you to use i2c commands at the u-boot
 		command line (as long as you set CONFIG_CMD_I2C in
 		CONFIG_COMMANDS) and communicate with i2c based realtime
 		clock chips. See common/cmd_i2c.c for a description of the
 		command line interface.
 		CONFIG_HARD_I2C selects a hardware I2C controller.
 		There are several other quantities that must also be
 		defined when you define CONFIG_HARD_I2C.
 		In both cases you will need to define CONFIG_SYS_I2C_SPEED
 		to be the frequency (in Hz) at which you wish your i2c bus
 		to run and CONFIG_SYS_I2C_SLAVE to be the address of this node (ie
 		the CPU's i2c node address).
 		Now, the u-boot i2c code for the mpc8xx
 		(arch/powerpc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node
 		and so its address should therefore be cleared to 0 (See,
 		eg, MPC823e User's Manual p.16-473). So, set
 		CONFIG_SYS_I2C_SLAVE to 0.
 		CONFIG_SYS_I2C_INIT_MPC5XXX
 		When a board is reset during an i2c bus transfer
 		chips might think that the current transfer is still
 		in progress.  Reset the slave devices by sending start
 		commands until the slave device responds.
 		That's all that's required for CONFIG_HARD_I2C.
 		If you use the software i2c interface (CONFIG_SYS_I2C_SOFT)
 		then the following macros need to be defined (examples are
 		from include/configs/lwmon.h):
 		I2C_INIT
 		(Optional). Any commands necessary to enable the I2C
 		controller or configure ports.
 		eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=	PB_SCL)
 		I2C_PORT
 		(Only for MPC8260 CPU). The I/O port to use (the code
 		assumes both bits are on the same port). Valid values
 		are 0..3 for ports A..D.
 		I2C_ACTIVE
 		The code necessary to make the I2C data line active
 		(driven).  If the data line is open collector, this
 		define can be null.
 		eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |=  PB_SDA)
 		I2C_TRISTATE
 		The code necessary to make the I2C data line tri-stated
 		(inactive).  If the data line is open collector, this
 		define can be null.
 		eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 		I2C_READ
 		Code that returns true if the I2C data line is high,
 		false if it is low.
 		eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 		I2C_SDA(bit)
 		If <bit> is true, sets the I2C data line high. If it
 		is false, it clears it (low).
 		eg: #define I2C_SDA(bit) \
 			if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
 		I2C_SCL(bit)
 		If <bit> is true, sets the I2C clock line high. If it
 		is false, it clears it (low).
 		eg: #define I2C_SCL(bit) \
 			if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
 		I2C_DELAY
 		This delay is invoked four times per clock cycle so this
 		controls the rate of data transfer.  The data rate thus
 		is 1 / (I2C_DELAY * 4). Often defined to be something
 		like:
 		#define I2C_DELAY  udelay(2)
 		CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA
 		If your arch supports the generic GPIO framework (asm/gpio.h),
 		then you may alternatively define the two GPIOs that are to be
 		used as SCL / SDA.  Any of the previous I2C_xxx macros will
 		have GPIO-based defaults assigned to them as appropriate.
 		You should define these to the GPIO value as given directly to
 		the generic GPIO functions.
 		CONFIG_SYS_I2C_INIT_BOARD
 		When a board is reset during an i2c bus transfer
 		chips might think that the current transfer is still
 		in progress. On some boards it is possible to access
 		the i2c SCLK line directly, either by using the
 		processor pin as a GPIO or by having a second pin
 		connected to the bus. If this option is defined a
 		custom i2c_init_board() routine in boards/xxx/board.c
 		is run early in the boot sequence.
 		CONFIG_SYS_I2C_BOARD_LATE_INIT
 		An alternative to CONFIG_SYS_I2C_INIT_BOARD. If this option is
 		defined a custom i2c_board_late_init() routine in
 		boards/xxx/board.c is run AFTER the operations in i2c_init()
 		is completed. This callpoint can be used to unreset i2c bus
 		using CPU i2c controller register accesses for CPUs whose i2c
 		controller provide such a method. It is called at the end of
 		i2c_init() to allow i2c_init operations to setup the i2c bus
 		controller on the CPU (e.g. setting bus speed & slave address).
 		CONFIG_I2CFAST (PPC405GP|PPC405EP only)
 		This option enables configuration of bi_iic_fast[] flags
 		in u-boot bd_info structure based on u-boot environment
 		variable "i2cfast". (see also i2cfast)
 		CONFIG_I2C_MULTI_BUS
 		This option allows the use of multiple I2C buses, each of which
 		must have a controller.	 At any point in time, only one bus is
 		active.	 To switch to a different bus, use the 'i2c dev' command.
 		Note that bus numbering is zero-based.
 		CONFIG_SYS_I2C_NOPROBES
 		This option specifies a list of I2C devices that will be skipped
 		when the 'i2c probe' command is issued.	 If CONFIG_I2C_MULTI_BUS
 		is set, specify a list of bus-device pairs.  Otherwise, specify
 		a 1D array of device addresses
 		e.g.
 			#undef	CONFIG_I2C_MULTI_BUS
 			#define CONFIG_SYS_I2C_NOPROBES {0x50,0x68}
 		will skip addresses 0x50 and 0x68 on a board with one I2C bus
 			#define CONFIG_I2C_MULTI_BUS
 			#define CONFIG_SYS_I2C_MULTI_NOPROBES	{{0,0x50},{0,0x68},{1,0x54}}
 		will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
 		CONFIG_SYS_SPD_BUS_NUM
 		If defined, then this indicates the I2C bus number for DDR SPD.
 		If not defined, then U-Boot assumes that SPD is on I2C bus 0.
 		CONFIG_SYS_RTC_BUS_NUM
 		If defined, then this indicates the I2C bus number for the RTC.
 		If not defined, then U-Boot assumes that RTC is on I2C bus 0.
 		CONFIG_SYS_DTT_BUS_NUM
 		If defined, then this indicates the I2C bus number for the DTT.
 		If not defined, then U-Boot assumes that DTT is on I2C bus 0.
 		CONFIG_SYS_I2C_DTT_ADDR:
 		If defined, specifies the I2C address of the DTT device.
 		If not defined, then U-Boot uses predefined value for
 		specified DTT device.
 		CONFIG_SOFT_I2C_READ_REPEATED_START
 		defining this will force the i2c_read() function in
 		the soft_i2c driver to perform an I2C repeated start
 		between writing the address pointer and reading the
 		data.  If this define is omitted the default behaviour
 		of doing a stop-start sequence will be used.  Most I2C
 		devices can use either method, but some require one or
 		the other.
 - SPI Support:	CONFIG_SPI
 		Enables SPI driver (so far only tested with
 		SPI EEPROM, also an instance works with Crystal A/D and
 		D/As on the SACSng board)
 		CONFIG_SH_SPI
 		Enables the driver for SPI controller on SuperH. Currently
 		only SH7757 is supported.
 		CONFIG_SPI_X
 		Enables extended (16-bit) SPI EEPROM addressing.
 		(symmetrical to CONFIG_I2C_X)
 		CONFIG_SOFT_SPI
 		Enables a software (bit-bang) SPI driver rather than
 		using hardware support. This is a general purpose
 		driver that only requires three general I/O port pins
 		(two outputs, one input) to function. If this is
 		defined, the board configuration must define several
 		SPI configuration items (port pins to use, etc). For
 		an example, see include/configs/sacsng.h.
 		CONFIG_HARD_SPI
 		Enables a hardware SPI driver for general-purpose reads
 		and writes.  As with CONFIG_SOFT_SPI, the board configuration
 		must define a list of chip-select function pointers.
 		Currently supported on some MPC8xxx processors.	 For an
 		example, see include/configs/mpc8349emds.h.
 		CONFIG_MXC_SPI
 		Enables the driver for the SPI controllers on i.MX and MXC
 		SoCs. Currently i.MX31/35/51 are supported.
 - FPGA Support: CONFIG_FPGA
 		Enables FPGA subsystem.
 		CONFIG_FPGA_<vendor>
 		Enables support for specific chip vendors.
 		(ALTERA, XILINX)
 		CONFIG_FPGA_<family>
 		Enables support for FPGA family.
 		(SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
 		CONFIG_FPGA_COUNT
 		Specify the number of FPGA devices to support.
 		CONFIG_SYS_FPGA_PROG_FEEDBACK
 		Enable printing of hash marks during FPGA configuration.
 		CONFIG_SYS_FPGA_CHECK_BUSY
 		Enable checks on FPGA configuration interface busy
 		status by the configuration function. This option
 		will require a board or device specific function to
 		be written.
 		CONFIG_FPGA_DELAY
 		If defined, a function that provides delays in the FPGA
 		configuration driver.
 		CONFIG_SYS_FPGA_CHECK_CTRLC
 		Allow Control-C to interrupt FPGA configuration
 		CONFIG_SYS_FPGA_CHECK_ERROR
 		Check for configuration errors during FPGA bitfile
 		loading. For example, abort during Virtex II
 		configuration if the INIT_B line goes low (which
 		indicated a CRC error).
 		CONFIG_SYS_FPGA_WAIT_INIT
 		Maximum time to wait for the INIT_B line to deassert
 		after PROB_B has been deasserted during a Virtex II
 		FPGA configuration sequence. The default time is 500
 		ms.
 		CONFIG_SYS_FPGA_WAIT_BUSY
 		Maximum time to wait for BUSY to deassert during
 		Virtex II FPGA configuration. The default is 5 ms.
 		CONFIG_SYS_FPGA_WAIT_CONFIG
 		Time to wait after FPGA configuration. The default is
 		200 ms.
 - Configuration Management:
 		CONFIG_IDENT_STRING
 		If defined, this string will be added to the U-Boot
 		version information (U_BOOT_VERSION)
 - Vendor Parameter Protection:
 		U-Boot considers the values of the environment
 		variables "serial#" (Board Serial Number) and
 		"ethaddr" (Ethernet Address) to be parameters that
 		are set once by the board vendor / manufacturer, and
 		protects these variables from casual modification by
 		the user. Once set, these variables are read-only,
 		and write or delete attempts are rejected. You can
 		change this behaviour:
 		If CONFIG_ENV_OVERWRITE is #defined in your config
 		file, the write protection for vendor parameters is
 		completely disabled. Anybody can change or delete
 		these parameters.
 		Alternatively, if you #define _both_ CONFIG_ETHADDR
 		_and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default
 		Ethernet address is installed in the environment,
 		which can be changed exactly ONCE by the user. [The
 		serial# is unaffected by this, i. e. it remains
 		read-only.]
 		The same can be accomplished in a more flexible way
 		for any variable by configuring the type of access
 		to allow for those variables in the ".flags" variable
 		or define CONFIG_ENV_FLAGS_LIST_STATIC.
 - Protected RAM:
 		CONFIG_PRAM
 		Define this variable to enable the reservation of
 		"protected RAM", i. e. RAM which is not overwritten
 		by U-Boot. Define CONFIG_PRAM to hold the number of
 		kB you want to reserve for pRAM. You can overwrite
 		this default value by defining an environment
 		variable "pram" to the number of kB you want to
 		reserve. Note that the board info structure will
 		still show the full amount of RAM. If pRAM is
 		reserved, a new environment variable "mem" will
 		automatically be defined to hold the amount of
 		remaining RAM in a form that can be passed as boot
 		argument to Linux, for instance like that:
 			setenv bootargs ... mem=\${mem}
 			saveenv
 		This way you can tell Linux not to use this memory,
 		either, which results in a memory region that will
 		not be affected by reboots.
 		*WARNING* If your board configuration uses automatic
 		detection of the RAM size, you must make sure that
 		this memory test is non-destructive. So far, the
 		following board configurations are known to be
 		"pRAM-clean":
 			IVMS8, IVML24, SPD8xx, TQM8xxL,
 			HERMES, IP860, RPXlite, LWMON,
 			FLAGADM, TQM8260
 - Access to physical memory region (> 4GB)
 		Some basic support is provided for operations on memory not
 		normally accessible to U-Boot - e.g. some architectures
 		support access to more than 4GB of memory on 32-bit
 		machines using physical address extension or similar.
 		Define CONFIG_PHYSMEM to access this basic support, which
 		currently only supports clearing the memory.
 - Error Recovery:
 		CONFIG_PANIC_HANG
 		Define this variable to stop the system in case of a
 		fatal error, so that you have to reset it manually.
 		This is probably NOT a good idea for an embedded
 		system where you want the system to reboot
 		automatically as fast as possible, but it may be
 		useful during development since you can try to debug
 		the conditions that lead to the situation.
 		CONFIG_NET_RETRY_COUNT
 		This variable defines the number of retries for
 		network operations like ARP, RARP, TFTP, or BOOTP
 		before giving up the operation. If not defined, a
 		default value of 5 is used.
 		CONFIG_ARP_TIMEOUT
 		Timeout waiting for an ARP reply in milliseconds.
 		CONFIG_NFS_TIMEOUT
 		Timeout in milliseconds used in NFS protocol.
 		If you encounter "ERROR: Cannot umount" in nfs command,
 		try longer timeout such as
 		#define CONFIG_NFS_TIMEOUT 10000UL
 - Command Interpreter:
 		CONFIG_AUTO_COMPLETE
 		Enable auto completion of commands using TAB.
 		Note that this feature has NOT been implemented yet
 		for the "hush" shell.
 		CONFIG_SYS_HUSH_PARSER
 		Define this variable to enable the "hush" shell (from
 		Busybox) as command line interpreter, thus enabling
 		powerful command line syntax like
 		if...then...else...fi conditionals or `&&' and '||'
 		constructs ("shell scripts").
 		If undefined, you get the old, much simpler behaviour
 		with a somewhat smaller memory footprint.
 		CONFIG_SYS_PROMPT_HUSH_PS2
 		This defines the secondary prompt string, which is
 		printed when the command interpreter needs more input
 		to complete a command. Usually "> ".
 	Note:
 		In the current implementation, the local variables
 		space and global environment variables space are
 		separated. Local variables are those you define by
 		simply typing `name=value'. To access a local
 		variable later on, you have write `$name' or
 		`${name}'; to execute the contents of a variable
 		directly type `$name' at the command prompt.
 		Global environment variables are those you use
 		setenv/printenv to work with. To run a command stored
 		in such a variable, you need to use the run command,
 		and you must not use the '$' sign to access them.
 		To store commands and special characters in a
 		variable, please use double quotation marks
 		surrounding the whole text of the variable, instead
 		of the backslashes before semicolons and special
 		symbols.
 - Commandline Editing and History:
 		CONFIG_CMDLINE_EDITING
 		Enable editing and History functions for interactive
 		commandline input operations
 - Default Environment:
 		CONFIG_EXTRA_ENV_SETTINGS
 		Define this to contain any number of null terminated
 		strings (variable = value pairs) that will be part of
 		the default environment compiled into the boot image.
 		For example, place something like this in your
 		board's config file:
 		#define CONFIG_EXTRA_ENV_SETTINGS \
 			"myvar1=value1\0" \
 			"myvar2=value2\0"
 		Warning: This method is based on knowledge about the
 		internal format how the environment is stored by the
 		U-Boot code. This is NOT an official, exported
 		interface! Although it is unlikely that this format
 		will change soon, there is no guarantee either.
 		You better know what you are doing here.
 		Note: overly (ab)use of the default environment is
 		discouraged. Make sure to check other ways to preset
 		the environment like the "source" command or the
 		boot command first.
 		CONFIG_ENV_VARS_UBOOT_CONFIG
 		Define this in order to add variables describing the
 		U-Boot build configuration to the default environment.
 		These will be named arch, cpu, board, vendor, and soc.
 		Enabling this option will cause the following to be defined:
 		- CONFIG_SYS_ARCH
 		- CONFIG_SYS_CPU
 		- CONFIG_SYS_BOARD
 		- CONFIG_SYS_VENDOR
 		- CONFIG_SYS_SOC
 		CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 		Define this in order to add variables describing certain
 		run-time determined information about the hardware to the
 		environment.  These will be named board_name, board_rev.
 		CONFIG_DELAY_ENVIRONMENT
 		Normally the environment is loaded when the board is
 		intialised so that it is available to U-Boot. This inhibits
 		that so that the environment is not available until
 		explicitly loaded later by U-Boot code. With CONFIG_OF_CONTROL
 		this is instead controlled by the value of
 		/config/load-environment.
 - DataFlash Support:
 		CONFIG_HAS_DATAFLASH
 		Defining this option enables DataFlash features and
 		allows to read/write in Dataflash via the standard
 		commands cp, md...
 - Serial Flash support
 		CONFIG_CMD_SF
 		Defining this option enables SPI flash commands
 		'sf probe/read/write/erase/update'.
 		Usage requires an initial 'probe' to define the serial
 		flash parameters, followed by read/write/erase/update
 		commands.
 		The following defaults may be provided by the platform
 		to handle the common case when only a single serial
 		flash is present on the system.
 		CONFIG_SF_DEFAULT_BUS		Bus identifier
 		CONFIG_SF_DEFAULT_CS		Chip-select
 		CONFIG_SF_DEFAULT_MODE 		(see include/spi.h)
 		CONFIG_SF_DEFAULT_SPEED		in Hz
 		CONFIG_CMD_SF_TEST
 		Define this option to include a destructive SPI flash
 		test ('sf test').
 		CONFIG_SPI_FLASH_BAR		Ban/Extended Addr Reg
 		Define this option to use the Bank addr/Extended addr
 		support on SPI flashes which has size > 16Mbytes.
 - SystemACE Support:
 		CONFIG_SYSTEMACE
 		Adding this option adds support for Xilinx SystemACE
 		chips attached via some sort of local bus. The address
 		of the chip must also be defined in the
 		CONFIG_SYS_SYSTEMACE_BASE macro. For example:
 		#define CONFIG_SYSTEMACE
 		#define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000
 		When SystemACE support is added, the "ace" device type
 		becomes available to the fat commands, i.e. fatls.
 - TFTP Fixed UDP Port:
 		CONFIG_TFTP_PORT
 		If this is defined, the environment variable tftpsrcp
 		is used to supply the TFTP UDP source port value.
 		If tftpsrcp isn't defined, the normal pseudo-random port
 		number generator is used.
 		Also, the environment variable tftpdstp is used to supply
 		the TFTP UDP destination port value.  If tftpdstp isn't
 		defined, the normal port 69 is used.
 		The purpose for tftpsrcp is to allow a TFTP server to
 		blindly start the TFTP transfer using the pre-configured
 		target IP address and UDP port. This has the effect of
 		"punching through" the (Windows XP) firewall, allowing
 		the remainder of the TFTP transfer to proceed normally.
 		A better solution is to properly configure the firewall,
 		but sometimes that is not allowed.
 - Hashing support:
 		CONFIG_CMD_HASH
 		This enables a generic 'hash' command which can produce
 		hashes / digests from a few algorithms (e.g. SHA1, SHA256).
 		CONFIG_HASH_VERIFY
 		Enable the hash verify command (hash -v). This adds to code
 		size a little.
 		CONFIG_SHA1 - support SHA1 hashing
 		CONFIG_SHA256 - support SHA256 hashing
 		Note: There is also a sha1sum command, which should perhaps
 		be deprecated in favour of 'hash sha1'.
 - Freescale i.MX specific commands:
 		CONFIG_CMD_HDMIDETECT
 		This enables 'hdmidet' command which returns true if an
 		HDMI monitor is detected.  This command is i.MX 6 specific.
 		CONFIG_CMD_BMODE
 		This enables the 'bmode' (bootmode) command for forcing
 		a boot from specific media.
 		This is useful for forcing the ROM's usb downloader to
 		activate upon a watchdog reset which is nice when iterating
 		on U-Boot.  Using the reset button or running bmode normal
 		will set it back to normal.  This command currently
 		supports i.MX53 and i.MX6.
 - Signing support:
 		CONFIG_RSA
 		This enables the RSA algorithm used for FIT image verification
 		in U-Boot. See doc/uImage/signature for more information.
 		The signing part is build into mkimage regardless of this
 		option.
 - Show boot progress:
 		CONFIG_SHOW_BOOT_PROGRESS
 		Defining this option allows to add some board-
 		specific code (calling a user-provided function
 		"show_boot_progress(int)") that enables you to show
 		the system's boot progress on some display (for
 		example, some LED's) on your board. At the moment,
 		the following checkpoints are implemented:
 - Detailed boot stage timing
 		CONFIG_BOOTSTAGE
 		Define this option to get detailed timing of each stage
 		of the boot process.
 		CONFIG_BOOTSTAGE_USER_COUNT
 		This is the number of available user bootstage records.
 		Each time you call bootstage_mark(BOOTSTAGE_ID_ALLOC, ...)
 		a new ID will be allocated from this stash. If you exceed
 		the limit, recording will stop.
 		CONFIG_BOOTSTAGE_REPORT
 		Define this to print a report before boot, similar to this:
 		Timer summary in microseconds:
 		       Mark    Elapsed  Stage
 			  0          0  reset
 		  3,575,678  3,575,678  board_init_f start
 		  3,575,695         17  arch_cpu_init A9
 		  3,575,777         82  arch_cpu_init done
 		  3,659,598     83,821  board_init_r start
 		  3,910,375    250,777  main_loop
 		 29,916,167 26,005,792  bootm_start
 		 30,361,327    445,160  start_kernel
 		CONFIG_CMD_BOOTSTAGE
 		Add a 'bootstage' command which supports printing a report
 		and un/stashing of bootstage data.
 		CONFIG_BOOTSTAGE_FDT
 		Stash the bootstage information in the FDT. A root 'bootstage'
 		node is created with each bootstage id as a child. Each child
 		has a 'name' property and either 'mark' containing the
 		mark time in microsecond, or 'accum' containing the
 		accumulated time for that bootstage id in microseconds.
 		For example:
 		bootstage {
 			154 {
 				name = "board_init_f";
 				mark = <3575678>;
 			};
 			170 {
 				name = "lcd";
 				accum = <33482>;
 			};
 		};
 		Code in the Linux kernel can find this in /proc/devicetree.
 Legacy uImage format:
   Arg	Where			When
     1	common/cmd_bootm.c	before attempting to boot an image
    -1	common/cmd_bootm.c	Image header has bad	 magic number
     2	common/cmd_bootm.c	Image header has correct magic number
    -2	common/cmd_bootm.c	Image header has bad	 checksum
     3	common/cmd_bootm.c	Image header has correct checksum
    -3	common/cmd_bootm.c	Image data   has bad	 checksum
     4	common/cmd_bootm.c	Image data   has correct checksum
    -4	common/cmd_bootm.c	Image is for unsupported architecture
     5	common/cmd_bootm.c	Architecture check OK
    -5	common/cmd_bootm.c	Wrong Image Type (not kernel, multi)
     6	common/cmd_bootm.c	Image Type check OK
    -6	common/cmd_bootm.c	gunzip uncompression error
    -7	common/cmd_bootm.c	Unimplemented compression type
     7	common/cmd_bootm.c	Uncompression OK
     8	common/cmd_bootm.c	No uncompress/copy overwrite error
    -9	common/cmd_bootm.c	Unsupported OS (not Linux, BSD, VxWorks, QNX)
     9	common/image.c		Start initial ramdisk verification
   -10	common/image.c		Ramdisk header has bad	   magic number
   -11	common/image.c		Ramdisk header has bad	   checksum
    10	common/image.c		Ramdisk header is OK
   -12	common/image.c		Ramdisk data   has bad	   checksum
    11	common/image.c		Ramdisk data   has correct checksum
    12	common/image.c		Ramdisk verification complete, start loading
   -13	common/image.c		Wrong Image Type (not PPC Linux ramdisk)
    13	common/image.c		Start multifile image verification
    14	common/image.c		No initial ramdisk, no multifile, continue.
    15	arch/<arch>/lib/bootm.c All preparation done, transferring control to OS
   -30	arch/powerpc/lib/board.c	Fatal error, hang the system
   -31	post/post.c		POST test failed, detected by post_output_backlog()
   -32	post/post.c		POST test failed, detected by post_run_single()
    34	common/cmd_doc.c	before loading a Image from a DOC device
   -35	common/cmd_doc.c	Bad usage of "doc" command
    35	common/cmd_doc.c	correct usage of "doc" command
   -36	common/cmd_doc.c	No boot device
    36	common/cmd_doc.c	correct boot device
   -37	common/cmd_doc.c	Unknown Chip ID on boot device
    37	common/cmd_doc.c	correct chip ID found, device available
   -38	common/cmd_doc.c	Read Error on boot device
    38	common/cmd_doc.c	reading Image header from DOC device OK
   -39	common/cmd_doc.c	Image header has bad magic number
    39	common/cmd_doc.c	Image header has correct magic number
   -40	common/cmd_doc.c	Error reading Image from DOC device
    40	common/cmd_doc.c	Image header has correct magic number
    41	common/cmd_ide.c	before loading a Image from a IDE device
   -42	common/cmd_ide.c	Bad usage of "ide" command
    42	common/cmd_ide.c	correct usage of "ide" command
   -43	common/cmd_ide.c	No boot device
    43	common/cmd_ide.c	boot device found
   -44	common/cmd_ide.c	Device not available
    44	common/cmd_ide.c	Device available
   -45	common/cmd_ide.c	wrong partition selected
    45	common/cmd_ide.c	partition selected
   -46	common/cmd_ide.c	Unknown partition table
    46	common/cmd_ide.c	valid partition table found
   -47	common/cmd_ide.c	Invalid partition type
    47	common/cmd_ide.c	correct partition type
   -48	common/cmd_ide.c	Error reading Image Header on boot device
    48	common/cmd_ide.c	reading Image Header from IDE device OK
   -49	common/cmd_ide.c	Image header has bad magic number
    49	common/cmd_ide.c	Image header has correct magic number
   -50	common/cmd_ide.c	Image header has bad	 checksum
    50	common/cmd_ide.c	Image header has correct checksum
   -51	common/cmd_ide.c	Error reading Image from IDE device
    51	common/cmd_ide.c	reading Image from IDE device OK
    52	common/cmd_nand.c	before loading a Image from a NAND device
   -53	common/cmd_nand.c	Bad usage of "nand" command
    53	common/cmd_nand.c	correct usage of "nand" command
   -54	common/cmd_nand.c	No boot device
    54	common/cmd_nand.c	boot device found
   -55	common/cmd_nand.c	Unknown Chip ID on boot device
    55	common/cmd_nand.c	correct chip ID found, device available
   -56	common/cmd_nand.c	Error reading Image Header on boot device
    56	common/cmd_nand.c	reading Image Header from NAND device OK
   -57	common/cmd_nand.c	Image header has bad magic number
    57	common/cmd_nand.c	Image header has correct magic number
   -58	common/cmd_nand.c	Error reading Image from NAND device
    58	common/cmd_nand.c	reading Image from NAND device OK
   -60	common/env_common.c	Environment has a bad CRC, using default
    64	net/eth.c		starting with Ethernet configuration.
   -64	net/eth.c		no Ethernet found.
    65	net/eth.c		Ethernet found.
   -80	common/cmd_net.c	usage wrong
    80	common/cmd_net.c	before calling NetLoop()
   -81	common/cmd_net.c	some error in NetLoop() occurred
    81	common/cmd_net.c	NetLoop() back without error
   -82	common/cmd_net.c	size == 0 (File with size 0 loaded)
    82	common/cmd_net.c	trying automatic boot
    83	common/cmd_net.c	running "source" command
   -83	common/cmd_net.c	some error in automatic boot or "source" command
    84	common/cmd_net.c	end without errors
 FIT uImage format:
   Arg	Where			When
   100	common/cmd_bootm.c	Kernel FIT Image has correct format
  -100	common/cmd_bootm.c	Kernel FIT Image has incorrect format
   101	common/cmd_bootm.c	No Kernel subimage unit name, using configuration
  -101	common/cmd_bootm.c	Can't get configuration for kernel subimage
   102	common/cmd_bootm.c	Kernel unit name specified
  -103	common/cmd_bootm.c	Can't get kernel subimage node offset
   103	common/cmd_bootm.c	Found configuration node
   104	common/cmd_bootm.c	Got kernel subimage node offset
  -104	common/cmd_bootm.c	Kernel subimage hash verification failed
   105	common/cmd_bootm.c	Kernel subimage hash verification OK
  -105	common/cmd_bootm.c	Kernel subimage is for unsupported architecture
   106	common/cmd_bootm.c	Architecture check OK
  -106	common/cmd_bootm.c	Kernel subimage has wrong type
   107	common/cmd_bootm.c	Kernel subimage type OK
  -107	common/cmd_bootm.c	Can't get kernel subimage data/size
   108	common/cmd_bootm.c	Got kernel subimage data/size
  -108	common/cmd_bootm.c	Wrong image type (not legacy, FIT)
  -109	common/cmd_bootm.c	Can't get kernel subimage type
  -110	common/cmd_bootm.c	Can't get kernel subimage comp
  -111	common/cmd_bootm.c	Can't get kernel subimage os
  -112	common/cmd_bootm.c	Can't get kernel subimage load address
  -113	common/cmd_bootm.c	Image uncompress/copy overwrite error
   120	common/image.c		Start initial ramdisk verification
  -120	common/image.c		Ramdisk FIT image has incorrect format
   121	common/image.c		Ramdisk FIT image has correct format
   122	common/image.c		No ramdisk subimage unit name, using configuration
  -122	common/image.c		Can't get configuration for ramdisk subimage
   123	common/image.c		Ramdisk unit name specified
  -124	common/image.c		Can't get ramdisk subimage node offset
   125	common/image.c		Got ramdisk subimage node offset
  -125	common/image.c		Ramdisk subimage hash verification failed
   126	common/image.c		Ramdisk subimage hash verification OK
  -126	common/image.c		Ramdisk subimage for unsupported architecture
   127	common/image.c		Architecture check OK
  -127	common/image.c		Can't get ramdisk subimage data/size
   128	common/image.c		Got ramdisk subimage data/size
   129	common/image.c		Can't get ramdisk load address
  -129	common/image.c		Got ramdisk load address
  -130	common/cmd_doc.c	Incorrect FIT image format
   131	common/cmd_doc.c	FIT image format OK
  -140	common/cmd_ide.c	Incorrect FIT image format
   141	common/cmd_ide.c	FIT image format OK
  -150	common/cmd_nand.c	Incorrect FIT image format
   151	common/cmd_nand.c	FIT image format OK
 - FIT image support:
 		CONFIG_FIT
 		Enable support for the FIT uImage format.
 		CONFIG_FIT_BEST_MATCH
 		When no configuration is explicitly selected, default to the
 		one whose fdt's compatibility field best matches that of
 		U-Boot itself. A match is considered "best" if it matches the
 		most specific compatibility entry of U-Boot's fdt's root node.
 		The order of entries in the configuration's fdt is ignored.
 		CONFIG_FIT_SIGNATURE
 		This option enables signature verification of FIT uImages,
 		using a hash signed and verified using RSA. See
 		doc/uImage.FIT/signature.txt for more details.
 - Standalone program support:
 		CONFIG_STANDALONE_LOAD_ADDR
 		This option defines a board specific value for the
 		address where standalone program gets loaded, thus
 		overwriting the architecture dependent default
 		settings.
 - Frame Buffer Address:
 		CONFIG_FB_ADDR
 		Define CONFIG_FB_ADDR if you want to use specific
 		address for frame buffer.  This is typically the case
 		when using a graphics controller has separate video
 		memory.  U-Boot will then place the frame buffer at
 		the given address instead of dynamically reserving it
 		in system RAM by calling lcd_setmem(), which grabs
 		the memory for the frame buffer depending on the
 		configured panel size.
 		Please see board_init_f function.
 - Automatic software updates via TFTP server
 		CONFIG_UPDATE_TFTP
 		CONFIG_UPDATE_TFTP_CNT_MAX
 		CONFIG_UPDATE_TFTP_MSEC_MAX
 		These options enable and control the auto-update feature;
 		for a more detailed description refer to doc/README.update.
 - MTD Support (mtdparts command, UBI support)
 		CONFIG_MTD_DEVICE
 		Adds the MTD device infrastructure from the Linux kernel.
 		Needed for mtdparts command support.
 		CONFIG_MTD_PARTITIONS
 		Adds the MTD partitioning infrastructure from the Linux
 		kernel. Needed for UBI support.
 - UBI support
 		CONFIG_CMD_UBI
 		Adds commands for interacting with MTD partitions formatted
 		with the UBI flash translation layer
 		Requires also defining CONFIG_RBTREE
 		CONFIG_UBI_SILENCE_MSG
 		Make the verbose messages from UBI stop printing.  This leaves
 		warnings and errors enabled.
 - UBIFS support
 		CONFIG_CMD_UBIFS
 		Adds commands for interacting with UBI volumes formatted as
 		UBIFS.  UBIFS is read-only in u-boot.
 		Requires UBI support as well as CONFIG_LZO
 		CONFIG_UBIFS_SILENCE_MSG
 		Make the verbose messages from UBIFS stop printing.  This leaves
 		warnings and errors enabled.
 - SPL framework
 		CONFIG_SPL
 		Enable building of SPL globally.
 		CONFIG_SPL_LDSCRIPT
 		LDSCRIPT for linking the SPL binary.
 		CONFIG_SPL_MAX_FOOTPRINT
 		Maximum size in memory allocated to the SPL, BSS included.
 		When defined, the linker checks that the actual memory
 		used by SPL from _start to __bss_end does not exceed it.
 		CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
 		must not be both defined at the same time.
 		CONFIG_SPL_MAX_SIZE
 		Maximum size of the SPL image (text, data, rodata, and
 		linker lists sections), BSS excluded.
 		When defined, the linker checks that the actual size does
 		not exceed it.
 		CONFIG_SPL_TEXT_BASE
 		TEXT_BASE for linking the SPL binary.
 		CONFIG_SPL_RELOC_TEXT_BASE
 		Address to relocate to.  If unspecified, this is equal to
 		CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).
 		CONFIG_SPL_BSS_START_ADDR
 		Link address for the BSS within the SPL binary.
 		CONFIG_SPL_BSS_MAX_SIZE
 		Maximum size in memory allocated to the SPL BSS.
 		When defined, the linker checks that the actual memory used
 		by SPL from __bss_start to __bss_end does not exceed it.
 		CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
 		must not be both defined at the same time.
 		CONFIG_SPL_STACK
 		Adress of the start of the stack SPL will use
 		CONFIG_SPL_RELOC_STACK
 		Adress of the start of the stack SPL will use after
 		relocation.  If unspecified, this is equal to
 		CONFIG_SPL_STACK.
 		CONFIG_SYS_SPL_MALLOC_START
 		Starting address of the malloc pool used in SPL.
 		CONFIG_SYS_SPL_MALLOC_SIZE
 		The size of the malloc pool used in SPL.
 		CONFIG_SPL_FRAMEWORK
 		Enable the SPL framework under common/.  This framework
 		supports MMC, NAND and YMODEM loading of U-Boot and NAND
 		NAND loading of the Linux Kernel.
 		CONFIG_SPL_DISPLAY_PRINT
 		For ARM, enable an optional function to print more information
 		about the running system.
 		CONFIG_SPL_INIT_MINIMAL
 		Arch init code should be built for a very small image
 		CONFIG_SPL_LIBCOMMON_SUPPORT
 		Support for common/libcommon.o in SPL binary
 		CONFIG_SPL_LIBDISK_SUPPORT
 		Support for disk/libdisk.o in SPL binary
 		CONFIG_SPL_I2C_SUPPORT
 		Support for drivers/i2c/libi2c.o in SPL binary
 		CONFIG_SPL_GPIO_SUPPORT
 		Support for drivers/gpio/libgpio.o in SPL binary
 		CONFIG_SPL_MMC_SUPPORT
 		Support for drivers/mmc/libmmc.o in SPL binary
 		CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
 		CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
 		CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION
 		Address, size and partition on the MMC to load U-Boot from
 		when the MMC is being used in raw mode.
 		CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
 		Sector to load kernel uImage from when MMC is being
 		used in raw mode (for Falcon mode)
 		CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
 		CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
 		Sector and number of sectors to load kernel argument
 		parameters from when MMC is being used in raw mode
 		(for falcon mode)
 		CONFIG_SPL_FAT_SUPPORT
 		Support for fs/fat/libfat.o in SPL binary
 		CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME
 		Filename to read to load U-Boot when reading from FAT
 		CONFIG_SPL_FAT_LOAD_KERNEL_NAME
 		Filename to read to load kernel uImage when reading
 		from FAT (for Falcon mode)
 		CONFIG_SPL_FAT_LOAD_ARGS_NAME
 		Filename to read to load kernel argument parameters
 		when reading from FAT (for Falcon mode)
 		CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
 		Set this for NAND SPL on PPC mpc83xx targets, so that
 		start.S waits for the rest of the SPL to load before
 		continuing (the hardware starts execution after just
 		loading the first page rather than the full 4K).
 		CONFIG_SPL_NAND_BASE
 		Include nand_base.c in the SPL.  Requires
 		CONFIG_SPL_NAND_DRIVERS.
 		CONFIG_SPL_NAND_DRIVERS
 		SPL uses normal NAND drivers, not minimal drivers.
 		CONFIG_SPL_NAND_ECC
 		Include standard software ECC in the SPL
 		CONFIG_SPL_NAND_SIMPLE
 		Support for NAND boot using simple NAND drivers that
 		expose the cmd_ctrl() interface.
 		CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 		Set for the SPL on PPC mpc8xxx targets, support for
 		drivers/ddr/fsl/libddr.o in SPL binary.
 		CONFIG_SPL_COMMON_INIT_DDR
 		Set for common ddr init with serial presence detect in
 		SPL binary.
 		CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
 		CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
 		CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
 		CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
 		CONFIG_SYS_NAND_ECCBYTES
 		Defines the size and behavior of the NAND that SPL uses
 		to read U-Boot
+		CONFIG_SPL_NAND_BOOT
+		Add support NAND boot
 		CONFIG_SYS_NAND_U_BOOT_OFFS
 		Location in NAND to read U-Boot from
 		CONFIG_SYS_NAND_U_BOOT_DST
 		Location in memory to load U-Boot to
 		CONFIG_SYS_NAND_U_BOOT_SIZE
 		Size of image to load
 		CONFIG_SYS_NAND_U_BOOT_START
 		Entry point in loaded image to jump to
 		CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 		Define this if you need to first read the OOB and then the
 		data. This is used for example on davinci plattforms.
 		CONFIG_SPL_OMAP3_ID_NAND
 		Support for an OMAP3-specific set of functions to return the
 		ID and MFR of the first attached NAND chip, if present.
 		CONFIG_SPL_SERIAL_SUPPORT
 		Support for drivers/serial/libserial.o in SPL binary
 		CONFIG_SPL_SPI_FLASH_SUPPORT
 		Support for drivers/mtd/spi/libspi_flash.o in SPL binary
 		CONFIG_SPL_SPI_SUPPORT
 		Support for drivers/spi/libspi.o in SPL binary
 		CONFIG_SPL_RAM_DEVICE
 		Support for running image already present in ram, in SPL binary
 		CONFIG_SPL_LIBGENERIC_SUPPORT
 		Support for lib/libgeneric.o in SPL binary
 		CONFIG_SPL_ENV_SUPPORT
 		Support for the environment operating in SPL binary
 		CONFIG_SPL_NET_SUPPORT
 		Support for the net/libnet.o in SPL binary.
 		It conflicts with SPL env from storage medium specified by
 		CONFIG_ENV_IS_xxx but CONFIG_ENV_IS_NOWHERE
 		CONFIG_SPL_PAD_TO
 		Image offset to which the SPL should be padded before appending
 		the SPL payload. By default, this is defined as
 		CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
 		CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
 		payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
 		CONFIG_SPL_TARGET
 		Final target image containing SPL and payload.  Some SPLs
 		use an arch-specific makefile fragment instead, for
 		example if more than one image needs to be produced.
 		CONFIG_FIT_SPL_PRINT
 		Printing information about a FIT image adds quite a bit of
 		code to SPL. So this is normally disabled in SPL. Use this
 		option to re-enable it. This will affect the output of the
 		bootm command when booting a FIT image.
 - TPL framework
 		CONFIG_TPL
 		Enable building of TPL globally.
 		CONFIG_TPL_PAD_TO
 		Image offset to which the TPL should be padded before appending
 		the TPL payload. By default, this is defined as
 		CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
 		CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
 		payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
 Modem Support:
 --------------
 [so far only for SMDK2400 boards]
 - Modem support enable:
 		CONFIG_MODEM_SUPPORT
 - RTS/CTS Flow control enable:
 		CONFIG_HWFLOW
 - Modem debug support:
 		CONFIG_MODEM_SUPPORT_DEBUG
 		Enables debugging stuff (char screen[1024], dbg())
 		for modem support. Useful only with BDI2000.
 - Interrupt support (PPC):
 		There are common interrupt_init() and timer_interrupt()
 		for all PPC archs. interrupt_init() calls interrupt_init_cpu()
 		for CPU specific initialization. interrupt_init_cpu()
 		should set decrementer_count to appropriate value. If
 		CPU resets decrementer automatically after interrupt
 		(ppc4xx) it should set decrementer_count to zero.
 		timer_interrupt() calls timer_interrupt_cpu() for CPU
 		specific handling. If board has watchdog / status_led
 		/ other_activity_monitor it works automatically from
 		general timer_interrupt().
 - General:
 		In the target system modem support is enabled when a
 		specific key (key combination) is pressed during
 		power-on. Otherwise U-Boot will boot normally
 		(autoboot). The key_pressed() function is called from
 		board_init(). Currently key_pressed() is a dummy
 		function, returning 1 and thus enabling modem
 		initialization.
 		If there are no modem init strings in the
 		environment, U-Boot proceed to autoboot; the
 		previous output (banner, info printfs) will be
 		suppressed, though.
 		See also: doc/README.Modem
 Board initialization settings:
 ------------------------------
 During Initialization u-boot calls a number of board specific functions
 to allow the preparation of board specific prerequisites, e.g. pin setup
 before drivers are initialized. To enable these callbacks the
 following configuration macros have to be defined. Currently this is
 architecture specific, so please check arch/your_architecture/lib/board.c
 typically in board_init_f() and board_init_r().
 - CONFIG_BOARD_EARLY_INIT_F: Call board_early_init_f()
 - CONFIG_BOARD_EARLY_INIT_R: Call board_early_init_r()
 - CONFIG_BOARD_LATE_INIT: Call board_late_init()
 - CONFIG_BOARD_POSTCLK_INIT: Call board_postclk_init()
 Configuration Settings:
 -----------------------
 - CONFIG_SYS_LONGHELP: Defined when you want long help messages included;
 		undefine this when you're short of memory.
 - CONFIG_SYS_HELP_CMD_WIDTH: Defined when you want to override the default
 		width of the commands listed in the 'help' command output.
 - CONFIG_SYS_PROMPT:	This is what U-Boot prints on the console to
 		prompt for user input.
 - CONFIG_SYS_CBSIZE:	Buffer size for input from the Console
 - CONFIG_SYS_PBSIZE:	Buffer size for Console output
 - CONFIG_SYS_MAXARGS:	max. Number of arguments accepted for monitor commands
 - CONFIG_SYS_BARGSIZE: Buffer size for Boot Arguments which are passed to
 		the application (usually a Linux kernel) when it is
 		booted
 - CONFIG_SYS_BAUDRATE_TABLE:
 		List of legal baudrate settings for this board.
 - CONFIG_SYS_CONSOLE_INFO_QUIET
 		Suppress display of console information at boot.
 - CONFIG_SYS_CONSOLE_IS_IN_ENV
 		If the board specific function
 			extern int overwrite_console (void);
 		returns 1, the stdin, stderr and stdout are switched to the
 		serial port, else the settings in the environment are used.
 - CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 		Enable the call to overwrite_console().
 - CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 		Enable overwrite of previous console environment settings.
 - CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END:
 		Begin and End addresses of the area used by the
 		simple memory test.
 - CONFIG_SYS_ALT_MEMTEST:
 		Enable an alternate, more extensive memory test.
 - CONFIG_SYS_MEMTEST_SCRATCH:
 		Scratch address used by the alternate memory test
 		You only need to set this if address zero isn't writeable
 - CONFIG_SYS_MEM_TOP_HIDE (PPC only):
 		If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config header,
 		this specified memory area will get subtracted from the top
 		(end) of RAM and won't get "touched" at all by U-Boot. By
 		fixing up gd->ram_size the Linux kernel should gets passed
 		the now "corrected" memory size and won't touch it either.
 		This should work for arch/ppc and arch/powerpc. Only Linux
 		board ports in arch/powerpc with bootwrapper support that
 		recalculate the memory size from the SDRAM controller setup
 		will have to get fixed in Linux additionally.
 		This option can be used as a workaround for the 440EPx/GRx
 		CHIP 11 errata where the last 256 bytes in SDRAM shouldn't
 		be touched.
 		WARNING: Please make sure that this value is a multiple of
 		the Linux page size (normally 4k). If this is not the case,
 		then the end address of the Linux memory will be located at a
 		non page size aligned address and this could cause major
 		problems.
 - CONFIG_SYS_LOADS_BAUD_CHANGE:
 		Enable temporary baudrate change while serial download
 - CONFIG_SYS_SDRAM_BASE:
 		Physical start address of SDRAM. _Must_ be 0 here.
 - CONFIG_SYS_MBIO_BASE:
 		Physical start address of Motherboard I/O (if using a
 		Cogent motherboard)
 - CONFIG_SYS_FLASH_BASE:
 		Physical start address of Flash memory.
 - CONFIG_SYS_MONITOR_BASE:
 		Physical start address of boot monitor code (set by
 		make config files to be same as the text base address
 		(CONFIG_SYS_TEXT_BASE) used when linking) - same as
 		CONFIG_SYS_FLASH_BASE when booting from flash.
 - CONFIG_SYS_MONITOR_LEN:
 		Size of memory reserved for monitor code, used to
 		determine _at_compile_time_ (!) if the environment is
 		embedded within the U-Boot image, or in a separate
 		flash sector.
 - CONFIG_SYS_MALLOC_LEN:
 		Size of DRAM reserved for malloc() use.
 - CONFIG_SYS_BOOTM_LEN:
 		Normally compressed uImages are limited to an
 		uncompressed size of 8 MBytes. If this is not enough,
 		you can define CONFIG_SYS_BOOTM_LEN in your board config file
 		to adjust this setting to your needs.
 - CONFIG_SYS_BOOTMAPSZ:
 		Maximum size of memory mapped by the startup code of
 		the Linux kernel; all data that must be processed by
 		the Linux kernel (bd_info, boot arguments, FDT blob if
 		used) must be put below this limit, unless "bootm_low"
 		environment variable is defined and non-zero. In such case
 		all data for the Linux kernel must be between "bootm_low"
 		and "bootm_low" + CONFIG_SYS_BOOTMAPSZ.	 The environment
 		variable "bootm_mapsize" will override the value of
 		CONFIG_SYS_BOOTMAPSZ.  If CONFIG_SYS_BOOTMAPSZ is undefined,
 		then the value in "bootm_size" will be used instead.
 - CONFIG_SYS_BOOT_RAMDISK_HIGH:
 		Enable initrd_high functionality.  If defined then the
 		initrd_high feature is enabled and the bootm ramdisk subcommand
 		is enabled.
 - CONFIG_SYS_BOOT_GET_CMDLINE:
 		Enables allocating and saving kernel cmdline in space between
 		"bootm_low" and "bootm_low" + BOOTMAPSZ.
 - CONFIG_SYS_BOOT_GET_KBD:
 		Enables allocating and saving a kernel copy of the bd_info in
 		space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
 - CONFIG_SYS_MAX_FLASH_BANKS:
 		Max number of Flash memory banks
 - CONFIG_SYS_MAX_FLASH_SECT:
 		Max number of sectors on a Flash chip
 - CONFIG_SYS_FLASH_ERASE_TOUT:
 		Timeout for Flash erase operations (in ms)
 - CONFIG_SYS_FLASH_WRITE_TOUT:
 		Timeout for Flash write operations (in ms)
 - CONFIG_SYS_FLASH_LOCK_TOUT
 		Timeout for Flash set sector lock bit operation (in ms)
 - CONFIG_SYS_FLASH_UNLOCK_TOUT
 		Timeout for Flash clear lock bits operation (in ms)
 - CONFIG_SYS_FLASH_PROTECTION
 		If defined, hardware flash sectors protection is used
 		instead of U-Boot software protection.
 - CONFIG_SYS_DIRECT_FLASH_TFTP:
 		Enable TFTP transfers directly to flash memory;
 		without this option such a download has to be
 		performed in two steps: (1) download to RAM, and (2)
 		copy from RAM to flash.
 		The two-step approach is usually more reliable, since
 		you can check if the download worked before you erase
 		the flash, but in some situations (when system RAM is
 		too limited to allow for a temporary copy of the
 		downloaded image) this option may be very useful.
 - CONFIG_SYS_FLASH_CFI:
 		Define if the flash driver uses extra elements in the
 		common flash structure for storing flash geometry.
 - CONFIG_FLASH_CFI_DRIVER
 		This option also enables the building of the cfi_flash driver
 		in the drivers directory
 - CONFIG_FLASH_CFI_MTD
 		This option enables the building of the cfi_mtd driver
 		in the drivers directory. The driver exports CFI flash
 		to the MTD layer.
 - CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 		Use buffered writes to flash.
 - CONFIG_FLASH_SPANSION_S29WS_N
 		s29ws-n MirrorBit flash has non-standard addresses for buffered
 		write commands.
 - CONFIG_SYS_FLASH_QUIET_TEST
 		If this option is defined, the common CFI flash doesn't
 		print it's warning upon not recognized FLASH banks. This
 		is useful, if some of the configured banks are only
 		optionally available.
 - CONFIG_FLASH_SHOW_PROGRESS
 		If defined (must be an integer), print out countdown
 		digits and dots.  Recommended value: 45 (9..1) for 80
 		column displays, 15 (3..1) for 40 column displays.
 - CONFIG_FLASH_VERIFY
 		If defined, the content of the flash (destination) is compared
 		against the source after the write operation. An error message
 		will be printed when the contents are not identical.
 		Please note that this option is useless in nearly all cases,
 		since such flash programming errors usually are detected earlier
 		while unprotecting/erasing/programming. Please only enable
 		this option if you really know what you are doing.
 - CONFIG_SYS_RX_ETH_BUFFER:
 		Defines the number of Ethernet receive buffers. On some
 		Ethernet controllers it is recommended to set this value
 		to 8 or even higher (EEPRO100 or 405 EMAC), since all
 		buffers can be full shortly after enabling the interface
 		on high Ethernet traffic.
 		Defaults to 4 if not defined.
 - CONFIG_ENV_MAX_ENTRIES
 	Maximum number of entries in the hash table that is used
 	internally to store the environment settings. The default
 	setting is supposed to be generous and should work in most
 	cases. This setting can be used to tune behaviour; see
 	lib/hashtable.c for details.
 - CONFIG_ENV_FLAGS_LIST_DEFAULT
 - CONFIG_ENV_FLAGS_LIST_STATIC
 	Enable validation of the values given to environment variables when
 	calling env set.  Variables can be restricted to only decimal,
 	hexadecimal, or boolean.  If CONFIG_CMD_NET is also defined,
 	the variables can also be restricted to IP address or MAC address.
 	The format of the list is:
 		type_attribute = [s|d|x|b|i|m]
 		access_atribute = [a|r|o|c]
 		attributes = type_attribute[access_atribute]
 		entry = variable_name[:attributes]
 		list = entry[,list]
 	The type attributes are:
 		s - String (default)
 		d - Decimal
 		x - Hexadecimal
 		b - Boolean ([1yYtT|0nNfF])
 		i - IP address
 		m - MAC address
 	The access attributes are:
 		a - Any (default)
 		r - Read-only
 		o - Write-once
 		c - Change-default
 	- CONFIG_ENV_FLAGS_LIST_DEFAULT
 		Define this to a list (string) to define the ".flags"
 		envirnoment variable in the default or embedded environment.
 	- CONFIG_ENV_FLAGS_LIST_STATIC
 		Define this to a list (string) to define validation that
 		should be done if an entry is not found in the ".flags"
 		environment variable.  To override a setting in the static
 		list, simply add an entry for the same variable name to the
 		".flags" variable.
 - CONFIG_ENV_ACCESS_IGNORE_FORCE
 	If defined, don't allow the -f switch to env set override variable
 	access flags.
 - CONFIG_SYS_GENERIC_BOARD
 	This selects the architecture-generic board system instead of the
 	architecture-specific board files. It is intended to move boards
 	to this new framework over time. Defining this will disable the
 	arch/foo/lib/board.c file and use common/board_f.c and
 	common/board_r.c instead. To use this option your architecture
 	must support it (i.e. must define __HAVE_ARCH_GENERIC_BOARD in
 	its config.mk file). If you find problems enabling this option on
 	your board please report the problem and send patches!
 - CONFIG_SYS_SYM_OFFSETS
 	This is set by architectures that use offsets for link symbols
 	instead of absolute values. So bss_start is obtained using an
 	offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than
 	directly. You should not need to touch this setting.
 - CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
 	This is set by OMAP boards for the max time that reset should
 	be asserted. See doc/README.omap-reset-time for details on how
 	the value can be calulated on a given board.
 The following definitions that deal with the placement and management
 of environment data (variable area); in general, we support the
 following configurations:
 - CONFIG_BUILD_ENVCRC:
 	Builds up envcrc with the target environment so that external utils
 	may easily extract it and embed it in final U-Boot images.
 - CONFIG_ENV_IS_IN_FLASH:
 	Define this if the environment is in flash memory.
 	a) The environment occupies one whole flash sector, which is
 	   "embedded" in the text segment with the U-Boot code. This
 	   happens usually with "bottom boot sector" or "top boot
 	   sector" type flash chips, which have several smaller
 	   sectors at the start or the end. For instance, such a
 	   layout can have sector sizes of 8, 2x4, 16, Nx32 kB. In
 	   such a case you would place the environment in one of the
 	   4 kB sectors - with U-Boot code before and after it. With
 	   "top boot sector" type flash chips, you would put the
 	   environment in one of the last sectors, leaving a gap
 	   between U-Boot and the environment.
 	- CONFIG_ENV_OFFSET:
 	   Offset of environment data (variable area) to the
 	   beginning of flash memory; for instance, with bottom boot
 	   type flash chips the second sector can be used: the offset
 	   for this sector is given here.
 	   CONFIG_ENV_OFFSET is used relative to CONFIG_SYS_FLASH_BASE.
 	- CONFIG_ENV_ADDR:
 	   This is just another way to specify the start address of
 	   the flash sector containing the environment (instead of
 	   CONFIG_ENV_OFFSET).
 	- CONFIG_ENV_SECT_SIZE:
 	   Size of the sector containing the environment.
 	b) Sometimes flash chips have few, equal sized, BIG sectors.
 	   In such a case you don't want to spend a whole sector for
 	   the environment.
 	- CONFIG_ENV_SIZE:
 	   If you use this in combination with CONFIG_ENV_IS_IN_FLASH
 	   and CONFIG_ENV_SECT_SIZE, you can specify to use only a part
 	   of this flash sector for the environment. This saves
 	   memory for the RAM copy of the environment.
 	   It may also save flash memory if you decide to use this
 	   when your environment is "embedded" within U-Boot code,
 	   since then the remainder of the flash sector could be used
 	   for U-Boot code. It should be pointed out that this is
 	   STRONGLY DISCOURAGED from a robustness point of view:
 	   updating the environment in flash makes it always
 	   necessary to erase the WHOLE sector. If something goes
 	   wrong before the contents has been restored from a copy in
 	   RAM, your target system will be dead.
 	- CONFIG_ENV_ADDR_REDUND
 	  CONFIG_ENV_SIZE_REDUND
 	   These settings describe a second storage area used to hold
 	   a redundant copy of the environment data, so that there is
 	   a valid backup copy in case there is a power failure during
 	   a "saveenv" operation.
 BE CAREFUL! Any changes to the flash layout, and some changes to the
 source code will make it necessary to adapt <board>/u-boot.lds*
 accordingly!
 - CONFIG_ENV_IS_IN_NVRAM:
 	Define this if you have some non-volatile memory device
 	(NVRAM, battery buffered SRAM) which you want to use for the
 	environment.
 	- CONFIG_ENV_ADDR:
 	- CONFIG_ENV_SIZE:
 	  These two #defines are used to determine the memory area you
 	  want to use for environment. It is assumed that this memory
 	  can just be read and written to, without any special
 	  provision.
 BE CAREFUL! The first access to the environment happens quite early
 in U-Boot initalization (when we try to get the setting of for the
 console baudrate). You *MUST* have mapped your NVRAM area then, or
 U-Boot will hang.
 Please note that even with NVRAM we still use a copy of the
 environment in RAM: we could work on NVRAM directly, but we want to
 keep settings there always unmodified except somebody uses "saveenv"
 to save the current settings.
 - CONFIG_ENV_IS_IN_EEPROM:
 	Use this if you have an EEPROM or similar serial access
 	device and a driver for it.
 	- CONFIG_ENV_OFFSET:
 	- CONFIG_ENV_SIZE:
 	  These two #defines specify the offset and size of the
 	  environment area within the total memory of your EEPROM.
 	- CONFIG_SYS_I2C_EEPROM_ADDR:
 	  If defined, specified the chip address of the EEPROM device.
 	  The default address is zero.
 	- CONFIG_SYS_EEPROM_PAGE_WRITE_BITS:
 	  If defined, the number of bits used to address bytes in a
 	  single page in the EEPROM device.  A 64 byte page, for example
 	  would require six bits.
 	- CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS:
 	  If defined, the number of milliseconds to delay between
 	  page writes.	The default is zero milliseconds.
 	- CONFIG_SYS_I2C_EEPROM_ADDR_LEN:
 	  The length in bytes of the EEPROM memory array address.  Note
 	  that this is NOT the chip address length!
 	- CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW:
 	  EEPROM chips that implement "address overflow" are ones
 	  like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 	  address and the extra bits end up in the "chip address" bit
 	  slots. This makes a 24WC08 (1Kbyte) chip look like four 256
 	  byte chips.
 	  Note that we consider the length of the address field to
 	  still be one byte because the extra address bits are hidden
 	  in the chip address.
 	- CONFIG_SYS_EEPROM_SIZE:
 	  The size in bytes of the EEPROM device.
 	- CONFIG_ENV_EEPROM_IS_ON_I2C
 	  define this, if you have I2C and SPI activated, and your
 	  EEPROM, which holds the environment, is on the I2C bus.
 	- CONFIG_I2C_ENV_EEPROM_BUS
 	  if you have an Environment on an EEPROM reached over
 	  I2C muxes, you can define here, how to reach this
 	  EEPROM. For example:
 	  #define CONFIG_I2C_ENV_EEPROM_BUS	  1
 	  EEPROM which holds the environment, is reached over
 	  a pca9547 i2c mux with address 0x70, channel 3.
 - CONFIG_ENV_IS_IN_DATAFLASH:
 	Define this if you have a DataFlash memory device which you
 	want to use for the environment.
 	- CONFIG_ENV_OFFSET:
 	- CONFIG_ENV_ADDR:
 	- CONFIG_ENV_SIZE:
 	  These three #defines specify the offset and size of the
 	  environment area within the total memory of your DataFlash placed
 	  at the specified address.
 - CONFIG_ENV_IS_IN_REMOTE:
 	Define this if you have a remote memory space which you
 	want to use for the local device's environment.
 	- CONFIG_ENV_ADDR:
 	- CONFIG_ENV_SIZE:
 	  These two #defines specify the address and size of the
 	  environment area within the remote memory space. The
 	  local device can get the environment from remote memory
 	  space by SRIO or PCIE links.
 BE CAREFUL! For some special cases, the local device can not use
 "saveenv" command. For example, the local device will get the
 environment stored in a remote NOR flash by SRIO or PCIE link,
 but it can not erase, write this NOR flash by SRIO or PCIE interface.
 - CONFIG_ENV_IS_IN_NAND:
 	Define this if you have a NAND device which you want to use
 	for the environment.
 	- CONFIG_ENV_OFFSET:
 	- CONFIG_ENV_SIZE:
 	  These two #defines specify the offset and size of the environment
 	  area within the first NAND device.  CONFIG_ENV_OFFSET must be
 	  aligned to an erase block boundary.
 	- CONFIG_ENV_OFFSET_REDUND (optional):
 	  This setting describes a second storage area of CONFIG_ENV_SIZE
 	  size used to hold a redundant copy of the environment data, so
 	  that there is a valid backup copy in case there is a power failure
 	  during a "saveenv" operation.	 CONFIG_ENV_OFFSET_RENDUND must be
 	  aligned to an erase block boundary.
 	- CONFIG_ENV_RANGE (optional):
 	  Specifies the length of the region in which the environment
 	  can be written.  This should be a multiple of the NAND device's
 	  block size.  Specifying a range with more erase blocks than
 	  are needed to hold CONFIG_ENV_SIZE allows bad blocks within
 	  the range to be avoided.
 	- CONFIG_ENV_OFFSET_OOB (optional):
 	  Enables support for dynamically retrieving the offset of the
 	  environment from block zero's out-of-band data.  The
 	  "nand env.oob" command can be used to record this offset.
 	  Currently, CONFIG_ENV_OFFSET_REDUND is not supported when
 	  using CONFIG_ENV_OFFSET_OOB.
 - CONFIG_NAND_ENV_DST
 	Defines address in RAM to which the nand_spl code should copy the
 	environment. If redundant environment is used, it will be copied to
 	CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE.
 - CONFIG_ENV_IS_IN_UBI:
 	Define this if you have an UBI volume that you want to use for the
 	environment.  This has the benefit of wear-leveling the environment
 	accesses, which is important on NAND.
 	- CONFIG_ENV_UBI_PART:
 	  Define this to a string that is the mtd partition containing the UBI.
 	- CONFIG_ENV_UBI_VOLUME:
 	  Define this to the name of the volume that you want to store the
 	  environment in.
 	- CONFIG_ENV_UBI_VOLUME_REDUND:
 	  Define this to the name of another volume to store a second copy of
 	  the environment in.  This will enable redundant environments in UBI.
 	  It is assumed that both volumes are in the same MTD partition.
 	- CONFIG_UBI_SILENCE_MSG
 	- CONFIG_UBIFS_SILENCE_MSG
 	  You will probably want to define these to avoid a really noisy system
 	  when storing the env in UBI.
 - CONFIG_ENV_IS_IN_MMC:
 	Define this if you have an MMC device which you want to use for the
 	environment.
 	- CONFIG_SYS_MMC_ENV_DEV:
 	  Specifies which MMC device the environment is stored in.
 	- CONFIG_SYS_MMC_ENV_PART (optional):
 	  Specifies which MMC partition the environment is stored in. If not
 	  set, defaults to partition 0, the user area. Common values might be
 	  1 (first MMC boot partition), 2 (second MMC boot partition).
 	- CONFIG_ENV_OFFSET:
 	- CONFIG_ENV_SIZE:
 	  These two #defines specify the offset and size of the environment
 	  area within the specified MMC device.
 	  If offset is positive (the usual case), it is treated as relative to
 	  the start of the MMC partition. If offset is negative, it is treated
 	  as relative to the end of the MMC partition. This can be useful if
 	  your board may be fitted with different MMC devices, which have
 	  different sizes for the MMC partitions, and you always want the
 	  environment placed at the very end of the partition, to leave the
 	  maximum possible space before it, to store other data.
 	  These two values are in units of bytes, but must be aligned to an
 	  MMC sector boundary.
 	- CONFIG_ENV_OFFSET_REDUND (optional):
 	  Specifies a second storage area, of CONFIG_ENV_SIZE size, used to
 	  hold a redundant copy of the environment data. This provides a
 	  valid backup copy in case the other copy is corrupted, e.g. due
 	  to a power failure during a "saveenv" operation.
 	  This value may also be positive or negative; this is handled in the
 	  same way as CONFIG_ENV_OFFSET.
 	  This value is also in units of bytes, but must also be aligned to
 	  an MMC sector boundary.
 	- CONFIG_ENV_SIZE_REDUND (optional):
 	  This value need not be set, even when CONFIG_ENV_OFFSET_REDUND is
 	  set. If this value is set, it must be set to the same value as
 	  CONFIG_ENV_SIZE.
 - CONFIG_SYS_SPI_INIT_OFFSET
 	Defines offset to the initial SPI buffer area in DPRAM. The
 	area is used at an early stage (ROM part) if the environment
 	is configured to reside in the SPI EEPROM: We need a 520 byte
 	scratch DPRAM area. It is used between the two initialization
 	calls (spi_init_f() and spi_init_r()). A value of 0xB00 seems
 	to be a good choice since it makes it far enough from the
 	start of the data area as well as from the stack pointer.
 Please note that the environment is read-only until the monitor
 has been relocated to RAM and a RAM copy of the environment has been
 created; also, when using EEPROM you will have to use getenv_f()
 until then to read environment variables.
 The environment is protected by a CRC32 checksum. Before the monitor
 is relocated into RAM, as a result of a bad CRC you will be working
 with the compiled-in default environment - *silently*!!! [This is
 necessary, because the first environment variable we need is the
 "baudrate" setting for the console - if we have a bad CRC, we don't
 have any device yet where we could complain.]
 Note: once the monitor has been relocated, then it will complain if
 the default environment is used; a new CRC is computed as soon as you
 use the "saveenv" command to store a valid environment.
 - CONFIG_SYS_FAULT_ECHO_LINK_DOWN:
 		Echo the inverted Ethernet link state to the fault LED.
 		Note: If this option is active, then CONFIG_SYS_FAULT_MII_ADDR
 		      also needs to be defined.
 - CONFIG_SYS_FAULT_MII_ADDR:
 		MII address of the PHY to check for the Ethernet link state.
 - CONFIG_NS16550_MIN_FUNCTIONS:
 		Define this if you desire to only have use of the NS16550_init
 		and NS16550_putc functions for the serial driver located at
 		drivers/serial/ns16550.c.  This option is useful for saving
 		space for already greatly restricted images, including but not
 		limited to NAND_SPL configurations.
 - CONFIG_DISPLAY_BOARDINFO
 		Display information about the board that U-Boot is running on
 		when U-Boot starts up. The board function checkboard() is called
 		to do this.
 - CONFIG_DISPLAY_BOARDINFO_LATE
 		Similar to the previous option, but display this information
 		later, once stdio is running and output goes to the LCD, if
 		present.
 Low Level (hardware related) configuration options:
 ---------------------------------------------------
 - CONFIG_SYS_CACHELINE_SIZE:
 		Cache Line Size of the CPU.
 - CONFIG_SYS_DEFAULT_IMMR:
 		Default address of the IMMR after system reset.
 		Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
 		and RPXsuper) to be able to adjust the position of
 		the IMMR register after a reset.
 - CONFIG_SYS_CCSRBAR_DEFAULT:
 		Default (power-on reset) physical address of CCSR on Freescale
 		PowerPC SOCs.
 - CONFIG_SYS_CCSRBAR:
 		Virtual address of CCSR.  On a 32-bit build, this is typically
 		the same value as CONFIG_SYS_CCSRBAR_DEFAULT.
 		CONFIG_SYS_DEFAULT_IMMR must also be set to this value,
 		for cross-platform code that uses that macro instead.
 - CONFIG_SYS_CCSRBAR_PHYS:
 		Physical address of CCSR.  CCSR can be relocated to a new
 		physical address, if desired.  In this case, this macro should
 		be set to that address.	 Otherwise, it should be set to the
 		same value as CONFIG_SYS_CCSRBAR_DEFAULT.  For example, CCSR
 		is typically relocated on 36-bit builds.  It is recommended
 		that this macro be defined via the _HIGH and _LOW macros:
 		#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH
 			* 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW)
 - CONFIG_SYS_CCSRBAR_PHYS_HIGH:
 		Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS.	This value is typically
 		either 0 (32-bit build) or 0xF (36-bit build).	This macro is
 		used in assembly code, so it must not contain typecasts or
 		integer size suffixes (e.g. "ULL").
 - CONFIG_SYS_CCSRBAR_PHYS_LOW:
 		Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS.  This macro is
 		used in assembly code, so it must not contain typecasts or
 		integer size suffixes (e.g. "ULL").
 - CONFIG_SYS_CCSR_DO_NOT_RELOCATE:
 		If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be
 		forced to a value that ensures that CCSR is not relocated.
 - Floppy Disk Support:
 		CONFIG_SYS_FDC_DRIVE_NUMBER
 		the default drive number (default value 0)
 		CONFIG_SYS_ISA_IO_STRIDE
 		defines the spacing between FDC chipset registers
 		(default value 1)
 		CONFIG_SYS_ISA_IO_OFFSET
 		defines the offset of register from address. It
 		depends on which part of the data bus is connected to
 		the FDC chipset. (default value 0)
 		If CONFIG_SYS_ISA_IO_STRIDE CONFIG_SYS_ISA_IO_OFFSET and
 		CONFIG_SYS_FDC_DRIVE_NUMBER are undefined, they take their
 		default value.
 		if CONFIG_SYS_FDC_HW_INIT is defined, then the function
 		fdc_hw_init() is called at the beginning of the FDC
 		setup. fdc_hw_init() must be provided by the board
 		source code. It is used to make hardware dependant
 		initializations.
 - CONFIG_IDE_AHB:
 		Most IDE controllers were designed to be connected with PCI
 		interface. Only few of them were designed for AHB interface.
 		When software is doing ATA command and data transfer to
 		IDE devices through IDE-AHB controller, some additional
 		registers accessing to these kind of IDE-AHB controller
 		is requierd.
 - CONFIG_SYS_IMMR:	Physical address of the Internal Memory.
 		DO NOT CHANGE unless you know exactly what you're
 		doing! (11-4) [MPC8xx/82xx systems only]
 - CONFIG_SYS_INIT_RAM_ADDR:
 		Start address of memory area that can be used for
 		initial data and stack; please note that this must be
 		writable memory that is working WITHOUT special
 		initialization, i. e. you CANNOT use normal RAM which
 		will become available only after programming the
 		memory controller and running certain initialization
 		sequences.
 		U-Boot uses the following memory types:
 		- MPC8xx and MPC8260: IMMR (internal memory of the CPU)
 		- MPC824X: data cache
 		- PPC4xx:  data cache
 - CONFIG_SYS_GBL_DATA_OFFSET:
 		Offset of the initial data structure in the memory
 		area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
 		CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
 		data is located at the end of the available space
 		(sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
 		CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just
 		below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
 		CONFIG_SYS_GBL_DATA_OFFSET) downward.
 	Note:
 		On the MPC824X (or other systems that use the data
 		cache for initial memory) the address chosen for
 		CONFIG_SYS_INIT_RAM_ADDR is basically arbitrary - it must
 		point to an otherwise UNUSED address space between
 		the top of RAM and the start of the PCI space.
 - CONFIG_SYS_SIUMCR:	SIU Module Configuration (11-6)
 - CONFIG_SYS_SYPCR:	System Protection Control (11-9)
 - CONFIG_SYS_TBSCR:	Time Base Status and Control (11-26)
 - CONFIG_SYS_PISCR:	Periodic Interrupt Status and Control (11-31)
 - CONFIG_SYS_PLPRCR:	PLL, Low-Power, and Reset Control Register (15-30)
 - CONFIG_SYS_SCCR:	System Clock and reset Control Register (15-27)
 - CONFIG_SYS_OR_TIMING_SDRAM:
 		SDRAM timing
 - CONFIG_SYS_MAMR_PTA:
 		periodic timer for refresh
 - CONFIG_SYS_DER:	Debug Event Register (37-47)
 - FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
   CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
   CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
   CONFIG_SYS_BR1_PRELIM:
 		Memory Controller Definitions: BR0/1 and OR0/1 (FLASH)
 - SDRAM_BASE2_PRELIM, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE,
   CONFIG_SYS_OR_TIMING_SDRAM, CONFIG_SYS_OR2_PRELIM, CONFIG_SYS_BR2_PRELIM,
   CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
 		Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
 - CONFIG_SYS_MAMR_PTA, CONFIG_SYS_MPTPR_2BK_4K, CONFIG_SYS_MPTPR_1BK_4K, CONFIG_SYS_MPTPR_2BK_8K,
   CONFIG_SYS_MPTPR_1BK_8K, CONFIG_SYS_MAMR_8COL, CONFIG_SYS_MAMR_9COL:
 		Machine Mode Register and Memory Periodic Timer
 		Prescaler definitions (SDRAM timing)
 - CONFIG_SYS_I2C_UCODE_PATCH, CONFIG_SYS_I2C_DPMEM_OFFSET [0x1FC0]:
 		enable I2C microcode relocation patch (MPC8xx);
 		define relocation offset in DPRAM [DSP2]
 - CONFIG_SYS_SMC_UCODE_PATCH, CONFIG_SYS_SMC_DPMEM_OFFSET [0x1FC0]:
 		enable SMC microcode relocation patch (MPC8xx);
 		define relocation offset in DPRAM [SMC1]
 - CONFIG_SYS_SPI_UCODE_PATCH, CONFIG_SYS_SPI_DPMEM_OFFSET [0x1FC0]:
 		enable SPI microcode relocation patch (MPC8xx);
 		define relocation offset in DPRAM [SCC4]
 - CONFIG_SYS_USE_OSCCLK:
 		Use OSCM clock mode on MBX8xx board. Be careful,
 		wrong setting might damage your board. Read
 		doc/README.MBX before setting this variable!
 - CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only)
 		Offset of the bootmode word in DPRAM used by post
 		(Power On Self Tests). This definition overrides
 		#define'd default value in commproc.h resp.
 		cpm_8260.h.
 - CONFIG_SYS_PCI_SLV_MEM_LOCAL, CONFIG_SYS_PCI_SLV_MEM_BUS, CONFIG_SYS_PICMR0_MASK_ATTRIB,
   CONFIG_SYS_PCI_MSTR0_LOCAL, CONFIG_SYS_PCIMSK0_MASK, CONFIG_SYS_PCI_MSTR1_LOCAL,
   CONFIG_SYS_PCIMSK1_MASK, CONFIG_SYS_PCI_MSTR_MEM_LOCAL, CONFIG_SYS_PCI_MSTR_MEM_BUS,
   CONFIG_SYS_CPU_PCI_MEM_START, CONFIG_SYS_PCI_MSTR_MEM_SIZE, CONFIG_SYS_POCMR0_MASK_ATTRIB,
   CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL, CONFIG_SYS_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START,
   CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL,
   CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE,
   CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
 		Overrides the default PCI memory map in arch/powerpc/cpu/mpc8260/pci.c if set.
 - CONFIG_PCI_DISABLE_PCIE:
 		Disable PCI-Express on systems where it is supported but not
 		required.
 - CONFIG_PCI_ENUM_ONLY
 		Only scan through and get the devices on the busses.
 		Don't do any setup work, presumably because someone or
 		something has already done it, and we don't need to do it
 		a second time.	Useful for platforms that are pre-booted
 		by coreboot or similar.
 - CONFIG_PCI_INDIRECT_BRIDGE:
 		Enable support for indirect PCI bridges.
 - CONFIG_SYS_SRIO:
 		Chip has SRIO or not
 - CONFIG_SRIO1:
 		Board has SRIO 1 port available
 - CONFIG_SRIO2:
 		Board has SRIO 2 port available
 - CONFIG_SRIO_PCIE_BOOT_MASTER
 		Board can support master function for Boot from SRIO and PCIE
 - CONFIG_SYS_SRIOn_MEM_VIRT:
 		Virtual Address of SRIO port 'n' memory region
 - CONFIG_SYS_SRIOn_MEM_PHYS:
 		Physical Address of SRIO port 'n' memory region
 - CONFIG_SYS_SRIOn_MEM_SIZE:
 		Size of SRIO port 'n' memory region
 - CONFIG_SYS_NAND_BUSWIDTH_16BIT
 		Defined to tell the NAND controller that the NAND chip is using
 		a 16 bit bus.
 		Not all NAND drivers use this symbol.
 		Example of drivers that use it:
 		- drivers/mtd/nand/ndfc.c
 		- drivers/mtd/nand/mxc_nand.c
 - CONFIG_SYS_NDFC_EBC0_CFG
 		Sets the EBC0_CFG register for the NDFC. If not defined
 		a default value will be used.
 - CONFIG_SPD_EEPROM
 		Get DDR timing information from an I2C EEPROM. Common
 		with pluggable memory modules such as SODIMMs
   SPD_EEPROM_ADDRESS
 		I2C address of the SPD EEPROM
 - CONFIG_SYS_SPD_BUS_NUM
 		If SPD EEPROM is on an I2C bus other than the first
 		one, specify here. Note that the value must resolve
 		to something your driver can deal with.
 - CONFIG_SYS_DDR_RAW_TIMING
 		Get DDR timing information from other than SPD. Common with
 		soldered DDR chips onboard without SPD. DDR raw timing
 		parameters are extracted from datasheet and hard-coded into
 		header files or board specific files.
 - CONFIG_FSL_DDR_INTERACTIVE
 		Enable interactive DDR debugging. See doc/README.fsl-ddr.
 - CONFIG_SYS_83XX_DDR_USES_CS0
 		Only for 83xx systems. If specified, then DDR should
 		be configured using CS0 and CS1 instead of CS2 and CS3.
 - CONFIG_ETHER_ON_FEC[12]
 		Define to enable FEC[12] on a 8xx series processor.
 - CONFIG_FEC[12]_PHY
 		Define to the hardcoded PHY address which corresponds
 		to the given FEC; i. e.
 			#define CONFIG_FEC1_PHY 4
 		means that the PHY with address 4 is connected to FEC1
 		When set to -1, means to probe for first available.
 - CONFIG_FEC[12]_PHY_NORXERR
 		The PHY does not have a RXERR line (RMII only).
 		(so program the FEC to ignore it).
 - CONFIG_RMII
 		Enable RMII mode for all FECs.
 		Note that this is a global option, we can't
 		have one FEC in standard MII mode and another in RMII mode.
 - CONFIG_CRC32_VERIFY
 		Add a verify option to the crc32 command.
 		The syntax is:
 		=> crc32 -v <address> <count> <crc32>
 		Where address/count indicate a memory area
 		and crc32 is the correct crc32 which the
 		area should have.
 - CONFIG_LOOPW
 		Add the "loopw" memory command. This only takes effect if
 		the memory commands are activated globally (CONFIG_CMD_MEM).
 - CONFIG_MX_CYCLIC
 		Add the "mdc" and "mwc" memory commands. These are cyclic
 		"md/mw" commands.
 		Examples:
 		=> mdc.b 10 4 500
 		This command will print 4 bytes (10,11,12,13) each 500 ms.
 		=> mwc.l 100 12345678 10
 		This command will write 12345678 to address 100 all 10 ms.
 		This only takes effect if the memory commands are activated
 		globally (CONFIG_CMD_MEM).
 - CONFIG_SKIP_LOWLEVEL_INIT
 		[ARM, NDS32, MIPS only] If this variable is defined, then certain
 		low level initializations (like setting up the memory
 		controller) are omitted and/or U-Boot does not
 		relocate itself into RAM.
 		Normally this variable MUST NOT be defined. The only
 		exception is when U-Boot is loaded (to RAM) by some
 		other boot loader or by a debugger which performs
 		these initializations itself.
 - CONFIG_SPL_BUILD
 		Modifies the behaviour of start.S when compiling a loader
 		that is executed before the actual U-Boot. E.g. when
 		compiling a NAND SPL.
 - CONFIG_TPL_BUILD
 		Modifies the behaviour of start.S  when compiling a loader
 		that is executed after the SPL and before the actual U-Boot.
 		It is loaded by the SPL.
 - CONFIG_SYS_MPC85XX_NO_RESETVEC
 		Only for 85xx systems. If this variable is specified, the section
 		.resetvec is not kept and the section .bootpg is placed in the
 		previous 4k of the .text section.
 - CONFIG_ARCH_MAP_SYSMEM
 		Generally U-Boot (and in particular the md command) uses
 		effective address. It is therefore not necessary to regard
 		U-Boot address as virtual addresses that need to be translated
 		to physical addresses. However, sandbox requires this, since
 		it maintains its own little RAM buffer which contains all
 		addressable memory. This option causes some memory accesses
 		to be mapped through map_sysmem() / unmap_sysmem().
 - CONFIG_USE_ARCH_MEMCPY
   CONFIG_USE_ARCH_MEMSET
 		If these options are used a optimized version of memcpy/memset will
 		be used if available. These functions may be faster under some
 		conditions but may increase the binary size.
 - CONFIG_X86_RESET_VECTOR
 		If defined, the x86 reset vector code is included. This is not
 		needed when U-Boot is running from Coreboot.
 - CONFIG_SYS_MPUCLK
 		Defines the MPU clock speed (in MHz).
 		NOTE : currently only supported on AM335x platforms.
 - CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC:
 		Enables the RTC32K OSC on AM33xx based plattforms
 Freescale QE/FMAN Firmware Support:
 -----------------------------------
 The Freescale QUICCEngine (QE) and Frame Manager (FMAN) both support the
 loading of "firmware", which is encoded in the QE firmware binary format.
 This firmware often needs to be loaded during U-Boot booting, so macros
 are used to identify the storage device (NOR flash, SPI, etc) and the address
 within that device.
 - CONFIG_SYS_QE_FMAN_FW_ADDR
 	The address in the storage device where the firmware is located.  The
 	meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
 	is also specified.
 - CONFIG_SYS_QE_FMAN_FW_LENGTH
 	The maximum possible size of the firmware.  The firmware binary format
 	has a field that specifies the actual size of the firmware, but it
 	might not be possible to read any part of the firmware unless some
 	local storage is allocated to hold the entire firmware first.
 - CONFIG_SYS_QE_FMAN_FW_IN_NOR
 	Specifies that QE/FMAN firmware is located in NOR flash, mapped as
 	normal addressable memory via the LBC.  CONFIG_SYS_FMAN_FW_ADDR is the
 	virtual address in NOR flash.
 - CONFIG_SYS_QE_FMAN_FW_IN_NAND
 	Specifies that QE/FMAN firmware is located in NAND flash.
 	CONFIG_SYS_FMAN_FW_ADDR is the offset within NAND flash.
 - CONFIG_SYS_QE_FMAN_FW_IN_MMC
 	Specifies that QE/FMAN firmware is located on the primary SD/MMC
 	device.  CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
 - CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH
 	Specifies that QE/FMAN firmware is located on the primary SPI
 	device.  CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
 - CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 	Specifies that QE/FMAN firmware is located in the remote (master)
 	memory space.	CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
 	can be mapped from slave TLB->slave LAW->slave SRIO or PCIE outbound
 	window->master inbound window->master LAW->the ucode address in
 	master's memory space.
 Building the Software:
 ======================
 Building U-Boot has been tested in several native build environments
 and in many different cross environments. Of course we cannot support
 all possibly existing versions of cross development tools in all
 (potentially obsolete) versions. In case of tool chain problems we
 recommend to use the ELDK (see http://www.denx.de/wiki/DULG/ELDK)
 which is extensively used to build and test U-Boot.
 If you are not using a native environment, it is assumed that you
 have GNU cross compiling tools available in your path. In this case,
 you must set the environment variable CROSS_COMPILE in your shell.
 Note that no changes to the Makefile or any other source files are
 necessary. For example using the ELDK on a 4xx CPU, please enter:
 	$ CROSS_COMPILE=ppc_4xx-
 	$ export CROSS_COMPILE
 Note: If you wish to generate Windows versions of the utilities in
       the tools directory you can use the MinGW toolchain
       (http://www.mingw.org).  Set your HOST tools to the MinGW
       toolchain and execute 'make tools'.  For example:
        $ make HOSTCC=i586-mingw32msvc-gcc HOSTSTRIP=i586-mingw32msvc-strip tools
       Binaries such as tools/mkimage.exe will be created which can
       be executed on computers running Windows.
 U-Boot is intended to be simple to build. After installing the
 sources you must configure U-Boot for one specific board type. This
 is done by typing:
 	make NAME_config
 where "NAME_config" is the name of one of the existing configu-
 rations; see boards.cfg for supported names.
 Note: for some board special configuration names may exist; check if
       additional information is available from the board vendor; for
       instance, the TQM823L systems are available without (standard)
       or with LCD support. You can select such additional "features"
       when choosing the configuration, i. e.
       make TQM823L_config
 	- will configure for a plain TQM823L, i. e. no LCD support
       make TQM823L_LCD_config
 	- will configure for a TQM823L with U-Boot console on LCD
       etc.
 Finally, type "make all", and you should get some working U-Boot
 images ready for download to / installation on your system:
 - "u-boot.bin" is a raw binary image
 - "u-boot" is an image in ELF binary format
 - "u-boot.srec" is in Motorola S-Record format
 By default the build is performed locally and the objects are saved
 in the source directory. One of the two methods can be used to change
 this behavior and build U-Boot to some external directory:
 1. Add O= to the make command line invocations:
 	make O=/tmp/build distclean
 	make O=/tmp/build NAME_config
 	make O=/tmp/build all
 2. Set environment variable BUILD_DIR to point to the desired location:
 	export BUILD_DIR=/tmp/build
 	make distclean
 	make NAME_config
 	make all
 Note that the command line "O=" setting overrides the BUILD_DIR environment
 variable.
 Please be aware that the Makefiles assume you are using GNU make, so
 for instance on NetBSD you might need to use "gmake" instead of
 native "make".
 If the system board that you have is not listed, then you will need
 to port U-Boot to your hardware platform. To do this, follow these
 steps:
 1.  Add a new configuration option for your board to the toplevel
     "boards.cfg" file, using the existing entries as examples.
     Follow the instructions there to keep the boards in order.
 2.  Create a new directory to hold your board specific code. Add any
     files you need. In your board directory, you will need at least
     the "Makefile", a "<board>.c", "flash.c" and "u-boot.lds".
 3.  Create a new configuration file "include/configs/<board>.h" for
     your board
 3.  If you're porting U-Boot to a new CPU, then also create a new
     directory to hold your CPU specific code. Add any files you need.
 4.  Run "make <board>_config" with your new name.
 5.  Type "make", and you should get a working "u-boot.srec" file
     to be installed on your target system.
 6.  Debug and solve any problems that might arise.
     [Of course, this last step is much harder than it sounds.]
 Testing of U-Boot Modifications, Ports to New Hardware, etc.:
 ==============================================================
 If you have modified U-Boot sources (for instance added a new board
 or support for new devices, a new CPU, etc.) you are expected to
 provide feedback to the other developers. The feedback normally takes
 the form of a "patch", i. e. a context diff against a certain (latest
 official or latest in the git repository) version of U-Boot sources.
 But before you submit such a patch, please verify that your modifi-
 cation did not break existing code. At least make sure that *ALL* of
 the supported boards compile WITHOUT ANY compiler warnings. To do so,
 just run the "MAKEALL" script, which will configure and build U-Boot
 for ALL supported system. Be warned, this will take a while. You can
 select which (cross) compiler to use by passing a `CROSS_COMPILE'
 environment variable to the script, i. e. to use the ELDK cross tools
 you can type
 	CROSS_COMPILE=ppc_8xx- MAKEALL
 or to build on a native PowerPC system you can type
 	CROSS_COMPILE=' ' MAKEALL
 When using the MAKEALL script, the default behaviour is to build
 U-Boot in the source directory. This location can be changed by
 setting the BUILD_DIR environment variable. Also, for each target
 built, the MAKEALL script saves two log files (<target>.ERR and
 <target>.MAKEALL) in the <source dir>/LOG directory. This default
 location can be changed by setting the MAKEALL_LOGDIR environment
 variable. For example:
 	export BUILD_DIR=/tmp/build
 	export MAKEALL_LOGDIR=/tmp/log
 	CROSS_COMPILE=ppc_8xx- MAKEALL
 With the above settings build objects are saved in the /tmp/build,
 log files are saved in the /tmp/log and the source tree remains clean
 during the whole build process.
 See also "U-Boot Porting Guide" below.
 Monitor Commands - Overview:
 ============================
 go	- start application at address 'addr'
 run	- run commands in an environment variable
 bootm	- boot application image from memory
 bootp	- boot image via network using BootP/TFTP protocol
 bootz   - boot zImage from memory
 tftpboot- boot image via network using TFTP protocol
 	       and env variables "ipaddr" and "serverip"
 	       (and eventually "gatewayip")
 tftpput - upload a file via network using TFTP protocol
 rarpboot- boot image via network using RARP/TFTP protocol
 diskboot- boot from IDE devicebootd   - boot default, i.e., run 'bootcmd'
 loads	- load S-Record file over serial line
 loadb	- load binary file over serial line (kermit mode)
 md	- memory display
 mm	- memory modify (auto-incrementing)
 nm	- memory modify (constant address)
 mw	- memory write (fill)
 cp	- memory copy
 cmp	- memory compare
 crc32	- checksum calculation
 i2c	- I2C sub-system
 sspi	- SPI utility commands
 base	- print or set address offset
 printenv- print environment variables
 setenv	- set environment variables
 saveenv - save environment variables to persistent storage
 protect - enable or disable FLASH write protection
 erase	- erase FLASH memory
 flinfo	- print FLASH memory information
 nand	- NAND memory operations (see doc/README.nand)
 bdinfo	- print Board Info structure
 iminfo	- print header information for application image
 coninfo - print console devices and informations
 ide	- IDE sub-system
 loop	- infinite loop on address range
 loopw	- infinite write loop on address range
 mtest	- simple RAM test
 icache	- enable or disable instruction cache
 dcache	- enable or disable data cache
 reset	- Perform RESET of the CPU
 echo	- echo args to console
 version - print monitor version
 help	- print online help
 ?	- alias for 'help'
 Monitor Commands - Detailed Description:
 ========================================
 TODO.
 For now: just type "help <command>".
 Environment Variables:
 ======================
 U-Boot supports user configuration using Environment Variables which
 can be made persistent by saving to Flash memory.
 Environment Variables are set using "setenv", printed using
 "printenv", and saved to Flash using "saveenv". Using "setenv"
 without a value can be used to delete a variable from the
 environment. As long as you don't save the environment you are
 working with an in-memory copy. In case the Flash area containing the
 environment is erased by accident, a default environment is provided.
 Some configuration options can be set using Environment Variables.
 List of environment variables (most likely not complete):
   baudrate	- see CONFIG_BAUDRATE
   bootdelay	- see CONFIG_BOOTDELAY
   bootcmd	- see CONFIG_BOOTCOMMAND
   bootargs	- Boot arguments when booting an RTOS image
   bootfile	- Name of the image to load with TFTP
   bootm_low	- Memory range available for image processing in the bootm
 		  command can be restricted. This variable is given as
 		  a hexadecimal number and defines lowest address allowed
 		  for use by the bootm command. See also "bootm_size"
 		  environment variable. Address defined by "bootm_low" is
 		  also the base of the initial memory mapping for the Linux
 		  kernel -- see the description of CONFIG_SYS_BOOTMAPSZ and
 		  bootm_mapsize.
   bootm_mapsize - Size of the initial memory mapping for the Linux kernel.
 		  This variable is given as a hexadecimal number and it
 		  defines the size of the memory region starting at base
 		  address bootm_low that is accessible by the Linux kernel
 		  during early boot.  If unset, CONFIG_SYS_BOOTMAPSZ is used
 		  as the default value if it is defined, and bootm_size is
 		  used otherwise.
   bootm_size	- Memory range available for image processing in the bootm
 		  command can be restricted. This variable is given as
 		  a hexadecimal number and defines the size of the region
 		  allowed for use by the bootm command. See also "bootm_low"
 		  environment variable.
   updatefile	- Location of the software update file on a TFTP server, used
 		  by the automatic software update feature. Please refer to
 		  documentation in doc/README.update for more details.
   autoload	- if set to "no" (any string beginning with 'n'),
 		  "bootp" will just load perform a lookup of the
 		  configuration from the BOOTP server, but not try to
 		  load any image using TFTP
   autostart	- if set to "yes", an image loaded using the "bootp",
 		  "rarpboot", "tftpboot" or "diskboot" commands will
 		  be automatically started (by internally calling
 		  "bootm")
 		  If set to "no", a standalone image passed to the
 		  "bootm" command will be copied to the load address
 		  (and eventually uncompressed), but NOT be started.
 		  This can be used to load and uncompress arbitrary
 		  data.
   fdt_high	- if set this restricts the maximum address that the
 		  flattened device tree will be copied into upon boot.
 		  For example, if you have a system with 1 GB memory
 		  at physical address 0x10000000, while Linux kernel
 		  only recognizes the first 704 MB as low memory, you
 		  may need to set fdt_high as 0x3C000000 to have the
 		  device tree blob be copied to the maximum address
 		  of the 704 MB low memory, so that Linux kernel can
 		  access it during the boot procedure.
 		  If this is set to the special value 0xFFFFFFFF then
 		  the fdt will not be copied at all on boot.  For this
 		  to work it must reside in writable memory, have
 		  sufficient padding on the end of it for u-boot to
 		  add the information it needs into it, and the memory
 		  must be accessible by the kernel.
   fdtcontroladdr- if set this is the address of the control flattened
 		  device tree used by U-Boot when CONFIG_OF_CONTROL is
 		  defined.
   i2cfast	- (PPC405GP|PPC405EP only)
 		  if set to 'y' configures Linux I2C driver for fast
 		  mode (400kHZ). This environment variable is used in
 		  initialization code. So, for changes to be effective
 		  it must be saved and board must be reset.
   initrd_high	- restrict positioning of initrd images:
 		  If this variable is not set, initrd images will be
 		  copied to the highest possible address in RAM; this
 		  is usually what you want since it allows for
 		  maximum initrd size. If for some reason you want to
 		  make sure that the initrd image is loaded below the
 		  CONFIG_SYS_BOOTMAPSZ limit, you can set this environment
 		  variable to a value of "no" or "off" or "0".
 		  Alternatively, you can set it to a maximum upper
 		  address to use (U-Boot will still check that it
 		  does not overwrite the U-Boot stack and data).
 		  For instance, when you have a system with 16 MB
 		  RAM, and want to reserve 4 MB from use by Linux,
 		  you can do this by adding "mem=12M" to the value of
 		  the "bootargs" variable. However, now you must make
 		  sure that the initrd image is placed in the first
 		  12 MB as well - this can be done with
 		  setenv initrd_high 00c00000
 		  If you set initrd_high to 0xFFFFFFFF, this is an
 		  indication to U-Boot that all addresses are legal
 		  for the Linux kernel, including addresses in flash
 		  memory. In this case U-Boot will NOT COPY the
 		  ramdisk at all. This may be useful to reduce the
 		  boot time on your system, but requires that this
 		  feature is supported by your Linux kernel.
   ipaddr	- IP address; needed for tftpboot command
   loadaddr	- Default load address for commands like "bootp",
 		  "rarpboot", "tftpboot", "loadb" or "diskboot"
   loads_echo	- see CONFIG_LOADS_ECHO
   serverip	- TFTP server IP address; needed for tftpboot command
   bootretry	- see CONFIG_BOOT_RETRY_TIME
   bootdelaykey	- see CONFIG_AUTOBOOT_DELAY_STR
   bootstopkey	- see CONFIG_AUTOBOOT_STOP_STR
   ethprime	- controls which interface is used first.
   ethact	- controls which interface is currently active.
 		  For example you can do the following
 		  => setenv ethact FEC
 		  => ping 192.168.0.1 # traffic sent on FEC
 		  => setenv ethact SCC
 		  => ping 10.0.0.1 # traffic sent on SCC
   ethrotate	- When set to "no" U-Boot does not go through all
 		  available network interfaces.
 		  It just stays at the currently selected interface.
   netretry	- When set to "no" each network operation will
 		  either succeed or fail without retrying.
 		  When set to "once" the network operation will
 		  fail when all the available network interfaces
 		  are tried once without success.
 		  Useful on scripts which control the retry operation
 		  themselves.
   npe_ucode	- set load address for the NPE microcode
   silent_linux  - If set then linux will be told to boot silently, by
 		  changing the console to be empty. If "yes" it will be
 		  made silent. If "no" it will not be made silent. If
 		  unset, then it will be made silent if the U-Boot console
 		  is silent.
   tftpsrcport	- If this is set, the value is used for TFTP's
 		  UDP source port.
   tftpdstport	- If this is set, the value is used for TFTP's UDP
 		  destination port instead of the Well Know Port 69.
   tftpblocksize - Block size to use for TFTP transfers; if not set,
 		  we use the TFTP server's default block size
   tftptimeout	- Retransmission timeout for TFTP packets (in milli-
 		  seconds, minimum value is 1000 = 1 second). Defines
 		  when a packet is considered to be lost so it has to
 		  be retransmitted. The default is 5000 = 5 seconds.
 		  Lowering this value may make downloads succeed
 		  faster in networks with high packet loss rates or
 		  with unreliable TFTP servers.
   vlan		- When set to a value < 4095 the traffic over
 		  Ethernet is encapsulated/received over 802.1q
 		  VLAN tagged frames.
 The following image location variables contain the location of images
 used in booting. The "Image" column gives the role of the image and is
 not an environment variable name. The other columns are environment
 variable names. "File Name" gives the name of the file on a TFTP
 server, "RAM Address" gives the location in RAM the image will be
 loaded to, and "Flash Location" gives the image's address in NOR
 flash or offset in NAND flash.
 *Note* - these variables don't have to be defined for all boards, some
 boards currenlty use other variables for these purposes, and some
 boards use these variables for other purposes.
 Image		    File Name	     RAM Address       Flash Location
 -----		    ---------	     -----------       --------------
 u-boot		    u-boot	     u-boot_addr_r     u-boot_addr
 Linux kernel	    bootfile	     kernel_addr_r     kernel_addr
 device tree blob    fdtfile	     fdt_addr_r	       fdt_addr
 ramdisk		    ramdiskfile	     ramdisk_addr_r    ramdisk_addr
 The following environment variables may be used and automatically
 updated by the network boot commands ("bootp" and "rarpboot"),
 depending the information provided by your boot server:
   bootfile	- see above
   dnsip		- IP address of your Domain Name Server
   dnsip2	- IP address of your secondary Domain Name Server
   gatewayip	- IP address of the Gateway (Router) to use
   hostname	- Target hostname
   ipaddr	- see above
   netmask	- Subnet Mask
   rootpath	- Pathname of the root filesystem on the NFS server
   serverip	- see above
 There are two special Environment Variables:
   serial#	- contains hardware identification information such
 		  as type string and/or serial number
   ethaddr	- Ethernet address
 These variables can be set only once (usually during manufacturing of
 the board). U-Boot refuses to delete or overwrite these variables
 once they have been set once.
 Further special Environment Variables:
   ver		- Contains the U-Boot version string as printed
 		  with the "version" command. This variable is
 		  readonly (see CONFIG_VERSION_VARIABLE).
 Please note that changes to some configuration parameters may take
 only effect after the next boot (yes, that's just like Windoze :-).
 Callback functions for environment variables:
 ---------------------------------------------
 For some environment variables, the behavior of u-boot needs to change
 when their values are changed.  This functionailty allows functions to
 be associated with arbitrary variables.  On creation, overwrite, or
 deletion, the callback will provide the opportunity for some side
 effect to happen or for the change to be rejected.
 The callbacks are named and associated with a function using the
 U_BOOT_ENV_CALLBACK macro in your board or driver code.
 These callbacks are associated with variables in one of two ways.  The
 static list can be added to by defining CONFIG_ENV_CALLBACK_LIST_STATIC
 in the board configuration to a string that defines a list of
 associations.  The list must be in the following format:
 	entry = variable_name[:callback_name]
 	list = entry[,list]
 If the callback name is not specified, then the callback is deleted.
 Spaces are also allowed anywhere in the list.
 Callbacks can also be associated by defining the ".callbacks" variable
 with the same list format above.  Any association in ".callbacks" will
 override any association in the static list. You can define
 CONFIG_ENV_CALLBACK_LIST_DEFAULT to a list (string) to define the
 ".callbacks" envirnoment variable in the default or embedded environment.
 Command Line Parsing:
 =====================
 There are two different command line parsers available with U-Boot:
 the old "simple" one, and the much more powerful "hush" shell:
 Old, simple command line parser:
 --------------------------------
 - supports environment variables (through setenv / saveenv commands)
 - several commands on one line, separated by ';'
 - variable substitution using "... ${name} ..." syntax
 - special characters ('$', ';') can be escaped by prefixing with '\',
   for example:
 	setenv bootcmd bootm \${address}
 - You can also escape text by enclosing in single apostrophes, for example:
 	setenv addip 'setenv bootargs $bootargs ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off'
 Hush shell:
 -----------
 - similar to Bourne shell, with control structures like
   if...then...else...fi, for...do...done; while...do...done,
   until...do...done, ...
 - supports environment ("global") variables (through setenv / saveenv
   commands) and local shell variables (through standard shell syntax
   "name=value"); only environment variables can be used with "run"
   command
 General rules:
 --------------
 (1) If a command line (or an environment variable executed by a "run"
     command) contains several commands separated by semicolon, and
     one of these commands fails, then the remaining commands will be
     executed anyway.
 (2) If you execute several variables with one call to run (i. e.
     calling run with a list of variables as arguments), any failing
     command will cause "run" to terminate, i. e. the remaining
     variables are not executed.
 Note for Redundant Ethernet Interfaces:
 =======================================
 Some boards come with redundant Ethernet interfaces; U-Boot supports
 such configurations and is capable of automatic selection of a
 "working" interface when needed. MAC assignment works as follows:
 Network interfaces are numbered eth0, eth1, eth2, ... Corresponding
 MAC addresses can be stored in the environment as "ethaddr" (=>eth0),
 "eth1addr" (=>eth1), "eth2addr", ...
 If the network interface stores some valid MAC address (for instance
 in SROM), this is used as default address if there is NO correspon-
 ding setting in the environment; if the corresponding environment
 variable is set, this overrides the settings in the card; that means:
 o If the SROM has a valid MAC address, and there is no address in the
   environment, the SROM's address is used.
 o If there is no valid address in the SROM, and a definition in the
   environment exists, then the value from the environment variable is
   used.
 o If both the SROM and the environment contain a MAC address, and
   both addresses are the same, this MAC address is used.
 o If both the SROM and the environment contain a MAC address, and the
   addresses differ, the value from the environment is used and a
   warning is printed.
 o If neither SROM nor the environment contain a MAC address, an error
   is raised.
 If Ethernet drivers implement the 'write_hwaddr' function, valid MAC addresses
 will be programmed into hardware as part of the initialization process.	 This
 may be skipped by setting the appropriate 'ethmacskip' environment variable.
 The naming convention is as follows:
 "ethmacskip" (=>eth0), "eth1macskip" (=>eth1) etc.
 Image Formats:
 ==============
 U-Boot is capable of booting (and performing other auxiliary operations on)
 images in two formats:
 New uImage format (FIT)
 -----------------------
 Flexible and powerful format based on Flattened Image Tree -- FIT (similar
 to Flattened Device Tree). It allows the use of images with multiple
 components (several kernels, ramdisks, etc.), with contents protected by
 SHA1, MD5 or CRC32. More details are found in the doc/uImage.FIT directory.
 Old uImage format
 -----------------
 Old image format is based on binary files which can be basically anything,
 preceded by a special header; see the definitions in include/image.h for
 details; basically, the header defines the following image properties:
 * Target Operating System (Provisions for OpenBSD, NetBSD, FreeBSD,
   4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks,
   LynxOS, pSOS, QNX, RTEMS, INTEGRITY;
   Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
   INTEGRITY).
 * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
   IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
   Currently supported: ARM, AVR32, Intel x86, MIPS, NDS32, Nios II, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point
 * Image Name
 * Image Timestamp
 The header is marked by a special Magic Number, and both the header
 and the data portions of the image are secured against corruption by
 CRC32 checksums.
 Linux Support:
 ==============
 Although U-Boot should support any OS or standalone application
 easily, the main focus has always been on Linux during the design of
 U-Boot.
 U-Boot includes many features that so far have been part of some
 special "boot loader" code within the Linux kernel. Also, any
 "initrd" images to be used are no longer part of one big Linux image;
 instead, kernel and "initrd" are separate images. This implementation
 serves several purposes:
 - the same features can be used for other OS or standalone
   applications (for instance: using compressed images to reduce the
   Flash memory footprint)
 - it becomes much easier to port new Linux kernel versions because
   lots of low-level, hardware dependent stuff are done by U-Boot
 - the same Linux kernel image can now be used with different "initrd"
   images; of course this also means that different kernel images can
   be run with the same "initrd". This makes testing easier (you don't
   have to build a new "zImage.initrd" Linux image when you just
   change a file in your "initrd"). Also, a field-upgrade of the
   software is easier now.
 Linux HOWTO:
 ============
 Porting Linux to U-Boot based systems:
 ---------------------------------------
 U-Boot cannot save you from doing all the necessary modifications to
 configure the Linux device drivers for use with your target hardware
 (no, we don't intend to provide a full virtual machine interface to
 Linux :-).
 But now you can ignore ALL boot loader code (in arch/powerpc/mbxboot).
 Just make sure your machine specific header file (for instance
 include/asm-ppc/tqm8xx.h) includes the same definition of the Board
 Information structure as we define in include/asm-<arch>/u-boot.h,
 and make sure that your definition of IMAP_ADDR uses the same value
 as your U-Boot configuration in CONFIG_SYS_IMMR.
 Configuring the Linux kernel:
 -----------------------------
 No specific requirements for U-Boot. Make sure you have some root
 device (initial ramdisk, NFS) for your target system.
 Building a Linux Image:
 -----------------------
 With U-Boot, "normal" build targets like "zImage" or "bzImage" are
 not used. If you use recent kernel source, a new build target
 "uImage" will exist which automatically builds an image usable by
 U-Boot. Most older kernels also have support for a "pImage" target,
 which was introduced for our predecessor project PPCBoot and uses a
 100% compatible format.
 Example:
 	make TQM850L_config
 	make oldconfig
 	make dep
 	make uImage
 The "uImage" build target uses a special tool (in 'tools/mkimage') to
 encapsulate a compressed Linux kernel image with header	 information,
 CRC32 checksum etc. for use with U-Boot. This is what we are doing:
 * build a standard "vmlinux" kernel image (in ELF binary format):
 * convert the kernel into a raw binary image:
 	${CROSS_COMPILE}-objcopy -O binary \
 				 -R .note -R .comment \
 				 -S vmlinux linux.bin
 * compress the binary image:
 	gzip -9 linux.bin
 * package compressed binary image for U-Boot:
 	mkimage -A ppc -O linux -T kernel -C gzip \
 		-a 0 -e 0 -n "Linux Kernel Image" \
 		-d linux.bin.gz uImage
 The "mkimage" tool can also be used to create ramdisk images for use
 with U-Boot, either separated from the Linux kernel image, or
 combined into one file. "mkimage" encapsulates the images with a 64
 byte header containing information about target architecture,
 operating system, image type, compression method, entry points, time
 stamp, CRC32 checksums, etc.
 "mkimage" can be called in two ways: to verify existing images and
 print the header information, or to build new images.
 In the first form (with "-l" option) mkimage lists the information
 contained in the header of an existing U-Boot image; this includes
 checksum verification:
 	tools/mkimage -l image
 	  -l ==> list image header information
 The second form (with "-d" option) is used to build a U-Boot image
 from a "data file" which is used as image payload:
 	tools/mkimage -A arch -O os -T type -C comp -a addr -e ep \
 		      -n name -d data_file image
 	  -A ==> set architecture to 'arch'
 	  -O ==> set operating system to 'os'
 	  -T ==> set image type to 'type'
 	  -C ==> set compression type 'comp'
 	  -a ==> set load address to 'addr' (hex)
 	  -e ==> set entry point to 'ep' (hex)
 	  -n ==> set image name to 'name'
 	  -d ==> use image data from 'datafile'
 Right now, all Linux kernels for PowerPC systems use the same load
 address (0x00000000), but the entry point address depends on the
 kernel version:
 - 2.2.x kernels have the entry point at 0x0000000C,
 - 2.3.x and later kernels have the entry point at 0x00000000.
 So a typical call to build a U-Boot image would read:
 	-> tools/mkimage -n '2.4.4 kernel for TQM850L' \
 	> -A ppc -O linux -T kernel -C gzip -a 0 -e 0 \
 	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz \
 	> examples/uImage.TQM850L
 	Image Name:   2.4.4 kernel for TQM850L
 	Created:      Wed Jul 19 02:34:59 2000
 	Image Type:   PowerPC Linux Kernel Image (gzip compressed)
 	Data Size:    335725 Bytes = 327.86 kB = 0.32 MB
 	Load Address: 0x00000000
 	Entry Point:  0x00000000
 To verify the contents of the image (or check for corruption):
 	-> tools/mkimage -l examples/uImage.TQM850L
 	Image Name:   2.4.4 kernel for TQM850L
 	Created:      Wed Jul 19 02:34:59 2000
 	Image Type:   PowerPC Linux Kernel Image (gzip compressed)
 	Data Size:    335725 Bytes = 327.86 kB = 0.32 MB
 	Load Address: 0x00000000
 	Entry Point:  0x00000000
 NOTE: for embedded systems where boot time is critical you can trade
 speed for memory and install an UNCOMPRESSED image instead: this
 needs more space in Flash, but boots much faster since it does not
 need to be uncompressed:
 	-> gunzip /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz
 	-> tools/mkimage -n '2.4.4 kernel for TQM850L' \
 	> -A ppc -O linux -T kernel -C none -a 0 -e 0 \
 	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux \
 	> examples/uImage.TQM850L-uncompressed
 	Image Name:   2.4.4 kernel for TQM850L
 	Created:      Wed Jul 19 02:34:59 2000
 	Image Type:   PowerPC Linux Kernel Image (uncompressed)
 	Data Size:    792160 Bytes = 773.59 kB = 0.76 MB
 	Load Address: 0x00000000
 	Entry Point:  0x00000000
 Similar you can build U-Boot images from a 'ramdisk.image.gz' file
 when your kernel is intended to use an initial ramdisk:
 	-> tools/mkimage -n 'Simple Ramdisk Image' \
 	> -A ppc -O linux -T ramdisk -C gzip \
 	> -d /LinuxPPC/images/SIMPLE-ramdisk.image.gz examples/simple-initrd
 	Image Name:   Simple Ramdisk Image
 	Created:      Wed Jan 12 14:01:50 2000
 	Image Type:   PowerPC Linux RAMDisk Image (gzip compressed)
 	Data Size:    566530 Bytes = 553.25 kB = 0.54 MB
 	Load Address: 0x00000000
 	Entry Point:  0x00000000
 The "dumpimage" is a tool to disassemble images built by mkimage. Its "-i"
 option performs the converse operation of the mkimage's second form (the "-d"
 option). Given an image built by mkimage, the dumpimage extracts a "data file"
 from the image:
 	tools/dumpimage -i image -p position data_file
 	  -i ==> extract from the 'image' a specific 'data_file', \
 	   indexed by 'position'
 Installing a Linux Image:
 -------------------------
 To downloading a U-Boot image over the serial (console) interface,
 you must convert the image to S-Record format:
 	objcopy -I binary -O srec examples/image examples/image.srec
 The 'objcopy' does not understand the information in the U-Boot
 image header, so the resulting S-Record file will be relative to
 address 0x00000000. To load it to a given address, you need to
 specify the target address as 'offset' parameter with the 'loads'
 command.
 Example: install the image to address 0x40100000 (which on the
 TQM8xxL is in the first Flash bank):
 	=> erase 40100000 401FFFFF
 	.......... done
 	Erased 8 sectors
 	=> loads 40100000
 	## Ready for S-Record download ...
 	~>examples/image.srec
 	1 2 3 4 5 6 7 8 9 10 11 12 13 ...
 	...
 	15989 15990 15991 15992
 	[file transfer complete]
 	[connected]
 	## Start Addr = 0x00000000
 You can check the success of the download using the 'iminfo' command;
 this includes a checksum verification so you can be sure no data
 corruption happened:
 	=> imi 40100000
 	## Checking Image at 40100000 ...
 	   Image Name:	 2.2.13 for initrd on TQM850L
 	   Image Type:	 PowerPC Linux Kernel Image (gzip compressed)
 	   Data Size:	 335725 Bytes = 327 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 0000000c
 	   Verifying Checksum ... OK
 Boot Linux:
 -----------
 The "bootm" command is used to boot an application that is stored in
 memory (RAM or Flash). In case of a Linux kernel image, the contents
 of the "bootargs" environment variable is passed to the kernel as
 parameters. You can check and modify this variable using the
 "printenv" and "setenv" commands:
 	=> printenv bootargs
 	bootargs=root=/dev/ram
 	=> setenv bootargs root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2
 	=> printenv bootargs
 	bootargs=root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2
 	=> bootm 40020000
 	## Booting Linux kernel at 40020000 ...
 	   Image Name:	 2.2.13 for NFS on TQM850L
 	   Image Type:	 PowerPC Linux Kernel Image (gzip compressed)
 	   Data Size:	 381681 Bytes = 372 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 0000000c
 	   Verifying Checksum ... OK
 	   Uncompressing Kernel Image ... OK
 	Linux version 2.2.13 (wd@denx.local.net) (gcc version 2.95.2 19991024 (release)) #1 Wed Jul 19 02:35:17 MEST 2000
 	Boot arguments: root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2
 	time_init: decrementer frequency = 187500000/60
 	Calibrating delay loop... 49.77 BogoMIPS
 	Memory: 15208k available (700k kernel code, 444k data, 32k init) [c0000000,c1000000]
 	...
 If you want to boot a Linux kernel with initial RAM disk, you pass
 the memory addresses of both the kernel and the initrd image (PPBCOOT
 format!) to the "bootm" command:
 	=> imi 40100000 40200000
 	## Checking Image at 40100000 ...
 	   Image Name:	 2.2.13 for initrd on TQM850L
 	   Image Type:	 PowerPC Linux Kernel Image (gzip compressed)
 	   Data Size:	 335725 Bytes = 327 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 0000000c
 	   Verifying Checksum ... OK
 	## Checking Image at 40200000 ...
 	   Image Name:	 Simple Ramdisk Image
 	   Image Type:	 PowerPC Linux RAMDisk Image (gzip compressed)
 	   Data Size:	 566530 Bytes = 553 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 00000000
 	   Verifying Checksum ... OK
 	=> bootm 40100000 40200000
 	## Booting Linux kernel at 40100000 ...
 	   Image Name:	 2.2.13 for initrd on TQM850L
 	   Image Type:	 PowerPC Linux Kernel Image (gzip compressed)
 	   Data Size:	 335725 Bytes = 327 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 0000000c
 	   Verifying Checksum ... OK
 	   Uncompressing Kernel Image ... OK
 	## Loading RAMDisk Image at 40200000 ...
 	   Image Name:	 Simple Ramdisk Image
 	   Image Type:	 PowerPC Linux RAMDisk Image (gzip compressed)
 	   Data Size:	 566530 Bytes = 553 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 00000000
 	   Verifying Checksum ... OK
 	   Loading Ramdisk ... OK
 	Linux version 2.2.13 (wd@denx.local.net) (gcc version 2.95.2 19991024 (release)) #1 Wed Jul 19 02:32:08 MEST 2000
 	Boot arguments: root=/dev/ram
 	time_init: decrementer frequency = 187500000/60
 	Calibrating delay loop... 49.77 BogoMIPS
 	...
 	RAMDISK: Compressed image found at block 0
 	VFS: Mounted root (ext2 filesystem).
 	bash#
 Boot Linux and pass a flat device tree:
 -----------
 First, U-Boot must be compiled with the appropriate defines. See the section
 titled "Linux Kernel Interface" above for a more in depth explanation. The
 following is an example of how to start a kernel and pass an updated
 flat device tree:
 => print oftaddr
 oftaddr=0x300000
 => print oft
 oft=oftrees/mpc8540ads.dtb
 => tftp $oftaddr $oft
 Speed: 1000, full duplex
 Using TSEC0 device
 TFTP from server 192.168.1.1; our IP address is 192.168.1.101
 Filename 'oftrees/mpc8540ads.dtb'.
 Load address: 0x300000
 Loading: #
 done
 Bytes transferred = 4106 (100a hex)
 => tftp $loadaddr $bootfile
 Speed: 1000, full duplex
 Using TSEC0 device
 TFTP from server 192.168.1.1; our IP address is 192.168.1.2
 Filename 'uImage'.
 Load address: 0x200000
 Loading:############
 done
 Bytes transferred = 1029407 (fb51f hex)
 => print loadaddr
 loadaddr=200000
 => print oftaddr
 oftaddr=0x300000
 => bootm $loadaddr - $oftaddr
 ## Booting image at 00200000 ...
    Image Name:	 Linux-2.6.17-dirty
    Image Type:	 PowerPC Linux Kernel Image (gzip compressed)
    Data Size:	 1029343 Bytes = 1005.2 kB
    Load Address: 00000000
    Entry Point:	 00000000
    Verifying Checksum ... OK
    Uncompressing Kernel Image ... OK
 Booting using flat device tree at 0x300000
 Using MPC85xx ADS machine description
 Memory CAM mapping: CAM0=256Mb, CAM1=256Mb, CAM2=0Mb residual: 0Mb
 [snip]
 More About U-Boot Image Types:
 ------------------------------
 U-Boot supports the following image types:
    "Standalone Programs" are directly runnable in the environment
 	provided by U-Boot; it is expected that (if they behave
 	well) you can continue to work in U-Boot after return from
 	the Standalone Program.
    "OS Kernel Images" are usually images of some Embedded OS which
 	will take over control completely. Usually these programs
 	will install their own set of exception handlers, device
 	drivers, set up the MMU, etc. - this means, that you cannot
 	expect to re-enter U-Boot except by resetting the CPU.
    "RAMDisk Images" are more or less just data blocks, and their
 	parameters (address, size) are passed to an OS kernel that is
 	being started.
    "Multi-File Images" contain several images, typically an OS
 	(Linux) kernel image and one or more data images like
 	RAMDisks. This construct is useful for instance when you want
 	to boot over the network using BOOTP etc., where the boot
 	server provides just a single image file, but you want to get
 	for instance an OS kernel and a RAMDisk image.
 	"Multi-File Images" start with a list of image sizes, each
 	image size (in bytes) specified by an "uint32_t" in network
 	byte order. This list is terminated by an "(uint32_t)0".
 	Immediately after the terminating 0 follow the images, one by
 	one, all aligned on "uint32_t" boundaries (size rounded up to
 	a multiple of 4 bytes).
    "Firmware Images" are binary images containing firmware (like
 	U-Boot or FPGA images) which usually will be programmed to
 	flash memory.
    "Script files" are command sequences that will be executed by
 	U-Boot's command interpreter; this feature is especially
 	useful when you configure U-Boot to use a real shell (hush)
 	as command interpreter.
 Booting the Linux zImage:
 -------------------------
 On some platforms, it's possible to boot Linux zImage. This is done
 using the "bootz" command. The syntax of "bootz" command is the same
 as the syntax of "bootm" command.
 Note, defining the CONFIG_SUPPORT_RAW_INITRD allows user to supply
 kernel with raw initrd images. The syntax is slightly different, the
 address of the initrd must be augmented by it's size, in the following
 format: "<initrd addres>:<initrd size>".
 Standalone HOWTO:
 =================
 One of the features of U-Boot is that you can dynamically load and
 run "standalone" applications, which can use some resources of
 U-Boot like console I/O functions or interrupt services.
 Two simple examples are included with the sources:
 "Hello World" Demo:
 -------------------
 'examples/hello_world.c' contains a small "Hello World" Demo
 application; it is automatically compiled when you build U-Boot.
 It's configured to run at address 0x00040004, so you can play with it
 like that:
 	=> loads
 	## Ready for S-Record download ...
 	~>examples/hello_world.srec
 	1 2 3 4 5 6 7 8 9 10 11 ...
 	[file transfer complete]
 	[connected]
 	## Start Addr = 0x00040004
 	=> go 40004 Hello World! This is a test.
 	## Starting application at 0x00040004 ...
 	Hello World
 	argc = 7
 	argv[0] = "40004"
 	argv[1] = "Hello"
 	argv[2] = "World!"
 	argv[3] = "This"
 	argv[4] = "is"
 	argv[5] = "a"
 	argv[6] = "test."
 	argv[7] = "<NULL>"
 	Hit any key to exit ...
 	## Application terminated, rc = 0x0
 Another example, which demonstrates how to register a CPM interrupt
 handler with the U-Boot code, can be found in 'examples/timer.c'.
 Here, a CPM timer is set up to generate an interrupt every second.
 The interrupt service routine is trivial, just printing a '.'
 character, but this is just a demo program. The application can be
 controlled by the following keys:
 	? - print current values og the CPM Timer registers
 	b - enable interrupts and start timer
 	e - stop timer and disable interrupts
 	q - quit application
 	=> loads
 	## Ready for S-Record download ...
 	~>examples/timer.srec
 	1 2 3 4 5 6 7 8 9 10 11 ...
 	[file transfer complete]
 	[connected]
 	## Start Addr = 0x00040004
 	=> go 40004
 	## Starting application at 0x00040004 ...
 	TIMERS=0xfff00980
 	Using timer 1
 	  tgcr @ 0xfff00980, tmr @ 0xfff00990, trr @ 0xfff00994, tcr @ 0xfff00998, tcn @ 0xfff0099c, ter @ 0xfff009b0
 Hit 'b':
 	[q, b, e, ?] Set interval 1000000 us
 	Enabling timer
 Hit '?':
 	[q, b, e, ?] ........
 	tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0xef6, ter=0x0
 Hit '?':
 	[q, b, e, ?] .
 	tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x2ad4, ter=0x0
 Hit '?':
 	[q, b, e, ?] .
 	tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x1efc, ter=0x0
 Hit '?':
 	[q, b, e, ?] .
 	tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x169d, ter=0x0
 Hit 'e':
 	[q, b, e, ?] ...Stopping timer
 Hit 'q':
 	[q, b, e, ?] ## Application terminated, rc = 0x0
 Minicom warning:
 ================
 Over time, many people have reported problems when trying to use the
 "minicom" terminal emulation program for serial download. I (wd)
 consider minicom to be broken, and recommend not to use it. Under
 Unix, I recommend to use C-Kermit for general purpose use (and
 especially for kermit binary protocol download ("loadb" command), and
 use "cu" for S-Record download ("loads" command).  See
 http://www.denx.de/wiki/view/DULG/SystemSetup#Section_4.3.
 for help with kermit.
 Nevertheless, if you absolutely want to use it try adding this
 configuration to your "File transfer protocols" section:
 	   Name	   Program			Name U/D FullScr IO-Red. Multi
 	X  kermit  /usr/bin/kermit -i -l %l -s	 Y    U	   Y	   N	  N
 	Y  kermit  /usr/bin/kermit -i -l %l -r	 N    D	   Y	   N	  N
 NetBSD Notes:
 =============
 Starting at version 0.9.2, U-Boot supports NetBSD both as host
 (build U-Boot) and target system (boots NetBSD/mpc8xx).
 Building requires a cross environment; it is known to work on
 NetBSD/i386 with the cross-powerpc-netbsd-1.3 package (you will also
 need gmake since the Makefiles are not compatible with BSD make).
 Note that the cross-powerpc package does not install include files;
 attempting to build U-Boot will fail because <machine/ansi.h> is
 missing.  This file has to be installed and patched manually:
 	# cd /usr/pkg/cross/powerpc-netbsd/include
 	# mkdir powerpc
 	# ln -s powerpc machine
 	# cp /usr/src/sys/arch/powerpc/include/ansi.h powerpc/ansi.h
 	# ${EDIT} powerpc/ansi.h	## must remove __va_list, _BSD_VA_LIST
 Native builds *don't* work due to incompatibilities between native
 and U-Boot include files.
 Booting assumes that (the first part of) the image booted is a
 stage-2 loader which in turn loads and then invokes the kernel
 proper. Loader sources will eventually appear in the NetBSD source
 tree (probably in sys/arc/mpc8xx/stand/u-boot_stage2/); in the
 meantime, see ftp://ftp.denx.de/pub/u-boot/ppcboot_stage2.tar.gz
 Implementation Internals:
 =========================
 The following is not intended to be a complete description of every
 implementation detail. However, it should help to understand the
 inner workings of U-Boot and make it easier to port it to custom
 hardware.
 Initial Stack, Global Data:
 ---------------------------
 The implementation of U-Boot is complicated by the fact that U-Boot
 starts running out of ROM (flash memory), usually without access to
 system RAM (because the memory controller is not initialized yet).
 This means that we don't have writable Data or BSS segments, and BSS
 is not initialized as zero. To be able to get a C environment working
 at all, we have to allocate at least a minimal stack. Implementation
 options for this are defined and restricted by the CPU used: Some CPU
 models provide on-chip memory (like the IMMR area on MPC8xx and
 MPC826x processors), on others (parts of) the data cache can be
 locked as (mis-) used as memory, etc.
 	Chris Hallinan posted a good summary of these issues to the
 	U-Boot mailing list:
 	Subject: RE: [U-Boot-Users] RE: More On Memory Bank x (nothingness)?
 	From: "Chris Hallinan" <clh@net1plus.com>
 	Date: Mon, 10 Feb 2003 16:43:46 -0500 (22:43 MET)
 	...
 	Correct me if I'm wrong, folks, but the way I understand it
 	is this: Using DCACHE as initial RAM for Stack, etc, does not
 	require any physical RAM backing up the cache. The cleverness
 	is that the cache is being used as a temporary supply of
 	necessary storage before the SDRAM controller is setup. It's
 	beyond the scope of this list to explain the details, but you
 	can see how this works by studying the cache architecture and
 	operation in the architecture and processor-specific manuals.
 	OCM is On Chip Memory, which I believe the 405GP has 4K. It
 	is another option for the system designer to use as an
 	initial stack/RAM area prior to SDRAM being available. Either
 	option should work for you. Using CS 4 should be fine if your
 	board designers haven't used it for something that would
 	cause you grief during the initial boot! It is frequently not
 	used.
 	CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
 	with your processor/board/system design. The default value
 	you will find in any recent u-boot distribution in
 	walnut.h should work for you. I'd set it to a value larger
 	than your SDRAM module. If you have a 64MB SDRAM module, set
 	it above 400_0000. Just make sure your board has no resources
 	that are supposed to respond to that address! That code in
 	start.S has been around a while and should work as is when
 	you get the config right.
 	-Chris Hallinan
 	DS4.COM, Inc.
 It is essential to remember this, since it has some impact on the C
 code for the initialization procedures:
 * Initialized global data (data segment) is read-only. Do not attempt
   to write it.
 * Do not use any uninitialized global data (or implicitely initialized
   as zero data - BSS segment) at all - this is undefined, initiali-
   zation is performed later (when relocating to RAM).
 * Stack space is very limited. Avoid big data buffers or things like
   that.
 Having only the stack as writable memory limits means we cannot use
 normal global data to share information beween the code. But it
 turned out that the implementation of U-Boot can be greatly
 simplified by making a global data structure (gd_t) available to all
 functions. We could pass a pointer to this data as argument to _all_
 functions, but this would bloat the code. Instead we use a feature of
 the GCC compiler (Global Register Variables) to share the data: we
 place a pointer (gd) to the global data into a register which we
 reserve for this purpose.
 When choosing a register for such a purpose we are restricted by the
 relevant  (E)ABI  specifications for the current architecture, and by
 GCC's implementation.
 For PowerPC, the following registers have specific use:
 	R1:	stack pointer
 	R2:	reserved for system use
 	R3-R4:	parameter passing and return values
 	R5-R10: parameter passing
 	R13:	small data area pointer
 	R30:	GOT pointer
 	R31:	frame pointer
 	(U-Boot also uses R12 as internal GOT pointer. r12
 	is a volatile register so r12 needs to be reset when
 	going back and forth between asm and C)
     ==> U-Boot will use R2 to hold a pointer to the global data
     Note: on PPC, we could use a static initializer (since the
     address of the global data structure is known at compile time),
     but it turned out that reserving a register results in somewhat
     smaller code - although the code savings are not that big (on
     average for all boards 752 bytes for the whole U-Boot image,
     624 text + 127 data).
 On Blackfin, the normal C ABI (except for P3) is followed as documented here:
 	http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
     ==> U-Boot will use P3 to hold a pointer to the global data
 On ARM, the following registers are used:
 	R0:	function argument word/integer result
 	R1-R3:	function argument word
 	R9:	platform specific
 	R10:	stack limit (used only if stack checking is enabled)
 	R11:	argument (frame) pointer
 	R12:	temporary workspace
 	R13:	stack pointer
 	R14:	link register
 	R15:	program counter
     ==> U-Boot will use R9 to hold a pointer to the global data
     Note: on ARM, only R_ARM_RELATIVE relocations are supported.
 On Nios II, the ABI is documented here:
 	http://www.altera.com/literature/hb/nios2/n2cpu_nii51016.pdf
     ==> U-Boot will use gp to hold a pointer to the global data
     Note: on Nios II, we give "-G0" option to gcc and don't use gp
     to access small data sections, so gp is free.
 On NDS32, the following registers are used:
 	R0-R1:	argument/return
 	R2-R5:	argument
 	R15:	temporary register for assembler
 	R16:	trampoline register
 	R28:	frame pointer (FP)
 	R29:	global pointer (GP)
 	R30:	link register (LP)
 	R31:	stack pointer (SP)
 	PC:	program counter (PC)
     ==> U-Boot will use R10 to hold a pointer to the global data
 NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
 or current versions of GCC may "optimize" the code too much.
 Memory Management:
 ------------------
 U-Boot runs in system state and uses physical addresses, i.e. the
 MMU is not used either for address mapping nor for memory protection.
 The available memory is mapped to fixed addresses using the memory
 controller. In this process, a contiguous block is formed for each
 memory type (Flash, SDRAM, SRAM), even when it consists of several
 physical memory banks.
 U-Boot is installed in the first 128 kB of the first Flash bank (on
 TQM8xxL modules this is the range 0x40000000 ... 0x4001FFFF). After
 booting and sizing and initializing DRAM, the code relocates itself
 to the upper end of DRAM. Immediately below the U-Boot code some
 memory is reserved for use by malloc() [see CONFIG_SYS_MALLOC_LEN
 configuration setting]. Below that, a structure with global Board
 Info data is placed, followed by the stack (growing downward).
 Additionally, some exception handler code is copied to the low 8 kB
 of DRAM (0x00000000 ... 0x00001FFF).
 So a typical memory configuration with 16 MB of DRAM could look like
 this:
 	0x0000 0000	Exception Vector code
 	      :
 	0x0000 1FFF
 	0x0000 2000	Free for Application Use
 	      :
 	      :
 	      :
 	      :
 	0x00FB FF20	Monitor Stack (Growing downward)
 	0x00FB FFAC	Board Info Data and permanent copy of global data
 	0x00FC 0000	Malloc Arena
 	      :
 	0x00FD FFFF
 	0x00FE 0000	RAM Copy of Monitor Code
 	...		eventually: LCD or video framebuffer
 	...		eventually: pRAM (Protected RAM - unchanged by reset)
 	0x00FF FFFF	[End of RAM]
 System Initialization:
 ----------------------
 In the reset configuration, U-Boot starts at the reset entry point
 (on most PowerPC systems at address 0x00000100). Because of the reset
 configuration for CS0# this is a mirror of the onboard Flash memory.
 To be able to re-map memory U-Boot then jumps to its link address.
 To be able to implement the initialization code in C, a (small!)
 initial stack is set up in the internal Dual Ported RAM (in case CPUs
 which provide such a feature like MPC8xx or MPC8260), or in a locked
 part of the data cache. After that, U-Boot initializes the CPU core,
 the caches and the SIU.
 Next, all (potentially) available memory banks are mapped using a
 preliminary mapping. For example, we put them on 512 MB boundaries
 (multiples of 0x20000000: SDRAM on 0x00000000 and 0x20000000, Flash
 on 0x40000000 and 0x60000000, SRAM on 0x80000000). Then UPM A is
 programmed for SDRAM access. Using the temporary configuration, a
 simple memory test is run that determines the size of the SDRAM
 banks.
 When there is more than one SDRAM bank, and the banks are of
 different size, the largest is mapped first. For equal size, the first
 bank (CS2#) is mapped first. The first mapping is always for address
 0x00000000, with any additional banks following immediately to create
 contiguous memory starting from 0.
 Then, the monitor installs itself at the upper end of the SDRAM area
 and allocates memory for use by malloc() and for the global Board
 Info data; also, the exception vector code is copied to the low RAM
 pages, and the final stack is set up.
 Only after this relocation will you have a "normal" C environment;
 until that you are restricted in several ways, mostly because you are
 running from ROM, and because the code will have to be relocated to a
 new address in RAM.
 U-Boot Porting Guide:
 ----------------------
 [Based on messages by Jerry Van Baren in the U-Boot-Users mailing
 list, October 2002]
 int main(int argc, char *argv[])
 {
 	sighandler_t no_more_time;
 	signal(SIGALRM, no_more_time);
 	alarm(PROJECT_DEADLINE - toSec (3 * WEEK));
 	if (available_money > available_manpower) {
 		Pay consultant to port U-Boot;
 		return 0;
 	}
 	Download latest U-Boot source;
 	Subscribe to u-boot mailing list;
 	if (clueless)
 		email("Hi, I am new to U-Boot, how do I get started?");
 	while (learning) {
 		Read the README file in the top level directory;
 		Read http://www.denx.de/twiki/bin/view/DULG/Manual;
 		Read applicable doc/*.README;
 		Read the source, Luke;
 		/* find . -name "*.[chS]" | xargs grep -i <keyword> */
 	}
 	if (available_money > toLocalCurrency ($2500))
 		Buy a BDI3000;
 	else
 		Add a lot of aggravation and time;
 	if (a similar board exists) {	/* hopefully... */
 		cp -a board/<similar> board/<myboard>
 		cp include/configs/<similar>.h include/configs/<myboard>.h
 	} else {
 		Create your own board support subdirectory;
 		Create your own board include/configs/<myboard>.h file;
 	}
 	Edit new board/<myboard> files
 	Edit new include/configs/<myboard>.h
 	while (!accepted) {
 		while (!running) {
 			do {
 				Add / modify source code;
 			} until (compiles);
 			Debug;
 			if (clueless)
 				email("Hi, I am having problems...");
 		}
 		Send patch file to the U-Boot email list;
 		if (reasonable critiques)
 			Incorporate improvements from email list code review;
 		else
 			Defend code as written;
 	}
 	return 0;
 }
 void no_more_time (int sig)
 {
       hire_a_guru();
 }
 Coding Standards:
 -----------------
 All contributions to U-Boot should conform to the Linux kernel
 coding style; see the file "Documentation/CodingStyle" and the script
 "scripts/Lindent" in your Linux kernel source directory.
 Source files originating from a different project (for example the
 MTD subsystem) are generally exempt from these guidelines and are not
 reformated to ease subsequent migration to newer versions of those
 sources.
 Please note that U-Boot is implemented in C (and to some small parts in
 Assembler); no C++ is used, so please do not use C++ style comments (//)
 in your code.
 Please also stick to the following formatting rules:
 - remove any trailing white space
 - use TAB characters for indentation and vertical alignment, not spaces
 - make sure NOT to use DOS '\r\n' line feeds
 - do not add more than 2 consecutive empty lines to source files
 - do not add trailing empty lines to source files
 Submissions which do not conform to the standards may be returned
 with a request to reformat the changes.
 Submitting Patches:
 -------------------
 Since the number of patches for U-Boot is growing, we need to
 establish some rules. Submissions which do not conform to these rules
 may be rejected, even when they contain important and valuable stuff.
 Please see http://www.denx.de/wiki/U-Boot/Patches for details.
 Patches shall be sent to the u-boot mailing list <u-boot@lists.denx.de>;
 see http://lists.denx.de/mailman/listinfo/u-boot
 When you send a patch, please include the following information with
 it:
 * For bug fixes: a description of the bug and how your patch fixes
   this bug. Please try to include a way of demonstrating that the
   patch actually fixes something.
 * For new features: a description of the feature and your
   implementation.
 * A CHANGELOG entry as plaintext (separate from the patch)
 * For major contributions, your entry to the CREDITS file
 * When you add support for a new board, don't forget to add a
   maintainer e-mail address to the boards.cfg file, too.
 * If your patch adds new configuration options, don't forget to
   document these in the README file.
 * The patch itself. If you are using git (which is *strongly*
   recommended) you can easily generate the patch using the
   "git format-patch". If you then use "git send-email" to send it to
   the U-Boot mailing list, you will avoid most of the common problems
   with some other mail clients.
   If you cannot use git, use "diff -purN OLD NEW". If your version of
   diff does not support these options, then get the latest version of
   GNU diff.
   The current directory when running this command shall be the parent
   directory of the U-Boot source tree (i. e. please make sure that
   your patch includes sufficient directory information for the
   affected files).
   We prefer patches as plain text. MIME attachments are discouraged,
   and compressed attachments must not be used.
 * If one logical set of modifications affects or creates several
   files, all these changes shall be submitted in a SINGLE patch file.
 * Changesets that contain different, unrelated modifications shall be
   submitted as SEPARATE patches, one patch per changeset.
 Notes:
 * Before sending the patch, run the MAKEALL script on your patched
   source tree and make sure that no errors or warnings are reported
   for any of the boards.
 * Keep your modifications to the necessary minimum: A patch
   containing several unrelated changes or arbitrary reformats will be
   returned with a request to re-formatting / split it.
 * If you modify existing code, make sure that your new code does not
   add to the memory footprint of the code ;-) Small is beautiful!
   When adding new features, these should compile conditionally only
   (using #ifdef), and the resulting code with the new feature
   disabled must not need more memory than the old code without your
   modification.
 * Remember that there is a size limit of 100 kB per message on the
   u-boot mailing list. Bigger patches will be moderated. If they are
   reasonable and not too big, they will be acknowledged. But patches
   bigger than the size limit should be avoided.

arch/powerpc/cpu/mpc85xx/speed.c

Diff comments View file @ e7be182

 /*
  * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2003 Motorola Inc.
  * Xianghua Xiao, (X.Xiao@motorola.com)
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <ppc_asm.tmpl>
 #include <linux/compiler.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 DECLARE_GLOBAL_DATA_PTR;
 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	6
 #endif
 /* --------------------------------------------------------------- */
 void get_sys_info(sys_info_t *sys_info)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #ifdef CONFIG_FSL_IFC
 	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
 	u32 ccr;
 #endif
 #ifdef CONFIG_FSL_CORENET
 	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
 	unsigned int cpu;
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 	int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
 #endif
 	const u8 core_cplx_PLL[16] = {
 		[ 0] = 0,	/* CC1 PPL / 1 */
 		[ 1] = 0,	/* CC1 PPL / 2 */
 		[ 2] = 0,	/* CC1 PPL / 4 */
 		[ 4] = 1,	/* CC2 PPL / 1 */
 		[ 5] = 1,	/* CC2 PPL / 2 */
 		[ 6] = 1,	/* CC2 PPL / 4 */
 		[ 8] = 2,	/* CC3 PPL / 1 */
 		[ 9] = 2,	/* CC3 PPL / 2 */
 		[10] = 2,	/* CC3 PPL / 4 */
 		[12] = 3,	/* CC4 PPL / 1 */
 		[13] = 3,	/* CC4 PPL / 2 */
 		[14] = 3,	/* CC4 PPL / 4 */
 	};
 	const u8 core_cplx_pll_div[16] = {
 		[ 0] = 1,	/* CC1 PPL / 1 */
 		[ 1] = 2,	/* CC1 PPL / 2 */
 		[ 2] = 4,	/* CC1 PPL / 4 */
 		[ 4] = 1,	/* CC2 PPL / 1 */
 		[ 5] = 2,	/* CC2 PPL / 2 */
 		[ 6] = 4,	/* CC2 PPL / 4 */
 		[ 8] = 1,	/* CC3 PPL / 1 */
 		[ 9] = 2,	/* CC3 PPL / 2 */
 		[10] = 4,	/* CC3 PPL / 4 */
 		[12] = 1,	/* CC4 PPL / 1 */
 		[13] = 2,	/* CC4 PPL / 2 */
 		[14] = 4,	/* CC4 PPL / 4 */
 	};
 	uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
 	uint rcw_tmp;
 #endif
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
 	uint mem_pll_rat;
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+	uint single_src;
+#endif
 	sys_info->freq_systembus = sysclk;
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+	/*
+	 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
+	 * are driven by separate DDR Refclock or single source
+	 * differential clock.
+	 */
+	single_src = (in_be32(&gur->rcwsr[5]) >>
+		      FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
+		      FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
+	/*
+	 * For single source clocking, both ddrclock and syclock
+	 * are driven by differential sysclock.
+	 */
+	if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) {
+		printf("Single Source Clock Configuration\n");
+		sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
+	} else
+#endif
 #ifdef CONFIG_DDR_CLK_FREQ
-	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+		sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
 #else
-	sys_info->freq_ddrbus = sysclk;
+		sys_info->freq_ddrbus = sysclk;
 #endif
 	sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
 	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
 			FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
 			& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
 	/* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
 	 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
 	 * it uses 6.
 	 */
 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
 	if (SVR_MAJ(get_svr()) >= 2)
 		mem_pll_rat *= 2;
 #endif
 	if (mem_pll_rat > 2)
 		sys_info->freq_ddrbus *= mem_pll_rat;
 	else
 		sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
 	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
 		ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
 		if (ratio[i] > 4)
 			freq_c_pll[i] = sysclk * ratio[i];
 		else
 			freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
 	}
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 	/*
 	 * As per CHASSIS2 architeture total 12 clusters are posible and
 	 * Each cluster has up to 4 cores, sharing the same PLL selection.
 	 * The cluster clock assignment is SoC defined.
 	 *
 	 * Total 4 clock groups are possible with 3 PLLs each.
 	 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
 	 * clock group B has 3, 4, 6 and so on.
 	 *
 	 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
 	 * depends upon the SoC architeture. Same applies to other
 	 * clock groups and clusters.
 	 *
 	 */
 	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
 		int cluster = fsl_qoriq_core_to_cluster(cpu);
 		u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
 				& 0xf;
 		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
 		cplx_pll += cc_group[cluster] - 1;
 		sys_info->freq_processor[cpu] =
 			 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 	}
 #if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080)
 #define FM1_CLK_SEL	0xe0000000
 #define FM1_CLK_SHIFT	29
 #else
 #define PME_CLK_SEL	0xe0000000
 #define PME_CLK_SHIFT	29
 #define FM1_CLK_SEL	0x1c000000
 #define FM1_CLK_SHIFT	26
 #endif
 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
 	rcw_tmp = in_be32(&gur->rcwsr[7]);
 #endif
 #ifdef CONFIG_SYS_DPAA_PME
 #ifndef CONFIG_PME_PLAT_CLK_DIV
 	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
 	case 1:
 		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
 		break;
 	case 2:
 		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
 		break;
 	case 3:
 		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
 		break;
 	case 4:
 		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
 		break;
 	case 6:
 		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
 		break;
 	case 7:
 		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
 		break;
 	default:
 		printf("Error: Unknown PME clock select!\n");
 	case 0:
 		sys_info->freq_pme = sys_info->freq_systembus / 2;
 		break;
 	}
 #else
 	sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
 #endif
 #endif
 #ifdef CONFIG_SYS_DPAA_QBMAN
 	sys_info->freq_qman = sys_info->freq_systembus / 2;
 #endif
 #ifdef CONFIG_SYS_DPAA_FMAN
 #ifndef CONFIG_FM_PLAT_CLK_DIV
 	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
 	case 1:
 		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
 		break;
 	case 2:
 		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
 		break;
 	case 3:
 		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
 		break;
 	case 4:
 		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
 		break;
 	case 5:
 		sys_info->freq_fman[0] = sys_info->freq_systembus;
 		break;
 	case 6:
 		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
 		break;
 	case 7:
 		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
 		break;
 	default:
 		printf("Error: Unknown FMan1 clock select!\n");
 	case 0:
 		sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
 		break;
 	}
 #if (CONFIG_SYS_NUM_FMAN) == 2
 #ifdef CONFIG_SYS_FM2_CLK
 #define FM2_CLK_SEL	0x00000038
 #define FM2_CLK_SHIFT	3
 	rcw_tmp = in_be32(&gur->rcwsr[15]);
 	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
 	case 1:
 		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
 		break;
 	case 2:
 		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
 		break;
 	case 3:
 		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
 		break;
 	case 4:
 		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
 		break;
 	case 5:
 		sys_info->freq_fman[1] = sys_info->freq_systembus;
 		break;
 	case 6:
 		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
 		break;
 	case 7:
 		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
 		break;
 	default:
 		printf("Error: Unknown FMan2 clock select!\n");
 	case 0:
 		sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
 		break;
 	}
 #endif
 #endif	/* CONFIG_SYS_NUM_FMAN == 2 */
 #else
 	sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
 #endif
 #endif
 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
 		u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
 				& 0xf;
 		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
 		sys_info->freq_processor[cpu] =
 			 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 	}
 #define PME_CLK_SEL	0x80000000
 #define FM1_CLK_SEL	0x40000000
 #define FM2_CLK_SEL	0x20000000
 #define HWA_ASYNC_DIV	0x04000000
 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
 #define HWA_CC_PLL	1
 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
 #define HWA_CC_PLL	2
 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
 #define HWA_CC_PLL	2
 #else
 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
 #endif
 	rcw_tmp = in_be32(&gur->rcwsr[7]);
 #ifdef CONFIG_SYS_DPAA_PME
 	if (rcw_tmp & PME_CLK_SEL) {
 		if (rcw_tmp & HWA_ASYNC_DIV)
 			sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
 		else
 			sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
 	} else {
 		sys_info->freq_pme = sys_info->freq_systembus / 2;
 	}
 #endif
 #ifdef CONFIG_SYS_DPAA_FMAN
 	if (rcw_tmp & FM1_CLK_SEL) {
 		if (rcw_tmp & HWA_ASYNC_DIV)
 			sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
 		else
 			sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
 	} else {
 		sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
 	}
 #if (CONFIG_SYS_NUM_FMAN) == 2
 	if (rcw_tmp & FM2_CLK_SEL) {
 		if (rcw_tmp & HWA_ASYNC_DIV)
 			sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
 		else
 			sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
 	} else {
 		sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
 	}
 #endif
 #endif
 #ifdef CONFIG_SYS_DPAA_QBMAN
 	sys_info->freq_qman = sys_info->freq_systembus / 2;
 #endif
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #else /* CONFIG_FSL_CORENET */
 	uint plat_ratio, e500_ratio, half_freq_systembus;
 	int i;
 #ifdef CONFIG_QE
 	__maybe_unused u32 qe_ratio;
 #endif
 	plat_ratio = (gur->porpllsr) & 0x0000003e;
 	plat_ratio >>= 1;
 	sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
 	/* Divide before multiply to avoid integer
 	 * overflow for processor speeds above 2GHz */
 	half_freq_systembus = sys_info->freq_systembus/2;
 	for (i = 0; i < cpu_numcores(); i++) {
 		e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
 		sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
 	}
 	/* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
 	sys_info->freq_ddrbus = sys_info->freq_systembus;
 #ifdef CONFIG_DDR_CLK_FREQ
 	{
 		u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
 			>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
 		if (ddr_ratio != 0x7)
 			sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
 	}
 #endif
 #ifdef CONFIG_QE
 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
 	sys_info->freq_qe =  sys_info->freq_systembus;
 #else
 	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
 			>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
 	sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
 #endif
 #endif
 #ifdef CONFIG_SYS_DPAA_FMAN
 		sys_info->freq_fman[0] = sys_info->freq_systembus;
 #endif
 #endif /* CONFIG_FSL_CORENET */
 #if defined(CONFIG_FSL_LBC)
 	uint lcrr_div;
 #if defined(CONFIG_SYS_LBC_LCRR)
 	/* We will program LCRR to this value later */
 	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
 #else
 	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
 #endif
 	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
 #if defined(CONFIG_FSL_CORENET)
 		/* If this is corenet based SoC, bit-representation
 		 * for four times the clock divider values.
 		 */
 		lcrr_div *= 4;
 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
     !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
 		/*
 		 * Yes, the entire PQ38 family use the same
 		 * bit-representation for twice the clock divider values.
 		 */
 		lcrr_div *= 2;
 #endif
 		sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
 	} else {
 		/* In case anyone cares what the unknown value is */
 		sys_info->freq_localbus = lcrr_div;
 	}
 #endif
 #if defined(CONFIG_FSL_IFC)
 	ccr = in_be32(&ifc_regs->ifc_ccr);
 	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
 	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
 #endif
 }
 int get_clocks (void)
 {
 	sys_info_t sys_info;
 #ifdef CONFIG_MPC8544
 	volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
 #endif
 #if defined(CONFIG_CPM2)
 	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
 	uint sccr, dfbrg;
 	/* set VCO = 4 * BRG */
 	cpm->im_cpm_intctl.sccr &= 0xfffffffc;
 	sccr = cpm->im_cpm_intctl.sccr;
 	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
 #endif
 	get_sys_info (&sys_info);
 	gd->cpu_clk = sys_info.freq_processor[0];
 	gd->bus_clk = sys_info.freq_systembus;
 	gd->mem_clk = sys_info.freq_ddrbus;
 	gd->arch.lbc_clk = sys_info.freq_localbus;
 #ifdef CONFIG_QE
 	gd->arch.qe_clk = sys_info.freq_qe;
 	gd->arch.brg_clk = gd->arch.qe_clk / 2;
 #endif
 	/*
 	 * The base clock for I2C depends on the actual SOC.  Unfortunately,
 	 * there is no pattern that can be used to determine the frequency, so
 	 * the only choice is to look up the actual SOC number and use the value
 	 * for that SOC. This information is taken from application note
 	 * AN2919.
 	 */
 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
 	defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
 	defined(CONFIG_P1022)
 	gd->arch.i2c1_clk = sys_info.freq_systembus;
 #elif defined(CONFIG_MPC8544)
 	/*
 	 * On the 8544, the I2C clock is the same as the SEC clock.  This can be
 	 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
 	 * 4.4.3.3 of the 8544 RM.  Note that this might actually work for all
 	 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
 	 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
 	 */
 	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
 		gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
 	else
 		gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
 #else
 	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
 	gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
 #endif
 	gd->arch.i2c2_clk = gd->arch.i2c1_clk;
 #if defined(CONFIG_FSL_ESDHC)
 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
        defined(CONFIG_P1014)
 	gd->arch.sdhc_clk = gd->bus_clk;
 #else
 	gd->arch.sdhc_clk = gd->bus_clk / 2;
 #endif
 #endif /* defined(CONFIG_FSL_ESDHC) */
 #if defined(CONFIG_CPM2)
 	gd->arch.vco_out = 2*sys_info.freq_systembus;
 	gd->arch.cpm_clk = gd->arch.vco_out / 2;
 	gd->arch.scc_clk = gd->arch.vco_out / 4;
 	gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
 #endif
 	if(gd->cpu_clk != 0) return (0);
 	else return (1);
 }
 /********************************************
  * get_bus_freq
  * return system bus freq in Hz
  *********************************************/
 ulong get_bus_freq (ulong dummy)
 {
 	return gd->bus_clk;
 }
 /********************************************
  * get_ddr_freq
  * return ddr bus freq in Hz
  *********************************************/
 ulong get_ddr_freq (ulong dummy)
 {
 	return gd->mem_clk;
 }

arch/powerpc/include/asm/config_mpc85xx.h

Diff comments View file @ e7be182

 /*
  * Copyright 2011-2012 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef _ASM_MPC85xx_CONFIG_H_
 #define _ASM_MPC85xx_CONFIG_H_
 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
 #endif
 /*
  * This macro should be removed when we no longer care about backwards
  * compatibility with older operating systems.
  */
 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
 #define FSL_DDR_VER_4_7	47
 #define FSL_DDR_VER_5_0	50
 /* Number of TLB CAM entries we have on FSL Book-E chips */
 #if defined(CONFIG_E500MC)
 #define CONFIG_SYS_NUM_TLBCAMS		64
 #elif defined(CONFIG_E500)
 #define CONFIG_SYS_NUM_TLBCAMS		16
 #endif
 #if defined(CONFIG_MPC8536)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	1
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #elif defined(CONFIG_MPC8540)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		8
 #define CONFIG_SYS_FSL_DDRC_GEN1
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #elif defined(CONFIG_MPC8541)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		8
 #define CONFIG_SYS_FSL_DDRC_GEN1
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #elif defined(CONFIG_MPC8544)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		10
 #define CONFIG_SYS_FSL_DDRC_GEN2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	0
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #elif defined(CONFIG_MPC8548)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		10
 #define CONFIG_SYS_FSL_DDRC_GEN2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	0
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	1
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CONFIG_SYS_FSL_RMU
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x00
 #elif defined(CONFIG_MPC8555)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		8
 #define CONFIG_SYS_FSL_DDRC_GEN1
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #elif defined(CONFIG_MPC8560)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		8
 #define CONFIG_SYS_FSL_DDRC_GEN1
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #elif defined(CONFIG_MPC8568)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		10
 #define CONFIG_SYS_FSL_DDRC_GEN2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define QE_MURAM_SIZE			0x10000UL
 #define MAX_QE_RISC			2
 #define QE_NUM_OF_SNUM			28
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	1
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CONFIG_SYS_FSL_RMU
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 #elif defined(CONFIG_MPC8569)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		10
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define QE_MURAM_SIZE			0x20000UL
 #define MAX_QE_RISC			4
 #define QE_NUM_OF_SNUM			46
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	1
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CONFIG_SYS_FSL_RMU
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #elif defined(CONFIG_MPC8572)
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #elif defined(CONFIG_P1010)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	3
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x10
 /* P1011 is single core version of P1020 */
 #elif defined(CONFIG_P1011)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 /* P1012 is single core version of P1021 */
 #elif defined(CONFIG_P1012)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 /* P1013 is single core version of P1022 */
 #elif defined(CONFIG_P1013)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_FSL_SATA_ERRATUM_A001
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #elif defined(CONFIG_P1014)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	3
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 /* P1017 is single core version of P1023 */
 #elif defined(CONFIG_P1017)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	2
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_QMAN_NUM_PORTALS	3
 #define CONFIG_SYS_BMAN_NUM_PORTALS	3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff600000
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #elif defined(CONFIG_P1020)
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #elif defined(CONFIG_P1021)
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #elif defined(CONFIG_P1022)
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_FSL_SATA_ERRATUM_A001
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #elif defined(CONFIG_P1023)
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	2
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_QMAN_NUM_PORTALS	3
 #define CONFIG_SYS_BMAN_NUM_PORTALS	3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff600000
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x11
 /* P1024 is lower end variant of P1020 */
 #elif defined(CONFIG_P1024)
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 /* P1025 is lower end variant of P1021 */
 #elif defined(CONFIG_P1025)
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 /* P2010 is single core version of P2020 */
 #elif defined(CONFIG_P2010)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #elif defined(CONFIG_P2020)
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CONFIG_SYS_FSL_RMU
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
 #define CONFIG_SYS_FSL_ERRATUM_USB14
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2	0x11
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x11
 #elif defined(CONFIG_PPC_P3041)
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
 #define CONFIG_SYS_FSL_ERRATUM_USB14
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2	0x11
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
 #define CONFIG_SYS_FSL_ERRATUM_A005812
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x20
 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_MAX_CPUS			8
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		2
 #define CONFIG_SYS_NUM_FM1_DTSEC	4
 #define CONFIG_SYS_NUM_FM2_DTSEC	4
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_SYS_NUM_FM2_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	2
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,p4080-pcie"
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
 #define CONFIG_SYS_P4080_ERRATUM_CPU22
 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CONFIG_SYS_FSL_RMU
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x20
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
 #define CONFIG_SYS_FSL_ERRATUM_A004580
 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
 #define CONFIG_SYS_FSL_ERRATUM_A005812
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x20
 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
 #define CONFIG_SYS_PPC64		/* 64-bit core */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	2
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_USB14
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x20
 #elif defined(CONFIG_PPC_P5040)
 #define CONFIG_SYS_PPC64
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	3
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		2
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_SYS_NUM_FM2_DTSEC	5
 #define CONFIG_SYS_NUM_FM2_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	2
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_USB14
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 #define CONFIG_SYS_FSL_ERRATUM_A004699
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 #define CONFIG_SYS_FSL_ERRATUM_A005812
 #elif defined(CONFIG_BSC9131)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR	0xb0000000
 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT	0xff600000
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #elif defined(CONFIG_BSC9132)
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	3
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_NUM_DDR_CONTROLLERS	2
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_FSL_DSP_DDR_ADDR	0x40000000
 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR	0xb0000000
 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR	0xc0000000
 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT	0xff600000
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x11
 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
 #define CONFIG_E6500
 #define CONFIG_SYS_PPC64		/* 64-bit core */
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
 #ifdef CONFIG_PPC_T4240
 #define CONFIG_MAX_CPUS			12
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 4 }
 #define CONFIG_SYS_NUM_FM1_DTSEC	8
 #define CONFIG_SYS_NUM_FM1_10GEC	2
 #define CONFIG_SYS_NUM_FM2_DTSEC	8
 #define CONFIG_SYS_NUM_FM2_10GEC	2
 #define CONFIG_NUM_DDR_CONTROLLERS	3
 #else
 #define CONFIG_MAX_CPUS			8
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1 }
 #define CONFIG_SYS_NUM_FM1_DTSEC	7
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_SYS_NUM_FM2_DTSEC	7
 #define CONFIG_SYS_NUM_FM2_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	2
 #endif
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	5
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_FSL_SRDS_3
 #define CONFIG_SYS_FSL_SRDS_4
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		2
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_PME_CLK		0
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM1_CLK		3
 #define CONFIG_SYS_FM2_CLK		3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v3.0"
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CONFIG_SYS_FSL_SRIO_LIODN
 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_A004468
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
 #define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_PCI_VER_3_X
 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
 #define CONFIG_E6500
 #define CONFIG_SYS_PPC64		/* 64-bit core */
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_FM1_CLK		0
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
 #define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #ifdef CONFIG_PPC_B4860
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
 #define CONFIG_SYS_NUM_FM1_DTSEC	6
 #define CONFIG_SYS_NUM_FM1_10GEC	2
 #define CONFIG_NUM_DDR_CONTROLLERS	2
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CONFIG_SYS_FSL_SRIO_LIODN
 #else
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4 }
 #define CONFIG_SYS_NUM_FM1_DTSEC	4
 #define CONFIG_SYS_NUM_FM1_10GEC	0
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #endif
 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_E5500
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
 #define CONFIG_MAX_CPUS			4
 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_MAX_CPUS			2
 #endif
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 1, 1 }
 #define CONFIG_SYS_SDHC_CLOCK		0
 #define CONFIG_SYS_FSL_NUM_LAWS		16
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_SEC_COMPAT	5
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_PME_PLAT_CLK_DIV		2
 #define CONFIG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_FM_PLAT_CLK_DIV	1
 #define CONFIG_SYS_FM1_CLK		CONFIG_FM_PLAT_CLK_DIV
 #define CONFIG_SYS_FM_MURAM_SIZE	0x30000
+#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
 #define CONFIG_E6500
 #define CONFIG_SYS_PPC64		/* 64-bit core */
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 #define CONFIG_SYS_FSL_QMAN_V3
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_PCI_VER_3_X
 #if defined(CONFIG_PPC_T2080)
 #define CONFIG_SYS_NUM_FM1_DTSEC	8
 #define CONFIG_SYS_NUM_FM1_10GEC	4
 #define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_FSL_SRIO_LIODN
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #elif defined(CONFIG_PPC_T2081)
 #define CONFIG_SYS_NUM_FM1_DTSEC	6
 #define CONFIG_SYS_NUM_FM1_10GEC	2
 #endif
-#define CONFIG_SYS_FSL_NUM_USB_CTRLS	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_PME_PLAT_CLK_DIV		1
 #define CONFIG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
 #define CONFIG_SYS_FM1_CLK		0
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v3.0"
 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 #define CONFIG_SYS_FSL_ISBC_VER		2
 #elif defined(CONFIG_PPC_C29X)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	3
 #define CONFIG_TSECV2_1
 #define CONFIG_SYS_FSL_SEC_COMPAT	6
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #else
 #error Processor type not defined for this platform
 #endif
 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
 #endif
 #ifdef CONFIG_E6500
 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
 #else
 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
 #endif
 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
 	!defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
 	!defined(CONFIG_SYS_FSL_DDRC_GEN3)
 #define CONFIG_SYS_FSL_DDRC_GEN3
 #endif
 #endif /* _ASM_MPC85xx_CONFIG_H_ */

arch/powerpc/include/asm/immap_85xx.h

Diff comments View file @ e7be182

 /*
  * MPC85xx Internal Memory Map
  *
  * Copyright 2007-2012 Freescale Semiconductor, Inc.
  *
  * Copyright(c) 2002,2003 Motorola Inc.
  * Xianghua Xiao (x.xiao@motorola.com)
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __IMMAP_85xx__
 #define __IMMAP_85xx__
 #include <asm/types.h>
 #include <asm/fsl_dma.h>
 #include <asm/fsl_i2c.h>
 #include <fsl_ifc.h>
 #include <asm/fsl_lbc.h>
 #include <asm/fsl_fman.h>
 #include <fsl_immap.h>
 typedef struct ccsr_local {
 	u32	ccsrbarh;	/* CCSR Base Addr High */
 	u32	ccsrbarl;	/* CCSR Base Addr Low */
 	u32	ccsrar;		/* CCSR Attr */
 #define CCSRAR_C	0x80000000	/* Commit */
 	u8	res1[4];
 	u32	altcbarh;	/* Alternate Configuration Base Addr High */
 	u32	altcbarl;	/* Alternate Configuration Base Addr Low */
 	u32	altcar;		/* Alternate Configuration Attr */
 	u8	res2[4];
 	u32	bstrh;		/* Boot space translation high */
 	u32	bstrl;		/* Boot space translation Low */
 	u32	bstrar;		/* Boot space translation attributes */
 	u8	res3[0xbd4];
 	struct {
 		u32	lawbarh;	/* LAWn base addr high */
 		u32	lawbarl;	/* LAWn base addr low */
 		u32	lawar;		/* LAWn attributes */
 		u8	res4[4];
 	} law[32];
 	u8	res35[0x204];
 } ccsr_local_t;
 /* Local-Access Registers & ECM Registers */
 typedef struct ccsr_local_ecm {
 	u32	ccsrbar;	/* CCSR Base Addr */
 	u8	res1[4];
 	u32	altcbar;	/* Alternate Configuration Base Addr */
 	u8	res2[4];
 	u32	altcar;		/* Alternate Configuration Attr */
 	u8	res3[12];
 	u32	bptr;		/* Boot Page Translation */
 	u8	res4[3044];
 	u32	lawbar0;	/* Local Access Window 0 Base Addr */
 	u8	res5[4];
 	u32	lawar0;		/* Local Access Window 0 Attrs */
 	u8	res6[20];
 	u32	lawbar1;	/* Local Access Window 1 Base Addr */
 	u8	res7[4];
 	u32	lawar1;		/* Local Access Window 1 Attrs */
 	u8	res8[20];
 	u32	lawbar2;	/* Local Access Window 2 Base Addr */
 	u8	res9[4];
 	u32	lawar2;		/* Local Access Window 2 Attrs */
 	u8	res10[20];
 	u32	lawbar3;	/* Local Access Window 3 Base Addr */
 	u8	res11[4];
 	u32	lawar3;		/* Local Access Window 3 Attrs */
 	u8	res12[20];
 	u32	lawbar4;	/* Local Access Window 4 Base Addr */
 	u8	res13[4];
 	u32	lawar4;		/* Local Access Window 4 Attrs */
 	u8	res14[20];
 	u32	lawbar5;	/* Local Access Window 5 Base Addr */
 	u8	res15[4];
 	u32	lawar5;		/* Local Access Window 5 Attrs */
 	u8	res16[20];
 	u32	lawbar6;	/* Local Access Window 6 Base Addr */
 	u8	res17[4];
 	u32	lawar6;		/* Local Access Window 6 Attrs */
 	u8	res18[20];
 	u32	lawbar7;	/* Local Access Window 7 Base Addr */
 	u8	res19[4];
 	u32	lawar7;		/* Local Access Window 7 Attrs */
 	u8	res19_8a[20];
 	u32	lawbar8;	/* Local Access Window 8 Base Addr */
 	u8	res19_8b[4];
 	u32	lawar8;		/* Local Access Window 8 Attrs */
 	u8	res19_9a[20];
 	u32	lawbar9;	/* Local Access Window 9 Base Addr */
 	u8	res19_9b[4];
 	u32	lawar9;		/* Local Access Window 9 Attrs */
 	u8	res19_10a[20];
 	u32	lawbar10;	/* Local Access Window 10 Base Addr */
 	u8	res19_10b[4];
 	u32	lawar10;	/* Local Access Window 10 Attrs */
 	u8	res19_11a[20];
 	u32	lawbar11;	/* Local Access Window 11 Base Addr */
 	u8	res19_11b[4];
 	u32	lawar11;	/* Local Access Window 11 Attrs */
 	u8	res20[652];
 	u32	eebacr;		/* ECM CCB Addr Configuration */
 	u8	res21[12];
 	u32	eebpcr;		/* ECM CCB Port Configuration */
 	u8	res22[3564];
 	u32	eedr;		/* ECM Error Detect */
 	u8	res23[4];
 	u32	eeer;		/* ECM Error Enable */
 	u32	eeatr;		/* ECM Error Attrs Capture */
 	u32	eeadr;		/* ECM Error Addr Capture */
 	u8	res24[492];
 } ccsr_local_ecm_t;
 #define DDR_EOR_RD_BDW_OPT_DIS	0x80000000 /* Read BDW Opt. disable */
 #define DDR_EOR_ADDR_HASH_EN	0x40000000 /* Address hash enabled */
 /* I2C Registers */
 typedef struct ccsr_i2c {
 	struct fsl_i2c	i2c[1];
 	u8	res[4096 - 1 * sizeof(struct fsl_i2c)];
 } ccsr_i2c_t;
 #if defined(CONFIG_MPC8540) \
 	|| defined(CONFIG_MPC8541) \
 	|| defined(CONFIG_MPC8548) \
 	|| defined(CONFIG_MPC8555)
 /* DUART Registers */
 typedef struct ccsr_duart {
 	u8	res1[1280];
 /* URBR1, UTHR1, UDLB1 with the same addr */
 	u8	urbr1_uthr1_udlb1;
 /* UIER1, UDMB1 with the same addr01 */
 	u8	uier1_udmb1;
 /* UIIR1, UFCR1, UAFR1 with the same addr */
 	u8	uiir1_ufcr1_uafr1;
 	u8	ulcr1;		/* UART1 Line Control */
 	u8	umcr1;		/* UART1 Modem Control */
 	u8	ulsr1;		/* UART1 Line Status */
 	u8	umsr1;		/* UART1 Modem Status */
 	u8	uscr1;		/* UART1 Scratch */
 	u8	res2[8];
 	u8	udsr1;		/* UART1 DMA Status */
 	u8	res3[239];
 /* URBR2, UTHR2, UDLB2 with the same addr */
 	u8	urbr2_uthr2_udlb2;
 /* UIER2, UDMB2 with the same addr */
 	u8	uier2_udmb2;
 /* UIIR2, UFCR2, UAFR2 with the same addr */
 	u8	uiir2_ufcr2_uafr2;
 	u8	ulcr2;		/* UART2 Line Control */
 	u8	umcr2;		/* UART2 Modem Control */
 	u8	ulsr2;		/* UART2 Line Status */
 	u8	umsr2;		/* UART2 Modem Status */
 	u8	uscr2;		/* UART2 Scratch */
 	u8	res4[8];
 	u8	udsr2;		/* UART2 DMA Status */
 	u8	res5[2543];
 } ccsr_duart_t;
 #else /* MPC8560 uses UART on its CPM */
 typedef struct ccsr_duart {
 	u8 res[4096];
 } ccsr_duart_t;
 #endif
 /* eSPI Registers */
 typedef struct ccsr_espi {
 	u32	mode;		/* eSPI mode */
 	u32	event;		/* eSPI event */
 	u32	mask;		/* eSPI mask */
 	u32	com;		/* eSPI command */
 	u32	tx;		/* eSPI transmit FIFO access */
 	u32	rx;		/* eSPI receive FIFO access */
 	u8	res1[8];	/* reserved */
 	u32	csmode[4];	/* 0x2c: sSPI CS0/1/2/3 mode */
 	u8	res2[4048];	/* fill up to 0x1000 */
 } ccsr_espi_t;
 /* PCI Registers */
 typedef struct ccsr_pcix {
 	u32	cfg_addr;	/* PCIX Configuration Addr */
 	u32	cfg_data;	/* PCIX Configuration Data */
 	u32	int_ack;	/* PCIX IRQ Acknowledge */
 	u8	res000c[52];
 	u32	liodn_base;	/* PCIX LIODN base register */
 	u8	res0044[2996];
 	u32	ipver1;		/* PCIX IP block revision register 1 */
 	u32	ipver2;		/* PCIX IP block revision register 2 */
 	u32	potar0;		/* PCIX Outbound Transaction Addr 0 */
 	u32	potear0;	/* PCIX Outbound Translation Extended Addr 0 */
 	u32	powbar0;	/* PCIX Outbound Window Base Addr 0 */
 	u32	powbear0;	/* PCIX Outbound Window Base Extended Addr 0 */
 	u32	powar0;		/* PCIX Outbound Window Attrs 0 */
 	u8	res2[12];
 	u32	potar1;		/* PCIX Outbound Transaction Addr 1 */
 	u32	potear1;	/* PCIX Outbound Translation Extended Addr 1 */
 	u32	powbar1;	/* PCIX Outbound Window Base Addr 1 */
 	u32	powbear1;	/* PCIX Outbound Window Base Extended Addr 1 */
 	u32	powar1;		/* PCIX Outbound Window Attrs 1 */
 	u8	res3[12];
 	u32	potar2;		/* PCIX Outbound Transaction Addr 2 */
 	u32	potear2;	/* PCIX Outbound Translation Extended Addr 2 */
 	u32	powbar2;	/* PCIX Outbound Window Base Addr 2 */
 	u32	powbear2;	/* PCIX Outbound Window Base Extended Addr 2 */
 	u32	powar2;		/* PCIX Outbound Window Attrs 2 */
 	u8	res4[12];
 	u32	potar3;		/* PCIX Outbound Transaction Addr 3 */
 	u32	potear3;	/* PCIX Outbound Translation Extended Addr 3 */
 	u32	powbar3;	/* PCIX Outbound Window Base Addr 3 */
 	u32	powbear3;	/* PCIX Outbound Window Base Extended Addr 3 */
 	u32	powar3;		/* PCIX Outbound Window Attrs 3 */
 	u8	res5[12];
 	u32	potar4;		/* PCIX Outbound Transaction Addr 4 */
 	u32	potear4;	/* PCIX Outbound Translation Extended Addr 4 */
 	u32	powbar4;	/* PCIX Outbound Window Base Addr 4 */
 	u32	powbear4;	/* PCIX Outbound Window Base Extended Addr 4 */
 	u32	powar4;		/* PCIX Outbound Window Attrs 4 */
 	u8	res6[268];
 	u32	pitar3;		/* PCIX Inbound Translation Addr 3 */
 	u32	pitear3;	/* PCIX Inbound Translation Extended Addr 3 */
 	u32	piwbar3;	/* PCIX Inbound Window Base Addr 3 */
 	u32	piwbear3;	/* PCIX Inbound Window Base Extended Addr 3 */
 	u32	piwar3;		/* PCIX Inbound Window Attrs 3 */
 	u8	res7[12];
 	u32	pitar2;		/* PCIX Inbound Translation Addr 2 */
 	u32	pitear2;	/* PCIX Inbound Translation Extended Addr 2 */
 	u32	piwbar2;	/* PCIX Inbound Window Base Addr 2 */
 	u32	piwbear2;	/* PCIX Inbound Window Base Extended Addr 2 */
 	u32	piwar2;		/* PCIX Inbound Window Attrs 2 */
 	u8	res8[12];
 	u32	pitar1;		/* PCIX Inbound Translation Addr 1 */
 	u32	pitear1;	/* PCIX Inbound Translation Extended Addr 1 */
 	u32	piwbar1;	/* PCIX Inbound Window Base Addr 1 */
 	u8	res9[4];
 	u32	piwar1;		/* PCIX Inbound Window Attrs 1 */
 	u8	res10[12];
 	u32	pedr;		/* PCIX Error Detect */
 	u32	pecdr;		/* PCIX Error Capture Disable */
 	u32	peer;		/* PCIX Error Enable */
 	u32	peattrcr;	/* PCIX Error Attrs Capture */
 	u32	peaddrcr;	/* PCIX Error Addr Capture */
 	u32	peextaddrcr;	/* PCIX Error Extended Addr Capture */
 	u32	pedlcr;		/* PCIX Error Data Low Capture */
 	u32	pedhcr;		/* PCIX Error Error Data High Capture */
 	u32	gas_timr;	/* PCIX Gasket Timer */
 	u8	res11[476];
 } ccsr_pcix_t;
 #define PCIX_COMMAND	0x62
 #define POWAR_EN	0x80000000
 #define POWAR_IO_READ	0x00080000
 #define POWAR_MEM_READ	0x00040000
 #define POWAR_IO_WRITE	0x00008000
 #define POWAR_MEM_WRITE	0x00004000
 #define POWAR_MEM_512M	0x0000001c
 #define POWAR_IO_1M	0x00000013
 #define PIWAR_EN	0x80000000
 #define PIWAR_PF	0x20000000
 #define PIWAR_LOCAL	0x00f00000
 #define PIWAR_READ_SNOOP	0x00050000
 #define PIWAR_WRITE_SNOOP	0x00005000
 #define PIWAR_MEM_2G		0x0000001e
 typedef struct ccsr_gpio {
 	u32	gpdir;
 	u32	gpodr;
 	u32	gpdat;
 	u32	gpier;
 	u32	gpimr;
 	u32	gpicr;
 } ccsr_gpio_t;
 /* L2 Cache Registers */
 typedef struct ccsr_l2cache {
 	u32	l2ctl;		/* L2 configuration 0 */
 	u8	res1[12];
 	u32	l2cewar0;	/* L2 cache external write addr 0 */
 	u8	res2[4];
 	u32	l2cewcr0;	/* L2 cache external write control 0 */
 	u8	res3[4];
 	u32	l2cewar1;	/* L2 cache external write addr 1 */
 	u8	res4[4];
 	u32	l2cewcr1;	/* L2 cache external write control 1 */
 	u8	res5[4];
 	u32	l2cewar2;	/* L2 cache external write addr 2 */
 	u8	res6[4];
 	u32	l2cewcr2;	/* L2 cache external write control 2 */
 	u8	res7[4];
 	u32	l2cewar3;	/* L2 cache external write addr 3 */
 	u8	res8[4];
 	u32	l2cewcr3;	/* L2 cache external write control 3 */
 	u8	res9[180];
 	u32	l2srbar0;	/* L2 memory-mapped SRAM base addr 0 */
 	u8	res10[4];
 	u32	l2srbar1;	/* L2 memory-mapped SRAM base addr 1 */
 	u8	res11[3316];
 	u32	l2errinjhi;	/* L2 error injection mask high */
 	u32	l2errinjlo;	/* L2 error injection mask low */
 	u32	l2errinjctl;	/* L2 error injection tag/ECC control */
 	u8	res12[20];
 	u32	l2captdatahi;	/* L2 error data high capture */
 	u32	l2captdatalo;	/* L2 error data low capture */
 	u32	l2captecc;	/* L2 error ECC capture */
 	u8	res13[20];
 	u32	l2errdet;	/* L2 error detect */
 	u32	l2errdis;	/* L2 error disable */
 	u32	l2errinten;	/* L2 error interrupt enable */
 	u32	l2errattr;	/* L2 error attributes capture */
 	u32	l2erraddr;	/* L2 error addr capture */
 	u8	res14[4];
 	u32	l2errctl;	/* L2 error control */
 	u8	res15[420];
 } ccsr_l2cache_t;
 #define MPC85xx_L2CTL_L2E			0x80000000
 #define MPC85xx_L2CTL_L2SRAM_ENTIRE		0x00010000
 #define MPC85xx_L2ERRDIS_MBECC			0x00000008
 #define MPC85xx_L2ERRDIS_SBECC			0x00000004
 /* DMA Registers */
 typedef struct ccsr_dma {
 	u8	res1[256];
 	struct fsl_dma dma[4];
 	u32	dgsr;		/* DMA General Status */
 	u8	res2[11516];
 } ccsr_dma_t;
 /* tsec */
 typedef struct ccsr_tsec {
 	u8	res1[16];
 	u32	ievent;		/* IRQ Event */
 	u32	imask;		/* IRQ Mask */
 	u32	edis;		/* Error Disabled */
 	u8	res2[4];
 	u32	ecntrl;		/* Ethernet Control */
 	u32	minflr;		/* Minimum Frame Len */
 	u32	ptv;		/* Pause Time Value */
 	u32	dmactrl;	/* DMA Control */
 	u32	tbipa;		/* TBI PHY Addr */
 	u8	res3[88];
 	u32	fifo_tx_thr;		/* FIFO transmit threshold */
 	u8	res4[8];
 	u32	fifo_tx_starve;		/* FIFO transmit starve */
 	u32	fifo_tx_starve_shutoff;	/* FIFO transmit starve shutoff */
 	u8	res5[96];
 	u32	tctrl;		/* TX Control */
 	u32	tstat;		/* TX Status */
 	u8	res6[4];
 	u32	tbdlen;		/* TX Buffer Desc Data Len */
 	u8	res7[16];
 	u32	ctbptrh;	/* Current TX Buffer Desc Ptr High */
 	u32	ctbptr;		/* Current TX Buffer Desc Ptr */
 	u8	res8[88];
 	u32	tbptrh;		/* TX Buffer Desc Ptr High */
 	u32	tbptr;		/* TX Buffer Desc Ptr Low */
 	u8	res9[120];
 	u32	tbaseh;		/* TX Desc Base Addr High */
 	u32	tbase;		/* TX Desc Base Addr */
 	u8	res10[168];
 	u32	ostbd;		/* Out-of-Sequence(OOS) TX Buffer Desc */
 	u32	ostbdp;		/* OOS TX Data Buffer Ptr */
 	u32	os32tbdp;	/* OOS 32 Bytes TX Data Buffer Ptr Low */
 	u32	os32iptrh;	/* OOS 32 Bytes TX Insert Ptr High */
 	u32	os32iptrl;	/* OOS 32 Bytes TX Insert Ptr Low */
 	u32	os32tbdr;	/* OOS 32 Bytes TX Reserved */
 	u32	os32iil;	/* OOS 32 Bytes TX Insert Idx/Len */
 	u8	res11[52];
 	u32	rctrl;		/* RX Control */
 	u32	rstat;		/* RX Status */
 	u8	res12[4];
 	u32	rbdlen;		/* RxBD Data Len */
 	u8	res13[16];
 	u32	crbptrh;	/* Current RX Buffer Desc Ptr High */
 	u32	crbptr;		/* Current RX Buffer Desc Ptr */
 	u8	res14[24];
 	u32	mrblr;		/* Maximum RX Buffer Len */
 	u32	mrblr2r3;	/* Maximum RX Buffer Len R2R3 */
 	u8	res15[56];
 	u32	rbptrh;		/* RX Buffer Desc Ptr High 0 */
 	u32	rbptr;		/* RX Buffer Desc Ptr */
 	u32	rbptrh1;	/* RX Buffer Desc Ptr High 1 */
 	u32	rbptrl1;	/* RX Buffer Desc Ptr Low 1 */
 	u32	rbptrh2;	/* RX Buffer Desc Ptr High 2 */
 	u32	rbptrl2;	/* RX Buffer Desc Ptr Low 2 */
 	u32	rbptrh3;	/* RX Buffer Desc Ptr High 3 */
 	u32	rbptrl3;	/* RX Buffer Desc Ptr Low 3 */
 	u8	res16[96];
 	u32	rbaseh;		/* RX Desc Base Addr High 0 */
 	u32	rbase;		/* RX Desc Base Addr */
 	u32	rbaseh1;	/* RX Desc Base Addr High 1 */
 	u32	rbasel1;	/* RX Desc Base Addr Low 1 */
 	u32	rbaseh2;	/* RX Desc Base Addr High 2 */
 	u32	rbasel2;	/* RX Desc Base Addr Low 2 */
 	u32	rbaseh3;	/* RX Desc Base Addr High 3 */
 	u32	rbasel3;	/* RX Desc Base Addr Low 3 */
 	u8	res17[224];
 	u32	maccfg1;	/* MAC Configuration 1 */
 	u32	maccfg2;	/* MAC Configuration 2 */
 	u32	ipgifg;		/* Inter Packet Gap/Inter Frame Gap */
 	u32	hafdup;		/* Half Duplex */
 	u32	maxfrm;		/* Maximum Frame Len */
 	u8	res18[12];
 	u32	miimcfg;	/* MII Management Configuration */
 	u32	miimcom;	/* MII Management Cmd */
 	u32	miimadd;	/* MII Management Addr */
 	u32	miimcon;	/* MII Management Control */
 	u32	miimstat;	/* MII Management Status */
 	u32	miimind;	/* MII Management Indicator */
 	u8	res19[4];
 	u32	ifstat;		/* Interface Status */
 	u32	macstnaddr1;	/* Station Addr Part 1 */
 	u32	macstnaddr2;	/* Station Addr Part 2 */
 	u8	res20[312];
 	u32	tr64;		/* TX & RX 64-byte Frame Counter */
 	u32	tr127;		/* TX & RX 65-127 byte Frame Counter */
 	u32	tr255;		/* TX & RX 128-255 byte Frame Counter */
 	u32	tr511;		/* TX & RX 256-511 byte Frame Counter */
 	u32	tr1k;		/* TX & RX 512-1023 byte Frame Counter */
 	u32	trmax;		/* TX & RX 1024-1518 byte Frame Counter */
 	u32	trmgv;		/* TX & RX 1519-1522 byte Good VLAN Frame */
 	u32	rbyt;		/* RX Byte Counter */
 	u32	rpkt;		/* RX Packet Counter */
 	u32	rfcs;		/* RX FCS Error Counter */
 	u32	rmca;		/* RX Multicast Packet Counter */
 	u32	rbca;		/* RX Broadcast Packet Counter */
 	u32	rxcf;		/* RX Control Frame Packet Counter */
 	u32	rxpf;		/* RX Pause Frame Packet Counter */
 	u32	rxuo;		/* RX Unknown OP Code Counter */
 	u32	raln;		/* RX Alignment Error Counter */
 	u32	rflr;		/* RX Frame Len Error Counter */
 	u32	rcde;		/* RX Code Error Counter */
 	u32	rcse;		/* RX Carrier Sense Error Counter */
 	u32	rund;		/* RX Undersize Packet Counter */
 	u32	rovr;		/* RX Oversize Packet Counter */
 	u32	rfrg;		/* RX Fragments Counter */
 	u32	rjbr;		/* RX Jabber Counter */
 	u32	rdrp;		/* RX Drop Counter */
 	u32	tbyt;		/* TX Byte Counter Counter */
 	u32	tpkt;		/* TX Packet Counter */
 	u32	tmca;		/* TX Multicast Packet Counter */
 	u32	tbca;		/* TX Broadcast Packet Counter */
 	u32	txpf;		/* TX Pause Control Frame Counter */
 	u32	tdfr;		/* TX Deferral Packet Counter */
 	u32	tedf;		/* TX Excessive Deferral Packet Counter */
 	u32	tscl;		/* TX Single Collision Packet Counter */
 	u32	tmcl;		/* TX Multiple Collision Packet Counter */
 	u32	tlcl;		/* TX Late Collision Packet Counter */
 	u32	txcl;		/* TX Excessive Collision Packet Counter */
 	u32	tncl;		/* TX Total Collision Counter */
 	u8	res21[4];
 	u32	tdrp;		/* TX Drop Frame Counter */
 	u32	tjbr;		/* TX Jabber Frame Counter */
 	u32	tfcs;		/* TX FCS Error Counter */
 	u32	txcf;		/* TX Control Frame Counter */
 	u32	tovr;		/* TX Oversize Frame Counter */
 	u32	tund;		/* TX Undersize Frame Counter */
 	u32	tfrg;		/* TX Fragments Frame Counter */
 	u32	car1;		/* Carry One */
 	u32	car2;		/* Carry Two */
 	u32	cam1;		/* Carry Mask One */
 	u32	cam2;		/* Carry Mask Two */
 	u8	res22[192];
 	u32	iaddr0;		/* Indivdual addr 0 */
 	u32	iaddr1;		/* Indivdual addr 1 */
 	u32	iaddr2;		/* Indivdual addr 2 */
 	u32	iaddr3;		/* Indivdual addr 3 */
 	u32	iaddr4;		/* Indivdual addr 4 */
 	u32	iaddr5;		/* Indivdual addr 5 */
 	u32	iaddr6;		/* Indivdual addr 6 */
 	u32	iaddr7;		/* Indivdual addr 7 */
 	u8	res23[96];
 	u32	gaddr0;		/* Global addr 0 */
 	u32	gaddr1;		/* Global addr 1 */
 	u32	gaddr2;		/* Global addr 2 */
 	u32	gaddr3;		/* Global addr 3 */
 	u32	gaddr4;		/* Global addr 4 */
 	u32	gaddr5;		/* Global addr 5 */
 	u32	gaddr6;		/* Global addr 6 */
 	u32	gaddr7;		/* Global addr 7 */
 	u8	res24[96];
 	u32	pmd0;		/* Pattern Match Data */
 	u8	res25[4];
 	u32	pmask0;		/* Pattern Mask */
 	u8	res26[4];
 	u32	pcntrl0;	/* Pattern Match Control */
 	u8	res27[4];
 	u32	pattrb0;	/* Pattern Match Attrs */
 	u32	pattrbeli0;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd1;		/* Pattern Match Data */
 	u8	res28[4];
 	u32	pmask1;		/* Pattern Mask */
 	u8	res29[4];
 	u32	pcntrl1;	/* Pattern Match Control */
 	u8	res30[4];
 	u32	pattrb1;	/* Pattern Match Attrs */
 	u32	pattrbeli1;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd2;		/* Pattern Match Data */
 	u8	res31[4];
 	u32	pmask2;		/* Pattern Mask */
 	u8	res32[4];
 	u32	pcntrl2;	/* Pattern Match Control */
 	u8	res33[4];
 	u32	pattrb2;	/* Pattern Match Attrs */
 	u32	pattrbeli2;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd3;		/* Pattern Match Data */
 	u8	res34[4];
 	u32	pmask3;		/* Pattern Mask */
 	u8	res35[4];
 	u32	pcntrl3;	/* Pattern Match Control */
 	u8	res36[4];
 	u32	pattrb3;	/* Pattern Match Attrs */
 	u32	pattrbeli3;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd4;		/* Pattern Match Data */
 	u8	res37[4];
 	u32	pmask4;		/* Pattern Mask */
 	u8	res38[4];
 	u32	pcntrl4;	/* Pattern Match Control */
 	u8	res39[4];
 	u32	pattrb4;	/* Pattern Match Attrs */
 	u32	pattrbeli4;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd5;		/* Pattern Match Data */
 	u8	res40[4];
 	u32	pmask5;		/* Pattern Mask */
 	u8	res41[4];
 	u32	pcntrl5;	/* Pattern Match Control */
 	u8	res42[4];
 	u32	pattrb5;	/* Pattern Match Attrs */
 	u32	pattrbeli5;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd6;		/* Pattern Match Data */
 	u8	res43[4];
 	u32	pmask6;		/* Pattern Mask */
 	u8	res44[4];
 	u32	pcntrl6;	/* Pattern Match Control */
 	u8	res45[4];
 	u32	pattrb6;	/* Pattern Match Attrs */
 	u32	pattrbeli6;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd7;		/* Pattern Match Data */
 	u8	res46[4];
 	u32	pmask7;		/* Pattern Mask */
 	u8	res47[4];
 	u32	pcntrl7;	/* Pattern Match Control */
 	u8	res48[4];
 	u32	pattrb7;	/* Pattern Match Attrs */
 	u32	pattrbeli7;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd8;		/* Pattern Match Data */
 	u8	res49[4];
 	u32	pmask8;		/* Pattern Mask */
 	u8	res50[4];
 	u32	pcntrl8;	/* Pattern Match Control */
 	u8	res51[4];
 	u32	pattrb8;	/* Pattern Match Attrs */
 	u32	pattrbeli8;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd9;		/* Pattern Match Data */
 	u8	res52[4];
 	u32	pmask9;		/* Pattern Mask */
 	u8	res53[4];
 	u32	pcntrl9;	/* Pattern Match Control */
 	u8	res54[4];
 	u32	pattrb9;	/* Pattern Match Attrs */
 	u32	pattrbeli9;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd10;		/* Pattern Match Data */
 	u8	res55[4];
 	u32	pmask10;	/* Pattern Mask */
 	u8	res56[4];
 	u32	pcntrl10;	/* Pattern Match Control */
 	u8	res57[4];
 	u32	pattrb10;	/* Pattern Match Attrs */
 	u32	pattrbeli10;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd11;		/* Pattern Match Data */
 	u8	res58[4];
 	u32	pmask11;	/* Pattern Mask */
 	u8	res59[4];
 	u32	pcntrl11;	/* Pattern Match Control */
 	u8	res60[4];
 	u32	pattrb11;	/* Pattern Match Attrs */
 	u32	pattrbeli11;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd12;		/* Pattern Match Data */
 	u8	res61[4];
 	u32	pmask12;	/* Pattern Mask */
 	u8	res62[4];
 	u32	pcntrl12;	/* Pattern Match Control */
 	u8	res63[4];
 	u32	pattrb12;	/* Pattern Match Attrs */
 	u32	pattrbeli12;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd13;		/* Pattern Match Data */
 	u8	res64[4];
 	u32	pmask13;	/* Pattern Mask */
 	u8	res65[4];
 	u32	pcntrl13;	/* Pattern Match Control */
 	u8	res66[4];
 	u32	pattrb13;	/* Pattern Match Attrs */
 	u32	pattrbeli13;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd14;		/* Pattern Match Data */
 	u8	res67[4];
 	u32	pmask14;	/* Pattern Mask */
 	u8	res68[4];
 	u32	pcntrl14;	/* Pattern Match Control */
 	u8	res69[4];
 	u32	pattrb14;	/* Pattern Match Attrs */
 	u32	pattrbeli14;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd15;		/* Pattern Match Data */
 	u8	res70[4];
 	u32	pmask15;	/* Pattern Mask */
 	u8	res71[4];
 	u32	pcntrl15;	/* Pattern Match Control */
 	u8	res72[4];
 	u32	pattrb15;	/* Pattern Match Attrs */
 	u32	pattrbeli15;	/* Pattern Match Attrs Extract Len & Idx */
 	u8	res73[248];
 	u32	attr;		/* Attrs */
 	u32	attreli;	/* Attrs Extract Len & Idx */
 	u8	res74[1024];
 } ccsr_tsec_t;
 /* PIC Registers */
 typedef struct ccsr_pic {
 	u8	res1[64];
 	u32	ipidr0;		/* Interprocessor IRQ Dispatch 0 */
 	u8	res2[12];
 	u32	ipidr1;		/* Interprocessor IRQ Dispatch 1 */
 	u8	res3[12];
 	u32	ipidr2;		/* Interprocessor IRQ Dispatch 2 */
 	u8	res4[12];
 	u32	ipidr3;		/* Interprocessor IRQ Dispatch 3 */
 	u8	res5[12];
 	u32	ctpr;		/* Current Task Priority */
 	u8	res6[12];
 	u32	whoami;		/* Who Am I */
 	u8	res7[12];
 	u32	iack;		/* IRQ Acknowledge */
 	u8	res8[12];
 	u32	eoi;		/* End Of IRQ */
 	u8	res9[3916];
 	u32	frr;		/* Feature Reporting */
 	u8	res10[28];
 	u32	gcr;		/* Global Configuration */
 #define MPC85xx_PICGCR_RST	0x80000000
 #define MPC85xx_PICGCR_M	0x20000000
 	u8	res11[92];
 	u32	vir;		/* Vendor Identification */
 	u8	res12[12];
 	u32	pir;		/* Processor Initialization */
 	u8	res13[12];
 	u32	ipivpr0;	/* IPI Vector/Priority 0 */
 	u8	res14[12];
 	u32	ipivpr1;	/* IPI Vector/Priority 1 */
 	u8	res15[12];
 	u32	ipivpr2;	/* IPI Vector/Priority 2 */
 	u8	res16[12];
 	u32	ipivpr3;	/* IPI Vector/Priority 3 */
 	u8	res17[12];
 	u32	svr;		/* Spurious Vector */
 	u8	res18[12];
 	u32	tfrr;		/* Timer Frequency Reporting */
 	u8	res19[12];
 	u32	gtccr0;		/* Global Timer Current Count 0 */
 	u8	res20[12];
 	u32	gtbcr0;		/* Global Timer Base Count 0 */
 	u8	res21[12];
 	u32	gtvpr0;		/* Global Timer Vector/Priority 0 */
 	u8	res22[12];
 	u32	gtdr0;		/* Global Timer Destination 0 */
 	u8	res23[12];
 	u32	gtccr1;		/* Global Timer Current Count 1 */
 	u8	res24[12];
 	u32	gtbcr1;		/* Global Timer Base Count 1 */
 	u8	res25[12];
 	u32	gtvpr1;		/* Global Timer Vector/Priority 1 */
 	u8	res26[12];
 	u32	gtdr1;		/* Global Timer Destination 1 */
 	u8	res27[12];
 	u32	gtccr2;		/* Global Timer Current Count 2 */
 	u8	res28[12];
 	u32	gtbcr2;		/* Global Timer Base Count 2 */
 	u8	res29[12];
 	u32	gtvpr2;		/* Global Timer Vector/Priority 2 */
 	u8	res30[12];
 	u32	gtdr2;		/* Global Timer Destination 2 */
 	u8	res31[12];
 	u32	gtccr3;		/* Global Timer Current Count 3 */
 	u8	res32[12];
 	u32	gtbcr3;		/* Global Timer Base Count 3 */
 	u8	res33[12];
 	u32	gtvpr3;		/* Global Timer Vector/Priority 3 */
 	u8	res34[12];
 	u32	gtdr3;		/* Global Timer Destination 3 */
 	u8	res35[268];
 	u32	tcr;		/* Timer Control */
 	u8	res36[12];
 	u32	irqsr0;		/* IRQ_OUT Summary 0 */
 	u8	res37[12];
 	u32	irqsr1;		/* IRQ_OUT Summary 1 */
 	u8	res38[12];
 	u32	cisr0;		/* Critical IRQ Summary 0 */
 	u8	res39[12];
 	u32	cisr1;		/* Critical IRQ Summary 1 */
 	u8	res40[188];
 	u32	msgr0;		/* Message 0 */
 	u8	res41[12];
 	u32	msgr1;		/* Message 1 */
 	u8	res42[12];
 	u32	msgr2;		/* Message 2 */
 	u8	res43[12];
 	u32	msgr3;		/* Message 3 */
 	u8	res44[204];
 	u32	mer;		/* Message Enable */
 	u8	res45[12];
 	u32	msr;		/* Message Status */
 	u8	res46[60140];
 	u32	eivpr0;		/* External IRQ Vector/Priority 0 */
 	u8	res47[12];
 	u32	eidr0;		/* External IRQ Destination 0 */
 	u8	res48[12];
 	u32	eivpr1;		/* External IRQ Vector/Priority 1 */
 	u8	res49[12];
 	u32	eidr1;		/* External IRQ Destination 1 */
 	u8	res50[12];
 	u32	eivpr2;		/* External IRQ Vector/Priority 2 */
 	u8	res51[12];
 	u32	eidr2;		/* External IRQ Destination 2 */
 	u8	res52[12];
 	u32	eivpr3;		/* External IRQ Vector/Priority 3 */
 	u8	res53[12];
 	u32	eidr3;		/* External IRQ Destination 3 */
 	u8	res54[12];
 	u32	eivpr4;		/* External IRQ Vector/Priority 4 */
 	u8	res55[12];
 	u32	eidr4;		/* External IRQ Destination 4 */
 	u8	res56[12];
 	u32	eivpr5;		/* External IRQ Vector/Priority 5 */
 	u8	res57[12];
 	u32	eidr5;		/* External IRQ Destination 5 */
 	u8	res58[12];
 	u32	eivpr6;		/* External IRQ Vector/Priority 6 */
 	u8	res59[12];
 	u32	eidr6;		/* External IRQ Destination 6 */
 	u8	res60[12];
 	u32	eivpr7;		/* External IRQ Vector/Priority 7 */
 	u8	res61[12];
 	u32	eidr7;		/* External IRQ Destination 7 */
 	u8	res62[12];
 	u32	eivpr8;		/* External IRQ Vector/Priority 8 */
 	u8	res63[12];
 	u32	eidr8;		/* External IRQ Destination 8 */
 	u8	res64[12];
 	u32	eivpr9;		/* External IRQ Vector/Priority 9 */
 	u8	res65[12];
 	u32	eidr9;		/* External IRQ Destination 9 */
 	u8	res66[12];
 	u32	eivpr10;	/* External IRQ Vector/Priority 10 */
 	u8	res67[12];
 	u32	eidr10;		/* External IRQ Destination 10 */
 	u8	res68[12];
 	u32	eivpr11;	/* External IRQ Vector/Priority 11 */
 	u8	res69[12];
 	u32	eidr11;		/* External IRQ Destination 11 */
 	u8	res70[140];
 	u32	iivpr0;		/* Internal IRQ Vector/Priority 0 */
 	u8	res71[12];
 	u32	iidr0;		/* Internal IRQ Destination 0 */
 	u8	res72[12];
 	u32	iivpr1;		/* Internal IRQ Vector/Priority 1 */
 	u8	res73[12];
 	u32	iidr1;		/* Internal IRQ Destination 1 */
 	u8	res74[12];
 	u32	iivpr2;		/* Internal IRQ Vector/Priority 2 */
 	u8	res75[12];
 	u32	iidr2;		/* Internal IRQ Destination 2 */
 	u8	res76[12];
 	u32	iivpr3;		/* Internal IRQ Vector/Priority 3 */
 	u8	res77[12];
 	u32	iidr3;		/* Internal IRQ Destination 3 */
 	u8	res78[12];
 	u32	iivpr4;		/* Internal IRQ Vector/Priority 4 */
 	u8	res79[12];
 	u32	iidr4;		/* Internal IRQ Destination 4 */
 	u8	res80[12];
 	u32	iivpr5;		/* Internal IRQ Vector/Priority 5 */
 	u8	res81[12];
 	u32	iidr5;		/* Internal IRQ Destination 5 */
 	u8	res82[12];
 	u32	iivpr6;		/* Internal IRQ Vector/Priority 6 */
 	u8	res83[12];
 	u32	iidr6;		/* Internal IRQ Destination 6 */
 	u8	res84[12];
 	u32	iivpr7;		/* Internal IRQ Vector/Priority 7 */
 	u8	res85[12];
 	u32	iidr7;		/* Internal IRQ Destination 7 */
 	u8	res86[12];
 	u32	iivpr8;		/* Internal IRQ Vector/Priority 8 */
 	u8	res87[12];
 	u32	iidr8;		/* Internal IRQ Destination 8 */
 	u8	res88[12];
 	u32	iivpr9;		/* Internal IRQ Vector/Priority 9 */
 	u8	res89[12];
 	u32	iidr9;		/* Internal IRQ Destination 9 */
 	u8	res90[12];
 	u32	iivpr10;	/* Internal IRQ Vector/Priority 10 */
 	u8	res91[12];
 	u32	iidr10;		/* Internal IRQ Destination 10 */
 	u8	res92[12];
 	u32	iivpr11;	/* Internal IRQ Vector/Priority 11 */
 	u8	res93[12];
 	u32	iidr11;		/* Internal IRQ Destination 11 */
 	u8	res94[12];
 	u32	iivpr12;	/* Internal IRQ Vector/Priority 12 */
 	u8	res95[12];
 	u32	iidr12;		/* Internal IRQ Destination 12 */
 	u8	res96[12];
 	u32	iivpr13;	/* Internal IRQ Vector/Priority 13 */
 	u8	res97[12];
 	u32	iidr13;		/* Internal IRQ Destination 13 */
 	u8	res98[12];
 	u32	iivpr14;	/* Internal IRQ Vector/Priority 14 */
 	u8	res99[12];
 	u32	iidr14;		/* Internal IRQ Destination 14 */
 	u8	res100[12];
 	u32	iivpr15;	/* Internal IRQ Vector/Priority 15 */
 	u8	res101[12];
 	u32	iidr15;		/* Internal IRQ Destination 15 */
 	u8	res102[12];
 	u32	iivpr16;	/* Internal IRQ Vector/Priority 16 */
 	u8	res103[12];
 	u32	iidr16;		/* Internal IRQ Destination 16 */
 	u8	res104[12];
 	u32	iivpr17;	/* Internal IRQ Vector/Priority 17 */
 	u8	res105[12];
 	u32	iidr17;		/* Internal IRQ Destination 17 */
 	u8	res106[12];
 	u32	iivpr18;	/* Internal IRQ Vector/Priority 18 */
 	u8	res107[12];
 	u32	iidr18;		/* Internal IRQ Destination 18 */
 	u8	res108[12];
 	u32	iivpr19;	/* Internal IRQ Vector/Priority 19 */
 	u8	res109[12];
 	u32	iidr19;		/* Internal IRQ Destination 19 */
 	u8	res110[12];
 	u32	iivpr20;	/* Internal IRQ Vector/Priority 20 */
 	u8	res111[12];
 	u32	iidr20;		/* Internal IRQ Destination 20 */
 	u8	res112[12];
 	u32	iivpr21;	/* Internal IRQ Vector/Priority 21 */
 	u8	res113[12];
 	u32	iidr21;		/* Internal IRQ Destination 21 */
 	u8	res114[12];
 	u32	iivpr22;	/* Internal IRQ Vector/Priority 22 */
 	u8	res115[12];
 	u32	iidr22;		/* Internal IRQ Destination 22 */
 	u8	res116[12];
 	u32	iivpr23;	/* Internal IRQ Vector/Priority 23 */
 	u8	res117[12];
 	u32	iidr23;		/* Internal IRQ Destination 23 */
 	u8	res118[12];
 	u32	iivpr24;	/* Internal IRQ Vector/Priority 24 */
 	u8	res119[12];
 	u32	iidr24;		/* Internal IRQ Destination 24 */
 	u8	res120[12];
 	u32	iivpr25;	/* Internal IRQ Vector/Priority 25 */
 	u8	res121[12];
 	u32	iidr25;		/* Internal IRQ Destination 25 */
 	u8	res122[12];
 	u32	iivpr26;	/* Internal IRQ Vector/Priority 26 */
 	u8	res123[12];
 	u32	iidr26;		/* Internal IRQ Destination 26 */
 	u8	res124[12];
 	u32	iivpr27;	/* Internal IRQ Vector/Priority 27 */
 	u8	res125[12];
 	u32	iidr27;		/* Internal IRQ Destination 27 */
 	u8	res126[12];
 	u32	iivpr28;	/* Internal IRQ Vector/Priority 28 */
 	u8	res127[12];
 	u32	iidr28;		/* Internal IRQ Destination 28 */
 	u8	res128[12];
 	u32	iivpr29;	/* Internal IRQ Vector/Priority 29 */
 	u8	res129[12];
 	u32	iidr29;		/* Internal IRQ Destination 29 */
 	u8	res130[12];
 	u32	iivpr30;	/* Internal IRQ Vector/Priority 30 */
 	u8	res131[12];
 	u32	iidr30;		/* Internal IRQ Destination 30 */
 	u8	res132[12];
 	u32	iivpr31;	/* Internal IRQ Vector/Priority 31 */
 	u8	res133[12];
 	u32	iidr31;		/* Internal IRQ Destination 31 */
 	u8	res134[4108];
 	u32	mivpr0;		/* Messaging IRQ Vector/Priority 0 */
 	u8	res135[12];
 	u32	midr0;		/* Messaging IRQ Destination 0 */
 	u8	res136[12];
 	u32	mivpr1;		/* Messaging IRQ Vector/Priority 1 */
 	u8	res137[12];
 	u32	midr1;		/* Messaging IRQ Destination 1 */
 	u8	res138[12];
 	u32	mivpr2;		/* Messaging IRQ Vector/Priority 2 */
 	u8	res139[12];
 	u32	midr2;		/* Messaging IRQ Destination 2 */
 	u8	res140[12];
 	u32	mivpr3;		/* Messaging IRQ Vector/Priority 3 */
 	u8	res141[12];
 	u32	midr3;		/* Messaging IRQ Destination 3 */
 	u8	res142[59852];
 	u32	ipi0dr0;	/* Processor 0 Interprocessor IRQ Dispatch 0 */
 	u8	res143[12];
 	u32	ipi0dr1;	/* Processor 0 Interprocessor IRQ Dispatch 1 */
 	u8	res144[12];
 	u32	ipi0dr2;	/* Processor 0 Interprocessor IRQ Dispatch 2 */
 	u8	res145[12];
 	u32	ipi0dr3;	/* Processor 0 Interprocessor IRQ Dispatch 3 */
 	u8	res146[12];
 	u32	ctpr0;		/* Current Task Priority for Processor 0 */
 	u8	res147[12];
 	u32	whoami0;	/* Who Am I for Processor 0 */
 	u8	res148[12];
 	u32	iack0;		/* IRQ Acknowledge for Processor 0 */
 	u8	res149[12];
 	u32	eoi0;		/* End Of IRQ for Processor 0 */
 	u8	res150[130892];
 } ccsr_pic_t;
 /* CPM Block */
 #ifndef CONFIG_CPM2
 typedef struct ccsr_cpm {
 	u8 res[262144];
 } ccsr_cpm_t;
 #else
 /*
  * DPARM
  * General SIU
  */
 typedef struct ccsr_cpm_siu {
 	u8	res1[80];
 	u32	smaer;
 	u32	smser;
 	u32	smevr;
 	u8	res2[4];
 	u32	lmaer;
 	u32	lmser;
 	u32	lmevr;
 	u8	res3[2964];
 } ccsr_cpm_siu_t;
 /* IRQ Controller */
 typedef struct ccsr_cpm_intctl {
 	u16	sicr;
 	u8	res1[2];
 	u32	sivec;
 	u32	sipnrh;
 	u32	sipnrl;
 	u32	siprr;
 	u32	scprrh;
 	u32	scprrl;
 	u32	simrh;
 	u32	simrl;
 	u32	siexr;
 	u8	res2[88];
 	u32	sccr;
 	u8	res3[124];
 } ccsr_cpm_intctl_t;
 /* input/output port */
 typedef struct ccsr_cpm_iop {
 	u32	pdira;
 	u32	ppara;
 	u32	psora;
 	u32	podra;
 	u32	pdata;
 	u8	res1[12];
 	u32	pdirb;
 	u32	pparb;
 	u32	psorb;
 	u32	podrb;
 	u32	pdatb;
 	u8	res2[12];
 	u32	pdirc;
 	u32	pparc;
 	u32	psorc;
 	u32	podrc;
 	u32	pdatc;
 	u8	res3[12];
 	u32	pdird;
 	u32	ppard;
 	u32	psord;
 	u32	podrd;
 	u32	pdatd;
 	u8	res4[12];
 } ccsr_cpm_iop_t;
 /* CPM timers */
 typedef struct ccsr_cpm_timer {
 	u8	tgcr1;
 	u8	res1[3];
 	u8	tgcr2;
 	u8	res2[11];
 	u16	tmr1;
 	u16	tmr2;
 	u16	trr1;
 	u16	trr2;
 	u16	tcr1;
 	u16	tcr2;
 	u16	tcn1;
 	u16	tcn2;
 	u16	tmr3;
 	u16	tmr4;
 	u16	trr3;
 	u16	trr4;
 	u16	tcr3;
 	u16	tcr4;
 	u16	tcn3;
 	u16	tcn4;
 	u16	ter1;
 	u16	ter2;
 	u16	ter3;
 	u16	ter4;
 	u8	res3[608];
 } ccsr_cpm_timer_t;
 /* SDMA */
 typedef struct ccsr_cpm_sdma {
 	u8	sdsr;
 	u8	res1[3];
 	u8	sdmr;
 	u8	res2[739];
 } ccsr_cpm_sdma_t;
 /* FCC1 */
 typedef struct ccsr_cpm_fcc1 {
 	u32	gfmr;
 	u32	fpsmr;
 	u16	ftodr;
 	u8	res1[2];
 	u16	fdsr;
 	u8	res2[2];
 	u16	fcce;
 	u8	res3[2];
 	u16	fccm;
 	u8	res4[2];
 	u8	fccs;
 	u8	res5[3];
 	u8	ftirr_phy[4];
 } ccsr_cpm_fcc1_t;
 /* FCC2 */
 typedef struct ccsr_cpm_fcc2 {
 	u32	gfmr;
 	u32	fpsmr;
 	u16	ftodr;
 	u8	res1[2];
 	u16	fdsr;
 	u8	res2[2];
 	u16	fcce;
 	u8	res3[2];
 	u16	fccm;
 	u8	res4[2];
 	u8	fccs;
 	u8	res5[3];
 	u8	ftirr_phy[4];
 } ccsr_cpm_fcc2_t;
 /* FCC3 */
 typedef struct ccsr_cpm_fcc3 {
 	u32	gfmr;
 	u32	fpsmr;
 	u16	ftodr;
 	u8	res1[2];
 	u16	fdsr;
 	u8	res2[2];
 	u16	fcce;
 	u8	res3[2];
 	u16	fccm;
 	u8	res4[2];
 	u8	fccs;
 	u8	res5[3];
 	u8	res[36];
 } ccsr_cpm_fcc3_t;
 /* FCC1 extended */
 typedef struct ccsr_cpm_fcc1_ext {
 	u32	firper;
 	u32	firer;
 	u32	firsr_h;
 	u32	firsr_l;
 	u8	gfemr;
 	u8	res[15];
 } ccsr_cpm_fcc1_ext_t;
 /* FCC2 extended */
 typedef struct ccsr_cpm_fcc2_ext {
 	u32	firper;
 	u32	firer;
 	u32	firsr_h;
 	u32	firsr_l;
 	u8	gfemr;
 	u8	res[31];
 } ccsr_cpm_fcc2_ext_t;
 /* FCC3 extended */
 typedef struct ccsr_cpm_fcc3_ext {
 	u8	gfemr;
 	u8	res[47];
 } ccsr_cpm_fcc3_ext_t;
 /* TC layers */
 typedef struct ccsr_cpm_tmp1 {
 	u8	res[496];
 } ccsr_cpm_tmp1_t;
 /* BRGs:5,6,7,8 */
 typedef struct ccsr_cpm_brg2 {
 	u32	brgc5;
 	u32	brgc6;
 	u32	brgc7;
 	u32	brgc8;
 	u8	res[608];
 } ccsr_cpm_brg2_t;
 /* I2C */
 typedef struct ccsr_cpm_i2c {
 	u8	i2mod;
 	u8	res1[3];
 	u8	i2add;
 	u8	res2[3];
 	u8	i2brg;
 	u8	res3[3];
 	u8	i2com;
 	u8	res4[3];
 	u8	i2cer;
 	u8	res5[3];
 	u8	i2cmr;
 	u8	res6[331];
 } ccsr_cpm_i2c_t;
 /* CPM core */
 typedef struct ccsr_cpm_cp {
 	u32	cpcr;
 	u32	rccr;
 	u8	res1[14];
 	u16	rter;
 	u8	res2[2];
 	u16	rtmr;
 	u16	rtscr;
 	u8	res3[2];
 	u32	rtsr;
 	u8	res4[12];
 } ccsr_cpm_cp_t;
 /* BRGs:1,2,3,4 */
 typedef struct ccsr_cpm_brg1 {
 	u32	brgc1;
 	u32	brgc2;
 	u32	brgc3;
 	u32	brgc4;
 } ccsr_cpm_brg1_t;
 /* SCC1-SCC4 */
 typedef struct ccsr_cpm_scc {
 	u32	gsmrl;
 	u32	gsmrh;
 	u16	psmr;
 	u8	res1[2];
 	u16	todr;
 	u16	dsr;
 	u16	scce;
 	u8	res2[2];
 	u16	sccm;
 	u8	res3;
 	u8	sccs;
 	u8	res4[8];
 } ccsr_cpm_scc_t;
 typedef struct ccsr_cpm_tmp2 {
 	u8	res[32];
 } ccsr_cpm_tmp2_t;
 /* SPI */
 typedef struct ccsr_cpm_spi {
 	u16	spmode;
 	u8	res1[4];
 	u8	spie;
 	u8	res2[3];
 	u8	spim;
 	u8	res3[2];
 	u8	spcom;
 	u8	res4[82];
 } ccsr_cpm_spi_t;
 /* CPM MUX */
 typedef struct ccsr_cpm_mux {
 	u8	cmxsi1cr;
 	u8	res1;
 	u8	cmxsi2cr;
 	u8	res2;
 	u32	cmxfcr;
 	u32	cmxscr;
 	u8	res3[2];
 	u16	cmxuar;
 	u8	res4[16];
 } ccsr_cpm_mux_t;
 /* SI,MCC,etc */
 typedef struct ccsr_cpm_tmp3 {
 	u8 res[58592];
 } ccsr_cpm_tmp3_t;
 typedef struct ccsr_cpm_iram {
 	u32	iram[8192];
 	u8	res[98304];
 } ccsr_cpm_iram_t;
 typedef struct ccsr_cpm {
 	/* Some references are into the unique & known dpram spaces,
 	 * others are from the generic base.
 	 */
 #define im_dprambase		im_dpram1
 	u8			im_dpram1[16*1024];
 	u8			res1[16*1024];
 	u8			im_dpram2[16*1024];
 	u8			res2[16*1024];
 	ccsr_cpm_siu_t		im_cpm_siu; /* SIU Configuration */
 	ccsr_cpm_intctl_t	im_cpm_intctl; /* IRQ Controller */
 	ccsr_cpm_iop_t		im_cpm_iop; /* IO Port control/status */
 	ccsr_cpm_timer_t	im_cpm_timer; /* CPM timers */
 	ccsr_cpm_sdma_t		im_cpm_sdma; /* SDMA control/status */
 	ccsr_cpm_fcc1_t		im_cpm_fcc1;
 	ccsr_cpm_fcc2_t		im_cpm_fcc2;
 	ccsr_cpm_fcc3_t		im_cpm_fcc3;
 	ccsr_cpm_fcc1_ext_t	im_cpm_fcc1_ext;
 	ccsr_cpm_fcc2_ext_t	im_cpm_fcc2_ext;
 	ccsr_cpm_fcc3_ext_t	im_cpm_fcc3_ext;
 	ccsr_cpm_tmp1_t		im_cpm_tmp1;
 	ccsr_cpm_brg2_t		im_cpm_brg2;
 	ccsr_cpm_i2c_t		im_cpm_i2c;
 	ccsr_cpm_cp_t		im_cpm_cp;
 	ccsr_cpm_brg1_t		im_cpm_brg1;
 	ccsr_cpm_scc_t		im_cpm_scc[4];
 	ccsr_cpm_tmp2_t		im_cpm_tmp2;
 	ccsr_cpm_spi_t		im_cpm_spi;
 	ccsr_cpm_mux_t		im_cpm_mux;
 	ccsr_cpm_tmp3_t		im_cpm_tmp3;
 	ccsr_cpm_iram_t		im_cpm_iram;
 } ccsr_cpm_t;
 #endif
 #ifdef CONFIG_SYS_SRIO
 /* Architectural regsiters */
 struct rio_arch {
 	u32	didcar;	/* Device Identity CAR */
 	u32	dicar;	/* Device Information CAR */
 	u32	aidcar;	/* Assembly Identity CAR */
 	u32	aicar;	/* Assembly Information CAR */
 	u32	pefcar;	/* Processing Element Features CAR */
 	u8	res0[4];
 	u32	socar;	/* Source Operations CAR */
 	u32	docar;	/* Destination Operations CAR */
 	u8	res1[32];
 	u32	mcsr;	/* Mailbox CSR */
 	u32	pwdcsr;	/* Port-Write and Doorbell CSR */
 	u8	res2[4];
 	u32	pellccsr;	/* Processing Element Logic Layer CCSR */
 	u8	res3[12];
 	u32	lcsbacsr;	/* Local Configuration Space BACSR */
 	u32	bdidcsr;	/* Base Device ID CSR */
 	u8	res4[4];
 	u32	hbdidlcsr;	/* Host Base Device ID Lock CSR */
 	u32	ctcsr;	/* Component Tag CSR */
 };
 /* Extended Features Space: 1x/4x LP-Serial Port registers */
 struct rio_lp_serial_port {
 	u32	plmreqcsr;	/* Port Link Maintenance Request CSR */
 	u32	plmrespcsr;	/* Port Link Maintenance Response CS */
 	u32	plascsr;	/* Port Local Ackid Status CSR */
 	u8	res0[12];
 	u32	pescsr;	/* Port Error and Status CSR */
 	u32	pccsr;	/* Port Control CSR */
 };
 /* Extended Features Space: 1x/4x LP-Serial registers */
 struct rio_lp_serial {
 	u32	pmbh0csr;	/* Port Maintenance Block Header 0 CSR */
 	u8	res0[28];
 	u32	pltoccsr;	/* Port Link Time-out CCSR */
 	u32	prtoccsr;	/* Port Response Time-out CCSR */
 	u8	res1[20];
 	u32	pgccsr;	/* Port General CSR */
 	struct rio_lp_serial_port	port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
 };
 /* Logical error reporting registers */
 struct rio_logical_err {
 	u32	erbh;	/* Error Reporting Block Header Register */
 	u8	res0[4];
 	u32	ltledcsr;	/* Logical/Transport layer error DCSR */
 	u32	ltleecsr;	/* Logical/Transport layer error ECSR */
 	u8	res1[4];
 	u32	ltlaccsr;	/* Logical/Transport layer ACCSR */
 	u32	ltldidccsr;	/* Logical/Transport layer DID CCSR */
 	u32	ltlcccsr;	/* Logical/Transport layer control CCSR */
 };
 /* Physical error reporting port registers */
 struct rio_phys_err_port {
 	u32	edcsr;	/* Port error detect CSR */
 	u32	erecsr;	/* Port error rate enable CSR */
 	u32	ecacsr;	/* Port error capture attributes CSR */
 	u32	pcseccsr0;	/* Port packet/control symbol ECCSR 0 */
 	u32	peccsr[3];	/* Port error capture CSR */
 	u8	res0[12];
 	u32	ercsr;	/* Port error rate CSR */
 	u32	ertcsr;	/* Port error rate threshold CSR */
 	u8	res1[16];
 };
 /* Physical error reporting registers */
 struct rio_phys_err {
 	struct rio_phys_err_port	port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
 };
 /* Implementation Space: General Port-Common */
 struct rio_impl_common {
 	u8	res0[4];
 	u32	llcr;	/* Logical Layer Configuration Register */
 	u8	res1[8];
 	u32	epwisr;	/* Error / Port-Write Interrupt SR */
 	u8	res2[12];
 	u32	lretcr;	/* Logical Retry Error Threshold CR */
 	u8	res3[92];
 	u32	pretcr;	/* Physical Retry Erorr Threshold CR */
 	u8	res4[124];
 };
 /* Implementation Space: Port Specific */
 struct rio_impl_port_spec {
 	u32	adidcsr;	/* Port Alt. Device ID CSR */
 	u8	res0[28];
 	u32	ptaacr;	/* Port Pass-Through/Accept-All CR */
 	u32	lopttlcr;
 	u8	res1[8];
 	u32	iecsr;	/* Port Implementation Error CSR */
 	u8	res2[12];
 	u32	pcr;		/* Port Phsyical Configuration Register */
 	u8	res3[20];
 	u32	slcsr;	/* Port Serial Link CSR */
 	u8	res4[4];
 	u32	sleicr;	/* Port Serial Link Error Injection */
 	u32	a0txcr;	/* Port Arbitration 0 Tx CR */
 	u32	a1txcr;	/* Port Arbitration 1 Tx CR */
 	u32	a2txcr;	/* Port Arbitration 2 Tx CR */
 	u32	mreqtxbacr[3];	/* Port Request Tx Buffer ACR */
 	u32	mrspfctxbacr;	/* Port Response/Flow Control Tx Buffer ACR */
 };
 /* Implementation Space: register */
 struct rio_implement {
 	struct rio_impl_common	com;
 	struct rio_impl_port_spec	port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
 };
 /* Revision Control Register */
 struct rio_rev_ctrl {
 	u32	ipbrr[2];	/* IP Block Revision Register */
 };
 struct rio_atmu_row {
 	u32	rowtar; /* RapidIO Outbound Window TAR */
 	u32	rowtear; /* RapidIO Outbound Window TEAR */
 	u32	rowbar;
 	u8	res0[4];
 	u32	rowar; /* RapidIO Outbound Attributes Register */
 	u32	rowsr[3]; /* Port RapidIO outbound window segment register */
 };
 struct rio_atmu_riw {
 	u32	riwtar; /* RapidIO Inbound Window Translation AR */
 	u8	res0[4];
 	u32	riwbar; /* RapidIO Inbound Window Base AR */
 	u8	res1[4];
 	u32	riwar; /* RapidIO Inbound Attributes Register */
 	u8	res2[12];
 };
 /* ATMU window registers */
 struct rio_atmu_win {
 	struct rio_atmu_row	outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
 	u8	res0[64];
 	struct rio_atmu_riw	inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
 };
 struct rio_atmu {
 	struct rio_atmu_win	port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
 };
 #ifdef CONFIG_SYS_FSL_RMU
 struct rio_msg {
 	u32	omr; /* Outbound Mode Register */
 	u32	osr; /* Outbound Status Register */
 	u32	eodqdpar; /* Extended Outbound DQ DPAR */
 	u32	odqdpar; /* Outbound Descriptor Queue DPAR */
 	u32	eosar; /* Extended Outbound Unit Source AR */
 	u32	osar; /* Outbound Unit Source AR */
 	u32	odpr; /* Outbound Destination Port Register */
 	u32	odatr; /* Outbound Destination Attributes Register */
 	u32	odcr; /* Outbound Doubleword Count Register */
 	u32	eodqepar; /* Extended Outbound DQ EPAR */
 	u32	odqepar; /* Outbound Descriptor Queue EPAR */
 	u32	oretr; /* Outbound Retry Error Threshold Register */
 	u32	omgr; /* Outbound Multicast Group Register */
 	u32	omlr; /* Outbound Multicast List Register */
 	u8	res0[40];
 	u32	imr;	 /* Outbound Mode Register */
 	u32	isr; /* Inbound Status Register */
 	u32	eidqdpar; /* Extended Inbound Descriptor Queue DPAR */
 	u32	idqdpar; /* Inbound Descriptor Queue DPAR */
 	u32	eifqepar; /* Extended Inbound Frame Queue EPAR */
 	u32	ifqepar; /* Inbound Frame Queue EPAR */
 	u32	imirir; /* Inbound Maximum Interrutp RIR */
 	u8	res1[4];
 	u32 eihqepar; /* Extended inbound message header queue EPAR */
 	u32 ihqepar; /* Inbound message header queue EPAR */
 	u8	res2[120];
 };
 struct rio_dbell {
 	u32	odmr; /* Outbound Doorbell Mode Register */
 	u32	odsr; /* Outbound Doorbell Status Register */
 	u8	res0[16];
 	u32	oddpr; /* Outbound Doorbell Destination Port */
 	u32	oddatr; /* Outbound Doorbell Destination AR */
 	u8	res1[12];
 	u32	oddretr; /* Outbound Doorbell Retry Threshold CR */
 	u8	res2[48];
 	u32	idmr; /* Inbound Doorbell Mode Register */
 	u32	idsr;	 /* Inbound Doorbell Status Register */
 	u32	iedqdpar; /* Extended Inbound Doorbell Queue DPAR */
 	u32	iqdpar; /* Inbound Doorbell Queue DPAR */
 	u32	iedqepar; /* Extended Inbound Doorbell Queue EPAR */
 	u32	idqepar; /* Inbound Doorbell Queue EPAR */
 	u32	idmirir; /* Inbound Doorbell Max Interrupt RIR */
 };
 struct rio_pw {
 	u32	pwmr; /* Port-Write Mode Register */
 	u32	pwsr; /* Port-Write Status Register */
 	u32	epwqbar; /* Extended Port-Write Queue BAR */
 	u32	pwqbar; /* Port-Write Queue Base Address Register */
 };
 #endif
 #ifdef CONFIG_SYS_FSL_SRIO_LIODN
 struct rio_liodn {
 	u32	plbr;
 	u8	res0[28];
 	u32	plaor;
 	u8	res1[12];
 	u32	pludr;
 	u32	plldr;
 	u8	res2[456];
 };
 #endif
 /* RapidIO Registers */
 struct ccsr_rio {
 	struct rio_arch	arch;
 	u8	res0[144];
 	struct rio_lp_serial	lp_serial;
 	u8	res1[1152];
 	struct rio_logical_err	logical_err;
 	u8	res2[32];
 	struct rio_phys_err	phys_err;
 	u8	res3[63808];
 	struct rio_implement	impl;
 	u8	res4[2552];
 	struct rio_rev_ctrl	rev;
 	struct rio_atmu	atmu;
 #ifdef CONFIG_SYS_FSL_RMU
 	u8	res5[8192];
 	struct rio_msg	msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
 	u8	res6[512];
 	struct rio_dbell	dbell;
 	u8	res7[100];
 	struct rio_pw	pw;
 #endif
 #ifdef CONFIG_SYS_FSL_SRIO_LIODN
 	u8	res5[8192];
 	struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
 #endif
 };
 #endif
 /* Quick Engine Block Pin Muxing Registers */
 typedef struct par_io {
 	u32	cpodr;
 	u32	cpdat;
 	u32	cpdir1;
 	u32	cpdir2;
 	u32	cppar1;
 	u32	cppar2;
 	u8	res[8];
 } par_io_t;
 #ifdef CONFIG_SYS_FSL_CPC
 /*
  * Define a single offset that is the start of all the CPC register
  * blocks - if there is more than one CPC, we expect these to be
  * contiguous 4k regions
  */
 typedef struct cpc_corenet {
 	u32 	cpccsr0;	/* Config/status reg */
 	u32	res1;
 	u32	cpccfg0;	/* Configuration register */
 	u32	res2;
 	u32	cpcewcr0;	/* External Write reg 0 */
 	u32	cpcewabr0;	/* External write base reg 0 */
 	u32	res3[2];
 	u32	cpcewcr1;	/* External Write reg 1 */
 	u32	cpcewabr1;	/* External write base reg 1 */
 	u32	res4[54];
 	u32	cpcsrcr1;	/* SRAM control reg 1 */
 	u32	cpcsrcr0;	/* SRAM control reg 0 */
 	u32	res5[62];
 	struct {
 		u32	id;	/* partition ID */
 		u32	res;
 		u32	alloc;	/* partition allocation */
 		u32	way;	/* partition way */
 	} partition_regs[16];
 	u32	res6[704];
 	u32	cpcerrinjhi;	/* Error injection high */
 	u32	cpcerrinjlo;	/* Error injection lo */
 	u32	cpcerrinjctl;	/* Error injection control */
 	u32	res7[5];
 	u32	cpccaptdatahi;	/* capture data high */
 	u32	cpccaptdatalo;	/* capture data low */
 	u32	cpcaptecc;	/* capture ECC */
 	u32	res8[5];
 	u32	cpcerrdet;	/* error detect */
 	u32	cpcerrdis;	/* error disable */
 	u32	cpcerrinten;	/* errir interrupt enable */
 	u32	cpcerrattr;	/* error attribute */
 	u32	cpcerreaddr;	/* error extended address */
 	u32	cpcerraddr;	/* error address */
 	u32	cpcerrctl;	/* error control */
 	u32	res9[41];	/* pad out to 4k */
 	u32	cpchdbcr0;	/* hardware debug control register 0 */
 	u32	res10[63];	/* pad out to 4k */
 } cpc_corenet_t;
 #define CPC_CSR0_CE	0x80000000	/* Cache Enable */
 #define CPC_CSR0_PE	0x40000000	/* Enable ECC */
 #define CPC_CSR0_FI	0x00200000	/* Cache Flash Invalidate */
 #define CPC_CSR0_WT	0x00080000	/* Write-through mode */
 #define CPC_CSR0_FL	0x00000800	/* Hardware cache flush */
 #define CPC_CSR0_LFC	0x00000400	/* Cache Lock Flash Clear */
 #define CPC_CFG0_SZ_MASK	0x00003fff
 #define CPC_CFG0_SZ_K(x)	((x & CPC_CFG0_SZ_MASK) << 6)
 #define CPC_CFG0_NUM_WAYS(x)	(((x >> 14) & 0x1f) + 1)
 #define CPC_CFG0_LINE_SZ(x)	((((x >> 23) & 0x3) + 1) * 32)
 #define CPC_SRCR1_SRBARU_MASK	0x0000ffff
 #define CPC_SRCR1_SRBARU(x)	(((unsigned long long)x >> 32) \
 				 & CPC_SRCR1_SRBARU_MASK)
 #define	CPC_SRCR0_SRBARL_MASK	0xffff8000
 #define CPC_SRCR0_SRBARL(x)	(x & CPC_SRCR0_SRBARL_MASK)
 #define CPC_SRCR0_INTLVEN	0x00000100
 #define CPC_SRCR0_SRAMSZ_1_WAY	0x00000000
 #define CPC_SRCR0_SRAMSZ_2_WAY	0x00000002
 #define CPC_SRCR0_SRAMSZ_4_WAY	0x00000004
 #define CPC_SRCR0_SRAMSZ_8_WAY	0x00000006
 #define CPC_SRCR0_SRAMSZ_16_WAY	0x00000008
 #define CPC_SRCR0_SRAMSZ_32_WAY	0x0000000a
 #define CPC_SRCR0_SRAMEN	0x00000001
 #define	CPC_ERRDIS_TMHITDIS  	0x00000080	/* multi-way hit disable */
 #define CPC_HDBCR0_CDQ_SPEC_DIS	0x08000000
 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS	0x01000000
 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS	0x00400000
 #define CPC_HDBCR0_SPLRU_LEVEL_EN	0x003c0000
 #endif /* CONFIG_SYS_FSL_CPC */
 /* Global Utilities Block */
 #ifdef CONFIG_FSL_CORENET
 typedef struct ccsr_gur {
 	u32	porsr1;		/* POR status 1 */
 	u32	porsr2;		/* POR status 2 */
 	u8	res_008[0x20-0x8];
 	u32	gpporcr1;	/* General-purpose POR configuration */
 	u32	gpporcr2;	/* General-purpose POR configuration 2 */
 	u32	dcfg_fusesr;	/* Fuse status register */
 #define FSL_CORENET_DCFG_FUSESR_VID_SHIFT	25
 #define FSL_CORENET_DCFG_FUSESR_VID_MASK	0x1F
 #define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT	20
 #define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK	0x1F
 	u8	res_02c[0x70-0x2c];
 	u32	devdisr;	/* Device disable control */
 	u32	devdisr2;	/* Device disable control 2 */
 	u32	devdisr3;	/* Device disable control 3 */
 	u32	devdisr4;	/* Device disable control 4 */
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 	u32	devdisr5;	/* Device disable control 5 */
 #define FSL_CORENET_DEVDISR_PBL	0x80000000
 #define FSL_CORENET_DEVDISR_PMAN	0x40000000
 #define FSL_CORENET_DEVDISR_ESDHC	0x20000000
 #define FSL_CORENET_DEVDISR_DMA1	0x00800000
 #define FSL_CORENET_DEVDISR_DMA2	0x00400000
 #define FSL_CORENET_DEVDISR_USB1	0x00080000
 #define FSL_CORENET_DEVDISR_USB2	0x00040000
 #define FSL_CORENET_DEVDISR_SATA1	0x00008000
 #define FSL_CORENET_DEVDISR_SATA2	0x00004000
 #define FSL_CORENET_DEVDISR_PME	0x00000800
 #define FSL_CORENET_DEVDISR_SEC	0x00000200
 #define FSL_CORENET_DEVDISR_RMU	0x00000080
 #define FSL_CORENET_DEVDISR_DCE	0x00000040
 #define FSL_CORENET_DEVDISR2_DTSEC1_1	0x80000000
 #define FSL_CORENET_DEVDISR2_DTSEC1_2	0x40000000
 #define FSL_CORENET_DEVDISR2_DTSEC1_3	0x20000000
 #define FSL_CORENET_DEVDISR2_DTSEC1_4	0x10000000
 #define FSL_CORENET_DEVDISR2_DTSEC1_5	0x08000000
 #define FSL_CORENET_DEVDISR2_DTSEC1_6	0x04000000
 #define FSL_CORENET_DEVDISR2_DTSEC1_9	0x00800000
 #define FSL_CORENET_DEVDISR2_DTSEC1_10	0x00400000
 #define FSL_CORENET_DEVDISR2_10GEC1_1	0x00800000
 #define FSL_CORENET_DEVDISR2_10GEC1_2	0x00400000
 #define FSL_CORENET_DEVDISR2_10GEC1_3	0x80000000
 #define FSL_CORENET_DEVDISR2_10GEC1_4	0x40000000
 #define FSL_CORENET_DEVDISR2_DTSEC2_1	0x00080000
 #define FSL_CORENET_DEVDISR2_DTSEC2_2	0x00040000
 #define FSL_CORENET_DEVDISR2_DTSEC2_3	0x00020000
 #define FSL_CORENET_DEVDISR2_DTSEC2_4	0x00010000
 #define FSL_CORENET_DEVDISR2_DTSEC2_5	0x00008000
 #define FSL_CORENET_DEVDISR2_DTSEC2_6	0x00004000
 #define FSL_CORENET_DEVDISR2_DTSEC2_9	0x00000800
 #define FSL_CORENET_DEVDISR2_DTSEC2_10	0x00000400
 #define FSL_CORENET_DEVDISR2_10GEC2_1	0x00000800
 #define FSL_CORENET_DEVDISR2_10GEC2_2	0x00000400
 #define FSL_CORENET_DEVDISR2_FM1	0x00000080
 #define FSL_CORENET_DEVDISR2_FM2	0x00000040
 #define FSL_CORENET_DEVDISR2_CPRI	0x00000008
 #define FSL_CORENET_DEVDISR3_PCIE1	0x80000000
 #define FSL_CORENET_DEVDISR3_PCIE2	0x40000000
 #define FSL_CORENET_DEVDISR3_PCIE3	0x20000000
 #define FSL_CORENET_DEVDISR3_PCIE4	0x10000000
 #define FSL_CORENET_DEVDISR3_SRIO1	0x08000000
 #define FSL_CORENET_DEVDISR3_SRIO2	0x04000000
 #define FSL_CORENET_DEVDISR3_QMAN	0x00080000
 #define FSL_CORENET_DEVDISR3_BMAN	0x00040000
 #define FSL_CORENET_DEVDISR3_LA1	0x00008000
 #define FSL_CORENET_DEVDISR3_MAPLE1	0x00000800
 #define FSL_CORENET_DEVDISR3_MAPLE2	0x00000400
 #define FSL_CORENET_DEVDISR3_MAPLE3	0x00000200
 #define FSL_CORENET_DEVDISR4_I2C1	0x80000000
 #define FSL_CORENET_DEVDISR4_I2C2	0x40000000
 #define FSL_CORENET_DEVDISR4_DUART1	0x20000000
 #define FSL_CORENET_DEVDISR4_DUART2	0x10000000
 #define FSL_CORENET_DEVDISR4_ESPI	0x08000000
 #define FSL_CORENET_DEVDISR5_DDR1	0x80000000
 #define FSL_CORENET_DEVDISR5_DDR2	0x40000000
 #define FSL_CORENET_DEVDISR5_DDR3	0x20000000
 #define FSL_CORENET_DEVDISR5_CPC1	0x08000000
 #define FSL_CORENET_DEVDISR5_CPC2	0x04000000
 #define FSL_CORENET_DEVDISR5_CPC3	0x02000000
 #define FSL_CORENET_DEVDISR5_IFC	0x00800000
 #define FSL_CORENET_DEVDISR5_GPIO	0x00400000
 #define FSL_CORENET_DEVDISR5_DBG	0x00200000
 #define FSL_CORENET_DEVDISR5_NAL	0x00100000
 #define FSL_CORENET_DEVDISR5_TIMERS	0x00020000
 #define FSL_CORENET_NUM_DEVDISR		5
 #else
 #define FSL_CORENET_DEVDISR_PCIE1	0x80000000
 #define FSL_CORENET_DEVDISR_PCIE2	0x40000000
 #define FSL_CORENET_DEVDISR_PCIE3	0x20000000
 #define FSL_CORENET_DEVDISR_PCIE4	0x10000000
 #define FSL_CORENET_DEVDISR_RMU		0x08000000
 #define FSL_CORENET_DEVDISR_SRIO1	0x04000000
 #define FSL_CORENET_DEVDISR_SRIO2	0x02000000
 #define FSL_CORENET_DEVDISR_DMA1	0x00400000
 #define FSL_CORENET_DEVDISR_DMA2	0x00200000
 #define FSL_CORENET_DEVDISR_DDR1	0x00100000
 #define FSL_CORENET_DEVDISR_DDR2	0x00080000
 #define FSL_CORENET_DEVDISR_DBG		0x00010000
 #define FSL_CORENET_DEVDISR_NAL		0x00008000
 #define FSL_CORENET_DEVDISR_SATA1	0x00004000
 #define FSL_CORENET_DEVDISR_SATA2	0x00002000
 #define FSL_CORENET_DEVDISR_ELBC	0x00001000
 #define FSL_CORENET_DEVDISR_USB1	0x00000800
 #define FSL_CORENET_DEVDISR_USB2	0x00000400
 #define FSL_CORENET_DEVDISR_ESDHC	0x00000100
 #define FSL_CORENET_DEVDISR_GPIO	0x00000080
 #define FSL_CORENET_DEVDISR_ESPI	0x00000040
 #define FSL_CORENET_DEVDISR_I2C1	0x00000020
 #define FSL_CORENET_DEVDISR_I2C2	0x00000010
 #define FSL_CORENET_DEVDISR_DUART1	0x00000002
 #define FSL_CORENET_DEVDISR_DUART2	0x00000001
 #define FSL_CORENET_DEVDISR2_PME	0x80000000
 #define FSL_CORENET_DEVDISR2_SEC	0x40000000
 #define FSL_CORENET_DEVDISR2_QMBM	0x08000000
 #define FSL_CORENET_DEVDISR2_FM1	0x02000000
 #define FSL_CORENET_DEVDISR2_10GEC1	0x01000000
 #define FSL_CORENET_DEVDISR2_DTSEC1_1	0x00800000
 #define FSL_CORENET_DEVDISR2_DTSEC1_2	0x00400000
 #define FSL_CORENET_DEVDISR2_DTSEC1_3	0x00200000
 #define FSL_CORENET_DEVDISR2_DTSEC1_4	0x00100000
 #define FSL_CORENET_DEVDISR2_DTSEC1_5	0x00080000
 #define FSL_CORENET_DEVDISR2_FM2	0x00020000
 #define FSL_CORENET_DEVDISR2_10GEC2	0x00010000
 #define FSL_CORENET_DEVDISR2_DTSEC2_1	0x00008000
 #define FSL_CORENET_DEVDISR2_DTSEC2_2	0x00004000
 #define FSL_CORENET_DEVDISR2_DTSEC2_3	0x00002000
 #define FSL_CORENET_DEVDISR2_DTSEC2_4	0x00001000
 #define FSL_CORENET_DEVDISR2_DTSEC2_5	0x00000800
 #define FSL_CORENET_NUM_DEVDISR		2
 	u32	powmgtcsr;	/* Power management status & control */
 #endif
 	u8	res8[12];
 	u32	coredisru;	/* uppper portion for support of 64 cores */
 	u32	coredisrl;	/* lower portion for support of 64 cores */
 	u8	res9[8];
 	u32	pvr;		/* Processor version */
 	u32	svr;		/* System version */
 	u8	res10[8];
 	u32	rstcr;		/* Reset control */
 	u32	rstrqpblsr;	/* Reset request preboot loader status */
 	u8	res11[8];
 	u32	rstrqmr1;	/* Reset request mask */
 	u8	res12[4];
 	u32	rstrqsr1;	/* Reset request status */
 	u8	res13[4];
 	u8	res14[4];
 	u32	rstrqwdtmrl;	/* Reset request WDT mask */
 	u8	res15[4];
 	u32	rstrqwdtsrl;	/* Reset request WDT status */
 	u8	res16[4];
 	u32	brrl;		/* Boot release */
 	u8	res17[24];
 	u32	rcwsr[16];	/* Reset control word status */
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	16
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK	0x3f
 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL		0xfc000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	26
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL		0x00fe0000
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	17
 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL		0x0000f800
 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT	11
 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL		0x000000f8
 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT	3
 #define FSL_CORENET_RCWSR6_BOOT_LOC	0x0f800000
 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL	0xfe000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	25
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL	0x00ff0000
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	16
 #define FSL_CORENET_RCWSR6_BOOT_LOC	0x0f800000
 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL	0xff000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	24
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL	0x00fe0000
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	17
 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL		0xff000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	24
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL		0x00ff0000
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	16
 #define FSL_CORENET_RCWSR6_BOOT_LOC		0x0f800000
 #endif
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1	0x00800000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2	0x00400000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1	0x00200000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2	0x00100000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1	0x00080000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2	0x00040000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1	0x00020000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2	0x00010000
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK	0x00000011
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK	1
 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	17
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK	0x1f
 #define FSL_CORENET_RCWSR4_SRDS_PRTCL		0xfc000000
 #define FSL_CORENET_RCWSR5_DDR_SYNC		0x00000080
 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT		 7
 #define FSL_CORENET_RCWSR5_SRDS_EN		0x00002000
 #define FSL_CORENET_RCWSR5_SRDS2_EN		0x00001000
 #define FSL_CORENET_RCWSR6_BOOT_LOC	0x0f800000
 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2		0x3c000000 /* bits 162..165 */
 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3		0x003c0000 /* bits 170..173 */
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT	0x00400000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B1		0x00e00000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B2		0x00100000
 #define FSL_CORENET_RCWSR11_EC1			0x00c00000 /* bits 360..361 */
 #ifdef CONFIG_PPC_P4080
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1		0x00000000
 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1		0x00800000
 #define FSL_CORENET_RCWSR11_EC2			0x001c0000 /* bits 363..365 */
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1		0x00000000
 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2		0x00080000
 #define FSL_CORENET_RCWSR11_EC2_USB2			0x00100000
 #endif
 #if defined(CONFIG_PPC_P2041) \
 	|| defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII	0x00000000
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII		0x00800000
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE		0x00c00000
 #define FSL_CORENET_RCWSR11_EC2			0x00180000 /* bits 363..364 */
 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII	0x00000000
 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII		0x00100000
 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE		0x00180000
 #endif
 #if defined(CONFIG_PPC_P5040)
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII        0x00000000
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII          0x00800000
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE         0x00c00000
 #define FSL_CORENET_RCWSR11_EC2                 0x00180000 /* bits 363..364 */
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII        0x00000000
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII          0x00100000
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE         0x00180000
 #endif
 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
 #define FSL_CORENET_RCWSR13_EC1			0x60000000 /* bits 417..418 */
 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII	0x00000000
 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO		0x40000000
 #define FSL_CORENET_RCWSR13_EC2			0x18000000 /* bits 419..420 */
 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII	0x00000000
 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII	0x08000000
 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO		0x10000000
 #endif
 #if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
 #define FSL_CORENET_RCWSR13_EC1			0x60000000 /* bits 417..418 */
 #define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII	0x00000000
 #define FSL_CORENET_RCWSR13_EC1_GPIO		0x40000000
 #define FSL_CORENET_RCWSR13_EC2			0x18000000 /* bits 419..420 */
 #define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII	0x00000000
 #define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII	0x08000000
 #define FSL_CORENET_RCWSR13_EC2_GPIO		0x10000000
 #endif
 	u8	res18[192];
 	u32	scratchrw[4];	/* Scratch Read/Write */
 	u8	res19[240];
 	u32	scratchw1r[4];	/* Scratch Read (Write once) */
 	u8	res20[240];
 	u32	scrtsr[8];	/* Core reset status */
 	u8	res21[224];
 	u32	pex1liodnr;	/* PCI Express 1 LIODN */
 	u32	pex2liodnr;	/* PCI Express 2 LIODN */
 	u32	pex3liodnr;	/* PCI Express 3 LIODN */
 	u32	pex4liodnr;	/* PCI Express 4 LIODN */
 	u32	rio1liodnr;	/* RIO 1 LIODN */
 	u32	rio2liodnr;	/* RIO 2 LIODN */
 	u32	rio3liodnr;	/* RIO 3 LIODN */
 	u32	rio4liodnr;	/* RIO 4 LIODN */
 	u32	usb1liodnr;	/* USB 1 LIODN */
 	u32	usb2liodnr;	/* USB 2 LIODN */
 	u32	usb3liodnr;	/* USB 3 LIODN */
 	u32	usb4liodnr;	/* USB 4 LIODN */
 	u32	sdmmc1liodnr;	/* SD/MMC 1 LIODN */
 	u32	sdmmc2liodnr;	/* SD/MMC 2 LIODN */
 	u32	sdmmc3liodnr;	/* SD/MMC 3 LIODN */
 	u32	sdmmc4liodnr;	/* SD/MMC 4 LIODN */
 	u32	rio1maintliodnr;/* RIO 1 Maintenance LIODN */
 	u32	rio2maintliodnr;/* RIO 2 Maintenance LIODN */
 	u32	rio3maintliodnr;/* RIO 3 Maintenance LIODN */
 	u32	rio4maintliodnr;/* RIO 4 Maintenance LIODN */
 	u32	sata1liodnr;	/* SATA 1 LIODN */
 	u32	sata2liodnr;	/* SATA 2 LIODN */
 	u32	sata3liodnr;	/* SATA 3 LIODN */
 	u32	sata4liodnr;	/* SATA 4 LIODN */
 	u8	res22[32];
 	u32	dma1liodnr;	/* DMA 1 LIODN */
 	u32	dma2liodnr;	/* DMA 2 LIODN */
 	u32	dma3liodnr;	/* DMA 3 LIODN */
 	u32	dma4liodnr;	/* DMA 4 LIODN */
 	u8	res23[48];
 	u8	res24[64];
 	u32	pblsr;		/* Preboot loader status */
 	u32	pamubypenr;	/* PAMU bypass enable */
 	u32	dmacr1;		/* DMA control */
 	u8	res25[4];
 	u32	gensr1;		/* General status */
 	u8	res26[12];
 	u32	gencr1;		/* General control */
 	u8	res27[12];
 	u8	res28[4];
 	u32	cgensrl;	/* Core general status */
 	u8	res29[8];
 	u8	res30[4];
 	u32	cgencrl;	/* Core general control */
 	u8	res31[184];
 	u32	sriopstecr;	/* SRIO prescaler timer enable control */
 	u32	dcsrcr;		/* DCSR Control register */
 	u8	res31a[56];
 	u32	tp_ityp[64];	/* Topology Initiator Type Register */
 	struct {
 		u32	upper;
 		u32	lower;
 	} tp_cluster[16];	/* Core Cluster n Topology Register */
 	u8	res32[1344];
 	u32	pmuxcr;		/* Pin multiplexing control */
 	u8	res33[60];
 	u32	iovselsr;	/* I/O voltage selection status */
 	u8	res34[28];
 	u32	ddrclkdr;	/* DDR clock disable */
 	u8	res35;
 	u32	elbcclkdr;	/* eLBC clock disable */
 	u8	res36[20];
 	u32	sdhcpcr;	/* eSDHC polarity configuration */
 	u8	res37[380];
 } ccsr_gur_t;
 #define TP_ITYP_AV	0x00000001		/* Initiator available */
 #define TP_ITYP_TYPE(x)	(((x) & 0x6) >> 1)	/* Initiator Type */
 #define TP_ITYP_TYPE_OTHER	0x0
 #define TP_ITYP_TYPE_PPC	0x1	/* PowerPC */
 #define TP_ITYP_TYPE_SC		0x2	/* StarCore DSP */
 #define TP_ITYP_TYPE_HA		0x3	/* HW Accelerator */
 #define TP_ITYP_THDS(x)	(((x) & 0x18) >> 3)	/* # threads */
 #define TP_ITYP_VER(x)	(((x) & 0xe0) >> 5)	/* Initiator Version */
 #define TP_CLUSTER_EOC		0x80000000	/* end of clusters */
 #define TP_CLUSTER_INIT_MASK	0x0000003f	/* initiator mask */
 #define TP_INIT_PER_CLUSTER	4
 #define FSL_CORENET_DCSR_SZ_MASK	0x00000003
 #define FSL_CORENET_DCSR_SZ_4M		0x0
 #define FSL_CORENET_DCSR_SZ_1G		0x3
 /*
  * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
  * everything after has RMan thus msg unit LIODN is used for maintenance
  */
 #define rmuliodnr rio1maintliodnr
 typedef struct ccsr_clk {
 	struct {
 		u32 clkcncsr;	/* core cluster n clock control status */
 		u8  res_004[0x0c];
 		u32 clkcgnhwacsr;/* clock generator n hardware accelerator */
 		u8  res_014[0x0c];
 	} clkcsr[12];
 	u8	res_100[0x680]; /* 0x100 */
 	struct {
 		u32 pllcngsr;
 		u8 res10[0x1c];
 	} pllcgsr[12];
 	u8	res21[0x280];
 	u32	pllpgsr;	/* 0xc00 Platform PLL General Status */
 	u8	res16[0x1c];
 	u32	plldgsr;	/* 0xc20 DDR PLL General Status */
 	u8	res17[0x3dc];
 } ccsr_clk_t;
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 typedef struct ccsr_rcpm {
 	u8	res_00[12];
 	u32	tph10sr0;	/* Thread PH10 Status Register */
 	u8	res_10[12];
 	u32	tph10setr0;	/* Thread PH10 Set Control Register */
 	u8	res_20[12];
 	u32	tph10clrr0;	/* Thread PH10 Clear Control Register */
 	u8	res_30[12];
 	u32	tph10psr0;	/* Thread PH10 Previous Status Register */
 	u8	res_40[12];
 	u32	twaitsr0;	/* Thread Wait Status Register */
 	u8	res_50[96];
 	u32	pcph15sr;	/* Physical Core PH15 Status Register */
 	u32	pcph15setr;	/* Physical Core PH15 Set Control Register */
 	u32	pcph15clrr;	/* Physical Core PH15 Clear Control Register */
 	u32	pcph15psr;	/* Physical Core PH15 Prev Status Register */
 	u8	res_c0[16];
 	u32	pcph20sr;	/* Physical Core PH20 Status Register */
 	u32	pcph20setr;	/* Physical Core PH20 Set Control Register */
 	u32	pcph20clrr;	/* Physical Core PH20 Clear Control Register */
 	u32	pcph20psr;	/* Physical Core PH20 Prev Status Register */
 	u32	pcpw20sr;	/* Physical Core PW20 Status Register */
 	u8	res_e0[12];
 	u32	pcph30sr;	/* Physical Core PH30 Status Register */
 	u32	pcph30setr;	/* Physical Core PH30 Set Control Register */
 	u32	pcph30clrr;	/* Physical Core PH30 Clear Control Register */
 	u32	pcph30psr;	/* Physical Core PH30 Prev Status Register */
 	u8	res_100[32];
 	u32	ippwrgatecr;	/* IP Power Gating Control Register */
 	u8	res_124[12];
 	u32	powmgtcsr;	/* Power Management Control & Status Reg */
 	u8	res_134[12];
 	u32	ippdexpcr[4];	/* IP Powerdown Exception Control Reg */
 	u8	res_150[12];
 	u32	tpmimr0;	/* Thread PM Interrupt Mask Reg */
 	u8	res_160[12];
 	u32	tpmcimr0;	/* Thread PM Crit Interrupt Mask Reg */
 	u8	res_170[12];
 	u32	tpmmcmr0;	/* Thread PM Machine Check Interrupt Mask Reg */
 	u8	res_180[12];
 	u32	tpmnmimr0;	/* Thread PM NMI Mask Reg */
 	u8	res_190[12];
 	u32	tmcpmaskcr0;	/* Thread Machine Check Mask Control Reg */
 	u32	pctbenr;	/* Physical Core Time Base Enable Reg */
 	u32	pctbclkselr;	/* Physical Core Time Base Clock Select */
 	u32	tbclkdivr;	/* Time Base Clock Divider Register */
 	u8	res_1ac[4];
 	u32	ttbhltcr[4];	/* Thread Time Base Halt Control Register */
 	u32	clpcl10sr;	/* Cluster PCL10 Status Register */
 	u32	clpcl10setr;	/* Cluster PCL30 Set Control Register */
 	u32	clpcl10clrr;	/* Cluster PCL30 Clear Control Register */
 	u32	clpcl10psr;	/* Cluster PCL30 Prev Status Register */
 	u32	cddslpsetr;	/* Core Domain Deep Sleep Set Register */
 	u32	cddslpclrr;	/* Core Domain Deep Sleep Clear Register */
 	u32	cdpwroksetr;	/* Core Domain Power OK Set Register */
 	u32	cdpwrokclrr;	/* Core Domain Power OK Clear Register */
 	u32	cdpwrensr;	/* Core Domain Power Enable Status Register */
 	u32	cddslsr;	/* Core Domain Deep Sleep Status Register */
 	u8	res_1e8[8];
 	u32	dslpcntcr[8];	/* Deep Sleep Counter Cfg Register */
 	u8	res_300[3568];
 } ccsr_rcpm_t;
 #define ctbenrl pctbenr
 #else
 typedef struct ccsr_rcpm {
 	u8	res1[4];
 	u32	cdozsrl;	/* Core Doze Status */
 	u8	res2[4];
 	u32	cdozcrl;	/* Core Doze Control */
 	u8	res3[4];
 	u32	cnapsrl;	/* Core Nap Status */
 	u8	res4[4];
 	u32	cnapcrl;	/* Core Nap Control */
 	u8	res5[4];
 	u32	cdozpsrl;	/* Core Doze Previous Status */
 	u8	res6[4];
 	u32	cdozpcrl;	/* Core Doze Previous Control */
 	u8	res7[4];
 	u32	cwaitsrl;	/* Core Wait Status */
 	u8	res8[8];
 	u32	powmgtcsr;	/* Power Mangement Control & Status */
 	u8	res9[12];
 	u32	ippdexpcr0;	/* IP Powerdown Exception Control 0 */
 	u8	res10[12];
 	u8	res11[4];
 	u32	cpmimrl;	/* Core PM IRQ Masking */
 	u8	res12[4];
 	u32	cpmcimrl;	/* Core PM Critical IRQ Masking */
 	u8	res13[4];
 	u32	cpmmcimrl;	/* Core PM Machine Check IRQ Masking */
 	u8	res14[4];
 	u32	cpmnmimrl;	/* Core PM NMI Masking */
 	u8	res15[4];
 	u32	ctbenrl;	/* Core Time Base Enable */
 	u8	res16[4];
 	u32	ctbclkselrl;	/* Core Time Base Clock Select */
 	u8	res17[4];
 	u32	ctbhltcrl;	/* Core Time Base Halt Control */
 	u8	res18[0xf68];
 } ccsr_rcpm_t;
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #else
 typedef struct ccsr_gur {
 	u32	porpllsr;	/* POR PLL ratio status */
 #ifdef CONFIG_MPC8536
 #define MPC85xx_PORPLLSR_DDR_RATIO	0x3e000000
 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	25
 #elif defined(CONFIG_PPC_C29X)
 #define MPC85xx_PORPLLSR_DDR_RATIO	0x00003f00
 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	(9 - ((gur->pordevsr2 \
 					& MPC85xx_PORDEVSR2_DDR_SPD_0) \
 					>> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
 #else
 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
 #define MPC85xx_PORPLLSR_DDR_RATIO	0x00003f00
 #else
 #define MPC85xx_PORPLLSR_DDR_RATIO	0x00003e00
 #endif
 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	9
 #endif
 #define MPC85xx_PORPLLSR_QE_RATIO	0x3e000000
 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT		25
 #define MPC85xx_PORPLLSR_PLAT_RATIO	0x0000003e
 #define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT	1
 	u32	porbmsr;	/* POR boot mode status */
 #define MPC85xx_PORBMSR_HA		0x00070000
 #define MPC85xx_PORBMSR_HA_SHIFT	16
 #define MPC85xx_PORBMSR_ROMLOC_SHIFT	24
 #define PORBMSR_ROMLOC_SPI	0x6
 #define PORBMSR_ROMLOC_SDHC	0x7
 #define PORBMSR_ROMLOC_NAND_2K	0x9
 #define PORBMSR_ROMLOC_NOR	0xf
 	u32	porimpscr;	/* POR I/O impedance status & control */
 	u32	pordevsr;	/* POR I/O device status regsiter */
 #if defined(CONFIG_P1017) || defined(CONFIG_P1023)
 #define MPC85xx_PORDEVSR_SGMII1_DIS	0x10000000
 #define MPC85xx_PORDEVSR_SGMII2_DIS	0x08000000
 #define MPC85xx_PORDEVSR_TSEC1_PRTC	0x02000000
 #else
 #define MPC85xx_PORDEVSR_SGMII1_DIS	0x20000000
 #define MPC85xx_PORDEVSR_SGMII2_DIS	0x10000000
 #endif
 #define MPC85xx_PORDEVSR_SGMII3_DIS	0x08000000
 #define MPC85xx_PORDEVSR_SGMII4_DIS	0x04000000
 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL	0x38000000
 #define MPC85xx_PORDEVSR_PCI1		0x00800000
 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
 #define MPC85xx_PORDEVSR_IO_SEL		0x007c0000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	18
 #elif defined(CONFIG_P1017) || defined(CONFIG_P1023)
 #define MPC85xx_PORDEVSR_IO_SEL		0x00600000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	21
 #else
 #if defined(CONFIG_P1010)
 #define MPC85xx_PORDEVSR_IO_SEL		0x00600000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	21
 #elif defined(CONFIG_BSC9132)
 #define MPC85xx_PORDEVSR_IO_SEL		0x00FE0000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	17
 #elif defined(CONFIG_PPC_C29X)
 #define MPC85xx_PORDEVSR_IO_SEL		0x00e00000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	21
 #else
 #define MPC85xx_PORDEVSR_IO_SEL		0x00780000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	19
 #endif /* if defined(CONFIG_P1010) */
 #endif
 #define MPC85xx_PORDEVSR_PCI2_ARB	0x00040000
 #define MPC85xx_PORDEVSR_PCI1_ARB	0x00020000
 #define MPC85xx_PORDEVSR_PCI1_PCI32	0x00010000
 #define MPC85xx_PORDEVSR_PCI1_SPD	0x00008000
 #define MPC85xx_PORDEVSR_PCI2_SPD	0x00004000
 #define MPC85xx_PORDEVSR_DRAM_RTYPE	0x00000060
 #define MPC85xx_PORDEVSR_RIO_CTLS	0x00000008
 #define MPC85xx_PORDEVSR_RIO_DEV_ID	0x00000007
 	u32	pordbgmsr;	/* POR debug mode status */
 	u32	pordevsr2;	/* POR I/O device status 2 */
 #if defined(CONFIG_PPC_C29X)
 #define MPC85xx_PORDEVSR2_DDR_SPD_0	0x00000008
 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT	3
 #endif
 /* The 8544 RM says this is bit 26, but it's really bit 24 */
 #define MPC85xx_PORDEVSR2_SEC_CFG	0x00000080
 	u8	res1[8];
 	u32	gpporcr;	/* General-purpose POR configuration */
 	u8	res2[12];
 #if defined(CONFIG_MPC8536)
 	u32	gencfgr;	/* General Configuration Register */
 #define MPC85xx_GENCFGR_SDHC_WP_INV	0x20000000
 #else
 	u32	gpiocr;		/* GPIO control */
 #endif
 	u8	res3[12];
 #if defined(CONFIG_MPC8569)
 	u32	plppar1;	/* Platform port pin assignment 1 */
 	u32	plppar2;	/* Platform port pin assignment 2 */
 	u32	plpdir1;	/* Platform port pin direction 1 */
 	u32	plpdir2;	/* Platform port pin direction 2 */
 #else
 	u32	gpoutdr;	/* General-purpose output data */
 	u8	res4[12];
 #endif
 	u32	gpindr;		/* General-purpose input data */
 	u8	res5[12];
 	u32	pmuxcr;		/* Alt. function signal multiplex control */
 #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
 #define MPC85xx_PMUXCR_TSEC1_0_1588		0x40000000
 #define MPC85xx_PMUXCR_TSEC1_0_RES		0xC0000000
 #define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG	0x10000000
 #define MPC85xx_PMUXCR_TSEC1_1_GPIO_12		0x20000000
 #define MPC85xx_PMUXCR_TSEC1_1_RES		0x30000000
 #define MPC85xx_PMUXCR_TSEC1_2_DMA		0x04000000
 #define MPC85xx_PMUXCR_TSEC1_2_GPIO		0x08000000
 #define MPC85xx_PMUXCR_TSEC1_2_RES		0x0C000000
 #define MPC85xx_PMUXCR_TSEC1_3_RES		0x01000000
 #define MPC85xx_PMUXCR_TSEC1_3_GPIO_15		0x02000000
 #define MPC85xx_PMUXCR_IFC_ADDR16_SDHC		0x00400000
 #define MPC85xx_PMUXCR_IFC_ADDR16_USB		0x00800000
 #define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2	0x00C00000
 #define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC	0x00100000
 #define MPC85xx_PMUXCR_IFC_ADDR17_18_USB	0x00200000
 #define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA	0x00300000
 #define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA	0x00040000
 #define MPC85xx_PMUXCR_IFC_ADDR19_USB		0x00080000
 #define MPC85xx_PMUXCR_IFC_ADDR19_DMA		0x000C0000
 #define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA	0x00010000
 #define MPC85xx_PMUXCR_IFC_ADDR20_21_USB	0x00020000
 #define MPC85xx_PMUXCR_IFC_ADDR20_21_RES	0x00030000
 #define MPC85xx_PMUXCR_IFC_ADDR22_SDHC		0x00004000
 #define MPC85xx_PMUXCR_IFC_ADDR22_USB		0x00008000
 #define MPC85xx_PMUXCR_IFC_ADDR22_RES		0x0000C000
 #define MPC85xx_PMUXCR_IFC_ADDR23_SDHC		0x00001000
 #define MPC85xx_PMUXCR_IFC_ADDR23_USB		0x00002000
 #define MPC85xx_PMUXCR_IFC_ADDR23_RES		0x00003000
 #define MPC85xx_PMUXCR_IFC_ADDR24_SDHC		0x00000400
 #define MPC85xx_PMUXCR_IFC_ADDR24_USB		0x00000800
 #define MPC85xx_PMUXCR_IFC_ADDR24_RES		0x00000C00
 #define MPC85xx_PMUXCR_IFC_PAR_PERR_RES		0x00000300
 #define MPC85xx_PMUXCR_IFC_PAR_PERR_USB		0x00000200
 #define MPC85xx_PMUXCR_LCLK_RES			0x00000040
 #define MPC85xx_PMUXCR_LCLK_USB			0x00000080
 #define MPC85xx_PMUXCR_LCLK_IFC_CS3		0x000000C0
 #define MPC85xx_PMUXCR_SPI_RES			0x00000030
 #define MPC85xx_PMUXCR_SPI_GPIO			0x00000020
 #define MPC85xx_PMUXCR_CAN1_UART		0x00000004
 #define MPC85xx_PMUXCR_CAN1_TDM			0x00000008
 #define MPC85xx_PMUXCR_CAN1_RES			0x0000000C
 #define MPC85xx_PMUXCR_CAN2_UART		0x00000001
 #define MPC85xx_PMUXCR_CAN2_TDM			0x00000002
 #define MPC85xx_PMUXCR_CAN2_RES			0x00000003
 #endif
 #if defined(CONFIG_P1017) || defined(CONFIG_P1023)
 #define MPC85xx_PMUXCR_TSEC1_1		0x10000000
 #else
 #define MPC85xx_PMUXCR_SD_DATA		0x80000000
 #define MPC85xx_PMUXCR_SDHC_CD		0x40000000
 #define MPC85xx_PMUXCR_SDHC_WP		0x20000000
 #define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON	0x01000000
 #define MPC85xx_PMUXCR_TDM_ENA		0x00800000
 #define MPC85xx_PMUXCR_QE0		0x00008000
 #define MPC85xx_PMUXCR_QE1		0x00004000
 #define MPC85xx_PMUXCR_QE2		0x00002000
 #define MPC85xx_PMUXCR_QE3		0x00001000
 #define MPC85xx_PMUXCR_QE4		0x00000800
 #define MPC85xx_PMUXCR_QE5		0x00000400
 #define MPC85xx_PMUXCR_QE6		0x00000200
 #define MPC85xx_PMUXCR_QE7		0x00000100
 #define MPC85xx_PMUXCR_QE8		0x00000080
 #define MPC85xx_PMUXCR_QE9		0x00000040
 #define MPC85xx_PMUXCR_QE10		0x00000020
 #define MPC85xx_PMUXCR_QE11		0x00000010
 #define MPC85xx_PMUXCR_QE12		0x00000008
 #endif
 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
 #define MPC85xx_PMUXCR_TDM_MASK		0x0001cc00
 #define MPC85xx_PMUXCR_TDM		0x00014800
 #define MPC85xx_PMUXCR_SPI_MASK		0x00600000
 #define MPC85xx_PMUXCR_SPI		0x00000000
 #endif
 #if defined(CONFIG_BSC9131)
 #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ	0x40000000
 #define MPC85xx_PMUXCR_TSEC2_USB		0xC0000000
 #define MPC85xx_PMUXCR_TSEC2_1588_PPS		0x10000000
 #define MPC85xx_PMUXCR_TSEC2_1588_RSVD		0x30000000
 #define MPC85xx_PMUXCR_IFC_AD_GPIO		0x04000000
 #define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK		0x0C000000
 #define MPC85xx_PMUXCR_IFC_AD15_GPIO		0x01000000
 #define MPC85xx_PMUXCR_IFC_AD15_TIMER2		0x02000000
 #define MPC85xx_PMUXCR_IFC_AD16_GPO8		0x00400000
 #define MPC85xx_PMUXCR_IFC_AD16_MSRCID0		0x00800000
 #define MPC85xx_PMUXCR_IFC_AD17_GPO		0x00100000
 #define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK	0x00300000
 #define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP	0x00200000
 #define MPC85xx_PMUXCR_IFC_CS2_GPO65		0x00040000
 #define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI		0x00080000
 #define MPC85xx_PMUXCR_SDHC_USIM		0x00010000
 #define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK		0x00020000
 #define MPC85xx_PMUXCR_SDHC_GPIO77		0x00030000
 #define MPC85xx_PMUXCR_SDHC_RESV		0x00004000
 #define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD		0x00008000
 #define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4		0x0000C000
 #define MPC85xx_PMUXCR_USB_CLK_UART_SIN		0x00001000
 #define MPC85xx_PMUXCR_USB_CLK_GPIO69		0x00002000
 #define MPC85xx_PMUXCR_USB_CLK_TIMER3		0x00003000
 #define MPC85xx_PMUXCR_USB_UART_GPIO0		0x00000400
 #define MPC85xx_PMUXCR_USB_RSVD			0x00000C00
 #define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN	0x00000800
 #define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL	0x00000100
 #define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72	0x00000200
 #define MPC85xx_PMUXCR_USB_D1_2_RSVD		0x00000300
 #define MPC85xx_PMUXCR_USB_DIR_GPIO2		0x00000040
 #define MPC85xx_PMUXCR_USB_DIR_TIMER1		0x00000080
 #define MPC85xx_PMUXCR_USB_DIR_MCP_B		0x000000C0
 #define MPC85xx_PMUXCR_SPI1_UART3		0x00000010
 #define MPC85xx_PMUXCR_SPI1_SIM			0x00000020
 #define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74	0x00000030
 #define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B	0x00000004
 #define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen	0x00000008
 #define MPC85xx_PMUXCR_SPI1_CS2_GPO75		0x0000000C
 #define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM	0x00000001
 #define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen	0x00000002
 #define MPC85xx_PMUXCR_SPI1_CS3_GPO76		0x00000003
 #endif
 #ifdef CONFIG_BSC9132
 #define MPC85xx_PMUXCR0_SIM_SEL_MASK	0x0003b000
 #define MPC85xx_PMUXCR0_SIM_SEL		0x00014000
 #endif
 #if defined(CONFIG_PPC_C29X)
 #define MPC85xx_PMUXCR_SPI_MASK			0x00000300
 #define MPC85xx_PMUXCR_SPI			0x00000000
 #define MPC85xx_PMUXCR_SPI_GPIO			0x00000100
 #endif
 	u32	pmuxcr2;	/* Alt. function signal multiplex control 2 */
 #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
 #define MPC85xx_PMUXCR2_UART_GPIO		0x40000000
 #define MPC85xx_PMUXCR2_UART_TDM		0x80000000
 #define MPC85xx_PMUXCR2_UART_RES		0xC0000000
 #define MPC85xx_PMUXCR2_IRQ2_TRIG_IN		0x10000000
 #define MPC85xx_PMUXCR2_IRQ2_RES		0x30000000
 #define MPC85xx_PMUXCR2_IRQ3_SRESET		0x04000000
 #define MPC85xx_PMUXCR2_IRQ3_RES		0x0C000000
 #define MPC85xx_PMUXCR2_GPIO01_DRVVBUS		0x01000000
 #define MPC85xx_PMUXCR2_GPIO01_RES		0x03000000
 #define MPC85xx_PMUXCR2_GPIO23_CKSTP		0x00400000
 #define MPC85xx_PMUXCR2_GPIO23_RES		0x00800000
 #define MPC85xx_PMUXCR2_GPIO23_USB		0x00C00000
 #define MPC85xx_PMUXCR2_GPIO4_MCP		0x00100000
 #define MPC85xx_PMUXCR2_GPIO4_RES		0x00200000
 #define MPC85xx_PMUXCR2_GPIO4_CLK_OUT		0x00300000
 #define MPC85xx_PMUXCR2_GPIO5_UDE		0x00040000
 #define MPC85xx_PMUXCR2_GPIO5_RES		0x00080000
 #define MPC85xx_PMUXCR2_READY_ASLEEP		0x00020000
 #define MPC85xx_PMUXCR2_DDR_ECC_MUX		0x00010000
 #define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE	0x00008000
 #define MPC85xx_PMUXCR2_POST_EXPOSE		0x00004000
 #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY	0x00002000
 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE		0x00001000
 #endif
 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
 #define MPC85xx_PMUXCR2_ETSECUSB_MASK	0x001f8000
 #define MPC85xx_PMUXCR2_USB		0x00150000
 #endif
 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
 #if defined(CONFIG_BSC9131)
 #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD		0X40000000
 #define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS		0X80000000
 #define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42		0xC0000000
 #define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2		0x10000000
 #define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK		0x20000000
 #define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43		0x30000000
 #define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD		0x04000000
 #define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B		0x08000000
 #define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44		0x0C000000
 #define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED		0x01000000
 #define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD		0x02000000
 #define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45		0x03000000
 #define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP			0x00400000
 #define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B		0x00800000
 #define MPC85xx_PMUXCR2_ANT1_TIMER5			0x00100000
 #define MPC85xx_PMUXCR2_ANT1_TSEC_1588			0x00200000
 #define MPC85xx_PMUXCR2_ANT1_GPIO95_19			0x00300000
 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK	0x00040000
 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD		0x00080000
 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20	0x000C0000
 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0		0x00010000
 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3		0x00020000
 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84		0x00030000
 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4		0x00004000
 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7		0x00008000
 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88		0x0000C000
 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK		0x00001000
 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9		0x00002000
 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22		0x00003000
 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7		0x00000400
 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11	0x00000800
 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24		0x00000C00
 #define MPC85xx_PMUXCR2_ANT2_RSVD			0x00000100
 #define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA		0x00000300
 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB		0x00000040
 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO	0x000000C0
 #define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD			0x00000010
 #define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8		0x00000020
 #define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61		0x00000030
 #define MPC85xx_PMUXCR2_ANT3_AGC_GPO53			0x00000004
 #define MPC85xx_PMUXCR2_ANT3_DO_TDM			0x00000001
 #define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49		0x00000002
 #endif
 	u32	pmuxcr3;
 #if defined(CONFIG_BSC9131)
 #define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM			0x40000000
 #define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51		0x80000000
 #define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B	0x10000000
 #define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53		0x20000000
 #define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B			0x04000000
 #define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54			0x08000000
 #define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT	0x01000000
 #define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56		0x02000000
 #define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT		0x00400000
 #define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57		0x00800000
 #define MPC85xx_PMUXCR3_SPI2_CS2_GPO93			0x00100000
 #define MPC85xx_PMUXCR3_SPI2_CS3_GPO94			0x00040000
 #define MPC85xx_PMUXCR3_ANT2_AGC_RSVD			0x00010000
 #define MPC85xx_PMUXCR3_ANT2_GPO89			0x00030000
 #endif
 #ifdef CONFIG_BSC9132
 #define MPC85xx_PMUXCR3_USB_SEL_MASK	0x0000ff00
 #define MPC85xx_PMUXCR3_UART2_SEL	0x00005000
 #define MPC85xx_PMUXCR3_UART3_SEL_MASK	0xc0000000
 #define MPC85xx_PMUXCR3_UART3_SEL	0x40000000
 #endif
 	u32 pmuxcr4;
 #else
 	u8	res6[8];
 #endif
 	u32	devdisr;	/* Device disable control */
 #define MPC85xx_DEVDISR_PCI1		0x80000000
 #define MPC85xx_DEVDISR_PCI2		0x40000000
 #define MPC85xx_DEVDISR_PCIE		0x20000000
 #define MPC85xx_DEVDISR_LBC		0x08000000
 #define MPC85xx_DEVDISR_PCIE2		0x04000000
 #define MPC85xx_DEVDISR_PCIE3		0x02000000
 #define MPC85xx_DEVDISR_SEC		0x01000000
 #define MPC85xx_DEVDISR_SRIO		0x00080000
 #define MPC85xx_DEVDISR_RMSG		0x00040000
 #define MPC85xx_DEVDISR_DDR		0x00010000
 #define MPC85xx_DEVDISR_CPU		0x00008000
 #define MPC85xx_DEVDISR_CPU0		MPC85xx_DEVDISR_CPU
 #define MPC85xx_DEVDISR_TB		0x00004000
 #define MPC85xx_DEVDISR_TB0		MPC85xx_DEVDISR_TB
 #define MPC85xx_DEVDISR_CPU1		0x00002000
 #define MPC85xx_DEVDISR_TB1		0x00001000
 #define MPC85xx_DEVDISR_DMA		0x00000400
 #define MPC85xx_DEVDISR_TSEC1		0x00000080
 #define MPC85xx_DEVDISR_TSEC2		0x00000040
 #define MPC85xx_DEVDISR_TSEC3		0x00000020
 #define MPC85xx_DEVDISR_TSEC4		0x00000010
 #define MPC85xx_DEVDISR_I2C		0x00000004
 #define MPC85xx_DEVDISR_DUART		0x00000002
 	u8	res7[12];
 	u32	powmgtcsr;	/* Power management status & control */
 	u8	res8[12];
 	u32	mcpsumr;	/* Machine check summary */
 	u8	res9[12];
 	u32	pvr;		/* Processor version */
 	u32	svr;		/* System version */
 	u8	res10[8];
 	u32	rstcr;		/* Reset control */
 #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
 	u8	res11a[76];
 	par_io_t qe_par_io[7];
 	u8	res11b[1600];
 #elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
 	u8      res11a[12];
 	u32     iovselsr;
 	u8      res11b[60];
 	par_io_t qe_par_io[3];
 	u8      res11c[1496];
 #else
 	u8	res11a[1868];
 #endif
 	u32	clkdvdr;	/* Clock Divide register */
 	u8	res12[1532];
 	u32	clkocr;		/* Clock out select */
 	u8	res13[12];
 	u32	ddrdllcr;	/* DDR DLL control */
 	u8	res14[12];
 	u32	lbcdllcr;	/* LBC DLL control */
 #if defined(CONFIG_BSC9131)
 	u8	res15[12];
 	u32	halt_req_mask;
 #define HALTED_TO_HALT_REQ_MASK_0	0x80000000
 	u8	res18[232];
 #else
 	u8	res15[248];
 #endif
 	u32	lbiuiplldcr0;	/* LBIU PLL Debug Reg 0 */
 	u32	lbiuiplldcr1;	/* LBIU PLL Debug Reg 1 */
 	u32	ddrioovcr;	/* DDR IO Override Control */
 	u32	tsec12ioovcr;	/* eTSEC 1/2 IO override control */
 	u32	tsec34ioovcr;	/* eTSEC 3/4 IO override control */
 	u8      res16[52];
 	u32	sdhcdcr;	/* SDHC debug control register */
 	u8      res17[61592];
 } ccsr_gur_t;
 #endif
 #define SDHCDCR_CD_INV		0x80000000 /* invert SDHC card detect */
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 #define MAX_SERDES 4
 #define SRDS_MAX_LANES 8
 #define SRDS_MAX_BANK 2
 typedef struct serdes_corenet {
 	struct {
 		u32	rstctl;	/* Reset Control Register */
 #define SRDS_RSTCTL_RST		0x80000000
 #define SRDS_RSTCTL_RSTDONE	0x40000000
 #define SRDS_RSTCTL_RSTERR	0x20000000
 #define SRDS_RSTCTL_SWRST	0x10000000
 #define SRDS_RSTCTL_SDEN	0x00000020
 #define SRDS_RSTCTL_SDRST_B	0x00000040
 #define SRDS_RSTCTL_PLLRST_B	0x00000080
 		u32	pllcr0; /* PLL Control Register 0 */
 #define SRDS_PLLCR0_POFF		0x80000000
 #define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
 #define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
 #define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
 #define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
 #define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
 #define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
 #define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
 #define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
 #define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
 #define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
 #define SRDS_PLLCR0_FRATE_SEL_5_15	0x00060000
 #define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
 #define SRDS_PLLCR0_FRATE_SEL_3_12	0x00090000
 #define SRDS_PLLCR0_FRATE_SEL_3		0x000a0000
 		u32	pllcr1; /* PLL Control Register 1 */
 #define SRDS_PLLCR1_PLL_BWSEL	0x08000000
 		u32	res_0c;	/* 0x00c */
 		u32	pllcr3;
 		u32	pllcr4;
 		u8	res_18[0x20-0x18];
 	} bank[2];
 	u8	res_40[0x90-0x40];
 	u32	srdstcalcr;	/* 0x90 TX Calibration Control */
 	u8	res_94[0xa0-0x94];
 	u32	srdsrcalcr;	/* 0xa0 RX Calibration Control */
 	u8	res_a4[0xb0-0xa4];
 	u32	srdsgr0;	/* 0xb0 General Register 0 */
 	u8	res_b4[0xe0-0xb4];
 	u32	srdspccr0;	/* 0xe0 Protocol Converter Config 0 */
 	u32	srdspccr1;	/* 0xe4 Protocol Converter Config 1 */
 	u32	srdspccr2;	/* 0xe8 Protocol Converter Config 2 */
 	u32	srdspccr3;	/* 0xec Protocol Converter Config 3 */
 	u32	srdspccr4;	/* 0xf0 Protocol Converter Config 4 */
 	u8	res_f4[0x100-0xf4];
 	struct {
 		u32	lnpssr;	/* 0x100, 0x120, ..., 0x1e0 */
 		u8	res_104[0x120-0x104];
 	} srdslnpssr[8];
 	u8	res_200[0x800-0x200];
 	struct {
 		u32	gcr0;	/* 0x800 General Control Register 0 */
 		u32	gcr1;	/* 0x804 General Control Register 1 */
 		u32	gcr2;	/* 0x808 General Control Register 2 */
 		u32	res_80c;
 		u32	recr0;	/* 0x810 Receive Equalization Control */
 		u32	res_814;
 		u32	tecr0;	/* 0x818 Transmit Equalization Control */
 		u32	res_81c;
 		u32	ttlcr0;	/* 0x820 Transition Tracking Loop Ctrl 0 */
 		u8	res_824[0x840-0x824];
 	} lane[8];	/* Lane A, B, C, D, E, F, G, H */
 	u8	res_a00[0x1000-0xa00];	/* from 0xa00 to 0xfff */
 } serdes_corenet_t;
 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #define SRDS_MAX_LANES		18
 #define SRDS_MAX_BANK		3
 typedef struct serdes_corenet {
 	struct {
 		u32	rstctl;	/* Reset Control Register */
 #define SRDS_RSTCTL_RST		0x80000000
 #define SRDS_RSTCTL_RSTDONE	0x40000000
 #define SRDS_RSTCTL_RSTERR	0x20000000
 #define SRDS_RSTCTL_SDPD	0x00000020
 		u32	pllcr0; /* PLL Control Register 0 */
 #define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
 #define SRDS_PLLCR0_PVCOCNT_EN		0x02000000
 #define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
 #define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
 #define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
 #define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
 #define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
 #define SRDS_PLLCR0_FRATE_SEL_MASK	0x00030000
 #define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
 #define SRDS_PLLCR0_FRATE_SEL_6_25	0x00010000
 		u32	pllcr1; /* PLL Control Register 1 */
 #define SRDS_PLLCR1_PLL_BWSEL	0x08000000
 		u32	res[5];
 	} bank[3];
 	u32	res1[12];
 	u32	srdstcalcr;	/* TX Calibration Control */
 	u32	res2[3];
 	u32	srdsrcalcr;	/* RX Calibration Control */
 	u32	res3[3];
 	u32	srdsgr0;	/* General Register 0 */
 	u32	res4[11];
 	u32	srdspccr0;	/* Protocol Converter Config 0 */
 	u32	srdspccr1;	/* Protocol Converter Config 1 */
 	u32	srdspccr2;	/* Protocol Converter Config 2 */
 #define SRDS_PCCR2_RST_XGMII1		0x00800000
 #define SRDS_PCCR2_RST_XGMII2		0x00400000
 	u32	res5[197];
 	struct serdes_lane {
 		u32	gcr0;	/* General Control Register 0 */
 #define SRDS_GCR0_RRST			0x00400000
 #define SRDS_GCR0_1STLANE		0x00010000
 #define SRDS_GCR0_UOTHL			0x00100000
 		u32	gcr1;	/* General Control Register 1 */
 #define SRDS_GCR1_REIDL_CTL_MASK	0x001f0000
 #define SRDS_GCR1_REIDL_CTL_PCIE	0x00100000
 #define SRDS_GCR1_REIDL_CTL_SRIO	0x00000000
 #define SRDS_GCR1_REIDL_CTL_SGMII	0x00040000
 #define SRDS_GCR1_OPAD_CTL		0x04000000
 		u32	res1[4];
 		u32	tecr0;	/* TX Equalization Control Reg 0 */
 #define SRDS_TECR0_TEQ_TYPE_MASK	0x30000000
 #define SRDS_TECR0_TEQ_TYPE_2LVL	0x10000000
 		u32	res3;
 		u32	ttlcr0;	/* Transition Tracking Loop Ctrl 0 */
 #define SRDS_TTLCR0_FLT_SEL_MASK	0x3f000000
 #define SRDS_TTLCR0_FLT_SEL_KFR_26	0x10000000
 #define SRDS_TTLCR0_FLT_SEL_KPH_28	0x08000000
 #define SRDS_TTLCR0_FLT_SEL_750PPM	0x03000000
 #define SRDS_TTLCR0_PM_DIS		0x00004000
 #define SRDS_TTLCR0_FREQOVD_EN		0x00000001
 		u32	res4[7];
 	} lane[24];
 	u32 res6[384];
 } serdes_corenet_t;
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 enum {
 	FSL_SRDS_B1_LANE_A = 0,
 	FSL_SRDS_B1_LANE_B = 1,
 	FSL_SRDS_B1_LANE_C = 2,
 	FSL_SRDS_B1_LANE_D = 3,
 	FSL_SRDS_B1_LANE_E = 4,
 	FSL_SRDS_B1_LANE_F = 5,
 	FSL_SRDS_B1_LANE_G = 6,
 	FSL_SRDS_B1_LANE_H = 7,
 	FSL_SRDS_B1_LANE_I = 8,
 	FSL_SRDS_B1_LANE_J = 9,
 	FSL_SRDS_B2_LANE_A = 16,
 	FSL_SRDS_B2_LANE_B = 17,
 	FSL_SRDS_B2_LANE_C = 18,
 	FSL_SRDS_B2_LANE_D = 19,
 	FSL_SRDS_B3_LANE_A = 20,
 	FSL_SRDS_B3_LANE_B = 21,
 	FSL_SRDS_B3_LANE_C = 22,
 	FSL_SRDS_B3_LANE_D = 23,
 };
 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
 typedef struct ccsr_sec {
 	u32	res0;
 	u32	mcfgr;		/* Master CFG Register */
 	u8	res1[0x8];
 	struct {
 		u32	ms;	/* Job Ring LIODN Register, MS */
 		u32	ls;	/* Job Ring LIODN Register, LS */
 	} jrliodnr[4];
 	u8	res2[0x30];
 	struct {
 		u32	ms;	/* RTIC LIODN Register, MS */
 		u32	ls;	/* RTIC LIODN Register, LS */
 	} rticliodnr[4];
 	u8	res3[0x1c];
 	u32	decorr;		/* DECO Request Register */
 	struct {
 		u32	ms;	/* DECO LIODN Register, MS */
 		u32	ls;	/* DECO LIODN Register, LS */
 	} decoliodnr[8];
 	u8	res4[0x40];
 	u32	dar;		/* DECO Avail Register */
 	u32	drr;		/* DECO Reset Register */
 	u8	res5[0xe78];
 	u32	crnr_ms;	/* CHA Revision Number Register, MS */
 	u32	crnr_ls;	/* CHA Revision Number Register, LS */
 	u32	ctpr_ms;	/* Compile Time Parameters Register, MS */
 	u32	ctpr_ls;	/* Compile Time Parameters Register, LS */
 	u8	res6[0x10];
 	u32	far_ms;		/* Fault Address Register, MS */
 	u32	far_ls;		/* Fault Address Register, LS */
 	u32	falr;		/* Fault Address LIODN Register */
 	u32	fadr;		/* Fault Address Detail Register */
 	u8	res7[0x4];
 	u32	csta;		/* CAAM Status Register */
 	u8	res8[0x8];
 	u32	rvid;		/* Run Time Integrity Checking Version ID Reg.*/
 	u32	ccbvid;		/* CHA Cluster Block Version ID Register */
 	u32	chavid_ms;	/* CHA Version ID Register, MS */
 	u32	chavid_ls;	/* CHA Version ID Register, LS */
 	u32	chanum_ms;	/* CHA Number Register, MS */
 	u32	chanum_ls;	/* CHA Number Register, LS */
 	u32	secvid_ms;	/* SEC Version ID Register, MS */
 	u32	secvid_ls;	/* SEC Version ID Register, LS */
 	u8	res9[0x6020];
 	u32	qilcr_ms;	/* Queue Interface LIODN CFG Register, MS */
 	u32	qilcr_ls;	/* Queue Interface LIODN CFG Register, LS */
 	u8	res10[0x8fd8];
 } ccsr_sec_t;
 #define SEC_CTPR_MS_AXI_LIODN		0x08000000
 #define SEC_CTPR_MS_QI			0x02000000
 #define SEC_RVID_MA			0x0f000000
 #define SEC_CHANUM_MS_JRNUM_MASK	0xf0000000
 #define SEC_CHANUM_MS_JRNUM_SHIFT	28
 #define SEC_CHANUM_MS_DECONUM_MASK	0x0f000000
 #define SEC_CHANUM_MS_DECONUM_SHIFT	24
 #define SEC_SECVID_MS_IPID_MASK	0xffff0000
 #define SEC_SECVID_MS_IPID_SHIFT	16
 #define SEC_SECVID_MS_MAJ_REV_MASK	0x0000ff00
 #define SEC_SECVID_MS_MAJ_REV_SHIFT	8
 #define SEC_CCBVID_ERA_MASK		0xff000000
 #define SEC_CCBVID_ERA_SHIFT		24
 #endif
 typedef struct ccsr_qman {
 #ifdef CONFIG_SYS_FSL_QMAN_V3
 	u8	res0[0x200];
 #else
 	struct {
 		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
 		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
 		u32	res;
 		u32	qcsp_dd_cfg;	/* 0xc - SW Portal n Dynamic Debug cfg */
 	} qcsp[32];
 #endif
 	/* Not actually reserved, but irrelevant to u-boot */
 	u8	res[0xbf8 - 0x200];
 	u32	ip_rev_1;
 	u32	ip_rev_2;
 	u32	fqd_bare;	/* FQD Extended Base Addr Register */
 	u32	fqd_bar;	/* FQD Base Addr Register */
 	u8	res1[0x8];
 	u32	fqd_ar;		/* FQD Attributes Register */
 	u8	res2[0xc];
 	u32	pfdr_bare;	/* PFDR Extended Base Addr Register */
 	u32	pfdr_bar;	/* PFDR Base Addr Register */
 	u8	res3[0x8];
 	u32	pfdr_ar;	/* PFDR Attributes Register */
 	u8	res4[0x4c];
 	u32	qcsp_bare;	/* QCSP Extended Base Addr Register */
 	u32	qcsp_bar;	/* QCSP Base Addr Register */
 	u8	res5[0x78];
 	u32	ci_sched_cfg;	/* Initiator Scheduling Configuration */
 	u32	srcidr;		/* Source ID Register */
 	u32	liodnr;		/* LIODN Register */
 	u8	res6[4];
 	u32	ci_rlm_cfg;	/* Initiator Read Latency Monitor Cfg */
 	u32	ci_rlm_avg;	/* Initiator Read Latency Monitor Avg */
 	u8	res7[0x2e8];
 #ifdef CONFIG_SYS_FSL_QMAN_V3
 	struct {
 		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
 		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
 		u32	res;
 		u32	qcsp_dd_cfg;	/* 0xc - SW Portal n Dynamic Debug cfg*/
 	} qcsp[50];
 #endif
 } ccsr_qman_t;
 typedef struct ccsr_bman {
 	/* Not actually reserved, but irrelevant to u-boot */
 	u8	res[0xbf8];
 	u32	ip_rev_1;
 	u32	ip_rev_2;
 	u32	fbpr_bare;	/* FBPR Extended Base Addr Register */
 	u32	fbpr_bar;	/* FBPR Base Addr Register */
 	u8	res1[0x8];
 	u32	fbpr_ar;	/* FBPR Attributes Register */
 	u8	res2[0xf0];
 	u32	srcidr;		/* Source ID Register */
 	u32	liodnr;		/* LIODN Register */
 	u8	res7[0x2f4];
 } ccsr_bman_t;
 typedef struct ccsr_pme {
 	u8	res0[0x804];
 	u32	liodnbr;	/* LIODN Base Register */
 	u8	res1[0x1f8];
 	u32	srcidr;		/* Source ID Register */
 	u8	res2[8];
 	u32	liodnr;		/* LIODN Register */
 	u8	res3[0x1e8];
 	u32	pm_ip_rev_1;	/* PME IP Block Revision Reg 1*/
 	u32	pm_ip_rev_2;	/* PME IP Block Revision Reg 1*/
 	u8	res4[0x400];
 } ccsr_pme_t;
 #ifdef CONFIG_SYS_FSL_RAID_ENGINE
 struct ccsr_raide {
 	u8	res0[0x543];
 	u32	liodnbr;			/* LIODN Base Register */
 	u8	res1[0xab8];
 	struct {
 		struct {
 			u32	cfg0;		/* cfg register 0 */
 			u32	cfg1;		/* cfg register 1 */
 			u8	res1[0x3f8];
 		} ring[2];
 		u8	res[0x800];
 	} jq[2];
 };
 #endif
 #ifdef CONFIG_SYS_DPAA_RMAN
 struct ccsr_rman {
 	u8	res0[0xf64];
 	u32	mmliodnbr;	/* Message Manager LIODN Base Register */
 	u32	mmitar;		/* RMAN Inbound Translation Address Register */
 	u32	mmitdr;		/* RMAN Inbound Translation Data Register */
 	u8	res4[0x1f090];
 };
 #endif
 #ifdef CONFIG_SYS_PMAN
 struct ccsr_pman {
 	u8	res_00[0x40];
 	u32	poes1;		/* PMAN Operation Error Status Register 1 */
 	u32	poes2;		/* PMAN Operation Error Status Register 2 */
 	u32	poeah;		/* PMAN Operation Error Address High */
 	u32	poeal;		/* PMAN Operation Error Address Low */
 	u8	res_50[0x50];
 	u32	pr1;		/* PMAN Revision Register 1 */
 	u32	pr2;		/* PMAN Revision Register 2 */
 	u8	res_a8[0x8];
 	u32	pcap;		/* PMAN Capabilities Register */
 	u8	res_b4[0xc];
 	u32	pc1;		/* PMAN Control Register 1 */
 	u32	pc2;		/* PMAN Control Register 2 */
 	u32	pc3;		/* PMAN Control Register 3 */
 	u32	pc4;		/* PMAN Control Register 4 */
 	u32	pc5;		/* PMAN Control Register 5 */
 	u32	pc6;		/* PMAN Control Register 6 */
 	u8	res_d8[0x8];
 	u32	ppa1;		/* PMAN Prefetch Attributes Register 1 */
 	u32	ppa2;		/* PMAN Prefetch Attributes Register 2 */
 	u8	res_e8[0x8];
 	u32	pics;		/* PMAN Interrupt Control and Status */
 	u8	res_f4[0xf0c];
 };
 #endif
 #ifdef CONFIG_FSL_CORENET
 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET	0x0000
 #ifdef CONFIG_SYS_PMAN
 #define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET	0x4000
 #define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET	0x5000
 #define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET	0x6000
 #endif
 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET		0x8000
 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET		0x9000
 #define CONFIG_SYS_MPC8xxx_DDR3_OFFSET		0xA000
 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET	0xE1000
 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET	0xE2000
 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET	0xEA000
 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET	0xEB000
 #define CONFIG_SYS_FSL_CPC_OFFSET		0x10000
 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET		0x100000
 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET		0x101000
 #define CONFIG_SYS_MPC85xx_DMA3_OFFSET		0x102000
 #define CONFIG_SYS_MPC85xx_DMA_OFFSET		CONFIG_SYS_MPC85xx_DMA1_OFFSET
 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET		0x110000
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x114000
 #define CONFIG_SYS_MPC85xx_LBC_OFFSET		0x124000
 #define CONFIG_SYS_MPC85xx_IFC_OFFSET		0x124000
 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0x130000
 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET	0x1e0000
 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
 	&& !defined(CONFIG_PPC_B4420)
 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET		0x240000
 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET		0x250000
 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET		0x260000
 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET		0x270000
 #else
 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET		0x200000
 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET		0x201000
 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET		0x202000
 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET		0x203000
 #endif
 #define CONFIG_SYS_MPC85xx_USB1_OFFSET		0x210000
 #define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x211000
 #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
 #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET		0x220000
 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET		0x221000
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x300000
 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET	0x316000
 #define CONFIG_SYS_FSL_QMAN_OFFSET		0x318000
 #define CONFIG_SYS_FSL_BMAN_OFFSET		0x31a000
 #define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET	0x320000
 #define CONFIG_SYS_FSL_FM1_OFFSET		0x400000
 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET	0x488000
 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET	0x489000
 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET	0x48a000
 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET	0x48b000
 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET	0x48c000
 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET	0x48d000
 #define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET	0x490000
 #define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET	0x491000
 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0x4e0000
 #define CONFIG_SYS_FSL_FM2_OFFSET		0x500000
 #define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET	0x588000
 #define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET	0x589000
 #define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET	0x58a000
 #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET	0x58b000
 #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET	0x58c000
 #define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET	0x58d000
 #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET	0x590000
 #define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET	0x591000
 #define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET	0xC20000
 #else
 #define CONFIG_SYS_MPC85xx_ECM_OFFSET		0x0000
 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET		0x2000
 #define CONFIG_SYS_MPC85xx_LBC_OFFSET		0x5000
 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET		0x6000
 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET		0x7000
 #define CONFIG_SYS_MPC85xx_PCI1_OFFSET		0x8000
 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET		0x8000
 #define CONFIG_SYS_MPC85xx_PCI2_OFFSET		0x9000
 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET		0x9000
 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET         0xa000
 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET         0x9000
 #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET         0x8000
 #else
 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET         0xb000
 #endif
 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0xF000
 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET		0x18000
 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET		0x19000
 #define CONFIG_SYS_MPC85xx_IFC_OFFSET		0x1e000
 #define CONFIG_SYS_MPC85xx_L2_OFFSET		0x20000
 #define CONFIG_SYS_MPC85xx_DMA_OFFSET		0x21000
 #define CONFIG_SYS_MPC85xx_USB1_OFFSET		0x22000
 #define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x23000
 #ifdef CONFIG_TSECV2
 #define CONFIG_SYS_TSEC1_OFFSET			0xB0000
 #elif defined(CONFIG_TSECV2_1)
 #define CONFIG_SYS_TSEC1_OFFSET			0x10000
 #else
 #define CONFIG_SYS_TSEC1_OFFSET			0x24000
 #endif
 #define CONFIG_SYS_MDIO1_OFFSET			0x24000
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
 #if defined(CONFIG_PPC_C29X)
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x80000
 #else
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x30000
 #endif
 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET	0xE3100
 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
 #define CONFIG_SYS_SNVS_OFFSET			0xE6000
 #define CONFIG_SYS_SFP_OFFSET			0xE7000
 #define CONFIG_SYS_MPC85xx_CPM_OFFSET		0x80000
 #define CONFIG_SYS_FSL_QMAN_OFFSET		0x88000
 #define CONFIG_SYS_FSL_BMAN_OFFSET		0x8a000
 #define CONFIG_SYS_FSL_FM1_OFFSET		0x100000
 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET	0x188000
 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET	0x189000
 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0x1e0000
 #endif
 #define CONFIG_SYS_MPC85xx_PIC_OFFSET		0x40000
 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET		0xE0000
 #define CONFIG_SYS_FSL_SRIO_OFFSET		0xC0000
 #if defined(CONFIG_BSC9132)
 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET	0x10000
 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
 	(CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
 #endif
 #define CONFIG_SYS_FSL_CPC_ADDR	\
 	(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
 #define CONFIG_SYS_FSL_QMAN_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
 #define CONFIG_SYS_FSL_BMAN_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_PME_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
 #define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
 #define CONFIG_SYS_MPC85xx_ECM_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
 #define CONFIG_SYS_FSL_DDR_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
 #define CONFIG_SYS_FSL_DDR2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
 #define CONFIG_SYS_FSL_DDR3_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
 #define CONFIG_SYS_LBC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
 #define CONFIG_SYS_IFC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
 #define CONFIG_SYS_MPC85xx_ESPI_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
 #define CONFIG_SYS_MPC85xx_PCIX_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
 #define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
 #define CONFIG_SYS_MPC85xx_GPIO_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
 #define CONFIG_SYS_MPC85xx_SATA1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
 #define CONFIG_SYS_MPC85xx_SATA2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
 #define CONFIG_SYS_MPC85xx_L2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
 #define CONFIG_SYS_MPC85xx_DMA_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
 #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
 #define CONFIG_SYS_MPC8xxx_PIC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
 #define CONFIG_SYS_MPC85xx_CPM_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
 #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
 #define CONFIG_SYS_FSL_SEC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
 #define CONFIG_SYS_FSL_FM1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
 #define CONFIG_SYS_FSL_FM2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
 #define CONFIG_SYS_FSL_SRIO_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
 #define CONFIG_SYS_PCI1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
 #define CONFIG_SYS_PCI2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
 #define CONFIG_SYS_PCIE1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
 #define CONFIG_SYS_PCIE2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
 #define CONFIG_SYS_PCIE3_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
 #define CONFIG_SYS_PCIE4_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
 #define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 #define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 struct ccsr_cluster_l2 {
 	u32 l2csr0;	/* 0x000 L2 cache control and status register 0 */
 	u32 l2csr1;	/* 0x004 L2 cache control and status register 1 */
 	u32 l2cfg0;	/* 0x008 L2 cache configuration register 0 */
 	u8  res_0c[500];/* 0x00c - 0x1ff */
 	u32 l2pir0;	/* 0x200 L2 cache partitioning ID register 0 */
 	u8  res_204[4];
 	u32 l2par0;	/* 0x208 L2 cache partitioning allocation register 0 */
 	u32 l2pwr0;	/* 0x20c L2 cache partitioning way register 0 */
 	u32 l2pir1;	/* 0x210 L2 cache partitioning ID register 1 */
 	u8  res_214[4];
 	u32 l2par1;	/* 0x218 L2 cache partitioning allocation register 1 */
 	u32 l2pwr1;	/* 0x21c L2 cache partitioning way register 1 */
 	u32 u2pir2;	/* 0x220 L2 cache partitioning ID register 2 */
 	u8  res_224[4];
 	u32 l2par2;	/* 0x228 L2 cache partitioning allocation register 2 */
 	u32 l2pwr2;	/* 0x22c L2 cache partitioning way register 2 */
 	u32 l2pir3;	/* 0x230 L2 cache partitioning ID register 3 */
 	u8  res_234[4];
 	u32 l2par3;	/* 0x238 L2 cache partitining allocation register 3 */
 	u32 l2pwr3;	/* 0x23c L2 cache partitining way register 3 */
 	u32 l2pir4;	/* 0x240 L2 cache partitioning ID register 3 */
 	u8  res244[4];
 	u32 l2par4;	/* 0x248 L2 cache partitioning allocation register 3 */
 	u32 l2pwr4;	/* 0x24c L2 cache partitioning way register 3 */
 	u32 l2pir5;	/* 0x250 L2 cache partitioning ID register 3 */
 	u8  res_254[4];
 	u32 l2par5;	/* 0x258 L2 cache partitioning allocation register 3 */
 	u32 l2pwr5;	/* 0x25c L2 cache partitioning way register 3 */
 	u32 l2pir6;	/* 0x260 L2 cache partitioning ID register 3 */
 	u8  res_264[4];
 	u32 l2par6;	/* 0x268 L2 cache partitioning allocation register 3 */
 	u32 l2pwr6;	/* 0x26c L2 cache partitioning way register 3 */
 	u32 l2pir7;	/* 0x270 L2 cache partitioning ID register 3 */
 	u8  res274[4];
 	u32 l2par7;	/* 0x278 L2 cache partitioning allocation register 3 */
 	u32 l2pwr7;	/* 0x27c L2 cache partitioning way register 3 */
 	u8  res_280[0xb80]; /* 0x280 - 0xdff */
 	u32 l2errinjhi;	/* 0xe00 L2 cache error injection mask high */
 	u32 l2errinjlo;	/* 0xe04 L2 cache error injection mask low */
 	u32 l2errinjctl;/* 0xe08 L2 cache error injection control */
 	u8  res_e0c[20];	/* 0xe0c - 0x01f */
 	u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */
 	u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */
 	u32 l2captecc;	/* 0xe28 L2 cache error capture ECC syndrome */
 	u8  res_e2c[20];	/* 0xe2c - 0xe3f */
 	u32 l2errdet;	/* 0xe40 L2 cache error detect */
 	u32 l2errdis;	/* 0xe44 L2 cache error disable */
 	u32 l2errinten;	/* 0xe48 L2 cache error interrupt enable */
 	u32 l2errattr;	/* 0xe4c L2 cache error attribute */
 	u32 l2erreaddr;	/* 0xe50 L2 cache error extended address */
 	u32 l2erraddr;	/* 0xe54 L2 cache error address */
 	u32 l2errctl;	/* 0xe58 L2 cache error control */
 };
 #define CONFIG_SYS_FSL_CLUSTER_1_L2 \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #define	CONFIG_SYS_DCSR_DCFG_OFFSET	0X20000
 struct dcsr_dcfg_regs {
 	u8  res_0[0x520];
 	u32 ecccr1;
 #define	DCSR_DCFG_ECC_DISABLE_USB1	0x00008000
 #define	DCSR_DCFG_ECC_DISABLE_USB2	0x00004000
 	u8  res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
 };
 #endif /*__IMMAP_85xx__*/

board/freescale/b4860qds/b4_rcw.cfg

Diff comments View file @ e7be182

1	#PBL preamble and RCW header	1	#PBL preamble and RCW header
2	aa55aa55 010e0100	2	aa55aa55 010e0100
3	# serdes protocol 0x2A_0x98	3	# serdes protocol 0x2A_0x98
4	140e0018 0f001218 00000000 00000000	4	140e0018 0f001218 00000000 00000000
5	54980000 9000a000 f8025000 a9000000	5	54980000 9000a000 e8104000 a9000000
6	01000000 00000000 00000000 0001b1f8	6	01000000 00000000 00000000 0001b1f8
7	00000000 14000020 00000000 00000011	7	00000000 14000020 00000000 00000011
8		8

board/freescale/bsc9131rdb/tlb.c

Diff comments View file @ e7be182

1	/*	1	/*
2	* Copyright 2011-2012 Freescale Semiconductor, Inc.	2	* Copyright 2011-2012 Freescale Semiconductor, Inc.
3	*	3	*
4	* SPDX-License-Identifier: GPL-2.0+	4	* SPDX-License-Identifier: GPL-2.0+
5	*/	5	*/
6		6
7	#include <common.h>	7	#include <common.h>
8	#include <asm/mmu.h>	8	#include <asm/mmu.h>
9		9
10	struct fsl_e_tlb_entry tlb_table[] = {	10	struct fsl_e_tlb_entry tlb_table[] = {
11	/* TLB 0 - for temp stack in cache */	11	/* TLB 0 - for temp stack in cache */
12	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,	12	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
13	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,	13	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
14	0, 0, BOOKE_PAGESZ_4K, 0),	14	0, 0, BOOKE_PAGESZ_4K, 0),
15	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,	15	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
16	CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,	16	CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
17	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,	17	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
18	0, 0, BOOKE_PAGESZ_4K, 0),	18	0, 0, BOOKE_PAGESZ_4K, 0),
19	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,	19	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
20	CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,	20	CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
21	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,	21	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
22	0, 0, BOOKE_PAGESZ_4K, 0),	22	0, 0, BOOKE_PAGESZ_4K, 0),
23	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,	23	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
24	CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,	24	CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
25	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,	25	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
26	0, 0, BOOKE_PAGESZ_4K, 0),	26	0, 0, BOOKE_PAGESZ_4K, 0),
27		27
28	/* TLB 1 */	28	/* TLB 1 */
29	/* I** - Covers boot page */	29	/* I** - Covers boot page */
30	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,	30	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
31	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,	31	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
32	0, 0, BOOKE_PAGESZ_4K, 1),	32	0, 0, BOOKE_PAGESZ_4K, 1),
33	#ifdef CONFIG_SPL_NAND_MINIMAL	33	#ifdef CONFIG_SPL_NAND_BOOT
34	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,	34	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
35	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,	35	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
36	0, 10, BOOKE_PAGESZ_4K, 1),	36	0, 10, BOOKE_PAGESZ_4K, 1),
37	#endif	37	#endif
38		38
39	/* IG* - CCSRBAR (PA) */	39	/* IG* - CCSRBAR (PA) */
40	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,	40	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
41	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,	41	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
42	0, 1, BOOKE_PAGESZ_1M, 1),	42	0, 1, BOOKE_PAGESZ_1M, 1),
43		43
44	/* CCSRBAR (DSP) */	44	/* CCSRBAR (DSP) */
45	SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,	45	SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
46	CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS,	46	CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS,
47	MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,	47	MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
48	0, 2, BOOKE_PAGESZ_1M, 1),	48	0, 2, BOOKE_PAGESZ_1M, 1),
49		49
50	#if defined(CONFIG_SYS_RAMBOOT) \|\| defined(CONFIG_SPL)	50	#if defined(CONFIG_SYS_RAMBOOT) \|\| defined(CONFIG_SPL)
51	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,	51	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
52	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,	52	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
53	0, 8, BOOKE_PAGESZ_1G, 1),	53	0, 8, BOOKE_PAGESZ_1G, 1),
54	#endif	54	#endif
55		55
56	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,	56	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
57	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,	57	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
58	0, 3, BOOKE_PAGESZ_1M, 1)	58	0, 3, BOOKE_PAGESZ_1M, 1)
59		59
60	};	60	};
61		61
62	int num_tlb_entries = ARRAY_SIZE(tlb_table);	62	int num_tlb_entries = ARRAY_SIZE(tlb_table);
63		63

board/freescale/bsc9132qds/tlb.c

Diff comments View file @ e7be182

1	/*	1	/*
2	* Copyright 2013 Freescale Semiconductor, Inc.	2	* Copyright 2013 Freescale Semiconductor, Inc.
3	*	3	*
4	* SPDX-License-Identifier: GPL-2.0+	4	* SPDX-License-Identifier: GPL-2.0+
5	*/	5	*/
6		6
7	#include <common.h>	7	#include <common.h>
8	#include <asm/mmu.h>	8	#include <asm/mmu.h>
9		9
10	struct fsl_e_tlb_entry tlb_table[] = {	10	struct fsl_e_tlb_entry tlb_table[] = {
11	/* TLB 0 - for temp stack in cache */	11	/* TLB 0 - for temp stack in cache */
12	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,	12	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
13	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,	13	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
14	0, 0, BOOKE_PAGESZ_4K, 0),	14	0, 0, BOOKE_PAGESZ_4K, 0),
15	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,	15	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
16	CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,	16	CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
17	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,	17	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
18	0, 0, BOOKE_PAGESZ_4K, 0),	18	0, 0, BOOKE_PAGESZ_4K, 0),
19	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,	19	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
20	CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,	20	CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
21	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,	21	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
22	0, 0, BOOKE_PAGESZ_4K, 0),	22	0, 0, BOOKE_PAGESZ_4K, 0),
23	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,	23	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
24	CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,	24	CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
25	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,	25	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
26	0, 0, BOOKE_PAGESZ_4K, 0),	26	0, 0, BOOKE_PAGESZ_4K, 0),
27		27
28	/* TLB 1 */	28	/* TLB 1 */
29	/* I** - Covers boot page */	29	/* I** - Covers boot page */
30	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,	30	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
31	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,	31	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
32	0, 0, BOOKE_PAGESZ_4K, 1),	32	0, 0, BOOKE_PAGESZ_4K, 1),
33	#ifdef CONFIG_SPL_NAND_MINIMAL	33	#ifdef CONFIG_SPL_NAND_BOOT
34	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,	34	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
35	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,	35	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
36	0, 10, BOOKE_PAGESZ_4K, 1),	36	0, 10, BOOKE_PAGESZ_4K, 1),
37	#endif	37	#endif
38		38
39	/* IG* - CCSRBAR (PA) */	39	/* IG* - CCSRBAR (PA) */
40	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,	40	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
41	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,	41	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
42	0, 1, BOOKE_PAGESZ_1M, 1),	42	0, 1, BOOKE_PAGESZ_1M, 1),
43		43
44	/* CCSRBAR (DSP) */	44	/* CCSRBAR (DSP) */
45	SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,	45	SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
46	CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, MAS3_SW\|MAS3_SR,	46	CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, MAS3_SW\|MAS3_SR,
47	MAS2_I\|MAS2_G, 0, 2, BOOKE_PAGESZ_1M, 1),	47	MAS2_I\|MAS2_G, 0, 2, BOOKE_PAGESZ_1M, 1),
48		48
49	#ifndef CONFIG_SPL_BUILD	49	#ifndef CONFIG_SPL_BUILD
50	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,	50	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
51	MAS3_SX\|MAS3_SR, MAS2_W\|MAS2_G,	51	MAS3_SX\|MAS3_SR, MAS2_W\|MAS2_G,
52	0, 3, BOOKE_PAGESZ_64M, 1),	52	0, 3, BOOKE_PAGESZ_64M, 1),
53		53
54	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000,	54	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000,
55	CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,	55	CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
56	MAS3_SX\|MAS3_SR, MAS2_W\|MAS2_G,	56	MAS3_SX\|MAS3_SR, MAS2_W\|MAS2_G,
57	0, 4, BOOKE_PAGESZ_64M, 1),	57	0, 4, BOOKE_PAGESZ_64M, 1),
58		58
59	#ifdef CONFIG_PCI	59	#ifdef CONFIG_PCI
60	/* IG* - PCI */	60	/* IG* - PCI */
61	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,	61	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
62	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,	62	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
63	0, 6, BOOKE_PAGESZ_256M, 1),	63	0, 6, BOOKE_PAGESZ_256M, 1),
64		64
65	/* IG* - PCI I/O */	65	/* IG* - PCI I/O */
66	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,	66	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
67	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,	67	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
68	0, 7, BOOKE_PAGESZ_64K, 1),	68	0, 7, BOOKE_PAGESZ_64K, 1),
69	#endif	69	#endif
70	#endif	70	#endif
71		71
72	#if defined(CONFIG_SYS_RAMBOOT) \|\| defined(CONFIG_SPL)	72	#if defined(CONFIG_SYS_RAMBOOT) \|\| defined(CONFIG_SPL)
73	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,	73	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
74	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,	74	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
75	0, 8, BOOKE_PAGESZ_1G, 1),	75	0, 8, BOOKE_PAGESZ_1G, 1),
76	#endif	76	#endif
77		77
78	#ifdef CONFIG_SYS_FPGA_BASE	78	#ifdef CONFIG_SYS_FPGA_BASE
79	/* IG - Board FPGA */	79	/* IG - Board FPGA */
80	SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS,	80	SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS,
81	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,	81	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
82	0, 9, BOOKE_PAGESZ_256K, 1),	82	0, 9, BOOKE_PAGESZ_256K, 1),
83	#endif	83	#endif
84		84
85	#ifdef CONFIG_SYS_NAND_BASE_PHYS	85	#ifdef CONFIG_SYS_NAND_BASE_PHYS
86	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,	86	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
87	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,	87	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
88	0, 5, BOOKE_PAGESZ_1M, 1),	88	0, 5, BOOKE_PAGESZ_1M, 1),
89	#endif	89	#endif
90	};	90	};
91		91
92	int num_tlb_entries = ARRAY_SIZE(tlb_table);	92	int num_tlb_entries = ARRAY_SIZE(tlb_table);
93		93

board/freescale/p1010rdb/tlb.c

Diff comments View file @ e7be182

1	/*	1	/*
2	* Copyright 2010-2011 Freescale Semiconductor, Inc.	2	* Copyright 2010-2011 Freescale Semiconductor, Inc.
3	*	3	*
4	* SPDX-License-Identifier: GPL-2.0+	4	* SPDX-License-Identifier: GPL-2.0+
5	*/	5	*/
6		6
7	#include <common.h>	7	#include <common.h>
8	#include <asm/mmu.h>	8	#include <asm/mmu.h>
9		9
10	struct fsl_e_tlb_entry tlb_table[] = {	10	struct fsl_e_tlb_entry tlb_table[] = {
11	/* TLB 0 - for temp stack in cache */	11	/* TLB 0 - for temp stack in cache */
12	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,	12	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
13	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,	13	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
14	0, 0, BOOKE_PAGESZ_4K, 0),	14	0, 0, BOOKE_PAGESZ_4K, 0),
15	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,	15	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
16	CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,	16	CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
17	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,	17	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
18	0, 0, BOOKE_PAGESZ_4K, 0),	18	0, 0, BOOKE_PAGESZ_4K, 0),
19	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,	19	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
20	CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,	20	CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
21	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,	21	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
22	0, 0, BOOKE_PAGESZ_4K, 0),	22	0, 0, BOOKE_PAGESZ_4K, 0),
23	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,	23	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
24	CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,	24	CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
25	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,	25	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
26	0, 0, BOOKE_PAGESZ_4K, 0),	26	0, 0, BOOKE_PAGESZ_4K, 0),
27		27
28	/* TLB 1 */	28	/* TLB 1 */
29	/* I** - Covers boot page */	29	/* I** - Covers boot page */
30	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,	30	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
31	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,	31	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
32	0, 0, BOOKE_PAGESZ_4K, 1),	32	0, 0, BOOKE_PAGESZ_4K, 1),
33	#ifdef CONFIG_SPL_NAND_MINIMAL	33	#ifdef CONFIG_SPL_NAND_BOOT
34	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,	34	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
35	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,	35	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
36	0, 10, BOOKE_PAGESZ_4K, 1),	36	0, 10, BOOKE_PAGESZ_4K, 1),
37	#endif	37	#endif
38		38
39	/* IG* - CCSRBAR */	39	/* IG* - CCSRBAR */
40	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,	40	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
41	MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,	41	MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
42	0, 1, BOOKE_PAGESZ_1M, 1),	42	0, 1, BOOKE_PAGESZ_1M, 1),
43		43
44	#ifndef CONFIG_SPL_BUILD	44	#ifndef CONFIG_SPL_BUILD
45	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,	45	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
46	MAS3_SX\|MAS3_SR, MAS2_W\|MAS2_G,	46	MAS3_SX\|MAS3_SR, MAS2_W\|MAS2_G,
47	0, 2, BOOKE_PAGESZ_16M, 1),	47	0, 2, BOOKE_PAGESZ_16M, 1),
48		48
49	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,	49	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
50	CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,	50	CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
51	MAS3_SX\|MAS3_SR, MAS2_W\|MAS2_G,	51	MAS3_SX\|MAS3_SR, MAS2_W\|MAS2_G,
52	0, 3, BOOKE_PAGESZ_16M, 1),	52	0, 3, BOOKE_PAGESZ_16M, 1),
53		53
54	#ifdef CONFIG_PCI	54	#ifdef CONFIG_PCI
55	/* IG* - PCI */	55	/* IG* - PCI */
56	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,	56	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
57	MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,	57	MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
58	0, 4, BOOKE_PAGESZ_1G, 1),	58	0, 4, BOOKE_PAGESZ_1G, 1),
59		59
60	/* IG* - PCI I/O */	60	/* IG* - PCI I/O */
61	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,	61	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
62	MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,	62	MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
63	0, 5, BOOKE_PAGESZ_256K, 1),	63	0, 5, BOOKE_PAGESZ_256K, 1),
64	#endif	64	#endif
65	#endif	65	#endif
66		66
67	/* IG - Board CPLD */	67	/* IG - Board CPLD */
68	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,	68	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
69	MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,	69	MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
70	0, 6, BOOKE_PAGESZ_256K, 1),	70	0, 6, BOOKE_PAGESZ_256K, 1),
71		71
72	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,	72	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
73	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,	73	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
74	0, 7, BOOKE_PAGESZ_1M, 1),	74	0, 7, BOOKE_PAGESZ_1M, 1),
75		75
76	#if defined(CONFIG_SYS_RAMBOOT) \|\| defined(CONFIG_SPL)	76	#if defined(CONFIG_SYS_RAMBOOT) \|\| defined(CONFIG_SPL)
77	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,	77	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
78	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,	78	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
79	0, 8, BOOKE_PAGESZ_1G, 1)	79	0, 8, BOOKE_PAGESZ_1G, 1)
80	#endif	80	#endif
81	};	81	};
82		82
83	int num_tlb_entries = ARRAY_SIZE(tlb_table);	83	int num_tlb_entries = ARRAY_SIZE(tlb_table);
84		84

board/freescale/t1040qds/t1040_pbi.cfg

Diff comments View file @ e7be182

1	#PBI commands	1	#PBI commands
2	#Initialize CPC1	2	#Initialize CPC1
3	09010000 00200400	3	09010000 00200400
4	09138000 00000000	4	09138000 00000000
5	091380c0 00000100	5	091380c0 00000100
6	#Configure CPC1 as 512KB SRAM	6	#Configure CPC1 as 256KB SRAM
7	09010100 00000000	7	09010100 00000000
8	09010104 fffc0007	8	09010104 fffc0007
9	09010f00 08000000	9	09010f00 08000000
10	09010000 80000000	10	09010000 80000000
11	#Configure LAW for CPC1	11	#Configure LAW for CPC1
12	09000cf0 00000000	12	09000cf0 00000000
13	09000cf4 fffc0000	13	09000cf4 fffc0000
14	09000cf8 81000011	14	09000cf8 81000011
15	#Configure alternate space	15	#Configure alternate space
16	09000010 00000000	16	09000010 00000000
17	09000014 ff000000	17	09000014 ff000000
18	09000018 81000000	18	09000018 81000000
19	#Configure SPI controller	19	#Configure SPI controller
20	09110000 80000403	20	09110000 80000403
21	09110020 2d170008	21	09110020 2d170008
22	09110024 00100008	22	09110024 00100008
23	09110028 00100008	23	09110028 00100008
24	0911002c 00100008	24	0911002c 00100008
25	#Flush PBL data	25	#Flush PBL data
26	09138000 00000000	26	09138000 00000000
27	091380c0 00000000	27	091380c0 00000000
28		28

board/freescale/t1040qds/t1040qds.c

Diff comments View file @ e7be182

 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <command.h>
 #include <i2c.h>
 #include <netdev.h>
 #include <linux/compiler.h>
 #include <asm/mmu.h>
 #include <asm/processor.h>
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
 #include <fm_eth.h>
 #include "../common/qixis.h"
 #include "t1040qds.h"
 #include "t1040qds_qixis.h"
 DECLARE_GLOBAL_DATA_PTR;
 int checkboard(void)
 {
 	char buf[64];
 	u8 sw;
 	struct cpu_type *cpu = gd->arch.cpu;
 	static const char *const freq[] = {"100", "125", "156.25", "161.13",
 						"122.88", "122.88", "122.88"};
 	int clock;
 	printf("Board: %sQDS, ", cpu->name);
 	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
 	       QIXIS_READ(id), QIXIS_READ(arch));
 	sw = QIXIS_READ(brdcfg[0]);
 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 	if (sw < 0x8)
 		printf("vBank: %d\n", sw);
 	else if (sw == 0x8)
 		puts("PromJet\n");
 	else if (sw == 0x9)
 		puts("NAND\n");
 	else if (sw == 0x15)
 		printf("IFCCard\n");
 	else
 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 	printf("FPGA: v%d (%s), build %d",
 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
 	       (int)qixis_read_minor());
 	/* the timestamp string contains "\n" at the end */
 	printf(" on %s", qixis_read_time(buf));
 	/*
 	 * Display the actual SERDES reference clocks as configured by the
 	 * dip switches on the board.  Note that the SWx registers could
 	 * technically be set to force the reference clocks to match the
 	 * values that the SERDES expects (or vice versa).  For now, however,
 	 * we just display both values and hope the user notices when they
 	 * don't match.
 	 */
 	puts("SERDES Reference: ");
 	sw = QIXIS_READ(brdcfg[2]);
 	clock = (sw >> 6) & 3;
 	printf("Clock1=%sMHz ", freq[clock]);
 	clock = (sw >> 4) & 3;
 	printf("Clock2=%sMHz\n", freq[clock]);
 	return 0;
 }
 int select_i2c_ch_pca9547(u8 ch)
 {
 	int ret;
 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 	if (ret) {
 		puts("PCA: failed to select proper channel\n");
 		return ret;
 	}
 	return 0;
 }
 int board_early_init_r(void)
 {
 #ifdef CONFIG_SYS_FLASH_BASE
 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
 	/*
 	 * Remap Boot flash + PROMJET region to caching-inhibited
 	 * so that flash can be erased properly.
 	 */
 	/* Flush d-cache and invalidate i-cache of any FLASH data */
 	flush_dcache();
 	invalidate_icache();
 	/* invalidate existing TLB entry for flash + promjet */
 	disable_tlb(flash_esel);
 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
 #endif
 	set_liodns();
 #ifdef CONFIG_SYS_DPAA_QBMAN
 	setup_portals();
 #endif
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 	return 0;
 }
 unsigned long get_board_sys_clk(void)
 {
 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 	switch (sysclk_conf & 0x0F) {
 	case QIXIS_SYSCLK_64:
 		return 64000000;
 	case QIXIS_SYSCLK_83:
 		return 83333333;
 	case QIXIS_SYSCLK_100:
 		return 100000000;
 	case QIXIS_SYSCLK_125:
 		return 125000000;
 	case QIXIS_SYSCLK_133:
 		return 133333333;
 	case QIXIS_SYSCLK_150:
 		return 150000000;
 	case QIXIS_SYSCLK_160:
 		return 160000000;
 	case QIXIS_SYSCLK_166:
 		return 166666666;
 	}
 	return 66666666;
 }
 unsigned long get_board_ddr_clk(void)
 {
 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 	switch ((ddrclk_conf & 0x30) >> 4) {
 	case QIXIS_DDRCLK_100:
 		return 100000000;
 	case QIXIS_DDRCLK_125:
 		return 125000000;
 	case QIXIS_DDRCLK_133:
 		return 133333333;
 	}
 	return 66666666;
 }
 #define NUM_SRDS_BANKS	2
 int misc_init_r(void)
 {
 	u8 sw;
 	serdes_corenet_t *srds_regs =
 		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 	u32 actual[NUM_SRDS_BANKS] = { 0 };
 	int i;
 	sw = QIXIS_READ(brdcfg[2]);
 	for (i = 0; i < NUM_SRDS_BANKS; i++) {
 		unsigned int clock = (sw >> (6 - 2 * i)) & 3;
 		switch (clock) {
 		case 0:
 			actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
 			break;
 		case 1:
 			actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
 			break;
 		case 2:
 			actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
 			break;
 		}
 	}
 	puts("SerDes1");
 	for (i = 0; i < NUM_SRDS_BANKS; i++) {
 		u32 pllcr0 = srds_regs->bank[i].pllcr0;
 		u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
 		if (expected != actual[i]) {
 			printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
 			       i + 1, serdes_clock_to_string(expected),
 			       serdes_clock_to_string(actual[i]));
 		}
 	}
 	return 0;
 }
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	phys_addr_t base;
 	phys_size_t size;
 	ft_cpu_setup(blob, bd);
 	base = getenv_bootm_low();
 	size = getenv_bootm_size();
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 #ifdef CONFIG_PCI
 	pci_of_setup(blob, bd);
 #endif
 	fdt_fixup_liodn(blob);
 #ifdef CONFIG_HAS_FSL_DR_USB
 	fdt_fixup_dr_usb(blob, bd);
 #endif
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_ethernet(blob);
 #endif
 }
 void qixis_dump_switch(void)
 {
 	int i, nr_of_cfgsw;
 	QIXIS_WRITE(cms[0], 0x00);
 	nr_of_cfgsw = QIXIS_READ(cms[1]);
 	puts("DIP switch settings dump:\n");
 	for (i = 1; i <= nr_of_cfgsw; i++) {
 		QIXIS_WRITE(cms[0], i);
 		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 	}
 }
+int board_need_mem_reset(void)
+{
+	return 1;
+}

boards.cfg

Diff comments View file @ e7be182

 #
 # List of boards
 #
 # Syntax:
 #	white-space separated list of entries;
 #	each entry has the fields documented below.
 #
 #	Unused fields can be specified as "-", or omitted if they
 #	are the last field on the line.
 #
 #	Lines starting with '#' are comments.
 #	Blank lines are ignored.
 #
 #	The CPU field takes the form:
 #		cpu[:spl_cpu]
 #	If spl_cpu is specified the make variable CPU will be set to this
 #	during the SPL build.
 #
 #	The options field takes the form:
 #		<board config name>[:comma separated config options]
 #	Each config option has the form (value defaults to "1"):
 #		option[=value]
 #	So if you have:
 #		FOO:HAS_BAR,BAZ=64
 #	The file include/configs/FOO.h will be used, and these defines created:
 #		#define CONFIG_HAS_BAR	1
 #		#define CONFIG_BAZ	64
 #
 #       The maintainers field lists the e-mail addresses of the board's
 #       maintainers, separated by colons. NOTE: there are spaces in this field!
 #       For any board without permanent maintainer, please contact
 #           Wolfgang Denk <wd@denx.de>
 #       And Cc: the <u-boot@lists.denx.de> mailing list.
 # The list should be ordered according to the C locale.
 #
 # To keep the list formatted and sorted, script tools/reformat.py is available.
 # It can be used from a shell:
 #	tools/reformat.py -i -d '-' -s 8 <boards.cfg >boards0.cfg && mv boards0.cfg boards.cfg
 # It can directly be invoked from vim:
 #	:%!tools/reformat.py -i -d '-' -s 8
 #
 # Status, Arch, CPU:SPLCPU, SoC, Vendor, Board name, Target, Options, Maintainers
 ###########################################################################################################
 Active  arm         arm1136        -           armltd          integrator          integratorcp_cm1136                  integratorcp:CM1136                                                                                                               Linus Walleij <linus.walleij@linaro.org>
 Active  arm         arm1136        mx31        -               -                   imx31_phycore                        -                                                                                                                                 -
 Active  arm         arm1136        mx31        davedenx        -                   qong                                 -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  arm         arm1136        mx31        freescale       -                   mx31pdk                              -                                                                                                                                 Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         arm1136        mx31        hale            -                   tt01                                 -                                                                                                                                 Helmut Raiger <helmut.raiger@hale.at>
 Active  arm         arm1136        mx31        logicpd         -                   imx31_litekit                        -                                                                                                                                 -
 Active  arm         arm1136        mx35        -               -                   woodburn                             -                                                                                                                                 Stefano Babic <sbabic@denx.de>
 Active  arm         arm1136        mx35        -               woodburn            woodburn_sd                          woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg                                                                                -
 Active  arm         arm1136        mx35        CarMediaLab     -                   flea3                                -                                                                                                                                 Stefano Babic <sbabic@denx.de>
 Active  arm         arm1136        mx35        freescale       -                   mx35pdk                              -                                                                                                                                 Stefano Babic <sbabic@denx.de>
 Active  arm         arm1176        bcm2835     raspberrypi     rpi_b               rpi_b                                -                                                                                                                                 Stephen Warren <swarren@wwwdotorg.org>
 Active  arm         arm1176        tnetv107x   ti              tnetv107xevm        tnetv107x_evm                        -                                                                                                                                 Chan-Taek Park <c-park@ti.com>
 Active  arm         arm720t        -           armltd          integrator          integratorap_cm720t                  integratorap:CM720T                                                                                                               Linus Walleij <linus.walleij@linaro.org>
 Active  arm         arm920t        -           armltd          integrator          integratorap_cm920t                  integratorap:CM920T                                                                                                               Linus Walleij <linus.walleij@linaro.org>
 Active  arm         arm920t        -           armltd          integrator          integratorcp_cm920t                  integratorcp:CM920T                                                                                                               Linus Walleij <linus.walleij@linaro.org>
 Active  arm         arm920t        a320        faraday         -                   a320evb                              -                                                                                                                                 Po-Yu Chuang <ratbert@faraday-tech.com>
 Active  arm         arm920t        at91        atmel           at91rm9200ek        at91rm9200ek                         at91rm9200ek                                                                                                                      Andreas Bießmann <andreas.devel@gmail.com>
 Active  arm         arm920t        at91        atmel           at91rm9200ek        at91rm9200ek_ram                     at91rm9200ek:RAMBOOT                                                                                                              Andreas Bießmann <andreas.devel@gmail.com>
 Active  arm         arm920t        at91        BuS             eb_cpux9k2          eb_cpux9k2                           eb_cpux9k2                                                                                                                        Jens Scharsig <esw@bus-elektronik.de>
 Active  arm         arm920t        at91        BuS             eb_cpux9k2          eb_cpux9k2_ram                       eb_cpux9k2:RAMBOOT                                                                                                                Jens Scharsig <esw@bus-elektronik.de>
 Active  arm         arm920t        at91        eukrea          cpuat91             cpuat91                              cpuat91                                                                                                                           Eric Benard <eric@eukrea.com>
 Active  arm         arm920t        at91        eukrea          cpuat91             cpuat91_ram                          cpuat91:RAMBOOT                                                                                                                   Eric Benard <eric@eukrea.com>
 Active  arm         arm920t        imx         -               -                   mx1ads                               -                                                                                                                                 -
 Active  arm         arm920t        imx         -               -                   scb9328                              -                                                                                                                                 Torsten Koschorrek <koschorrek@synertronixx.de>
 Active  arm         arm920t        ks8695      -               -                   cm4008                               -                                                                                                                                 Greg Ungerer <greg.ungerer@opengear.com>
 Active  arm         arm920t        ks8695      -               -                   cm41xx                               -                                                                                                                                 -
 Active  arm         arm920t        s3c24x0     friendlyarm     mini2440            mini2440                             -                                                                                                                                 Gabriel Huau <contact@huau-gabriel.fr>
 Active  arm         arm920t        s3c24x0     mpl             vcma9               VCMA9                                -                                                                                                                                 David Müller <d.mueller@elsoft.ch>
 Active  arm         arm920t        s3c24x0     samsung         -                   smdk2410                             -                                                                                                                                 David Müller <d.mueller@elsoft.ch>
 Active  arm         arm926ejs      -           armltd          integrator          integratorap_cm926ejs                integratorap:CM926EJ_S                                                                                                            Linus Walleij <linus.walleij@linaro.org>
 Active  arm         arm926ejs      -           armltd          integrator          integratorcp_cm926ejs                integratorcp:CM924EJ_S                                                                                                            Linus Walleij <linus.walleij@linaro.org>
 Active  arm         arm926ejs      armada100   Marvell         -                   aspenite                             -                                                                                                                                 Prafulla Wadaskar <prafulla@marvell.com>
 Active  arm         arm926ejs      armada100   Marvell         -                   gplugd                               -                                                                                                                                 Ajay Bhargav <ajay.bhargav@einfochips.com>
 Active  arm         arm926ejs      at91        -               -                   afeb9260                             -                                                                                                                                 Sergey Lapin <slapin@ossfans.org>
 Active  arm         arm926ejs      at91        atmel           at91sam9260ek       at91sam9260ek_dataflash_cs0          at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0                                                                                   Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9260ek       at91sam9260ek_dataflash_cs1          at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1                                                                                   Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9260ek       at91sam9260ek_nandflash              at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH                                                                                       Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9260ek       at91sam9g20ek_2mmc_nandflash         at91sam9260ek:AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH                                                                    Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9260ek       at91sam9g20ek_dataflash_cs0          at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS0                                                                                   Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9260ek       at91sam9g20ek_dataflash_cs1          at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS1                                                                                   Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9260ek       at91sam9g20ek_mmc                    at91sam9260ek:AT91SAM9G20,SYS_USE_MMC                                                                                             Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9260ek       at91sam9g20ek_nandflash              at91sam9260ek:AT91SAM9G20,SYS_USE_NANDFLASH                                                                                       Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9260ek       at91sam9xeek_dataflash_cs0           at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0                                                                                    Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9260ek       at91sam9xeek_dataflash_cs1           at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1                                                                                    Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9260ek       at91sam9xeek_nandflash               at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH                                                                                        Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9261ek       at91sam9261ek_dataflash_cs0          at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS0                                                                                   Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9261ek       at91sam9261ek_dataflash_cs3          at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS3                                                                                   Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9261ek       at91sam9261ek_nandflash              at91sam9261ek:AT91SAM9261,SYS_USE_NANDFLASH                                                                                       Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9261ek       at91sam9g10ek_dataflash_cs0          at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS0                                                                                   Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9261ek       at91sam9g10ek_dataflash_cs3          at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS3                                                                                   Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9261ek       at91sam9g10ek_nandflash              at91sam9261ek:AT91SAM9G10,SYS_USE_NANDFLASH                                                                                       Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9263ek       at91sam9263ek_dataflash              at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH                                                                                       Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9263ek       at91sam9263ek_dataflash_cs0          at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH                                                                                       Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9263ek       at91sam9263ek_nandflash              at91sam9263ek:AT91SAM9263,SYS_USE_NANDFLASH                                                                                       Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9263ek       at91sam9263ek_norflash               at91sam9263ek:AT91SAM9263,SYS_USE_NORFLASH                                                                                        Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9263ek       at91sam9263ek_norflash_boot          at91sam9263ek:AT91SAM9263,SYS_USE_BOOT_NORFLASH                                                                                   Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9m10g45ek    at91sam9m10g45ek_nandflash           at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH                                                                                 Bo Shen<voice.shen@atmel.com>
 Active  arm         arm926ejs      at91        atmel           at91sam9n12ek       at91sam9n12ek_mmc                    at91sam9n12ek:AT91SAM9N12,SYS_USE_MMC                                                                                             Josh Wu <josh.wu@atmel.com>
 Active  arm         arm926ejs      at91        atmel           at91sam9n12ek       at91sam9n12ek_nandflash              at91sam9n12ek:AT91SAM9N12,SYS_USE_NANDFLASH                                                                                       Josh Wu <josh.wu@atmel.com>
 Active  arm         arm926ejs      at91        atmel           at91sam9n12ek       at91sam9n12ek_spiflash               at91sam9n12ek:AT91SAM9N12,SYS_USE_SPIFLASH                                                                                        Josh Wu <josh.wu@atmel.com>
 Active  arm         arm926ejs      at91        atmel           at91sam9rlek        at91sam9rlek_dataflash               at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH                                                                                         Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9rlek        at91sam9rlek_nandflash               at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH                                                                                         Stelian Pop <stelian@popies.net>
 Active  arm         arm926ejs      at91        atmel           at91sam9x5ek        at91sam9x5ek_dataflash               at91sam9x5ek:AT91SAM9X5,SYS_USE_DATAFLASH                                                                                         Bo Shen <voice.shen@atmel.com>
 Active  arm         arm926ejs      at91        atmel           at91sam9x5ek        at91sam9x5ek_mmc                     at91sam9x5ek:AT91SAM9X5,SYS_USE_MMC                                                                                               Bo Shen <voice.shen@atmel.com>
 Active  arm         arm926ejs      at91        atmel           at91sam9x5ek        at91sam9x5ek_nandflash               at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH                                                                                         Bo Shen <voice.shen@atmel.com>
 Active  arm         arm926ejs      at91        atmel           at91sam9x5ek        at91sam9x5ek_spiflash                at91sam9x5ek:AT91SAM9X5,SYS_USE_SPIFLASH                                                                                          Bo Shen <voice.shen@atmel.com>
 Active  arm         arm926ejs      at91        bluewater       -                   snapper9260                          snapper9260:AT91SAM9260                                                                                                           Ryan Mallon <ryan@bluewatersys.com>
 Active  arm         arm926ejs      at91        bluewater       snapper9260         snapper9g20                          snapper9260:AT91SAM9G20                                                                                                           Ryan Mallon <ryan@bluewatersys.com>
 Active  arm         arm926ejs      at91        BuS             vl_ma2sc            vl_ma2sc                             -                                                                                                                                 Jens Scharsig <esw@bus-elektronik.de>
 Active  arm         arm926ejs      at91        BuS             vl_ma2sc            vl_ma2sc_ram                         vl_ma2sc:RAMLOAD                                                                                                                  Jens Scharsig <esw@bus-elektronik.de>
 Active  arm         arm926ejs      at91        calao           sbc35_a9g20         sbc35_a9g20_eeprom                   sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM                                                                                            Albin Tonnerre <albin.tonnerre@free-electrons.com>
 Active  arm         arm926ejs      at91        calao           sbc35_a9g20         sbc35_a9g20_nandflash                sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH                                                                                         Albin Tonnerre <albin.tonnerre@free-electrons.com>
 Active  arm         arm926ejs      at91        calao           tny_a9260           tny_a9260_eeprom                     tny_a9260:AT91SAM9260,SYS_USE_EEPROM                                                                                              Albin Tonnerre <albin.tonnerre@free-electrons.com>
 Active  arm         arm926ejs      at91        calao           tny_a9260           tny_a9260_nandflash                  tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH                                                                                           Albin Tonnerre <albin.tonnerre@free-electrons.com>
 Active  arm         arm926ejs      at91        calao           tny_a9260           tny_a9g20_eeprom                     tny_a9260:AT91SAM9G20,SYS_USE_EEPROM                                                                                              Albin Tonnerre <albin.tonnerre@free-electrons.com>
 Active  arm         arm926ejs      at91        calao           tny_a9260           tny_a9g20_nandflash                  tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH                                                                                           Albin Tonnerre <albin.tonnerre@free-electrons.com>
 Active  arm         arm926ejs      at91        calao           usb_a9263           usb_a9263_dataflash                  usb_a9263:AT91SAM9263,SYS_USE_DATAFLASH                                                                                           Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
 Active  arm         arm926ejs      at91        egnite          ethernut5           ethernut5                            ethernut5:AT91SAM9XE                                                                                                              egnite GmbH <info@egnite.de>
 Active  arm         arm926ejs      at91        emk             top9000             top9000eval_xe                       top9000:EVAL9000                                                                                                                  Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
 Active  arm         arm926ejs      at91        emk             top9000             top9000su_xe                         top9000:SU9000                                                                                                                    Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
 Active  arm         arm926ejs      at91        esd             meesc               meesc                                meesc:AT91SAM9263,SYS_USE_NANDFLASH                                                                                               Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
 Active  arm         arm926ejs      at91        esd             meesc               meesc_dataflash                      meesc:AT91SAM9263,SYS_USE_DATAFLASH                                                                                               Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
 Active  arm         arm926ejs      at91        esd             otc570              otc570                               otc570:AT91SAM9263,SYS_USE_NANDFLASH                                                                                              Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
 Active  arm         arm926ejs      at91        esd             otc570              otc570_dataflash                     otc570:AT91SAM9263,SYS_USE_DATAFLASH                                                                                              Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
 Active  arm         arm926ejs      at91        eukrea          cpu9260             cpu9260                              cpu9260:CPU9260                                                                                                                   Eric Benard <eric@eukrea.com>
 Active  arm         arm926ejs      at91        eukrea          cpu9260             cpu9260_128M                         cpu9260:CPU9260,CPU9260_128M                                                                                                      Eric Benard <eric@eukrea.com>
 Active  arm         arm926ejs      at91        eukrea          cpu9260             cpu9260_nand                         cpu9260:CPU9260,NANDBOOT                                                                                                          Eric Benard <eric@eukrea.com>
 Active  arm         arm926ejs      at91        eukrea          cpu9260             cpu9260_nand_128M                    cpu9260:CPU9260,CPU9260_128M,NANDBOOT                                                                                             Eric Benard <eric@eukrea.com>
 Active  arm         arm926ejs      at91        eukrea          cpu9260             cpu9G20                              cpu9260:CPU9G20                                                                                                                   Eric Benard <eric@eukrea.com>
 Active  arm         arm926ejs      at91        eukrea          cpu9260             cpu9G20_128M                         cpu9260:CPU9G20,CPU9G20_128M                                                                                                      Eric Benard <eric@eukrea.com>
 Active  arm         arm926ejs      at91        eukrea          cpu9260             cpu9G20_nand                         cpu9260:CPU9G20,NANDBOOT                                                                                                          Eric Benard <eric@eukrea.com>
 Active  arm         arm926ejs      at91        eukrea          cpu9260             cpu9G20_nand_128M                    cpu9260:CPU9G20,CPU9G20_128M,NANDBOOT                                                                                             Eric Benard <eric@eukrea.com>
 Active  arm         arm926ejs      at91        ronetix         pm9261              pm9261                               pm9261:AT91SAM9261                                                                                                                Ilko Iliev <iliev@ronetix.at>
 Active  arm         arm926ejs      at91        ronetix         pm9263              pm9263                               pm9263:AT91SAM9263                                                                                                                Ilko Iliev <iliev@ronetix.at>
 Active  arm         arm926ejs      at91        ronetix         pm9g45              pm9g45                               pm9g45:AT91SAM9G45                                                                                                                Ilko Iliev <iliev@ronetix.at>
 Active  arm         arm926ejs      at91        taskit          stamp9g20           portuxg20                            stamp9g20:AT91SAM9G20,PORTUXG20                                                                                                   Markus Hubig <mhubig@imko.de>
 Active  arm         arm926ejs      at91        taskit          stamp9g20           stamp9g20                            stamp9g20:AT91SAM9G20                                                                                                             Markus Hubig <mhubig@imko.de>
 Active  arm         arm926ejs      at91        siemens         taurus              axm                                  taurus:AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM                                                                                       Heiko Schocher <hs@denx.de>
 Active  arm         arm926ejs      at91        siemens         corvus              corvus                               corvus:AT91SAM9M10G45,SYS_USE_NANDFLASH                                                                                           Heiko Schocher <hs@denx.de>
 Active  arm         arm926ejs      at91        siemens         taurus              taurus                               taurus:AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS                                                                                    Heiko Schocher <hs@denx.de>
 Active  arm         arm926ejs      davinci     ait             cam_enc_4xx         cam_enc_4xx                          cam_enc_4xx                                                                                                                       Heiko Schocher <hs@denx.de>
 Active  arm         arm926ejs      davinci     Barix           ipam390             ipam390                              -                                                                                                                                 Heiko Schocher <hs@denx.de>
 Active  arm         arm926ejs      davinci     davinci         da8xxevm            da830evm                             -                                                                                                                                 Nick Thompson <nick.thompson@gefanuc.com>
 Active  arm         arm926ejs      davinci     davinci         da8xxevm            da850_am18xxevm                      da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50                                    Sudhakar Rajashekhara <sudhakar.raj@ti.com>
 Active  arm         arm926ejs      davinci     davinci         da8xxevm            da850evm                             da850evm:MAC_ADDR_IN_SPIFLASH                                                                                                     Sudhakar Rajashekhara <sudhakar.raj@ti.com>
 Active  arm         arm926ejs      davinci     davinci         da8xxevm            da850evm_direct_nor                  da850evm:MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT                                                                             Sudhakar Rajashekhara <sudhakar.raj@ti.com>
 Active  arm         arm926ejs      davinci     davinci         da8xxevm            hawkboard                            -                                                                                                                                 Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
 Active  arm         arm926ejs      davinci     davinci         da8xxevm            hawkboard_uart                       hawkboard:UART_U_BOOT                                                                                                             Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
 Active  arm         arm926ejs      davinci     davinci         dm355evm            davinci_dm355evm                     -                                                                                                                                 Sandeep Paulraj <s-paulraj@ti.com>
 Active  arm         arm926ejs      davinci     davinci         dm355leopard        davinci_dm355leopard                 -                                                                                                                                 Sandeep Paulraj <s-paulraj@ti.com>
 Active  arm         arm926ejs      davinci     davinci         dm365evm            davinci_dm365evm                     -                                                                                                                                 Sandeep Paulraj <s-paulraj@ti.com>
 Active  arm         arm926ejs      davinci     davinci         dm6467evm           davinci_dm6467evm                    davinci_dm6467evm:REFCLK_FREQ=27000000                                                                                            Sandeep Paulraj <s-paulraj@ti.com>
 Active  arm         arm926ejs      davinci     davinci         dm6467evm           davinci_dm6467Tevm                   davinci_dm6467evm:DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000                                                                         Sandeep Paulraj <s-paulraj@ti.com>
 Active  arm         arm926ejs      davinci     davinci         dvevm               davinci_dvevm                        -                                                                                                                                 -
 Active  arm         arm926ejs      davinci     davinci         ea20                ea20                                 -                                                                                                                                 Stefano Babic <sbabic@denx.de>
 Active  arm         arm926ejs      davinci     davinci         schmoogie           davinci_schmoogie                    -                                                                                                                                 -
 Active  arm         arm926ejs      davinci     davinci         sffsdr              davinci_sffsdr                       -                                                                                                                                 -
 Active  arm         arm926ejs      davinci     davinci         sonata              davinci_sonata                       -                                                                                                                                 -
 Active  arm         arm926ejs      davinci     enbw            enbw_cmc            enbw_cmc                             -                                                                                                                                 Heiko Schocher <hs@denx.de>
 Active  arm         arm926ejs      davinci     omicron         calimain            calimain                             -                                                                                                                                 Manfred Rudigier <manfred.rudigier@omicron.at>:Christian Riesch <christian.riesch@omicron.at>
 Active  arm         arm926ejs      kirkwood    buffalo         lsxl                lschlv2                              lsxl:LSCHLV2                                                                                                                      Michael Walle <michael@walle.cc>
 Active  arm         arm926ejs      kirkwood    buffalo         lsxl                lsxhl                                lsxl:LSXHL                                                                                                                        Michael Walle <michael@walle.cc>
 Active  arm         arm926ejs      kirkwood    cloudengines    -                   pogo_e02                             -                                                                                                                                 Dave Purdy <david.c.purdy@gmail.com>
 Active  arm         arm926ejs      kirkwood    d-link          -                   dns325                               -                                                                                                                                 Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
 Active  arm         arm926ejs      kirkwood    iomega          -                   iconnect                             -                                                                                                                                 Luka Perkov <luka@openwrt.org>
 Active  arm         arm926ejs      kirkwood    karo            tk71                tk71                                 -                                                                                                                                 -
 Active  arm         arm926ejs      kirkwood    keymile         km_arm              km_kirkwood                          km_kirkwood:KM_KIRKWOOD                                                                                                           Valentin Longchamp <valentin.longchamp@keymile.com>
 Active  arm         arm926ejs      kirkwood    keymile         km_arm              km_kirkwood_pci                      km_kirkwood:KM_KIRKWOOD_PCI                                                                                                       Valentin Longchamp <valentin.longchamp@keymile.com>
 Active  arm         arm926ejs      kirkwood    keymile         km_arm              kmcoge5un                            km_kirkwood:KM_COGE5UN                                                                                                            Valentin Longchamp <valentin.longchamp@keymile.com>
 Active  arm         arm926ejs      kirkwood    keymile         km_arm              kmnusa                               km_kirkwood:KM_NUSA                                                                                                               Valentin Longchamp <valentin.longchamp@keymile.com>
 Active  arm         arm926ejs      kirkwood    keymile         km_arm              kmsuv31                              km_kirkwood:KM_SUV31                                                                                                              Valentin Longchamp <valentin.longchamp@keymile.com>
 Active  arm         arm926ejs      kirkwood    keymile         km_arm              mgcoge3un                            km_kirkwood:KM_MGCOGE3UN                                                                                                          Valentin Longchamp <valentin.longchamp@keymile.com>
 Active  arm         arm926ejs      kirkwood    keymile         km_arm              portl2                               km_kirkwood:KM_PORTL2                                                                                                             Valentin Longchamp <valentin.longchamp@keymile.com>
 Active  arm         arm926ejs      kirkwood    LaCie           net2big_v2          d2net_v2                             lacie_kw:D2NET_V2                                                                                                                 -
 Active  arm         arm926ejs      kirkwood    LaCie           net2big_v2          net2big_v2                           lacie_kw:NET2BIG_V2                                                                                                               Simon Guinot <simon.guinot@sequanux.org>
 Active  arm         arm926ejs      kirkwood    LaCie           netspace_v2         inetspace_v2                         lacie_kw:INETSPACE_V2                                                                                                             Simon Guinot <simon.guinot@sequanux.org>
 Active  arm         arm926ejs      kirkwood    LaCie           netspace_v2         netspace_lite_v2                     lacie_kw:NETSPACE_LITE_V2                                                                                                         -
 Active  arm         arm926ejs      kirkwood    LaCie           netspace_v2         netspace_max_v2                      lacie_kw:NETSPACE_MAX_V2                                                                                                          Simon Guinot <simon.guinot@sequanux.org>
 Active  arm         arm926ejs      kirkwood    LaCie           netspace_v2         netspace_mini_v2                     lacie_kw:NETSPACE_MINI_V2                                                                                                         -
 Active  arm         arm926ejs      kirkwood    LaCie           netspace_v2         netspace_v2                          lacie_kw:NETSPACE_V2                                                                                                              Simon Guinot <simon.guinot@sequanux.org>
 Active  arm         arm926ejs      kirkwood    LaCie           wireless_space      wireless_space                       -                                                                                                                                 -
 Active  arm         arm926ejs      kirkwood    Marvell         -                   dreamplug                            -                                                                                                                                 Jason Cooper <u-boot@lakedaemon.net>
 Active  arm         arm926ejs      kirkwood    Marvell         -                   guruplug                             -                                                                                                                                 Siddarth Gore <gores@marvell.com>
 Active  arm         arm926ejs      kirkwood    Marvell         -                   mv88f6281gtw_ge                      -                                                                                                                                 Prafulla Wadaskar <prafulla@marvell.com>
 Active  arm         arm926ejs      kirkwood    Marvell         -                   rd6281a                              -                                                                                                                                 Prafulla Wadaskar <prafulla@marvell.com>
 Active  arm         arm926ejs      kirkwood    Marvell         -                   sheevaplug                           -                                                                                                                                 Prafulla Wadaskar <prafulla@marvell.com>
 Active  arm         arm926ejs      kirkwood    Marvell         openrd              openrd_base                          openrd:BOARD_IS_OPENRD_BASE                                                                                                       Prafulla Wadaskar <prafulla@marvell.com>
 Active  arm         arm926ejs      kirkwood    Marvell         openrd              openrd_client                        openrd:BOARD_IS_OPENRD_CLIENT                                                                                                     -
 Active  arm         arm926ejs      kirkwood    Marvell         openrd              openrd_ultimate                      openrd:BOARD_IS_OPENRD_ULTIMATE                                                                                                   -
 Active  arm         arm926ejs      kirkwood    raidsonic       ib62x0              ib62x0                               -                                                                                                                                 Luka Perkov <luka@openwrt.org>
 Active  arm         arm926ejs      kirkwood    Seagate         -                   dockstar                             -                                                                                                                                 Eric Cooper <ecc@cmu.edu>
 Active  arm         arm926ejs      kirkwood    Seagate         -                   goflexhome                           -                                                                                                                                 Suriyan Ramasami <suriyan.r@gmail.com>
 Active  arm         arm926ejs      lpc32xx     timll           devkit3250          devkit3250                           -                                                                                                                                 Vladimir Zapolskiy <vz@mleia.com>
 Active  arm         arm926ejs      mb86r0x     syteco          jadecpu             jadecpu                              -                                                                                                                                 Matthias Weisser <weisserm@arcor.de>
 Active  arm         arm926ejs      mx25        freescale       mx25pdk             mx25pdk                              mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg                                                                           Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         arm926ejs      mx25        karo            tx25                tx25                                 -                                                                                                                                 John Rigby <jcrigby@gmail.com>
 Active  arm         arm926ejs      mx25        syteco          zmx25               zmx25                                -                                                                                                                                 Matthias Weisser <weisserm@arcor.de>
 Active  arm         arm926ejs      mx27        armadeus        apf27               apf27                                -                                                                                                                                 Philippe Reynes <tremyfr@yahoo.fr>:Eric Jarrige <eric.jarrige@armadeus.org>
 Active  arm         arm926ejs      mx27        logicpd         imx27lite           imx27lite                            -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  arm         arm926ejs      mx27        logicpd         imx27lite           magnesium                            -                                                                                                                                 Heiko Schocher <hs@denx.de>
 Active  arm         arm926ejs      mxs         bluegiga        apx4devkit          apx4devkit                           apx4devkit                                                                                                                        Lauri Hintsala <lauri.hintsala@bluegiga.com>
 Active  arm         arm926ejs      mxs         creative        xfi3                xfi3                                 -                                                                                                                                 Marek Vasut <marek.vasut@gmail.com>
 Active  arm         arm926ejs      mxs         denx            m28evk              m28evk                               m28evk                                                                                                                            Marek Vasut <marek.vasut@gmail.com>
 Active  arm         arm926ejs      mxs         freescale       mx23evk             mx23evk                              mx23evk                                                                                                                           Otavio Salvador <otavio@ossystems.com.br>
 Active  arm         arm926ejs      mxs         freescale       mx28evk             mx28evk                              mx28evk:ENV_IS_IN_MMC                                                                                                             Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         arm926ejs      mxs         freescale       mx28evk             mx28evk_auart_console                mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC                                                                  Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         arm926ejs      mxs         freescale       mx28evk             mx28evk_nand                         mx28evk:ENV_IS_IN_NAND                                                                                                            Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         arm926ejs      mxs         olimex          mx23_olinuxino      mx23_olinuxino                       mx23_olinuxino                                                                                                                    Marek Vasut <marek.vasut@gmail.com>
 Active  arm         arm926ejs      mxs         ppcag           bg0900              bg0900                               bg0900                                                                                                                            Marek Vasut <marex@denx.de>
 Active  arm         arm926ejs      mxs         sandisk         sansa_fuze_plus     sansa_fuze_plus                      -                                                                                                                                 Marek Vasut <marek.vasut@gmail.com>
 Active  arm         arm926ejs      mxs         schulercontrol  sc_sps_1            sc_sps_1                             -                                                                                                                                 Marek Vasut <marek.vasut@gmail.com>
 Active  arm         arm926ejs      nomadik     st              nhk8815             nhk8815                              -                                                                                                                                 Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
 Active  arm         arm926ejs      nomadik     st              nhk8815             nhk8815_onenand                      nhk8815:BOOT_ONENAND                                                                                                              Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
 Active  arm         arm926ejs      omap        ti              -                   omap5912osk                          -                                                                                                                                 Rishi Bhattacharya <rishi@ti.com>
 Active  arm         arm926ejs      orion5x     LaCie           -                   edminiv2                             -                                                                                                                                 Albert ARIBAUD <albert.u.boot@aribaud.net>
 Active  arm         arm926ejs      pantheon    Marvell         -                   dkb                                  -                                                                                                                                 Lei Wen <leiwen@marvell.com>
 Active  arm         arm926ejs      spear       spear           -                   x600                                 x600                                                                                                                              Stefan Roese <sr@denx.de>
 Active  arm         arm926ejs      spear       spear           spear300            spear300                             spear3xx_evb:spear300                                                                                                             Vipin Kumar <vipin.kumar@st.com>
 Active  arm         arm926ejs      spear       spear           spear300            spear300_nand                        spear3xx_evb:spear300,nand                                                                                                        -
 Active  arm         arm926ejs      spear       spear           spear300            spear300_usbtty                      spear3xx_evb:spear300,usbtty                                                                                                      -
 Active  arm         arm926ejs      spear       spear           spear300            spear300_usbtty_nand                 spear3xx_evb:spear300,usbtty,nand                                                                                                 -
 Active  arm         arm926ejs      spear       spear           spear310            spear310                             spear3xx_evb:spear310                                                                                                             Vipin Kumar <vipin.kumar@st.com>
 Active  arm         arm926ejs      spear       spear           spear310            spear310_nand                        spear3xx_evb:spear310,nand                                                                                                        -
 Active  arm         arm926ejs      spear       spear           spear310            spear310_pnor                        spear3xx_evb:spear310,FLASH_PNOR                                                                                                  -
 Active  arm         arm926ejs      spear       spear           spear310            spear310_usbtty                      spear3xx_evb:spear310,usbtty                                                                                                      -
 Active  arm         arm926ejs      spear       spear           spear310            spear310_usbtty_nand                 spear3xx_evb:spear310,usbtty,nand                                                                                                 -
 Active  arm         arm926ejs      spear       spear           spear310            spear310_usbtty_pnor                 spear3xx_evb:spear310,usbtty,FLASH_PNOR                                                                                           -
 Active  arm         arm926ejs      spear       spear           spear320            spear320                             spear3xx_evb:spear320                                                                                                             Vipin Kumar <vipin.kumar@st.com>
 Active  arm         arm926ejs      spear       spear           spear320            spear320_nand                        spear3xx_evb:spear320,nand                                                                                                        -
 Active  arm         arm926ejs      spear       spear           spear320            spear320_pnor                        spear3xx_evb:spear320,FLASH_PNOR                                                                                                  -
 Active  arm         arm926ejs      spear       spear           spear320            spear320_usbtty                      spear3xx_evb:spear320,usbtty                                                                                                      -
 Active  arm         arm926ejs      spear       spear           spear320            spear320_usbtty_nand                 spear3xx_evb:spear320,usbtty,nand                                                                                                 -
 Active  arm         arm926ejs      spear       spear           spear320            spear320_usbtty_pnor                 spear3xx_evb:spear320,usbtty,FLASH_PNOR                                                                                           -
 Active  arm         arm926ejs      spear       spear           spear600            spear600                             spear6xx_evb:spear600                                                                                                             Vipin Kumar <vipin.kumar@st.com>
 Active  arm         arm926ejs      spear       spear           spear600            spear600_nand                        spear6xx_evb:spear600,nand                                                                                                        -
 Active  arm         arm926ejs      spear       spear           spear600            spear600_usbtty                      spear6xx_evb:spear600,usbtty                                                                                                      -
 Active  arm         arm926ejs      spear       spear           spear600            spear600_usbtty_nand                 spear6xx_evb:spear600,usbtty,nand                                                                                                 -
 Active  arm         arm926ejs      versatile   armltd          versatile           versatileab                          versatile:ARCH_VERSATILE_AB                                                                                                       -
 Active  arm         arm926ejs      versatile   armltd          versatile           versatilepb                          versatile:ARCH_VERSATILE_PB                                                                                                       -
 Active  arm         arm926ejs      versatile   armltd          versatile           versatileqemu                        versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB                                                                                   -
 Active  arm         arm946es       -           armltd          integrator          integratorap_cm946es                 integratorap:CM946ES                                                                                                              Linus Walleij <linus.walleij@linaro.org>
 Active  arm         arm946es       -           armltd          integrator          integratorcp_cm946es                 integratorcp:CM946ES                                                                                                              Linus Walleij <linus.walleij@linaro.org>
 Active  arm         armv7          -           armltd          vexpress            vexpress_ca15_tc2                    -                                                                                                                                 -
 Active  arm         armv7          -           armltd          vexpress            vexpress_ca5x2                       -                                                                                                                                 Matt Waddel <matt.waddel@linaro.org>
 Active  arm         armv7          -           armltd          vexpress            vexpress_ca9x4                       -                                                                                                                                 Matt Waddel <matt.waddel@linaro.org>
 Active  arm         armv7          am33xx      compulab        cm_t335             cm_t335                              cm_t335                                                                                                                           Igor Grinberg <grinberg@compulab.co.il>
 Active  arm         armv7          am33xx      isee            igep0033            am335x_igep0033                      -                                                                                                                                 Enric Balletbo i Serra <eballetbo@iseebcn.com>
 Active  arm         armv7          am33xx      phytec          pcm051              pcm051_rev1                          pcm051:REV1                                                                                                                       Lars Poeschel <poeschel@lemonage.de>
 Active  arm         armv7          am33xx      phytec          pcm051              pcm051_rev3                          pcm051:REV3                                                                                                                       Lars Poeschel <poeschel@lemonage.de>
 Active  arm         armv7          am33xx      siemens         dxr2                dxr2                                 -                                                                                                                                 Roger Meier <r.meier@siemens.com>
 Active  arm         armv7          am33xx      siemens         pxm2                pxm2                                 -                                                                                                                                 Roger Meier <r.meier@siemens.com>
 Active  arm         armv7          am33xx      siemens         rut                 rut                                  -                                                                                                                                 Roger Meier <r.meier@siemens.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_boneblack                     am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT                                                                                         Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm                           am335x_evm:SERIAL1,CONS_INDEX=1,NAND                                                                                              Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_nor                       am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR                                                                                          Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_norboot                   am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT                                                                                      Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_spiboot                   am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT                                                                                          Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart1                     am335x_evm:SERIAL2,CONS_INDEX=2,NAND                                                                                              Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart2                     am335x_evm:SERIAL3,CONS_INDEX=3,NAND                                                                                              Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart3                     am335x_evm:SERIAL4,CONS_INDEX=4,NAND                                                                                              Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart4                     am335x_evm:SERIAL5,CONS_INDEX=5,NAND                                                                                              Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart5                     am335x_evm:SERIAL6,CONS_INDEX=6,NAND                                                                                              Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_usbspl                    am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT                                                                           Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am43xx              am43xx_evm                           am43xx_evm:SERIAL1,CONS_INDEX=1                                                                                                   -
 Active  arm         armv7          am33xx      ti              ti814x              ti814x_evm                           -                                                                                                                                 Matt Porter <matt.porter@linaro.org>
 Active  arm         armv7          am33xx      ti              ti816x              ti816x_evm                           -                                                                                                                                 -
 Active  arm         armv7          at91        atmel           sama5d3xek          sama5d3xek_mmc                       sama5d3xek:SAMA5D3,SYS_USE_MMC                                                                                                    Bo Shen <voice.shen@atmel.com>
 Active  arm         armv7          at91        atmel           sama5d3xek          sama5d3xek_nandflash                 sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH                                                                                              Bo Shen <voice.shen@atmel.com>
 Active  arm         armv7          at91        atmel           sama5d3xek          sama5d3xek_spiflash                  sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH                                                                                            Bo Shen <voice.shen@atmel.com>
 Active  arm         armv7          exynos      samsung         arndale             arndale                              -                                                                                                                                 Inderpal Singh <inderpal.singh@linaro.org>
 Active  arm         armv7          exynos      samsung         origen              origen                               -                                                                                                                                 Chander Kashyap <k.chander@samsung.com>
 Active  arm         armv7          exynos      samsung         smdk5250            smdk5250                             -                                                                                                                                 Chander Kashyap <k.chander@samsung.com>
 Active  arm         armv7          exynos      samsung         smdk5250            snow                                 -                                                                                                                                 Rajeshwari Shinde <rajeshwari.s@samsung.com>
 Active  arm         armv7          exynos      samsung         smdkv310            smdkv310                             -                                                                                                                                 Chander Kashyap <k.chander@samsung.com>
 Active  arm         armv7          exynos      samsung         trats               trats                                -                                                                                                                                 Lukasz Majewski <l.majewski@samsung.com>
 Active  arm         armv7          exynos      samsung         trats2              trats2                               -                                                                                                                                 Piotr Wilczek <p.wilczek@samsung.com>
 Active  arm         armv7          exynos      samsung         universal_c210      s5pc210_universal                    -                                                                                                                                 Przemyslaw Marczak <p.marczak@samsung.com>
 Active  arm         armv7          highbank    -               highbank            highbank                             -                                                                                                                                 Rob Herring <rob.herring@calxeda.com>
 Active  arm         armv7          mx5         denx            m53evk              m53evk                               m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg                                                                                  Marek Vasut <marek.vasut@gmail.com>
 Active  arm         armv7          mx5         esg             ima3-mx53           ima3-mx53                            ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg                                                                             -
 Active  arm         armv7          mx5         freescale       mx51evk             mx51evk                              mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg                                                                           Stefano Babic <sbabic@denx.de>
 Active  arm         armv7          mx5         freescale       mx53ard             mx53ard                              mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg                                                                       Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         armv7          mx5         freescale       mx53evk             mx53evk                              mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg                                                                           Jason Liu <r64343@freescale.com>
 Active  arm         armv7          mx5         freescale       mx53loco            mx53loco                             mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg                                                                         Jason Liu <r64343@freescale.com>
 Active  arm         armv7          mx5         freescale       mx53smd             mx53smd                              mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg                                                                           Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         armv7          mx5         genesi          mx51_efikamx        mx51_efikamx                         mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg                                -
 Active  arm         armv7          mx5         genesi          mx51_efikamx        mx51_efikasb                         mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg                                -
 Active  arm         armv7          mx5         ttcontrol       vision2             vision2                              vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg                                                                     Stefano Babic <sbabic@denx.de>
 Active  arm         armv7          mx6         -               udoo		   udoo_quad				udoo:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024          Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         armv7          mx6         -               wandboard           wandboard_dl                         wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024                                                  Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         armv7          mx6         -               wandboard           wandboard_quad                       wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048                                                  Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         armv7          mx6         -               wandboard           wandboard_solo                       wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512                                                     Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         armv7          mx6         boundary        nitrogen6x          mx6qsabrelite                        nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE                                         Eric Nelson <eric.nelson@boundarydevices.com>
 Active  arm         armv7          mx6         boundary        nitrogen6x          nitrogen6dl                          nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024                                                 Eric Nelson <eric.nelson@boundarydevices.com>
 Active  arm         armv7          mx6         boundary        nitrogen6x          nitrogen6dl2g                        nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048                                               Eric Nelson <eric.nelson@boundarydevices.com>
 Active  arm         armv7          mx6         boundary        nitrogen6x          nitrogen6q                           nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024                                                   Eric Nelson <eric.nelson@boundarydevices.com>
 Active  arm         armv7          mx6         boundary        nitrogen6x          nitrogen6q2g                         nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048                                                 Eric Nelson <eric.nelson@boundarydevices.com>
 Active  arm         armv7          mx6         boundary        nitrogen6x          nitrogen6s                           nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512                                                    Eric Nelson <eric.nelson@boundarydevices.com>
 Active  arm         armv7          mx6         boundary        nitrogen6x          nitrogen6s1g                         nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024                                                 Eric Nelson <eric.nelson@boundarydevices.com>
 Active  arm         armv7          mx6         congatec        cgtqmx6eval         cgtqmx6qeval                         cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q                                                          Leo Sartre <lsartre@adeneo-embedded.com>
 Active  arm         armv7          mx6         freescale       mx6qarm2            mx6qarm2                             mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg                                                                         Jason Liu <r64343@freescale.com>
 Active  arm         armv7          mx6         freescale       mx6qsabreauto       mx6qsabreauto                        mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q                                                          Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         armv7          mx6         freescale       mx6sabresd          mx6dlsabresd                         mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL                                                             Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         armv7          mx6         freescale       mx6sabresd          mx6qsabresd                          mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q                                                           Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         armv7          mx6         freescale       mx6slevk            mx6slevk                             mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL                                                                   Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         armv7          mx6         freescale       titanium            titanium                             titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg                                                                         Stefan Roese <sr@denx.de>
 Active  arm         armv7          omap3       -               overo               omap3_overo                          -                                                                                                                                 Steve Sakoman <sakoman@gmail.com>
 Active  arm         armv7          omap3       -               pandora             omap3_pandora                        -                                                                                                                                 Grazvydas Ignotas <notasas@gmail.com>
 Active  arm         armv7          omap3       8dtech          eco5pk              eco5pk                               -                                                                                                                                 Raphael Assenat <raph@8d.com>
 Active  arm         armv7          omap3       comelit         dig297              dig297                               -                                                                                                                                 Luca Ceresoli <luca.ceresoli@comelit.it>
 Active  arm         armv7          omap3       compulab        cm_t35              cm_t35                               -                                                                                                                                 Igor Grinberg <grinberg@compulab.co.il>
 Active  arm         armv7          omap3       corscience      tricorder           tricorder                            -                                                                                                                                 Thomas Weber <weber@corscience.de>
 Active  arm         armv7          omap3       corscience      tricorder           tricorder_flash                      tricorder:FLASHCARD                                                                                                               Thomas Weber <weber@corscience.de>
 Active  arm         armv7          omap3       htkw            mcx                 mcx                                  -                                                                                                                                 Ilya Yanok <yanok@emcraft.com>
 Active  arm         armv7          omap3       isee            igep00x0            igep0020                             omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND                                                                          Enric Balletbo i Serra <eballetbo@iseebcn.com>
 Active  arm         armv7          omap3       isee            igep00x0            igep0020_nand                        omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND                                                                             -
 Active  arm         armv7          omap3       isee            igep00x0            igep0030                             omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND                                                                          Enric Balletbo i Serra <eballetbo@iseebcn.com>
 Active  arm         armv7          omap3       isee            igep00x0            igep0030_nand                        omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND                                                                             -
 Active  arm         armv7          omap3       isee            igep00x0            igep0032                             omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND                                                                          Enric Balletbo i Serra <eballetbo@iseebcn.com>
 Active  arm         armv7          omap3       logicpd         am3517evm           am3517_evm                           -                                                                                                                                 Vaibhav Hiremath <hvaibhav@ti.com>
 Active  arm         armv7          omap3       logicpd         omap3som            omap3_logic                          -                                                                                                                                 Peter Barada <peter.barada@logicpd.com>
 Active  arm         armv7          omap3       logicpd         zoom1               omap3_zoom1                          -                                                                                                                                 Nishanth Menon <nm@ti.com>
 Active  arm         armv7          omap3       logicpd         zoom2               omap3_zoom2                          -                                                                                                                                 Tom Rix <Tom.Rix@windriver.com>
 Active  arm         armv7          omap3       matrix_vision   mvblx               omap3_mvblx                          -                                                                                                                                 Michael Jones <michael.jones@matrix-vision.de>
 Active  arm         armv7          omap3       nokia           rx51                nokia_rx51                           -                                                                                                                                 Pali Rohár <pali.rohar@gmail.com>
 Active  arm         armv7          omap3       technexion      twister             twister                              -                                                                                                                                 Stefano Babic <sbabic@denx.de>
 Active  arm         armv7          omap3       teejet          mt_ventoux          mt_ventoux                           -                                                                                                                                 Stefano Babic <sbabic@denx.de>
 Active  arm         armv7          omap3       ti              am3517crane         am3517_crane                         -                                                                                                                                 Nagendra T S  <nagendra@mistralsolutions.com>
 Active  arm         armv7          omap3       ti              beagle              omap3_beagle                         -                                                                                                                                 Tom Rini <trini@ti.com>
 Active  arm         armv7          omap3       ti              evm                 omap3_evm                            -                                                                                                                                 Tom Rini <trini@ti.com>
 Active  arm         armv7          omap3       ti              evm                 omap3_evm_quick_mmc                  -                                                                                                                                 -
 Active  arm         armv7          omap3       ti              evm                 omap3_evm_quick_nand                 -                                                                                                                                 -
 Active  arm         armv7          omap3       ti              sdp3430             omap3_sdp3430                        -                                                                                                                                 Nishanth Menon <nm@ti.com>
 Active  arm         armv7          omap3       timll           devkit8000          devkit8000                           -                                                                                                                                 Thomas Weber <weber@corscience.de>
 Active  arm         armv7          omap4       ti              panda               omap4_panda                          -                                                                                                                                 Sricharan R <r.sricharan@ti.com>
 Active  arm         armv7          omap4       ti              sdp4430             omap4_sdp4430                        -                                                                                                                                 Sricharan R <r.sricharan@ti.com>
 Active  arm         armv7          omap5       ti              dra7xx              dra7xx_evm                           dra7xx_evm:CONS_INDEX=1                                                                                                           Lokesh Vutla <lokeshvutla@ti.com>
 Active  arm         armv7          omap5       ti              dra7xx              dra7xx_evm_uart3                     dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT                                                                                        Lokesh Vutla <lokeshvutla@ti.com>
 Active  arm         armv7          omap5       ti              omap5_uevm          omap5_uevm                           -                                                                                                                                 -
 Active  arm         armv7          rmobile     atmark-techno   armadillo-800eva    armadillo-800eva                     -                                                                                                                                 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 Active  arm         armv7          rmobile     kmc             kzm9g               kzm9g                                -                                                                                                                                 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
 Active  arm         armv7          rmobile     renesas         lager               lager                                -                                                                                                                                 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 Active  arm         armv7          rmobile     renesas         lager               lager_nor                            lager:NORFLASH                                                                                                                    Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 Active  arm         armv7          rmobile     renesas         koelsch             koelsch                              -                                                                                                                                 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 Active  arm         armv7          rmobile     renesas         koelsch             koelsch_nor                          koelsch:NORFLASH                                                                                                                  Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 Active  arm         armv7          s5pc1xx     samsung         goni                s5p_goni                             -                                                                                                                                 Mateusz Zalega <m.zalega@samsung.com>
 Active  arm         armv7          s5pc1xx     samsung         smdkc100            smdkc100                             -                                                                                                                                 Minkyu Kang <mk7.kang@samsung.com>
 Active  arm         armv7          socfpga     altera          socfpga             socfpga_cyclone5                     -                                                                                                                                 -
 Active  arm         armv7          u8500       st-ericsson     snowball            snowball                             -                                                                                                                                 Mathieu Poirier <mathieu.poirier@linaro.org>
 Active  arm         armv7          u8500       st-ericsson     u8500               u8500_href                           -                                                                                                                                 -
 Active  arm         armv7          vf610       freescale       vf610twr            vf610twr                             vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg                                                                         Alison Wang <b18965@freescale.com>
 Active  arm         armv7          zynq        xilinx          zynq                zynq                                 -                                                                                                                                 Michal Simek <monstr@monstr.eu>
 Active  arm         armv7          zynq        xilinx          zynq                zynq_dcc                             zynq:ZYNQ_DCC                                                                                                                     Michal Simek <monstr@monstr.eu>
 Active  arm         armv7:arm720t  tegra114    nvidia          dalmore             dalmore                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     avionic-design  medcom-wide         medcom-wide                          -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
 Active  arm         armv7:arm720t  tegra20     avionic-design  plutux              plutux                               -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
 Active  arm         armv7:arm720t  tegra20     avionic-design  tec                 tec                                  -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
 Active  arm         armv7:arm720t  tegra20     compal          paz00               paz00                                -                                                                                                                                 Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     compulab        trimslice           trimslice                            -                                                                                                                                 Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     nvidia          harmony             harmony                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     nvidia          seaboard            seaboard                             -                                                                                                                                 Tom Warren <twarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     nvidia          ventana             ventana                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     nvidia          whistler            whistler                             -                                                                                                                                 Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     toradex         colibri_t20_iris    colibri_t20_iris                     -                                                                                                                                 Lucas Stach <dev@lynxeye.de>
 Active  arm         armv7:arm720t  tegra30     nvidia          beaver              beaver                               -                                                                                                                                 Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra30     nvidia          cardhu              cardhu                               -                                                                                                                                 Tom Warren <twarren@nvidia.com>
 Active  arm         ixp            -           -               -                   actux2                               -                                                                                                                                 Michael Schwingen <michael@schwingen.org>
 Active  arm         ixp            -           -               -                   actux3                               -                                                                                                                                 Michael Schwingen <michael@schwingen.org>
 Active  arm         ixp            -           -               -                   actux4                               -                                                                                                                                 Michael Schwingen <michael@schwingen.org>
 Active  arm         ixp            -           -               -                   dvlhost                              -                                                                                                                                 Michael Schwingen <michael@schwingen.org>
 Active  arm         ixp            -           -               actux1              actux1_4_16                          actux1:FLASH2X2                                                                                                                   Michael Schwingen <michael@schwingen.org>
 Active  arm         ixp            -           -               actux1              actux1_4_32                          actux1:FLASH2X2,RAM_32MB                                                                                                          Michael Schwingen <michael@schwingen.org>
 Active  arm         ixp            -           -               actux1              actux1_8_16                          actux1:FLASH1X8                                                                                                                   Michael Schwingen <michael@schwingen.org>
 Active  arm         ixp            -           -               actux1              actux1_8_32                          actux1:FLASH1X8,RAM_32MB                                                                                                          Michael Schwingen <michael@schwingen.org>
 Active  arm         pxa            -           -               -                   balloon3                             -                                                                                                                                 Marek Vasut <marek.vasut@gmail.com>
 Active  arm         pxa            -           -               -                   h2200                                -                                                                                                                                 Lukasz Dalek <luk0104@gmail.com>
 Active  arm         pxa            -           -               -                   palmld                               -                                                                                                                                 Marek Vasut <marek.vasut@gmail.com>
 Active  arm         pxa            -           -               -                   palmtc                               -                                                                                                                                 Marek Vasut <marek.vasut@gmail.com>
 Active  arm         pxa            -           -               -                   palmtreo680                          -                                                                                                                                 Mike Dunn <mikedunn@newsguy.com>
 Active  arm         pxa            -           -               -                   pxa255_idp                           -                                                                                                                                 Cliff Brake <cliff.brake@gmail.com>
 Active  arm         pxa            -           -               -                   trizepsiv                            -                                                                                                                                 Stefano Babic <sbabic@denx.de>
 Active  arm         pxa            -           -               -                   xaeniax                              -                                                                                                                                 -
 Active  arm         pxa            -           -               -                   zipitz2                              -                                                                                                                                 Marek Vasut <marek.vasut@gmail.com>
 Active  arm         pxa            -           -               trizepsiv           polaris                              trizepsiv:POLARIS                                                                                                                 Stefano Babic <sbabic@denx.de>
 Active  arm         pxa            -           -               vpac270             vpac270_nor_128                      vpac270:NOR,RAM_128M                                                                                                              Marek Vasut <marek.vasut@gmail.com>
 Active  arm         pxa            -           -               vpac270             vpac270_nor_256                      vpac270:NOR,RAM_256M                                                                                                              Marek Vasut <marek.vasut@gmail.com>
 Active  arm         pxa            -           -               vpac270             vpac270_ond_256                      vpac270:ONENAND,RAM_256M                                                                                                          Marek Vasut <marek.vasut@gmail.com>
 Active  arm         pxa            -           icpdas          lp8x4x              lp8x4x                               -                                                                                                                                 Sergey Yanovich <ynvich@gmail.com>
 Active  arm         pxa            -           toradex         -                   colibri_pxa270                       -                                                                                                                                 Marek Vasut <marek.vasut@gmail.com>
 Active  arm         sa1100         -           -               -                   jornada                              -                                                                                                                                 Kristoffer Ericson <kristoffer.ericson@gmail.com>
 Active  avr32       at32ap         at32ap700x  atmel           -                   atngw100                             -                                                                                                                                 Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
 Active  avr32       at32ap         at32ap700x  atmel           -                   atngw100mkii                         -                                                                                                                                 Andreas Bießmann <andreas.devel@googlemail.com>
 Active  avr32       at32ap         at32ap700x  atmel           atstk1000           atstk1002                            -                                                                                                                                 Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
 Active  avr32       at32ap         at32ap700x  atmel           atstk1000           atstk1003                            -                                                                                                                                 Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
 Active  avr32       at32ap         at32ap700x  atmel           atstk1000           atstk1004                            -                                                                                                                                 Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
 Active  avr32       at32ap         at32ap700x  atmel           atstk1000           atstk1006                            -                                                                                                                                 Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
 Active  avr32       at32ap         at32ap700x  earthlcd        -                   favr-32-ezkit                        -                                                                                                                                 Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
 Active  avr32       at32ap         at32ap700x  in-circuit      -                   grasshopper                          -                                                                                                                                 Andreas Bießmann <andreas.devel@googlemail.com>
 Active  avr32       at32ap         at32ap700x  mimc            -                   mimc200                              -                                                                                                                                 Mark Jackson <mpfj@mimc.co.uk>
 Active  avr32       at32ap         at32ap700x  miromico        -                   hammerhead                           -                                                                                                                                 Julien May <julien.may@miromico.ch>:Alex Raimondi <alex.raimondi@miromico.ch>
 Active  blackfin    blackfin       -           -               -                   bct-brettl2                          -                                                                                                                                 Peter Meerwald <devel@bct-electronic.com>
 Active  blackfin    blackfin       -           -               -                   bf506f-ezkit                         -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   bf518f-ezbrd                         -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   bf525-ucr2                           -                                                                                                                                 Haitao Zhang <hzhang@ucrobotics.com>:Chong Huang <chuang@ucrobotics.com>
 Active  blackfin    blackfin       -           -               -                   bf526-ezbrd                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   bf527-ad7160-eval                    -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   bf527-ezkit                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   bf527-sdp                            -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   bf533-ezkit                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   bf533-stamp                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   bf537-minotaur                       -                                                                                                                                 Martin Strubel <strubel@section5.ch>
 Active  blackfin    blackfin       -           -               -                   bf537-pnav                           -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   bf537-srv1                           -                                                                                                                                 Martin Strubel <strubel@section5.ch>
 Active  blackfin    blackfin       -           -               -                   bf537-stamp                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   bf538f-ezkit                         -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   bf548-ezkit                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   bf561-acvilon                        -                                                                                                                                 Anton Shurpin <shurpin.aa@niistt.ru>:Valentin Yakovenkov <yakovenkov@niistt.ru>
 Active  blackfin    blackfin       -           -               -                   bf561-ezkit                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   bf609-ezkit                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   blackstamp                           -                                                                                                                                 Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
 Active  blackfin    blackfin       -           -               -                   blackvme                             -                                                                                                                                 Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
 Active  blackfin    blackfin       -           -               -                   br4                                  -                                                                                                                                 Dimitar Penev <dpn@switchfin.org>
 Active  blackfin    blackfin       -           -               -                   cm-bf527                             -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   cm-bf533                             -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   cm-bf537e                            -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   cm-bf537u                            -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   cm-bf548                             -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   cm-bf561                             -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   dnp5370                              -                                                                                                                                 M.Hasewinkel (MHA) <info@ssv-embedded.de>
 Active  blackfin    blackfin       -           -               -                   ibf-dsp561                           -                                                                                                                                 I-SYST Micromodule <support@i-syst.com>
 Active  blackfin    blackfin       -           -               -                   ip04                                 -                                                                                                                                 Brent Kandetzki <brentk@teleco.com>
 Active  blackfin    blackfin       -           -               -                   pr1                                  -                                                                                                                                 Dimitar Penev <dpn@switchfin.org>
 Active  blackfin    blackfin       -           -               -                   tcm-bf518                            -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   tcm-bf537                            -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               bf527-ezkit         bf527-ezkit-v2                       bf527-ezkit:BF527_EZKIT_REV_2_1                                                                                                   Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 Active  m68k        mcf5227x       -           freescale       m52277evb           M52277EVB                            M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000                                                                              TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf5227x       -           freescale       m52277evb           M52277EVB_stmicro                    M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000                                                                        TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf523x        -           freescale       m5235evb            M5235EVB                             M5235EVB:SYS_TEXT_BASE=0xFFE00000                                                                                                 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf523x        -           freescale       m5235evb            M5235EVB_Flash32                     M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000                                                                                TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf52x2        -           -               -                   idmr                                 -                                                                                                                                 -
 Active  m68k        mcf52x2        -           -               cobra5272           cobra5272                            -                                                                                                                                 -
 Active  m68k        mcf52x2        -           BuS             eb_cpu5282          eb_cpu5282                           eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400                                                                   Jens Scharsig <esw@bus-elektronik.de>
 Active  m68k        mcf52x2        -           BuS             eb_cpu5282          eb_cpu5282_internal                  eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418                                                                   Jens Scharsig <esw@bus-elektronik.de>
 Active  m68k        mcf52x2        -           esd             tasreg              TASREG                               -                                                                                                                                 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 Active  m68k        mcf52x2        -           freescale       m5208evbe           M5208EVBE                            -                                                                                                                                 -
 Active  m68k        mcf52x2        -           freescale       m5249evb            M5249EVB                             -                                                                                                                                 -
 Active  m68k        mcf52x2        -           freescale       m5253demo           M5253DEMO                            -                                                                                                                                 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf52x2        -           freescale       m5253evbe           M5253EVBE                            -                                                                                                                                 Hayden Fraser <Hayden.Fraser@freescale.com>
 Active  m68k        mcf52x2        -           freescale       m5271evb            M5271EVB                             -                                                                                                                                 -
 Active  m68k        mcf52x2        -           freescale       m5272c3             M5272C3                              -                                                                                                                                 -
 Active  m68k        mcf52x2        -           freescale       m5275evb            M5275EVB                             -                                                                                                                                 -
 Active  m68k        mcf52x2        -           freescale       m5282evb            M5282EVB                             -                                                                                                                                 -
 Active  m68k        mcf532x        -           astro           mcf5373l            astro_mcf5373l                       -                                                                                                                                 Wolfgang Wegner <w.wegner@astro-kom.de>
 Active  m68k        mcf532x        -           freescale       m53017evb           M53017EVB                            -                                                                                                                                 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf532x        -           freescale       m5329evb            M5329AFEE                            M5329EVB:NANDFLASH_SIZE=0                                                                                                         TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf532x        -           freescale       m5329evb            M5329BFEE                            M5329EVB:NANDFLASH_SIZE=16                                                                                                        TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf532x        -           freescale       m5373evb            M5373EVB                             M5373EVB:NANDFLASH_SIZE=16                                                                                                        TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf5445x       -           freescale       m54418twr           M54418TWR                            M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000                                               -
 Active  m68k        mcf5445x       -           freescale       m54418twr           M54418TWR_nand_mii                   M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000                                                        -
 Active  m68k        mcf5445x       -           freescale       m54418twr           M54418TWR_nand_rmii                  M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000                                                        -
 Active  m68k        mcf5445x       -           freescale       m54418twr           M54418TWR_nand_rmii_lowfreq          M54418TWR:SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000                                             -
 Active  m68k        mcf5445x       -           freescale       m54418twr           M54418TWR_serial_mii                 M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000                                               -
 Active  m68k        mcf5445x       -           freescale       m54418twr           M54418TWR_serial_rmii                M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000                                               -
 Active  m68k        mcf5445x       -           freescale       m54451evb           M54451EVB                            M54451EVB:SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000                                                                      -
 Active  m68k        mcf5445x       -           freescale       m54451evb           M54451EVB_stmicro                    M54451EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000                                              -
 Active  m68k        mcf5445x       -           freescale       m54455evb           M54455EVB                            M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333                                                       TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf5445x       -           freescale       m54455evb           M54455EVB_a66                        M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=66666666                                                       TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf5445x       -           freescale       m54455evb           M54455EVB_i66                        M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=66666666                                                       TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf5445x       -           freescale       m54455evb           M54455EVB_intel                      M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=33333333                                                       TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf5445x       -           freescale       m54455evb           M54455EVB_stm33                      M54455EVB:SYS_STMICRO_BOOT,CF_SBF,SYS_TEXT_BASE=0x4FE00000,SYS_INPUT_CLKSRC=33333333                                              TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf547x_8x     -           freescale       m547xevb            M5475AFE                             M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64                                                                          TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf547x_8x     -           freescale       m547xevb            M5475BFE                             M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16                                                            TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf547x_8x     -           freescale       m547xevb            M5475CFE                             M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL                                      TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf547x_8x     -           freescale       m547xevb            M5475DFE                             M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL                                                              TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf547x_8x     -           freescale       m547xevb            M5475EFE                             M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL                                                    TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf547x_8x     -           freescale       m547xevb            M5475FFE                             M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64                       TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf547x_8x     -           freescale       m547xevb            M5475GFE                             M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64                                                                          TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf547x_8x     -           freescale       m548xevb            M5485AFE                             M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64                                                                          TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf547x_8x     -           freescale       m548xevb            M5485BFE                             M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16                                                            TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf547x_8x     -           freescale       m548xevb            M5485CFE                             M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL                                      TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf547x_8x     -           freescale       m548xevb            M5485DFE                             M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL                                                              TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf547x_8x     -           freescale       m548xevb            M5485EFE                             M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL                                                    TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf547x_8x     -           freescale       m548xevb            M5485FFE                             M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64                       TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf547x_8x     -           freescale       m548xevb            M5485GFE                             M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64                                                                          TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf547x_8x     -           freescale       m548xevb            M5485HFE                             M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO                                                  TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  microblaze  microblaze     -           xilinx          microblaze-generic  microblaze-generic                   -                                                                                                                                 Michal Simek <monstr@monstr.eu>
 Active  mips        mips32         -           -               qemu-mips           qemu_mips                            qemu-mips:SYS_BIG_ENDIAN                                                                                                          Vlad Lungu <vlad.lungu@windriver.com>
 Active  mips        mips32         -           -               qemu-mips           qemu_mipsel                          qemu-mips:SYS_LITTLE_ENDIAN                                                                                                       -
 Active  mips        mips32         -           imgtec          malta               malta                                malta:MIPS32,SYS_BIG_ENDIAN                                                                                                       Paul Burton <paul.burton@imgtec.com>
 Active  mips        mips32         -           imgtec          malta               maltael                              malta:MIPS32,SYS_LITTLE_ENDIAN                                                                                                    Paul Burton <paul.burton@imgtec.com>
 Active  mips        mips32         -           micronas        vct                 vct_platinum                         vct:VCT_PLATINUM                                                                                                                  -
 Active  mips        mips32         -           micronas        vct                 vct_platinum_onenand                 vct:VCT_PLATINUM,VCT_ONENAND                                                                                                      -
 Active  mips        mips32         -           micronas        vct                 vct_platinum_onenand_small           vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE                                                                                      -
 Active  mips        mips32         -           micronas        vct                 vct_platinum_small                   vct:VCT_PLATINUM,VCT_SMALL_IMAGE                                                                                                  -
 Active  mips        mips32         -           micronas        vct                 vct_platinumavc                      vct:VCT_PLATINUMAVC                                                                                                               -
 Active  mips        mips32         -           micronas        vct                 vct_platinumavc_onenand              vct:VCT_PLATINUMAVC,VCT_ONENAND                                                                                                   -
 Active  mips        mips32         -           micronas        vct                 vct_platinumavc_onenand_small        vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE                                                                                   -
 Active  mips        mips32         -           micronas        vct                 vct_platinumavc_small                vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE                                                                                               -
 Active  mips        mips32         -           micronas        vct                 vct_premium                          vct:VCT_PREMIUM                                                                                                                   -
 Active  mips        mips32         -           micronas        vct                 vct_premium_onenand                  vct:VCT_PREMIUM,VCT_ONENAND                                                                                                       -
 Active  mips        mips32         -           micronas        vct                 vct_premium_onenand_small            vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE                                                                                       -
 Active  mips        mips32         -           micronas        vct                 vct_premium_small                    vct:VCT_PREMIUM,VCT_SMALL_IMAGE                                                                                                   -
 Active  mips        mips32         au1x00      -               dbau1x00            dbau1000                             dbau1x00:DBAU1000                                                                                                                 Thomas Lange <thomas@corelatus.se>
 Active  mips        mips32         au1x00      -               dbau1x00            dbau1100                             dbau1x00:DBAU1100                                                                                                                 Thomas Lange <thomas@corelatus.se>
 Active  mips        mips32         au1x00      -               dbau1x00            dbau1500                             dbau1x00:DBAU1500                                                                                                                 Thomas Lange <thomas@corelatus.se>
 Active  mips        mips32         au1x00      -               dbau1x00            dbau1550                             dbau1x00:DBAU1550                                                                                                                 Thomas Lange <thomas@corelatus.se>
 Active  mips        mips32         au1x00      -               dbau1x00            dbau1550_el                          dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN                                                                                               Thomas Lange <thomas@corelatus.se>
 Active  mips        mips32         au1x00      -               pb1x00              pb1000                               pb1x00:PB1000                                                                                                                     -
 Active  mips        mips32         incaip      -               incaip              incaip                               -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  mips        mips32         incaip      -               incaip              incaip_100MHz                        incaip:CPU_CLOCK_RATE=100000000                                                                                                   Wolfgang Denk <wd@denx.de>
 Active  mips        mips32         incaip      -               incaip              incaip_133MHz                        incaip:CPU_CLOCK_RATE=133000000                                                                                                   Wolfgang Denk <wd@denx.de>
 Active  mips        mips32         incaip      -               incaip              incaip_150MHz                        incaip:CPU_CLOCK_RATE=150000000                                                                                                   Wolfgang Denk <wd@denx.de>
 Active  mips        mips64         -           -               qemu-mips           qemu_mips64                          qemu-mips64:SYS_BIG_ENDIAN                                                                                                        -
 Active  mips        mips64         -           -               qemu-mips           qemu_mips64el                        qemu-mips64:SYS_LITTLE_ENDIAN                                                                                                     -
 Active  nds32       n1213          ag101       AndesTech       adp-ag101           adp-ag101                            -                                                                                                                                 Andes <uboot@andestech.com>
 Active  nds32       n1213          ag101       AndesTech       adp-ag101p          adp-ag101p                           -                                                                                                                                 Andes <uboot@andestech.com>
 Active  nds32       n1213          ag102       AndesTech       adp-ag102           adp-ag102                            -                                                                                                                                 Andes <uboot@andestech.com>
 Active  nios2       nios2          -           altera          nios2-generic       nios2-generic                        -                                                                                                                                 Scott McNutt <smcnutt@psyent.com>
 Active  nios2       nios2          -           psyent          pci5441             PCI5441                              -                                                                                                                                 Scott McNutt <smcnutt@psyent.com>
 Active  nios2       nios2          -           psyent          pk1c20              PK1C20                               -                                                                                                                                 Scott McNutt <smcnutt@psyent.com>
 Active  openrisc    or1200         -           openrisc        openrisc-generic    openrisc-generic                     -                                                                                                                                 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
 Active  powerpc     74xx_7xx       -           -               -                   ppmc7xx                              -                                                                                                                                 -
 Active  powerpc     74xx_7xx       -           -               evb64260            P3G4                                 -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     74xx_7xx       -           -               evb64260            ZUMA                                 -                                                                                                                                 Nye Liu <nyet@zumanetworks.com>
 Active  powerpc     74xx_7xx       -           eltec           elppc               ELPPC                                -                                                                                                                                 -
 Active  powerpc     74xx_7xx       -           esd             cpci750             CPCI750                              -                                                                                                                                 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 Active  powerpc     74xx_7xx       -           freescale       mpc7448hpc2         mpc7448hpc2                          -                                                                                                                                 Roy Zang <tie-fei.zang@freescale.com>
 Active  powerpc     74xx_7xx       -           Marvell         db64360             DB64360                              -                                                                                                                                 -
 Active  powerpc     74xx_7xx       -           Marvell         db64460             DB64460                              -                                                                                                                                 -
 Active  powerpc     74xx_7xx       -           prodrive        p3mx                p3m7448                              p3mx:P3M7448                                                                                                                      Stefan Roese <sr@denx.de>
 Active  powerpc     74xx_7xx       -           prodrive        p3mx                p3m750                               p3mx:P3M750                                                                                                                       Stefan Roese <sr@denx.de>
 Active  powerpc     mpc512x        -           -               -                   pdm360ng                             -                                                                                                                                 Michael Weiss <michael.weiss@ifm.com>
 Active  powerpc     mpc512x        -           davedenx        -                   aria                                 -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc512x        -           esd             -                   mecp5123                             -                                                                                                                                 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 Active  powerpc     mpc512x        -           freescale       mpc5121ads          mpc5121ads                           -                                                                                                                                 -
 Active  powerpc     mpc512x        -           freescale       mpc5121ads          mpc5121ads_rev2                      mpc5121ads:MPC5121ADS_REV2                                                                                                        -
 Active  powerpc     mpc512x        -           ifm             ac14xx              ac14xx                               -                                                                                                                                 Anatolij Gustschin <agust@denx.de>
 Active  powerpc     mpc5xx         -           -               cmi                 cmi_mpc5xx                           -                                                                                                                                 -
 Active  powerpc     mpc5xx         -           mpl             pati                PATI                                 -                                                                                                                                 -
 Active  powerpc     mpc5xxx        -           -               -                   canmb                                -                                                                                                                                 -
 Active  powerpc     mpc5xxx        -           -               -                   cm5200                               -                                                                                                                                 -
 Active  powerpc     mpc5xxx        -           -               -                   inka4x0                              -                                                                                                                                 Detlev Zundel <dzu@denx.de>
 Active  powerpc     mpc5xxx        -           -               -                   ipek01                               -                                                                                                                                 Wolfgang Grandegger <wg@denx.de>
 Active  powerpc     mpc5xxx        -           -               -                   jupiter                              -                                                                                                                                 Heiko Schocher <hs@denx.de>
 Active  powerpc     mpc5xxx        -           -               -                   motionpro                            -                                                                                                                                 -
 Active  powerpc     mpc5xxx        -           -               -                   munices                              -                                                                                                                                 -
 Active  powerpc     mpc5xxx        -           -               -                   v38b                                 -                                                                                                                                 -
 Active  powerpc     mpc5xxx        -           -               a3m071              a3m071                               -                                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     mpc5xxx        -           -               a3m071              a4m2k                                a3m071:A4M2K                                                                                                                      Stefan Roese <sr@denx.de>
 Active  powerpc     mpc5xxx        -           -               a4m072              a4m072                               -                                                                                                                                 Sergei Poselenov <sposelenov@emcraft.com>
 Active  powerpc     mpc5xxx        -           -               bc3450              BC3450                               -                                                                                                                                 -
 Active  powerpc     mpc5xxx        -           -               galaxy5200          galaxy5200                           galaxy5200:galaxy5200                                                                                                             Eric Millbrandt <emillbrandt@dekaresearch.com>
 Active  powerpc     mpc5xxx        -           -               galaxy5200          galaxy5200_LOWBOOT                   galaxy5200:galaxy5200_LOWBOOT                                                                                                     Eric Millbrandt <emillbrandt@dekaresearch.com>
 Active  powerpc     mpc5xxx        -           -               icecube             icecube_5200                         IceCube                                                                                                                           Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc5xxx        -           -               icecube             icecube_5200_DDR                     IceCube:MPC5200_DDR                                                                                                               -
 Active  powerpc     mpc5xxx        -           -               icecube             icecube_5200_DDR_LOWBOOT             IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR                                                                                      -
 Active  powerpc     mpc5xxx        -           -               icecube             icecube_5200_DDR_LOWBOOT08           IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR                                                                                      -
 Active  powerpc     mpc5xxx        -           -               icecube             icecube_5200_LOWBOOT                 IceCube:SYS_TEXT_BASE=0xFF000000                                                                                                  -
 Active  powerpc     mpc5xxx        -           -               icecube             icecube_5200_LOWBOOT08               IceCube:SYS_TEXT_BASE=0xFF800000                                                                                                  -
 Active  powerpc     mpc5xxx        -           -               icecube             Lite5200                             IceCube                                                                                                                           -
 Active  powerpc     mpc5xxx        -           -               icecube             Lite5200_LOWBOOT                     IceCube:SYS_TEXT_BASE=0xFF000000                                                                                                  -
 Active  powerpc     mpc5xxx        -           -               icecube             Lite5200_LOWBOOT08                   IceCube:SYS_TEXT_BASE=0xFF800000                                                                                                  -
 Active  powerpc     mpc5xxx        -           -               icecube             lite5200b                            IceCube:MPC5200_DDR,LITE5200B                                                                                                     -
 Active  powerpc     mpc5xxx        -           -               icecube             lite5200b_LOWBOOT                    IceCube:MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000                                                                            -
 Active  powerpc     mpc5xxx        -           -               icecube             lite5200b_PM                         IceCube:MPC5200_DDR,LITE5200B,LITE5200B_PM                                                                                        -
 Active  powerpc     mpc5xxx        -           -               mcc200              mcc200                               mcc200                                                                                                                            -
 Active  powerpc     mpc5xxx        -           -               mcc200              mcc200_COM12                         mcc200:CONSOLE_COM12                                                                                                              -
 Active  powerpc     mpc5xxx        -           -               mcc200              mcc200_COM12_highboot                mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000                                                                                     -
 Active  powerpc     mpc5xxx        -           -               mcc200              mcc200_COM12_highboot_SDRAM          mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM                                                                        -
 Active  powerpc     mpc5xxx        -           -               mcc200              mcc200_COM12_SDRAM                   mcc200:CONSOLE_COM12,MCC200_SDRAM                                                                                                 -
 Active  powerpc     mpc5xxx        -           -               mcc200              mcc200_highboot                      mcc200:SYS_TEXT_BASE=0xFFF00000                                                                                                   -
 Active  powerpc     mpc5xxx        -           -               mcc200              mcc200_highboot_SDRAM                mcc200:SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM                                                                                      -
 Active  powerpc     mpc5xxx        -           -               mcc200              mcc200_SDRAM                         mcc200:MCC200_SDRAM                                                                                                               -
 Active  powerpc     mpc5xxx        -           -               mcc200              prs200                               mcc200:PRS200,MCC200_SDRAM                                                                                                        -
 Active  powerpc     mpc5xxx        -           -               mcc200              prs200_DDR                           mcc200:PRS200                                                                                                                     -
 Active  powerpc     mpc5xxx        -           -               mcc200              prs200_highboot                      mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM                                                                               -
 Active  powerpc     mpc5xxx        -           -               mcc200              prs200_highboot_DDR                  mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000                                                                                            -
 Active  powerpc     mpc5xxx        -           -               pm520               PM520                                -                                                                                                                                 Josef Wagner <Wagner@Microsys.de>
 Active  powerpc     mpc5xxx        -           -               pm520               PM520_DDR                            PM520:MPC5200_DDR                                                                                                                 Josef Wagner <Wagner@Microsys.de>
 Active  powerpc     mpc5xxx        -           -               pm520               PM520_ROMBOOT                        PM520:BOOT_ROM                                                                                                                    Josef Wagner <Wagner@Microsys.de>
 Active  powerpc     mpc5xxx        -           -               pm520               PM520_ROMBOOT_DDR                    PM520:MPC5200_DDR,BOOT_ROM                                                                                                        Josef Wagner <Wagner@Microsys.de>
 Active  powerpc     mpc5xxx        -           -               total5200           Total5200                            Total5200:TOTAL5200_REV=1                                                                                                         -
 Active  powerpc     mpc5xxx        -           -               total5200           Total5200_lowboot                    Total5200:TOTAL5200_REV=1,SYS_TEXT_BASE=0xFE000000                                                                                -
 Active  powerpc     mpc5xxx        -           -               total5200           Total5200_Rev2                       Total5200:TOTAL5200_REV=2                                                                                                         -
 Active  powerpc     mpc5xxx        -           -               total5200           Total5200_Rev2_lowboot               Total5200:TOTAL5200_REV=2,SYS_TEXT_BASE=0xFE000000                                                                                -
 Active  powerpc     mpc5xxx        -           emk             top5200             EVAL5200                             TOP5200:EVAL5200                                                                                                                  Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
 Active  powerpc     mpc5xxx        -           emk             top5200             MINI5200                             TOP5200:MINI5200                                                                                                                  Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
 Active  powerpc     mpc5xxx        -           emk             top5200             TOP5200                              TOP5200:TOP5200                                                                                                                   Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
 Active  powerpc     mpc5xxx        -           esd             -                   cpci5200                             -                                                                                                                                 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 Active  powerpc     mpc5xxx        -           esd             -                   mecp5200                             -                                                                                                                                 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 Active  powerpc     mpc5xxx        -           esd             -                   pf5200                               -                                                                                                                                 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 Active  powerpc     mpc5xxx        -           ifm             o2dnt2              O2D                                  o2d                                                                                                                               Anatolij Gustschin <agust@denx.de>
 Active  powerpc     mpc5xxx        -           ifm             o2dnt2              O2D300                               o2d300                                                                                                                            Anatolij Gustschin <agust@denx.de>
 Active  powerpc     mpc5xxx        -           ifm             o2dnt2              O2DNT2                               o2dnt2                                                                                                                            Anatolij Gustschin <agust@denx.de>
 Active  powerpc     mpc5xxx        -           ifm             o2dnt2              O2DNT2_RAMBOOT                       o2dnt2:SYS_TEXT_BASE=0x00100000                                                                                                   Anatolij Gustschin <agust@denx.de>
 Active  powerpc     mpc5xxx        -           ifm             o2dnt2              O2I                                  o2i                                                                                                                               Anatolij Gustschin <agust@denx.de>
 Active  powerpc     mpc5xxx        -           ifm             o2dnt2              O2MNT                                o2mnt                                                                                                                             Anatolij Gustschin <agust@denx.de>
 Active  powerpc     mpc5xxx        -           ifm             o2dnt2              O2MNT_O2M110                         o2mnt:IFM_SENSOR_TYPE="O2M110"                                                                                                    Anatolij Gustschin <agust@denx.de>
 Active  powerpc     mpc5xxx        -           ifm             o2dnt2              O2MNT_O2M112                         o2mnt:IFM_SENSOR_TYPE="O2M112"                                                                                                    Anatolij Gustschin <agust@denx.de>
 Active  powerpc     mpc5xxx        -           ifm             o2dnt2              O2MNT_O2M113                         o2mnt:IFM_SENSOR_TYPE="O2M113"                                                                                                    Anatolij Gustschin <agust@denx.de>
 Active  powerpc     mpc5xxx        -           ifm             o2dnt2              O3DNT                                o3dnt                                                                                                                             Anatolij Gustschin <agust@denx.de>
 Active  powerpc     mpc5xxx        -           intercontrol    digsy_mtc           digsy_mtc                            -                                                                                                                                 Werner Pfister <Pfister_Werner@intercontrol.de>
 Active  powerpc     mpc5xxx        -           intercontrol    digsy_mtc           digsy_mtc_RAMBOOT                    digsy_mtc:SYS_TEXT_BASE=0x00100000                                                                                                Werner Pfister <Pfister_Werner@intercontrol.de>
 Active  powerpc     mpc5xxx        -           intercontrol    digsy_mtc           digsy_mtc_rev5                       digsy_mtc:DIGSY_REV5                                                                                                              Werner Pfister <Pfister_Werner@intercontrol.de>
 Active  powerpc     mpc5xxx        -           intercontrol    digsy_mtc           digsy_mtc_rev5_RAMBOOT               digsy_mtc:SYS_TEXT_BASE=0x00100000,DIGSY_REV5                                                                                     Werner Pfister <Pfister_Werner@intercontrol.de>
 Active  powerpc     mpc5xxx        -           manroland       -                   hmi1001                              -                                                                                                                                 -
 Active  powerpc     mpc5xxx        -           manroland       -                   mucmc52                              -                                                                                                                                 Heiko Schocher <hs@denx.de>
 Active  powerpc     mpc5xxx        -           manroland       -                   uc101                                -                                                                                                                                 Heiko Schocher <hs@denx.de>
 Active  powerpc     mpc5xxx        -           matrix_vision   mvbc_p              MVBC_P                               MVBC_P:MVBC_P                                                                                                                     Andre Schwarz <andre.schwarz@matrix-vision.de>
 Active  powerpc     mpc5xxx        -           matrix_vision   mvsmr               MVSMR                                -                                                                                                                                 Andre Schwarz <andre.schwarz@matrix-vision.de>
 Active  powerpc     mpc5xxx        -           phytec          pcm030              pcm030                               pcm030                                                                                                                            Jon Smirl <jonsmirl@gmail.com>
 Active  powerpc     mpc5xxx        -           phytec          pcm030              pcm030_LOWBOOT                       pcm030:SYS_TEXT_BASE=0xFF000000                                                                                                   Jon Smirl <jonsmirl@gmail.com>
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             aev                                  -                                                                                                                                 -
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             cam5200                              TQM5200:CAM5200,TQM5200S,TQM5200_B                                                                                                -
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             cam5200_niosflash                    TQM5200:CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH                                                                              -
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             charon                               charon                                                                                                                            Heiko Schocher <hs@denx.de>
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             fo300                                TQM5200:FO300                                                                                                                     -
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             MiniFAP                              TQM5200:MINIFAP                                                                                                                   -
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             TB5200                               -                                                                                                                                 -
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             TB5200_B                             TB5200:TQM5200_B                                                                                                                  -
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             TQM5200                              TQM5200:                                                                                                                          -
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             TQM5200_B                            TQM5200:TQM5200_B                                                                                                                 -
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             TQM5200_B_HIGHBOOT                   TQM5200:TQM5200_B,SYS_TEXT_BASE=0xFFF00000                                                                                        -
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             TQM5200_STK100                       TQM5200:STK52XX_REV100                                                                                                            -
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             TQM5200S                             TQM5200:TQM5200_B,TQM5200S                                                                                                        -
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             TQM5200S_HIGHBOOT                    TQM5200:TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000                                                                               -
 Active  powerpc     mpc824x        -           -               -                   utx8245                              -                                                                                                                                 Greg Allen <gallen@arlut.utexas.edu>
 Active  powerpc     mpc824x        -           -               a3000               A3000                                -                                                                                                                                 -
 Active  powerpc     mpc824x        -           -               cpc45               CPC45                                CPC45                                                                                                                             Josef Wagner <Wagner@Microsys.de>
 Active  powerpc     mpc824x        -           -               cpc45               CPC45_ROMBOOT                        CPC45:BOOT_ROM                                                                                                                    Josef Wagner <Wagner@Microsys.de>
 Active  powerpc     mpc824x        -           -               cu824               CU824                                -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc824x        -           -               eXalion             eXalion                              -                                                                                                                                 Torsten Demke <torsten.demke@fci.com>
 Active  powerpc     mpc824x        -           -               hidden_dragon       HIDDEN_DRAGON                        -                                                                                                                                 Yusdi Santoso <yusdi_santoso@adaptec.com>
 Active  powerpc     mpc824x        -           -               musenki             MUSENKI                              -                                                                                                                                 Jim Thompson <jim@musenki.com>
 Active  powerpc     mpc824x        -           -               mvblue              MVBLUE                               -                                                                                                                                 -
 Active  powerpc     mpc824x        -           -               sandpoint           Sandpoint8240                        -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc824x        -           -               sandpoint           Sandpoint8245                        -                                                                                                                                 Jim Thompson <jim@musenki.com>
 Active  powerpc     mpc824x        -           etin            -                   debris                               -                                                                                                                                 Sangmoon Kim <dogoil@etinsys.com>
 Active  powerpc     mpc824x        -           etin            -                   kvme080                              -                                                                                                                                 Sangmoon Kim <dogoil@etinsys.com>
 Active  powerpc     mpc8260        -           -               -                   atc                                  -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           -               -                   ep8260                               -                                                                                                                                 Frank Panno <fpanno@delphintech.com>
 Active  powerpc     mpc8260        -           -               -                   ep82xxm                              -                                                                                                                                 -
 Active  powerpc     mpc8260        -           -               -                   gw8260                               -                                                                                                                                 Oliver Brown <obrown@adventnetworks.com>
 Active  powerpc     mpc8260        -           -               -                   hymod                                -                                                                                                                                 Murray Jensen <Murray.Jensen@csiro.au>
 Active  powerpc     mpc8260        -           -               -                   ppmc8260                             -                                                                                                                                 Brad Kemp <Brad.Kemp@seranoa.com>
 Active  powerpc     mpc8260        -           -               -                   sacsng                               -                                                                                                                                 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
 Active  powerpc     mpc8260        -           -               cogent              cogent_mpc8260                       -                                                                                                                                 Murray Jensen <Murray.Jensen@csiro.au>
 Active  powerpc     mpc8260        -           -               cpu86               CPU86                                CPU86                                                                                                                             Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           -               cpu86               CPU86_ROMBOOT                        CPU86:BOOT_ROM                                                                                                                    Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           -               cpu87               CPU87                                CPU87                                                                                                                             -
 Active  powerpc     mpc8260        -           -               cpu87               CPU87_ROMBOOT                        CPU87:BOOT_ROM                                                                                                                    -
 Active  powerpc     mpc8260        -           -               ep8248              ep8248                               -                                                                                                                                 Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           -               ep8248              ep8248E                              ep8248                                                                                                                            Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           -               ids8247             IDS8247                              -                                                                                                                                 Heiko Schocher <hs@denx.de>
 Active  powerpc     mpc8260        -           -               iphase4539          IPHASE4539                           -                                                                                                                                 Wolfgang Grandegger <wg@denx.de>
 Active  powerpc     mpc8260        -           -               ispan               ISPAN                                -                                                                                                                                 Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           -               ispan               ISPAN_REVB                           ISPAN:SYS_REV_B                                                                                                                   Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           -               muas3001            muas3001                             -                                                                                                                                 Heiko Schocher <hs@denx.de>
 Active  powerpc     mpc8260        -           -               muas3001            muas3001_dev                         muas3001:MUAS_DEV_BOARD                                                                                                           Heiko Schocher <hs@denx.de>
 Active  powerpc     mpc8260        -           -               pm826               PM825                                PM826:PCI,SYS_TEXT_BASE=0xFF000000                                                                                                Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           -               pm826               PM825_BIGFLASH                       PM826:PCI,FLASH_32MB,SYS_TEXT_BASE=0x40000000                                                                                     Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           -               pm826               PM825_ROMBOOT                        PM826:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000                                                                                       Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           -               pm826               PM825_ROMBOOT_BIGFLASH               PM826:PCI,BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000                                                                            Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           -               pm826               PM826                                PM826:SYS_TEXT_BASE=0xFF000000                                                                                                    Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           -               pm826               PM826_BIGFLASH                       PM826:FLASH_32MB,SYS_TEXT_BASE=0x40000000                                                                                         Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           -               pm826               PM826_ROMBOOT                        PM826:BOOT_ROM,SYS_TEXT_BASE=0xFF800000                                                                                           Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           -               pm826               PM826_ROMBOOT_BIGFLASH               PM826:BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000                                                                                Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           -               pm828               PM828                                PM828                                                                                                                             -
 Active  powerpc     mpc8260        -           -               pm828               PM828_PCI                            PM828:PCI                                                                                                                         -
 Active  powerpc     mpc8260        -           -               pm828               PM828_ROMBOOT                        PM828:BOOT_ROM,SYS_TEXT_BASE=0xFF800000                                                                                           -
 Active  powerpc     mpc8260        -           -               pm828               PM828_ROMBOOT_PCI                    PM828:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000                                                                                       -
 Active  powerpc     mpc8260        -           -               rattler             Rattler                              Rattler                                                                                                                           Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           -               rattler             Rattler8248                          Rattler:MPC8248                                                                                                                   Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           -               zpc1900             ZPC1900                              -                                                                                                                                 Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8260ADS                           MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS                                                                                             Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8260ADS_33MHz                     MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000                                                                         Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8260ADS_33MHz_lowboot             MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000                                                Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8260ADS_40MHz                     MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000                                                                         Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8260ADS_40MHz_lowboot             MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000                                                Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8260ADS_lowboot                   MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000                                                                    Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8272ADS                           MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS                                                                                             Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8272ADS_lowboot                   MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000                                                                    Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS                              MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS                                                                                             Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS-VR                           MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000                                                                         Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS-VR_lowboot                   MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000                                                Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS-ZU                           MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS                                                                                             Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS-ZU_66MHz                     MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000                                                                         Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS-ZU_66MHz_lowboot             MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000                                                Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS-ZU_lowboot                   MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000                                                                    Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS_lowboot                      MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000                                                                    Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           freescale       mpc8266ads          MPC8266ADS                           -                                                                                                                                 Rune Torgersen <runet@innovsys.com>
 Active  powerpc     mpc8260        -           funkwerk        vovpn-gw            VoVPN-GW_66MHz                       VoVPN-GW:CLKIN_66MHz                                                                                                              -
 Active  powerpc     mpc8260        -           keymile         km82xx              mgcoge                               km82xx:MGCOGE                                                                                                                     Holger Brunck <holger.brunck@keymile.com>
 Active  powerpc     mpc8260        -           keymile         km82xx              mgcoge3ne                            km82xx:MGCOGE3NE                                                                                                                  Holger Brunck <holger.brunck@keymile.com>
 Active  powerpc     mpc8260        -           tqc             tqm8260             TQM8255_AA                           TQM8260:MPC8255,300MHz                                                                                                            Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           tqc             tqm8260             TQM8260_AA                           TQM8260:MPC8260,200MHz                                                                                                            Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           tqc             tqm8260             TQM8260_AB                           TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x                                                                                       Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           tqc             tqm8260             TQM8260_AC                           TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x                                                                                       Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           tqc             tqm8260             TQM8260_AD                           TQM8260:MPC8260,300MHz,BUSMODE_60x                                                                                                Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           tqc             tqm8260             TQM8260_AE                           TQM8260:MPC8260,266MHz                                                                                                            Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           tqc             tqm8260             TQM8260_AF                           TQM8260:MPC8260,300MHz,BUSMODE_60x                                                                                                Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           tqc             tqm8260             TQM8260_AG                           TQM8260:MPC8260,300MHz                                                                                                            Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           tqc             tqm8260             TQM8260_AH                           TQM8260:MPC8260,300MHz,L2_CACHE,BUSMODE_60x                                                                                       Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           tqc             tqm8260             TQM8260_AI                           TQM8260:MPC8260,300MHz,BUSMODE_60x                                                                                                Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           tqc             tqm8260             TQM8265_AA                           TQM8260:MPC8265,300MHz,BUSMODE_60x                                                                                                Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           tqc             tqm8272             TQM8272                              -                                                                                                                                 -
 Active  powerpc     mpc83xx        -           -               -                   mpc8308_p1m                          -                                                                                                                                 Ilya Yanok <yanok@emcraft.com>
 Active  powerpc     mpc83xx        -           -               sbc8349             sbc8349                              sbc8349                                                                                                                           Paul Gortmaker <paul.gortmaker@windriver.com>
 Active  powerpc     mpc83xx        -           -               sbc8349             sbc8349_PCI_33                       sbc8349:PCI,PCI_33M                                                                                                               Paul Gortmaker <paul.gortmaker@windriver.com>
 Active  powerpc     mpc83xx        -           -               sbc8349             sbc8349_PCI_66                       sbc8349:PCI,PCI_66M                                                                                                               Paul Gortmaker <paul.gortmaker@windriver.com>
 Active  powerpc     mpc83xx        -           -               ve8313              ve8313                               -                                                                                                                                 Heiko Schocher <hs@denx.de>
 Active  powerpc     mpc83xx        -           esd             vme8349             caddy2                               vme8349:CADDY2                                                                                                                    Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 Active  powerpc     mpc83xx        -           esd             vme8349             vme8349                              vme8349                                                                                                                           Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8308rdb          MPC8308RDB                           -                                                                                                                                 Ilya Yanok <yanok@emcraft.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8313erdb         MPC8313ERDB_33                       MPC8313ERDB:SYS_33MHZ                                                                                                             -
 Active  powerpc     mpc83xx        -           freescale       mpc8313erdb         MPC8313ERDB_66                       MPC8313ERDB:SYS_66MHZ                                                                                                             -
 Active  powerpc     mpc83xx        -           freescale       mpc8313erdb         MPC8313ERDB_NAND_33                  MPC8313ERDB:SYS_33MHZ,NAND                                                                                                        -
 Active  powerpc     mpc83xx        -           freescale       mpc8313erdb         MPC8313ERDB_NAND_66                  MPC8313ERDB:SYS_66MHZ,NAND                                                                                                        -
 Active  powerpc     mpc83xx        -           freescale       mpc8315erdb         MPC8315ERDB                          MPC8315ERDB                                                                                                                       Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8315erdb         MPC8315ERDB_NAND                     MPC8315ERDB:NAND_U_BOOT                                                                                                           Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8323erdb         MPC8323ERDB                          -                                                                                                                                 Michael Barkowski <michael.barkowski@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc832xemds         MPC832XEMDS                          MPC832XEMDS:                                                                                                                      Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc832xemds         MPC832XEMDS_ATM                      MPC832XEMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1                                                                                         Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc832xemds         MPC832XEMDS_HOST_33                  MPC832XEMDS:PCI,PCI_33M,PQ_MDS_PIB=1                                                                                              Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc832xemds         MPC832XEMDS_HOST_66                  MPC832XEMDS:PCI,PCI_66M,PQ_MDS_PIB=1                                                                                              Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc832xemds         MPC832XEMDS_SLAVE                    MPC832XEMDS:PCI,PCISLAVE                                                                                                          Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8349emds         MPC8349EMDS                          -                                                                                                                                 Kim Phillips <kim.phillips@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8349itx          MPC8349ITX                           MPC8349ITX:MPC8349ITX                                                                                                             -
 Active  powerpc     mpc83xx        -           freescale       mpc8349itx          MPC8349ITX_LOWBOOT                   MPC8349ITX:MPC8349ITX,SYS_TEXT_BASE=0xFE000000                                                                                    -
 Active  powerpc     mpc83xx        -           freescale       mpc8349itx          MPC8349ITXGP                         MPC8349ITX:MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000                                                                                  -
 Active  powerpc     mpc83xx        -           freescale       mpc8360emds         MPC8360EMDS_33                       MPC8360EMDS:CLKIN_33MHZ                                                                                                           Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8360emds         MPC8360EMDS_33_ATM                   MPC8360EMDS:CLKIN_33MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1                                                                             Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8360emds         MPC8360EMDS_33_HOST_33               MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_33M,PQ_MDS_PIB=1                                                                                  Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8360emds         MPC8360EMDS_33_HOST_66               MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_66M,PQ_MDS_PIB=1                                                                                  Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8360emds         MPC8360EMDS_33_SLAVE                 MPC8360EMDS:CLKIN_33MHZ,PCI,PCISLAVE                                                                                              Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8360emds         MPC8360EMDS_66                       MPC8360EMDS:CLKIN_66MHZ                                                                                                           Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8360emds         MPC8360EMDS_66_ATM                   MPC8360EMDS:CLKIN_66MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1                                                                             Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8360emds         MPC8360EMDS_66_HOST_33               MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1                                                                                  Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8360emds         MPC8360EMDS_66_HOST_66               MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1                                                                                  Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8360emds         MPC8360EMDS_66_SLAVE                 MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE                                                                                              Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8360erdk         MPC8360ERDK                          MPC8360ERDK                                                                                                                       Anton Vorontsov <avorontsov@ru.mvista.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8360erdk         MPC8360ERDK_33                       MPC8360ERDK:CLKIN_33MHZ                                                                                                           Anton Vorontsov <avorontsov@ru.mvista.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8360erdk         MPC8360ERDK_66                       MPC8360ERDK                                                                                                                       Anton Vorontsov <avorontsov@ru.mvista.com>
 Active  powerpc     mpc83xx        -           freescale       mpc837xemds         MPC837XEMDS                          MPC837XEMDS                                                                                                                       Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc837xemds         MPC837XEMDS_HOST                     MPC837XEMDS:PCI                                                                                                                   Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc837xerdb         MPC837XERDB                          -                                                                                                                                 Joe D'Abbraccio <ljd015@freescale.com>
 Active  powerpc     mpc83xx        -           keymile         km83xx              kmcoge5ne                            km8360:KMCOGE5NE                                                                                                                  Holger Brunck <holger.brunck@keymile.com>
 Active  powerpc     mpc83xx        -           keymile         km83xx              kmeter1                              km8360:KMETER1                                                                                                                    Holger Brunck <holger.brunck@keymile.com>
 Active  powerpc     mpc83xx        -           keymile         km83xx              kmopti2                              tuxx1:KMOPTI2                                                                                                                     Holger Brunck <holger.brunck@keymile.com>
 Active  powerpc     mpc83xx        -           keymile         km83xx              kmsupx5                              tuxx1:KMSUPX5                                                                                                                     Heiko Schocher <hs@denx.de>
 Active  powerpc     mpc83xx        -           keymile         km83xx              kmvect1                              suvd3:KMVECT1                                                                                                                     Holger Brunck <holger.brunck@keymile.com>
 Active  powerpc     mpc83xx        -           keymile         km83xx              suvd3                                suvd3:SUVD3                                                                                                                       Holger Brunck <holger.brunck@keymile.com>
 Active  powerpc     mpc83xx        -           keymile         km83xx              tuge1                                tuxx1:TUGE1                                                                                                                       Holger Brunck <holger.brunck@keymile.com>
 Active  powerpc     mpc83xx        -           keymile         km83xx              tuxx1                                tuxx1:TUXX1                                                                                                                       Holger Brunck <holger.brunck@keymile.com>
 Active  powerpc     mpc83xx        -           matrix_vision   mergerbox           MERGERBOX                            -                                                                                                                                 Andre Schwarz <andre.schwarz@matrix-vision.de>
 Active  powerpc     mpc83xx        -           matrix_vision   mvblm7              MVBLM7                               -                                                                                                                                 Andre Schwarz <andre.schwarz@matrix-vision.de>
 Active  powerpc     mpc83xx        -           sheldon         simpc8313           SIMPC8313_LP                         SIMPC8313:NAND_LP                                                                                                                 Ron Madrid <info@sheldoninst.com>
 Active  powerpc     mpc83xx        -           sheldon         simpc8313           SIMPC8313_SP                         SIMPC8313:NAND_SP                                                                                                                 Ron Madrid <info@sheldoninst.com>
 Active  powerpc     mpc83xx        -           tqc             tqm834x             TQM834x                              -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           -               sbc8548             sbc8548                              sbc8548                                                                                                                           Paul Gortmaker <paul.gortmaker@windriver.com>
 Active  powerpc     mpc85xx        -           -               sbc8548             sbc8548_PCI_33                       sbc8548:PCI,33                                                                                                                    Paul Gortmaker <paul.gortmaker@windriver.com>
 Active  powerpc     mpc85xx        -           -               sbc8548             sbc8548_PCI_33_PCIE                  sbc8548:PCI,33,PCIE                                                                                                               Paul Gortmaker <paul.gortmaker@windriver.com>
 Active  powerpc     mpc85xx        -           -               sbc8548             sbc8548_PCI_66                       sbc8548:PCI,66                                                                                                                    Paul Gortmaker <paul.gortmaker@windriver.com>
 Active  powerpc     mpc85xx        -           -               sbc8548             sbc8548_PCI_66_PCIE                  sbc8548:PCI,66,PCIE                                                                                                               Paul Gortmaker <paul.gortmaker@windriver.com>
 Active  powerpc     mpc85xx        -           -               socrates            socrates                             -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           exmeritus       hww1u1a             HWW1U1A                              -                                                                                                                                 Kyle Moffett <Kyle.D.Moffett@boeing.com>
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4420QDS                             B4860QDS:PPC_B4420                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4420QDS_NAND                        B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000                                                                      -
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4420QDS_SPIFLASH                    B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS                             B4860QDS:PPC_B4860                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_NAND                        B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000                                                                      -
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_SPIFLASH                    B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_SRIO_PCIE_BOOT              B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       bsc9131rdb          BSC9131RDB_NAND                      BSC9131RDB:BSC9131RDB,NAND                                                                                                        Poonam Aggrwal <poonam.aggrwal@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       bsc9131rdb          BSC9131RDB_NAND_SYSCLK100            BSC9131RDB:BSC9131RDB,NAND,SYS_CLK_100                                                                                            Poonam Aggrwal <poonam.aggrwal@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       bsc9131rdb          BSC9131RDB_SPIFLASH                  BSC9131RDB:BSC9131RDB,SPIFLASH                                                                                                    Poonam Aggrwal <poonam.aggrwal@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       bsc9131rdb          BSC9131RDB_SPIFLASH_SYSCLK100        BSC9131RDB:BSC9131RDB,SPIFLASH,SYS_CLK_100                                                                                        Poonam Aggrwal <poonam.aggrwal@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       bsc9132qds          BSC9132QDS_NAND_DDRCLK100            BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_100                                                                                    Naveen Burmi <NaveenBurmi@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       bsc9132qds          BSC9132QDS_NAND_DDRCLK133            BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_133                                                                                    Naveen Burmi <NaveenBurmi@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       bsc9132qds          BSC9132QDS_NOR_DDRCLK100             BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100                                                                                         Naveen Burmi <NaveenBurmi@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       bsc9132qds          BSC9132QDS_NOR_DDRCLK133             BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133                                                                                         Naveen Burmi <NaveenBurmi@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       bsc9132qds          BSC9132QDS_SDCARD_DDRCLK100          BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100                                                                                  Naveen Burmi <NaveenBurmi@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       bsc9132qds          BSC9132QDS_SDCARD_DDRCLK133          BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133                                                                                  Naveen Burmi <NaveenBurmi@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       bsc9132qds          BSC9132QDS_SPIFLASH_DDRCLK100        BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100                                                                                Naveen Burmi <NaveenBurmi@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       bsc9132qds          BSC9132QDS_SPIFLASH_DDRCLK133        BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133                                                                                Naveen Burmi <NaveenBurmi@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       c29xpcie            C29XPCIE                             C29XPCIE:C29XPCIE,36BIT                                                                                                           Po Liu <po.liu@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       c29xpcie            C29XPCIE_SPIFLASH                    C29XPCIE:C29XPCIE,36BIT,SPIFLASH                                                                                                  Po Liu <po.liu@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P3041DS                              -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P3041DS_NAND                         P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P3041DS_SDCARD                       P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000                                                                               -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P3041DS_SECURE_BOOT                  P3041DS:SECURE_BOOT                                                                                                               -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P3041DS_SPIFLASH                     P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000                                                                             -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P3041DS_SRIO_PCIE_BOOT               P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000                                                                             -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P4080DS                              -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P4080DS_SDCARD                       P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000                                                                               -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P4080DS_SECURE_BOOT                  P4080DS:SECURE_BOOT                                                                                                               -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P4080DS_SPIFLASH                     P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000                                                                             -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P4080DS_SRIO_PCIE_BOOT               P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000                                                                             -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5020DS                              -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5020DS_NAND                         P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5020DS_SDCARD                       P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000                                                                               -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5020DS_SECURE_BOOT                  P5020DS:SECURE_BOOT                                                                                                               -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5020DS_SPIFLASH                     P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000                                                                             -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5020DS_SRIO_PCIE_BOOT               P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000                                                                             -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5040DS                              -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5040DS_NAND                         P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5040DS_SDCARD                       P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000                                                                               -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5040DS_SPIFLASH                     P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000                                                                             -
 Active  powerpc     mpc85xx        -           freescale       mpc8536ds           MPC8536DS                            MPC8536DS                                                                                                                         -
 Active  powerpc     mpc85xx        -           freescale       mpc8536ds           MPC8536DS_36BIT                      MPC8536DS:36BIT                                                                                                                   -
 Active  powerpc     mpc85xx        -           freescale       mpc8536ds           MPC8536DS_NAND                       MPC8536DS:NAND                                                                                                                    -
 Active  powerpc     mpc85xx        -           freescale       mpc8536ds           MPC8536DS_SDCARD                     MPC8536DS:SDCARD                                                                                                                  -
 Active  powerpc     mpc85xx        -           freescale       mpc8536ds           MPC8536DS_SPIFLASH                   MPC8536DS:SPIFLASH                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       mpc8540ads          MPC8540ADS                           -                                                                                                                                 Kumar Gala <kumar.gala@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       mpc8541cds          MPC8541CDS                           MPC8541CDS                                                                                                                        Kumar Gala <kumar.gala@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       mpc8541cds          MPC8541CDS_legacy                    MPC8541CDS:LEGACY                                                                                                                 Kumar Gala <kumar.gala@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       mpc8544ds           MPC8544DS                            -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       mpc8548cds          MPC8548CDS                           MPC8548CDS                                                                                                                        -
 Active  powerpc     mpc85xx        -           freescale       mpc8548cds          MPC8548CDS_36BIT                     MPC8548CDS:36BIT                                                                                                                  -
 Active  powerpc     mpc85xx        -           freescale       mpc8548cds          MPC8548CDS_legacy                    MPC8548CDS:LEGACY                                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       mpc8555cds          MPC8555CDS                           MPC8555CDS                                                                                                                        Kumar Gala <kumar.gala@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       mpc8555cds          MPC8555CDS_legacy                    MPC8555CDS:LEGACY                                                                                                                 Kumar Gala <kumar.gala@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       mpc8560ads          MPC8560ADS                           -                                                                                                                                 Kumar Gala <kumar.gala@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       mpc8568mds          MPC8568MDS                           -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       mpc8569mds          MPC8569MDS                           MPC8569MDS                                                                                                                        -
 Active  powerpc     mpc85xx        -           freescale       mpc8569mds          MPC8569MDS_ATM                       MPC8569MDS:ATM                                                                                                                    -
 Active  powerpc     mpc85xx        -           freescale       mpc8569mds          MPC8569MDS_NAND                      MPC8569MDS:NAND                                                                                                                   -
 Active  powerpc     mpc85xx        -           freescale       mpc8572ds           MPC8572DS                            MPC8572DS                                                                                                                         -
 Active  powerpc     mpc85xx        -           freescale       mpc8572ds           MPC8572DS_36BIT                      MPC8572DS:36BIT                                                                                                                   -
 Active  powerpc     mpc85xx        -           freescale       mpc8572ds           MPC8572DS_NAND                       MPC8572DS:NAND                                                                                                                    -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_NAND               P1010RDB:P1010RDB_PA,36BIT,NAND                                                                                                   -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_NAND_SECBOOT       P1010RDB:P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT                                                                               -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_NOR                P1010RDB:P1010RDB_PA,36BIT                                                                                                        -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_NOR_SECBOOT        P1010RDB:P1010RDB_PA,36BIT,SECURE_BOOT                                                                                            -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_SDCARD             P1010RDB:P1010RDB_PA,36BIT,SDCARD                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_SPIFLASH           P1010RDB:P1010RDB_PA,36BIT,SPIFLASH                                                                                               -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_SPIFLASH_SECBOOT   P1010RDB:P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT                                                                                   -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_NAND                     P1010RDB:P1010RDB_PA,NAND                                                                                                         -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_NAND_SECBOOT             P1010RDB:P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT                                                                                     -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_NOR                      P1010RDB:P1010RDB_PA                                                                                                              -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_NOR_SECBOOT              P1010RDB:P1010RDB_PA,SECURE_BOOT                                                                                                  -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_SDCARD                   P1010RDB:P1010RDB_PA,SDCARD                                                                                                       -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_SPIFLASH                 P1010RDB:P1010RDB_PA,SPIFLASH                                                                                                     -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_SPIFLASH_SECBOOT         P1010RDB:P1010RDB_PA,SPIFLASH,SECURE_BOOT                                                                                         -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_NAND               P1010RDB:P1010RDB_PB,36BIT,NAND                                                                                                   -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_NAND_SECBOOT       P1010RDB:P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT                                                                               -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_NOR                P1010RDB:P1010RDB_PB,36BIT                                                                                                        -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_NOR_SECBOOT        P1010RDB:P1010RDB_PB,36BIT,SECURE_BOOT                                                                                            -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_SDCARD             P1010RDB:P1010RDB_PB,36BIT,SDCARD                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_SPIFLASH           P1010RDB:P1010RDB_PB,36BIT,SPIFLASH                                                                                               -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_SPIFLASH_SECBOOT   P1010RDB:P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT                                                                                   -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_NAND                     P1010RDB:P1010RDB_PB,NAND                                                                                                         -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_NAND_SECBOOT             P1010RDB:P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT                                                                                     -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_NOR                      P1010RDB:P1010RDB_PB                                                                                                              -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_NOR_SECBOOT              P1010RDB:P1010RDB_PB,SECURE_BOOT                                                                                                  -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_SDCARD                   P1010RDB:P1010RDB_PB,SDCARD                                                                                                       -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_SPIFLASH                 P1010RDB:P1010RDB_PB,SPIFLASH                                                                                                     -
 Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_SPIFLASH_SECBOOT         P1010RDB:P1010RDB_PB,SPIFLASH,SECURE_BOOT                                                                                         -
 Active  powerpc     mpc85xx        -           freescale       p1022ds             P1022DS                              -                                                                                                                                 Timur Tabi <timur@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       p1022ds             P1022DS_36BIT                        P1022DS:36BIT                                                                                                                     Timur Tabi <timur@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       p1022ds             P1022DS_36BIT_NAND                   P1022DS:36BIT,NAND                                                                                                                Timur Tabi <timur@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       p1022ds             P1022DS_36BIT_SDCARD                 P1022DS:36BIT,SDCARD                                                                                                              Timur Tabi <timur@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       p1022ds             P1022DS_36BIT_SPIFLASH               P1022DS:36BIT,SPIFLASH                                                                                                            Timur Tabi <timur@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       p1022ds             P1022DS_NAND                         P1022DS:NAND                                                                                                                      Timur Tabi <timur@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       p1022ds             P1022DS_SDCARD                       P1022DS:SDCARD                                                                                                                    Timur Tabi <timur@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       p1022ds             P1022DS_SPIFLASH                     P1022DS:SPIFLASH                                                                                                                  Timur Tabi <timur@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       p1023rdb            P1023RDB                             P1023RDB                                                                                                                          -
 Active  powerpc     mpc85xx        -           freescale       p1023rds            P1023RDS                             P1023RDS                                                                                                                          Roy Zang <tie-fei.zang@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       p1023rds            P1023RDS_NAND                        P1023RDS:NAND                                                                                                                     Roy Zang <tie-fei.zang@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P1011RDB                             P1_P2_RDB:P1011RDB                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P1011RDB_36BIT                       P1_P2_RDB:P1011RDB,36BIT                                                                                                          -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P1011RDB_36BIT_SDCARD                P1_P2_RDB:P1011RDB,36BIT,SDCARD                                                                                                   -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P1011RDB_36BIT_SPIFLASH              P1_P2_RDB:P1011RDB,36BIT,SPIFLASH                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P1011RDB_NAND                        P1_P2_RDB:P1011RDB,NAND                                                                                                           -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P1011RDB_SDCARD                      P1_P2_RDB:P1011RDB,SDCARD                                                                                                         -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P1011RDB_SPIFLASH                    P1_P2_RDB:P1011RDB,SPIFLASH                                                                                                       -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P1020RDB                             P1_P2_RDB:P1020RDB                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P1020RDB_36BIT                       P1_P2_RDB:P1020RDB,36BIT                                                                                                          -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P1020RDB_36BIT_SDCARD                P1_P2_RDB:P1020RDB,36BIT,SDCARD                                                                                                   -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P1020RDB_36BIT_SPIFLASH              P1_P2_RDB:P1020RDB,36BIT,SPIFLASH                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P1020RDB_NAND                        P1_P2_RDB:P1020RDB,NAND                                                                                                           -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P1020RDB_SDCARD                      P1_P2_RDB:P1020RDB,SDCARD                                                                                                         -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P1020RDB_SPIFLASH                    P1_P2_RDB:P1020RDB,SPIFLASH                                                                                                       -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P2010RDB                             P1_P2_RDB:P2010RDB                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P2010RDB_36BIT                       P1_P2_RDB:P2010RDB,36BIT                                                                                                          -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P2010RDB_36BIT_SDCARD                P1_P2_RDB:P2010RDB,36BIT,SDCARD                                                                                                   -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P2010RDB_36BIT_SPIFLASH              P1_P2_RDB:P2010RDB,36BIT,SPIFLASH                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P2010RDB_NAND                        P1_P2_RDB:P2010RDB,NAND                                                                                                           -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P2010RDB_SDCARD                      P1_P2_RDB:P2010RDB,SDCARD                                                                                                         -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P2010RDB_SPIFLASH                    P1_P2_RDB:P2010RDB,SPIFLASH                                                                                                       -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P2020RDB                             P1_P2_RDB:P2020RDB                                                                                                                Poonam Aggrwal <poonam.aggrwal@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P2020RDB_36BIT                       P1_P2_RDB:P2020RDB,36BIT                                                                                                          -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P2020RDB_36BIT_SDCARD                P1_P2_RDB:P2020RDB,36BIT,SDCARD                                                                                                   -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P2020RDB_36BIT_SPIFLASH              P1_P2_RDB:P2020RDB,36BIT,SPIFLASH                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P2020RDB_NAND                        P1_P2_RDB:P2020RDB,NAND                                                                                                           -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P2020RDB_SDCARD                      P1_P2_RDB:P2020RDB,SDCARD                                                                                                         -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P2020RDB_SPIFLASH                    P1_P2_RDB:P2020RDB,SPIFLASH                                                                                                       -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1020MBG-PC                          p1_p2_rdb_pc:P1020MBG                                                                                                             -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1020MBG-PC_36BIT                    p1_p2_rdb_pc:P1020MBG,36BIT                                                                                                       -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1020MBG-PC_36BIT_SDCARD             p1_p2_rdb_pc:P1020MBG,SDCARD,36BIT                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1020MBG-PC_SDCARD                   p1_p2_rdb_pc:P1020MBG,SDCARD                                                                                                      -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1020RDB-PC                          p1_p2_rdb_pc:P1020RDB_PC                                                                                                          -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1020RDB-PC_36BIT                    p1_p2_rdb_pc:P1020RDB_PC,36BIT                                                                                                    -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1020RDB-PC_36BIT_NAND               p1_p2_rdb_pc:P1020RDB_PC,36BIT,NAND                                                                                               -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1020RDB-PC_36BIT_SDCARD             p1_p2_rdb_pc:P1020RDB_PC,36BIT,SDCARD                                                                                             -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1020RDB-PC_36BIT_SPIFLASH           p1_p2_rdb_pc:P1020RDB_PC,36BIT,SPIFLASH                                                                                           -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1020RDB-PC_NAND                     p1_p2_rdb_pc:P1020RDB_PC,NAND                                                                                                     -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1020RDB-PC_SDCARD                   p1_p2_rdb_pc:P1020RDB_PC,SDCARD                                                                                                   -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1020RDB-PC_SPIFLASH                 p1_p2_rdb_pc:P1020RDB_PC,SPIFLASH                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1020RDB-PD                          p1_p2_rdb_pc:P1020RDB_PD                                                                                                          -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1020RDB-PD_NAND                     p1_p2_rdb_pc:P1020RDB_PD,NAND                                                                                                     -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1020RDB-PD_SDCARD                   p1_p2_rdb_pc:P1020RDB_PD,SDCARD                                                                                                   -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1020RDB-PD_SPIFLASH                 p1_p2_rdb_pc:P1020RDB_PD,SPIFLASH                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1020UTM-PC                          p1_p2_rdb_pc:P1020UTM                                                                                                             -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1020UTM-PC_36BIT                    p1_p2_rdb_pc:P1020UTM,36BIT                                                                                                       -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1020UTM-PC_36BIT_SDCARD             p1_p2_rdb_pc:P1020UTM,36BIT,SDCARD                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1020UTM-PC_SDCARD                   p1_p2_rdb_pc:P1020UTM,SDCARD                                                                                                      -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1021RDB-PC                          p1_p2_rdb_pc:P1021RDB                                                                                                             -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1021RDB-PC_36BIT                    p1_p2_rdb_pc:P1021RDB,36BIT                                                                                                       -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1021RDB-PC_36BIT_NAND               p1_p2_rdb_pc:P1021RDB,36BIT,NAND                                                                                                  -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1021RDB-PC_36BIT_SDCARD             p1_p2_rdb_pc:P1021RDB,36BIT,SDCARD                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1021RDB-PC_36BIT_SPIFLASH           p1_p2_rdb_pc:P1021RDB,36BIT,SPIFLASH                                                                                              -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1021RDB-PC_NAND                     p1_p2_rdb_pc:P1021RDB,NAND                                                                                                        -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1021RDB-PC_SDCARD                   p1_p2_rdb_pc:P1021RDB,SDCARD                                                                                                      -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1021RDB-PC_SPIFLASH                 p1_p2_rdb_pc:P1021RDB,SPIFLASH                                                                                                    -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1024RDB                             p1_p2_rdb_pc:P1024RDB                                                                                                             -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1024RDB_36BIT                       p1_p2_rdb_pc:P1024RDB,36BIT                                                                                                       -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1024RDB_NAND                        p1_p2_rdb_pc:P1024RDB,NAND                                                                                                        -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1024RDB_SDCARD                      p1_p2_rdb_pc:P1024RDB,SDCARD                                                                                                      -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1024RDB_SPIFLASH                    p1_p2_rdb_pc:P1024RDB,SPIFLASH                                                                                                    -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1025RDB                             p1_p2_rdb_pc:P1025RDB                                                                                                             -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1025RDB_36BIT                       p1_p2_rdb_pc:P1025RDB,36BIT                                                                                                       -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1025RDB_NAND                        p1_p2_rdb_pc:P1025RDB,NAND                                                                                                        -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1025RDB_SDCARD                      p1_p2_rdb_pc:P1025RDB,SDCARD                                                                                                      -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P1025RDB_SPIFLASH                    p1_p2_rdb_pc:P1025RDB,SPIFLASH                                                                                                    -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P2020RDB-PC                          p1_p2_rdb_pc:P2020RDB                                                                                                             -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P2020RDB-PC_36BIT                    p1_p2_rdb_pc:P2020RDB,36BIT                                                                                                       -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P2020RDB-PC_36BIT_NAND               p1_p2_rdb_pc:P2020RDB,36BIT,NAND                                                                                                  -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P2020RDB-PC_36BIT_SDCARD             p1_p2_rdb_pc:P2020RDB,36BIT,SDCARD                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P2020RDB-PC_36BIT_SPIFLASH           p1_p2_rdb_pc:P2020RDB,36BIT,SPIFLASH                                                                                              -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P2020RDB-PC_NAND                     p1_p2_rdb_pc:P2020RDB,NAND                                                                                                        -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P2020RDB-PC_SDCARD                   p1_p2_rdb_pc:P2020RDB,SDCARD                                                                                                      -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb_pc        P2020RDB-PC_SPIFLASH                 p1_p2_rdb_pc:P2020RDB,SPIFLASH                                                                                                    -
 Active  powerpc     mpc85xx        -           freescale       p1_twr              TWR-P1025                            p1_twr:TWR_P1025                                                                                                                  -
 Active  powerpc     mpc85xx        -           freescale       p2020come           P2020COME_SDCARD                     P2020COME:SDCARD                                                                                                                  Ira W. Snyder <iws@ovro.caltech.edu>
 Active  powerpc     mpc85xx        -           freescale       p2020come           P2020COME_SPIFLASH                   P2020COME:SPIFLASH                                                                                                                Ira W. Snyder <iws@ovro.caltech.edu>
 Active  powerpc     mpc85xx        -           freescale       p2020ds             P2020DS                              -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       p2020ds             P2020DS_36BIT                        P2020DS:36BIT                                                                                                                     -
 Active  powerpc     mpc85xx        -           freescale       p2020ds             P2020DS_DDR2                         P2020DS:DDR2                                                                                                                      -
 Active  powerpc     mpc85xx        -           freescale       p2020ds             P2020DS_SDCARD                       P2020DS:SDCARD                                                                                                                    -
 Active  powerpc     mpc85xx        -           freescale       p2020ds             P2020DS_SPIFLASH                     P2020DS:SPIFLASH                                                                                                                  -
 Active  powerpc     mpc85xx        -           freescale       p2041rdb            P2041RDB                             -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       p2041rdb            P2041RDB_NAND                        P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000                                                                                -
 Active  powerpc     mpc85xx        -           freescale       p2041rdb            P2041RDB_SDCARD                      P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000                                                                              -
 Active  powerpc     mpc85xx        -           freescale       p2041rdb            P2041RDB_SECURE_BOOT                 P2041RDB:SECURE_BOOT                                                                                                              -
 Active  powerpc     mpc85xx        -           freescale       p2041rdb            P2041RDB_SPIFLASH                    P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000                                                                            -
 Active  powerpc     mpc85xx        -           freescale       p2041rdb            P2041RDB_SRIO_PCIE_BOOT              P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000                                                                            -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS                             T4240QDS:PPC_T4160                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS_SDCARD                      T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000                                                                    -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS_SPIFLASH                    T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4240EMU                             T4240EMU:PPC_T4240                                                                                                                York Sun <yorksun@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS                             T4240QDS:PPC_T4240                                                                                                                -
+Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_NAND	                T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000                                                                      -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_SDCARD                      T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000                                                                    -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_SPIFLASH                    T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_SRIO_PCIE_BOOT              T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t1040qds            T1040QDS                             T1040QDS:PPC_T1040                                                                                                             Poonam Aggrwal <poonam.aggrwal@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       t104xrdb            T1040RDB                             T1040RDB:PPC_T1040                                                                                                             Poonam Aggrwal  <poonam.aggrwal@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       t104xrdb            T1042RDB_PI                          T1042RDB_PI:PPC_T1042                                                                                                          Poonam Aggrwal  <poonam.aggrwal@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       t2080qds            T2080QDS              T2080QDS:PPC_T2080
 Active  powerpc     mpc85xx        -           freescale       t2080qds            T2080QDS_SDCARD       T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
 Active  powerpc     mpc85xx        -           freescale       t2080qds            T2080QDS_SPIFLASH     T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
 Active  powerpc     mpc85xx        -           freescale       t2080qds            T2080QDS_NAND         T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
 Active  powerpc     mpc85xx        -           freescale       t2080qds            T2080QDS_SRIO_PCIE_BOOT  T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
 Active  powerpc     mpc85xx        -           gdsys           p1022               controlcenterd_36BIT_SDCARD          controlcenterd:36BIT,SDCARD                                                                                                       Dirk Eibach <eibach@gdsys.de>
 Active  powerpc     mpc85xx        -           gdsys           p1022               controlcenterd_36BIT_SDCARD_DEVELOP  controlcenterd:36BIT,SDCARD,DEVELOP                                                                                               Dirk Eibach <eibach@gdsys.de>
 Active  powerpc     mpc85xx        -           gdsys           p1022               controlcenterd_TRAILBLAZER           controlcenterd:TRAILBLAZER,SPIFLASH                                                                                               Dirk Eibach <eibach@gdsys.de>
 Active  powerpc     mpc85xx        -           gdsys           p1022               controlcenterd_TRAILBLAZER_DEVELOP   controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP                                                                                       Dirk Eibach <eibach@gdsys.de>
 Active  powerpc     mpc85xx        -           keymile         kmp204x             kmlion1                              kmp204x:KMLION1                                                                                                                   Valentin Longchamp <valentin.longchamp@keymile.com>
 Active  powerpc     mpc85xx        -           stx             stxgp3              stxgp3                               -                                                                                                                                 Dan Malek <dan@embeddedalley.com>
 Active  powerpc     mpc85xx        -           stx             stxssa              stxssa                               stxssa                                                                                                                            Dan Malek <dan@embeddedalley.com>
 Active  powerpc     mpc85xx        -           stx             stxssa              stxssa_4M                            stxssa:STXSSA_4M                                                                                                                  Dan Malek <dan@embeddedalley.com>
 Active  powerpc     mpc85xx        -           xes             -                   xpedite520x                          -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           xes             -                   xpedite537x                          -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           xes             -                   xpedite550x                          -                                                                                                                                 -
 Active  powerpc     mpc86xx        -           -               -                   sbc8641d                             -                                                                                                                                 Paul Gortmaker <paul.gortmaker@windriver.com>
 Active  powerpc     mpc86xx        -           freescale       mpc8610hpcd         MPC8610HPCD                          -                                                                                                                                 -
 Active  powerpc     mpc86xx        -           freescale       mpc8641hpcn         MPC8641HPCN                          MPC8641HPCN                                                                                                                       Kumar Gala <kumar.gala@freescale.com>
 Active  powerpc     mpc86xx        -           freescale       mpc8641hpcn         MPC8641HPCN_36BIT                    MPC8641HPCN:PHYS_64BIT                                                                                                            Kumar Gala <kumar.gala@freescale.com>
 Active  powerpc     mpc86xx        -           xes             -                   xpedite517x                          -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           -               -                   hermes                               -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           -               -                   lwmon                                -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           -               -                   quantum                              -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           -               -                   RRvision                             -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           -               -                   spc1920                              -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           -               -                   svm_sc8xx                            -                                                                                                                                 John Zhan <zhanz@sinovee.com>
 Active  powerpc     mpc8xx         -           -               -                   v37                                  -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           -               adder               Adder                                -                                                                                                                                 Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8xx         -           -               adder               Adder87x                             Adder                                                                                                                             Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8xx         -           -               adder               AdderII                              Adder:MPC852T                                                                                                                     Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8xx         -           -               adder               AdderUSB                             Adder                                                                                                                             Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8xx         -           -               cogent              cogent_mpc8xx                        -                                                                                                                                 Murray Jensen <Murray.Jensen@csiro.au>
 Active  powerpc     mpc8xx         -           -               esteem192e          ESTEEM192E                           -                                                                                                                                 Conn Clark <clark@esteem.com>
 Active  powerpc     mpc8xx         -           -               fads                MPC86xADS                            -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           -               fads                MPC885ADS                            -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           -               flagadm             FLAGADM                              -                                                                                                                                 Kári Davíðsson <kd@flaga.is>
 Active  powerpc     mpc8xx         -           -               gen860t             GEN860T                              -                                                                                                                                 Keith Outwater <Keith_Outwater@mvis.com>
 Active  powerpc     mpc8xx         -           -               gen860t             GEN860T_SC                           GEN860T:SC                                                                                                                        Keith Outwater <Keith_Outwater@mvis.com>
 Active  powerpc     mpc8xx         -           -               icu862              ICU862                               -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           -               icu862              ICU862_100MHz                        ICU862:100MHz                                                                                                                     Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           -               ip860               IP860                                -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           -               ivm                 IVML24                               IVML24:IVML24_16M                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           -               ivm                 IVML24_128                           IVML24:IVML24_32M                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           -               ivm                 IVML24_256                           IVML24:IVML24_64M                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           -               ivm                 IVMS8                                IVMS8:IVMS8_16M                                                                                                                   Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           -               ivm                 IVMS8_128                            IVMS8:IVMS8_32M                                                                                                                   Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           -               ivm                 IVMS8_256                            IVMS8:IVMS8_64M                                                                                                                   Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           -               netphone            NETPHONE                             NETPHONE:NETPHONE_VERSION=1                                                                                                       -
 Active  powerpc     mpc8xx         -           -               netphone            NETPHONE_V2                          NETPHONE:NETPHONE_VERSION=2                                                                                                       -
 Active  powerpc     mpc8xx         -           -               netta               NETTA                                NETTA                                                                                                                             -
 Active  powerpc     mpc8xx         -           -               netta               NETTA_6412                           NETTA:NETTA_6412=1                                                                                                                -
 Active  powerpc     mpc8xx         -           -               netta               NETTA_6412_SWAPHOOK                  NETTA:NETTA_6412=1,NETTA_SWAPHOOK=1                                                                                               -
 Active  powerpc     mpc8xx         -           -               netta               NETTA_ISDN                           NETTA:NETTA_ISDN=1                                                                                                                -
 Active  powerpc     mpc8xx         -           -               netta               NETTA_ISDN_6412                      NETTA:NETTA_ISDN=1,NETTA_6412=1                                                                                                   -
 Active  powerpc     mpc8xx         -           -               netta               NETTA_ISDN_6412_SWAPHOOK             NETTA:NETTA_ISDN=1,NETTA_6412=1,NETTA_SWAPHOOK=1                                                                                  -
 Active  powerpc     mpc8xx         -           -               netta               NETTA_ISDN_SWAPHOOK                  NETTA:NETTA_ISDN=1,NETTA_SWAPHOOK=1                                                                                               -
 Active  powerpc     mpc8xx         -           -               netta               NETTA_SWAPHOOK                       NETTA:NETTA_SWAPHOOK=1                                                                                                            -
 Active  powerpc     mpc8xx         -           -               netta2              NETTA2                               NETTA2:NETTA2_VERSION=1                                                                                                           -
 Active  powerpc     mpc8xx         -           -               netta2              NETTA2_V2                            NETTA2:NETTA2_VERSION=2                                                                                                           -
 Active  powerpc     mpc8xx         -           -               netvia              NETVIA                               NETVIA:NETVIA_VERSION=1                                                                                                           Pantelis Antoniou <panto@intracom.gr>
 Active  powerpc     mpc8xx         -           -               netvia              NETVIA_V2                            NETVIA:NETVIA_VERSION=2                                                                                                           Pantelis Antoniou <panto@intracom.gr>
 Active  powerpc     mpc8xx         -           -               r360mpi             R360MPI                              -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           -               rbc823              RBC823                               -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           -               RPXlite_dw          RPXlite_DW                           RPXlite_DW                                                                                                                        -
 Active  powerpc     mpc8xx         -           -               RPXlite_dw          RPXlite_DW_64                        RPXlite_DW:RPXlite_64MHz                                                                                                          -
 Active  powerpc     mpc8xx         -           -               RPXlite_dw          RPXlite_DW_64_LCD                    RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20                                                                                       -
 Active  powerpc     mpc8xx         -           -               RPXlite_dw          RPXlite_DW_LCD                       RPXlite_DW:LCD,NEC_NL6448BC20                                                                                                     -
 Active  powerpc     mpc8xx         -           -               RPXlite_dw          RPXlite_DW_NVRAM                     RPXlite_DW:ENV_IS_IN_NVRAM                                                                                                        -
 Active  powerpc     mpc8xx         -           -               RPXlite_dw          RPXlite_DW_NVRAM_64                  RPXlite_DW:RPXlite_64MHz,ENV_IS_IN_NVRAM                                                                                          -
 Active  powerpc     mpc8xx         -           -               RPXlite_dw          RPXlite_DW_NVRAM_64_LCD              RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM                                                                       -
 Active  powerpc     mpc8xx         -           -               RPXlite_dw          RPXlite_DW_NVRAM_LCD                 RPXlite_DW:LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM                                                                                     -
 Active  powerpc     mpc8xx         -           -               RRvision            RRvision_LCD                         RRvision:LCD,SHARP_LQ104V7DS01                                                                                                    Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           -               sixnet              SXNI855T                             -                                                                                                                                 Dave Ellis <DGE@sixnetio.com>
 Active  powerpc     mpc8xx         -           -               spd8xx              SPD823TS                             -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           eltec           mhpc                MHPC                                 -                                                                                                                                 Frank Gottschling <fgottschling@eltec.de>
 Active  powerpc     mpc8xx         -           emk             top860              TOP860                               -                                                                                                                                 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
 Active  powerpc     mpc8xx         -           kup             kup4k               KUP4K                                -                                                                                                                                 Klaus Heydeck <heydeck@kieback-peter.de>
 Active  powerpc     mpc8xx         -           kup             kup4x               KUP4X                                -                                                                                                                                 Klaus Heydeck <heydeck@kieback-peter.de>
 Active  powerpc     mpc8xx         -           LEOX            elpt860             ELPT860                              -                                                                                                                                 The LEOX team <team@leox.org>
 Active  powerpc     mpc8xx         -           manroland       -                   uc100                                -                                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     mpc8xx         -           snmc            qs850               QS823                                -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           snmc            qs850               QS850                                -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           snmc            qs860t              QS860T                               -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           stx             stxxtc              stxxtc                               -                                                                                                                                 Dan Malek <dan@embeddedalley.com>
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              FPS850L                              -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              FPS860L                              -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              NSCU                                 -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              SM850                                -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TK885D                               -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM823L                              -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM823L_LCD                          TQM823L:LCD,NEC_NL6448BC20                                                                                                        Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM823M                              -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM850L                              -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM850M                              -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM855L                              -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM855M                              -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM860L                              -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM860M                              -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM862L                              -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM862M                              -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM866M                              -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM885D                              -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TTTech                               TQM823L:LCD,SHARP_LQ104V7DS01                                                                                                     Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              virtlab2                             -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              wtk                                  TQM823L:LCD,SHARP_LQ065T9DR51U                                                                                                    Wolfgang Denk <wd@denx.de>
 Active  powerpc     ppc4xx         -           -               -                   csb272                               -                                                                                                                                 Tolunay Orkun <torkun@nextio.com>
 Active  powerpc     ppc4xx         -           -               -                   csb472                               -                                                                                                                                 Tolunay Orkun <torkun@nextio.com>
 Active  powerpc     ppc4xx         -           -               -                   korat                                -                                                                                                                                 Larry Johnson <lrj@acm.org>
 Active  powerpc     ppc4xx         -           -               -                   lwmon5                               -                                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           -               -                   pcs440ep                             -                                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           -               -                   quad100hd                            -                                                                                                                                 Gary Jennejohn <garyj@denx.de>
 Active  powerpc     ppc4xx         -           -               -                   sbc405                               -                                                                                                                                 -
 Active  powerpc     ppc4xx         -           -               -                   sc3                                  -                                                                                                                                 Heiko Schocher <hs@denx.de>
 Active  powerpc     ppc4xx         -           -               -                   t3corp                               -                                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           -               -                   zeus                                 -                                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           -               g2000               G2000                                -                                                                                                                                 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 Active  powerpc     ppc4xx         -           -               jse                 JSE                                  -                                                                                                                                 Stephen Williams <steve@icarus.com>
 Active  powerpc     ppc4xx         -           -               korat               korat_perm                           korat:KORAT_PERMANENT                                                                                                             Larry Johnson <lrj@acm.org>
 Active  powerpc     ppc4xx         -           -               lwmon5              lcd4_lwmon5                          lwmon5:LCD4_LWMON5                                                                                                                Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           -               w7o                 W7OLMC                               -                                                                                                                                 Erik Theisen <etheisen@mindspring.com>
 Active  powerpc     ppc4xx         -           -               w7o                 W7OLMG                               -                                                                                                                                 Erik Theisen <etheisen@mindspring.com>
 Active  powerpc     ppc4xx         -           amcc            -                   acadia                               -                                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            -                   bamboo                               -                                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            -                   bluestone                            -                                                                                                                                 Tirumala Marri <tmarri@apm.com>
 Active  powerpc     ppc4xx         -           amcc            -                   bubinga                              -                                                                                                                                 -
 Active  powerpc     ppc4xx         -           amcc            -                   ebony                                -                                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            -                   katmai                               -                                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            -                   luan                                 -                                                                                                                                 John Otken <jotken@softadvances.com>
 Active  powerpc     ppc4xx         -           amcc            -                   makalu                               -                                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            -                   ocotea                               -                                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            -                   redwood                              -                                                                                                                                 Feng Kan <fkan@amcc.com>
 Active  powerpc     ppc4xx         -           amcc            -                   taihu                                -                                                                                                                                 John Otken <jotken@softadvances.com>
 Active  powerpc     ppc4xx         -           amcc            -                   taishan                              -                                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            -                   yucca                                -                                                                                                                                 -
 Active  powerpc     ppc4xx         -           amcc            acadia              acadia_nand                          acadia:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000                                                                                       Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            bamboo              bamboo_nand                          bamboo:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000                                                                                       Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            canyonlands         arches                               canyonlands:ARCHES                                                                                                                Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            canyonlands         canyonlands                          canyonlands:CANYONLANDS                                                                                                           Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            canyonlands         canyonlands_nand                     canyonlands:CANYONLANDS,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000                                                                      Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            canyonlands         glacier                              canyonlands:GLACIER                                                                                                               Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            canyonlands         glacier_nand                         canyonlands:GLACIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000                                                                          Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            kilauea             haleakala                            kilauea:HALEAKALA                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            kilauea             haleakala_nand                       kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000                                                                                      Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            kilauea             kilauea                              kilauea:KILAUEA                                                                                                                   Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            kilauea             kilauea_nand                         kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000                                                                                      Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            sequoia             rainier                              sequoia:RAINIER                                                                                                                   Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            sequoia             rainier_nand                         sequoia:RAINIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000                                                                              Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            sequoia             rainier_ramboot                      sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds                               Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            sequoia             sequoia                              sequoia:SEQUOIA                                                                                                                   Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            sequoia             sequoia_nand                         sequoia:SEQUOIA,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000                                                                              Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            sequoia             sequoia_ramboot                      sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds                               Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            walnut              sycamore                             walnut                                                                                                                            Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            walnut              walnut                               -                                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            yosemite            yellowstone                          yosemite:YELLOWSTONE                                                                                                              Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            yosemite            yosemite                             yosemite:YOSEMITE                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           avnet           fx12mm              fx12mm                               fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o                       Georg Schardt <schardt@team-ctech.de>
 Active  powerpc     ppc4xx         -           avnet           fx12mm              fx12mm_flash                         fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o                       Georg Schardt <schardt@team-ctech.de>
 Active  powerpc     ppc4xx         -           avnet           v5fx30teval         v5fx30teval                          v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o  Ricardo Ribalda <ricardo.ribalda@uam.es>
 Active  powerpc     ppc4xx         -           avnet           v5fx30teval         v5fx30teval_flash                    v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o                  Ricardo Ribalda <ricardo.ribalda@uam.es>
 Active  powerpc     ppc4xx         -           cray            L1                  CRAYL1                               -                                                                                                                                 David Updegraff <dave@cray.com>
 Active  powerpc     ppc4xx         -           dave            PPChameleonEVB      CATcenter                            CATcenter:PPCHAMELEON_MODULE_MODEL=1                                                                                              -
 Active  powerpc     ppc4xx         -           dave            PPChameleonEVB      CATcenter_25                         CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25                                                                           -
 Active  powerpc     ppc4xx         -           dave            PPChameleonEVB      CATcenter_33                         CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33                                                                           -
 Active  powerpc     ppc4xx         -           dave            PPChameleonEVB      PPChameleonEVB                       -                                                                                                                                 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
 Active  powerpc     ppc4xx         -           dave            PPChameleonEVB      PPChameleonEVB_BA_25                 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_25                                                                      Andrea "llandre" Marson <andrea.marson@dave-tech.it>
 Active  powerpc     ppc4xx         -           dave            PPChameleonEVB      PPChameleonEVB_BA_33                 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_33                                                                      Andrea "llandre" Marson <andrea.marson@dave-tech.it>
 Active  powerpc     ppc4xx         -           dave            PPChameleonEVB      PPChameleonEVB_HI_25                 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_25                                                                      Andrea "llandre" Marson <andrea.marson@dave-tech.it>
 Active  powerpc     ppc4xx         -           dave            PPChameleonEVB      PPChameleonEVB_HI_33                 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_33                                                                      Andrea "llandre" Marson <andrea.marson@dave-tech.it>
 Active  powerpc     ppc4xx         -           dave            PPChameleonEVB      PPChameleonEVB_ME_25                 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25                                                                      Andrea "llandre" Marson <andrea.marson@dave-tech.it>
 Active  powerpc     ppc4xx         -           dave            PPChameleonEVB      PPChameleonEVB_ME_33                 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33                                                                      Andrea "llandre" Marson <andrea.marson@dave-tech.it>
 Active  powerpc     ppc4xx         -           esd             apc405              APC405                               -                                                                                                                                 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 Active  powerpc     ppc4xx         -           esd             ar405               AR405                                -                                                                                                                                 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 Active  powerpc     ppc4xx         -           esd             ash405              ASH405                               -                                                                                                                                 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 Active  powerpc     ppc4xx         -           esd             cms700              CMS700                               -                                                                                                                                 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 Active  powerpc     ppc4xx         -           esd             cpci2dp             CPCI2DP                              -                                                                                                                                 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 Active  powerpc     ppc4xx         -           esd             cpci405             CPCI405                              -                                                                                                                                 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 Active  powerpc     ppc4xx         -           esd             cpci405             CPCI4052                             -                                                                                                                                 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 Active  powerpc     ppc4xx         -           esd             cpci405             CPCI405AB                            -                                                                                                                                 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 Active  powerpc     ppc4xx         -           esd             cpci405             CPCI405DT                            -                                                                                                                                 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 Active  powerpc     ppc4xx         -           esd             cpciiser4           CPCIISER4                            -                                                                                                                                 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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 Active  powerpc     ppc4xx         -           prodrive        -                   alpr                                 -                                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           prodrive        -                   p3p440                               -                                                                                                                                 Stefan Roese <sr@denx.de>
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 Active  powerpc     ppc4xx         -           xilinx          ml507               ml507                                ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o        Ricardo Ribalda <ricardo.ribalda@uam.es>
 Active  powerpc     ppc4xx         -           xilinx          ml507               ml507_flash                          ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o                        Ricardo Ribalda <ricardo.ribalda@uam.es>
 Active  powerpc     ppc4xx         -           xilinx          ppc405-generic      xilinx-ppc405-generic                xilinx-ppc405-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000                                                    Ricardo Ribalda <ricardo.ribalda@uam.es>
 Active  powerpc     ppc4xx         -           xilinx          ppc405-generic      xilinx-ppc405-generic_flash          xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC                                                    Ricardo Ribalda <ricardo.ribalda@uam.es>
 Active  powerpc     ppc4xx         -           xilinx          ppc440-generic      xilinx-ppc440-generic                xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1                                    Ricardo Ribalda <ricardo.ribalda@uam.es>
 Active  powerpc     ppc4xx         -           xilinx          ppc440-generic      xilinx-ppc440-generic_flash          xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC                                                    Ricardo Ribalda <ricardo.ribalda@uam.es>
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 Active  sh          sh4            -           renesas         sh7752evb           sh7752evb                            -                                                                                                                                 -
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 Active  x86         x86            coreboot    chromebook-x86  coreboot            coreboot-x86                         coreboot:SYS_TEXT_BASE=0x01110000                                                                                                 -
 Orphan  arm         arm1136        mx31        -               imx31_phycore       imx31_phycore_eet                    imx31_phycore:IMX31_PHYCORE_EET                                                                                                   (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
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 Orphan  powerpc     mpc8xx         -           -               nx823               NX823                                -                                                                                                                                 -

include/configs/B4860QDS.h

Diff comments View file @ e7be182

 /*
  * Copyright 2011-2012 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * B4860 QDS board configuration file
  */
 #define CONFIG_B4860QDS
 #define CONFIG_PHYS_64BIT
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
 #endif
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 #define CONFIG_SYS_NO_FLASH
 #endif
 /* High Level Configuration Options */
 #define CONFIG_BOOKE
 #define CONFIG_E500			/* BOOKE e500 family */
 #define CONFIG_E500MC			/* BOOKE e500mc family */
 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
 #define CONFIG_MPC85xx			/* MPC85xx/PQ3 platform */
 #define CONFIG_MP			/* support multiple processors */
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xeff80000
 #endif
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
 #define CONFIG_FSL_IFC			/* Enable IFC Support */
 #define CONFIG_PCI			/* Enable PCI/PCIE */
 #define CONFIG_PCIE1			/* PCIE controler 1 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 #ifndef CONFIG_PPC_B4420
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */
 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 #endif
 #define CONFIG_FSL_LAW			/* Use common FSL init code */
 /* I2C bus multiplexer */
 #define I2C_MUX_PCA_ADDR                0x77
 /* VSC Crossbar switches */
 #define CONFIG_VSC_CROSSBAR
 #define I2C_CH_DEFAULT                  0x8
 #define I2C_CH_VSC3316                  0xc
 #define I2C_CH_VSC3308                  0xd
 #define VSC3316_TX_ADDRESS              0x70
 #define VSC3316_RX_ADDRESS              0x71
 #define VSC3308_TX_ADDRESS              0x02
 #define VSC3308_RX_ADDRESS              0x03
 /* IDT clock synthesizers */
 #define CONFIG_IDT8T49N222A
 #define I2C_CH_IDT                     0x9
 #define IDT_SERDES1_ADDRESS            0x6E
 #define IDT_SERDES2_ADDRESS            0x6C
 #define CONFIG_ENV_OVERWRITE
 #ifdef CONFIG_SYS_NO_FLASH
 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_ENV_IS_NOWHERE
 #endif
 #else
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #endif
 #if defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SPI_BUS              0
 #define CONFIG_ENV_SPI_CS               0
 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 #define CONFIG_ENV_SPI_MODE             0
 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 #define CONFIG_ENV_SECT_SIZE            0x10000
 #elif defined(CONFIG_SDCARD)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV          0
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_OFFSET		(512 * 1097)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_IS_IN_REMOTE
 #define CONFIG_ENV_ADDR		0xffe20000
 #define CONFIG_ENV_SIZE		0x2000
 #elif defined(CONFIG_ENV_IS_NOWHERE)
 #define CONFIG_ENV_SIZE		0x2000
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
 #ifndef __ASSEMBLY__
 unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
 #endif
 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BTB			/* toggle branch predition */
 #define CONFIG_DDR_ECC
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
 #define CONFIG_ENABLE_36BIT_PHYS
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_ADDR_MAP
 #define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
 #endif
 #if 0
 #define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
 #endif
 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 /*
  *  Config the L3 Cache as L3 SRAM
  */
 #define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_DCSRBAR		0xf0000000
 #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
 #endif
 /* EEPROM */
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM	0
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_SYS_FSL_DDR3
 #define CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SYS_SPD_BUS_NUM	0
 #define SPD_EEPROM_ADDRESS1	0x51
 #define SPD_EEPROM_ADDRESS2	0x53
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
 #define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
 /*
  * IFC Definitions
  */
 #define CONFIG_SYS_FLASH_BASE	0xe0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 #else
 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 #endif
 #define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 				+ 0x8000000) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
 #define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128 * 1024 * 1024)
 /* NOR Flash Timing Params */
 #define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(4)
 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x01) | \
 				FTIM0_NOR_TEADC(0x04) | \
 				FTIM0_NOR_TEAHC(0x20))
 #define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
 				FTIM1_NOR_TRAD_NOR(0x1A) |\
 				FTIM1_NOR_TSEQRAD_NOR(0x13))
 #define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x01) | \
 				FTIM2_NOR_TCH(0x0E) | \
 				FTIM2_NOR_TWPH(0x0E) | \
 				FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3	0x0
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
 					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 #define CONFIG_FSL_QIXIS	/* use common QIXIS code */
 #define CONFIG_FSL_QIXIS_V2
 #define QIXIS_BASE		0xffdf0000
 #ifdef CONFIG_PHYS_64BIT
 #define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
 #else
 #define QIXIS_BASE_PHYS		QIXIS_BASE
 #endif
 #define QIXIS_LBMAP_SWITCH		0x01
 #define QIXIS_LBMAP_MASK		0x0f
 #define QIXIS_LBMAP_SHIFT		0
 #define QIXIS_LBMAP_DFLTBANK		0x00
 #define QIXIS_LBMAP_ALTBANK		0x02
 #define QIXIS_RST_CTL_RESET		0x31
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
 #define CONFIG_SYS_CSPR3_EXT	(0xf)
 #define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
 #define CONFIG_SYS_AMASK3	IFC_AMASK(4 * 1024)
 #define CONFIG_SYS_CSOR3	0x0
 /* QIXIS Timing parameters for IFC CS3 */
 #define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
 					FTIM0_GPCM_TEAHC(0x0e))
 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
 					FTIM1_GPCM_TRAD(0x1f))
 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
 					FTIM2_GPCM_TCH(0x0) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3		0x0
 /* NAND Flash on IFC */
 #define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
 #define CONFIG_SYS_NAND_BASE		0xff800000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
 #else
 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
 #endif
 #define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
 				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
 				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 /* ONFI NAND Flash mode0 Timing Params */
 #define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
 #define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a) | \
 					FTIM2_NAND_TWHRE(0x1e))
 #define CONFIG_SYS_NAND_FTIM3		0x0
 #define CONFIG_SYS_NAND_DDR_LAW		11
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
 #if defined(CONFIG_NAND)
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
 #else
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
 #endif
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 #if defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_SYS_RAMBOOT
 #endif
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 #else
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS	0xfe0ec000 /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 #endif
 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
 					GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
  */
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 #define CONFIG_SERIAL_MULTI		/* Enable both serial ports */
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT
 #define CONFIG_OF_BOARD_SETUP
 #define CONFIG_OF_STDOUT_VIA_ALIAS
 /* new uImage format support */
 #define CONFIG_FIT
 #define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
 #define CONFIG_SYS_FSL_I2C_SPEED	400000	/* I2C speed in Hz */
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_SPEED	400000	/* I2C speed in Hz */
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x119000
 /*
  * RTC configuration
  */
 #define RTC
 #define CONFIG_RTC_DS3231               1
 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 /*
  * RapidIO
  */
 #ifdef CONFIG_SYS_SRIO
 #ifdef CONFIG_SRIO1
 #define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
 #else
 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
 #endif
 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
 #endif
 #ifdef CONFIG_SRIO2
 #define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
 #else
 #define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
 #endif
 #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
 #endif
 #endif
 /*
  * for slave u-boot IMAGE instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000	/* 512K */
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
 /*
  * for slave UCODE and ENV instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
 /* slave core release by master*/
 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 /*
  * SRIO_PCIE_BOOT - SLAVE
  */
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 #endif
 /*
  * eSPI - Enhanced SPI
  */
 #define CONFIG_FSL_ESPI
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_SST
 #define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED         10000000
 #define CONFIG_SF_DEFAULT_MODE          0
 /*
  * MAPLE
  */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
 #else
 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
 #endif
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
 #else
 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
 #endif
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 #else
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
 #endif
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	25
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
 #else
 #define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
 #endif
 #define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
 #define CONFIG_SYS_QMAN_NUM_PORTALS	25
 #define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
 #else
 #define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
 #endif
 #define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
 #define CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_DPAA_RMAN
 /* Default address of microcode for the Linux Fman driver */
 #if defined(CONFIG_SPIFLASH)
 /*
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	0x110000
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1130)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing
  * in two corenet boards, slave's ucode could be stored in master's memory
  * space, the address can be mapped from slave TLB->slave LAW->
  * slave SRIO or PCIE outbound window->master inbound window->
  * master LAW->the ucode address in master's memory space.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	0xFFE00000
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF40000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 #endif /* CONFIG_NOBQFMAN */
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_TERANETICS
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
 #endif
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 #define CONFIG_E1000
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #define CONFIG_DOS_PARTITION
 #endif	/* CONFIG_PCI */
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x10
 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR	0x11
 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7	 /*SLOT 1*/
 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6	 /*SLOT 2*/
 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 #define CONFIG_MII		/* MII PHY management */
 #define CONFIG_ETHPRIME		"FM1@DTSEC1"
 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
 #endif
 /*
  * Environment
  */
 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SETEXPR
 #ifdef CONFIG_PCI
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_NET
 #endif
 /*
 * USB
 */
 #define CONFIG_HAS_FSL_DR_USB
 #ifdef CONFIG_HAS_FSL_DR_USB
 #define CONFIG_USB_EHCI
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_CMD_EXT2
 #endif
 #endif
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 #define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE	115200
 #define __USB_PHY_TYPE	ulpi
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"hwconfig=fsl_ddr:ctlr_intlv=null,"		\
 	"bank_intlv=cs0_cs1;"					\
 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 	"netdev=eth0\0"						\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"			\
 	"tftpflash=tftpboot $loadaddr $uboot && "		\
 	"protect off $ubootaddr +$filesize && "			\
 	"erase $ubootaddr +$filesize && "			\
 	"cp.b $loadaddr $ubootaddr $filesize && "		\
 	"protect on $ubootaddr +$filesize && "			\
 	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=b4860qds/ramdisk.uboot\0"			\
 	"fdtaddr=c00000\0"					\
 	"fdtfile=b4860qds/b4860qds.dtb\0"				\
 	"bdev=sda3\0"						\
 	"c=ffe\0"
 /* For emulation this causes u-boot to jump to the start of the proof point
    app code automatically */
 #define CONFIG_PROOF_POINTS			\
  "setenv bootargs root=/dev/$bdev rw "		\
  "console=$consoledev,$baudrate $othbootargs;"	\
  "cpu 1 release 0x29000000 - - -;"		\
  "cpu 2 release 0x29000000 - - -;"		\
  "cpu 3 release 0x29000000 - - -;"		\
  "cpu 4 release 0x29000000 - - -;"		\
  "cpu 5 release 0x29000000 - - -;"		\
  "cpu 6 release 0x29000000 - - -;"		\
  "cpu 7 release 0x29000000 - - -;"		\
  "go 0x29000000"
 #define CONFIG_HVBOOT	\
  "setenv bootargs config-addr=0x60000000; "	\
  "bootm 0x01000000 - 0x00f00000"
 #define CONFIG_ALU				\
  "setenv bootargs root=/dev/$bdev rw "		\
  "console=$consoledev,$baudrate $othbootargs;"	\
  "cpu 1 release 0x01000000 - - -;"		\
  "cpu 2 release 0x01000000 - - -;"		\
  "cpu 3 release 0x01000000 - - -;"		\
  "cpu 4 release 0x01000000 - - -;"		\
  "cpu 5 release 0x01000000 - - -;"		\
  "cpu 6 release 0x01000000 - - -;"		\
  "cpu 7 release 0x01000000 - - -;"		\
  "go 0x01000000"
 #define CONFIG_LINUX				\
  "setenv bootargs root=/dev/ram rw "		\
  "console=$consoledev,$baudrate $othbootargs;"	\
  "setenv ramdiskaddr 0x02000000;"		\
  "setenv fdtaddr 0x00c00000;"			\
  "setenv loadaddr 0x1000000;"			\
  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_HDBOOT					\
 	"setenv bootargs root=/dev/$bdev rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_NFSBOOTCOMMAND			\
 	"setenv bootargs root=/dev/nfs rw "	\
 	"nfsroot=$serverip:$rootpath "		\
 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"		\
 	"tftp $fdtaddr $fdtfile;"		\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND				\
 	"setenv bootargs root=/dev/ram rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $ramdiskaddr $ramdiskfile;"		\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND		CONFIG_LINUX
 #include <asm/fsl_secure_boot.h>
 #endif	/* __CONFIG_H */

include/configs/BSC9131RDB.h

Diff comments View file @ e7be182

include/configs/BSC9132QDS.h

Diff comments View file @ e7be182

include/configs/CMS700.h

Diff comments View file @ e7be182

 /*
  * (C) Copyright 2005
  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 /*
  * CMS700.h - configuration options, board specific
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * High Level Configuration Options
  * (easy to change)
  */
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
 #define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_VOM405		1	/* ...on a VOM405 board		*/
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC8000
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 #define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
 #define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 #undef	CONFIG_BOOTARGS
 #undef  CONFIG_BOOTCOMMAND
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 #define CONFIG_PPC4xx_EMAC
 #undef  CONFIG_HAS_ETH1
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_DNS
 #define CONFIG_BOOTP_DNS2
 #define CONFIG_BOOTP_SEND_HOSTNAME
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_EEPROM
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 #undef  CONFIG_PRAM			/* no "protected RAM"           */
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 #define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 #define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 #define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 #define CONFIG_CONS_INDEX	2	/* Use UART1			*/
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_serial_clock()
 #undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
 #define CONFIG_SYS_BASE_BAUD	    691200
 /* The following table includes the supported baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 #define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 /*-----------------------------------------------------------------------
  * RTC stuff
  *-----------------------------------------------------------------------
  */
 #define CONFIG_RTC_DS1337
 #define CONFIG_SYS_I2C_RTC_ADDR	0x68
 /*-----------------------------------------------------------------------
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
 #define NAND_BIG_DELAY_US	25
 #define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
 #define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
 #define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 #define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
 #define CONFIG_SYS_NAND_QUIET          1
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_MAX_ECCPOS	48
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
 #define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 #define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 #define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
 #define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
 #define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
 #define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
 #define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
 #define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 #define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 #define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_MONITOR_BASE
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
 #define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
 #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
 # define CONFIG_SYS_RAMBOOT		1
 #else
 # undef CONFIG_SYS_RAMBOOT
 #endif
 /*-----------------------------------------------------------------------
  * Environment Variable setup
  */
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
 #define CONFIG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
 #define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC16 is 2048 bytes */
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_PPC4XX
 #define CONFIG_SYS_I2C_PPC4XX_CH0
 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 #define CONFIG_SYS_EEPROM_WREN         1
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  */
 #define CONFIG_SYS_PLD_BASE            0xf0000000
 #define CONFIG_SYS_NAND_BASE	        0xF4000000  /* NAND FLASH Base Address		*/
 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
 #define CONFIG_SYS_EBC_PB0AP		0x92015480
 #define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
 #define CONFIG_SYS_EBC_PB1AP		0x92015480
 #define CONFIG_SYS_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
 #define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 #define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
 #define CONFIG_SYS_XSVF_DEFAULT_ADDR	0xfffc0000
 /* FPGA program pin configuration */
 #define CONFIG_SYS_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
 #define CONFIG_SYS_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
 #define CONFIG_SYS_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
 #define CONFIG_SYS_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
 #define CONFIG_SYS_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 #define CONFIG_SYS_TEMP_STACK_OCM	  1
 /* On Chip Memory location */
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
 #define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 /*-----------------------------------------------------------------------
  * Definitions for GPIO setup (PPC405EP specific)
  *
  * GPIO0[0]	- External Bus Controller BLAST output
  * GPIO0[1-9]	- Instruction trace outputs -> GPIO
  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
  * GPIO0[24-27] - UART0 control signal inputs/outputs
  * GPIO0[28-29] - UART1 data signal input/output
  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  */
 /* GPIO Input:		OSR=00, ISR=00, TSR=00, TCR=0 */
 /* GPIO Output:		OSR=00, ISR=00, TSR=00, TCR=1 */
 /* Alt. Funtion Input:	OSR=00, ISR=01, TSR=00, TCR=0 */
 /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
 #define CONFIG_SYS_GPIO0_OSRL		0x40000500  /*	0 ... 15 */
 #define CONFIG_SYS_GPIO0_OSRH		0x00000110  /* 16 ... 31 */
 #define CONFIG_SYS_GPIO0_ISR1L		0x00000000  /*	0 ... 15 */
 #define CONFIG_SYS_GPIO0_ISR1H		0x14000045  /* 16 ... 31 */
 #define CONFIG_SYS_GPIO0_TSRL		0x00000000  /*	0 ... 15 */
 #define CONFIG_SYS_GPIO0_TSRH		0x00000000  /* 16 ... 31 */
 #define CONFIG_SYS_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */
 #define CONFIG_SYS_EEPROM_WP		(0x80000000 >> 8)    /* GPIO8 */
 #define CONFIG_SYS_PLD_RESET		(0x80000000 >> 12)   /* GPIO12 */
 /*
  * Default speed selection (cpu_plb_opb_ebc) in mhz.
  * This value will be set if iic boot eprom is disabled.
  */
 #define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
 #define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
 #endif	/* __CONFIG_H */

include/configs/P1010RDB.h

Diff comments View file @ e7be182

include/configs/P1022DS.h

Diff comments View file @ e7be182

 /*
  * Copyright 2010-2012 Freescale Semiconductor, Inc.
  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
  *          Timur Tabi <timur@freescale.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #include "../board/freescale/common/ics307_clk.h"
 #ifdef CONFIG_36BIT
 #define CONFIG_PHYS_64BIT
 #endif
 #ifdef CONFIG_SDCARD
 #define CONFIG_SPL
 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 #define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SPL_MMC_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
 #define CONFIG_FSL_LAW			/* Use common FSL init code */
 #define CONFIG_SYS_TEXT_BASE		0x11001000
 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
 #define CONFIG_SPL_PAD_TO		0x18000
 #define CONFIG_SPL_MAX_SIZE		(96 * 1024)
 #define CONFIG_SYS_MMC_U_BOOT_SIZE	(512 << 10)
 #define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
 #define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
 #define CONFIG_SYS_MMC_U_BOOT_OFFS	(96 << 10)
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #define CONFIG_SYS_LDSCRIPT		"arch/powerpc/cpu/mpc85xx/u-boot.lds"
 #define CONFIG_SPL_MMC_BOOT
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_COMMON_INIT_DDR
 #endif
 #endif
 #ifdef CONFIG_SPIFLASH
 #define CONFIG_SPL
 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 #define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
 #define CONFIG_FSL_LAW		/* Use common FSL init code */
 #define CONFIG_SYS_TEXT_BASE		0x11001000
 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
 #define CONFIG_SPL_PAD_TO		0x18000
 #define CONFIG_SPL_MAX_SIZE		(96 * 1024)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(512 << 10)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(96 << 10)
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
 #define CONFIG_SPL_SPI_BOOT
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_COMMON_INIT_DDR
 #endif
 #endif
 #define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
+#define CONFIG_SYS_NAND_MAX_OOBFREE	5
 #ifdef CONFIG_NAND
 #define CONFIG_SPL
 #define CONFIG_TPL
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_SPL_NAND_BOOT
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SPL_NAND_INIT
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 #define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SPL_MAX_SIZE		(128 << 10)
 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(576 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
 #define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
 #elif defined(CONFIG_SPL_BUILD)
 #define CONFIG_SPL_INIT_MINIMAL
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TEXT_BASE		0xff800000
 #define CONFIG_SPL_MAX_SIZE		4096
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
 #define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
 #endif
 #define CONFIG_SPL_PAD_TO		0x20000
 #define CONFIG_TPL_PAD_TO		0x20000
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 #define CONFIG_SYS_TEXT_BASE		0x11001000
 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #endif
 /* High Level Configuration Options */
 #define CONFIG_BOOKE			/* BOOKE */
 #define CONFIG_E500			/* BOOKE e500 family */
 #define CONFIG_MPC85xx			/* MPC8540/60/55/41/48 */
 #define CONFIG_P1022
 #define CONFIG_P1022DS
 #define CONFIG_MP			/* support multiple processors */
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xeff80000
 #endif
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 #define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
 #define CONFIG_PCI			/* Enable PCI/PCIE */
 #define CONFIG_PCIE1			/* PCIE controler 1 (slot 1) */
 #define CONFIG_PCIE2			/* PCIE controler 2 (slot 2) */
 #define CONFIG_PCIE3			/* PCIE controler 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 #define CONFIG_ENABLE_36BIT_PHYS
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_ADDR_MAP
 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
 #endif
 #define CONFIG_FSL_LAW			/* Use common FSL init code */
 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
 #define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE
 #define CONFIG_BTB
 #define CONFIG_SYS_MEMTEST_START	0x00000000
 #define CONFIG_SYS_MEMTEST_END		0x7fffffff
 #define CONFIG_SYS_CCSRBAR		0xffe00000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
        SPL code*/
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 /* DDR Setup */
 #define CONFIG_DDR_SPD
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_FSL_DDR3
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 /* I2C addresses of SPD EEPROMs */
 #define CONFIG_SYS_SPD_BUS_NUM		1
 #define SPD_EEPROM_ADDRESS		0x51	/* CTLR 0 DIMM 0 */
 /* These are used when DDR doesn't use SPD.  */
 #define CONFIG_SYS_SDRAM_SIZE		2048
 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_2G
 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000003F
 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
 #define CONFIG_SYS_DDR_CS1_BNDS		0x0040007F
 #define CONFIG_SYS_DDR_CS1_CONFIG	0x80014202
 #define CONFIG_SYS_DDR_TIMING_3		0x00010000
 #define CONFIG_SYS_DDR_TIMING_0		0x40110104
 #define CONFIG_SYS_DDR_TIMING_1		0x5c5bd746
 #define CONFIG_SYS_DDR_TIMING_2		0x0fa8d4ca
 #define CONFIG_SYS_DDR_MODE_1		0x00441221
 #define CONFIG_SYS_DDR_MODE_2		0x00000000
 #define CONFIG_SYS_DDR_INTERVAL		0x0a280100
 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
 #define CONFIG_SYS_DDR_CLK_CTRL		0x02800000
 #define CONFIG_SYS_DDR_CONTROL		0xc7000008
 #define CONFIG_SYS_DDR_CONTROL_2	0x24401041
 #define	CONFIG_SYS_DDR_TIMING_4		0x00220001
 #define	CONFIG_SYS_DDR_TIMING_5		0x02401400
 #define	CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
 #define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8675f608
 /*
  * Memory map
  *
  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
  * 0x8000_0000	0xdfff_ffff	PCI Express Mem		1.5G non-cacheable
  * 0xffc0_0000	0xffc2_ffff	PCI IO range		192K non-cacheable
  *
  * Localbus cacheable (TBD)
  * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
  *
  * Localbus non-cacheable
  * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
  * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
  * 0xff80_0000	0xff80_7fff	NAND			32K non-cacheable
  * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
  */
 /*
  * Local Bus Definitions
  */
 #define CONFIG_SYS_FLASH_BASE		0xe8000000 /* start of FLASH 128M */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_FLASH_BASE_PHYS	0xfe8000000ull
 #else
 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 #endif
 #define CONFIG_FLASH_BR_PRELIM  \
 	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 #define CONFIG_FLASH_OR_PRELIM	(OR_AM_128MB | 0xff7)
 #ifdef CONFIG_NAND
 #define CONFIG_SYS_BR1_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
 #define CONFIG_SYS_OR1_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
 #else
 #define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 #define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 #endif
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	1024
 #ifndef CONFIG_SYS_MONITOR_BASE
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SPL_TEXT_BASE
 #else
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
 #endif
 #endif
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 /* Nand Flash */
 #if defined(CONFIG_NAND_FSL_ELBC)
 #define CONFIG_SYS_NAND_BASE		0xff800000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
 #else
 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
 #endif
 #define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE}
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_CMD_NAND			1
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(256 * 1024)
 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
 /* NAND flash config */
 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 			       | BR_PS_8	       /* Port Size = 8 bit */ \
 			       | BR_MS_FCM	       /* MSEL = FCM */ \
 			       | BR_V)		       /* valid */
 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_32KB	       /* length 256K */ \
 			       | OR_FCM_PGS	       /* Large Page*/ \
 			       | OR_FCM_CSCT \
 			       | OR_FCM_CST \
 			       | OR_FCM_CHT \
 			       | OR_FCM_SCY_1 \
 			       | OR_FCM_TRLX \
 			       | OR_FCM_EHTR)
 #ifdef CONFIG_NAND
 #define CONFIG_SYS_BR0_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 #define CONFIG_SYS_OR0_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 #else
 #define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 #endif
 #endif /* CONFIG_NAND_FSL_ELBC */
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
 #define CONFIG_FSL_NGPIXIS
 #define PIXIS_BASE		0xffdf0000	/* PIXIS registers */
 #ifdef CONFIG_PHYS_64BIT
 #define PIXIS_BASE_PHYS		0xfffdf0000ull
 #else
 #define PIXIS_BASE_PHYS		PIXIS_BASE
 #endif
 #define CONFIG_SYS_BR2_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 #define CONFIG_SYS_OR2_PRELIM	(OR_AM_32KB | 0x6ff7)
 #define PIXIS_LBMAP_SWITCH	7
 #define PIXIS_LBMAP_MASK	0xF0
 #define PIXIS_LBMAP_ALTBANK	0x20
 #define PIXIS_SPD		0x07
 #define PIXIS_SPD_SYSCLK_MASK	0x07
 #define PIXIS_ELBC_SPI_MASK	0xc0
 #define PIXIS_SPI		0x80
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000 /* Size of used area in RAM */
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
 /*
  * Config the L2 Cache as L2 SRAM
 */
 #if defined(CONFIG_SPL_BUILD)
 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_INIT_L2_ADDR	0xf8f80000
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
 #define CONFIG_SYS_L2_SIZE		(256 << 10)
 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 #define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 #define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(96 << 10)
 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 #elif defined(CONFIG_NAND)
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
 #define CONFIG_SYS_L2_SIZE		(256 << 10)
 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 #define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 #else
 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
 #define CONFIG_SYS_L2_SIZE		(256 << 10)
 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 #define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x2000)
 #define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 #endif
 #endif
 #endif
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 #define CONFIG_NS16550_MIN_FUNCTIONS
 #endif
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 /* Video */
 #ifdef CONFIG_FSL_DIU_FB
 #define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x10000)
 #define CONFIG_VIDEO
 #define CONFIG_CMD_BMP
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VIDEO_SW_CURSOR
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 /*
  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
  * disable empty flash sector detection, which is I/O-intensive.
  */
 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 #endif
 #ifndef CONFIG_FSL_DIU_FB
 #endif
 #ifdef CONFIG_ATI
 #define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE1_IO_VIRT
 #define CONFIG_VIDEO
 #define CONFIG_BIOSEMU
 #define CONFIG_VIDEO_SW_CURSOR
 #define CONFIG_ATI_RADEON_FB
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #endif
 /*
  * Pass open firmware flat tree
  */
 #define CONFIG_OF_LIBFDT
 #define CONFIG_OF_BOARD_SETUP
 #define CONFIG_OF_STDOUT_VIA_ALIAS
 /* new uImage format support */
 #define CONFIG_FIT
 #define CONFIG_FIT_VERBOSE
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
 #define CONFIG_SYS_I2C_NOPROBES		{{0, 0x29}}
 /*
  * I2C2 EEPROM
  */
 #define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 #define CONFIG_SYS_EEPROM_BUS_NUM	1
 /*
  * eSPI - Enhanced SPI
  */
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_SPANSION
 #define CONFIG_HARD_SPI
 #define CONFIG_FSL_ESPI
 #define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED		10000000
 #define CONFIG_SF_DEFAULT_MODE		0
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
 #else
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
 #endif
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
 #else
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
 #endif
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
 #else
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
 #endif
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
 #else
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
 #endif
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc00000000ull
 #else
 #define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
 #endif
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xfffc00000ull
 #else
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
 #endif
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #define CONFIG_E1000			/* Define e1000 pci Ethernet card */
 #endif
 /* SATA */
 #define CONFIG_LIBATA
 #define CONFIG_FSL_SATA
 #define CONFIG_FSL_SATA_V2
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 #ifdef CONFIG_FSL_SATA
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
 #define CONFIG_DOS_PARTITION
 #define CONFIG_CMD_EXT2
 #endif
 #define CONFIG_MMC
 #ifdef CONFIG_MMC
 #define CONFIG_CMD_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #endif
 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 #define CONFIG_TSEC_ENET
 #ifdef CONFIG_TSEC_ENET
 #define CONFIG_TSECV2
 #define CONFIG_MII			/* MII PHY management */
 #define CONFIG_TSEC1		1
 #define CONFIG_TSEC1_NAME	"eTSEC1"
 #define CONFIG_TSEC2		1
 #define CONFIG_TSEC2_NAME	"eTSEC2"
 #define TSEC1_PHY_ADDR		1
 #define TSEC2_PHY_ADDR		2
 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 #define CONFIG_ETHPRIME		"eTSEC1"
 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
 #endif
 /*
  * Environment
  */
 #ifdef CONFIG_SPIFLASH
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SPI_BUS	0
 #define CONFIG_ENV_SPI_CS	0
 #define CONFIG_ENV_SPI_MAX_HZ	10000000
 #define CONFIG_ENV_SPI_MODE	0
 #define CONFIG_ENV_SIZE		0x2000	/* 8KB */
 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #elif defined(CONFIG_SDCARD)
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_FSL_FIXED_MMC_LOCATION
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_SYS_MMC_ENV_DEV	0
 #elif defined(CONFIG_NAND)
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 #else
 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
 #endif
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_OFFSET	(1024 * 1024)
 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
 #elif defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #define CONFIG_ENV_SIZE		0x2000
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 #define CONFIG_ENV_ADDR	0xfff80000
 #else
 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #endif
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
 #define CONFIG_LOADS_ECHO
 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SETEXPR
 #define CONFIG_CMD_REGINFO
 #ifdef CONFIG_PCI
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_NET
 #endif
 /*
  * USB
  */
 #define CONFIG_HAS_FSL_DR_USB
 #ifdef CONFIG_HAS_FSL_DR_USB
 #define CONFIG_USB_EHCI
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_FAT
 #endif
 #endif
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_MAXARGS	16
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_HOSTNAME		p1022ds
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
 #define CONFIG_LOADADDR		1000000
 #define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE	115200
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"netdev=eth0\0"						\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
 	"tftpflash=tftpboot $loadaddr $uboot && "		\
 		"protect off $ubootaddr +$filesize && "		\
 		"erase $ubootaddr +$filesize && "		\
 		"cp.b $loadaddr $ubootaddr $filesize && "	\
 		"protect on $ubootaddr +$filesize && "		\
 		"cmp.b $loadaddr $ubootaddr $filesize\0"	\
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
 	"fdtaddr=c00000\0"	  			      	\
 	"fdtfile=p1022ds.dtb\0"	  				\
 	"bdev=sda3\0"		  			      	\
 	"hwconfig=esdhc;audclk:12\0"
 #define CONFIG_HDBOOT					\
 	"setenv bootargs root=/dev/$bdev rw "		\
 	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_NFSBOOTCOMMAND						\
 	"setenv bootargs root=/dev/nfs rw "				\
 	"nfsroot=$serverip:$rootpath "					\
 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND						\
 	"setenv bootargs root=/dev/ram rw "				\
 	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
 	"tftp $ramdiskaddr $ramdiskfile;"				\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND		CONFIG_RAMBOOTCOMMAND
 #endif

include/configs/T1040QDS.h

Diff comments View file @ e7be182

 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * T1040 QDS board configuration file
  */
 #define CONFIG_T1040QDS
 #define CONFIG_PHYS_64BIT
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg
 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg
 #endif
 /* High Level Configuration Options */
 #define CONFIG_BOOKE
 #define CONFIG_E500			/* BOOKE e500 family */
 #define CONFIG_E500MC			/* BOOKE e500mc family */
 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
 #define CONFIG_MPC85xx			/* MPC85xx/PQ3 platform */
 #define CONFIG_MP			/* support multiple processors */
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xeff80000
 #endif
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
 #define CONFIG_FSL_IFC			/* Enable IFC Support */
 #define CONFIG_PCI			/* Enable PCI/PCIE */
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCIE1			/* PCIE controler 1 */
 #define CONFIG_PCIE2			/* PCIE controler 2 */
 #define CONFIG_PCIE3			/* PCIE controler 3 */
 #define CONFIG_PCIE4			/* PCIE controler 4 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 #define CONFIG_FSL_LAW			/* Use common FSL init code */
 #define CONFIG_ENV_OVERWRITE
 #ifdef CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_IS_NOWHERE
 #else
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #endif
 #ifndef CONFIG_SYS_NO_FLASH
 #if defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SPI_BUS              0
 #define CONFIG_ENV_SPI_CS               0
 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 #define CONFIG_ENV_SPI_MODE             0
 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 #define CONFIG_ENV_SECT_SIZE            0x10000
 #elif defined(CONFIG_SDCARD)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV          0
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_OFFSET		(512 * 1105)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
 #else /* CONFIG_SYS_NO_FLASH */
 #define CONFIG_ENV_SIZE                0x2000
 #define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
 #endif
 #ifndef __ASSEMBLY__
 unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
 #endif
 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BACKSIDE_L2_CACHE
 #define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
 #define CONFIG_BTB			/* toggle branch predition */
 #define CONFIG_DDR_ECC
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
 #define CONFIG_ENABLE_36BIT_PHYS
 #define CONFIG_ADDR_MAP
 #define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 /*
  *  Config the L3 Cache as L3 SRAM
  */
 #define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
 #define CONFIG_SYS_DCSRBAR		0xf0000000
 #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
 /* EEPROM */
 #define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM	0
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_FSL_DDR3
 #define CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SYS_SPD_BUS_NUM	0
 #define SPD_EEPROM_ADDRESS	0x51
 #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
 /*
  * IFC Definitions
  */
 #define CONFIG_SYS_FLASH_BASE	0xe0000000
 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 #define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 				+ 0x8000000) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
 #define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
 /* NOR Flash Timing Params */
 #define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TEAHC(0x5))
 #define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
 				FTIM1_NOR_TRAD_NOR(0x1A) |\
 				FTIM1_NOR_TSEQRAD_NOR(0x13))
 #define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
 				FTIM2_NOR_TCH(0x4) | \
 				FTIM2_NOR_TWPH(0x0E) | \
 				FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3	0x0
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
 					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 #define CONFIG_FSL_QIXIS	/* use common QIXIS code */
 #define QIXIS_BASE		0xffdf0000
 #define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
 #define QIXIS_LBMAP_SWITCH		0x06
 #define QIXIS_LBMAP_MASK		0x0f
 #define QIXIS_LBMAP_SHIFT		0
 #define QIXIS_LBMAP_DFLTBANK		0x00
 #define QIXIS_LBMAP_ALTBANK		0x04
 #define QIXIS_RST_CTL_RESET		0x31
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define	QIXIS_RST_FORCE_MEM		0x01
 #define CONFIG_SYS_CSPR3_EXT	(0xf)
 #define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
 #define CONFIG_SYS_AMASK3	IFC_AMASK(4*1024)
 #define CONFIG_SYS_CSOR3	0x0
 /* QIXIS Timing parameters for IFC CS3 */
 #define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
 					FTIM0_GPCM_TEAHC(0x0e))
 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
 					FTIM1_GPCM_TRAD(0x3f))
 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
-					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3		0x0
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_NAND_BASE		0xff800000
 #define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
 #define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
 				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
 				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 /* ONFI NAND Flash mode0 Timing Params */
 #define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
 #define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a) | \
 					FTIM2_NAND_TWHRE(0x1e))
 #define CONFIG_SYS_NAND_FTIM3		0x0
 #define CONFIG_SYS_NAND_DDR_LAW		11
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
 #if defined(CONFIG_NAND)
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
 #else
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
 #endif
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 #if defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_SYS_RAMBOOT
 #endif
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
 					GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
  */
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 #define CONFIG_SERIAL_MULTI		/* Enable both serial ports */
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT
 #define CONFIG_OF_BOARD_SETUP
 #define CONFIG_OF_STDOUT_VIA_ALIAS
 /* new uImage format support */
 #define CONFIG_FIT
 #define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
 #define CONFIG_SYS_FSL_I2C_SPEED	400000	/* I2C speed in Hz */
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_SPEED	400000	/* I2C speed in Hz */
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x119000
 #define I2C_MUX_PCA_ADDR		0x77
 #define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
 /* I2C bus multiplexer */
 #define I2C_MUX_CH_DEFAULT      0x8
 /*
  * RTC configuration
  */
 #define RTC
 #define CONFIG_RTC_DS3231               1
 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 /*
  * eSPI - Enhanced SPI
  */
 #define CONFIG_FSL_ESPI
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_SPI_FLASH_SST
 #define CONFIG_SPI_FLASH_EON
 #define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED         10000000
 #define CONFIG_SF_DEFAULT_MODE          0
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #ifdef CONFIG_PCI
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #ifdef CONFIG_PCIE1
 #define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
 #define	CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 #endif
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #ifdef CONFIG_PCIE2
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 #endif
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #ifdef CONFIG_PCIE3
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 #endif
 /* controller 4, Base address 203000 */
 #ifdef CONFIG_PCIE4
 #define CONFIG_SYS_PCIE4_MEM_VIRT	0xb0000000
 #define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc30000000ull
 #define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE4_IO_VIRT	0xf8030000
 #define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 #endif
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 #define CONFIG_E1000
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #define CONFIG_DOS_PARTITION
 #endif	/* CONFIG_PCI */
 /* SATA */
 #define CONFIG_FSL_SATA_V2
 #ifdef CONFIG_FSL_SATA_V2
 #define CONFIG_LIBATA
 #define CONFIG_FSL_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
 #define CONFIG_DOS_PARTITION
 #define CONFIG_CMD_EXT2
 #endif
 /*
 * USB
 */
 #define CONFIG_HAS_FSL_DR_USB
 #ifdef CONFIG_HAS_FSL_DR_USB
 #define CONFIG_USB_EHCI
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_CMD_EXT2
 #endif
 #endif
 #define CONFIG_MMC
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	25
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
 #define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
 #define CONFIG_SYS_QMAN_NUM_PORTALS	25
 #define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
 #define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
 #define CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_DPAA_PME
 /* Default address of microcode for the Linux Fman driver */
 #if defined(CONFIG_SPIFLASH)
 /*
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	0x110000
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1130)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF40000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 #endif /* CONFIG_NOBQFMAN */
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
 #define CONFIG_PHY_TERANETICS
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
 #endif
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x10
 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR	0x11
 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR	4
 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 #define CONFIG_MII		/* MII PHY management */
 #define CONFIG_ETHPRIME		"FM1@DTSEC1"
 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
 #endif
 /*
  * Environment
  */
 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SETEXPR
 #ifdef CONFIG_PCI
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_NET
 #endif
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks*/
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 #define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE	115200
 #define __USB_PHY_TYPE	utmi
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
 	"bank_intlv=cs0_cs1;"					\
 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 	"netdev=eth0\0"						\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
 	"tftpflash=tftpboot $loadaddr $uboot && "		\
 	"protect off $ubootaddr +$filesize && "			\
 	"erase $ubootaddr +$filesize && "			\
 	"cp.b $loadaddr $ubootaddr $filesize && "		\
 	"protect on $ubootaddr +$filesize && "			\
 	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=t1040qds/ramdisk.uboot\0"			\
 	"fdtaddr=c00000\0"					\
 	"fdtfile=t1040qds/t1040qds.dtb\0"			\
 	"bdev=sda3\0"						\
 	"c=ffe\0"
 #define CONFIG_LINUX                       \
 	"setenv bootargs root=/dev/ram rw "            \
 	"console=$consoledev,$baudrate $othbootargs;"  \
 	"setenv ramdiskaddr 0x02000000;"               \
 	"setenv fdtaddr 0x00c00000;"		       \
 	"setenv loadaddr 0x1000000;"		       \
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_HDBOOT					\
 	"setenv bootargs root=/dev/$bdev rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_NFSBOOTCOMMAND			\
 	"setenv bootargs root=/dev/nfs rw "	\
 	"nfsroot=$serverip:$rootpath "		\
 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"		\
 	"tftp $fdtaddr $fdtfile;"		\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND				\
 	"setenv bootargs root=/dev/ram rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $ramdiskaddr $ramdiskfile;"		\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND		CONFIG_LINUX
 #ifdef CONFIG_SECURE_BOOT
 #include <asm/fsl_secure_boot.h>
 #endif
 #endif	/* __CONFIG_H */