Commit e7be18225fbea76d1f0034b224f0d1e60f07cfcf

Authored by Tom Rini

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

Showing 18 changed files Inline Diff

1 # 1 #
2 # (C) Copyright 2000 - 2013 2 # (C) Copyright 2000 - 2013
3 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 # 4 #
5 # SPDX-License-Identifier: GPL-2.0+ 5 # SPDX-License-Identifier: GPL-2.0+
6 # 6 #
7 7
8 Summary: 8 Summary:
9 ======== 9 ========
10 10
11 This directory contains the source code for U-Boot, a boot loader for 11 This directory contains the source code for U-Boot, a boot loader for
12 Embedded boards based on PowerPC, ARM, MIPS and several other 12 Embedded boards based on PowerPC, ARM, MIPS and several other
13 processors, which can be installed in a boot ROM and used to 13 processors, which can be installed in a boot ROM and used to
14 initialize and test the hardware or to download and run application 14 initialize and test the hardware or to download and run application
15 code. 15 code.
16 16
17 The development of U-Boot is closely related to Linux: some parts of 17 The development of U-Boot is closely related to Linux: some parts of
18 the source code originate in the Linux source tree, we have some 18 the source code originate in the Linux source tree, we have some
19 header files in common, and special provision has been made to 19 header files in common, and special provision has been made to
20 support booting of Linux images. 20 support booting of Linux images.
21 21
22 Some attention has been paid to make this software easily 22 Some attention has been paid to make this software easily
23 configurable and extendable. For instance, all monitor commands are 23 configurable and extendable. For instance, all monitor commands are
24 implemented with the same call interface, so that it's very easy to 24 implemented with the same call interface, so that it's very easy to
25 add new commands. Also, instead of permanently adding rarely used 25 add new commands. Also, instead of permanently adding rarely used
26 code (for instance hardware test utilities) to the monitor, you can 26 code (for instance hardware test utilities) to the monitor, you can
27 load and run it dynamically. 27 load and run it dynamically.
28 28
29 29
30 Status: 30 Status:
31 ======= 31 =======
32 32
33 In general, all boards for which a configuration option exists in the 33 In general, all boards for which a configuration option exists in the
34 Makefile have been tested to some extent and can be considered 34 Makefile have been tested to some extent and can be considered
35 "working". In fact, many of them are used in production systems. 35 "working". In fact, many of them are used in production systems.
36 36
37 In case of problems see the CHANGELOG and CREDITS files to find out 37 In case of problems see the CHANGELOG and CREDITS files to find out
38 who contributed the specific port. The boards.cfg file lists board 38 who contributed the specific port. The boards.cfg file lists board
39 maintainers. 39 maintainers.
40 40
41 Note: There is no CHANGELOG file in the actual U-Boot source tree; 41 Note: There is no CHANGELOG file in the actual U-Boot source tree;
42 it can be created dynamically from the Git log using: 42 it can be created dynamically from the Git log using:
43 43
44 make CHANGELOG 44 make CHANGELOG
45 45
46 46
47 Where to get help: 47 Where to get help:
48 ================== 48 ==================
49 49
50 In case you have questions about, problems with or contributions for 50 In case you have questions about, problems with or contributions for
51 U-Boot you should send a message to the U-Boot mailing list at 51 U-Boot you should send a message to the U-Boot mailing list at
52 <u-boot@lists.denx.de>. There is also an archive of previous traffic 52 <u-boot@lists.denx.de>. There is also an archive of previous traffic
53 on the mailing list - please search the archive before asking FAQ's. 53 on the mailing list - please search the archive before asking FAQ's.
54 Please see http://lists.denx.de/pipermail/u-boot and 54 Please see http://lists.denx.de/pipermail/u-boot and
55 http://dir.gmane.org/gmane.comp.boot-loaders.u-boot 55 http://dir.gmane.org/gmane.comp.boot-loaders.u-boot
56 56
57 57
58 Where to get source code: 58 Where to get source code:
59 ========================= 59 =========================
60 60
61 The U-Boot source code is maintained in the git repository at 61 The U-Boot source code is maintained in the git repository at
62 git://www.denx.de/git/u-boot.git ; you can browse it online at 62 git://www.denx.de/git/u-boot.git ; you can browse it online at
63 http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=summary 63 http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=summary
64 64
65 The "snapshot" links on this page allow you to download tarballs of 65 The "snapshot" links on this page allow you to download tarballs of
66 any version you might be interested in. Official releases are also 66 any version you might be interested in. Official releases are also
67 available for FTP download from the ftp://ftp.denx.de/pub/u-boot/ 67 available for FTP download from the ftp://ftp.denx.de/pub/u-boot/
68 directory. 68 directory.
69 69
70 Pre-built (and tested) images are available from 70 Pre-built (and tested) images are available from
71 ftp://ftp.denx.de/pub/u-boot/images/ 71 ftp://ftp.denx.de/pub/u-boot/images/
72 72
73 73
74 Where we come from: 74 Where we come from:
75 =================== 75 ===================
76 76
77 - start from 8xxrom sources 77 - start from 8xxrom sources
78 - create PPCBoot project (http://sourceforge.net/projects/ppcboot) 78 - create PPCBoot project (http://sourceforge.net/projects/ppcboot)
79 - clean up code 79 - clean up code
80 - make it easier to add custom boards 80 - make it easier to add custom boards
81 - make it possible to add other [PowerPC] CPUs 81 - make it possible to add other [PowerPC] CPUs
82 - extend functions, especially: 82 - extend functions, especially:
83 * Provide extended interface to Linux boot loader 83 * Provide extended interface to Linux boot loader
84 * S-Record download 84 * S-Record download
85 * network boot 85 * network boot
86 * PCMCIA / CompactFlash / ATA disk / SCSI ... boot 86 * PCMCIA / CompactFlash / ATA disk / SCSI ... boot
87 - create ARMBoot project (http://sourceforge.net/projects/armboot) 87 - create ARMBoot project (http://sourceforge.net/projects/armboot)
88 - add other CPU families (starting with ARM) 88 - add other CPU families (starting with ARM)
89 - create U-Boot project (http://sourceforge.net/projects/u-boot) 89 - create U-Boot project (http://sourceforge.net/projects/u-boot)
90 - current project page: see http://www.denx.de/wiki/U-Boot 90 - current project page: see http://www.denx.de/wiki/U-Boot
91 91
92 92
93 Names and Spelling: 93 Names and Spelling:
94 =================== 94 ===================
95 95
96 The "official" name of this project is "Das U-Boot". The spelling 96 The "official" name of this project is "Das U-Boot". The spelling
97 "U-Boot" shall be used in all written text (documentation, comments 97 "U-Boot" shall be used in all written text (documentation, comments
98 in source files etc.). Example: 98 in source files etc.). Example:
99 99
100 This is the README file for the U-Boot project. 100 This is the README file for the U-Boot project.
101 101
102 File names etc. shall be based on the string "u-boot". Examples: 102 File names etc. shall be based on the string "u-boot". Examples:
103 103
104 include/asm-ppc/u-boot.h 104 include/asm-ppc/u-boot.h
105 105
106 #include <asm/u-boot.h> 106 #include <asm/u-boot.h>
107 107
108 Variable names, preprocessor constants etc. shall be either based on 108 Variable names, preprocessor constants etc. shall be either based on
109 the string "u_boot" or on "U_BOOT". Example: 109 the string "u_boot" or on "U_BOOT". Example:
110 110
111 U_BOOT_VERSION u_boot_logo 111 U_BOOT_VERSION u_boot_logo
112 IH_OS_U_BOOT u_boot_hush_start 112 IH_OS_U_BOOT u_boot_hush_start
113 113
114 114
115 Versioning: 115 Versioning:
116 =========== 116 ===========
117 117
118 Starting with the release in October 2008, the names of the releases 118 Starting with the release in October 2008, the names of the releases
119 were changed from numerical release numbers without deeper meaning 119 were changed from numerical release numbers without deeper meaning
120 into a time stamp based numbering. Regular releases are identified by 120 into a time stamp based numbering. Regular releases are identified by
121 names consisting of the calendar year and month of the release date. 121 names consisting of the calendar year and month of the release date.
122 Additional fields (if present) indicate release candidates or bug fix 122 Additional fields (if present) indicate release candidates or bug fix
123 releases in "stable" maintenance trees. 123 releases in "stable" maintenance trees.
124 124
125 Examples: 125 Examples:
126 U-Boot v2009.11 - Release November 2009 126 U-Boot v2009.11 - Release November 2009
127 U-Boot v2009.11.1 - Release 1 in version November 2009 stable tree 127 U-Boot v2009.11.1 - Release 1 in version November 2009 stable tree
128 U-Boot v2010.09-rc1 - Release candiate 1 for September 2010 release 128 U-Boot v2010.09-rc1 - Release candiate 1 for September 2010 release
129 129
130 130
131 Directory Hierarchy: 131 Directory Hierarchy:
132 ==================== 132 ====================
133 133
134 /arch Architecture specific files 134 /arch Architecture specific files
135 /arm Files generic to ARM architecture 135 /arm Files generic to ARM architecture
136 /cpu CPU specific files 136 /cpu CPU specific files
137 /arm720t Files specific to ARM 720 CPUs 137 /arm720t Files specific to ARM 720 CPUs
138 /arm920t Files specific to ARM 920 CPUs 138 /arm920t Files specific to ARM 920 CPUs
139 /at91 Files specific to Atmel AT91RM9200 CPU 139 /at91 Files specific to Atmel AT91RM9200 CPU
140 /imx Files specific to Freescale MC9328 i.MX CPUs 140 /imx Files specific to Freescale MC9328 i.MX CPUs
141 /s3c24x0 Files specific to Samsung S3C24X0 CPUs 141 /s3c24x0 Files specific to Samsung S3C24X0 CPUs
142 /arm926ejs Files specific to ARM 926 CPUs 142 /arm926ejs Files specific to ARM 926 CPUs
143 /arm1136 Files specific to ARM 1136 CPUs 143 /arm1136 Files specific to ARM 1136 CPUs
144 /ixp Files specific to Intel XScale IXP CPUs 144 /ixp Files specific to Intel XScale IXP CPUs
145 /pxa Files specific to Intel XScale PXA CPUs 145 /pxa Files specific to Intel XScale PXA CPUs
146 /sa1100 Files specific to Intel StrongARM SA1100 CPUs 146 /sa1100 Files specific to Intel StrongARM SA1100 CPUs
147 /lib Architecture specific library files 147 /lib Architecture specific library files
148 /avr32 Files generic to AVR32 architecture 148 /avr32 Files generic to AVR32 architecture
149 /cpu CPU specific files 149 /cpu CPU specific files
150 /lib Architecture specific library files 150 /lib Architecture specific library files
151 /blackfin Files generic to Analog Devices Blackfin architecture 151 /blackfin Files generic to Analog Devices Blackfin architecture
152 /cpu CPU specific files 152 /cpu CPU specific files
153 /lib Architecture specific library files 153 /lib Architecture specific library files
154 /m68k Files generic to m68k architecture 154 /m68k Files generic to m68k architecture
155 /cpu CPU specific files 155 /cpu CPU specific files
156 /mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs 156 /mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs
157 /mcf5227x Files specific to Freescale ColdFire MCF5227x CPUs 157 /mcf5227x Files specific to Freescale ColdFire MCF5227x CPUs
158 /mcf532x Files specific to Freescale ColdFire MCF5329 CPUs 158 /mcf532x Files specific to Freescale ColdFire MCF5329 CPUs
159 /mcf5445x Files specific to Freescale ColdFire MCF5445x CPUs 159 /mcf5445x Files specific to Freescale ColdFire MCF5445x CPUs
160 /mcf547x_8x Files specific to Freescale ColdFire MCF547x_8x CPUs 160 /mcf547x_8x Files specific to Freescale ColdFire MCF547x_8x CPUs
161 /lib Architecture specific library files 161 /lib Architecture specific library files
162 /microblaze Files generic to microblaze architecture 162 /microblaze Files generic to microblaze architecture
163 /cpu CPU specific files 163 /cpu CPU specific files
164 /lib Architecture specific library files 164 /lib Architecture specific library files
165 /mips Files generic to MIPS architecture 165 /mips Files generic to MIPS architecture
166 /cpu CPU specific files 166 /cpu CPU specific files
167 /mips32 Files specific to MIPS32 CPUs 167 /mips32 Files specific to MIPS32 CPUs
168 /xburst Files specific to Ingenic XBurst CPUs 168 /xburst Files specific to Ingenic XBurst CPUs
169 /lib Architecture specific library files 169 /lib Architecture specific library files
170 /nds32 Files generic to NDS32 architecture 170 /nds32 Files generic to NDS32 architecture
171 /cpu CPU specific files 171 /cpu CPU specific files
172 /n1213 Files specific to Andes Technology N1213 CPUs 172 /n1213 Files specific to Andes Technology N1213 CPUs
173 /lib Architecture specific library files 173 /lib Architecture specific library files
174 /nios2 Files generic to Altera NIOS2 architecture 174 /nios2 Files generic to Altera NIOS2 architecture
175 /cpu CPU specific files 175 /cpu CPU specific files
176 /lib Architecture specific library files 176 /lib Architecture specific library files
177 /openrisc Files generic to OpenRISC architecture 177 /openrisc Files generic to OpenRISC architecture
178 /cpu CPU specific files 178 /cpu CPU specific files
179 /lib Architecture specific library files 179 /lib Architecture specific library files
180 /powerpc Files generic to PowerPC architecture 180 /powerpc Files generic to PowerPC architecture
181 /cpu CPU specific files 181 /cpu CPU specific files
182 /74xx_7xx Files specific to Freescale MPC74xx and 7xx CPUs 182 /74xx_7xx Files specific to Freescale MPC74xx and 7xx CPUs
183 /mpc5xx Files specific to Freescale MPC5xx CPUs 183 /mpc5xx Files specific to Freescale MPC5xx CPUs
184 /mpc5xxx Files specific to Freescale MPC5xxx CPUs 184 /mpc5xxx Files specific to Freescale MPC5xxx CPUs
185 /mpc8xx Files specific to Freescale MPC8xx CPUs 185 /mpc8xx Files specific to Freescale MPC8xx CPUs
186 /mpc824x Files specific to Freescale MPC824x CPUs 186 /mpc824x Files specific to Freescale MPC824x CPUs
187 /mpc8260 Files specific to Freescale MPC8260 CPUs 187 /mpc8260 Files specific to Freescale MPC8260 CPUs
188 /mpc85xx Files specific to Freescale MPC85xx CPUs 188 /mpc85xx Files specific to Freescale MPC85xx CPUs
189 /ppc4xx Files specific to AMCC PowerPC 4xx CPUs 189 /ppc4xx Files specific to AMCC PowerPC 4xx CPUs
190 /lib Architecture specific library files 190 /lib Architecture specific library files
191 /sh Files generic to SH architecture 191 /sh Files generic to SH architecture
192 /cpu CPU specific files 192 /cpu CPU specific files
193 /sh2 Files specific to sh2 CPUs 193 /sh2 Files specific to sh2 CPUs
194 /sh3 Files specific to sh3 CPUs 194 /sh3 Files specific to sh3 CPUs
195 /sh4 Files specific to sh4 CPUs 195 /sh4 Files specific to sh4 CPUs
196 /lib Architecture specific library files 196 /lib Architecture specific library files
197 /sparc Files generic to SPARC architecture 197 /sparc Files generic to SPARC architecture
198 /cpu CPU specific files 198 /cpu CPU specific files
199 /leon2 Files specific to Gaisler LEON2 SPARC CPU 199 /leon2 Files specific to Gaisler LEON2 SPARC CPU
200 /leon3 Files specific to Gaisler LEON3 SPARC CPU 200 /leon3 Files specific to Gaisler LEON3 SPARC CPU
201 /lib Architecture specific library files 201 /lib Architecture specific library files
202 /x86 Files generic to x86 architecture 202 /x86 Files generic to x86 architecture
203 /cpu CPU specific files 203 /cpu CPU specific files
204 /lib Architecture specific library files 204 /lib Architecture specific library files
205 /api Machine/arch independent API for external apps 205 /api Machine/arch independent API for external apps
206 /board Board dependent files 206 /board Board dependent files
207 /common Misc architecture independent functions 207 /common Misc architecture independent functions
208 /disk Code for disk drive partition handling 208 /disk Code for disk drive partition handling
209 /doc Documentation (don't expect too much) 209 /doc Documentation (don't expect too much)
210 /drivers Commonly used device drivers 210 /drivers Commonly used device drivers
211 /dts Contains Makefile for building internal U-Boot fdt. 211 /dts Contains Makefile for building internal U-Boot fdt.
212 /examples Example code for standalone applications, etc. 212 /examples Example code for standalone applications, etc.
213 /fs Filesystem code (cramfs, ext2, jffs2, etc.) 213 /fs Filesystem code (cramfs, ext2, jffs2, etc.)
214 /include Header Files 214 /include Header Files
215 /lib Files generic to all architectures 215 /lib Files generic to all architectures
216 /libfdt Library files to support flattened device trees 216 /libfdt Library files to support flattened device trees
217 /lzma Library files to support LZMA decompression 217 /lzma Library files to support LZMA decompression
218 /lzo Library files to support LZO decompression 218 /lzo Library files to support LZO decompression
219 /net Networking code 219 /net Networking code
220 /post Power On Self Test 220 /post Power On Self Test
221 /spl Secondary Program Loader framework 221 /spl Secondary Program Loader framework
222 /tools Tools to build S-Record or U-Boot images, etc. 222 /tools Tools to build S-Record or U-Boot images, etc.
223 223
224 Software Configuration: 224 Software Configuration:
225 ======================= 225 =======================
226 226
227 Configuration is usually done using C preprocessor defines; the 227 Configuration is usually done using C preprocessor defines; the
228 rationale behind that is to avoid dead code whenever possible. 228 rationale behind that is to avoid dead code whenever possible.
229 229
230 There are two classes of configuration variables: 230 There are two classes of configuration variables:
231 231
232 * Configuration _OPTIONS_: 232 * Configuration _OPTIONS_:
233 These are selectable by the user and have names beginning with 233 These are selectable by the user and have names beginning with
234 "CONFIG_". 234 "CONFIG_".
235 235
236 * Configuration _SETTINGS_: 236 * Configuration _SETTINGS_:
237 These depend on the hardware etc. and should not be meddled with if 237 These depend on the hardware etc. and should not be meddled with if
238 you don't know what you're doing; they have names beginning with 238 you don't know what you're doing; they have names beginning with
239 "CONFIG_SYS_". 239 "CONFIG_SYS_".
240 240
241 Later we will add a configuration tool - probably similar to or even 241 Later we will add a configuration tool - probably similar to or even
242 identical to what's used for the Linux kernel. Right now, we have to 242 identical to what's used for the Linux kernel. Right now, we have to
243 do the configuration by hand, which means creating some symbolic 243 do the configuration by hand, which means creating some symbolic
244 links and editing some configuration files. We use the TQM8xxL boards 244 links and editing some configuration files. We use the TQM8xxL boards
245 as an example here. 245 as an example here.
246 246
247 247
248 Selection of Processor Architecture and Board Type: 248 Selection of Processor Architecture and Board Type:
249 --------------------------------------------------- 249 ---------------------------------------------------
250 250
251 For all supported boards there are ready-to-use default 251 For all supported boards there are ready-to-use default
252 configurations available; just type "make <board_name>_config". 252 configurations available; just type "make <board_name>_config".
253 253
254 Example: For a TQM823L module type: 254 Example: For a TQM823L module type:
255 255
256 cd u-boot 256 cd u-boot
257 make TQM823L_config 257 make TQM823L_config
258 258
259 For the Cogent platform, you need to specify the CPU type as well; 259 For the Cogent platform, you need to specify the CPU type as well;
260 e.g. "make cogent_mpc8xx_config". And also configure the cogent 260 e.g. "make cogent_mpc8xx_config". And also configure the cogent
261 directory according to the instructions in cogent/README. 261 directory according to the instructions in cogent/README.
262 262
263 263
264 Configuration Options: 264 Configuration Options:
265 ---------------------- 265 ----------------------
266 266
267 Configuration depends on the combination of board and CPU type; all 267 Configuration depends on the combination of board and CPU type; all
268 such information is kept in a configuration file 268 such information is kept in a configuration file
269 "include/configs/<board_name>.h". 269 "include/configs/<board_name>.h".
270 270
271 Example: For a TQM823L module, all configuration settings are in 271 Example: For a TQM823L module, all configuration settings are in
272 "include/configs/TQM823L.h". 272 "include/configs/TQM823L.h".
273 273
274 274
275 Many of the options are named exactly as the corresponding Linux 275 Many of the options are named exactly as the corresponding Linux
276 kernel configuration options. The intention is to make it easier to 276 kernel configuration options. The intention is to make it easier to
277 build a config tool - later. 277 build a config tool - later.
278 278
279 279
280 The following options need to be configured: 280 The following options need to be configured:
281 281
282 - CPU Type: Define exactly one, e.g. CONFIG_MPC85XX. 282 - CPU Type: Define exactly one, e.g. CONFIG_MPC85XX.
283 283
284 - Board Type: Define exactly one, e.g. CONFIG_MPC8540ADS. 284 - Board Type: Define exactly one, e.g. CONFIG_MPC8540ADS.
285 285
286 - CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined) 286 - CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
287 Define exactly one, e.g. CONFIG_ATSTK1002 287 Define exactly one, e.g. CONFIG_ATSTK1002
288 288
289 - CPU Module Type: (if CONFIG_COGENT is defined) 289 - CPU Module Type: (if CONFIG_COGENT is defined)
290 Define exactly one of 290 Define exactly one of
291 CONFIG_CMA286_60_OLD 291 CONFIG_CMA286_60_OLD
292 --- FIXME --- not tested yet: 292 --- FIXME --- not tested yet:
293 CONFIG_CMA286_60, CONFIG_CMA286_21, CONFIG_CMA286_60P, 293 CONFIG_CMA286_60, CONFIG_CMA286_21, CONFIG_CMA286_60P,
294 CONFIG_CMA287_23, CONFIG_CMA287_50 294 CONFIG_CMA287_23, CONFIG_CMA287_50
295 295
296 - Motherboard Type: (if CONFIG_COGENT is defined) 296 - Motherboard Type: (if CONFIG_COGENT is defined)
297 Define exactly one of 297 Define exactly one of
298 CONFIG_CMA101, CONFIG_CMA102 298 CONFIG_CMA101, CONFIG_CMA102
299 299
300 - Motherboard I/O Modules: (if CONFIG_COGENT is defined) 300 - Motherboard I/O Modules: (if CONFIG_COGENT is defined)
301 Define one or more of 301 Define one or more of
302 CONFIG_CMA302 302 CONFIG_CMA302
303 303
304 - Motherboard Options: (if CONFIG_CMA101 or CONFIG_CMA102 are defined) 304 - Motherboard Options: (if CONFIG_CMA101 or CONFIG_CMA102 are defined)
305 Define one or more of 305 Define one or more of
306 CONFIG_LCD_HEARTBEAT - update a character position on 306 CONFIG_LCD_HEARTBEAT - update a character position on
307 the LCD display every second with 307 the LCD display every second with
308 a "rotator" |\-/|\-/ 308 a "rotator" |\-/|\-/
309 309
310 - Board flavour: (if CONFIG_MPC8260ADS is defined) 310 - Board flavour: (if CONFIG_MPC8260ADS is defined)
311 CONFIG_ADSTYPE 311 CONFIG_ADSTYPE
312 Possible values are: 312 Possible values are:
313 CONFIG_SYS_8260ADS - original MPC8260ADS 313 CONFIG_SYS_8260ADS - original MPC8260ADS
314 CONFIG_SYS_8266ADS - MPC8266ADS 314 CONFIG_SYS_8266ADS - MPC8266ADS
315 CONFIG_SYS_PQ2FADS - PQ2FADS-ZU or PQ2FADS-VR 315 CONFIG_SYS_PQ2FADS - PQ2FADS-ZU or PQ2FADS-VR
316 CONFIG_SYS_8272ADS - MPC8272ADS 316 CONFIG_SYS_8272ADS - MPC8272ADS
317 317
318 - Marvell Family Member 318 - Marvell Family Member
319 CONFIG_SYS_MVFS - define it if you want to enable 319 CONFIG_SYS_MVFS - define it if you want to enable
320 multiple fs option at one time 320 multiple fs option at one time
321 for marvell soc family 321 for marvell soc family
322 322
323 - MPC824X Family Member (if CONFIG_MPC824X is defined) 323 - MPC824X Family Member (if CONFIG_MPC824X is defined)
324 Define exactly one of 324 Define exactly one of
325 CONFIG_MPC8240, CONFIG_MPC8245 325 CONFIG_MPC8240, CONFIG_MPC8245
326 326
327 - 8xx CPU Options: (if using an MPC8xx CPU) 327 - 8xx CPU Options: (if using an MPC8xx CPU)
328 CONFIG_8xx_GCLK_FREQ - deprecated: CPU clock if 328 CONFIG_8xx_GCLK_FREQ - deprecated: CPU clock if
329 get_gclk_freq() cannot work 329 get_gclk_freq() cannot work
330 e.g. if there is no 32KHz 330 e.g. if there is no 32KHz
331 reference PIT/RTC clock 331 reference PIT/RTC clock
332 CONFIG_8xx_OSCLK - PLL input clock (either EXTCLK 332 CONFIG_8xx_OSCLK - PLL input clock (either EXTCLK
333 or XTAL/EXTAL) 333 or XTAL/EXTAL)
334 334
335 - 859/866/885 CPU options: (if using a MPC859 or MPC866 or MPC885 CPU): 335 - 859/866/885 CPU options: (if using a MPC859 or MPC866 or MPC885 CPU):
336 CONFIG_SYS_8xx_CPUCLK_MIN 336 CONFIG_SYS_8xx_CPUCLK_MIN
337 CONFIG_SYS_8xx_CPUCLK_MAX 337 CONFIG_SYS_8xx_CPUCLK_MAX
338 CONFIG_8xx_CPUCLK_DEFAULT 338 CONFIG_8xx_CPUCLK_DEFAULT
339 See doc/README.MPC866 339 See doc/README.MPC866
340 340
341 CONFIG_SYS_MEASURE_CPUCLK 341 CONFIG_SYS_MEASURE_CPUCLK
342 342
343 Define this to measure the actual CPU clock instead 343 Define this to measure the actual CPU clock instead
344 of relying on the correctness of the configured 344 of relying on the correctness of the configured
345 values. Mostly useful for board bringup to make sure 345 values. Mostly useful for board bringup to make sure
346 the PLL is locked at the intended frequency. Note 346 the PLL is locked at the intended frequency. Note
347 that this requires a (stable) reference clock (32 kHz 347 that this requires a (stable) reference clock (32 kHz
348 RTC clock or CONFIG_SYS_8XX_XIN) 348 RTC clock or CONFIG_SYS_8XX_XIN)
349 349
350 CONFIG_SYS_DELAYED_ICACHE 350 CONFIG_SYS_DELAYED_ICACHE
351 351
352 Define this option if you want to enable the 352 Define this option if you want to enable the
353 ICache only when Code runs from RAM. 353 ICache only when Code runs from RAM.
354 354
355 - 85xx CPU Options: 355 - 85xx CPU Options:
356 CONFIG_SYS_PPC64 356 CONFIG_SYS_PPC64
357 357
358 Specifies that the core is a 64-bit PowerPC implementation (implements 358 Specifies that the core is a 64-bit PowerPC implementation (implements
359 the "64" category of the Power ISA). This is necessary for ePAPR 359 the "64" category of the Power ISA). This is necessary for ePAPR
360 compliance, among other possible reasons. 360 compliance, among other possible reasons.
361 361
362 CONFIG_SYS_FSL_TBCLK_DIV 362 CONFIG_SYS_FSL_TBCLK_DIV
363 363
364 Defines the core time base clock divider ratio compared to the 364 Defines the core time base clock divider ratio compared to the
365 system clock. On most PQ3 devices this is 8, on newer QorIQ 365 system clock. On most PQ3 devices this is 8, on newer QorIQ
366 devices it can be 16 or 32. The ratio varies from SoC to Soc. 366 devices it can be 16 or 32. The ratio varies from SoC to Soc.
367 367
368 CONFIG_SYS_FSL_PCIE_COMPAT 368 CONFIG_SYS_FSL_PCIE_COMPAT
369 369
370 Defines the string to utilize when trying to match PCIe device 370 Defines the string to utilize when trying to match PCIe device
371 tree nodes for the given platform. 371 tree nodes for the given platform.
372 372
373 CONFIG_SYS_PPC_E500_DEBUG_TLB 373 CONFIG_SYS_PPC_E500_DEBUG_TLB
374 374
375 Enables a temporary TLB entry to be used during boot to work 375 Enables a temporary TLB entry to be used during boot to work
376 around limitations in e500v1 and e500v2 external debugger 376 around limitations in e500v1 and e500v2 external debugger
377 support. This reduces the portions of the boot code where 377 support. This reduces the portions of the boot code where
378 breakpoints and single stepping do not work. The value of this 378 breakpoints and single stepping do not work. The value of this
379 symbol should be set to the TLB1 entry to be used for this 379 symbol should be set to the TLB1 entry to be used for this
380 purpose. 380 purpose.
381 381
382 CONFIG_SYS_FSL_ERRATUM_A004510 382 CONFIG_SYS_FSL_ERRATUM_A004510
383 383
384 Enables a workaround for erratum A004510. If set, 384 Enables a workaround for erratum A004510. If set,
385 then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and 385 then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and
386 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set. 386 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
387 387
388 CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 388 CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
389 CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional) 389 CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional)
390 390
391 Defines one or two SoC revisions (low 8 bits of SVR) 391 Defines one or two SoC revisions (low 8 bits of SVR)
392 for which the A004510 workaround should be applied. 392 for which the A004510 workaround should be applied.
393 393
394 The rest of SVR is either not relevant to the decision 394 The rest of SVR is either not relevant to the decision
395 of whether the erratum is present (e.g. p2040 versus 395 of whether the erratum is present (e.g. p2040 versus
396 p2041) or is implied by the build target, which controls 396 p2041) or is implied by the build target, which controls
397 whether CONFIG_SYS_FSL_ERRATUM_A004510 is set. 397 whether CONFIG_SYS_FSL_ERRATUM_A004510 is set.
398 398
399 See Freescale App Note 4493 for more information about 399 See Freescale App Note 4493 for more information about
400 this erratum. 400 this erratum.
401 401
402 CONFIG_A003399_NOR_WORKAROUND 402 CONFIG_A003399_NOR_WORKAROUND
403 Enables a workaround for IFC erratum A003399. It is only 403 Enables a workaround for IFC erratum A003399. It is only
404 requred during NOR boot. 404 requred during NOR boot.
405 405
406 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 406 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
407 407
408 This is the value to write into CCSR offset 0x18600 408 This is the value to write into CCSR offset 0x18600
409 according to the A004510 workaround. 409 according to the A004510 workaround.
410 410
411 CONFIG_SYS_FSL_DSP_DDR_ADDR 411 CONFIG_SYS_FSL_DSP_DDR_ADDR
412 This value denotes start offset of DDR memory which is 412 This value denotes start offset of DDR memory which is
413 connected exclusively to the DSP cores. 413 connected exclusively to the DSP cores.
414 414
415 CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 415 CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
416 This value denotes start offset of M2 memory 416 This value denotes start offset of M2 memory
417 which is directly connected to the DSP core. 417 which is directly connected to the DSP core.
418 418
419 CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 419 CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
420 This value denotes start offset of M3 memory which is directly 420 This value denotes start offset of M3 memory which is directly
421 connected to the DSP core. 421 connected to the DSP core.
422 422
423 CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 423 CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
424 This value denotes start offset of DSP CCSR space. 424 This value denotes start offset of DSP CCSR space.
425 425
426 CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
427 Single Source Clock is clocking mode present in some of FSL SoC's.
428 In this mode, a single differential clock is used to supply
429 clocks to the sysclock, ddrclock and usbclock.
430
426 - Generic CPU options: 431 - Generic CPU options:
427 CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN 432 CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
428 433
429 Defines the endianess of the CPU. Implementation of those 434 Defines the endianess of the CPU. Implementation of those
430 values is arch specific. 435 values is arch specific.
431 436
432 CONFIG_SYS_FSL_DDR 437 CONFIG_SYS_FSL_DDR
433 Freescale DDR driver in use. This type of DDR controller is 438 Freescale DDR driver in use. This type of DDR controller is
434 found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core 439 found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
435 SoCs. 440 SoCs.
436 441
437 CONFIG_SYS_FSL_DDR_ADDR 442 CONFIG_SYS_FSL_DDR_ADDR
438 Freescale DDR memory-mapped register base. 443 Freescale DDR memory-mapped register base.
439 444
440 CONFIG_SYS_FSL_DDR_EMU 445 CONFIG_SYS_FSL_DDR_EMU
441 Specify emulator support for DDR. Some DDR features such as 446 Specify emulator support for DDR. Some DDR features such as
442 deskew training are not available. 447 deskew training are not available.
443 448
444 CONFIG_SYS_FSL_DDRC_GEN1 449 CONFIG_SYS_FSL_DDRC_GEN1
445 Freescale DDR1 controller. 450 Freescale DDR1 controller.
446 451
447 CONFIG_SYS_FSL_DDRC_GEN2 452 CONFIG_SYS_FSL_DDRC_GEN2
448 Freescale DDR2 controller. 453 Freescale DDR2 controller.
449 454
450 CONFIG_SYS_FSL_DDRC_GEN3 455 CONFIG_SYS_FSL_DDRC_GEN3
451 Freescale DDR3 controller. 456 Freescale DDR3 controller.
452 457
453 CONFIG_SYS_FSL_DDRC_ARM_GEN3 458 CONFIG_SYS_FSL_DDRC_ARM_GEN3
454 Freescale DDR3 controller for ARM-based SoCs. 459 Freescale DDR3 controller for ARM-based SoCs.
455 460
456 CONFIG_SYS_FSL_DDR1 461 CONFIG_SYS_FSL_DDR1
457 Board config to use DDR1. It can be enabled for SoCs with 462 Board config to use DDR1. It can be enabled for SoCs with
458 Freescale DDR1 or DDR2 controllers, depending on the board 463 Freescale DDR1 or DDR2 controllers, depending on the board
459 implemetation. 464 implemetation.
460 465
461 CONFIG_SYS_FSL_DDR2 466 CONFIG_SYS_FSL_DDR2
462 Board config to use DDR2. It can be eanbeld for SoCs with 467 Board config to use DDR2. It can be eanbeld for SoCs with
463 Freescale DDR2 or DDR3 controllers, depending on the board 468 Freescale DDR2 or DDR3 controllers, depending on the board
464 implementation. 469 implementation.
465 470
466 CONFIG_SYS_FSL_DDR3 471 CONFIG_SYS_FSL_DDR3
467 Board config to use DDR3. It can be enabled for SoCs with 472 Board config to use DDR3. It can be enabled for SoCs with
468 Freescale DDR3 controllers. 473 Freescale DDR3 controllers.
469 474
470 - Intel Monahans options: 475 - Intel Monahans options:
471 CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 476 CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
472 477
473 Defines the Monahans run mode to oscillator 478 Defines the Monahans run mode to oscillator
474 ratio. Valid values are 8, 16, 24, 31. The core 479 ratio. Valid values are 8, 16, 24, 31. The core
475 frequency is this value multiplied by 13 MHz. 480 frequency is this value multiplied by 13 MHz.
476 481
477 CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 482 CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
478 483
479 Defines the Monahans turbo mode to oscillator 484 Defines the Monahans turbo mode to oscillator
480 ratio. Valid values are 1 (default if undefined) and 485 ratio. Valid values are 1 (default if undefined) and
481 2. The core frequency as calculated above is multiplied 486 2. The core frequency as calculated above is multiplied
482 by this value. 487 by this value.
483 488
484 - MIPS CPU options: 489 - MIPS CPU options:
485 CONFIG_SYS_INIT_SP_OFFSET 490 CONFIG_SYS_INIT_SP_OFFSET
486 491
487 Offset relative to CONFIG_SYS_SDRAM_BASE for initial stack 492 Offset relative to CONFIG_SYS_SDRAM_BASE for initial stack
488 pointer. This is needed for the temporary stack before 493 pointer. This is needed for the temporary stack before
489 relocation. 494 relocation.
490 495
491 CONFIG_SYS_MIPS_CACHE_MODE 496 CONFIG_SYS_MIPS_CACHE_MODE
492 497
493 Cache operation mode for the MIPS CPU. 498 Cache operation mode for the MIPS CPU.
494 See also arch/mips/include/asm/mipsregs.h. 499 See also arch/mips/include/asm/mipsregs.h.
495 Possible values are: 500 Possible values are:
496 CONF_CM_CACHABLE_NO_WA 501 CONF_CM_CACHABLE_NO_WA
497 CONF_CM_CACHABLE_WA 502 CONF_CM_CACHABLE_WA
498 CONF_CM_UNCACHED 503 CONF_CM_UNCACHED
499 CONF_CM_CACHABLE_NONCOHERENT 504 CONF_CM_CACHABLE_NONCOHERENT
500 CONF_CM_CACHABLE_CE 505 CONF_CM_CACHABLE_CE
501 CONF_CM_CACHABLE_COW 506 CONF_CM_CACHABLE_COW
502 CONF_CM_CACHABLE_CUW 507 CONF_CM_CACHABLE_CUW
503 CONF_CM_CACHABLE_ACCELERATED 508 CONF_CM_CACHABLE_ACCELERATED
504 509
505 CONFIG_SYS_XWAY_EBU_BOOTCFG 510 CONFIG_SYS_XWAY_EBU_BOOTCFG
506 511
507 Special option for Lantiq XWAY SoCs for booting from NOR flash. 512 Special option for Lantiq XWAY SoCs for booting from NOR flash.
508 See also arch/mips/cpu/mips32/start.S. 513 See also arch/mips/cpu/mips32/start.S.
509 514
510 CONFIG_XWAY_SWAP_BYTES 515 CONFIG_XWAY_SWAP_BYTES
511 516
512 Enable compilation of tools/xway-swap-bytes needed for Lantiq 517 Enable compilation of tools/xway-swap-bytes needed for Lantiq
513 XWAY SoCs for booting from NOR flash. The U-Boot image needs to 518 XWAY SoCs for booting from NOR flash. The U-Boot image needs to
514 be swapped if a flash programmer is used. 519 be swapped if a flash programmer is used.
515 520
516 - ARM options: 521 - ARM options:
517 CONFIG_SYS_EXCEPTION_VECTORS_HIGH 522 CONFIG_SYS_EXCEPTION_VECTORS_HIGH
518 523
519 Select high exception vectors of the ARM core, e.g., do not 524 Select high exception vectors of the ARM core, e.g., do not
520 clear the V bit of the c1 register of CP15. 525 clear the V bit of the c1 register of CP15.
521 526
522 CONFIG_SYS_THUMB_BUILD 527 CONFIG_SYS_THUMB_BUILD
523 528
524 Use this flag to build U-Boot using the Thumb instruction 529 Use this flag to build U-Boot using the Thumb instruction
525 set for ARM architectures. Thumb instruction set provides 530 set for ARM architectures. Thumb instruction set provides
526 better code density. For ARM architectures that support 531 better code density. For ARM architectures that support
527 Thumb2 this flag will result in Thumb2 code generated by 532 Thumb2 this flag will result in Thumb2 code generated by
528 GCC. 533 GCC.
529 534
530 CONFIG_ARM_ERRATA_716044 535 CONFIG_ARM_ERRATA_716044
531 CONFIG_ARM_ERRATA_742230 536 CONFIG_ARM_ERRATA_742230
532 CONFIG_ARM_ERRATA_743622 537 CONFIG_ARM_ERRATA_743622
533 CONFIG_ARM_ERRATA_751472 538 CONFIG_ARM_ERRATA_751472
534 539
535 If set, the workarounds for these ARM errata are applied early 540 If set, the workarounds for these ARM errata are applied early
536 during U-Boot startup. Note that these options force the 541 during U-Boot startup. Note that these options force the
537 workarounds to be applied; no CPU-type/version detection 542 workarounds to be applied; no CPU-type/version detection
538 exists, unlike the similar options in the Linux kernel. Do not 543 exists, unlike the similar options in the Linux kernel. Do not
539 set these options unless they apply! 544 set these options unless they apply!
540 545
541 - CPU timer options: 546 - CPU timer options:
542 CONFIG_SYS_HZ 547 CONFIG_SYS_HZ
543 548
544 The frequency of the timer returned by get_timer(). 549 The frequency of the timer returned by get_timer().
545 get_timer() must operate in milliseconds and this CONFIG 550 get_timer() must operate in milliseconds and this CONFIG
546 option must be set to 1000. 551 option must be set to 1000.
547 552
548 - Linux Kernel Interface: 553 - Linux Kernel Interface:
549 CONFIG_CLOCKS_IN_MHZ 554 CONFIG_CLOCKS_IN_MHZ
550 555
551 U-Boot stores all clock information in Hz 556 U-Boot stores all clock information in Hz
552 internally. For binary compatibility with older Linux 557 internally. For binary compatibility with older Linux
553 kernels (which expect the clocks passed in the 558 kernels (which expect the clocks passed in the
554 bd_info data to be in MHz) the environment variable 559 bd_info data to be in MHz) the environment variable
555 "clocks_in_mhz" can be defined so that U-Boot 560 "clocks_in_mhz" can be defined so that U-Boot
556 converts clock data to MHZ before passing it to the 561 converts clock data to MHZ before passing it to the
557 Linux kernel. 562 Linux kernel.
558 When CONFIG_CLOCKS_IN_MHZ is defined, a definition of 563 When CONFIG_CLOCKS_IN_MHZ is defined, a definition of
559 "clocks_in_mhz=1" is automatically included in the 564 "clocks_in_mhz=1" is automatically included in the
560 default environment. 565 default environment.
561 566
562 CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only] 567 CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only]
563 568
564 When transferring memsize parameter to linux, some versions 569 When transferring memsize parameter to linux, some versions
565 expect it to be in bytes, others in MB. 570 expect it to be in bytes, others in MB.
566 Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes. 571 Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
567 572
568 CONFIG_OF_LIBFDT 573 CONFIG_OF_LIBFDT
569 574
570 New kernel versions are expecting firmware settings to be 575 New kernel versions are expecting firmware settings to be
571 passed using flattened device trees (based on open firmware 576 passed using flattened device trees (based on open firmware
572 concepts). 577 concepts).
573 578
574 CONFIG_OF_LIBFDT 579 CONFIG_OF_LIBFDT
575 * New libfdt-based support 580 * New libfdt-based support
576 * Adds the "fdt" command 581 * Adds the "fdt" command
577 * The bootm command automatically updates the fdt 582 * The bootm command automatically updates the fdt
578 583
579 OF_CPU - The proper name of the cpus node (only required for 584 OF_CPU - The proper name of the cpus node (only required for
580 MPC512X and MPC5xxx based boards). 585 MPC512X and MPC5xxx based boards).
581 OF_SOC - The proper name of the soc node (only required for 586 OF_SOC - The proper name of the soc node (only required for
582 MPC512X and MPC5xxx based boards). 587 MPC512X and MPC5xxx based boards).
583 OF_TBCLK - The timebase frequency. 588 OF_TBCLK - The timebase frequency.
584 OF_STDOUT_PATH - The path to the console device 589 OF_STDOUT_PATH - The path to the console device
585 590
586 boards with QUICC Engines require OF_QE to set UCC MAC 591 boards with QUICC Engines require OF_QE to set UCC MAC
587 addresses 592 addresses
588 593
589 CONFIG_OF_BOARD_SETUP 594 CONFIG_OF_BOARD_SETUP
590 595
591 Board code has addition modification that it wants to make 596 Board code has addition modification that it wants to make
592 to the flat device tree before handing it off to the kernel 597 to the flat device tree before handing it off to the kernel
593 598
594 CONFIG_OF_BOOT_CPU 599 CONFIG_OF_BOOT_CPU
595 600
596 This define fills in the correct boot CPU in the boot 601 This define fills in the correct boot CPU in the boot
597 param header, the default value is zero if undefined. 602 param header, the default value is zero if undefined.
598 603
599 CONFIG_OF_IDE_FIXUP 604 CONFIG_OF_IDE_FIXUP
600 605
601 U-Boot can detect if an IDE device is present or not. 606 U-Boot can detect if an IDE device is present or not.
602 If not, and this new config option is activated, U-Boot 607 If not, and this new config option is activated, U-Boot
603 removes the ATA node from the DTS before booting Linux, 608 removes the ATA node from the DTS before booting Linux,
604 so the Linux IDE driver does not probe the device and 609 so the Linux IDE driver does not probe the device and
605 crash. This is needed for buggy hardware (uc101) where 610 crash. This is needed for buggy hardware (uc101) where
606 no pull down resistor is connected to the signal IDE5V_DD7. 611 no pull down resistor is connected to the signal IDE5V_DD7.
607 612
608 CONFIG_MACH_TYPE [relevant for ARM only][mandatory] 613 CONFIG_MACH_TYPE [relevant for ARM only][mandatory]
609 614
610 This setting is mandatory for all boards that have only one 615 This setting is mandatory for all boards that have only one
611 machine type and must be used to specify the machine type 616 machine type and must be used to specify the machine type
612 number as it appears in the ARM machine registry 617 number as it appears in the ARM machine registry
613 (see http://www.arm.linux.org.uk/developer/machines/). 618 (see http://www.arm.linux.org.uk/developer/machines/).
614 Only boards that have multiple machine types supported 619 Only boards that have multiple machine types supported
615 in a single configuration file and the machine type is 620 in a single configuration file and the machine type is
616 runtime discoverable, do not have to use this setting. 621 runtime discoverable, do not have to use this setting.
617 622
618 - vxWorks boot parameters: 623 - vxWorks boot parameters:
619 624
620 bootvx constructs a valid bootline using the following 625 bootvx constructs a valid bootline using the following
621 environments variables: bootfile, ipaddr, serverip, hostname. 626 environments variables: bootfile, ipaddr, serverip, hostname.
622 It loads the vxWorks image pointed bootfile. 627 It loads the vxWorks image pointed bootfile.
623 628
624 CONFIG_SYS_VXWORKS_BOOT_DEVICE - The vxworks device name 629 CONFIG_SYS_VXWORKS_BOOT_DEVICE - The vxworks device name
625 CONFIG_SYS_VXWORKS_MAC_PTR - Ethernet 6 byte MA -address 630 CONFIG_SYS_VXWORKS_MAC_PTR - Ethernet 6 byte MA -address
626 CONFIG_SYS_VXWORKS_SERVERNAME - Name of the server 631 CONFIG_SYS_VXWORKS_SERVERNAME - Name of the server
627 CONFIG_SYS_VXWORKS_BOOT_ADDR - Address of boot parameters 632 CONFIG_SYS_VXWORKS_BOOT_ADDR - Address of boot parameters
628 633
629 CONFIG_SYS_VXWORKS_ADD_PARAMS 634 CONFIG_SYS_VXWORKS_ADD_PARAMS
630 635
631 Add it at the end of the bootline. E.g "u=username pw=secret" 636 Add it at the end of the bootline. E.g "u=username pw=secret"
632 637
633 Note: If a "bootargs" environment is defined, it will overwride 638 Note: If a "bootargs" environment is defined, it will overwride
634 the defaults discussed just above. 639 the defaults discussed just above.
635 640
636 - Cache Configuration: 641 - Cache Configuration:
637 CONFIG_SYS_ICACHE_OFF - Do not enable instruction cache in U-Boot 642 CONFIG_SYS_ICACHE_OFF - Do not enable instruction cache in U-Boot
638 CONFIG_SYS_DCACHE_OFF - Do not enable data cache in U-Boot 643 CONFIG_SYS_DCACHE_OFF - Do not enable data cache in U-Boot
639 CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot 644 CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot
640 645
641 - Cache Configuration for ARM: 646 - Cache Configuration for ARM:
642 CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache 647 CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache
643 controller 648 controller
644 CONFIG_SYS_PL310_BASE - Physical base address of PL310 649 CONFIG_SYS_PL310_BASE - Physical base address of PL310
645 controller register space 650 controller register space
646 651
647 - Serial Ports: 652 - Serial Ports:
648 CONFIG_PL010_SERIAL 653 CONFIG_PL010_SERIAL
649 654
650 Define this if you want support for Amba PrimeCell PL010 UARTs. 655 Define this if you want support for Amba PrimeCell PL010 UARTs.
651 656
652 CONFIG_PL011_SERIAL 657 CONFIG_PL011_SERIAL
653 658
654 Define this if you want support for Amba PrimeCell PL011 UARTs. 659 Define this if you want support for Amba PrimeCell PL011 UARTs.
655 660
656 CONFIG_PL011_CLOCK 661 CONFIG_PL011_CLOCK
657 662
658 If you have Amba PrimeCell PL011 UARTs, set this variable to 663 If you have Amba PrimeCell PL011 UARTs, set this variable to
659 the clock speed of the UARTs. 664 the clock speed of the UARTs.
660 665
661 CONFIG_PL01x_PORTS 666 CONFIG_PL01x_PORTS
662 667
663 If you have Amba PrimeCell PL010 or PL011 UARTs on your board, 668 If you have Amba PrimeCell PL010 or PL011 UARTs on your board,
664 define this to a list of base addresses for each (supported) 669 define this to a list of base addresses for each (supported)
665 port. See e.g. include/configs/versatile.h 670 port. See e.g. include/configs/versatile.h
666 671
667 CONFIG_PL011_SERIAL_RLCR 672 CONFIG_PL011_SERIAL_RLCR
668 673
669 Some vendor versions of PL011 serial ports (e.g. ST-Ericsson U8500) 674 Some vendor versions of PL011 serial ports (e.g. ST-Ericsson U8500)
670 have separate receive and transmit line control registers. Set 675 have separate receive and transmit line control registers. Set
671 this variable to initialize the extra register. 676 this variable to initialize the extra register.
672 677
673 CONFIG_PL011_SERIAL_FLUSH_ON_INIT 678 CONFIG_PL011_SERIAL_FLUSH_ON_INIT
674 679
675 On some platforms (e.g. U8500) U-Boot is loaded by a second stage 680 On some platforms (e.g. U8500) U-Boot is loaded by a second stage
676 boot loader that has already initialized the UART. Define this 681 boot loader that has already initialized the UART. Define this
677 variable to flush the UART at init time. 682 variable to flush the UART at init time.
678 683
679 684
680 - Console Interface: 685 - Console Interface:
681 Depending on board, define exactly one serial port 686 Depending on board, define exactly one serial port
682 (like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2, 687 (like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2,
683 CONFIG_8xx_CONS_SCC1, ...), or switch off the serial 688 CONFIG_8xx_CONS_SCC1, ...), or switch off the serial
684 console by defining CONFIG_8xx_CONS_NONE 689 console by defining CONFIG_8xx_CONS_NONE
685 690
686 Note: if CONFIG_8xx_CONS_NONE is defined, the serial 691 Note: if CONFIG_8xx_CONS_NONE is defined, the serial
687 port routines must be defined elsewhere 692 port routines must be defined elsewhere
688 (i.e. serial_init(), serial_getc(), ...) 693 (i.e. serial_init(), serial_getc(), ...)
689 694
690 CONFIG_CFB_CONSOLE 695 CONFIG_CFB_CONSOLE
691 Enables console device for a color framebuffer. Needs following 696 Enables console device for a color framebuffer. Needs following
692 defines (cf. smiLynxEM, i8042) 697 defines (cf. smiLynxEM, i8042)
693 VIDEO_FB_LITTLE_ENDIAN graphic memory organisation 698 VIDEO_FB_LITTLE_ENDIAN graphic memory organisation
694 (default big endian) 699 (default big endian)
695 VIDEO_HW_RECTFILL graphic chip supports 700 VIDEO_HW_RECTFILL graphic chip supports
696 rectangle fill 701 rectangle fill
697 (cf. smiLynxEM) 702 (cf. smiLynxEM)
698 VIDEO_HW_BITBLT graphic chip supports 703 VIDEO_HW_BITBLT graphic chip supports
699 bit-blit (cf. smiLynxEM) 704 bit-blit (cf. smiLynxEM)
700 VIDEO_VISIBLE_COLS visible pixel columns 705 VIDEO_VISIBLE_COLS visible pixel columns
701 (cols=pitch) 706 (cols=pitch)
702 VIDEO_VISIBLE_ROWS visible pixel rows 707 VIDEO_VISIBLE_ROWS visible pixel rows
703 VIDEO_PIXEL_SIZE bytes per pixel 708 VIDEO_PIXEL_SIZE bytes per pixel
704 VIDEO_DATA_FORMAT graphic data format 709 VIDEO_DATA_FORMAT graphic data format
705 (0-5, cf. cfb_console.c) 710 (0-5, cf. cfb_console.c)
706 VIDEO_FB_ADRS framebuffer address 711 VIDEO_FB_ADRS framebuffer address
707 VIDEO_KBD_INIT_FCT keyboard int fct 712 VIDEO_KBD_INIT_FCT keyboard int fct
708 (i.e. i8042_kbd_init()) 713 (i.e. i8042_kbd_init())
709 VIDEO_TSTC_FCT test char fct 714 VIDEO_TSTC_FCT test char fct
710 (i.e. i8042_tstc) 715 (i.e. i8042_tstc)
711 VIDEO_GETC_FCT get char fct 716 VIDEO_GETC_FCT get char fct
712 (i.e. i8042_getc) 717 (i.e. i8042_getc)
713 CONFIG_CONSOLE_CURSOR cursor drawing on/off 718 CONFIG_CONSOLE_CURSOR cursor drawing on/off
714 (requires blink timer 719 (requires blink timer
715 cf. i8042.c) 720 cf. i8042.c)
716 CONFIG_SYS_CONSOLE_BLINK_COUNT blink interval (cf. i8042.c) 721 CONFIG_SYS_CONSOLE_BLINK_COUNT blink interval (cf. i8042.c)
717 CONFIG_CONSOLE_TIME display time/date info in 722 CONFIG_CONSOLE_TIME display time/date info in
718 upper right corner 723 upper right corner
719 (requires CONFIG_CMD_DATE) 724 (requires CONFIG_CMD_DATE)
720 CONFIG_VIDEO_LOGO display Linux logo in 725 CONFIG_VIDEO_LOGO display Linux logo in
721 upper left corner 726 upper left corner
722 CONFIG_VIDEO_BMP_LOGO use bmp_logo.h instead of 727 CONFIG_VIDEO_BMP_LOGO use bmp_logo.h instead of
723 linux_logo.h for logo. 728 linux_logo.h for logo.
724 Requires CONFIG_VIDEO_LOGO 729 Requires CONFIG_VIDEO_LOGO
725 CONFIG_CONSOLE_EXTRA_INFO 730 CONFIG_CONSOLE_EXTRA_INFO
726 additional board info beside 731 additional board info beside
727 the logo 732 the logo
728 733
729 When CONFIG_CFB_CONSOLE_ANSI is defined, console will support 734 When CONFIG_CFB_CONSOLE_ANSI is defined, console will support
730 a limited number of ANSI escape sequences (cursor control, 735 a limited number of ANSI escape sequences (cursor control,
731 erase functions and limited graphics rendition control). 736 erase functions and limited graphics rendition control).
732 737
733 When CONFIG_CFB_CONSOLE is defined, video console is 738 When CONFIG_CFB_CONSOLE is defined, video console is
734 default i/o. Serial console can be forced with 739 default i/o. Serial console can be forced with
735 environment 'console=serial'. 740 environment 'console=serial'.
736 741
737 When CONFIG_SILENT_CONSOLE is defined, all console 742 When CONFIG_SILENT_CONSOLE is defined, all console
738 messages (by U-Boot and Linux!) can be silenced with 743 messages (by U-Boot and Linux!) can be silenced with
739 the "silent" environment variable. See 744 the "silent" environment variable. See
740 doc/README.silent for more information. 745 doc/README.silent for more information.
741 746
742 CONFIG_SYS_CONSOLE_BG_COL: define the backgroundcolor, default 747 CONFIG_SYS_CONSOLE_BG_COL: define the backgroundcolor, default
743 is 0x00. 748 is 0x00.
744 CONFIG_SYS_CONSOLE_FG_COL: define the foregroundcolor, default 749 CONFIG_SYS_CONSOLE_FG_COL: define the foregroundcolor, default
745 is 0xa0. 750 is 0xa0.
746 751
747 - Console Baudrate: 752 - Console Baudrate:
748 CONFIG_BAUDRATE - in bps 753 CONFIG_BAUDRATE - in bps
749 Select one of the baudrates listed in 754 Select one of the baudrates listed in
750 CONFIG_SYS_BAUDRATE_TABLE, see below. 755 CONFIG_SYS_BAUDRATE_TABLE, see below.
751 CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale 756 CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale
752 757
753 - Console Rx buffer length 758 - Console Rx buffer length
754 With CONFIG_SYS_SMC_RXBUFLEN it is possible to define 759 With CONFIG_SYS_SMC_RXBUFLEN it is possible to define
755 the maximum receive buffer length for the SMC. 760 the maximum receive buffer length for the SMC.
756 This option is actual only for 82xx and 8xx possible. 761 This option is actual only for 82xx and 8xx possible.
757 If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE 762 If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE
758 must be defined, to setup the maximum idle timeout for 763 must be defined, to setup the maximum idle timeout for
759 the SMC. 764 the SMC.
760 765
761 - Pre-Console Buffer: 766 - Pre-Console Buffer:
762 Prior to the console being initialised (i.e. serial UART 767 Prior to the console being initialised (i.e. serial UART
763 initialised etc) all console output is silently discarded. 768 initialised etc) all console output is silently discarded.
764 Defining CONFIG_PRE_CONSOLE_BUFFER will cause U-Boot to 769 Defining CONFIG_PRE_CONSOLE_BUFFER will cause U-Boot to
765 buffer any console messages prior to the console being 770 buffer any console messages prior to the console being
766 initialised to a buffer of size CONFIG_PRE_CON_BUF_SZ 771 initialised to a buffer of size CONFIG_PRE_CON_BUF_SZ
767 bytes located at CONFIG_PRE_CON_BUF_ADDR. The buffer is 772 bytes located at CONFIG_PRE_CON_BUF_ADDR. The buffer is
768 a circular buffer, so if more than CONFIG_PRE_CON_BUF_SZ 773 a circular buffer, so if more than CONFIG_PRE_CON_BUF_SZ
769 bytes are output before the console is initialised, the 774 bytes are output before the console is initialised, the
770 earlier bytes are discarded. 775 earlier bytes are discarded.
771 776
772 'Sane' compilers will generate smaller code if 777 'Sane' compilers will generate smaller code if
773 CONFIG_PRE_CON_BUF_SZ is a power of 2 778 CONFIG_PRE_CON_BUF_SZ is a power of 2
774 779
775 - Safe printf() functions 780 - Safe printf() functions
776 Define CONFIG_SYS_VSNPRINTF to compile in safe versions of 781 Define CONFIG_SYS_VSNPRINTF to compile in safe versions of
777 the printf() functions. These are defined in 782 the printf() functions. These are defined in
778 include/vsprintf.h and include snprintf(), vsnprintf() and 783 include/vsprintf.h and include snprintf(), vsnprintf() and
779 so on. Code size increase is approximately 300-500 bytes. 784 so on. Code size increase is approximately 300-500 bytes.
780 If this option is not given then these functions will 785 If this option is not given then these functions will
781 silently discard their buffer size argument - this means 786 silently discard their buffer size argument - this means
782 you are not getting any overflow checking in this case. 787 you are not getting any overflow checking in this case.
783 788
784 - Boot Delay: CONFIG_BOOTDELAY - in seconds 789 - Boot Delay: CONFIG_BOOTDELAY - in seconds
785 Delay before automatically booting the default image; 790 Delay before automatically booting the default image;
786 set to -1 to disable autoboot. 791 set to -1 to disable autoboot.
787 set to -2 to autoboot with no delay and not check for abort 792 set to -2 to autoboot with no delay and not check for abort
788 (even when CONFIG_ZERO_BOOTDELAY_CHECK is defined). 793 (even when CONFIG_ZERO_BOOTDELAY_CHECK is defined).
789 794
790 See doc/README.autoboot for these options that 795 See doc/README.autoboot for these options that
791 work with CONFIG_BOOTDELAY. None are required. 796 work with CONFIG_BOOTDELAY. None are required.
792 CONFIG_BOOT_RETRY_TIME 797 CONFIG_BOOT_RETRY_TIME
793 CONFIG_BOOT_RETRY_MIN 798 CONFIG_BOOT_RETRY_MIN
794 CONFIG_AUTOBOOT_KEYED 799 CONFIG_AUTOBOOT_KEYED
795 CONFIG_AUTOBOOT_PROMPT 800 CONFIG_AUTOBOOT_PROMPT
796 CONFIG_AUTOBOOT_DELAY_STR 801 CONFIG_AUTOBOOT_DELAY_STR
797 CONFIG_AUTOBOOT_STOP_STR 802 CONFIG_AUTOBOOT_STOP_STR
798 CONFIG_AUTOBOOT_DELAY_STR2 803 CONFIG_AUTOBOOT_DELAY_STR2
799 CONFIG_AUTOBOOT_STOP_STR2 804 CONFIG_AUTOBOOT_STOP_STR2
800 CONFIG_ZERO_BOOTDELAY_CHECK 805 CONFIG_ZERO_BOOTDELAY_CHECK
801 CONFIG_RESET_TO_RETRY 806 CONFIG_RESET_TO_RETRY
802 807
803 - Autoboot Command: 808 - Autoboot Command:
804 CONFIG_BOOTCOMMAND 809 CONFIG_BOOTCOMMAND
805 Only needed when CONFIG_BOOTDELAY is enabled; 810 Only needed when CONFIG_BOOTDELAY is enabled;
806 define a command string that is automatically executed 811 define a command string that is automatically executed
807 when no character is read on the console interface 812 when no character is read on the console interface
808 within "Boot Delay" after reset. 813 within "Boot Delay" after reset.
809 814
810 CONFIG_BOOTARGS 815 CONFIG_BOOTARGS
811 This can be used to pass arguments to the bootm 816 This can be used to pass arguments to the bootm
812 command. The value of CONFIG_BOOTARGS goes into the 817 command. The value of CONFIG_BOOTARGS goes into the
813 environment value "bootargs". 818 environment value "bootargs".
814 819
815 CONFIG_RAMBOOT and CONFIG_NFSBOOT 820 CONFIG_RAMBOOT and CONFIG_NFSBOOT
816 The value of these goes into the environment as 821 The value of these goes into the environment as
817 "ramboot" and "nfsboot" respectively, and can be used 822 "ramboot" and "nfsboot" respectively, and can be used
818 as a convenience, when switching between booting from 823 as a convenience, when switching between booting from
819 RAM and NFS. 824 RAM and NFS.
820 825
821 - Bootcount: 826 - Bootcount:
822 CONFIG_BOOTCOUNT_LIMIT 827 CONFIG_BOOTCOUNT_LIMIT
823 Implements a mechanism for detecting a repeating reboot 828 Implements a mechanism for detecting a repeating reboot
824 cycle, see: 829 cycle, see:
825 http://www.denx.de/wiki/view/DULG/UBootBootCountLimit 830 http://www.denx.de/wiki/view/DULG/UBootBootCountLimit
826 831
827 CONFIG_BOOTCOUNT_ENV 832 CONFIG_BOOTCOUNT_ENV
828 If no softreset save registers are found on the hardware 833 If no softreset save registers are found on the hardware
829 "bootcount" is stored in the environment. To prevent a 834 "bootcount" is stored in the environment. To prevent a
830 saveenv on all reboots, the environment variable 835 saveenv on all reboots, the environment variable
831 "upgrade_available" is used. If "upgrade_available" is 836 "upgrade_available" is used. If "upgrade_available" is
832 0, "bootcount" is always 0, if "upgrade_available" is 837 0, "bootcount" is always 0, if "upgrade_available" is
833 1 "bootcount" is incremented in the environment. 838 1 "bootcount" is incremented in the environment.
834 So the Userspace Applikation must set the "upgrade_available" 839 So the Userspace Applikation must set the "upgrade_available"
835 and "bootcount" variable to 0, if a boot was successfully. 840 and "bootcount" variable to 0, if a boot was successfully.
836 841
837 - Pre-Boot Commands: 842 - Pre-Boot Commands:
838 CONFIG_PREBOOT 843 CONFIG_PREBOOT
839 844
840 When this option is #defined, the existence of the 845 When this option is #defined, the existence of the
841 environment variable "preboot" will be checked 846 environment variable "preboot" will be checked
842 immediately before starting the CONFIG_BOOTDELAY 847 immediately before starting the CONFIG_BOOTDELAY
843 countdown and/or running the auto-boot command resp. 848 countdown and/or running the auto-boot command resp.
844 entering interactive mode. 849 entering interactive mode.
845 850
846 This feature is especially useful when "preboot" is 851 This feature is especially useful when "preboot" is
847 automatically generated or modified. For an example 852 automatically generated or modified. For an example
848 see the LWMON board specific code: here "preboot" is 853 see the LWMON board specific code: here "preboot" is
849 modified when the user holds down a certain 854 modified when the user holds down a certain
850 combination of keys on the (special) keyboard when 855 combination of keys on the (special) keyboard when
851 booting the systems 856 booting the systems
852 857
853 - Serial Download Echo Mode: 858 - Serial Download Echo Mode:
854 CONFIG_LOADS_ECHO 859 CONFIG_LOADS_ECHO
855 If defined to 1, all characters received during a 860 If defined to 1, all characters received during a
856 serial download (using the "loads" command) are 861 serial download (using the "loads" command) are
857 echoed back. This might be needed by some terminal 862 echoed back. This might be needed by some terminal
858 emulations (like "cu"), but may as well just take 863 emulations (like "cu"), but may as well just take
859 time on others. This setting #define's the initial 864 time on others. This setting #define's the initial
860 value of the "loads_echo" environment variable. 865 value of the "loads_echo" environment variable.
861 866
862 - Kgdb Serial Baudrate: (if CONFIG_CMD_KGDB is defined) 867 - Kgdb Serial Baudrate: (if CONFIG_CMD_KGDB is defined)
863 CONFIG_KGDB_BAUDRATE 868 CONFIG_KGDB_BAUDRATE
864 Select one of the baudrates listed in 869 Select one of the baudrates listed in
865 CONFIG_SYS_BAUDRATE_TABLE, see below. 870 CONFIG_SYS_BAUDRATE_TABLE, see below.
866 871
867 - Monitor Functions: 872 - Monitor Functions:
868 Monitor commands can be included or excluded 873 Monitor commands can be included or excluded
869 from the build by using the #include files 874 from the build by using the #include files
870 <config_cmd_all.h> and #undef'ing unwanted 875 <config_cmd_all.h> and #undef'ing unwanted
871 commands, or using <config_cmd_default.h> 876 commands, or using <config_cmd_default.h>
872 and augmenting with additional #define's 877 and augmenting with additional #define's
873 for wanted commands. 878 for wanted commands.
874 879
875 The default command configuration includes all commands 880 The default command configuration includes all commands
876 except those marked below with a "*". 881 except those marked below with a "*".
877 882
878 CONFIG_CMD_ASKENV * ask for env variable 883 CONFIG_CMD_ASKENV * ask for env variable
879 CONFIG_CMD_BDI bdinfo 884 CONFIG_CMD_BDI bdinfo
880 CONFIG_CMD_BEDBUG * Include BedBug Debugger 885 CONFIG_CMD_BEDBUG * Include BedBug Debugger
881 CONFIG_CMD_BMP * BMP support 886 CONFIG_CMD_BMP * BMP support
882 CONFIG_CMD_BSP * Board specific commands 887 CONFIG_CMD_BSP * Board specific commands
883 CONFIG_CMD_BOOTD bootd 888 CONFIG_CMD_BOOTD bootd
884 CONFIG_CMD_CACHE * icache, dcache 889 CONFIG_CMD_CACHE * icache, dcache
885 CONFIG_CMD_CONSOLE coninfo 890 CONFIG_CMD_CONSOLE coninfo
886 CONFIG_CMD_CRC32 * crc32 891 CONFIG_CMD_CRC32 * crc32
887 CONFIG_CMD_DATE * support for RTC, date/time... 892 CONFIG_CMD_DATE * support for RTC, date/time...
888 CONFIG_CMD_DHCP * DHCP support 893 CONFIG_CMD_DHCP * DHCP support
889 CONFIG_CMD_DIAG * Diagnostics 894 CONFIG_CMD_DIAG * Diagnostics
890 CONFIG_CMD_DS4510 * ds4510 I2C gpio commands 895 CONFIG_CMD_DS4510 * ds4510 I2C gpio commands
891 CONFIG_CMD_DS4510_INFO * ds4510 I2C info command 896 CONFIG_CMD_DS4510_INFO * ds4510 I2C info command
892 CONFIG_CMD_DS4510_MEM * ds4510 I2C eeprom/sram commansd 897 CONFIG_CMD_DS4510_MEM * ds4510 I2C eeprom/sram commansd
893 CONFIG_CMD_DS4510_RST * ds4510 I2C rst command 898 CONFIG_CMD_DS4510_RST * ds4510 I2C rst command
894 CONFIG_CMD_DTT * Digital Therm and Thermostat 899 CONFIG_CMD_DTT * Digital Therm and Thermostat
895 CONFIG_CMD_ECHO echo arguments 900 CONFIG_CMD_ECHO echo arguments
896 CONFIG_CMD_EDITENV edit env variable 901 CONFIG_CMD_EDITENV edit env variable
897 CONFIG_CMD_EEPROM * EEPROM read/write support 902 CONFIG_CMD_EEPROM * EEPROM read/write support
898 CONFIG_CMD_ELF * bootelf, bootvx 903 CONFIG_CMD_ELF * bootelf, bootvx
899 CONFIG_CMD_ENV_CALLBACK * display details about env callbacks 904 CONFIG_CMD_ENV_CALLBACK * display details about env callbacks
900 CONFIG_CMD_ENV_FLAGS * display details about env flags 905 CONFIG_CMD_ENV_FLAGS * display details about env flags
901 CONFIG_CMD_ENV_EXISTS * check existence of env variable 906 CONFIG_CMD_ENV_EXISTS * check existence of env variable
902 CONFIG_CMD_EXPORTENV * export the environment 907 CONFIG_CMD_EXPORTENV * export the environment
903 CONFIG_CMD_EXT2 * ext2 command support 908 CONFIG_CMD_EXT2 * ext2 command support
904 CONFIG_CMD_EXT4 * ext4 command support 909 CONFIG_CMD_EXT4 * ext4 command support
905 CONFIG_CMD_SAVEENV saveenv 910 CONFIG_CMD_SAVEENV saveenv
906 CONFIG_CMD_FDC * Floppy Disk Support 911 CONFIG_CMD_FDC * Floppy Disk Support
907 CONFIG_CMD_FAT * FAT command support 912 CONFIG_CMD_FAT * FAT command support
908 CONFIG_CMD_FDOS * Dos diskette Support 913 CONFIG_CMD_FDOS * Dos diskette Support
909 CONFIG_CMD_FLASH flinfo, erase, protect 914 CONFIG_CMD_FLASH flinfo, erase, protect
910 CONFIG_CMD_FPGA FPGA device initialization support 915 CONFIG_CMD_FPGA FPGA device initialization support
911 CONFIG_CMD_FUSE * Device fuse support 916 CONFIG_CMD_FUSE * Device fuse support
912 CONFIG_CMD_GETTIME * Get time since boot 917 CONFIG_CMD_GETTIME * Get time since boot
913 CONFIG_CMD_GO * the 'go' command (exec code) 918 CONFIG_CMD_GO * the 'go' command (exec code)
914 CONFIG_CMD_GREPENV * search environment 919 CONFIG_CMD_GREPENV * search environment
915 CONFIG_CMD_HASH * calculate hash / digest 920 CONFIG_CMD_HASH * calculate hash / digest
916 CONFIG_CMD_HWFLOW * RTS/CTS hw flow control 921 CONFIG_CMD_HWFLOW * RTS/CTS hw flow control
917 CONFIG_CMD_I2C * I2C serial bus support 922 CONFIG_CMD_I2C * I2C serial bus support
918 CONFIG_CMD_IDE * IDE harddisk support 923 CONFIG_CMD_IDE * IDE harddisk support
919 CONFIG_CMD_IMI iminfo 924 CONFIG_CMD_IMI iminfo
920 CONFIG_CMD_IMLS List all images found in NOR flash 925 CONFIG_CMD_IMLS List all images found in NOR flash
921 CONFIG_CMD_IMLS_NAND * List all images found in NAND flash 926 CONFIG_CMD_IMLS_NAND * List all images found in NAND flash
922 CONFIG_CMD_IMMAP * IMMR dump support 927 CONFIG_CMD_IMMAP * IMMR dump support
923 CONFIG_CMD_IMPORTENV * import an environment 928 CONFIG_CMD_IMPORTENV * import an environment
924 CONFIG_CMD_INI * import data from an ini file into the env 929 CONFIG_CMD_INI * import data from an ini file into the env
925 CONFIG_CMD_IRQ * irqinfo 930 CONFIG_CMD_IRQ * irqinfo
926 CONFIG_CMD_ITEST Integer/string test of 2 values 931 CONFIG_CMD_ITEST Integer/string test of 2 values
927 CONFIG_CMD_JFFS2 * JFFS2 Support 932 CONFIG_CMD_JFFS2 * JFFS2 Support
928 CONFIG_CMD_KGDB * kgdb 933 CONFIG_CMD_KGDB * kgdb
929 CONFIG_CMD_LDRINFO * ldrinfo (display Blackfin loader) 934 CONFIG_CMD_LDRINFO * ldrinfo (display Blackfin loader)
930 CONFIG_CMD_LINK_LOCAL * link-local IP address auto-configuration 935 CONFIG_CMD_LINK_LOCAL * link-local IP address auto-configuration
931 (169.254.*.*) 936 (169.254.*.*)
932 CONFIG_CMD_LOADB loadb 937 CONFIG_CMD_LOADB loadb
933 CONFIG_CMD_LOADS loads 938 CONFIG_CMD_LOADS loads
934 CONFIG_CMD_MD5SUM * print md5 message digest 939 CONFIG_CMD_MD5SUM * print md5 message digest
935 (requires CONFIG_CMD_MEMORY and CONFIG_MD5) 940 (requires CONFIG_CMD_MEMORY and CONFIG_MD5)
936 CONFIG_CMD_MEMINFO * Display detailed memory information 941 CONFIG_CMD_MEMINFO * Display detailed memory information
937 CONFIG_CMD_MEMORY md, mm, nm, mw, cp, cmp, crc, base, 942 CONFIG_CMD_MEMORY md, mm, nm, mw, cp, cmp, crc, base,
938 loop, loopw 943 loop, loopw
939 CONFIG_CMD_MEMTEST * mtest 944 CONFIG_CMD_MEMTEST * mtest
940 CONFIG_CMD_MISC Misc functions like sleep etc 945 CONFIG_CMD_MISC Misc functions like sleep etc
941 CONFIG_CMD_MMC * MMC memory mapped support 946 CONFIG_CMD_MMC * MMC memory mapped support
942 CONFIG_CMD_MII * MII utility commands 947 CONFIG_CMD_MII * MII utility commands
943 CONFIG_CMD_MTDPARTS * MTD partition support 948 CONFIG_CMD_MTDPARTS * MTD partition support
944 CONFIG_CMD_NAND * NAND support 949 CONFIG_CMD_NAND * NAND support
945 CONFIG_CMD_NET bootp, tftpboot, rarpboot 950 CONFIG_CMD_NET bootp, tftpboot, rarpboot
946 CONFIG_CMD_NFS NFS support 951 CONFIG_CMD_NFS NFS support
947 CONFIG_CMD_PCA953X * PCA953x I2C gpio commands 952 CONFIG_CMD_PCA953X * PCA953x I2C gpio commands
948 CONFIG_CMD_PCA953X_INFO * PCA953x I2C gpio info command 953 CONFIG_CMD_PCA953X_INFO * PCA953x I2C gpio info command
949 CONFIG_CMD_PCI * pciinfo 954 CONFIG_CMD_PCI * pciinfo
950 CONFIG_CMD_PCMCIA * PCMCIA support 955 CONFIG_CMD_PCMCIA * PCMCIA support
951 CONFIG_CMD_PING * send ICMP ECHO_REQUEST to network 956 CONFIG_CMD_PING * send ICMP ECHO_REQUEST to network
952 host 957 host
953 CONFIG_CMD_PORTIO * Port I/O 958 CONFIG_CMD_PORTIO * Port I/O
954 CONFIG_CMD_READ * Read raw data from partition 959 CONFIG_CMD_READ * Read raw data from partition
955 CONFIG_CMD_REGINFO * Register dump 960 CONFIG_CMD_REGINFO * Register dump
956 CONFIG_CMD_RUN run command in env variable 961 CONFIG_CMD_RUN run command in env variable
957 CONFIG_CMD_SANDBOX * sb command to access sandbox features 962 CONFIG_CMD_SANDBOX * sb command to access sandbox features
958 CONFIG_CMD_SAVES * save S record dump 963 CONFIG_CMD_SAVES * save S record dump
959 CONFIG_CMD_SCSI * SCSI Support 964 CONFIG_CMD_SCSI * SCSI Support
960 CONFIG_CMD_SDRAM * print SDRAM configuration information 965 CONFIG_CMD_SDRAM * print SDRAM configuration information
961 (requires CONFIG_CMD_I2C) 966 (requires CONFIG_CMD_I2C)
962 CONFIG_CMD_SETGETDCR Support for DCR Register access 967 CONFIG_CMD_SETGETDCR Support for DCR Register access
963 (4xx only) 968 (4xx only)
964 CONFIG_CMD_SF * Read/write/erase SPI NOR flash 969 CONFIG_CMD_SF * Read/write/erase SPI NOR flash
965 CONFIG_CMD_SHA1SUM * print sha1 memory digest 970 CONFIG_CMD_SHA1SUM * print sha1 memory digest
966 (requires CONFIG_CMD_MEMORY) 971 (requires CONFIG_CMD_MEMORY)
967 CONFIG_CMD_SOFTSWITCH * Soft switch setting command for BF60x 972 CONFIG_CMD_SOFTSWITCH * Soft switch setting command for BF60x
968 CONFIG_CMD_SOURCE "source" command Support 973 CONFIG_CMD_SOURCE "source" command Support
969 CONFIG_CMD_SPI * SPI serial bus support 974 CONFIG_CMD_SPI * SPI serial bus support
970 CONFIG_CMD_TFTPSRV * TFTP transfer in server mode 975 CONFIG_CMD_TFTPSRV * TFTP transfer in server mode
971 CONFIG_CMD_TFTPPUT * TFTP put command (upload) 976 CONFIG_CMD_TFTPPUT * TFTP put command (upload)
972 CONFIG_CMD_TIME * run command and report execution time (ARM specific) 977 CONFIG_CMD_TIME * run command and report execution time (ARM specific)
973 CONFIG_CMD_TIMER * access to the system tick timer 978 CONFIG_CMD_TIMER * access to the system tick timer
974 CONFIG_CMD_USB * USB support 979 CONFIG_CMD_USB * USB support
975 CONFIG_CMD_CDP * Cisco Discover Protocol support 980 CONFIG_CMD_CDP * Cisco Discover Protocol support
976 CONFIG_CMD_MFSL * Microblaze FSL support 981 CONFIG_CMD_MFSL * Microblaze FSL support
977 CONFIG_CMD_XIMG Load part of Multi Image 982 CONFIG_CMD_XIMG Load part of Multi Image
978 983
979 984
980 EXAMPLE: If you want all functions except of network 985 EXAMPLE: If you want all functions except of network
981 support you can write: 986 support you can write:
982 987
983 #include "config_cmd_all.h" 988 #include "config_cmd_all.h"
984 #undef CONFIG_CMD_NET 989 #undef CONFIG_CMD_NET
985 990
986 Other Commands: 991 Other Commands:
987 fdt (flattened device tree) command: CONFIG_OF_LIBFDT 992 fdt (flattened device tree) command: CONFIG_OF_LIBFDT
988 993
989 Note: Don't enable the "icache" and "dcache" commands 994 Note: Don't enable the "icache" and "dcache" commands
990 (configuration option CONFIG_CMD_CACHE) unless you know 995 (configuration option CONFIG_CMD_CACHE) unless you know
991 what you (and your U-Boot users) are doing. Data 996 what you (and your U-Boot users) are doing. Data
992 cache cannot be enabled on systems like the 8xx or 997 cache cannot be enabled on systems like the 8xx or
993 8260 (where accesses to the IMMR region must be 998 8260 (where accesses to the IMMR region must be
994 uncached), and it cannot be disabled on all other 999 uncached), and it cannot be disabled on all other
995 systems where we (mis-) use the data cache to hold an 1000 systems where we (mis-) use the data cache to hold an
996 initial stack and some data. 1001 initial stack and some data.
997 1002
998 1003
999 XXX - this list needs to get updated! 1004 XXX - this list needs to get updated!
1000 1005
1001 - Regular expression support: 1006 - Regular expression support:
1002 CONFIG_REGEX 1007 CONFIG_REGEX
1003 If this variable is defined, U-Boot is linked against 1008 If this variable is defined, U-Boot is linked against
1004 the SLRE (Super Light Regular Expression) library, 1009 the SLRE (Super Light Regular Expression) library,
1005 which adds regex support to some commands, as for 1010 which adds regex support to some commands, as for
1006 example "env grep" and "setexpr". 1011 example "env grep" and "setexpr".
1007 1012
1008 - Device tree: 1013 - Device tree:
1009 CONFIG_OF_CONTROL 1014 CONFIG_OF_CONTROL
1010 If this variable is defined, U-Boot will use a device tree 1015 If this variable is defined, U-Boot will use a device tree
1011 to configure its devices, instead of relying on statically 1016 to configure its devices, instead of relying on statically
1012 compiled #defines in the board file. This option is 1017 compiled #defines in the board file. This option is
1013 experimental and only available on a few boards. The device 1018 experimental and only available on a few boards. The device
1014 tree is available in the global data as gd->fdt_blob. 1019 tree is available in the global data as gd->fdt_blob.
1015 1020
1016 U-Boot needs to get its device tree from somewhere. This can 1021 U-Boot needs to get its device tree from somewhere. This can
1017 be done using one of the two options below: 1022 be done using one of the two options below:
1018 1023
1019 CONFIG_OF_EMBED 1024 CONFIG_OF_EMBED
1020 If this variable is defined, U-Boot will embed a device tree 1025 If this variable is defined, U-Boot will embed a device tree
1021 binary in its image. This device tree file should be in the 1026 binary in its image. This device tree file should be in the
1022 board directory and called <soc>-<board>.dts. The binary file 1027 board directory and called <soc>-<board>.dts. The binary file
1023 is then picked up in board_init_f() and made available through 1028 is then picked up in board_init_f() and made available through
1024 the global data structure as gd->blob. 1029 the global data structure as gd->blob.
1025 1030
1026 CONFIG_OF_SEPARATE 1031 CONFIG_OF_SEPARATE
1027 If this variable is defined, U-Boot will build a device tree 1032 If this variable is defined, U-Boot will build a device tree
1028 binary. It will be called u-boot.dtb. Architecture-specific 1033 binary. It will be called u-boot.dtb. Architecture-specific
1029 code will locate it at run-time. Generally this works by: 1034 code will locate it at run-time. Generally this works by:
1030 1035
1031 cat u-boot.bin u-boot.dtb >image.bin 1036 cat u-boot.bin u-boot.dtb >image.bin
1032 1037
1033 and in fact, U-Boot does this for you, creating a file called 1038 and in fact, U-Boot does this for you, creating a file called
1034 u-boot-dtb.bin which is useful in the common case. You can 1039 u-boot-dtb.bin which is useful in the common case. You can
1035 still use the individual files if you need something more 1040 still use the individual files if you need something more
1036 exotic. 1041 exotic.
1037 1042
1038 - Watchdog: 1043 - Watchdog:
1039 CONFIG_WATCHDOG 1044 CONFIG_WATCHDOG
1040 If this variable is defined, it enables watchdog 1045 If this variable is defined, it enables watchdog
1041 support for the SoC. There must be support in the SoC 1046 support for the SoC. There must be support in the SoC
1042 specific code for a watchdog. For the 8xx and 8260 1047 specific code for a watchdog. For the 8xx and 8260
1043 CPUs, the SIU Watchdog feature is enabled in the SYPCR 1048 CPUs, the SIU Watchdog feature is enabled in the SYPCR
1044 register. When supported for a specific SoC is 1049 register. When supported for a specific SoC is
1045 available, then no further board specific code should 1050 available, then no further board specific code should
1046 be needed to use it. 1051 be needed to use it.
1047 1052
1048 CONFIG_HW_WATCHDOG 1053 CONFIG_HW_WATCHDOG
1049 When using a watchdog circuitry external to the used 1054 When using a watchdog circuitry external to the used
1050 SoC, then define this variable and provide board 1055 SoC, then define this variable and provide board
1051 specific code for the "hw_watchdog_reset" function. 1056 specific code for the "hw_watchdog_reset" function.
1052 1057
1053 - U-Boot Version: 1058 - U-Boot Version:
1054 CONFIG_VERSION_VARIABLE 1059 CONFIG_VERSION_VARIABLE
1055 If this variable is defined, an environment variable 1060 If this variable is defined, an environment variable
1056 named "ver" is created by U-Boot showing the U-Boot 1061 named "ver" is created by U-Boot showing the U-Boot
1057 version as printed by the "version" command. 1062 version as printed by the "version" command.
1058 Any change to this variable will be reverted at the 1063 Any change to this variable will be reverted at the
1059 next reset. 1064 next reset.
1060 1065
1061 - Real-Time Clock: 1066 - Real-Time Clock:
1062 1067
1063 When CONFIG_CMD_DATE is selected, the type of the RTC 1068 When CONFIG_CMD_DATE is selected, the type of the RTC
1064 has to be selected, too. Define exactly one of the 1069 has to be selected, too. Define exactly one of the
1065 following options: 1070 following options:
1066 1071
1067 CONFIG_RTC_MPC8xx - use internal RTC of MPC8xx 1072 CONFIG_RTC_MPC8xx - use internal RTC of MPC8xx
1068 CONFIG_RTC_PCF8563 - use Philips PCF8563 RTC 1073 CONFIG_RTC_PCF8563 - use Philips PCF8563 RTC
1069 CONFIG_RTC_MC13XXX - use MC13783 or MC13892 RTC 1074 CONFIG_RTC_MC13XXX - use MC13783 or MC13892 RTC
1070 CONFIG_RTC_MC146818 - use MC146818 RTC 1075 CONFIG_RTC_MC146818 - use MC146818 RTC
1071 CONFIG_RTC_DS1307 - use Maxim, Inc. DS1307 RTC 1076 CONFIG_RTC_DS1307 - use Maxim, Inc. DS1307 RTC
1072 CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC 1077 CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC
1073 CONFIG_RTC_DS1338 - use Maxim, Inc. DS1338 RTC 1078 CONFIG_RTC_DS1338 - use Maxim, Inc. DS1338 RTC
1074 CONFIG_RTC_DS164x - use Dallas DS164x RTC 1079 CONFIG_RTC_DS164x - use Dallas DS164x RTC
1075 CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC 1080 CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC
1076 CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC 1081 CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC
1077 CONFIG_SYS_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337 1082 CONFIG_SYS_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337
1078 CONFIG_SYS_RV3029_TCR - enable trickle charger on 1083 CONFIG_SYS_RV3029_TCR - enable trickle charger on
1079 RV3029 RTC. 1084 RV3029 RTC.
1080 1085
1081 Note that if the RTC uses I2C, then the I2C interface 1086 Note that if the RTC uses I2C, then the I2C interface
1082 must also be configured. See I2C Support, below. 1087 must also be configured. See I2C Support, below.
1083 1088
1084 - GPIO Support: 1089 - GPIO Support:
1085 CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO 1090 CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO
1086 1091
1087 The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of 1092 The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of
1088 chip-ngpio pairs that tell the PCA953X driver the number of 1093 chip-ngpio pairs that tell the PCA953X driver the number of
1089 pins supported by a particular chip. 1094 pins supported by a particular chip.
1090 1095
1091 Note that if the GPIO device uses I2C, then the I2C interface 1096 Note that if the GPIO device uses I2C, then the I2C interface
1092 must also be configured. See I2C Support, below. 1097 must also be configured. See I2C Support, below.
1093 1098
1094 - Timestamp Support: 1099 - Timestamp Support:
1095 1100
1096 When CONFIG_TIMESTAMP is selected, the timestamp 1101 When CONFIG_TIMESTAMP is selected, the timestamp
1097 (date and time) of an image is printed by image 1102 (date and time) of an image is printed by image
1098 commands like bootm or iminfo. This option is 1103 commands like bootm or iminfo. This option is
1099 automatically enabled when you select CONFIG_CMD_DATE . 1104 automatically enabled when you select CONFIG_CMD_DATE .
1100 1105
1101 - Partition Labels (disklabels) Supported: 1106 - Partition Labels (disklabels) Supported:
1102 Zero or more of the following: 1107 Zero or more of the following:
1103 CONFIG_MAC_PARTITION Apple's MacOS partition table. 1108 CONFIG_MAC_PARTITION Apple's MacOS partition table.
1104 CONFIG_DOS_PARTITION MS Dos partition table, traditional on the 1109 CONFIG_DOS_PARTITION MS Dos partition table, traditional on the
1105 Intel architecture, USB sticks, etc. 1110 Intel architecture, USB sticks, etc.
1106 CONFIG_ISO_PARTITION ISO partition table, used on CDROM etc. 1111 CONFIG_ISO_PARTITION ISO partition table, used on CDROM etc.
1107 CONFIG_EFI_PARTITION GPT partition table, common when EFI is the 1112 CONFIG_EFI_PARTITION GPT partition table, common when EFI is the
1108 bootloader. Note 2TB partition limit; see 1113 bootloader. Note 2TB partition limit; see
1109 disk/part_efi.c 1114 disk/part_efi.c
1110 CONFIG_MTD_PARTITIONS Memory Technology Device partition table. 1115 CONFIG_MTD_PARTITIONS Memory Technology Device partition table.
1111 1116
1112 If IDE or SCSI support is enabled (CONFIG_CMD_IDE or 1117 If IDE or SCSI support is enabled (CONFIG_CMD_IDE or
1113 CONFIG_CMD_SCSI) you must configure support for at 1118 CONFIG_CMD_SCSI) you must configure support for at
1114 least one non-MTD partition type as well. 1119 least one non-MTD partition type as well.
1115 1120
1116 - IDE Reset method: 1121 - IDE Reset method:
1117 CONFIG_IDE_RESET_ROUTINE - this is defined in several 1122 CONFIG_IDE_RESET_ROUTINE - this is defined in several
1118 board configurations files but used nowhere! 1123 board configurations files but used nowhere!
1119 1124
1120 CONFIG_IDE_RESET - is this is defined, IDE Reset will 1125 CONFIG_IDE_RESET - is this is defined, IDE Reset will
1121 be performed by calling the function 1126 be performed by calling the function
1122 ide_set_reset(int reset) 1127 ide_set_reset(int reset)
1123 which has to be defined in a board specific file 1128 which has to be defined in a board specific file
1124 1129
1125 - ATAPI Support: 1130 - ATAPI Support:
1126 CONFIG_ATAPI 1131 CONFIG_ATAPI
1127 1132
1128 Set this to enable ATAPI support. 1133 Set this to enable ATAPI support.
1129 1134
1130 - LBA48 Support 1135 - LBA48 Support
1131 CONFIG_LBA48 1136 CONFIG_LBA48
1132 1137
1133 Set this to enable support for disks larger than 137GB 1138 Set this to enable support for disks larger than 137GB
1134 Also look at CONFIG_SYS_64BIT_LBA. 1139 Also look at CONFIG_SYS_64BIT_LBA.
1135 Whithout these , LBA48 support uses 32bit variables and will 'only' 1140 Whithout these , LBA48 support uses 32bit variables and will 'only'
1136 support disks up to 2.1TB. 1141 support disks up to 2.1TB.
1137 1142
1138 CONFIG_SYS_64BIT_LBA: 1143 CONFIG_SYS_64BIT_LBA:
1139 When enabled, makes the IDE subsystem use 64bit sector addresses. 1144 When enabled, makes the IDE subsystem use 64bit sector addresses.
1140 Default is 32bit. 1145 Default is 32bit.
1141 1146
1142 - SCSI Support: 1147 - SCSI Support:
1143 At the moment only there is only support for the 1148 At the moment only there is only support for the
1144 SYM53C8XX SCSI controller; define 1149 SYM53C8XX SCSI controller; define
1145 CONFIG_SCSI_SYM53C8XX to enable it. 1150 CONFIG_SCSI_SYM53C8XX to enable it.
1146 1151
1147 CONFIG_SYS_SCSI_MAX_LUN [8], CONFIG_SYS_SCSI_MAX_SCSI_ID [7] and 1152 CONFIG_SYS_SCSI_MAX_LUN [8], CONFIG_SYS_SCSI_MAX_SCSI_ID [7] and
1148 CONFIG_SYS_SCSI_MAX_DEVICE [CONFIG_SYS_SCSI_MAX_SCSI_ID * 1153 CONFIG_SYS_SCSI_MAX_DEVICE [CONFIG_SYS_SCSI_MAX_SCSI_ID *
1149 CONFIG_SYS_SCSI_MAX_LUN] can be adjusted to define the 1154 CONFIG_SYS_SCSI_MAX_LUN] can be adjusted to define the
1150 maximum numbers of LUNs, SCSI ID's and target 1155 maximum numbers of LUNs, SCSI ID's and target
1151 devices. 1156 devices.
1152 CONFIG_SYS_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz) 1157 CONFIG_SYS_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)
1153 1158
1154 The environment variable 'scsidevs' is set to the number of 1159 The environment variable 'scsidevs' is set to the number of
1155 SCSI devices found during the last scan. 1160 SCSI devices found during the last scan.
1156 1161
1157 - NETWORK Support (PCI): 1162 - NETWORK Support (PCI):
1158 CONFIG_E1000 1163 CONFIG_E1000
1159 Support for Intel 8254x/8257x gigabit chips. 1164 Support for Intel 8254x/8257x gigabit chips.
1160 1165
1161 CONFIG_E1000_SPI 1166 CONFIG_E1000_SPI
1162 Utility code for direct access to the SPI bus on Intel 8257x. 1167 Utility code for direct access to the SPI bus on Intel 8257x.
1163 This does not do anything useful unless you set at least one 1168 This does not do anything useful unless you set at least one
1164 of CONFIG_CMD_E1000 or CONFIG_E1000_SPI_GENERIC. 1169 of CONFIG_CMD_E1000 or CONFIG_E1000_SPI_GENERIC.
1165 1170
1166 CONFIG_E1000_SPI_GENERIC 1171 CONFIG_E1000_SPI_GENERIC
1167 Allow generic access to the SPI bus on the Intel 8257x, for 1172 Allow generic access to the SPI bus on the Intel 8257x, for
1168 example with the "sspi" command. 1173 example with the "sspi" command.
1169 1174
1170 CONFIG_CMD_E1000 1175 CONFIG_CMD_E1000
1171 Management command for E1000 devices. When used on devices 1176 Management command for E1000 devices. When used on devices
1172 with SPI support you can reprogram the EEPROM from U-Boot. 1177 with SPI support you can reprogram the EEPROM from U-Boot.
1173 1178
1174 CONFIG_E1000_FALLBACK_MAC 1179 CONFIG_E1000_FALLBACK_MAC
1175 default MAC for empty EEPROM after production. 1180 default MAC for empty EEPROM after production.
1176 1181
1177 CONFIG_EEPRO100 1182 CONFIG_EEPRO100
1178 Support for Intel 82557/82559/82559ER chips. 1183 Support for Intel 82557/82559/82559ER chips.
1179 Optional CONFIG_EEPRO100_SROM_WRITE enables EEPROM 1184 Optional CONFIG_EEPRO100_SROM_WRITE enables EEPROM
1180 write routine for first time initialisation. 1185 write routine for first time initialisation.
1181 1186
1182 CONFIG_TULIP 1187 CONFIG_TULIP
1183 Support for Digital 2114x chips. 1188 Support for Digital 2114x chips.
1184 Optional CONFIG_TULIP_SELECT_MEDIA for board specific 1189 Optional CONFIG_TULIP_SELECT_MEDIA for board specific
1185 modem chip initialisation (KS8761/QS6611). 1190 modem chip initialisation (KS8761/QS6611).
1186 1191
1187 CONFIG_NATSEMI 1192 CONFIG_NATSEMI
1188 Support for National dp83815 chips. 1193 Support for National dp83815 chips.
1189 1194
1190 CONFIG_NS8382X 1195 CONFIG_NS8382X
1191 Support for National dp8382[01] gigabit chips. 1196 Support for National dp8382[01] gigabit chips.
1192 1197
1193 - NETWORK Support (other): 1198 - NETWORK Support (other):
1194 1199
1195 CONFIG_DRIVER_AT91EMAC 1200 CONFIG_DRIVER_AT91EMAC
1196 Support for AT91RM9200 EMAC. 1201 Support for AT91RM9200 EMAC.
1197 1202
1198 CONFIG_RMII 1203 CONFIG_RMII
1199 Define this to use reduced MII inteface 1204 Define this to use reduced MII inteface
1200 1205
1201 CONFIG_DRIVER_AT91EMAC_QUIET 1206 CONFIG_DRIVER_AT91EMAC_QUIET
1202 If this defined, the driver is quiet. 1207 If this defined, the driver is quiet.
1203 The driver doen't show link status messages. 1208 The driver doen't show link status messages.
1204 1209
1205 CONFIG_CALXEDA_XGMAC 1210 CONFIG_CALXEDA_XGMAC
1206 Support for the Calxeda XGMAC device 1211 Support for the Calxeda XGMAC device
1207 1212
1208 CONFIG_LAN91C96 1213 CONFIG_LAN91C96
1209 Support for SMSC's LAN91C96 chips. 1214 Support for SMSC's LAN91C96 chips.
1210 1215
1211 CONFIG_LAN91C96_BASE 1216 CONFIG_LAN91C96_BASE
1212 Define this to hold the physical address 1217 Define this to hold the physical address
1213 of the LAN91C96's I/O space 1218 of the LAN91C96's I/O space
1214 1219
1215 CONFIG_LAN91C96_USE_32_BIT 1220 CONFIG_LAN91C96_USE_32_BIT
1216 Define this to enable 32 bit addressing 1221 Define this to enable 32 bit addressing
1217 1222
1218 CONFIG_SMC91111 1223 CONFIG_SMC91111
1219 Support for SMSC's LAN91C111 chip 1224 Support for SMSC's LAN91C111 chip
1220 1225
1221 CONFIG_SMC91111_BASE 1226 CONFIG_SMC91111_BASE
1222 Define this to hold the physical address 1227 Define this to hold the physical address
1223 of the device (I/O space) 1228 of the device (I/O space)
1224 1229
1225 CONFIG_SMC_USE_32_BIT 1230 CONFIG_SMC_USE_32_BIT
1226 Define this if data bus is 32 bits 1231 Define this if data bus is 32 bits
1227 1232
1228 CONFIG_SMC_USE_IOFUNCS 1233 CONFIG_SMC_USE_IOFUNCS
1229 Define this to use i/o functions instead of macros 1234 Define this to use i/o functions instead of macros
1230 (some hardware wont work with macros) 1235 (some hardware wont work with macros)
1231 1236
1232 CONFIG_DRIVER_TI_EMAC 1237 CONFIG_DRIVER_TI_EMAC
1233 Support for davinci emac 1238 Support for davinci emac
1234 1239
1235 CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 1240 CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
1236 Define this if you have more then 3 PHYs. 1241 Define this if you have more then 3 PHYs.
1237 1242
1238 CONFIG_FTGMAC100 1243 CONFIG_FTGMAC100
1239 Support for Faraday's FTGMAC100 Gigabit SoC Ethernet 1244 Support for Faraday's FTGMAC100 Gigabit SoC Ethernet
1240 1245
1241 CONFIG_FTGMAC100_EGIGA 1246 CONFIG_FTGMAC100_EGIGA
1242 Define this to use GE link update with gigabit PHY. 1247 Define this to use GE link update with gigabit PHY.
1243 Define this if FTGMAC100 is connected to gigabit PHY. 1248 Define this if FTGMAC100 is connected to gigabit PHY.
1244 If your system has 10/100 PHY only, it might not occur 1249 If your system has 10/100 PHY only, it might not occur
1245 wrong behavior. Because PHY usually return timeout or 1250 wrong behavior. Because PHY usually return timeout or
1246 useless data when polling gigabit status and gigabit 1251 useless data when polling gigabit status and gigabit
1247 control registers. This behavior won't affect the 1252 control registers. This behavior won't affect the
1248 correctnessof 10/100 link speed update. 1253 correctnessof 10/100 link speed update.
1249 1254
1250 CONFIG_SMC911X 1255 CONFIG_SMC911X
1251 Support for SMSC's LAN911x and LAN921x chips 1256 Support for SMSC's LAN911x and LAN921x chips
1252 1257
1253 CONFIG_SMC911X_BASE 1258 CONFIG_SMC911X_BASE
1254 Define this to hold the physical address 1259 Define this to hold the physical address
1255 of the device (I/O space) 1260 of the device (I/O space)
1256 1261
1257 CONFIG_SMC911X_32_BIT 1262 CONFIG_SMC911X_32_BIT
1258 Define this if data bus is 32 bits 1263 Define this if data bus is 32 bits
1259 1264
1260 CONFIG_SMC911X_16_BIT 1265 CONFIG_SMC911X_16_BIT
1261 Define this if data bus is 16 bits. If your processor 1266 Define this if data bus is 16 bits. If your processor
1262 automatically converts one 32 bit word to two 16 bit 1267 automatically converts one 32 bit word to two 16 bit
1263 words you may also try CONFIG_SMC911X_32_BIT. 1268 words you may also try CONFIG_SMC911X_32_BIT.
1264 1269
1265 CONFIG_SH_ETHER 1270 CONFIG_SH_ETHER
1266 Support for Renesas on-chip Ethernet controller 1271 Support for Renesas on-chip Ethernet controller
1267 1272
1268 CONFIG_SH_ETHER_USE_PORT 1273 CONFIG_SH_ETHER_USE_PORT
1269 Define the number of ports to be used 1274 Define the number of ports to be used
1270 1275
1271 CONFIG_SH_ETHER_PHY_ADDR 1276 CONFIG_SH_ETHER_PHY_ADDR
1272 Define the ETH PHY's address 1277 Define the ETH PHY's address
1273 1278
1274 CONFIG_SH_ETHER_CACHE_WRITEBACK 1279 CONFIG_SH_ETHER_CACHE_WRITEBACK
1275 If this option is set, the driver enables cache flush. 1280 If this option is set, the driver enables cache flush.
1276 1281
1277 - TPM Support: 1282 - TPM Support:
1278 CONFIG_TPM 1283 CONFIG_TPM
1279 Support TPM devices. 1284 Support TPM devices.
1280 1285
1281 CONFIG_TPM_TIS_I2C 1286 CONFIG_TPM_TIS_I2C
1282 Support for i2c bus TPM devices. Only one device 1287 Support for i2c bus TPM devices. Only one device
1283 per system is supported at this time. 1288 per system is supported at this time.
1284 1289
1285 CONFIG_TPM_TIS_I2C_BUS_NUMBER 1290 CONFIG_TPM_TIS_I2C_BUS_NUMBER
1286 Define the the i2c bus number for the TPM device 1291 Define the the i2c bus number for the TPM device
1287 1292
1288 CONFIG_TPM_TIS_I2C_SLAVE_ADDRESS 1293 CONFIG_TPM_TIS_I2C_SLAVE_ADDRESS
1289 Define the TPM's address on the i2c bus 1294 Define the TPM's address on the i2c bus
1290 1295
1291 CONFIG_TPM_TIS_I2C_BURST_LIMITATION 1296 CONFIG_TPM_TIS_I2C_BURST_LIMITATION
1292 Define the burst count bytes upper limit 1297 Define the burst count bytes upper limit
1293 1298
1294 CONFIG_TPM_ATMEL_TWI 1299 CONFIG_TPM_ATMEL_TWI
1295 Support for Atmel TWI TPM device. Requires I2C support. 1300 Support for Atmel TWI TPM device. Requires I2C support.
1296 1301
1297 CONFIG_TPM_TIS_LPC 1302 CONFIG_TPM_TIS_LPC
1298 Support for generic parallel port TPM devices. Only one device 1303 Support for generic parallel port TPM devices. Only one device
1299 per system is supported at this time. 1304 per system is supported at this time.
1300 1305
1301 CONFIG_TPM_TIS_BASE_ADDRESS 1306 CONFIG_TPM_TIS_BASE_ADDRESS
1302 Base address where the generic TPM device is mapped 1307 Base address where the generic TPM device is mapped
1303 to. Contemporary x86 systems usually map it at 1308 to. Contemporary x86 systems usually map it at
1304 0xfed40000. 1309 0xfed40000.
1305 1310
1306 CONFIG_CMD_TPM 1311 CONFIG_CMD_TPM
1307 Add tpm monitor functions. 1312 Add tpm monitor functions.
1308 Requires CONFIG_TPM. If CONFIG_TPM_AUTH_SESSIONS is set, also 1313 Requires CONFIG_TPM. If CONFIG_TPM_AUTH_SESSIONS is set, also
1309 provides monitor access to authorized functions. 1314 provides monitor access to authorized functions.
1310 1315
1311 CONFIG_TPM 1316 CONFIG_TPM
1312 Define this to enable the TPM support library which provides 1317 Define this to enable the TPM support library which provides
1313 functional interfaces to some TPM commands. 1318 functional interfaces to some TPM commands.
1314 Requires support for a TPM device. 1319 Requires support for a TPM device.
1315 1320
1316 CONFIG_TPM_AUTH_SESSIONS 1321 CONFIG_TPM_AUTH_SESSIONS
1317 Define this to enable authorized functions in the TPM library. 1322 Define this to enable authorized functions in the TPM library.
1318 Requires CONFIG_TPM and CONFIG_SHA1. 1323 Requires CONFIG_TPM and CONFIG_SHA1.
1319 1324
1320 - USB Support: 1325 - USB Support:
1321 At the moment only the UHCI host controller is 1326 At the moment only the UHCI host controller is
1322 supported (PIP405, MIP405, MPC5200); define 1327 supported (PIP405, MIP405, MPC5200); define
1323 CONFIG_USB_UHCI to enable it. 1328 CONFIG_USB_UHCI to enable it.
1324 define CONFIG_USB_KEYBOARD to enable the USB Keyboard 1329 define CONFIG_USB_KEYBOARD to enable the USB Keyboard
1325 and define CONFIG_USB_STORAGE to enable the USB 1330 and define CONFIG_USB_STORAGE to enable the USB
1326 storage devices. 1331 storage devices.
1327 Note: 1332 Note:
1328 Supported are USB Keyboards and USB Floppy drives 1333 Supported are USB Keyboards and USB Floppy drives
1329 (TEAC FD-05PUB). 1334 (TEAC FD-05PUB).
1330 MPC5200 USB requires additional defines: 1335 MPC5200 USB requires additional defines:
1331 CONFIG_USB_CLOCK 1336 CONFIG_USB_CLOCK
1332 for 528 MHz Clock: 0x0001bbbb 1337 for 528 MHz Clock: 0x0001bbbb
1333 CONFIG_PSC3_USB 1338 CONFIG_PSC3_USB
1334 for USB on PSC3 1339 for USB on PSC3
1335 CONFIG_USB_CONFIG 1340 CONFIG_USB_CONFIG
1336 for differential drivers: 0x00001000 1341 for differential drivers: 0x00001000
1337 for single ended drivers: 0x00005000 1342 for single ended drivers: 0x00005000
1338 for differential drivers on PSC3: 0x00000100 1343 for differential drivers on PSC3: 0x00000100
1339 for single ended drivers on PSC3: 0x00004100 1344 for single ended drivers on PSC3: 0x00004100
1340 CONFIG_SYS_USB_EVENT_POLL 1345 CONFIG_SYS_USB_EVENT_POLL
1341 May be defined to allow interrupt polling 1346 May be defined to allow interrupt polling
1342 instead of using asynchronous interrupts 1347 instead of using asynchronous interrupts
1343 1348
1344 CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the 1349 CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
1345 txfilltuning field in the EHCI controller on reset. 1350 txfilltuning field in the EHCI controller on reset.
1346 1351
1347 CONFIG_USB_HUB_MIN_POWER_ON_DELAY defines the minimum 1352 CONFIG_USB_HUB_MIN_POWER_ON_DELAY defines the minimum
1348 interval for usb hub power-on delay.(minimum 100msec) 1353 interval for usb hub power-on delay.(minimum 100msec)
1349 1354
1350 - USB Device: 1355 - USB Device:
1351 Define the below if you wish to use the USB console. 1356 Define the below if you wish to use the USB console.
1352 Once firmware is rebuilt from a serial console issue the 1357 Once firmware is rebuilt from a serial console issue the
1353 command "setenv stdin usbtty; setenv stdout usbtty" and 1358 command "setenv stdin usbtty; setenv stdout usbtty" and
1354 attach your USB cable. The Unix command "dmesg" should print 1359 attach your USB cable. The Unix command "dmesg" should print
1355 it has found a new device. The environment variable usbtty 1360 it has found a new device. The environment variable usbtty
1356 can be set to gserial or cdc_acm to enable your device to 1361 can be set to gserial or cdc_acm to enable your device to
1357 appear to a USB host as a Linux gserial device or a 1362 appear to a USB host as a Linux gserial device or a
1358 Common Device Class Abstract Control Model serial device. 1363 Common Device Class Abstract Control Model serial device.
1359 If you select usbtty = gserial you should be able to enumerate 1364 If you select usbtty = gserial you should be able to enumerate
1360 a Linux host by 1365 a Linux host by
1361 # modprobe usbserial vendor=0xVendorID product=0xProductID 1366 # modprobe usbserial vendor=0xVendorID product=0xProductID
1362 else if using cdc_acm, simply setting the environment 1367 else if using cdc_acm, simply setting the environment
1363 variable usbtty to be cdc_acm should suffice. The following 1368 variable usbtty to be cdc_acm should suffice. The following
1364 might be defined in YourBoardName.h 1369 might be defined in YourBoardName.h
1365 1370
1366 CONFIG_USB_DEVICE 1371 CONFIG_USB_DEVICE
1367 Define this to build a UDC device 1372 Define this to build a UDC device
1368 1373
1369 CONFIG_USB_TTY 1374 CONFIG_USB_TTY
1370 Define this to have a tty type of device available to 1375 Define this to have a tty type of device available to
1371 talk to the UDC device 1376 talk to the UDC device
1372 1377
1373 CONFIG_USBD_HS 1378 CONFIG_USBD_HS
1374 Define this to enable the high speed support for usb 1379 Define this to enable the high speed support for usb
1375 device and usbtty. If this feature is enabled, a routine 1380 device and usbtty. If this feature is enabled, a routine
1376 int is_usbd_high_speed(void) 1381 int is_usbd_high_speed(void)
1377 also needs to be defined by the driver to dynamically poll 1382 also needs to be defined by the driver to dynamically poll
1378 whether the enumeration has succeded at high speed or full 1383 whether the enumeration has succeded at high speed or full
1379 speed. 1384 speed.
1380 1385
1381 CONFIG_SYS_CONSOLE_IS_IN_ENV 1386 CONFIG_SYS_CONSOLE_IS_IN_ENV
1382 Define this if you want stdin, stdout &/or stderr to 1387 Define this if you want stdin, stdout &/or stderr to
1383 be set to usbtty. 1388 be set to usbtty.
1384 1389
1385 mpc8xx: 1390 mpc8xx:
1386 CONFIG_SYS_USB_EXTC_CLK 0xBLAH 1391 CONFIG_SYS_USB_EXTC_CLK 0xBLAH
1387 Derive USB clock from external clock "blah" 1392 Derive USB clock from external clock "blah"
1388 - CONFIG_SYS_USB_EXTC_CLK 0x02 1393 - CONFIG_SYS_USB_EXTC_CLK 0x02
1389 1394
1390 CONFIG_SYS_USB_BRG_CLK 0xBLAH 1395 CONFIG_SYS_USB_BRG_CLK 0xBLAH
1391 Derive USB clock from brgclk 1396 Derive USB clock from brgclk
1392 - CONFIG_SYS_USB_BRG_CLK 0x04 1397 - CONFIG_SYS_USB_BRG_CLK 0x04
1393 1398
1394 If you have a USB-IF assigned VendorID then you may wish to 1399 If you have a USB-IF assigned VendorID then you may wish to
1395 define your own vendor specific values either in BoardName.h 1400 define your own vendor specific values either in BoardName.h
1396 or directly in usbd_vendor_info.h. If you don't define 1401 or directly in usbd_vendor_info.h. If you don't define
1397 CONFIG_USBD_MANUFACTURER, CONFIG_USBD_PRODUCT_NAME, 1402 CONFIG_USBD_MANUFACTURER, CONFIG_USBD_PRODUCT_NAME,
1398 CONFIG_USBD_VENDORID and CONFIG_USBD_PRODUCTID, then U-Boot 1403 CONFIG_USBD_VENDORID and CONFIG_USBD_PRODUCTID, then U-Boot
1399 should pretend to be a Linux device to it's target host. 1404 should pretend to be a Linux device to it's target host.
1400 1405
1401 CONFIG_USBD_MANUFACTURER 1406 CONFIG_USBD_MANUFACTURER
1402 Define this string as the name of your company for 1407 Define this string as the name of your company for
1403 - CONFIG_USBD_MANUFACTURER "my company" 1408 - CONFIG_USBD_MANUFACTURER "my company"
1404 1409
1405 CONFIG_USBD_PRODUCT_NAME 1410 CONFIG_USBD_PRODUCT_NAME
1406 Define this string as the name of your product 1411 Define this string as the name of your product
1407 - CONFIG_USBD_PRODUCT_NAME "acme usb device" 1412 - CONFIG_USBD_PRODUCT_NAME "acme usb device"
1408 1413
1409 CONFIG_USBD_VENDORID 1414 CONFIG_USBD_VENDORID
1410 Define this as your assigned Vendor ID from the USB 1415 Define this as your assigned Vendor ID from the USB
1411 Implementors Forum. This *must* be a genuine Vendor ID 1416 Implementors Forum. This *must* be a genuine Vendor ID
1412 to avoid polluting the USB namespace. 1417 to avoid polluting the USB namespace.
1413 - CONFIG_USBD_VENDORID 0xFFFF 1418 - CONFIG_USBD_VENDORID 0xFFFF
1414 1419
1415 CONFIG_USBD_PRODUCTID 1420 CONFIG_USBD_PRODUCTID
1416 Define this as the unique Product ID 1421 Define this as the unique Product ID
1417 for your device 1422 for your device
1418 - CONFIG_USBD_PRODUCTID 0xFFFF 1423 - CONFIG_USBD_PRODUCTID 0xFFFF
1419 1424
1420 Some USB device drivers may need to check USB cable attachment. 1425 Some USB device drivers may need to check USB cable attachment.
1421 In this case you can enable following config in BoardName.h: 1426 In this case you can enable following config in BoardName.h:
1422 CONFIG_USB_CABLE_CHECK 1427 CONFIG_USB_CABLE_CHECK
1423 This enables function definition: 1428 This enables function definition:
1424 - usb_cable_connected() in include/usb.h 1429 - usb_cable_connected() in include/usb.h
1425 Implementation of this function is board-specific. 1430 Implementation of this function is board-specific.
1426 1431
1427 - ULPI Layer Support: 1432 - ULPI Layer Support:
1428 The ULPI (UTMI Low Pin (count) Interface) PHYs are supported via 1433 The ULPI (UTMI Low Pin (count) Interface) PHYs are supported via
1429 the generic ULPI layer. The generic layer accesses the ULPI PHY 1434 the generic ULPI layer. The generic layer accesses the ULPI PHY
1430 via the platform viewport, so you need both the genric layer and 1435 via the platform viewport, so you need both the genric layer and
1431 the viewport enabled. Currently only Chipidea/ARC based 1436 the viewport enabled. Currently only Chipidea/ARC based
1432 viewport is supported. 1437 viewport is supported.
1433 To enable the ULPI layer support, define CONFIG_USB_ULPI and 1438 To enable the ULPI layer support, define CONFIG_USB_ULPI and
1434 CONFIG_USB_ULPI_VIEWPORT in your board configuration file. 1439 CONFIG_USB_ULPI_VIEWPORT in your board configuration file.
1435 If your ULPI phy needs a different reference clock than the 1440 If your ULPI phy needs a different reference clock than the
1436 standard 24 MHz then you have to define CONFIG_ULPI_REF_CLK to 1441 standard 24 MHz then you have to define CONFIG_ULPI_REF_CLK to
1437 the appropriate value in Hz. 1442 the appropriate value in Hz.
1438 1443
1439 - MMC Support: 1444 - MMC Support:
1440 The MMC controller on the Intel PXA is supported. To 1445 The MMC controller on the Intel PXA is supported. To
1441 enable this define CONFIG_MMC. The MMC can be 1446 enable this define CONFIG_MMC. The MMC can be
1442 accessed from the boot prompt by mapping the device 1447 accessed from the boot prompt by mapping the device
1443 to physical memory similar to flash. Command line is 1448 to physical memory similar to flash. Command line is
1444 enabled with CONFIG_CMD_MMC. The MMC driver also works with 1449 enabled with CONFIG_CMD_MMC. The MMC driver also works with
1445 the FAT fs. This is enabled with CONFIG_CMD_FAT. 1450 the FAT fs. This is enabled with CONFIG_CMD_FAT.
1446 1451
1447 CONFIG_SH_MMCIF 1452 CONFIG_SH_MMCIF
1448 Support for Renesas on-chip MMCIF controller 1453 Support for Renesas on-chip MMCIF controller
1449 1454
1450 CONFIG_SH_MMCIF_ADDR 1455 CONFIG_SH_MMCIF_ADDR
1451 Define the base address of MMCIF registers 1456 Define the base address of MMCIF registers
1452 1457
1453 CONFIG_SH_MMCIF_CLK 1458 CONFIG_SH_MMCIF_CLK
1454 Define the clock frequency for MMCIF 1459 Define the clock frequency for MMCIF
1455 1460
1456 - USB Device Firmware Update (DFU) class support: 1461 - USB Device Firmware Update (DFU) class support:
1457 CONFIG_DFU_FUNCTION 1462 CONFIG_DFU_FUNCTION
1458 This enables the USB portion of the DFU USB class 1463 This enables the USB portion of the DFU USB class
1459 1464
1460 CONFIG_CMD_DFU 1465 CONFIG_CMD_DFU
1461 This enables the command "dfu" which is used to have 1466 This enables the command "dfu" which is used to have
1462 U-Boot create a DFU class device via USB. This command 1467 U-Boot create a DFU class device via USB. This command
1463 requires that the "dfu_alt_info" environment variable be 1468 requires that the "dfu_alt_info" environment variable be
1464 set and define the alt settings to expose to the host. 1469 set and define the alt settings to expose to the host.
1465 1470
1466 CONFIG_DFU_MMC 1471 CONFIG_DFU_MMC
1467 This enables support for exposing (e)MMC devices via DFU. 1472 This enables support for exposing (e)MMC devices via DFU.
1468 1473
1469 CONFIG_DFU_NAND 1474 CONFIG_DFU_NAND
1470 This enables support for exposing NAND devices via DFU. 1475 This enables support for exposing NAND devices via DFU.
1471 1476
1472 CONFIG_DFU_RAM 1477 CONFIG_DFU_RAM
1473 This enables support for exposing RAM via DFU. 1478 This enables support for exposing RAM via DFU.
1474 Note: DFU spec refer to non-volatile memory usage, but 1479 Note: DFU spec refer to non-volatile memory usage, but
1475 allow usages beyond the scope of spec - here RAM usage, 1480 allow usages beyond the scope of spec - here RAM usage,
1476 one that would help mostly the developer. 1481 one that would help mostly the developer.
1477 1482
1478 CONFIG_SYS_DFU_DATA_BUF_SIZE 1483 CONFIG_SYS_DFU_DATA_BUF_SIZE
1479 Dfu transfer uses a buffer before writing data to the 1484 Dfu transfer uses a buffer before writing data to the
1480 raw storage device. Make the size (in bytes) of this buffer 1485 raw storage device. Make the size (in bytes) of this buffer
1481 configurable. The size of this buffer is also configurable 1486 configurable. The size of this buffer is also configurable
1482 through the "dfu_bufsiz" environment variable. 1487 through the "dfu_bufsiz" environment variable.
1483 1488
1484 CONFIG_SYS_DFU_MAX_FILE_SIZE 1489 CONFIG_SYS_DFU_MAX_FILE_SIZE
1485 When updating files rather than the raw storage device, 1490 When updating files rather than the raw storage device,
1486 we use a static buffer to copy the file into and then write 1491 we use a static buffer to copy the file into and then write
1487 the buffer once we've been given the whole file. Define 1492 the buffer once we've been given the whole file. Define
1488 this to the maximum filesize (in bytes) for the buffer. 1493 this to the maximum filesize (in bytes) for the buffer.
1489 Default is 4 MiB if undefined. 1494 Default is 4 MiB if undefined.
1490 1495
1491 - Journaling Flash filesystem support: 1496 - Journaling Flash filesystem support:
1492 CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE, 1497 CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
1493 CONFIG_JFFS2_NAND_DEV 1498 CONFIG_JFFS2_NAND_DEV
1494 Define these for a default partition on a NAND device 1499 Define these for a default partition on a NAND device
1495 1500
1496 CONFIG_SYS_JFFS2_FIRST_SECTOR, 1501 CONFIG_SYS_JFFS2_FIRST_SECTOR,
1497 CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS 1502 CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
1498 Define these for a default partition on a NOR device 1503 Define these for a default partition on a NOR device
1499 1504
1500 CONFIG_SYS_JFFS_CUSTOM_PART 1505 CONFIG_SYS_JFFS_CUSTOM_PART
1501 Define this to create an own partition. You have to provide a 1506 Define this to create an own partition. You have to provide a
1502 function struct part_info* jffs2_part_info(int part_num) 1507 function struct part_info* jffs2_part_info(int part_num)
1503 1508
1504 If you define only one JFFS2 partition you may also want to 1509 If you define only one JFFS2 partition you may also want to
1505 #define CONFIG_SYS_JFFS_SINGLE_PART 1 1510 #define CONFIG_SYS_JFFS_SINGLE_PART 1
1506 to disable the command chpart. This is the default when you 1511 to disable the command chpart. This is the default when you
1507 have not defined a custom partition 1512 have not defined a custom partition
1508 1513
1509 - FAT(File Allocation Table) filesystem write function support: 1514 - FAT(File Allocation Table) filesystem write function support:
1510 CONFIG_FAT_WRITE 1515 CONFIG_FAT_WRITE
1511 1516
1512 Define this to enable support for saving memory data as a 1517 Define this to enable support for saving memory data as a
1513 file in FAT formatted partition. 1518 file in FAT formatted partition.
1514 1519
1515 This will also enable the command "fatwrite" enabling the 1520 This will also enable the command "fatwrite" enabling the
1516 user to write files to FAT. 1521 user to write files to FAT.
1517 1522
1518 CBFS (Coreboot Filesystem) support 1523 CBFS (Coreboot Filesystem) support
1519 CONFIG_CMD_CBFS 1524 CONFIG_CMD_CBFS
1520 1525
1521 Define this to enable support for reading from a Coreboot 1526 Define this to enable support for reading from a Coreboot
1522 filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls 1527 filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls
1523 and cbfsload. 1528 and cbfsload.
1524 1529
1525 - Keyboard Support: 1530 - Keyboard Support:
1526 CONFIG_ISA_KEYBOARD 1531 CONFIG_ISA_KEYBOARD
1527 1532
1528 Define this to enable standard (PC-Style) keyboard 1533 Define this to enable standard (PC-Style) keyboard
1529 support 1534 support
1530 1535
1531 CONFIG_I8042_KBD 1536 CONFIG_I8042_KBD
1532 Standard PC keyboard driver with US (is default) and 1537 Standard PC keyboard driver with US (is default) and
1533 GERMAN key layout (switch via environment 'keymap=de') support. 1538 GERMAN key layout (switch via environment 'keymap=de') support.
1534 Export function i8042_kbd_init, i8042_tstc and i8042_getc 1539 Export function i8042_kbd_init, i8042_tstc and i8042_getc
1535 for cfb_console. Supports cursor blinking. 1540 for cfb_console. Supports cursor blinking.
1536 1541
1537 CONFIG_CROS_EC_KEYB 1542 CONFIG_CROS_EC_KEYB
1538 Enables a Chrome OS keyboard using the CROS_EC interface. 1543 Enables a Chrome OS keyboard using the CROS_EC interface.
1539 This uses CROS_EC to communicate with a second microcontroller 1544 This uses CROS_EC to communicate with a second microcontroller
1540 which provides key scans on request. 1545 which provides key scans on request.
1541 1546
1542 - Video support: 1547 - Video support:
1543 CONFIG_VIDEO 1548 CONFIG_VIDEO
1544 1549
1545 Define this to enable video support (for output to 1550 Define this to enable video support (for output to
1546 video). 1551 video).
1547 1552
1548 CONFIG_VIDEO_CT69000 1553 CONFIG_VIDEO_CT69000
1549 1554
1550 Enable Chips & Technologies 69000 Video chip 1555 Enable Chips & Technologies 69000 Video chip
1551 1556
1552 CONFIG_VIDEO_SMI_LYNXEM 1557 CONFIG_VIDEO_SMI_LYNXEM
1553 Enable Silicon Motion SMI 712/710/810 Video chip. The 1558 Enable Silicon Motion SMI 712/710/810 Video chip. The
1554 video output is selected via environment 'videoout' 1559 video output is selected via environment 'videoout'
1555 (1 = LCD and 2 = CRT). If videoout is undefined, CRT is 1560 (1 = LCD and 2 = CRT). If videoout is undefined, CRT is
1556 assumed. 1561 assumed.
1557 1562
1558 For the CT69000 and SMI_LYNXEM drivers, videomode is 1563 For the CT69000 and SMI_LYNXEM drivers, videomode is
1559 selected via environment 'videomode'. Two different ways 1564 selected via environment 'videomode'. Two different ways
1560 are possible: 1565 are possible:
1561 - "videomode=num" 'num' is a standard LiLo mode numbers. 1566 - "videomode=num" 'num' is a standard LiLo mode numbers.
1562 Following standard modes are supported (* is default): 1567 Following standard modes are supported (* is default):
1563 1568
1564 Colors 640x480 800x600 1024x768 1152x864 1280x1024 1569 Colors 640x480 800x600 1024x768 1152x864 1280x1024
1565 -------------+--------------------------------------------- 1570 -------------+---------------------------------------------
1566 8 bits | 0x301* 0x303 0x305 0x161 0x307 1571 8 bits | 0x301* 0x303 0x305 0x161 0x307
1567 15 bits | 0x310 0x313 0x316 0x162 0x319 1572 15 bits | 0x310 0x313 0x316 0x162 0x319
1568 16 bits | 0x311 0x314 0x317 0x163 0x31A 1573 16 bits | 0x311 0x314 0x317 0x163 0x31A
1569 24 bits | 0x312 0x315 0x318 ? 0x31B 1574 24 bits | 0x312 0x315 0x318 ? 0x31B
1570 -------------+--------------------------------------------- 1575 -------------+---------------------------------------------
1571 (i.e. setenv videomode 317; saveenv; reset;) 1576 (i.e. setenv videomode 317; saveenv; reset;)
1572 1577
1573 - "videomode=bootargs" all the video parameters are parsed 1578 - "videomode=bootargs" all the video parameters are parsed
1574 from the bootargs. (See drivers/video/videomodes.c) 1579 from the bootargs. (See drivers/video/videomodes.c)
1575 1580
1576 1581
1577 CONFIG_VIDEO_SED13806 1582 CONFIG_VIDEO_SED13806
1578 Enable Epson SED13806 driver. This driver supports 8bpp 1583 Enable Epson SED13806 driver. This driver supports 8bpp
1579 and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP 1584 and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP
1580 or CONFIG_VIDEO_SED13806_16BPP 1585 or CONFIG_VIDEO_SED13806_16BPP
1581 1586
1582 CONFIG_FSL_DIU_FB 1587 CONFIG_FSL_DIU_FB
1583 Enable the Freescale DIU video driver. Reference boards for 1588 Enable the Freescale DIU video driver. Reference boards for
1584 SOCs that have a DIU should define this macro to enable DIU 1589 SOCs that have a DIU should define this macro to enable DIU
1585 support, and should also define these other macros: 1590 support, and should also define these other macros:
1586 1591
1587 CONFIG_SYS_DIU_ADDR 1592 CONFIG_SYS_DIU_ADDR
1588 CONFIG_VIDEO 1593 CONFIG_VIDEO
1589 CONFIG_CMD_BMP 1594 CONFIG_CMD_BMP
1590 CONFIG_CFB_CONSOLE 1595 CONFIG_CFB_CONSOLE
1591 CONFIG_VIDEO_SW_CURSOR 1596 CONFIG_VIDEO_SW_CURSOR
1592 CONFIG_VGA_AS_SINGLE_DEVICE 1597 CONFIG_VGA_AS_SINGLE_DEVICE
1593 CONFIG_VIDEO_LOGO 1598 CONFIG_VIDEO_LOGO
1594 CONFIG_VIDEO_BMP_LOGO 1599 CONFIG_VIDEO_BMP_LOGO
1595 1600
1596 The DIU driver will look for the 'video-mode' environment 1601 The DIU driver will look for the 'video-mode' environment
1597 variable, and if defined, enable the DIU as a console during 1602 variable, and if defined, enable the DIU as a console during
1598 boot. See the documentation file README.video for a 1603 boot. See the documentation file README.video for a
1599 description of this variable. 1604 description of this variable.
1600 1605
1601 CONFIG_VIDEO_VGA 1606 CONFIG_VIDEO_VGA
1602 1607
1603 Enable the VGA video / BIOS for x86. The alternative if you 1608 Enable the VGA video / BIOS for x86. The alternative if you
1604 are using coreboot is to use the coreboot frame buffer 1609 are using coreboot is to use the coreboot frame buffer
1605 driver. 1610 driver.
1606 1611
1607 1612
1608 - Keyboard Support: 1613 - Keyboard Support:
1609 CONFIG_KEYBOARD 1614 CONFIG_KEYBOARD
1610 1615
1611 Define this to enable a custom keyboard support. 1616 Define this to enable a custom keyboard support.
1612 This simply calls drv_keyboard_init() which must be 1617 This simply calls drv_keyboard_init() which must be
1613 defined in your board-specific files. 1618 defined in your board-specific files.
1614 The only board using this so far is RBC823. 1619 The only board using this so far is RBC823.
1615 1620
1616 - LCD Support: CONFIG_LCD 1621 - LCD Support: CONFIG_LCD
1617 1622
1618 Define this to enable LCD support (for output to LCD 1623 Define this to enable LCD support (for output to LCD
1619 display); also select one of the supported displays 1624 display); also select one of the supported displays
1620 by defining one of these: 1625 by defining one of these:
1621 1626
1622 CONFIG_ATMEL_LCD: 1627 CONFIG_ATMEL_LCD:
1623 1628
1624 HITACHI TX09D70VM1CCA, 3.5", 240x320. 1629 HITACHI TX09D70VM1CCA, 3.5", 240x320.
1625 1630
1626 CONFIG_NEC_NL6448AC33: 1631 CONFIG_NEC_NL6448AC33:
1627 1632
1628 NEC NL6448AC33-18. Active, color, single scan. 1633 NEC NL6448AC33-18. Active, color, single scan.
1629 1634
1630 CONFIG_NEC_NL6448BC20 1635 CONFIG_NEC_NL6448BC20
1631 1636
1632 NEC NL6448BC20-08. 6.5", 640x480. 1637 NEC NL6448BC20-08. 6.5", 640x480.
1633 Active, color, single scan. 1638 Active, color, single scan.
1634 1639
1635 CONFIG_NEC_NL6448BC33_54 1640 CONFIG_NEC_NL6448BC33_54
1636 1641
1637 NEC NL6448BC33-54. 10.4", 640x480. 1642 NEC NL6448BC33-54. 10.4", 640x480.
1638 Active, color, single scan. 1643 Active, color, single scan.
1639 1644
1640 CONFIG_SHARP_16x9 1645 CONFIG_SHARP_16x9
1641 1646
1642 Sharp 320x240. Active, color, single scan. 1647 Sharp 320x240. Active, color, single scan.
1643 It isn't 16x9, and I am not sure what it is. 1648 It isn't 16x9, and I am not sure what it is.
1644 1649
1645 CONFIG_SHARP_LQ64D341 1650 CONFIG_SHARP_LQ64D341
1646 1651
1647 Sharp LQ64D341 display, 640x480. 1652 Sharp LQ64D341 display, 640x480.
1648 Active, color, single scan. 1653 Active, color, single scan.
1649 1654
1650 CONFIG_HLD1045 1655 CONFIG_HLD1045
1651 1656
1652 HLD1045 display, 640x480. 1657 HLD1045 display, 640x480.
1653 Active, color, single scan. 1658 Active, color, single scan.
1654 1659
1655 CONFIG_OPTREX_BW 1660 CONFIG_OPTREX_BW
1656 1661
1657 Optrex CBL50840-2 NF-FW 99 22 M5 1662 Optrex CBL50840-2 NF-FW 99 22 M5
1658 or 1663 or
1659 Hitachi LMG6912RPFC-00T 1664 Hitachi LMG6912RPFC-00T
1660 or 1665 or
1661 Hitachi SP14Q002 1666 Hitachi SP14Q002
1662 1667
1663 320x240. Black & white. 1668 320x240. Black & white.
1664 1669
1665 Normally display is black on white background; define 1670 Normally display is black on white background; define
1666 CONFIG_SYS_WHITE_ON_BLACK to get it inverted. 1671 CONFIG_SYS_WHITE_ON_BLACK to get it inverted.
1667 1672
1668 CONFIG_LCD_ALIGNMENT 1673 CONFIG_LCD_ALIGNMENT
1669 1674
1670 Normally the LCD is page-aligned (tyically 4KB). If this is 1675 Normally the LCD is page-aligned (tyically 4KB). If this is
1671 defined then the LCD will be aligned to this value instead. 1676 defined then the LCD will be aligned to this value instead.
1672 For ARM it is sometimes useful to use MMU_SECTION_SIZE 1677 For ARM it is sometimes useful to use MMU_SECTION_SIZE
1673 here, since it is cheaper to change data cache settings on 1678 here, since it is cheaper to change data cache settings on
1674 a per-section basis. 1679 a per-section basis.
1675 1680
1676 CONFIG_CONSOLE_SCROLL_LINES 1681 CONFIG_CONSOLE_SCROLL_LINES
1677 1682
1678 When the console need to be scrolled, this is the number of 1683 When the console need to be scrolled, this is the number of
1679 lines to scroll by. It defaults to 1. Increasing this makes 1684 lines to scroll by. It defaults to 1. Increasing this makes
1680 the console jump but can help speed up operation when scrolling 1685 the console jump but can help speed up operation when scrolling
1681 is slow. 1686 is slow.
1682 1687
1683 CONFIG_LCD_BMP_RLE8 1688 CONFIG_LCD_BMP_RLE8
1684 1689
1685 Support drawing of RLE8-compressed bitmaps on the LCD. 1690 Support drawing of RLE8-compressed bitmaps on the LCD.
1686 1691
1687 CONFIG_I2C_EDID 1692 CONFIG_I2C_EDID
1688 1693
1689 Enables an 'i2c edid' command which can read EDID 1694 Enables an 'i2c edid' command which can read EDID
1690 information over I2C from an attached LCD display. 1695 information over I2C from an attached LCD display.
1691 1696
1692 - Splash Screen Support: CONFIG_SPLASH_SCREEN 1697 - Splash Screen Support: CONFIG_SPLASH_SCREEN
1693 1698
1694 If this option is set, the environment is checked for 1699 If this option is set, the environment is checked for
1695 a variable "splashimage". If found, the usual display 1700 a variable "splashimage". If found, the usual display
1696 of logo, copyright and system information on the LCD 1701 of logo, copyright and system information on the LCD
1697 is suppressed and the BMP image at the address 1702 is suppressed and the BMP image at the address
1698 specified in "splashimage" is loaded instead. The 1703 specified in "splashimage" is loaded instead. The
1699 console is redirected to the "nulldev", too. This 1704 console is redirected to the "nulldev", too. This
1700 allows for a "silent" boot where a splash screen is 1705 allows for a "silent" boot where a splash screen is
1701 loaded very quickly after power-on. 1706 loaded very quickly after power-on.
1702 1707
1703 CONFIG_SPLASHIMAGE_GUARD 1708 CONFIG_SPLASHIMAGE_GUARD
1704 1709
1705 If this option is set, then U-Boot will prevent the environment 1710 If this option is set, then U-Boot will prevent the environment
1706 variable "splashimage" from being set to a problematic address 1711 variable "splashimage" from being set to a problematic address
1707 (see README.displaying-bmps and README.arm-unaligned-accesses). 1712 (see README.displaying-bmps and README.arm-unaligned-accesses).
1708 This option is useful for targets where, due to alignment 1713 This option is useful for targets where, due to alignment
1709 restrictions, an improperly aligned BMP image will cause a data 1714 restrictions, an improperly aligned BMP image will cause a data
1710 abort. If you think you will not have problems with unaligned 1715 abort. If you think you will not have problems with unaligned
1711 accesses (for example because your toolchain prevents them) 1716 accesses (for example because your toolchain prevents them)
1712 there is no need to set this option. 1717 there is no need to set this option.
1713 1718
1714 CONFIG_SPLASH_SCREEN_ALIGN 1719 CONFIG_SPLASH_SCREEN_ALIGN
1715 1720
1716 If this option is set the splash image can be freely positioned 1721 If this option is set the splash image can be freely positioned
1717 on the screen. Environment variable "splashpos" specifies the 1722 on the screen. Environment variable "splashpos" specifies the
1718 position as "x,y". If a positive number is given it is used as 1723 position as "x,y". If a positive number is given it is used as
1719 number of pixel from left/top. If a negative number is given it 1724 number of pixel from left/top. If a negative number is given it
1720 is used as number of pixel from right/bottom. You can also 1725 is used as number of pixel from right/bottom. You can also
1721 specify 'm' for centering the image. 1726 specify 'm' for centering the image.
1722 1727
1723 Example: 1728 Example:
1724 setenv splashpos m,m 1729 setenv splashpos m,m
1725 => image at center of screen 1730 => image at center of screen
1726 1731
1727 setenv splashpos 30,20 1732 setenv splashpos 30,20
1728 => image at x = 30 and y = 20 1733 => image at x = 30 and y = 20
1729 1734
1730 setenv splashpos -10,m 1735 setenv splashpos -10,m
1731 => vertically centered image 1736 => vertically centered image
1732 at x = dspWidth - bmpWidth - 9 1737 at x = dspWidth - bmpWidth - 9
1733 1738
1734 - Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP 1739 - Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP
1735 1740
1736 If this option is set, additionally to standard BMP 1741 If this option is set, additionally to standard BMP
1737 images, gzipped BMP images can be displayed via the 1742 images, gzipped BMP images can be displayed via the
1738 splashscreen support or the bmp command. 1743 splashscreen support or the bmp command.
1739 1744
1740 - Run length encoded BMP image (RLE8) support: CONFIG_VIDEO_BMP_RLE8 1745 - Run length encoded BMP image (RLE8) support: CONFIG_VIDEO_BMP_RLE8
1741 1746
1742 If this option is set, 8-bit RLE compressed BMP images 1747 If this option is set, 8-bit RLE compressed BMP images
1743 can be displayed via the splashscreen support or the 1748 can be displayed via the splashscreen support or the
1744 bmp command. 1749 bmp command.
1745 1750
1746 - Do compresssing for memory range: 1751 - Do compresssing for memory range:
1747 CONFIG_CMD_ZIP 1752 CONFIG_CMD_ZIP
1748 1753
1749 If this option is set, it would use zlib deflate method 1754 If this option is set, it would use zlib deflate method
1750 to compress the specified memory at its best effort. 1755 to compress the specified memory at its best effort.
1751 1756
1752 - Compression support: 1757 - Compression support:
1753 CONFIG_GZIP 1758 CONFIG_GZIP
1754 1759
1755 Enabled by default to support gzip compressed images. 1760 Enabled by default to support gzip compressed images.
1756 1761
1757 CONFIG_BZIP2 1762 CONFIG_BZIP2
1758 1763
1759 If this option is set, support for bzip2 compressed 1764 If this option is set, support for bzip2 compressed
1760 images is included. If not, only uncompressed and gzip 1765 images is included. If not, only uncompressed and gzip
1761 compressed images are supported. 1766 compressed images are supported.
1762 1767
1763 NOTE: the bzip2 algorithm requires a lot of RAM, so 1768 NOTE: the bzip2 algorithm requires a lot of RAM, so
1764 the malloc area (as defined by CONFIG_SYS_MALLOC_LEN) should 1769 the malloc area (as defined by CONFIG_SYS_MALLOC_LEN) should
1765 be at least 4MB. 1770 be at least 4MB.
1766 1771
1767 CONFIG_LZMA 1772 CONFIG_LZMA
1768 1773
1769 If this option is set, support for lzma compressed 1774 If this option is set, support for lzma compressed
1770 images is included. 1775 images is included.
1771 1776
1772 Note: The LZMA algorithm adds between 2 and 4KB of code and it 1777 Note: The LZMA algorithm adds between 2 and 4KB of code and it
1773 requires an amount of dynamic memory that is given by the 1778 requires an amount of dynamic memory that is given by the
1774 formula: 1779 formula:
1775 1780
1776 (1846 + 768 << (lc + lp)) * sizeof(uint16) 1781 (1846 + 768 << (lc + lp)) * sizeof(uint16)
1777 1782
1778 Where lc and lp stand for, respectively, Literal context bits 1783 Where lc and lp stand for, respectively, Literal context bits
1779 and Literal pos bits. 1784 and Literal pos bits.
1780 1785
1781 This value is upper-bounded by 14MB in the worst case. Anyway, 1786 This value is upper-bounded by 14MB in the worst case. Anyway,
1782 for a ~4MB large kernel image, we have lc=3 and lp=0 for a 1787 for a ~4MB large kernel image, we have lc=3 and lp=0 for a
1783 total amount of (1846 + 768 << (3 + 0)) * 2 = ~41KB... that is 1788 total amount of (1846 + 768 << (3 + 0)) * 2 = ~41KB... that is
1784 a very small buffer. 1789 a very small buffer.
1785 1790
1786 Use the lzmainfo tool to determinate the lc and lp values and 1791 Use the lzmainfo tool to determinate the lc and lp values and
1787 then calculate the amount of needed dynamic memory (ensuring 1792 then calculate the amount of needed dynamic memory (ensuring
1788 the appropriate CONFIG_SYS_MALLOC_LEN value). 1793 the appropriate CONFIG_SYS_MALLOC_LEN value).
1789 1794
1790 CONFIG_LZO 1795 CONFIG_LZO
1791 1796
1792 If this option is set, support for LZO compressed images 1797 If this option is set, support for LZO compressed images
1793 is included. 1798 is included.
1794 1799
1795 - MII/PHY support: 1800 - MII/PHY support:
1796 CONFIG_PHY_ADDR 1801 CONFIG_PHY_ADDR
1797 1802
1798 The address of PHY on MII bus. 1803 The address of PHY on MII bus.
1799 1804
1800 CONFIG_PHY_CLOCK_FREQ (ppc4xx) 1805 CONFIG_PHY_CLOCK_FREQ (ppc4xx)
1801 1806
1802 The clock frequency of the MII bus 1807 The clock frequency of the MII bus
1803 1808
1804 CONFIG_PHY_GIGE 1809 CONFIG_PHY_GIGE
1805 1810
1806 If this option is set, support for speed/duplex 1811 If this option is set, support for speed/duplex
1807 detection of gigabit PHY is included. 1812 detection of gigabit PHY is included.
1808 1813
1809 CONFIG_PHY_RESET_DELAY 1814 CONFIG_PHY_RESET_DELAY
1810 1815
1811 Some PHY like Intel LXT971A need extra delay after 1816 Some PHY like Intel LXT971A need extra delay after
1812 reset before any MII register access is possible. 1817 reset before any MII register access is possible.
1813 For such PHY, set this option to the usec delay 1818 For such PHY, set this option to the usec delay
1814 required. (minimum 300usec for LXT971A) 1819 required. (minimum 300usec for LXT971A)
1815 1820
1816 CONFIG_PHY_CMD_DELAY (ppc4xx) 1821 CONFIG_PHY_CMD_DELAY (ppc4xx)
1817 1822
1818 Some PHY like Intel LXT971A need extra delay after 1823 Some PHY like Intel LXT971A need extra delay after
1819 command issued before MII status register can be read 1824 command issued before MII status register can be read
1820 1825
1821 - Ethernet address: 1826 - Ethernet address:
1822 CONFIG_ETHADDR 1827 CONFIG_ETHADDR
1823 CONFIG_ETH1ADDR 1828 CONFIG_ETH1ADDR
1824 CONFIG_ETH2ADDR 1829 CONFIG_ETH2ADDR
1825 CONFIG_ETH3ADDR 1830 CONFIG_ETH3ADDR
1826 CONFIG_ETH4ADDR 1831 CONFIG_ETH4ADDR
1827 CONFIG_ETH5ADDR 1832 CONFIG_ETH5ADDR
1828 1833
1829 Define a default value for Ethernet address to use 1834 Define a default value for Ethernet address to use
1830 for the respective Ethernet interface, in case this 1835 for the respective Ethernet interface, in case this
1831 is not determined automatically. 1836 is not determined automatically.
1832 1837
1833 - IP address: 1838 - IP address:
1834 CONFIG_IPADDR 1839 CONFIG_IPADDR
1835 1840
1836 Define a default value for the IP address to use for 1841 Define a default value for the IP address to use for
1837 the default Ethernet interface, in case this is not 1842 the default Ethernet interface, in case this is not
1838 determined through e.g. bootp. 1843 determined through e.g. bootp.
1839 (Environment variable "ipaddr") 1844 (Environment variable "ipaddr")
1840 1845
1841 - Server IP address: 1846 - Server IP address:
1842 CONFIG_SERVERIP 1847 CONFIG_SERVERIP
1843 1848
1844 Defines a default value for the IP address of a TFTP 1849 Defines a default value for the IP address of a TFTP
1845 server to contact when using the "tftboot" command. 1850 server to contact when using the "tftboot" command.
1846 (Environment variable "serverip") 1851 (Environment variable "serverip")
1847 1852
1848 CONFIG_KEEP_SERVERADDR 1853 CONFIG_KEEP_SERVERADDR
1849 1854
1850 Keeps the server's MAC address, in the env 'serveraddr' 1855 Keeps the server's MAC address, in the env 'serveraddr'
1851 for passing to bootargs (like Linux's netconsole option) 1856 for passing to bootargs (like Linux's netconsole option)
1852 1857
1853 - Gateway IP address: 1858 - Gateway IP address:
1854 CONFIG_GATEWAYIP 1859 CONFIG_GATEWAYIP
1855 1860
1856 Defines a default value for the IP address of the 1861 Defines a default value for the IP address of the
1857 default router where packets to other networks are 1862 default router where packets to other networks are
1858 sent to. 1863 sent to.
1859 (Environment variable "gatewayip") 1864 (Environment variable "gatewayip")
1860 1865
1861 - Subnet mask: 1866 - Subnet mask:
1862 CONFIG_NETMASK 1867 CONFIG_NETMASK
1863 1868
1864 Defines a default value for the subnet mask (or 1869 Defines a default value for the subnet mask (or
1865 routing prefix) which is used to determine if an IP 1870 routing prefix) which is used to determine if an IP
1866 address belongs to the local subnet or needs to be 1871 address belongs to the local subnet or needs to be
1867 forwarded through a router. 1872 forwarded through a router.
1868 (Environment variable "netmask") 1873 (Environment variable "netmask")
1869 1874
1870 - Multicast TFTP Mode: 1875 - Multicast TFTP Mode:
1871 CONFIG_MCAST_TFTP 1876 CONFIG_MCAST_TFTP
1872 1877
1873 Defines whether you want to support multicast TFTP as per 1878 Defines whether you want to support multicast TFTP as per
1874 rfc-2090; for example to work with atftp. Lets lots of targets 1879 rfc-2090; for example to work with atftp. Lets lots of targets
1875 tftp down the same boot image concurrently. Note: the Ethernet 1880 tftp down the same boot image concurrently. Note: the Ethernet
1876 driver in use must provide a function: mcast() to join/leave a 1881 driver in use must provide a function: mcast() to join/leave a
1877 multicast group. 1882 multicast group.
1878 1883
1879 - BOOTP Recovery Mode: 1884 - BOOTP Recovery Mode:
1880 CONFIG_BOOTP_RANDOM_DELAY 1885 CONFIG_BOOTP_RANDOM_DELAY
1881 1886
1882 If you have many targets in a network that try to 1887 If you have many targets in a network that try to
1883 boot using BOOTP, you may want to avoid that all 1888 boot using BOOTP, you may want to avoid that all
1884 systems send out BOOTP requests at precisely the same 1889 systems send out BOOTP requests at precisely the same
1885 moment (which would happen for instance at recovery 1890 moment (which would happen for instance at recovery
1886 from a power failure, when all systems will try to 1891 from a power failure, when all systems will try to
1887 boot, thus flooding the BOOTP server. Defining 1892 boot, thus flooding the BOOTP server. Defining
1888 CONFIG_BOOTP_RANDOM_DELAY causes a random delay to be 1893 CONFIG_BOOTP_RANDOM_DELAY causes a random delay to be
1889 inserted before sending out BOOTP requests. The 1894 inserted before sending out BOOTP requests. The
1890 following delays are inserted then: 1895 following delays are inserted then:
1891 1896
1892 1st BOOTP request: delay 0 ... 1 sec 1897 1st BOOTP request: delay 0 ... 1 sec
1893 2nd BOOTP request: delay 0 ... 2 sec 1898 2nd BOOTP request: delay 0 ... 2 sec
1894 3rd BOOTP request: delay 0 ... 4 sec 1899 3rd BOOTP request: delay 0 ... 4 sec
1895 4th and following 1900 4th and following
1896 BOOTP requests: delay 0 ... 8 sec 1901 BOOTP requests: delay 0 ... 8 sec
1897 1902
1898 - DHCP Advanced Options: 1903 - DHCP Advanced Options:
1899 You can fine tune the DHCP functionality by defining 1904 You can fine tune the DHCP functionality by defining
1900 CONFIG_BOOTP_* symbols: 1905 CONFIG_BOOTP_* symbols:
1901 1906
1902 CONFIG_BOOTP_SUBNETMASK 1907 CONFIG_BOOTP_SUBNETMASK
1903 CONFIG_BOOTP_GATEWAY 1908 CONFIG_BOOTP_GATEWAY
1904 CONFIG_BOOTP_HOSTNAME 1909 CONFIG_BOOTP_HOSTNAME
1905 CONFIG_BOOTP_NISDOMAIN 1910 CONFIG_BOOTP_NISDOMAIN
1906 CONFIG_BOOTP_BOOTPATH 1911 CONFIG_BOOTP_BOOTPATH
1907 CONFIG_BOOTP_BOOTFILESIZE 1912 CONFIG_BOOTP_BOOTFILESIZE
1908 CONFIG_BOOTP_DNS 1913 CONFIG_BOOTP_DNS
1909 CONFIG_BOOTP_DNS2 1914 CONFIG_BOOTP_DNS2
1910 CONFIG_BOOTP_SEND_HOSTNAME 1915 CONFIG_BOOTP_SEND_HOSTNAME
1911 CONFIG_BOOTP_NTPSERVER 1916 CONFIG_BOOTP_NTPSERVER
1912 CONFIG_BOOTP_TIMEOFFSET 1917 CONFIG_BOOTP_TIMEOFFSET
1913 CONFIG_BOOTP_VENDOREX 1918 CONFIG_BOOTP_VENDOREX
1914 CONFIG_BOOTP_MAY_FAIL 1919 CONFIG_BOOTP_MAY_FAIL
1915 1920
1916 CONFIG_BOOTP_SERVERIP - TFTP server will be the serverip 1921 CONFIG_BOOTP_SERVERIP - TFTP server will be the serverip
1917 environment variable, not the BOOTP server. 1922 environment variable, not the BOOTP server.
1918 1923
1919 CONFIG_BOOTP_MAY_FAIL - If the DHCP server is not found 1924 CONFIG_BOOTP_MAY_FAIL - If the DHCP server is not found
1920 after the configured retry count, the call will fail 1925 after the configured retry count, the call will fail
1921 instead of starting over. This can be used to fail over 1926 instead of starting over. This can be used to fail over
1922 to Link-local IP address configuration if the DHCP server 1927 to Link-local IP address configuration if the DHCP server
1923 is not available. 1928 is not available.
1924 1929
1925 CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS 1930 CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS
1926 serverip from a DHCP server, it is possible that more 1931 serverip from a DHCP server, it is possible that more
1927 than one DNS serverip is offered to the client. 1932 than one DNS serverip is offered to the client.
1928 If CONFIG_BOOTP_DNS2 is enabled, the secondary DNS 1933 If CONFIG_BOOTP_DNS2 is enabled, the secondary DNS
1929 serverip will be stored in the additional environment 1934 serverip will be stored in the additional environment
1930 variable "dnsip2". The first DNS serverip is always 1935 variable "dnsip2". The first DNS serverip is always
1931 stored in the variable "dnsip", when CONFIG_BOOTP_DNS 1936 stored in the variable "dnsip", when CONFIG_BOOTP_DNS
1932 is defined. 1937 is defined.
1933 1938
1934 CONFIG_BOOTP_SEND_HOSTNAME - Some DHCP servers are capable 1939 CONFIG_BOOTP_SEND_HOSTNAME - Some DHCP servers are capable
1935 to do a dynamic update of a DNS server. To do this, they 1940 to do a dynamic update of a DNS server. To do this, they
1936 need the hostname of the DHCP requester. 1941 need the hostname of the DHCP requester.
1937 If CONFIG_BOOTP_SEND_HOSTNAME is defined, the content 1942 If CONFIG_BOOTP_SEND_HOSTNAME is defined, the content
1938 of the "hostname" environment variable is passed as 1943 of the "hostname" environment variable is passed as
1939 option 12 to the DHCP server. 1944 option 12 to the DHCP server.
1940 1945
1941 CONFIG_BOOTP_DHCP_REQUEST_DELAY 1946 CONFIG_BOOTP_DHCP_REQUEST_DELAY
1942 1947
1943 A 32bit value in microseconds for a delay between 1948 A 32bit value in microseconds for a delay between
1944 receiving a "DHCP Offer" and sending the "DHCP Request". 1949 receiving a "DHCP Offer" and sending the "DHCP Request".
1945 This fixes a problem with certain DHCP servers that don't 1950 This fixes a problem with certain DHCP servers that don't
1946 respond 100% of the time to a "DHCP request". E.g. On an 1951 respond 100% of the time to a "DHCP request". E.g. On an
1947 AT91RM9200 processor running at 180MHz, this delay needed 1952 AT91RM9200 processor running at 180MHz, this delay needed
1948 to be *at least* 15,000 usec before a Windows Server 2003 1953 to be *at least* 15,000 usec before a Windows Server 2003
1949 DHCP server would reply 100% of the time. I recommend at 1954 DHCP server would reply 100% of the time. I recommend at
1950 least 50,000 usec to be safe. The alternative is to hope 1955 least 50,000 usec to be safe. The alternative is to hope
1951 that one of the retries will be successful but note that 1956 that one of the retries will be successful but note that
1952 the DHCP timeout and retry process takes a longer than 1957 the DHCP timeout and retry process takes a longer than
1953 this delay. 1958 this delay.
1954 1959
1955 - Link-local IP address negotiation: 1960 - Link-local IP address negotiation:
1956 Negotiate with other link-local clients on the local network 1961 Negotiate with other link-local clients on the local network
1957 for an address that doesn't require explicit configuration. 1962 for an address that doesn't require explicit configuration.
1958 This is especially useful if a DHCP server cannot be guaranteed 1963 This is especially useful if a DHCP server cannot be guaranteed
1959 to exist in all environments that the device must operate. 1964 to exist in all environments that the device must operate.
1960 1965
1961 See doc/README.link-local for more information. 1966 See doc/README.link-local for more information.
1962 1967
1963 - CDP Options: 1968 - CDP Options:
1964 CONFIG_CDP_DEVICE_ID 1969 CONFIG_CDP_DEVICE_ID
1965 1970
1966 The device id used in CDP trigger frames. 1971 The device id used in CDP trigger frames.
1967 1972
1968 CONFIG_CDP_DEVICE_ID_PREFIX 1973 CONFIG_CDP_DEVICE_ID_PREFIX
1969 1974
1970 A two character string which is prefixed to the MAC address 1975 A two character string which is prefixed to the MAC address
1971 of the device. 1976 of the device.
1972 1977
1973 CONFIG_CDP_PORT_ID 1978 CONFIG_CDP_PORT_ID
1974 1979
1975 A printf format string which contains the ascii name of 1980 A printf format string which contains the ascii name of
1976 the port. Normally is set to "eth%d" which sets 1981 the port. Normally is set to "eth%d" which sets
1977 eth0 for the first Ethernet, eth1 for the second etc. 1982 eth0 for the first Ethernet, eth1 for the second etc.
1978 1983
1979 CONFIG_CDP_CAPABILITIES 1984 CONFIG_CDP_CAPABILITIES
1980 1985
1981 A 32bit integer which indicates the device capabilities; 1986 A 32bit integer which indicates the device capabilities;
1982 0x00000010 for a normal host which does not forwards. 1987 0x00000010 for a normal host which does not forwards.
1983 1988
1984 CONFIG_CDP_VERSION 1989 CONFIG_CDP_VERSION
1985 1990
1986 An ascii string containing the version of the software. 1991 An ascii string containing the version of the software.
1987 1992
1988 CONFIG_CDP_PLATFORM 1993 CONFIG_CDP_PLATFORM
1989 1994
1990 An ascii string containing the name of the platform. 1995 An ascii string containing the name of the platform.
1991 1996
1992 CONFIG_CDP_TRIGGER 1997 CONFIG_CDP_TRIGGER
1993 1998
1994 A 32bit integer sent on the trigger. 1999 A 32bit integer sent on the trigger.
1995 2000
1996 CONFIG_CDP_POWER_CONSUMPTION 2001 CONFIG_CDP_POWER_CONSUMPTION
1997 2002
1998 A 16bit integer containing the power consumption of the 2003 A 16bit integer containing the power consumption of the
1999 device in .1 of milliwatts. 2004 device in .1 of milliwatts.
2000 2005
2001 CONFIG_CDP_APPLIANCE_VLAN_TYPE 2006 CONFIG_CDP_APPLIANCE_VLAN_TYPE
2002 2007
2003 A byte containing the id of the VLAN. 2008 A byte containing the id of the VLAN.
2004 2009
2005 - Status LED: CONFIG_STATUS_LED 2010 - Status LED: CONFIG_STATUS_LED
2006 2011
2007 Several configurations allow to display the current 2012 Several configurations allow to display the current
2008 status using a LED. For instance, the LED will blink 2013 status using a LED. For instance, the LED will blink
2009 fast while running U-Boot code, stop blinking as 2014 fast while running U-Boot code, stop blinking as
2010 soon as a reply to a BOOTP request was received, and 2015 soon as a reply to a BOOTP request was received, and
2011 start blinking slow once the Linux kernel is running 2016 start blinking slow once the Linux kernel is running
2012 (supported by a status LED driver in the Linux 2017 (supported by a status LED driver in the Linux
2013 kernel). Defining CONFIG_STATUS_LED enables this 2018 kernel). Defining CONFIG_STATUS_LED enables this
2014 feature in U-Boot. 2019 feature in U-Boot.
2015 2020
2016 Additional options: 2021 Additional options:
2017 2022
2018 CONFIG_GPIO_LED 2023 CONFIG_GPIO_LED
2019 The status LED can be connected to a GPIO pin. 2024 The status LED can be connected to a GPIO pin.
2020 In such cases, the gpio_led driver can be used as a 2025 In such cases, the gpio_led driver can be used as a
2021 status LED backend implementation. Define CONFIG_GPIO_LED 2026 status LED backend implementation. Define CONFIG_GPIO_LED
2022 to include the gpio_led driver in the U-Boot binary. 2027 to include the gpio_led driver in the U-Boot binary.
2023 2028
2024 CONFIG_GPIO_LED_INVERTED_TABLE 2029 CONFIG_GPIO_LED_INVERTED_TABLE
2025 Some GPIO connected LEDs may have inverted polarity in which 2030 Some GPIO connected LEDs may have inverted polarity in which
2026 case the GPIO high value corresponds to LED off state and 2031 case the GPIO high value corresponds to LED off state and
2027 GPIO low value corresponds to LED on state. 2032 GPIO low value corresponds to LED on state.
2028 In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined 2033 In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
2029 with a list of GPIO LEDs that have inverted polarity. 2034 with a list of GPIO LEDs that have inverted polarity.
2030 2035
2031 - CAN Support: CONFIG_CAN_DRIVER 2036 - CAN Support: CONFIG_CAN_DRIVER
2032 2037
2033 Defining CONFIG_CAN_DRIVER enables CAN driver support 2038 Defining CONFIG_CAN_DRIVER enables CAN driver support
2034 on those systems that support this (optional) 2039 on those systems that support this (optional)
2035 feature, like the TQM8xxL modules. 2040 feature, like the TQM8xxL modules.
2036 2041
2037 - I2C Support: CONFIG_SYS_I2C 2042 - I2C Support: CONFIG_SYS_I2C
2038 2043
2039 This enable the NEW i2c subsystem, and will allow you to use 2044 This enable the NEW i2c subsystem, and will allow you to use
2040 i2c commands at the u-boot command line (as long as you set 2045 i2c commands at the u-boot command line (as long as you set
2041 CONFIG_CMD_I2C in CONFIG_COMMANDS) and communicate with i2c 2046 CONFIG_CMD_I2C in CONFIG_COMMANDS) and communicate with i2c
2042 based realtime clock chips or other i2c devices. See 2047 based realtime clock chips or other i2c devices. See
2043 common/cmd_i2c.c for a description of the command line 2048 common/cmd_i2c.c for a description of the command line
2044 interface. 2049 interface.
2045 2050
2046 ported i2c driver to the new framework: 2051 ported i2c driver to the new framework:
2047 - drivers/i2c/soft_i2c.c: 2052 - drivers/i2c/soft_i2c.c:
2048 - activate first bus with CONFIG_SYS_I2C_SOFT define 2053 - activate first bus with CONFIG_SYS_I2C_SOFT define
2049 CONFIG_SYS_I2C_SOFT_SPEED and CONFIG_SYS_I2C_SOFT_SLAVE 2054 CONFIG_SYS_I2C_SOFT_SPEED and CONFIG_SYS_I2C_SOFT_SLAVE
2050 for defining speed and slave address 2055 for defining speed and slave address
2051 - activate second bus with I2C_SOFT_DECLARATIONS2 define 2056 - activate second bus with I2C_SOFT_DECLARATIONS2 define
2052 CONFIG_SYS_I2C_SOFT_SPEED_2 and CONFIG_SYS_I2C_SOFT_SLAVE_2 2057 CONFIG_SYS_I2C_SOFT_SPEED_2 and CONFIG_SYS_I2C_SOFT_SLAVE_2
2053 for defining speed and slave address 2058 for defining speed and slave address
2054 - activate third bus with I2C_SOFT_DECLARATIONS3 define 2059 - activate third bus with I2C_SOFT_DECLARATIONS3 define
2055 CONFIG_SYS_I2C_SOFT_SPEED_3 and CONFIG_SYS_I2C_SOFT_SLAVE_3 2060 CONFIG_SYS_I2C_SOFT_SPEED_3 and CONFIG_SYS_I2C_SOFT_SLAVE_3
2056 for defining speed and slave address 2061 for defining speed and slave address
2057 - activate fourth bus with I2C_SOFT_DECLARATIONS4 define 2062 - activate fourth bus with I2C_SOFT_DECLARATIONS4 define
2058 CONFIG_SYS_I2C_SOFT_SPEED_4 and CONFIG_SYS_I2C_SOFT_SLAVE_4 2063 CONFIG_SYS_I2C_SOFT_SPEED_4 and CONFIG_SYS_I2C_SOFT_SLAVE_4
2059 for defining speed and slave address 2064 for defining speed and slave address
2060 2065
2061 - drivers/i2c/fsl_i2c.c: 2066 - drivers/i2c/fsl_i2c.c:
2062 - activate i2c driver with CONFIG_SYS_I2C_FSL 2067 - activate i2c driver with CONFIG_SYS_I2C_FSL
2063 define CONFIG_SYS_FSL_I2C_OFFSET for setting the register 2068 define CONFIG_SYS_FSL_I2C_OFFSET for setting the register
2064 offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and 2069 offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and
2065 CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first 2070 CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first
2066 bus. 2071 bus.
2067 - If your board supports a second fsl i2c bus, define 2072 - If your board supports a second fsl i2c bus, define
2068 CONFIG_SYS_FSL_I2C2_OFFSET for the register offset 2073 CONFIG_SYS_FSL_I2C2_OFFSET for the register offset
2069 CONFIG_SYS_FSL_I2C2_SPEED for the speed and 2074 CONFIG_SYS_FSL_I2C2_SPEED for the speed and
2070 CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the 2075 CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the
2071 second bus. 2076 second bus.
2072 2077
2073 - drivers/i2c/tegra_i2c.c: 2078 - drivers/i2c/tegra_i2c.c:
2074 - activate this driver with CONFIG_SYS_I2C_TEGRA 2079 - activate this driver with CONFIG_SYS_I2C_TEGRA
2075 - This driver adds 4 i2c buses with a fix speed from 2080 - This driver adds 4 i2c buses with a fix speed from
2076 100000 and the slave addr 0! 2081 100000 and the slave addr 0!
2077 2082
2078 - drivers/i2c/ppc4xx_i2c.c 2083 - drivers/i2c/ppc4xx_i2c.c
2079 - activate this driver with CONFIG_SYS_I2C_PPC4XX 2084 - activate this driver with CONFIG_SYS_I2C_PPC4XX
2080 - CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0 2085 - CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0
2081 - CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1 2086 - CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1
2082 2087
2083 - drivers/i2c/i2c_mxc.c 2088 - drivers/i2c/i2c_mxc.c
2084 - activate this driver with CONFIG_SYS_I2C_MXC 2089 - activate this driver with CONFIG_SYS_I2C_MXC
2085 - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED 2090 - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
2086 - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE 2091 - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
2087 - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED 2092 - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
2088 - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE 2093 - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
2089 - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED 2094 - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
2090 - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE 2095 - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
2091 If thoses defines are not set, default value is 100000 2096 If thoses defines are not set, default value is 100000
2092 for speed, and 0 for slave. 2097 for speed, and 0 for slave.
2093 2098
2094 - drivers/i2c/rcar_i2c.c: 2099 - drivers/i2c/rcar_i2c.c:
2095 - activate this driver with CONFIG_SYS_I2C_RCAR 2100 - activate this driver with CONFIG_SYS_I2C_RCAR
2096 - This driver adds 4 i2c buses 2101 - This driver adds 4 i2c buses
2097 2102
2098 - CONFIG_SYS_RCAR_I2C0_BASE for setting the register channel 0 2103 - CONFIG_SYS_RCAR_I2C0_BASE for setting the register channel 0
2099 - CONFIG_SYS_RCAR_I2C0_SPEED for for the speed channel 0 2104 - CONFIG_SYS_RCAR_I2C0_SPEED for for the speed channel 0
2100 - CONFIG_SYS_RCAR_I2C1_BASE for setting the register channel 1 2105 - CONFIG_SYS_RCAR_I2C1_BASE for setting the register channel 1
2101 - CONFIG_SYS_RCAR_I2C1_SPEED for for the speed channel 1 2106 - CONFIG_SYS_RCAR_I2C1_SPEED for for the speed channel 1
2102 - CONFIG_SYS_RCAR_I2C2_BASE for setting the register channel 2 2107 - CONFIG_SYS_RCAR_I2C2_BASE for setting the register channel 2
2103 - CONFIG_SYS_RCAR_I2C2_SPEED for for the speed channel 2 2108 - CONFIG_SYS_RCAR_I2C2_SPEED for for the speed channel 2
2104 - CONFIG_SYS_RCAR_I2C3_BASE for setting the register channel 3 2109 - CONFIG_SYS_RCAR_I2C3_BASE for setting the register channel 3
2105 - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3 2110 - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
2106 - CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses 2111 - CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
2107 2112
2108 - drivers/i2c/sh_i2c.c: 2113 - drivers/i2c/sh_i2c.c:
2109 - activate this driver with CONFIG_SYS_I2C_SH 2114 - activate this driver with CONFIG_SYS_I2C_SH
2110 - This driver adds from 2 to 5 i2c buses 2115 - This driver adds from 2 to 5 i2c buses
2111 2116
2112 - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0 2117 - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0
2113 - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0 2118 - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0
2114 - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1 2119 - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1
2115 - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1 2120 - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1
2116 - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2 2121 - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2
2117 - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2 2122 - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2
2118 - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3 2123 - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3
2119 - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3 2124 - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
2120 - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4 2125 - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
2121 - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4 2126 - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
2122 - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5 2127 - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5
2123 - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5 2128 - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
2124 - CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses 2129 - CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses
2125 2130
2126 - drivers/i2c/omap24xx_i2c.c 2131 - drivers/i2c/omap24xx_i2c.c
2127 - activate this driver with CONFIG_SYS_I2C_OMAP24XX 2132 - activate this driver with CONFIG_SYS_I2C_OMAP24XX
2128 - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0 2133 - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0
2129 - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0 2134 - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0
2130 - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1 2135 - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1
2131 - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1 2136 - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1
2132 - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2 2137 - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2
2133 - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2 2138 - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2
2134 - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3 2139 - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3
2135 - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3 2140 - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3
2136 - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4 2141 - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
2137 - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4 2142 - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4
2138 2143
2139 - drivers/i2c/zynq_i2c.c 2144 - drivers/i2c/zynq_i2c.c
2140 - activate this driver with CONFIG_SYS_I2C_ZYNQ 2145 - activate this driver with CONFIG_SYS_I2C_ZYNQ
2141 - set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting 2146 - set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting
2142 - set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr 2147 - set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr
2143 2148
2144 - drivers/i2c/s3c24x0_i2c.c: 2149 - drivers/i2c/s3c24x0_i2c.c:
2145 - activate this driver with CONFIG_SYS_I2C_S3C24X0 2150 - activate this driver with CONFIG_SYS_I2C_S3C24X0
2146 - This driver adds i2c buses (11 for Exynos5250, Exynos5420 2151 - This driver adds i2c buses (11 for Exynos5250, Exynos5420
2147 9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung) 2152 9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
2148 with a fix speed from 100000 and the slave addr 0! 2153 with a fix speed from 100000 and the slave addr 0!
2149 2154
2150 additional defines: 2155 additional defines:
2151 2156
2152 CONFIG_SYS_NUM_I2C_BUSES 2157 CONFIG_SYS_NUM_I2C_BUSES
2153 Hold the number of i2c busses you want to use. If you 2158 Hold the number of i2c busses you want to use. If you
2154 don't use/have i2c muxes on your i2c bus, this 2159 don't use/have i2c muxes on your i2c bus, this
2155 is equal to CONFIG_SYS_NUM_I2C_ADAPTERS, and you can 2160 is equal to CONFIG_SYS_NUM_I2C_ADAPTERS, and you can
2156 omit this define. 2161 omit this define.
2157 2162
2158 CONFIG_SYS_I2C_DIRECT_BUS 2163 CONFIG_SYS_I2C_DIRECT_BUS
2159 define this, if you don't use i2c muxes on your hardware. 2164 define this, if you don't use i2c muxes on your hardware.
2160 if CONFIG_SYS_I2C_MAX_HOPS is not defined or == 0 you can 2165 if CONFIG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
2161 omit this define. 2166 omit this define.
2162 2167
2163 CONFIG_SYS_I2C_MAX_HOPS 2168 CONFIG_SYS_I2C_MAX_HOPS
2164 define how many muxes are maximal consecutively connected 2169 define how many muxes are maximal consecutively connected
2165 on one i2c bus. If you not use i2c muxes, omit this 2170 on one i2c bus. If you not use i2c muxes, omit this
2166 define. 2171 define.
2167 2172
2168 CONFIG_SYS_I2C_BUSES 2173 CONFIG_SYS_I2C_BUSES
2169 hold a list of busses you want to use, only used if 2174 hold a list of busses you want to use, only used if
2170 CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example 2175 CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example
2171 a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and 2176 a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and
2172 CONFIG_SYS_NUM_I2C_BUSES = 9: 2177 CONFIG_SYS_NUM_I2C_BUSES = 9:
2173 2178
2174 CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \ 2179 CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \
2175 {0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \ 2180 {0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \
2176 {0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \ 2181 {0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \
2177 {0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \ 2182 {0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \
2178 {0, {{I2C_MUX_PCA9547, 0x70, 4}}}, \ 2183 {0, {{I2C_MUX_PCA9547, 0x70, 4}}}, \
2179 {0, {{I2C_MUX_PCA9547, 0x70, 5}}}, \ 2184 {0, {{I2C_MUX_PCA9547, 0x70, 5}}}, \
2180 {1, {I2C_NULL_HOP}}, \ 2185 {1, {I2C_NULL_HOP}}, \
2181 {1, {{I2C_MUX_PCA9544, 0x72, 1}}}, \ 2186 {1, {{I2C_MUX_PCA9544, 0x72, 1}}}, \
2182 {1, {{I2C_MUX_PCA9544, 0x72, 2}}}, \ 2187 {1, {{I2C_MUX_PCA9544, 0x72, 2}}}, \
2183 } 2188 }
2184 2189
2185 which defines 2190 which defines
2186 bus 0 on adapter 0 without a mux 2191 bus 0 on adapter 0 without a mux
2187 bus 1 on adapter 0 with a PCA9547 on address 0x70 port 1 2192 bus 1 on adapter 0 with a PCA9547 on address 0x70 port 1
2188 bus 2 on adapter 0 with a PCA9547 on address 0x70 port 2 2193 bus 2 on adapter 0 with a PCA9547 on address 0x70 port 2
2189 bus 3 on adapter 0 with a PCA9547 on address 0x70 port 3 2194 bus 3 on adapter 0 with a PCA9547 on address 0x70 port 3
2190 bus 4 on adapter 0 with a PCA9547 on address 0x70 port 4 2195 bus 4 on adapter 0 with a PCA9547 on address 0x70 port 4
2191 bus 5 on adapter 0 with a PCA9547 on address 0x70 port 5 2196 bus 5 on adapter 0 with a PCA9547 on address 0x70 port 5
2192 bus 6 on adapter 1 without a mux 2197 bus 6 on adapter 1 without a mux
2193 bus 7 on adapter 1 with a PCA9544 on address 0x72 port 1 2198 bus 7 on adapter 1 with a PCA9544 on address 0x72 port 1
2194 bus 8 on adapter 1 with a PCA9544 on address 0x72 port 2 2199 bus 8 on adapter 1 with a PCA9544 on address 0x72 port 2
2195 2200
2196 If you do not have i2c muxes on your board, omit this define. 2201 If you do not have i2c muxes on your board, omit this define.
2197 2202
2198 - Legacy I2C Support: CONFIG_HARD_I2C 2203 - Legacy I2C Support: CONFIG_HARD_I2C
2199 2204
2200 NOTE: It is intended to move drivers to CONFIG_SYS_I2C which 2205 NOTE: It is intended to move drivers to CONFIG_SYS_I2C which
2201 provides the following compelling advantages: 2206 provides the following compelling advantages:
2202 2207
2203 - more than one i2c adapter is usable 2208 - more than one i2c adapter is usable
2204 - approved multibus support 2209 - approved multibus support
2205 - better i2c mux support 2210 - better i2c mux support
2206 2211
2207 ** Please consider updating your I2C driver now. ** 2212 ** Please consider updating your I2C driver now. **
2208 2213
2209 These enable legacy I2C serial bus commands. Defining 2214 These enable legacy I2C serial bus commands. Defining
2210 CONFIG_HARD_I2C will include the appropriate I2C driver 2215 CONFIG_HARD_I2C will include the appropriate I2C driver
2211 for the selected CPU. 2216 for the selected CPU.
2212 2217
2213 This will allow you to use i2c commands at the u-boot 2218 This will allow you to use i2c commands at the u-boot
2214 command line (as long as you set CONFIG_CMD_I2C in 2219 command line (as long as you set CONFIG_CMD_I2C in
2215 CONFIG_COMMANDS) and communicate with i2c based realtime 2220 CONFIG_COMMANDS) and communicate with i2c based realtime
2216 clock chips. See common/cmd_i2c.c for a description of the 2221 clock chips. See common/cmd_i2c.c for a description of the
2217 command line interface. 2222 command line interface.
2218 2223
2219 CONFIG_HARD_I2C selects a hardware I2C controller. 2224 CONFIG_HARD_I2C selects a hardware I2C controller.
2220 2225
2221 There are several other quantities that must also be 2226 There are several other quantities that must also be
2222 defined when you define CONFIG_HARD_I2C. 2227 defined when you define CONFIG_HARD_I2C.
2223 2228
2224 In both cases you will need to define CONFIG_SYS_I2C_SPEED 2229 In both cases you will need to define CONFIG_SYS_I2C_SPEED
2225 to be the frequency (in Hz) at which you wish your i2c bus 2230 to be the frequency (in Hz) at which you wish your i2c bus
2226 to run and CONFIG_SYS_I2C_SLAVE to be the address of this node (ie 2231 to run and CONFIG_SYS_I2C_SLAVE to be the address of this node (ie
2227 the CPU's i2c node address). 2232 the CPU's i2c node address).
2228 2233
2229 Now, the u-boot i2c code for the mpc8xx 2234 Now, the u-boot i2c code for the mpc8xx
2230 (arch/powerpc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node 2235 (arch/powerpc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node
2231 and so its address should therefore be cleared to 0 (See, 2236 and so its address should therefore be cleared to 0 (See,
2232 eg, MPC823e User's Manual p.16-473). So, set 2237 eg, MPC823e User's Manual p.16-473). So, set
2233 CONFIG_SYS_I2C_SLAVE to 0. 2238 CONFIG_SYS_I2C_SLAVE to 0.
2234 2239
2235 CONFIG_SYS_I2C_INIT_MPC5XXX 2240 CONFIG_SYS_I2C_INIT_MPC5XXX
2236 2241
2237 When a board is reset during an i2c bus transfer 2242 When a board is reset during an i2c bus transfer
2238 chips might think that the current transfer is still 2243 chips might think that the current transfer is still
2239 in progress. Reset the slave devices by sending start 2244 in progress. Reset the slave devices by sending start
2240 commands until the slave device responds. 2245 commands until the slave device responds.
2241 2246
2242 That's all that's required for CONFIG_HARD_I2C. 2247 That's all that's required for CONFIG_HARD_I2C.
2243 2248
2244 If you use the software i2c interface (CONFIG_SYS_I2C_SOFT) 2249 If you use the software i2c interface (CONFIG_SYS_I2C_SOFT)
2245 then the following macros need to be defined (examples are 2250 then the following macros need to be defined (examples are
2246 from include/configs/lwmon.h): 2251 from include/configs/lwmon.h):
2247 2252
2248 I2C_INIT 2253 I2C_INIT
2249 2254
2250 (Optional). Any commands necessary to enable the I2C 2255 (Optional). Any commands necessary to enable the I2C
2251 controller or configure ports. 2256 controller or configure ports.
2252 2257
2253 eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) 2258 eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
2254 2259
2255 I2C_PORT 2260 I2C_PORT
2256 2261
2257 (Only for MPC8260 CPU). The I/O port to use (the code 2262 (Only for MPC8260 CPU). The I/O port to use (the code
2258 assumes both bits are on the same port). Valid values 2263 assumes both bits are on the same port). Valid values
2259 are 0..3 for ports A..D. 2264 are 0..3 for ports A..D.
2260 2265
2261 I2C_ACTIVE 2266 I2C_ACTIVE
2262 2267
2263 The code necessary to make the I2C data line active 2268 The code necessary to make the I2C data line active
2264 (driven). If the data line is open collector, this 2269 (driven). If the data line is open collector, this
2265 define can be null. 2270 define can be null.
2266 2271
2267 eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) 2272 eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
2268 2273
2269 I2C_TRISTATE 2274 I2C_TRISTATE
2270 2275
2271 The code necessary to make the I2C data line tri-stated 2276 The code necessary to make the I2C data line tri-stated
2272 (inactive). If the data line is open collector, this 2277 (inactive). If the data line is open collector, this
2273 define can be null. 2278 define can be null.
2274 2279
2275 eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) 2280 eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
2276 2281
2277 I2C_READ 2282 I2C_READ
2278 2283
2279 Code that returns true if the I2C data line is high, 2284 Code that returns true if the I2C data line is high,
2280 false if it is low. 2285 false if it is low.
2281 2286
2282 eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) 2287 eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
2283 2288
2284 I2C_SDA(bit) 2289 I2C_SDA(bit)
2285 2290
2286 If <bit> is true, sets the I2C data line high. If it 2291 If <bit> is true, sets the I2C data line high. If it
2287 is false, it clears it (low). 2292 is false, it clears it (low).
2288 2293
2289 eg: #define I2C_SDA(bit) \ 2294 eg: #define I2C_SDA(bit) \
2290 if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ 2295 if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
2291 else immr->im_cpm.cp_pbdat &= ~PB_SDA 2296 else immr->im_cpm.cp_pbdat &= ~PB_SDA
2292 2297
2293 I2C_SCL(bit) 2298 I2C_SCL(bit)
2294 2299
2295 If <bit> is true, sets the I2C clock line high. If it 2300 If <bit> is true, sets the I2C clock line high. If it
2296 is false, it clears it (low). 2301 is false, it clears it (low).
2297 2302
2298 eg: #define I2C_SCL(bit) \ 2303 eg: #define I2C_SCL(bit) \
2299 if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ 2304 if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
2300 else immr->im_cpm.cp_pbdat &= ~PB_SCL 2305 else immr->im_cpm.cp_pbdat &= ~PB_SCL
2301 2306
2302 I2C_DELAY 2307 I2C_DELAY
2303 2308
2304 This delay is invoked four times per clock cycle so this 2309 This delay is invoked four times per clock cycle so this
2305 controls the rate of data transfer. The data rate thus 2310 controls the rate of data transfer. The data rate thus
2306 is 1 / (I2C_DELAY * 4). Often defined to be something 2311 is 1 / (I2C_DELAY * 4). Often defined to be something
2307 like: 2312 like:
2308 2313
2309 #define I2C_DELAY udelay(2) 2314 #define I2C_DELAY udelay(2)
2310 2315
2311 CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA 2316 CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA
2312 2317
2313 If your arch supports the generic GPIO framework (asm/gpio.h), 2318 If your arch supports the generic GPIO framework (asm/gpio.h),
2314 then you may alternatively define the two GPIOs that are to be 2319 then you may alternatively define the two GPIOs that are to be
2315 used as SCL / SDA. Any of the previous I2C_xxx macros will 2320 used as SCL / SDA. Any of the previous I2C_xxx macros will
2316 have GPIO-based defaults assigned to them as appropriate. 2321 have GPIO-based defaults assigned to them as appropriate.
2317 2322
2318 You should define these to the GPIO value as given directly to 2323 You should define these to the GPIO value as given directly to
2319 the generic GPIO functions. 2324 the generic GPIO functions.
2320 2325
2321 CONFIG_SYS_I2C_INIT_BOARD 2326 CONFIG_SYS_I2C_INIT_BOARD
2322 2327
2323 When a board is reset during an i2c bus transfer 2328 When a board is reset during an i2c bus transfer
2324 chips might think that the current transfer is still 2329 chips might think that the current transfer is still
2325 in progress. On some boards it is possible to access 2330 in progress. On some boards it is possible to access
2326 the i2c SCLK line directly, either by using the 2331 the i2c SCLK line directly, either by using the
2327 processor pin as a GPIO or by having a second pin 2332 processor pin as a GPIO or by having a second pin
2328 connected to the bus. If this option is defined a 2333 connected to the bus. If this option is defined a
2329 custom i2c_init_board() routine in boards/xxx/board.c 2334 custom i2c_init_board() routine in boards/xxx/board.c
2330 is run early in the boot sequence. 2335 is run early in the boot sequence.
2331 2336
2332 CONFIG_SYS_I2C_BOARD_LATE_INIT 2337 CONFIG_SYS_I2C_BOARD_LATE_INIT
2333 2338
2334 An alternative to CONFIG_SYS_I2C_INIT_BOARD. If this option is 2339 An alternative to CONFIG_SYS_I2C_INIT_BOARD. If this option is
2335 defined a custom i2c_board_late_init() routine in 2340 defined a custom i2c_board_late_init() routine in
2336 boards/xxx/board.c is run AFTER the operations in i2c_init() 2341 boards/xxx/board.c is run AFTER the operations in i2c_init()
2337 is completed. This callpoint can be used to unreset i2c bus 2342 is completed. This callpoint can be used to unreset i2c bus
2338 using CPU i2c controller register accesses for CPUs whose i2c 2343 using CPU i2c controller register accesses for CPUs whose i2c
2339 controller provide such a method. It is called at the end of 2344 controller provide such a method. It is called at the end of
2340 i2c_init() to allow i2c_init operations to setup the i2c bus 2345 i2c_init() to allow i2c_init operations to setup the i2c bus
2341 controller on the CPU (e.g. setting bus speed & slave address). 2346 controller on the CPU (e.g. setting bus speed & slave address).
2342 2347
2343 CONFIG_I2CFAST (PPC405GP|PPC405EP only) 2348 CONFIG_I2CFAST (PPC405GP|PPC405EP only)
2344 2349
2345 This option enables configuration of bi_iic_fast[] flags 2350 This option enables configuration of bi_iic_fast[] flags
2346 in u-boot bd_info structure based on u-boot environment 2351 in u-boot bd_info structure based on u-boot environment
2347 variable "i2cfast". (see also i2cfast) 2352 variable "i2cfast". (see also i2cfast)
2348 2353
2349 CONFIG_I2C_MULTI_BUS 2354 CONFIG_I2C_MULTI_BUS
2350 2355
2351 This option allows the use of multiple I2C buses, each of which 2356 This option allows the use of multiple I2C buses, each of which
2352 must have a controller. At any point in time, only one bus is 2357 must have a controller. At any point in time, only one bus is
2353 active. To switch to a different bus, use the 'i2c dev' command. 2358 active. To switch to a different bus, use the 'i2c dev' command.
2354 Note that bus numbering is zero-based. 2359 Note that bus numbering is zero-based.
2355 2360
2356 CONFIG_SYS_I2C_NOPROBES 2361 CONFIG_SYS_I2C_NOPROBES
2357 2362
2358 This option specifies a list of I2C devices that will be skipped 2363 This option specifies a list of I2C devices that will be skipped
2359 when the 'i2c probe' command is issued. If CONFIG_I2C_MULTI_BUS 2364 when the 'i2c probe' command is issued. If CONFIG_I2C_MULTI_BUS
2360 is set, specify a list of bus-device pairs. Otherwise, specify 2365 is set, specify a list of bus-device pairs. Otherwise, specify
2361 a 1D array of device addresses 2366 a 1D array of device addresses
2362 2367
2363 e.g. 2368 e.g.
2364 #undef CONFIG_I2C_MULTI_BUS 2369 #undef CONFIG_I2C_MULTI_BUS
2365 #define CONFIG_SYS_I2C_NOPROBES {0x50,0x68} 2370 #define CONFIG_SYS_I2C_NOPROBES {0x50,0x68}
2366 2371
2367 will skip addresses 0x50 and 0x68 on a board with one I2C bus 2372 will skip addresses 0x50 and 0x68 on a board with one I2C bus
2368 2373
2369 #define CONFIG_I2C_MULTI_BUS 2374 #define CONFIG_I2C_MULTI_BUS
2370 #define CONFIG_SYS_I2C_MULTI_NOPROBES {{0,0x50},{0,0x68},{1,0x54}} 2375 #define CONFIG_SYS_I2C_MULTI_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
2371 2376
2372 will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1 2377 will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
2373 2378
2374 CONFIG_SYS_SPD_BUS_NUM 2379 CONFIG_SYS_SPD_BUS_NUM
2375 2380
2376 If defined, then this indicates the I2C bus number for DDR SPD. 2381 If defined, then this indicates the I2C bus number for DDR SPD.
2377 If not defined, then U-Boot assumes that SPD is on I2C bus 0. 2382 If not defined, then U-Boot assumes that SPD is on I2C bus 0.
2378 2383
2379 CONFIG_SYS_RTC_BUS_NUM 2384 CONFIG_SYS_RTC_BUS_NUM
2380 2385
2381 If defined, then this indicates the I2C bus number for the RTC. 2386 If defined, then this indicates the I2C bus number for the RTC.
2382 If not defined, then U-Boot assumes that RTC is on I2C bus 0. 2387 If not defined, then U-Boot assumes that RTC is on I2C bus 0.
2383 2388
2384 CONFIG_SYS_DTT_BUS_NUM 2389 CONFIG_SYS_DTT_BUS_NUM
2385 2390
2386 If defined, then this indicates the I2C bus number for the DTT. 2391 If defined, then this indicates the I2C bus number for the DTT.
2387 If not defined, then U-Boot assumes that DTT is on I2C bus 0. 2392 If not defined, then U-Boot assumes that DTT is on I2C bus 0.
2388 2393
2389 CONFIG_SYS_I2C_DTT_ADDR: 2394 CONFIG_SYS_I2C_DTT_ADDR:
2390 2395
2391 If defined, specifies the I2C address of the DTT device. 2396 If defined, specifies the I2C address of the DTT device.
2392 If not defined, then U-Boot uses predefined value for 2397 If not defined, then U-Boot uses predefined value for
2393 specified DTT device. 2398 specified DTT device.
2394 2399
2395 CONFIG_SOFT_I2C_READ_REPEATED_START 2400 CONFIG_SOFT_I2C_READ_REPEATED_START
2396 2401
2397 defining this will force the i2c_read() function in 2402 defining this will force the i2c_read() function in
2398 the soft_i2c driver to perform an I2C repeated start 2403 the soft_i2c driver to perform an I2C repeated start
2399 between writing the address pointer and reading the 2404 between writing the address pointer and reading the
2400 data. If this define is omitted the default behaviour 2405 data. If this define is omitted the default behaviour
2401 of doing a stop-start sequence will be used. Most I2C 2406 of doing a stop-start sequence will be used. Most I2C
2402 devices can use either method, but some require one or 2407 devices can use either method, but some require one or
2403 the other. 2408 the other.
2404 2409
2405 - SPI Support: CONFIG_SPI 2410 - SPI Support: CONFIG_SPI
2406 2411
2407 Enables SPI driver (so far only tested with 2412 Enables SPI driver (so far only tested with
2408 SPI EEPROM, also an instance works with Crystal A/D and 2413 SPI EEPROM, also an instance works with Crystal A/D and
2409 D/As on the SACSng board) 2414 D/As on the SACSng board)
2410 2415
2411 CONFIG_SH_SPI 2416 CONFIG_SH_SPI
2412 2417
2413 Enables the driver for SPI controller on SuperH. Currently 2418 Enables the driver for SPI controller on SuperH. Currently
2414 only SH7757 is supported. 2419 only SH7757 is supported.
2415 2420
2416 CONFIG_SPI_X 2421 CONFIG_SPI_X
2417 2422
2418 Enables extended (16-bit) SPI EEPROM addressing. 2423 Enables extended (16-bit) SPI EEPROM addressing.
2419 (symmetrical to CONFIG_I2C_X) 2424 (symmetrical to CONFIG_I2C_X)
2420 2425
2421 CONFIG_SOFT_SPI 2426 CONFIG_SOFT_SPI
2422 2427
2423 Enables a software (bit-bang) SPI driver rather than 2428 Enables a software (bit-bang) SPI driver rather than
2424 using hardware support. This is a general purpose 2429 using hardware support. This is a general purpose
2425 driver that only requires three general I/O port pins 2430 driver that only requires three general I/O port pins
2426 (two outputs, one input) to function. If this is 2431 (two outputs, one input) to function. If this is
2427 defined, the board configuration must define several 2432 defined, the board configuration must define several
2428 SPI configuration items (port pins to use, etc). For 2433 SPI configuration items (port pins to use, etc). For
2429 an example, see include/configs/sacsng.h. 2434 an example, see include/configs/sacsng.h.
2430 2435
2431 CONFIG_HARD_SPI 2436 CONFIG_HARD_SPI
2432 2437
2433 Enables a hardware SPI driver for general-purpose reads 2438 Enables a hardware SPI driver for general-purpose reads
2434 and writes. As with CONFIG_SOFT_SPI, the board configuration 2439 and writes. As with CONFIG_SOFT_SPI, the board configuration
2435 must define a list of chip-select function pointers. 2440 must define a list of chip-select function pointers.
2436 Currently supported on some MPC8xxx processors. For an 2441 Currently supported on some MPC8xxx processors. For an
2437 example, see include/configs/mpc8349emds.h. 2442 example, see include/configs/mpc8349emds.h.
2438 2443
2439 CONFIG_MXC_SPI 2444 CONFIG_MXC_SPI
2440 2445
2441 Enables the driver for the SPI controllers on i.MX and MXC 2446 Enables the driver for the SPI controllers on i.MX and MXC
2442 SoCs. Currently i.MX31/35/51 are supported. 2447 SoCs. Currently i.MX31/35/51 are supported.
2443 2448
2444 - FPGA Support: CONFIG_FPGA 2449 - FPGA Support: CONFIG_FPGA
2445 2450
2446 Enables FPGA subsystem. 2451 Enables FPGA subsystem.
2447 2452
2448 CONFIG_FPGA_<vendor> 2453 CONFIG_FPGA_<vendor>
2449 2454
2450 Enables support for specific chip vendors. 2455 Enables support for specific chip vendors.
2451 (ALTERA, XILINX) 2456 (ALTERA, XILINX)
2452 2457
2453 CONFIG_FPGA_<family> 2458 CONFIG_FPGA_<family>
2454 2459
2455 Enables support for FPGA family. 2460 Enables support for FPGA family.
2456 (SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX) 2461 (SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
2457 2462
2458 CONFIG_FPGA_COUNT 2463 CONFIG_FPGA_COUNT
2459 2464
2460 Specify the number of FPGA devices to support. 2465 Specify the number of FPGA devices to support.
2461 2466
2462 CONFIG_SYS_FPGA_PROG_FEEDBACK 2467 CONFIG_SYS_FPGA_PROG_FEEDBACK
2463 2468
2464 Enable printing of hash marks during FPGA configuration. 2469 Enable printing of hash marks during FPGA configuration.
2465 2470
2466 CONFIG_SYS_FPGA_CHECK_BUSY 2471 CONFIG_SYS_FPGA_CHECK_BUSY
2467 2472
2468 Enable checks on FPGA configuration interface busy 2473 Enable checks on FPGA configuration interface busy
2469 status by the configuration function. This option 2474 status by the configuration function. This option
2470 will require a board or device specific function to 2475 will require a board or device specific function to
2471 be written. 2476 be written.
2472 2477
2473 CONFIG_FPGA_DELAY 2478 CONFIG_FPGA_DELAY
2474 2479
2475 If defined, a function that provides delays in the FPGA 2480 If defined, a function that provides delays in the FPGA
2476 configuration driver. 2481 configuration driver.
2477 2482
2478 CONFIG_SYS_FPGA_CHECK_CTRLC 2483 CONFIG_SYS_FPGA_CHECK_CTRLC
2479 Allow Control-C to interrupt FPGA configuration 2484 Allow Control-C to interrupt FPGA configuration
2480 2485
2481 CONFIG_SYS_FPGA_CHECK_ERROR 2486 CONFIG_SYS_FPGA_CHECK_ERROR
2482 2487
2483 Check for configuration errors during FPGA bitfile 2488 Check for configuration errors during FPGA bitfile
2484 loading. For example, abort during Virtex II 2489 loading. For example, abort during Virtex II
2485 configuration if the INIT_B line goes low (which 2490 configuration if the INIT_B line goes low (which
2486 indicated a CRC error). 2491 indicated a CRC error).
2487 2492
2488 CONFIG_SYS_FPGA_WAIT_INIT 2493 CONFIG_SYS_FPGA_WAIT_INIT
2489 2494
2490 Maximum time to wait for the INIT_B line to deassert 2495 Maximum time to wait for the INIT_B line to deassert
2491 after PROB_B has been deasserted during a Virtex II 2496 after PROB_B has been deasserted during a Virtex II
2492 FPGA configuration sequence. The default time is 500 2497 FPGA configuration sequence. The default time is 500
2493 ms. 2498 ms.
2494 2499
2495 CONFIG_SYS_FPGA_WAIT_BUSY 2500 CONFIG_SYS_FPGA_WAIT_BUSY
2496 2501
2497 Maximum time to wait for BUSY to deassert during 2502 Maximum time to wait for BUSY to deassert during
2498 Virtex II FPGA configuration. The default is 5 ms. 2503 Virtex II FPGA configuration. The default is 5 ms.
2499 2504
2500 CONFIG_SYS_FPGA_WAIT_CONFIG 2505 CONFIG_SYS_FPGA_WAIT_CONFIG
2501 2506
2502 Time to wait after FPGA configuration. The default is 2507 Time to wait after FPGA configuration. The default is
2503 200 ms. 2508 200 ms.
2504 2509
2505 - Configuration Management: 2510 - Configuration Management:
2506 CONFIG_IDENT_STRING 2511 CONFIG_IDENT_STRING
2507 2512
2508 If defined, this string will be added to the U-Boot 2513 If defined, this string will be added to the U-Boot
2509 version information (U_BOOT_VERSION) 2514 version information (U_BOOT_VERSION)
2510 2515
2511 - Vendor Parameter Protection: 2516 - Vendor Parameter Protection:
2512 2517
2513 U-Boot considers the values of the environment 2518 U-Boot considers the values of the environment
2514 variables "serial#" (Board Serial Number) and 2519 variables "serial#" (Board Serial Number) and
2515 "ethaddr" (Ethernet Address) to be parameters that 2520 "ethaddr" (Ethernet Address) to be parameters that
2516 are set once by the board vendor / manufacturer, and 2521 are set once by the board vendor / manufacturer, and
2517 protects these variables from casual modification by 2522 protects these variables from casual modification by
2518 the user. Once set, these variables are read-only, 2523 the user. Once set, these variables are read-only,
2519 and write or delete attempts are rejected. You can 2524 and write or delete attempts are rejected. You can
2520 change this behaviour: 2525 change this behaviour:
2521 2526
2522 If CONFIG_ENV_OVERWRITE is #defined in your config 2527 If CONFIG_ENV_OVERWRITE is #defined in your config
2523 file, the write protection for vendor parameters is 2528 file, the write protection for vendor parameters is
2524 completely disabled. Anybody can change or delete 2529 completely disabled. Anybody can change or delete
2525 these parameters. 2530 these parameters.
2526 2531
2527 Alternatively, if you #define _both_ CONFIG_ETHADDR 2532 Alternatively, if you #define _both_ CONFIG_ETHADDR
2528 _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default 2533 _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default
2529 Ethernet address is installed in the environment, 2534 Ethernet address is installed in the environment,
2530 which can be changed exactly ONCE by the user. [The 2535 which can be changed exactly ONCE by the user. [The
2531 serial# is unaffected by this, i. e. it remains 2536 serial# is unaffected by this, i. e. it remains
2532 read-only.] 2537 read-only.]
2533 2538
2534 The same can be accomplished in a more flexible way 2539 The same can be accomplished in a more flexible way
2535 for any variable by configuring the type of access 2540 for any variable by configuring the type of access
2536 to allow for those variables in the ".flags" variable 2541 to allow for those variables in the ".flags" variable
2537 or define CONFIG_ENV_FLAGS_LIST_STATIC. 2542 or define CONFIG_ENV_FLAGS_LIST_STATIC.
2538 2543
2539 - Protected RAM: 2544 - Protected RAM:
2540 CONFIG_PRAM 2545 CONFIG_PRAM
2541 2546
2542 Define this variable to enable the reservation of 2547 Define this variable to enable the reservation of
2543 "protected RAM", i. e. RAM which is not overwritten 2548 "protected RAM", i. e. RAM which is not overwritten
2544 by U-Boot. Define CONFIG_PRAM to hold the number of 2549 by U-Boot. Define CONFIG_PRAM to hold the number of
2545 kB you want to reserve for pRAM. You can overwrite 2550 kB you want to reserve for pRAM. You can overwrite
2546 this default value by defining an environment 2551 this default value by defining an environment
2547 variable "pram" to the number of kB you want to 2552 variable "pram" to the number of kB you want to
2548 reserve. Note that the board info structure will 2553 reserve. Note that the board info structure will
2549 still show the full amount of RAM. If pRAM is 2554 still show the full amount of RAM. If pRAM is
2550 reserved, a new environment variable "mem" will 2555 reserved, a new environment variable "mem" will
2551 automatically be defined to hold the amount of 2556 automatically be defined to hold the amount of
2552 remaining RAM in a form that can be passed as boot 2557 remaining RAM in a form that can be passed as boot
2553 argument to Linux, for instance like that: 2558 argument to Linux, for instance like that:
2554 2559
2555 setenv bootargs ... mem=\${mem} 2560 setenv bootargs ... mem=\${mem}
2556 saveenv 2561 saveenv
2557 2562
2558 This way you can tell Linux not to use this memory, 2563 This way you can tell Linux not to use this memory,
2559 either, which results in a memory region that will 2564 either, which results in a memory region that will
2560 not be affected by reboots. 2565 not be affected by reboots.
2561 2566
2562 *WARNING* If your board configuration uses automatic 2567 *WARNING* If your board configuration uses automatic
2563 detection of the RAM size, you must make sure that 2568 detection of the RAM size, you must make sure that
2564 this memory test is non-destructive. So far, the 2569 this memory test is non-destructive. So far, the
2565 following board configurations are known to be 2570 following board configurations are known to be
2566 "pRAM-clean": 2571 "pRAM-clean":
2567 2572
2568 IVMS8, IVML24, SPD8xx, TQM8xxL, 2573 IVMS8, IVML24, SPD8xx, TQM8xxL,
2569 HERMES, IP860, RPXlite, LWMON, 2574 HERMES, IP860, RPXlite, LWMON,
2570 FLAGADM, TQM8260 2575 FLAGADM, TQM8260
2571 2576
2572 - Access to physical memory region (> 4GB) 2577 - Access to physical memory region (> 4GB)
2573 Some basic support is provided for operations on memory not 2578 Some basic support is provided for operations on memory not
2574 normally accessible to U-Boot - e.g. some architectures 2579 normally accessible to U-Boot - e.g. some architectures
2575 support access to more than 4GB of memory on 32-bit 2580 support access to more than 4GB of memory on 32-bit
2576 machines using physical address extension or similar. 2581 machines using physical address extension or similar.
2577 Define CONFIG_PHYSMEM to access this basic support, which 2582 Define CONFIG_PHYSMEM to access this basic support, which
2578 currently only supports clearing the memory. 2583 currently only supports clearing the memory.
2579 2584
2580 - Error Recovery: 2585 - Error Recovery:
2581 CONFIG_PANIC_HANG 2586 CONFIG_PANIC_HANG
2582 2587
2583 Define this variable to stop the system in case of a 2588 Define this variable to stop the system in case of a
2584 fatal error, so that you have to reset it manually. 2589 fatal error, so that you have to reset it manually.
2585 This is probably NOT a good idea for an embedded 2590 This is probably NOT a good idea for an embedded
2586 system where you want the system to reboot 2591 system where you want the system to reboot
2587 automatically as fast as possible, but it may be 2592 automatically as fast as possible, but it may be
2588 useful during development since you can try to debug 2593 useful during development since you can try to debug
2589 the conditions that lead to the situation. 2594 the conditions that lead to the situation.
2590 2595
2591 CONFIG_NET_RETRY_COUNT 2596 CONFIG_NET_RETRY_COUNT
2592 2597
2593 This variable defines the number of retries for 2598 This variable defines the number of retries for
2594 network operations like ARP, RARP, TFTP, or BOOTP 2599 network operations like ARP, RARP, TFTP, or BOOTP
2595 before giving up the operation. If not defined, a 2600 before giving up the operation. If not defined, a
2596 default value of 5 is used. 2601 default value of 5 is used.
2597 2602
2598 CONFIG_ARP_TIMEOUT 2603 CONFIG_ARP_TIMEOUT
2599 2604
2600 Timeout waiting for an ARP reply in milliseconds. 2605 Timeout waiting for an ARP reply in milliseconds.
2601 2606
2602 CONFIG_NFS_TIMEOUT 2607 CONFIG_NFS_TIMEOUT
2603 2608
2604 Timeout in milliseconds used in NFS protocol. 2609 Timeout in milliseconds used in NFS protocol.
2605 If you encounter "ERROR: Cannot umount" in nfs command, 2610 If you encounter "ERROR: Cannot umount" in nfs command,
2606 try longer timeout such as 2611 try longer timeout such as
2607 #define CONFIG_NFS_TIMEOUT 10000UL 2612 #define CONFIG_NFS_TIMEOUT 10000UL
2608 2613
2609 - Command Interpreter: 2614 - Command Interpreter:
2610 CONFIG_AUTO_COMPLETE 2615 CONFIG_AUTO_COMPLETE
2611 2616
2612 Enable auto completion of commands using TAB. 2617 Enable auto completion of commands using TAB.
2613 2618
2614 Note that this feature has NOT been implemented yet 2619 Note that this feature has NOT been implemented yet
2615 for the "hush" shell. 2620 for the "hush" shell.
2616 2621
2617 2622
2618 CONFIG_SYS_HUSH_PARSER 2623 CONFIG_SYS_HUSH_PARSER
2619 2624
2620 Define this variable to enable the "hush" shell (from 2625 Define this variable to enable the "hush" shell (from
2621 Busybox) as command line interpreter, thus enabling 2626 Busybox) as command line interpreter, thus enabling
2622 powerful command line syntax like 2627 powerful command line syntax like
2623 if...then...else...fi conditionals or `&&' and '||' 2628 if...then...else...fi conditionals or `&&' and '||'
2624 constructs ("shell scripts"). 2629 constructs ("shell scripts").
2625 2630
2626 If undefined, you get the old, much simpler behaviour 2631 If undefined, you get the old, much simpler behaviour
2627 with a somewhat smaller memory footprint. 2632 with a somewhat smaller memory footprint.
2628 2633
2629 2634
2630 CONFIG_SYS_PROMPT_HUSH_PS2 2635 CONFIG_SYS_PROMPT_HUSH_PS2
2631 2636
2632 This defines the secondary prompt string, which is 2637 This defines the secondary prompt string, which is
2633 printed when the command interpreter needs more input 2638 printed when the command interpreter needs more input
2634 to complete a command. Usually "> ". 2639 to complete a command. Usually "> ".
2635 2640
2636 Note: 2641 Note:
2637 2642
2638 In the current implementation, the local variables 2643 In the current implementation, the local variables
2639 space and global environment variables space are 2644 space and global environment variables space are
2640 separated. Local variables are those you define by 2645 separated. Local variables are those you define by
2641 simply typing `name=value'. To access a local 2646 simply typing `name=value'. To access a local
2642 variable later on, you have write `$name' or 2647 variable later on, you have write `$name' or
2643 `${name}'; to execute the contents of a variable 2648 `${name}'; to execute the contents of a variable
2644 directly type `$name' at the command prompt. 2649 directly type `$name' at the command prompt.
2645 2650
2646 Global environment variables are those you use 2651 Global environment variables are those you use
2647 setenv/printenv to work with. To run a command stored 2652 setenv/printenv to work with. To run a command stored
2648 in such a variable, you need to use the run command, 2653 in such a variable, you need to use the run command,
2649 and you must not use the '$' sign to access them. 2654 and you must not use the '$' sign to access them.
2650 2655
2651 To store commands and special characters in a 2656 To store commands and special characters in a
2652 variable, please use double quotation marks 2657 variable, please use double quotation marks
2653 surrounding the whole text of the variable, instead 2658 surrounding the whole text of the variable, instead
2654 of the backslashes before semicolons and special 2659 of the backslashes before semicolons and special
2655 symbols. 2660 symbols.
2656 2661
2657 - Commandline Editing and History: 2662 - Commandline Editing and History:
2658 CONFIG_CMDLINE_EDITING 2663 CONFIG_CMDLINE_EDITING
2659 2664
2660 Enable editing and History functions for interactive 2665 Enable editing and History functions for interactive
2661 commandline input operations 2666 commandline input operations
2662 2667
2663 - Default Environment: 2668 - Default Environment:
2664 CONFIG_EXTRA_ENV_SETTINGS 2669 CONFIG_EXTRA_ENV_SETTINGS
2665 2670
2666 Define this to contain any number of null terminated 2671 Define this to contain any number of null terminated
2667 strings (variable = value pairs) that will be part of 2672 strings (variable = value pairs) that will be part of
2668 the default environment compiled into the boot image. 2673 the default environment compiled into the boot image.
2669 2674
2670 For example, place something like this in your 2675 For example, place something like this in your
2671 board's config file: 2676 board's config file:
2672 2677
2673 #define CONFIG_EXTRA_ENV_SETTINGS \ 2678 #define CONFIG_EXTRA_ENV_SETTINGS \
2674 "myvar1=value1\0" \ 2679 "myvar1=value1\0" \
2675 "myvar2=value2\0" 2680 "myvar2=value2\0"
2676 2681
2677 Warning: This method is based on knowledge about the 2682 Warning: This method is based on knowledge about the
2678 internal format how the environment is stored by the 2683 internal format how the environment is stored by the
2679 U-Boot code. This is NOT an official, exported 2684 U-Boot code. This is NOT an official, exported
2680 interface! Although it is unlikely that this format 2685 interface! Although it is unlikely that this format
2681 will change soon, there is no guarantee either. 2686 will change soon, there is no guarantee either.
2682 You better know what you are doing here. 2687 You better know what you are doing here.
2683 2688
2684 Note: overly (ab)use of the default environment is 2689 Note: overly (ab)use of the default environment is
2685 discouraged. Make sure to check other ways to preset 2690 discouraged. Make sure to check other ways to preset
2686 the environment like the "source" command or the 2691 the environment like the "source" command or the
2687 boot command first. 2692 boot command first.
2688 2693
2689 CONFIG_ENV_VARS_UBOOT_CONFIG 2694 CONFIG_ENV_VARS_UBOOT_CONFIG
2690 2695
2691 Define this in order to add variables describing the 2696 Define this in order to add variables describing the
2692 U-Boot build configuration to the default environment. 2697 U-Boot build configuration to the default environment.
2693 These will be named arch, cpu, board, vendor, and soc. 2698 These will be named arch, cpu, board, vendor, and soc.
2694 2699
2695 Enabling this option will cause the following to be defined: 2700 Enabling this option will cause the following to be defined:
2696 2701
2697 - CONFIG_SYS_ARCH 2702 - CONFIG_SYS_ARCH
2698 - CONFIG_SYS_CPU 2703 - CONFIG_SYS_CPU
2699 - CONFIG_SYS_BOARD 2704 - CONFIG_SYS_BOARD
2700 - CONFIG_SYS_VENDOR 2705 - CONFIG_SYS_VENDOR
2701 - CONFIG_SYS_SOC 2706 - CONFIG_SYS_SOC
2702 2707
2703 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 2708 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
2704 2709
2705 Define this in order to add variables describing certain 2710 Define this in order to add variables describing certain
2706 run-time determined information about the hardware to the 2711 run-time determined information about the hardware to the
2707 environment. These will be named board_name, board_rev. 2712 environment. These will be named board_name, board_rev.
2708 2713
2709 CONFIG_DELAY_ENVIRONMENT 2714 CONFIG_DELAY_ENVIRONMENT
2710 2715
2711 Normally the environment is loaded when the board is 2716 Normally the environment is loaded when the board is
2712 intialised so that it is available to U-Boot. This inhibits 2717 intialised so that it is available to U-Boot. This inhibits
2713 that so that the environment is not available until 2718 that so that the environment is not available until
2714 explicitly loaded later by U-Boot code. With CONFIG_OF_CONTROL 2719 explicitly loaded later by U-Boot code. With CONFIG_OF_CONTROL
2715 this is instead controlled by the value of 2720 this is instead controlled by the value of
2716 /config/load-environment. 2721 /config/load-environment.
2717 2722
2718 - DataFlash Support: 2723 - DataFlash Support:
2719 CONFIG_HAS_DATAFLASH 2724 CONFIG_HAS_DATAFLASH
2720 2725
2721 Defining this option enables DataFlash features and 2726 Defining this option enables DataFlash features and
2722 allows to read/write in Dataflash via the standard 2727 allows to read/write in Dataflash via the standard
2723 commands cp, md... 2728 commands cp, md...
2724 2729
2725 - Serial Flash support 2730 - Serial Flash support
2726 CONFIG_CMD_SF 2731 CONFIG_CMD_SF
2727 2732
2728 Defining this option enables SPI flash commands 2733 Defining this option enables SPI flash commands
2729 'sf probe/read/write/erase/update'. 2734 'sf probe/read/write/erase/update'.
2730 2735
2731 Usage requires an initial 'probe' to define the serial 2736 Usage requires an initial 'probe' to define the serial
2732 flash parameters, followed by read/write/erase/update 2737 flash parameters, followed by read/write/erase/update
2733 commands. 2738 commands.
2734 2739
2735 The following defaults may be provided by the platform 2740 The following defaults may be provided by the platform
2736 to handle the common case when only a single serial 2741 to handle the common case when only a single serial
2737 flash is present on the system. 2742 flash is present on the system.
2738 2743
2739 CONFIG_SF_DEFAULT_BUS Bus identifier 2744 CONFIG_SF_DEFAULT_BUS Bus identifier
2740 CONFIG_SF_DEFAULT_CS Chip-select 2745 CONFIG_SF_DEFAULT_CS Chip-select
2741 CONFIG_SF_DEFAULT_MODE (see include/spi.h) 2746 CONFIG_SF_DEFAULT_MODE (see include/spi.h)
2742 CONFIG_SF_DEFAULT_SPEED in Hz 2747 CONFIG_SF_DEFAULT_SPEED in Hz
2743 2748
2744 CONFIG_CMD_SF_TEST 2749 CONFIG_CMD_SF_TEST
2745 2750
2746 Define this option to include a destructive SPI flash 2751 Define this option to include a destructive SPI flash
2747 test ('sf test'). 2752 test ('sf test').
2748 2753
2749 CONFIG_SPI_FLASH_BAR Ban/Extended Addr Reg 2754 CONFIG_SPI_FLASH_BAR Ban/Extended Addr Reg
2750 2755
2751 Define this option to use the Bank addr/Extended addr 2756 Define this option to use the Bank addr/Extended addr
2752 support on SPI flashes which has size > 16Mbytes. 2757 support on SPI flashes which has size > 16Mbytes.
2753 2758
2754 - SystemACE Support: 2759 - SystemACE Support:
2755 CONFIG_SYSTEMACE 2760 CONFIG_SYSTEMACE
2756 2761
2757 Adding this option adds support for Xilinx SystemACE 2762 Adding this option adds support for Xilinx SystemACE
2758 chips attached via some sort of local bus. The address 2763 chips attached via some sort of local bus. The address
2759 of the chip must also be defined in the 2764 of the chip must also be defined in the
2760 CONFIG_SYS_SYSTEMACE_BASE macro. For example: 2765 CONFIG_SYS_SYSTEMACE_BASE macro. For example:
2761 2766
2762 #define CONFIG_SYSTEMACE 2767 #define CONFIG_SYSTEMACE
2763 #define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000 2768 #define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000
2764 2769
2765 When SystemACE support is added, the "ace" device type 2770 When SystemACE support is added, the "ace" device type
2766 becomes available to the fat commands, i.e. fatls. 2771 becomes available to the fat commands, i.e. fatls.
2767 2772
2768 - TFTP Fixed UDP Port: 2773 - TFTP Fixed UDP Port:
2769 CONFIG_TFTP_PORT 2774 CONFIG_TFTP_PORT
2770 2775
2771 If this is defined, the environment variable tftpsrcp 2776 If this is defined, the environment variable tftpsrcp
2772 is used to supply the TFTP UDP source port value. 2777 is used to supply the TFTP UDP source port value.
2773 If tftpsrcp isn't defined, the normal pseudo-random port 2778 If tftpsrcp isn't defined, the normal pseudo-random port
2774 number generator is used. 2779 number generator is used.
2775 2780
2776 Also, the environment variable tftpdstp is used to supply 2781 Also, the environment variable tftpdstp is used to supply
2777 the TFTP UDP destination port value. If tftpdstp isn't 2782 the TFTP UDP destination port value. If tftpdstp isn't
2778 defined, the normal port 69 is used. 2783 defined, the normal port 69 is used.
2779 2784
2780 The purpose for tftpsrcp is to allow a TFTP server to 2785 The purpose for tftpsrcp is to allow a TFTP server to
2781 blindly start the TFTP transfer using the pre-configured 2786 blindly start the TFTP transfer using the pre-configured
2782 target IP address and UDP port. This has the effect of 2787 target IP address and UDP port. This has the effect of
2783 "punching through" the (Windows XP) firewall, allowing 2788 "punching through" the (Windows XP) firewall, allowing
2784 the remainder of the TFTP transfer to proceed normally. 2789 the remainder of the TFTP transfer to proceed normally.
2785 A better solution is to properly configure the firewall, 2790 A better solution is to properly configure the firewall,
2786 but sometimes that is not allowed. 2791 but sometimes that is not allowed.
2787 2792
2788 - Hashing support: 2793 - Hashing support:
2789 CONFIG_CMD_HASH 2794 CONFIG_CMD_HASH
2790 2795
2791 This enables a generic 'hash' command which can produce 2796 This enables a generic 'hash' command which can produce
2792 hashes / digests from a few algorithms (e.g. SHA1, SHA256). 2797 hashes / digests from a few algorithms (e.g. SHA1, SHA256).
2793 2798
2794 CONFIG_HASH_VERIFY 2799 CONFIG_HASH_VERIFY
2795 2800
2796 Enable the hash verify command (hash -v). This adds to code 2801 Enable the hash verify command (hash -v). This adds to code
2797 size a little. 2802 size a little.
2798 2803
2799 CONFIG_SHA1 - support SHA1 hashing 2804 CONFIG_SHA1 - support SHA1 hashing
2800 CONFIG_SHA256 - support SHA256 hashing 2805 CONFIG_SHA256 - support SHA256 hashing
2801 2806
2802 Note: There is also a sha1sum command, which should perhaps 2807 Note: There is also a sha1sum command, which should perhaps
2803 be deprecated in favour of 'hash sha1'. 2808 be deprecated in favour of 'hash sha1'.
2804 2809
2805 - Freescale i.MX specific commands: 2810 - Freescale i.MX specific commands:
2806 CONFIG_CMD_HDMIDETECT 2811 CONFIG_CMD_HDMIDETECT
2807 This enables 'hdmidet' command which returns true if an 2812 This enables 'hdmidet' command which returns true if an
2808 HDMI monitor is detected. This command is i.MX 6 specific. 2813 HDMI monitor is detected. This command is i.MX 6 specific.
2809 2814
2810 CONFIG_CMD_BMODE 2815 CONFIG_CMD_BMODE
2811 This enables the 'bmode' (bootmode) command for forcing 2816 This enables the 'bmode' (bootmode) command for forcing
2812 a boot from specific media. 2817 a boot from specific media.
2813 2818
2814 This is useful for forcing the ROM's usb downloader to 2819 This is useful for forcing the ROM's usb downloader to
2815 activate upon a watchdog reset which is nice when iterating 2820 activate upon a watchdog reset which is nice when iterating
2816 on U-Boot. Using the reset button or running bmode normal 2821 on U-Boot. Using the reset button or running bmode normal
2817 will set it back to normal. This command currently 2822 will set it back to normal. This command currently
2818 supports i.MX53 and i.MX6. 2823 supports i.MX53 and i.MX6.
2819 2824
2820 - Signing support: 2825 - Signing support:
2821 CONFIG_RSA 2826 CONFIG_RSA
2822 2827
2823 This enables the RSA algorithm used for FIT image verification 2828 This enables the RSA algorithm used for FIT image verification
2824 in U-Boot. See doc/uImage/signature for more information. 2829 in U-Boot. See doc/uImage/signature for more information.
2825 2830
2826 The signing part is build into mkimage regardless of this 2831 The signing part is build into mkimage regardless of this
2827 option. 2832 option.
2828 2833
2829 2834
2830 - Show boot progress: 2835 - Show boot progress:
2831 CONFIG_SHOW_BOOT_PROGRESS 2836 CONFIG_SHOW_BOOT_PROGRESS
2832 2837
2833 Defining this option allows to add some board- 2838 Defining this option allows to add some board-
2834 specific code (calling a user-provided function 2839 specific code (calling a user-provided function
2835 "show_boot_progress(int)") that enables you to show 2840 "show_boot_progress(int)") that enables you to show
2836 the system's boot progress on some display (for 2841 the system's boot progress on some display (for
2837 example, some LED's) on your board. At the moment, 2842 example, some LED's) on your board. At the moment,
2838 the following checkpoints are implemented: 2843 the following checkpoints are implemented:
2839 2844
2840 - Detailed boot stage timing 2845 - Detailed boot stage timing
2841 CONFIG_BOOTSTAGE 2846 CONFIG_BOOTSTAGE
2842 Define this option to get detailed timing of each stage 2847 Define this option to get detailed timing of each stage
2843 of the boot process. 2848 of the boot process.
2844 2849
2845 CONFIG_BOOTSTAGE_USER_COUNT 2850 CONFIG_BOOTSTAGE_USER_COUNT
2846 This is the number of available user bootstage records. 2851 This is the number of available user bootstage records.
2847 Each time you call bootstage_mark(BOOTSTAGE_ID_ALLOC, ...) 2852 Each time you call bootstage_mark(BOOTSTAGE_ID_ALLOC, ...)
2848 a new ID will be allocated from this stash. If you exceed 2853 a new ID will be allocated from this stash. If you exceed
2849 the limit, recording will stop. 2854 the limit, recording will stop.
2850 2855
2851 CONFIG_BOOTSTAGE_REPORT 2856 CONFIG_BOOTSTAGE_REPORT
2852 Define this to print a report before boot, similar to this: 2857 Define this to print a report before boot, similar to this:
2853 2858
2854 Timer summary in microseconds: 2859 Timer summary in microseconds:
2855 Mark Elapsed Stage 2860 Mark Elapsed Stage
2856 0 0 reset 2861 0 0 reset
2857 3,575,678 3,575,678 board_init_f start 2862 3,575,678 3,575,678 board_init_f start
2858 3,575,695 17 arch_cpu_init A9 2863 3,575,695 17 arch_cpu_init A9
2859 3,575,777 82 arch_cpu_init done 2864 3,575,777 82 arch_cpu_init done
2860 3,659,598 83,821 board_init_r start 2865 3,659,598 83,821 board_init_r start
2861 3,910,375 250,777 main_loop 2866 3,910,375 250,777 main_loop
2862 29,916,167 26,005,792 bootm_start 2867 29,916,167 26,005,792 bootm_start
2863 30,361,327 445,160 start_kernel 2868 30,361,327 445,160 start_kernel
2864 2869
2865 CONFIG_CMD_BOOTSTAGE 2870 CONFIG_CMD_BOOTSTAGE
2866 Add a 'bootstage' command which supports printing a report 2871 Add a 'bootstage' command which supports printing a report
2867 and un/stashing of bootstage data. 2872 and un/stashing of bootstage data.
2868 2873
2869 CONFIG_BOOTSTAGE_FDT 2874 CONFIG_BOOTSTAGE_FDT
2870 Stash the bootstage information in the FDT. A root 'bootstage' 2875 Stash the bootstage information in the FDT. A root 'bootstage'
2871 node is created with each bootstage id as a child. Each child 2876 node is created with each bootstage id as a child. Each child
2872 has a 'name' property and either 'mark' containing the 2877 has a 'name' property and either 'mark' containing the
2873 mark time in microsecond, or 'accum' containing the 2878 mark time in microsecond, or 'accum' containing the
2874 accumulated time for that bootstage id in microseconds. 2879 accumulated time for that bootstage id in microseconds.
2875 For example: 2880 For example:
2876 2881
2877 bootstage { 2882 bootstage {
2878 154 { 2883 154 {
2879 name = "board_init_f"; 2884 name = "board_init_f";
2880 mark = <3575678>; 2885 mark = <3575678>;
2881 }; 2886 };
2882 170 { 2887 170 {
2883 name = "lcd"; 2888 name = "lcd";
2884 accum = <33482>; 2889 accum = <33482>;
2885 }; 2890 };
2886 }; 2891 };
2887 2892
2888 Code in the Linux kernel can find this in /proc/devicetree. 2893 Code in the Linux kernel can find this in /proc/devicetree.
2889 2894
2890 Legacy uImage format: 2895 Legacy uImage format:
2891 2896
2892 Arg Where When 2897 Arg Where When
2893 1 common/cmd_bootm.c before attempting to boot an image 2898 1 common/cmd_bootm.c before attempting to boot an image
2894 -1 common/cmd_bootm.c Image header has bad magic number 2899 -1 common/cmd_bootm.c Image header has bad magic number
2895 2 common/cmd_bootm.c Image header has correct magic number 2900 2 common/cmd_bootm.c Image header has correct magic number
2896 -2 common/cmd_bootm.c Image header has bad checksum 2901 -2 common/cmd_bootm.c Image header has bad checksum
2897 3 common/cmd_bootm.c Image header has correct checksum 2902 3 common/cmd_bootm.c Image header has correct checksum
2898 -3 common/cmd_bootm.c Image data has bad checksum 2903 -3 common/cmd_bootm.c Image data has bad checksum
2899 4 common/cmd_bootm.c Image data has correct checksum 2904 4 common/cmd_bootm.c Image data has correct checksum
2900 -4 common/cmd_bootm.c Image is for unsupported architecture 2905 -4 common/cmd_bootm.c Image is for unsupported architecture
2901 5 common/cmd_bootm.c Architecture check OK 2906 5 common/cmd_bootm.c Architecture check OK
2902 -5 common/cmd_bootm.c Wrong Image Type (not kernel, multi) 2907 -5 common/cmd_bootm.c Wrong Image Type (not kernel, multi)
2903 6 common/cmd_bootm.c Image Type check OK 2908 6 common/cmd_bootm.c Image Type check OK
2904 -6 common/cmd_bootm.c gunzip uncompression error 2909 -6 common/cmd_bootm.c gunzip uncompression error
2905 -7 common/cmd_bootm.c Unimplemented compression type 2910 -7 common/cmd_bootm.c Unimplemented compression type
2906 7 common/cmd_bootm.c Uncompression OK 2911 7 common/cmd_bootm.c Uncompression OK
2907 8 common/cmd_bootm.c No uncompress/copy overwrite error 2912 8 common/cmd_bootm.c No uncompress/copy overwrite error
2908 -9 common/cmd_bootm.c Unsupported OS (not Linux, BSD, VxWorks, QNX) 2913 -9 common/cmd_bootm.c Unsupported OS (not Linux, BSD, VxWorks, QNX)
2909 2914
2910 9 common/image.c Start initial ramdisk verification 2915 9 common/image.c Start initial ramdisk verification
2911 -10 common/image.c Ramdisk header has bad magic number 2916 -10 common/image.c Ramdisk header has bad magic number
2912 -11 common/image.c Ramdisk header has bad checksum 2917 -11 common/image.c Ramdisk header has bad checksum
2913 10 common/image.c Ramdisk header is OK 2918 10 common/image.c Ramdisk header is OK
2914 -12 common/image.c Ramdisk data has bad checksum 2919 -12 common/image.c Ramdisk data has bad checksum
2915 11 common/image.c Ramdisk data has correct checksum 2920 11 common/image.c Ramdisk data has correct checksum
2916 12 common/image.c Ramdisk verification complete, start loading 2921 12 common/image.c Ramdisk verification complete, start loading
2917 -13 common/image.c Wrong Image Type (not PPC Linux ramdisk) 2922 -13 common/image.c Wrong Image Type (not PPC Linux ramdisk)
2918 13 common/image.c Start multifile image verification 2923 13 common/image.c Start multifile image verification
2919 14 common/image.c No initial ramdisk, no multifile, continue. 2924 14 common/image.c No initial ramdisk, no multifile, continue.
2920 2925
2921 15 arch/<arch>/lib/bootm.c All preparation done, transferring control to OS 2926 15 arch/<arch>/lib/bootm.c All preparation done, transferring control to OS
2922 2927
2923 -30 arch/powerpc/lib/board.c Fatal error, hang the system 2928 -30 arch/powerpc/lib/board.c Fatal error, hang the system
2924 -31 post/post.c POST test failed, detected by post_output_backlog() 2929 -31 post/post.c POST test failed, detected by post_output_backlog()
2925 -32 post/post.c POST test failed, detected by post_run_single() 2930 -32 post/post.c POST test failed, detected by post_run_single()
2926 2931
2927 34 common/cmd_doc.c before loading a Image from a DOC device 2932 34 common/cmd_doc.c before loading a Image from a DOC device
2928 -35 common/cmd_doc.c Bad usage of "doc" command 2933 -35 common/cmd_doc.c Bad usage of "doc" command
2929 35 common/cmd_doc.c correct usage of "doc" command 2934 35 common/cmd_doc.c correct usage of "doc" command
2930 -36 common/cmd_doc.c No boot device 2935 -36 common/cmd_doc.c No boot device
2931 36 common/cmd_doc.c correct boot device 2936 36 common/cmd_doc.c correct boot device
2932 -37 common/cmd_doc.c Unknown Chip ID on boot device 2937 -37 common/cmd_doc.c Unknown Chip ID on boot device
2933 37 common/cmd_doc.c correct chip ID found, device available 2938 37 common/cmd_doc.c correct chip ID found, device available
2934 -38 common/cmd_doc.c Read Error on boot device 2939 -38 common/cmd_doc.c Read Error on boot device
2935 38 common/cmd_doc.c reading Image header from DOC device OK 2940 38 common/cmd_doc.c reading Image header from DOC device OK
2936 -39 common/cmd_doc.c Image header has bad magic number 2941 -39 common/cmd_doc.c Image header has bad magic number
2937 39 common/cmd_doc.c Image header has correct magic number 2942 39 common/cmd_doc.c Image header has correct magic number
2938 -40 common/cmd_doc.c Error reading Image from DOC device 2943 -40 common/cmd_doc.c Error reading Image from DOC device
2939 40 common/cmd_doc.c Image header has correct magic number 2944 40 common/cmd_doc.c Image header has correct magic number
2940 41 common/cmd_ide.c before loading a Image from a IDE device 2945 41 common/cmd_ide.c before loading a Image from a IDE device
2941 -42 common/cmd_ide.c Bad usage of "ide" command 2946 -42 common/cmd_ide.c Bad usage of "ide" command
2942 42 common/cmd_ide.c correct usage of "ide" command 2947 42 common/cmd_ide.c correct usage of "ide" command
2943 -43 common/cmd_ide.c No boot device 2948 -43 common/cmd_ide.c No boot device
2944 43 common/cmd_ide.c boot device found 2949 43 common/cmd_ide.c boot device found
2945 -44 common/cmd_ide.c Device not available 2950 -44 common/cmd_ide.c Device not available
2946 44 common/cmd_ide.c Device available 2951 44 common/cmd_ide.c Device available
2947 -45 common/cmd_ide.c wrong partition selected 2952 -45 common/cmd_ide.c wrong partition selected
2948 45 common/cmd_ide.c partition selected 2953 45 common/cmd_ide.c partition selected
2949 -46 common/cmd_ide.c Unknown partition table 2954 -46 common/cmd_ide.c Unknown partition table
2950 46 common/cmd_ide.c valid partition table found 2955 46 common/cmd_ide.c valid partition table found
2951 -47 common/cmd_ide.c Invalid partition type 2956 -47 common/cmd_ide.c Invalid partition type
2952 47 common/cmd_ide.c correct partition type 2957 47 common/cmd_ide.c correct partition type
2953 -48 common/cmd_ide.c Error reading Image Header on boot device 2958 -48 common/cmd_ide.c Error reading Image Header on boot device
2954 48 common/cmd_ide.c reading Image Header from IDE device OK 2959 48 common/cmd_ide.c reading Image Header from IDE device OK
2955 -49 common/cmd_ide.c Image header has bad magic number 2960 -49 common/cmd_ide.c Image header has bad magic number
2956 49 common/cmd_ide.c Image header has correct magic number 2961 49 common/cmd_ide.c Image header has correct magic number
2957 -50 common/cmd_ide.c Image header has bad checksum 2962 -50 common/cmd_ide.c Image header has bad checksum
2958 50 common/cmd_ide.c Image header has correct checksum 2963 50 common/cmd_ide.c Image header has correct checksum
2959 -51 common/cmd_ide.c Error reading Image from IDE device 2964 -51 common/cmd_ide.c Error reading Image from IDE device
2960 51 common/cmd_ide.c reading Image from IDE device OK 2965 51 common/cmd_ide.c reading Image from IDE device OK
2961 52 common/cmd_nand.c before loading a Image from a NAND device 2966 52 common/cmd_nand.c before loading a Image from a NAND device
2962 -53 common/cmd_nand.c Bad usage of "nand" command 2967 -53 common/cmd_nand.c Bad usage of "nand" command
2963 53 common/cmd_nand.c correct usage of "nand" command 2968 53 common/cmd_nand.c correct usage of "nand" command
2964 -54 common/cmd_nand.c No boot device 2969 -54 common/cmd_nand.c No boot device
2965 54 common/cmd_nand.c boot device found 2970 54 common/cmd_nand.c boot device found
2966 -55 common/cmd_nand.c Unknown Chip ID on boot device 2971 -55 common/cmd_nand.c Unknown Chip ID on boot device
2967 55 common/cmd_nand.c correct chip ID found, device available 2972 55 common/cmd_nand.c correct chip ID found, device available
2968 -56 common/cmd_nand.c Error reading Image Header on boot device 2973 -56 common/cmd_nand.c Error reading Image Header on boot device
2969 56 common/cmd_nand.c reading Image Header from NAND device OK 2974 56 common/cmd_nand.c reading Image Header from NAND device OK
2970 -57 common/cmd_nand.c Image header has bad magic number 2975 -57 common/cmd_nand.c Image header has bad magic number
2971 57 common/cmd_nand.c Image header has correct magic number 2976 57 common/cmd_nand.c Image header has correct magic number
2972 -58 common/cmd_nand.c Error reading Image from NAND device 2977 -58 common/cmd_nand.c Error reading Image from NAND device
2973 58 common/cmd_nand.c reading Image from NAND device OK 2978 58 common/cmd_nand.c reading Image from NAND device OK
2974 2979
2975 -60 common/env_common.c Environment has a bad CRC, using default 2980 -60 common/env_common.c Environment has a bad CRC, using default
2976 2981
2977 64 net/eth.c starting with Ethernet configuration. 2982 64 net/eth.c starting with Ethernet configuration.
2978 -64 net/eth.c no Ethernet found. 2983 -64 net/eth.c no Ethernet found.
2979 65 net/eth.c Ethernet found. 2984 65 net/eth.c Ethernet found.
2980 2985
2981 -80 common/cmd_net.c usage wrong 2986 -80 common/cmd_net.c usage wrong
2982 80 common/cmd_net.c before calling NetLoop() 2987 80 common/cmd_net.c before calling NetLoop()
2983 -81 common/cmd_net.c some error in NetLoop() occurred 2988 -81 common/cmd_net.c some error in NetLoop() occurred
2984 81 common/cmd_net.c NetLoop() back without error 2989 81 common/cmd_net.c NetLoop() back without error
2985 -82 common/cmd_net.c size == 0 (File with size 0 loaded) 2990 -82 common/cmd_net.c size == 0 (File with size 0 loaded)
2986 82 common/cmd_net.c trying automatic boot 2991 82 common/cmd_net.c trying automatic boot
2987 83 common/cmd_net.c running "source" command 2992 83 common/cmd_net.c running "source" command
2988 -83 common/cmd_net.c some error in automatic boot or "source" command 2993 -83 common/cmd_net.c some error in automatic boot or "source" command
2989 84 common/cmd_net.c end without errors 2994 84 common/cmd_net.c end without errors
2990 2995
2991 FIT uImage format: 2996 FIT uImage format:
2992 2997
2993 Arg Where When 2998 Arg Where When
2994 100 common/cmd_bootm.c Kernel FIT Image has correct format 2999 100 common/cmd_bootm.c Kernel FIT Image has correct format
2995 -100 common/cmd_bootm.c Kernel FIT Image has incorrect format 3000 -100 common/cmd_bootm.c Kernel FIT Image has incorrect format
2996 101 common/cmd_bootm.c No Kernel subimage unit name, using configuration 3001 101 common/cmd_bootm.c No Kernel subimage unit name, using configuration
2997 -101 common/cmd_bootm.c Can't get configuration for kernel subimage 3002 -101 common/cmd_bootm.c Can't get configuration for kernel subimage
2998 102 common/cmd_bootm.c Kernel unit name specified 3003 102 common/cmd_bootm.c Kernel unit name specified
2999 -103 common/cmd_bootm.c Can't get kernel subimage node offset 3004 -103 common/cmd_bootm.c Can't get kernel subimage node offset
3000 103 common/cmd_bootm.c Found configuration node 3005 103 common/cmd_bootm.c Found configuration node
3001 104 common/cmd_bootm.c Got kernel subimage node offset 3006 104 common/cmd_bootm.c Got kernel subimage node offset
3002 -104 common/cmd_bootm.c Kernel subimage hash verification failed 3007 -104 common/cmd_bootm.c Kernel subimage hash verification failed
3003 105 common/cmd_bootm.c Kernel subimage hash verification OK 3008 105 common/cmd_bootm.c Kernel subimage hash verification OK
3004 -105 common/cmd_bootm.c Kernel subimage is for unsupported architecture 3009 -105 common/cmd_bootm.c Kernel subimage is for unsupported architecture
3005 106 common/cmd_bootm.c Architecture check OK 3010 106 common/cmd_bootm.c Architecture check OK
3006 -106 common/cmd_bootm.c Kernel subimage has wrong type 3011 -106 common/cmd_bootm.c Kernel subimage has wrong type
3007 107 common/cmd_bootm.c Kernel subimage type OK 3012 107 common/cmd_bootm.c Kernel subimage type OK
3008 -107 common/cmd_bootm.c Can't get kernel subimage data/size 3013 -107 common/cmd_bootm.c Can't get kernel subimage data/size
3009 108 common/cmd_bootm.c Got kernel subimage data/size 3014 108 common/cmd_bootm.c Got kernel subimage data/size
3010 -108 common/cmd_bootm.c Wrong image type (not legacy, FIT) 3015 -108 common/cmd_bootm.c Wrong image type (not legacy, FIT)
3011 -109 common/cmd_bootm.c Can't get kernel subimage type 3016 -109 common/cmd_bootm.c Can't get kernel subimage type
3012 -110 common/cmd_bootm.c Can't get kernel subimage comp 3017 -110 common/cmd_bootm.c Can't get kernel subimage comp
3013 -111 common/cmd_bootm.c Can't get kernel subimage os 3018 -111 common/cmd_bootm.c Can't get kernel subimage os
3014 -112 common/cmd_bootm.c Can't get kernel subimage load address 3019 -112 common/cmd_bootm.c Can't get kernel subimage load address
3015 -113 common/cmd_bootm.c Image uncompress/copy overwrite error 3020 -113 common/cmd_bootm.c Image uncompress/copy overwrite error
3016 3021
3017 120 common/image.c Start initial ramdisk verification 3022 120 common/image.c Start initial ramdisk verification
3018 -120 common/image.c Ramdisk FIT image has incorrect format 3023 -120 common/image.c Ramdisk FIT image has incorrect format
3019 121 common/image.c Ramdisk FIT image has correct format 3024 121 common/image.c Ramdisk FIT image has correct format
3020 122 common/image.c No ramdisk subimage unit name, using configuration 3025 122 common/image.c No ramdisk subimage unit name, using configuration
3021 -122 common/image.c Can't get configuration for ramdisk subimage 3026 -122 common/image.c Can't get configuration for ramdisk subimage
3022 123 common/image.c Ramdisk unit name specified 3027 123 common/image.c Ramdisk unit name specified
3023 -124 common/image.c Can't get ramdisk subimage node offset 3028 -124 common/image.c Can't get ramdisk subimage node offset
3024 125 common/image.c Got ramdisk subimage node offset 3029 125 common/image.c Got ramdisk subimage node offset
3025 -125 common/image.c Ramdisk subimage hash verification failed 3030 -125 common/image.c Ramdisk subimage hash verification failed
3026 126 common/image.c Ramdisk subimage hash verification OK 3031 126 common/image.c Ramdisk subimage hash verification OK
3027 -126 common/image.c Ramdisk subimage for unsupported architecture 3032 -126 common/image.c Ramdisk subimage for unsupported architecture
3028 127 common/image.c Architecture check OK 3033 127 common/image.c Architecture check OK
3029 -127 common/image.c Can't get ramdisk subimage data/size 3034 -127 common/image.c Can't get ramdisk subimage data/size
3030 128 common/image.c Got ramdisk subimage data/size 3035 128 common/image.c Got ramdisk subimage data/size
3031 129 common/image.c Can't get ramdisk load address 3036 129 common/image.c Can't get ramdisk load address
3032 -129 common/image.c Got ramdisk load address 3037 -129 common/image.c Got ramdisk load address
3033 3038
3034 -130 common/cmd_doc.c Incorrect FIT image format 3039 -130 common/cmd_doc.c Incorrect FIT image format
3035 131 common/cmd_doc.c FIT image format OK 3040 131 common/cmd_doc.c FIT image format OK
3036 3041
3037 -140 common/cmd_ide.c Incorrect FIT image format 3042 -140 common/cmd_ide.c Incorrect FIT image format
3038 141 common/cmd_ide.c FIT image format OK 3043 141 common/cmd_ide.c FIT image format OK
3039 3044
3040 -150 common/cmd_nand.c Incorrect FIT image format 3045 -150 common/cmd_nand.c Incorrect FIT image format
3041 151 common/cmd_nand.c FIT image format OK 3046 151 common/cmd_nand.c FIT image format OK
3042 3047
3043 - FIT image support: 3048 - FIT image support:
3044 CONFIG_FIT 3049 CONFIG_FIT
3045 Enable support for the FIT uImage format. 3050 Enable support for the FIT uImage format.
3046 3051
3047 CONFIG_FIT_BEST_MATCH 3052 CONFIG_FIT_BEST_MATCH
3048 When no configuration is explicitly selected, default to the 3053 When no configuration is explicitly selected, default to the
3049 one whose fdt's compatibility field best matches that of 3054 one whose fdt's compatibility field best matches that of
3050 U-Boot itself. A match is considered "best" if it matches the 3055 U-Boot itself. A match is considered "best" if it matches the
3051 most specific compatibility entry of U-Boot's fdt's root node. 3056 most specific compatibility entry of U-Boot's fdt's root node.
3052 The order of entries in the configuration's fdt is ignored. 3057 The order of entries in the configuration's fdt is ignored.
3053 3058
3054 CONFIG_FIT_SIGNATURE 3059 CONFIG_FIT_SIGNATURE
3055 This option enables signature verification of FIT uImages, 3060 This option enables signature verification of FIT uImages,
3056 using a hash signed and verified using RSA. See 3061 using a hash signed and verified using RSA. See
3057 doc/uImage.FIT/signature.txt for more details. 3062 doc/uImage.FIT/signature.txt for more details.
3058 3063
3059 - Standalone program support: 3064 - Standalone program support:
3060 CONFIG_STANDALONE_LOAD_ADDR 3065 CONFIG_STANDALONE_LOAD_ADDR
3061 3066
3062 This option defines a board specific value for the 3067 This option defines a board specific value for the
3063 address where standalone program gets loaded, thus 3068 address where standalone program gets loaded, thus
3064 overwriting the architecture dependent default 3069 overwriting the architecture dependent default
3065 settings. 3070 settings.
3066 3071
3067 - Frame Buffer Address: 3072 - Frame Buffer Address:
3068 CONFIG_FB_ADDR 3073 CONFIG_FB_ADDR
3069 3074
3070 Define CONFIG_FB_ADDR if you want to use specific 3075 Define CONFIG_FB_ADDR if you want to use specific
3071 address for frame buffer. This is typically the case 3076 address for frame buffer. This is typically the case
3072 when using a graphics controller has separate video 3077 when using a graphics controller has separate video
3073 memory. U-Boot will then place the frame buffer at 3078 memory. U-Boot will then place the frame buffer at
3074 the given address instead of dynamically reserving it 3079 the given address instead of dynamically reserving it
3075 in system RAM by calling lcd_setmem(), which grabs 3080 in system RAM by calling lcd_setmem(), which grabs
3076 the memory for the frame buffer depending on the 3081 the memory for the frame buffer depending on the
3077 configured panel size. 3082 configured panel size.
3078 3083
3079 Please see board_init_f function. 3084 Please see board_init_f function.
3080 3085
3081 - Automatic software updates via TFTP server 3086 - Automatic software updates via TFTP server
3082 CONFIG_UPDATE_TFTP 3087 CONFIG_UPDATE_TFTP
3083 CONFIG_UPDATE_TFTP_CNT_MAX 3088 CONFIG_UPDATE_TFTP_CNT_MAX
3084 CONFIG_UPDATE_TFTP_MSEC_MAX 3089 CONFIG_UPDATE_TFTP_MSEC_MAX
3085 3090
3086 These options enable and control the auto-update feature; 3091 These options enable and control the auto-update feature;
3087 for a more detailed description refer to doc/README.update. 3092 for a more detailed description refer to doc/README.update.
3088 3093
3089 - MTD Support (mtdparts command, UBI support) 3094 - MTD Support (mtdparts command, UBI support)
3090 CONFIG_MTD_DEVICE 3095 CONFIG_MTD_DEVICE
3091 3096
3092 Adds the MTD device infrastructure from the Linux kernel. 3097 Adds the MTD device infrastructure from the Linux kernel.
3093 Needed for mtdparts command support. 3098 Needed for mtdparts command support.
3094 3099
3095 CONFIG_MTD_PARTITIONS 3100 CONFIG_MTD_PARTITIONS
3096 3101
3097 Adds the MTD partitioning infrastructure from the Linux 3102 Adds the MTD partitioning infrastructure from the Linux
3098 kernel. Needed for UBI support. 3103 kernel. Needed for UBI support.
3099 3104
3100 - UBI support 3105 - UBI support
3101 CONFIG_CMD_UBI 3106 CONFIG_CMD_UBI
3102 3107
3103 Adds commands for interacting with MTD partitions formatted 3108 Adds commands for interacting with MTD partitions formatted
3104 with the UBI flash translation layer 3109 with the UBI flash translation layer
3105 3110
3106 Requires also defining CONFIG_RBTREE 3111 Requires also defining CONFIG_RBTREE
3107 3112
3108 CONFIG_UBI_SILENCE_MSG 3113 CONFIG_UBI_SILENCE_MSG
3109 3114
3110 Make the verbose messages from UBI stop printing. This leaves 3115 Make the verbose messages from UBI stop printing. This leaves
3111 warnings and errors enabled. 3116 warnings and errors enabled.
3112 3117
3113 - UBIFS support 3118 - UBIFS support
3114 CONFIG_CMD_UBIFS 3119 CONFIG_CMD_UBIFS
3115 3120
3116 Adds commands for interacting with UBI volumes formatted as 3121 Adds commands for interacting with UBI volumes formatted as
3117 UBIFS. UBIFS is read-only in u-boot. 3122 UBIFS. UBIFS is read-only in u-boot.
3118 3123
3119 Requires UBI support as well as CONFIG_LZO 3124 Requires UBI support as well as CONFIG_LZO
3120 3125
3121 CONFIG_UBIFS_SILENCE_MSG 3126 CONFIG_UBIFS_SILENCE_MSG
3122 3127
3123 Make the verbose messages from UBIFS stop printing. This leaves 3128 Make the verbose messages from UBIFS stop printing. This leaves
3124 warnings and errors enabled. 3129 warnings and errors enabled.
3125 3130
3126 - SPL framework 3131 - SPL framework
3127 CONFIG_SPL 3132 CONFIG_SPL
3128 Enable building of SPL globally. 3133 Enable building of SPL globally.
3129 3134
3130 CONFIG_SPL_LDSCRIPT 3135 CONFIG_SPL_LDSCRIPT
3131 LDSCRIPT for linking the SPL binary. 3136 LDSCRIPT for linking the SPL binary.
3132 3137
3133 CONFIG_SPL_MAX_FOOTPRINT 3138 CONFIG_SPL_MAX_FOOTPRINT
3134 Maximum size in memory allocated to the SPL, BSS included. 3139 Maximum size in memory allocated to the SPL, BSS included.
3135 When defined, the linker checks that the actual memory 3140 When defined, the linker checks that the actual memory
3136 used by SPL from _start to __bss_end does not exceed it. 3141 used by SPL from _start to __bss_end does not exceed it.
3137 CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE 3142 CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
3138 must not be both defined at the same time. 3143 must not be both defined at the same time.
3139 3144
3140 CONFIG_SPL_MAX_SIZE 3145 CONFIG_SPL_MAX_SIZE
3141 Maximum size of the SPL image (text, data, rodata, and 3146 Maximum size of the SPL image (text, data, rodata, and
3142 linker lists sections), BSS excluded. 3147 linker lists sections), BSS excluded.
3143 When defined, the linker checks that the actual size does 3148 When defined, the linker checks that the actual size does
3144 not exceed it. 3149 not exceed it.
3145 3150
3146 CONFIG_SPL_TEXT_BASE 3151 CONFIG_SPL_TEXT_BASE
3147 TEXT_BASE for linking the SPL binary. 3152 TEXT_BASE for linking the SPL binary.
3148 3153
3149 CONFIG_SPL_RELOC_TEXT_BASE 3154 CONFIG_SPL_RELOC_TEXT_BASE
3150 Address to relocate to. If unspecified, this is equal to 3155 Address to relocate to. If unspecified, this is equal to
3151 CONFIG_SPL_TEXT_BASE (i.e. no relocation is done). 3156 CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).
3152 3157
3153 CONFIG_SPL_BSS_START_ADDR 3158 CONFIG_SPL_BSS_START_ADDR
3154 Link address for the BSS within the SPL binary. 3159 Link address for the BSS within the SPL binary.
3155 3160
3156 CONFIG_SPL_BSS_MAX_SIZE 3161 CONFIG_SPL_BSS_MAX_SIZE
3157 Maximum size in memory allocated to the SPL BSS. 3162 Maximum size in memory allocated to the SPL BSS.
3158 When defined, the linker checks that the actual memory used 3163 When defined, the linker checks that the actual memory used
3159 by SPL from __bss_start to __bss_end does not exceed it. 3164 by SPL from __bss_start to __bss_end does not exceed it.
3160 CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE 3165 CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
3161 must not be both defined at the same time. 3166 must not be both defined at the same time.
3162 3167
3163 CONFIG_SPL_STACK 3168 CONFIG_SPL_STACK
3164 Adress of the start of the stack SPL will use 3169 Adress of the start of the stack SPL will use
3165 3170
3166 CONFIG_SPL_RELOC_STACK 3171 CONFIG_SPL_RELOC_STACK
3167 Adress of the start of the stack SPL will use after 3172 Adress of the start of the stack SPL will use after
3168 relocation. If unspecified, this is equal to 3173 relocation. If unspecified, this is equal to
3169 CONFIG_SPL_STACK. 3174 CONFIG_SPL_STACK.
3170 3175
3171 CONFIG_SYS_SPL_MALLOC_START 3176 CONFIG_SYS_SPL_MALLOC_START
3172 Starting address of the malloc pool used in SPL. 3177 Starting address of the malloc pool used in SPL.
3173 3178
3174 CONFIG_SYS_SPL_MALLOC_SIZE 3179 CONFIG_SYS_SPL_MALLOC_SIZE
3175 The size of the malloc pool used in SPL. 3180 The size of the malloc pool used in SPL.
3176 3181
3177 CONFIG_SPL_FRAMEWORK 3182 CONFIG_SPL_FRAMEWORK
3178 Enable the SPL framework under common/. This framework 3183 Enable the SPL framework under common/. This framework
3179 supports MMC, NAND and YMODEM loading of U-Boot and NAND 3184 supports MMC, NAND and YMODEM loading of U-Boot and NAND
3180 NAND loading of the Linux Kernel. 3185 NAND loading of the Linux Kernel.
3181 3186
3182 CONFIG_SPL_DISPLAY_PRINT 3187 CONFIG_SPL_DISPLAY_PRINT
3183 For ARM, enable an optional function to print more information 3188 For ARM, enable an optional function to print more information
3184 about the running system. 3189 about the running system.
3185 3190
3186 CONFIG_SPL_INIT_MINIMAL 3191 CONFIG_SPL_INIT_MINIMAL
3187 Arch init code should be built for a very small image 3192 Arch init code should be built for a very small image
3188 3193
3189 CONFIG_SPL_LIBCOMMON_SUPPORT 3194 CONFIG_SPL_LIBCOMMON_SUPPORT
3190 Support for common/libcommon.o in SPL binary 3195 Support for common/libcommon.o in SPL binary
3191 3196
3192 CONFIG_SPL_LIBDISK_SUPPORT 3197 CONFIG_SPL_LIBDISK_SUPPORT
3193 Support for disk/libdisk.o in SPL binary 3198 Support for disk/libdisk.o in SPL binary
3194 3199
3195 CONFIG_SPL_I2C_SUPPORT 3200 CONFIG_SPL_I2C_SUPPORT
3196 Support for drivers/i2c/libi2c.o in SPL binary 3201 Support for drivers/i2c/libi2c.o in SPL binary
3197 3202
3198 CONFIG_SPL_GPIO_SUPPORT 3203 CONFIG_SPL_GPIO_SUPPORT
3199 Support for drivers/gpio/libgpio.o in SPL binary 3204 Support for drivers/gpio/libgpio.o in SPL binary
3200 3205
3201 CONFIG_SPL_MMC_SUPPORT 3206 CONFIG_SPL_MMC_SUPPORT
3202 Support for drivers/mmc/libmmc.o in SPL binary 3207 Support for drivers/mmc/libmmc.o in SPL binary
3203 3208
3204 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, 3209 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
3205 CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS, 3210 CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
3206 CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 3211 CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION
3207 Address, size and partition on the MMC to load U-Boot from 3212 Address, size and partition on the MMC to load U-Boot from
3208 when the MMC is being used in raw mode. 3213 when the MMC is being used in raw mode.
3209 3214
3210 CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 3215 CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
3211 Sector to load kernel uImage from when MMC is being 3216 Sector to load kernel uImage from when MMC is being
3212 used in raw mode (for Falcon mode) 3217 used in raw mode (for Falcon mode)
3213 3218
3214 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR, 3219 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
3215 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 3220 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
3216 Sector and number of sectors to load kernel argument 3221 Sector and number of sectors to load kernel argument
3217 parameters from when MMC is being used in raw mode 3222 parameters from when MMC is being used in raw mode
3218 (for falcon mode) 3223 (for falcon mode)
3219 3224
3220 CONFIG_SPL_FAT_SUPPORT 3225 CONFIG_SPL_FAT_SUPPORT
3221 Support for fs/fat/libfat.o in SPL binary 3226 Support for fs/fat/libfat.o in SPL binary
3222 3227
3223 CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME 3228 CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME
3224 Filename to read to load U-Boot when reading from FAT 3229 Filename to read to load U-Boot when reading from FAT
3225 3230
3226 CONFIG_SPL_FAT_LOAD_KERNEL_NAME 3231 CONFIG_SPL_FAT_LOAD_KERNEL_NAME
3227 Filename to read to load kernel uImage when reading 3232 Filename to read to load kernel uImage when reading
3228 from FAT (for Falcon mode) 3233 from FAT (for Falcon mode)
3229 3234
3230 CONFIG_SPL_FAT_LOAD_ARGS_NAME 3235 CONFIG_SPL_FAT_LOAD_ARGS_NAME
3231 Filename to read to load kernel argument parameters 3236 Filename to read to load kernel argument parameters
3232 when reading from FAT (for Falcon mode) 3237 when reading from FAT (for Falcon mode)
3233 3238
3234 CONFIG_SPL_MPC83XX_WAIT_FOR_NAND 3239 CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
3235 Set this for NAND SPL on PPC mpc83xx targets, so that 3240 Set this for NAND SPL on PPC mpc83xx targets, so that
3236 start.S waits for the rest of the SPL to load before 3241 start.S waits for the rest of the SPL to load before
3237 continuing (the hardware starts execution after just 3242 continuing (the hardware starts execution after just
3238 loading the first page rather than the full 4K). 3243 loading the first page rather than the full 4K).
3239 3244
3240 CONFIG_SPL_NAND_BASE 3245 CONFIG_SPL_NAND_BASE
3241 Include nand_base.c in the SPL. Requires 3246 Include nand_base.c in the SPL. Requires
3242 CONFIG_SPL_NAND_DRIVERS. 3247 CONFIG_SPL_NAND_DRIVERS.
3243 3248
3244 CONFIG_SPL_NAND_DRIVERS 3249 CONFIG_SPL_NAND_DRIVERS
3245 SPL uses normal NAND drivers, not minimal drivers. 3250 SPL uses normal NAND drivers, not minimal drivers.
3246 3251
3247 CONFIG_SPL_NAND_ECC 3252 CONFIG_SPL_NAND_ECC
3248 Include standard software ECC in the SPL 3253 Include standard software ECC in the SPL
3249 3254
3250 CONFIG_SPL_NAND_SIMPLE 3255 CONFIG_SPL_NAND_SIMPLE
3251 Support for NAND boot using simple NAND drivers that 3256 Support for NAND boot using simple NAND drivers that
3252 expose the cmd_ctrl() interface. 3257 expose the cmd_ctrl() interface.
3253 3258
3254 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 3259 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
3255 Set for the SPL on PPC mpc8xxx targets, support for 3260 Set for the SPL on PPC mpc8xxx targets, support for
3256 drivers/ddr/fsl/libddr.o in SPL binary. 3261 drivers/ddr/fsl/libddr.o in SPL binary.
3257 3262
3258 CONFIG_SPL_COMMON_INIT_DDR 3263 CONFIG_SPL_COMMON_INIT_DDR
3259 Set for common ddr init with serial presence detect in 3264 Set for common ddr init with serial presence detect in
3260 SPL binary. 3265 SPL binary.
3261 3266
3262 CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT, 3267 CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
3263 CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE, 3268 CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
3264 CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS, 3269 CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
3265 CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE, 3270 CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
3266 CONFIG_SYS_NAND_ECCBYTES 3271 CONFIG_SYS_NAND_ECCBYTES
3267 Defines the size and behavior of the NAND that SPL uses 3272 Defines the size and behavior of the NAND that SPL uses
3268 to read U-Boot 3273 to read U-Boot
3274
3275 CONFIG_SPL_NAND_BOOT
3276 Add support NAND boot
3269 3277
3270 CONFIG_SYS_NAND_U_BOOT_OFFS 3278 CONFIG_SYS_NAND_U_BOOT_OFFS
3271 Location in NAND to read U-Boot from 3279 Location in NAND to read U-Boot from
3272 3280
3273 CONFIG_SYS_NAND_U_BOOT_DST 3281 CONFIG_SYS_NAND_U_BOOT_DST
3274 Location in memory to load U-Boot to 3282 Location in memory to load U-Boot to
3275 3283
3276 CONFIG_SYS_NAND_U_BOOT_SIZE 3284 CONFIG_SYS_NAND_U_BOOT_SIZE
3277 Size of image to load 3285 Size of image to load
3278 3286
3279 CONFIG_SYS_NAND_U_BOOT_START 3287 CONFIG_SYS_NAND_U_BOOT_START
3280 Entry point in loaded image to jump to 3288 Entry point in loaded image to jump to
3281 3289
3282 CONFIG_SYS_NAND_HW_ECC_OOBFIRST 3290 CONFIG_SYS_NAND_HW_ECC_OOBFIRST
3283 Define this if you need to first read the OOB and then the 3291 Define this if you need to first read the OOB and then the
3284 data. This is used for example on davinci plattforms. 3292 data. This is used for example on davinci plattforms.
3285 3293
3286 CONFIG_SPL_OMAP3_ID_NAND 3294 CONFIG_SPL_OMAP3_ID_NAND
3287 Support for an OMAP3-specific set of functions to return the 3295 Support for an OMAP3-specific set of functions to return the
3288 ID and MFR of the first attached NAND chip, if present. 3296 ID and MFR of the first attached NAND chip, if present.
3289 3297
3290 CONFIG_SPL_SERIAL_SUPPORT 3298 CONFIG_SPL_SERIAL_SUPPORT
3291 Support for drivers/serial/libserial.o in SPL binary 3299 Support for drivers/serial/libserial.o in SPL binary
3292 3300
3293 CONFIG_SPL_SPI_FLASH_SUPPORT 3301 CONFIG_SPL_SPI_FLASH_SUPPORT
3294 Support for drivers/mtd/spi/libspi_flash.o in SPL binary 3302 Support for drivers/mtd/spi/libspi_flash.o in SPL binary
3295 3303
3296 CONFIG_SPL_SPI_SUPPORT 3304 CONFIG_SPL_SPI_SUPPORT
3297 Support for drivers/spi/libspi.o in SPL binary 3305 Support for drivers/spi/libspi.o in SPL binary
3298 3306
3299 CONFIG_SPL_RAM_DEVICE 3307 CONFIG_SPL_RAM_DEVICE
3300 Support for running image already present in ram, in SPL binary 3308 Support for running image already present in ram, in SPL binary
3301 3309
3302 CONFIG_SPL_LIBGENERIC_SUPPORT 3310 CONFIG_SPL_LIBGENERIC_SUPPORT
3303 Support for lib/libgeneric.o in SPL binary 3311 Support for lib/libgeneric.o in SPL binary
3304 3312
3305 CONFIG_SPL_ENV_SUPPORT 3313 CONFIG_SPL_ENV_SUPPORT
3306 Support for the environment operating in SPL binary 3314 Support for the environment operating in SPL binary
3307 3315
3308 CONFIG_SPL_NET_SUPPORT 3316 CONFIG_SPL_NET_SUPPORT
3309 Support for the net/libnet.o in SPL binary. 3317 Support for the net/libnet.o in SPL binary.
3310 It conflicts with SPL env from storage medium specified by 3318 It conflicts with SPL env from storage medium specified by
3311 CONFIG_ENV_IS_xxx but CONFIG_ENV_IS_NOWHERE 3319 CONFIG_ENV_IS_xxx but CONFIG_ENV_IS_NOWHERE
3312 3320
3313 CONFIG_SPL_PAD_TO 3321 CONFIG_SPL_PAD_TO
3314 Image offset to which the SPL should be padded before appending 3322 Image offset to which the SPL should be padded before appending
3315 the SPL payload. By default, this is defined as 3323 the SPL payload. By default, this is defined as
3316 CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined. 3324 CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
3317 CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL 3325 CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
3318 payload without any padding, or >= CONFIG_SPL_MAX_SIZE. 3326 payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
3319 3327
3320 CONFIG_SPL_TARGET 3328 CONFIG_SPL_TARGET
3321 Final target image containing SPL and payload. Some SPLs 3329 Final target image containing SPL and payload. Some SPLs
3322 use an arch-specific makefile fragment instead, for 3330 use an arch-specific makefile fragment instead, for
3323 example if more than one image needs to be produced. 3331 example if more than one image needs to be produced.
3324 3332
3325 CONFIG_FIT_SPL_PRINT 3333 CONFIG_FIT_SPL_PRINT
3326 Printing information about a FIT image adds quite a bit of 3334 Printing information about a FIT image adds quite a bit of
3327 code to SPL. So this is normally disabled in SPL. Use this 3335 code to SPL. So this is normally disabled in SPL. Use this
3328 option to re-enable it. This will affect the output of the 3336 option to re-enable it. This will affect the output of the
3329 bootm command when booting a FIT image. 3337 bootm command when booting a FIT image.
3330 3338
3331 - TPL framework 3339 - TPL framework
3332 CONFIG_TPL 3340 CONFIG_TPL
3333 Enable building of TPL globally. 3341 Enable building of TPL globally.
3334 3342
3335 CONFIG_TPL_PAD_TO 3343 CONFIG_TPL_PAD_TO
3336 Image offset to which the TPL should be padded before appending 3344 Image offset to which the TPL should be padded before appending
3337 the TPL payload. By default, this is defined as 3345 the TPL payload. By default, this is defined as
3338 CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined. 3346 CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
3339 CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL 3347 CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
3340 payload without any padding, or >= CONFIG_SPL_MAX_SIZE. 3348 payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
3341 3349
3342 Modem Support: 3350 Modem Support:
3343 -------------- 3351 --------------
3344 3352
3345 [so far only for SMDK2400 boards] 3353 [so far only for SMDK2400 boards]
3346 3354
3347 - Modem support enable: 3355 - Modem support enable:
3348 CONFIG_MODEM_SUPPORT 3356 CONFIG_MODEM_SUPPORT
3349 3357
3350 - RTS/CTS Flow control enable: 3358 - RTS/CTS Flow control enable:
3351 CONFIG_HWFLOW 3359 CONFIG_HWFLOW
3352 3360
3353 - Modem debug support: 3361 - Modem debug support:
3354 CONFIG_MODEM_SUPPORT_DEBUG 3362 CONFIG_MODEM_SUPPORT_DEBUG
3355 3363
3356 Enables debugging stuff (char screen[1024], dbg()) 3364 Enables debugging stuff (char screen[1024], dbg())
3357 for modem support. Useful only with BDI2000. 3365 for modem support. Useful only with BDI2000.
3358 3366
3359 - Interrupt support (PPC): 3367 - Interrupt support (PPC):
3360 3368
3361 There are common interrupt_init() and timer_interrupt() 3369 There are common interrupt_init() and timer_interrupt()
3362 for all PPC archs. interrupt_init() calls interrupt_init_cpu() 3370 for all PPC archs. interrupt_init() calls interrupt_init_cpu()
3363 for CPU specific initialization. interrupt_init_cpu() 3371 for CPU specific initialization. interrupt_init_cpu()
3364 should set decrementer_count to appropriate value. If 3372 should set decrementer_count to appropriate value. If
3365 CPU resets decrementer automatically after interrupt 3373 CPU resets decrementer automatically after interrupt
3366 (ppc4xx) it should set decrementer_count to zero. 3374 (ppc4xx) it should set decrementer_count to zero.
3367 timer_interrupt() calls timer_interrupt_cpu() for CPU 3375 timer_interrupt() calls timer_interrupt_cpu() for CPU
3368 specific handling. If board has watchdog / status_led 3376 specific handling. If board has watchdog / status_led
3369 / other_activity_monitor it works automatically from 3377 / other_activity_monitor it works automatically from
3370 general timer_interrupt(). 3378 general timer_interrupt().
3371 3379
3372 - General: 3380 - General:
3373 3381
3374 In the target system modem support is enabled when a 3382 In the target system modem support is enabled when a
3375 specific key (key combination) is pressed during 3383 specific key (key combination) is pressed during
3376 power-on. Otherwise U-Boot will boot normally 3384 power-on. Otherwise U-Boot will boot normally
3377 (autoboot). The key_pressed() function is called from 3385 (autoboot). The key_pressed() function is called from
3378 board_init(). Currently key_pressed() is a dummy 3386 board_init(). Currently key_pressed() is a dummy
3379 function, returning 1 and thus enabling modem 3387 function, returning 1 and thus enabling modem
3380 initialization. 3388 initialization.
3381 3389
3382 If there are no modem init strings in the 3390 If there are no modem init strings in the
3383 environment, U-Boot proceed to autoboot; the 3391 environment, U-Boot proceed to autoboot; the
3384 previous output (banner, info printfs) will be 3392 previous output (banner, info printfs) will be
3385 suppressed, though. 3393 suppressed, though.
3386 3394
3387 See also: doc/README.Modem 3395 See also: doc/README.Modem
3388 3396
3389 Board initialization settings: 3397 Board initialization settings:
3390 ------------------------------ 3398 ------------------------------
3391 3399
3392 During Initialization u-boot calls a number of board specific functions 3400 During Initialization u-boot calls a number of board specific functions
3393 to allow the preparation of board specific prerequisites, e.g. pin setup 3401 to allow the preparation of board specific prerequisites, e.g. pin setup
3394 before drivers are initialized. To enable these callbacks the 3402 before drivers are initialized. To enable these callbacks the
3395 following configuration macros have to be defined. Currently this is 3403 following configuration macros have to be defined. Currently this is
3396 architecture specific, so please check arch/your_architecture/lib/board.c 3404 architecture specific, so please check arch/your_architecture/lib/board.c
3397 typically in board_init_f() and board_init_r(). 3405 typically in board_init_f() and board_init_r().
3398 3406
3399 - CONFIG_BOARD_EARLY_INIT_F: Call board_early_init_f() 3407 - CONFIG_BOARD_EARLY_INIT_F: Call board_early_init_f()
3400 - CONFIG_BOARD_EARLY_INIT_R: Call board_early_init_r() 3408 - CONFIG_BOARD_EARLY_INIT_R: Call board_early_init_r()
3401 - CONFIG_BOARD_LATE_INIT: Call board_late_init() 3409 - CONFIG_BOARD_LATE_INIT: Call board_late_init()
3402 - CONFIG_BOARD_POSTCLK_INIT: Call board_postclk_init() 3410 - CONFIG_BOARD_POSTCLK_INIT: Call board_postclk_init()
3403 3411
3404 Configuration Settings: 3412 Configuration Settings:
3405 ----------------------- 3413 -----------------------
3406 3414
3407 - CONFIG_SYS_LONGHELP: Defined when you want long help messages included; 3415 - CONFIG_SYS_LONGHELP: Defined when you want long help messages included;
3408 undefine this when you're short of memory. 3416 undefine this when you're short of memory.
3409 3417
3410 - CONFIG_SYS_HELP_CMD_WIDTH: Defined when you want to override the default 3418 - CONFIG_SYS_HELP_CMD_WIDTH: Defined when you want to override the default
3411 width of the commands listed in the 'help' command output. 3419 width of the commands listed in the 'help' command output.
3412 3420
3413 - CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to 3421 - CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to
3414 prompt for user input. 3422 prompt for user input.
3415 3423
3416 - CONFIG_SYS_CBSIZE: Buffer size for input from the Console 3424 - CONFIG_SYS_CBSIZE: Buffer size for input from the Console
3417 3425
3418 - CONFIG_SYS_PBSIZE: Buffer size for Console output 3426 - CONFIG_SYS_PBSIZE: Buffer size for Console output
3419 3427
3420 - CONFIG_SYS_MAXARGS: max. Number of arguments accepted for monitor commands 3428 - CONFIG_SYS_MAXARGS: max. Number of arguments accepted for monitor commands
3421 3429
3422 - CONFIG_SYS_BARGSIZE: Buffer size for Boot Arguments which are passed to 3430 - CONFIG_SYS_BARGSIZE: Buffer size for Boot Arguments which are passed to
3423 the application (usually a Linux kernel) when it is 3431 the application (usually a Linux kernel) when it is
3424 booted 3432 booted
3425 3433
3426 - CONFIG_SYS_BAUDRATE_TABLE: 3434 - CONFIG_SYS_BAUDRATE_TABLE:
3427 List of legal baudrate settings for this board. 3435 List of legal baudrate settings for this board.
3428 3436
3429 - CONFIG_SYS_CONSOLE_INFO_QUIET 3437 - CONFIG_SYS_CONSOLE_INFO_QUIET
3430 Suppress display of console information at boot. 3438 Suppress display of console information at boot.
3431 3439
3432 - CONFIG_SYS_CONSOLE_IS_IN_ENV 3440 - CONFIG_SYS_CONSOLE_IS_IN_ENV
3433 If the board specific function 3441 If the board specific function
3434 extern int overwrite_console (void); 3442 extern int overwrite_console (void);
3435 returns 1, the stdin, stderr and stdout are switched to the 3443 returns 1, the stdin, stderr and stdout are switched to the
3436 serial port, else the settings in the environment are used. 3444 serial port, else the settings in the environment are used.
3437 3445
3438 - CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 3446 - CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
3439 Enable the call to overwrite_console(). 3447 Enable the call to overwrite_console().
3440 3448
3441 - CONFIG_SYS_CONSOLE_ENV_OVERWRITE 3449 - CONFIG_SYS_CONSOLE_ENV_OVERWRITE
3442 Enable overwrite of previous console environment settings. 3450 Enable overwrite of previous console environment settings.
3443 3451
3444 - CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END: 3452 - CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END:
3445 Begin and End addresses of the area used by the 3453 Begin and End addresses of the area used by the
3446 simple memory test. 3454 simple memory test.
3447 3455
3448 - CONFIG_SYS_ALT_MEMTEST: 3456 - CONFIG_SYS_ALT_MEMTEST:
3449 Enable an alternate, more extensive memory test. 3457 Enable an alternate, more extensive memory test.
3450 3458
3451 - CONFIG_SYS_MEMTEST_SCRATCH: 3459 - CONFIG_SYS_MEMTEST_SCRATCH:
3452 Scratch address used by the alternate memory test 3460 Scratch address used by the alternate memory test
3453 You only need to set this if address zero isn't writeable 3461 You only need to set this if address zero isn't writeable
3454 3462
3455 - CONFIG_SYS_MEM_TOP_HIDE (PPC only): 3463 - CONFIG_SYS_MEM_TOP_HIDE (PPC only):
3456 If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config header, 3464 If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config header,
3457 this specified memory area will get subtracted from the top 3465 this specified memory area will get subtracted from the top
3458 (end) of RAM and won't get "touched" at all by U-Boot. By 3466 (end) of RAM and won't get "touched" at all by U-Boot. By
3459 fixing up gd->ram_size the Linux kernel should gets passed 3467 fixing up gd->ram_size the Linux kernel should gets passed
3460 the now "corrected" memory size and won't touch it either. 3468 the now "corrected" memory size and won't touch it either.
3461 This should work for arch/ppc and arch/powerpc. Only Linux 3469 This should work for arch/ppc and arch/powerpc. Only Linux
3462 board ports in arch/powerpc with bootwrapper support that 3470 board ports in arch/powerpc with bootwrapper support that
3463 recalculate the memory size from the SDRAM controller setup 3471 recalculate the memory size from the SDRAM controller setup
3464 will have to get fixed in Linux additionally. 3472 will have to get fixed in Linux additionally.
3465 3473
3466 This option can be used as a workaround for the 440EPx/GRx 3474 This option can be used as a workaround for the 440EPx/GRx
3467 CHIP 11 errata where the last 256 bytes in SDRAM shouldn't 3475 CHIP 11 errata where the last 256 bytes in SDRAM shouldn't
3468 be touched. 3476 be touched.
3469 3477
3470 WARNING: Please make sure that this value is a multiple of 3478 WARNING: Please make sure that this value is a multiple of
3471 the Linux page size (normally 4k). If this is not the case, 3479 the Linux page size (normally 4k). If this is not the case,
3472 then the end address of the Linux memory will be located at a 3480 then the end address of the Linux memory will be located at a
3473 non page size aligned address and this could cause major 3481 non page size aligned address and this could cause major
3474 problems. 3482 problems.
3475 3483
3476 - CONFIG_SYS_LOADS_BAUD_CHANGE: 3484 - CONFIG_SYS_LOADS_BAUD_CHANGE:
3477 Enable temporary baudrate change while serial download 3485 Enable temporary baudrate change while serial download
3478 3486
3479 - CONFIG_SYS_SDRAM_BASE: 3487 - CONFIG_SYS_SDRAM_BASE:
3480 Physical start address of SDRAM. _Must_ be 0 here. 3488 Physical start address of SDRAM. _Must_ be 0 here.
3481 3489
3482 - CONFIG_SYS_MBIO_BASE: 3490 - CONFIG_SYS_MBIO_BASE:
3483 Physical start address of Motherboard I/O (if using a 3491 Physical start address of Motherboard I/O (if using a
3484 Cogent motherboard) 3492 Cogent motherboard)
3485 3493
3486 - CONFIG_SYS_FLASH_BASE: 3494 - CONFIG_SYS_FLASH_BASE:
3487 Physical start address of Flash memory. 3495 Physical start address of Flash memory.
3488 3496
3489 - CONFIG_SYS_MONITOR_BASE: 3497 - CONFIG_SYS_MONITOR_BASE:
3490 Physical start address of boot monitor code (set by 3498 Physical start address of boot monitor code (set by
3491 make config files to be same as the text base address 3499 make config files to be same as the text base address
3492 (CONFIG_SYS_TEXT_BASE) used when linking) - same as 3500 (CONFIG_SYS_TEXT_BASE) used when linking) - same as
3493 CONFIG_SYS_FLASH_BASE when booting from flash. 3501 CONFIG_SYS_FLASH_BASE when booting from flash.
3494 3502
3495 - CONFIG_SYS_MONITOR_LEN: 3503 - CONFIG_SYS_MONITOR_LEN:
3496 Size of memory reserved for monitor code, used to 3504 Size of memory reserved for monitor code, used to
3497 determine _at_compile_time_ (!) if the environment is 3505 determine _at_compile_time_ (!) if the environment is
3498 embedded within the U-Boot image, or in a separate 3506 embedded within the U-Boot image, or in a separate
3499 flash sector. 3507 flash sector.
3500 3508
3501 - CONFIG_SYS_MALLOC_LEN: 3509 - CONFIG_SYS_MALLOC_LEN:
3502 Size of DRAM reserved for malloc() use. 3510 Size of DRAM reserved for malloc() use.
3503 3511
3504 - CONFIG_SYS_BOOTM_LEN: 3512 - CONFIG_SYS_BOOTM_LEN:
3505 Normally compressed uImages are limited to an 3513 Normally compressed uImages are limited to an
3506 uncompressed size of 8 MBytes. If this is not enough, 3514 uncompressed size of 8 MBytes. If this is not enough,
3507 you can define CONFIG_SYS_BOOTM_LEN in your board config file 3515 you can define CONFIG_SYS_BOOTM_LEN in your board config file
3508 to adjust this setting to your needs. 3516 to adjust this setting to your needs.
3509 3517
3510 - CONFIG_SYS_BOOTMAPSZ: 3518 - CONFIG_SYS_BOOTMAPSZ:
3511 Maximum size of memory mapped by the startup code of 3519 Maximum size of memory mapped by the startup code of
3512 the Linux kernel; all data that must be processed by 3520 the Linux kernel; all data that must be processed by
3513 the Linux kernel (bd_info, boot arguments, FDT blob if 3521 the Linux kernel (bd_info, boot arguments, FDT blob if
3514 used) must be put below this limit, unless "bootm_low" 3522 used) must be put below this limit, unless "bootm_low"
3515 environment variable is defined and non-zero. In such case 3523 environment variable is defined and non-zero. In such case
3516 all data for the Linux kernel must be between "bootm_low" 3524 all data for the Linux kernel must be between "bootm_low"
3517 and "bootm_low" + CONFIG_SYS_BOOTMAPSZ. The environment 3525 and "bootm_low" + CONFIG_SYS_BOOTMAPSZ. The environment
3518 variable "bootm_mapsize" will override the value of 3526 variable "bootm_mapsize" will override the value of
3519 CONFIG_SYS_BOOTMAPSZ. If CONFIG_SYS_BOOTMAPSZ is undefined, 3527 CONFIG_SYS_BOOTMAPSZ. If CONFIG_SYS_BOOTMAPSZ is undefined,
3520 then the value in "bootm_size" will be used instead. 3528 then the value in "bootm_size" will be used instead.
3521 3529
3522 - CONFIG_SYS_BOOT_RAMDISK_HIGH: 3530 - CONFIG_SYS_BOOT_RAMDISK_HIGH:
3523 Enable initrd_high functionality. If defined then the 3531 Enable initrd_high functionality. If defined then the
3524 initrd_high feature is enabled and the bootm ramdisk subcommand 3532 initrd_high feature is enabled and the bootm ramdisk subcommand
3525 is enabled. 3533 is enabled.
3526 3534
3527 - CONFIG_SYS_BOOT_GET_CMDLINE: 3535 - CONFIG_SYS_BOOT_GET_CMDLINE:
3528 Enables allocating and saving kernel cmdline in space between 3536 Enables allocating and saving kernel cmdline in space between
3529 "bootm_low" and "bootm_low" + BOOTMAPSZ. 3537 "bootm_low" and "bootm_low" + BOOTMAPSZ.
3530 3538
3531 - CONFIG_SYS_BOOT_GET_KBD: 3539 - CONFIG_SYS_BOOT_GET_KBD:
3532 Enables allocating and saving a kernel copy of the bd_info in 3540 Enables allocating and saving a kernel copy of the bd_info in
3533 space between "bootm_low" and "bootm_low" + BOOTMAPSZ. 3541 space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
3534 3542
3535 - CONFIG_SYS_MAX_FLASH_BANKS: 3543 - CONFIG_SYS_MAX_FLASH_BANKS:
3536 Max number of Flash memory banks 3544 Max number of Flash memory banks
3537 3545
3538 - CONFIG_SYS_MAX_FLASH_SECT: 3546 - CONFIG_SYS_MAX_FLASH_SECT:
3539 Max number of sectors on a Flash chip 3547 Max number of sectors on a Flash chip
3540 3548
3541 - CONFIG_SYS_FLASH_ERASE_TOUT: 3549 - CONFIG_SYS_FLASH_ERASE_TOUT:
3542 Timeout for Flash erase operations (in ms) 3550 Timeout for Flash erase operations (in ms)
3543 3551
3544 - CONFIG_SYS_FLASH_WRITE_TOUT: 3552 - CONFIG_SYS_FLASH_WRITE_TOUT:
3545 Timeout for Flash write operations (in ms) 3553 Timeout for Flash write operations (in ms)
3546 3554
3547 - CONFIG_SYS_FLASH_LOCK_TOUT 3555 - CONFIG_SYS_FLASH_LOCK_TOUT
3548 Timeout for Flash set sector lock bit operation (in ms) 3556 Timeout for Flash set sector lock bit operation (in ms)
3549 3557
3550 - CONFIG_SYS_FLASH_UNLOCK_TOUT 3558 - CONFIG_SYS_FLASH_UNLOCK_TOUT
3551 Timeout for Flash clear lock bits operation (in ms) 3559 Timeout for Flash clear lock bits operation (in ms)
3552 3560
3553 - CONFIG_SYS_FLASH_PROTECTION 3561 - CONFIG_SYS_FLASH_PROTECTION
3554 If defined, hardware flash sectors protection is used 3562 If defined, hardware flash sectors protection is used
3555 instead of U-Boot software protection. 3563 instead of U-Boot software protection.
3556 3564
3557 - CONFIG_SYS_DIRECT_FLASH_TFTP: 3565 - CONFIG_SYS_DIRECT_FLASH_TFTP:
3558 3566
3559 Enable TFTP transfers directly to flash memory; 3567 Enable TFTP transfers directly to flash memory;
3560 without this option such a download has to be 3568 without this option such a download has to be
3561 performed in two steps: (1) download to RAM, and (2) 3569 performed in two steps: (1) download to RAM, and (2)
3562 copy from RAM to flash. 3570 copy from RAM to flash.
3563 3571
3564 The two-step approach is usually more reliable, since 3572 The two-step approach is usually more reliable, since
3565 you can check if the download worked before you erase 3573 you can check if the download worked before you erase
3566 the flash, but in some situations (when system RAM is 3574 the flash, but in some situations (when system RAM is
3567 too limited to allow for a temporary copy of the 3575 too limited to allow for a temporary copy of the
3568 downloaded image) this option may be very useful. 3576 downloaded image) this option may be very useful.
3569 3577
3570 - CONFIG_SYS_FLASH_CFI: 3578 - CONFIG_SYS_FLASH_CFI:
3571 Define if the flash driver uses extra elements in the 3579 Define if the flash driver uses extra elements in the
3572 common flash structure for storing flash geometry. 3580 common flash structure for storing flash geometry.
3573 3581
3574 - CONFIG_FLASH_CFI_DRIVER 3582 - CONFIG_FLASH_CFI_DRIVER
3575 This option also enables the building of the cfi_flash driver 3583 This option also enables the building of the cfi_flash driver
3576 in the drivers directory 3584 in the drivers directory
3577 3585
3578 - CONFIG_FLASH_CFI_MTD 3586 - CONFIG_FLASH_CFI_MTD
3579 This option enables the building of the cfi_mtd driver 3587 This option enables the building of the cfi_mtd driver
3580 in the drivers directory. The driver exports CFI flash 3588 in the drivers directory. The driver exports CFI flash
3581 to the MTD layer. 3589 to the MTD layer.
3582 3590
3583 - CONFIG_SYS_FLASH_USE_BUFFER_WRITE 3591 - CONFIG_SYS_FLASH_USE_BUFFER_WRITE
3584 Use buffered writes to flash. 3592 Use buffered writes to flash.
3585 3593
3586 - CONFIG_FLASH_SPANSION_S29WS_N 3594 - CONFIG_FLASH_SPANSION_S29WS_N
3587 s29ws-n MirrorBit flash has non-standard addresses for buffered 3595 s29ws-n MirrorBit flash has non-standard addresses for buffered
3588 write commands. 3596 write commands.
3589 3597
3590 - CONFIG_SYS_FLASH_QUIET_TEST 3598 - CONFIG_SYS_FLASH_QUIET_TEST
3591 If this option is defined, the common CFI flash doesn't 3599 If this option is defined, the common CFI flash doesn't
3592 print it's warning upon not recognized FLASH banks. This 3600 print it's warning upon not recognized FLASH banks. This
3593 is useful, if some of the configured banks are only 3601 is useful, if some of the configured banks are only
3594 optionally available. 3602 optionally available.
3595 3603
3596 - CONFIG_FLASH_SHOW_PROGRESS 3604 - CONFIG_FLASH_SHOW_PROGRESS
3597 If defined (must be an integer), print out countdown 3605 If defined (must be an integer), print out countdown
3598 digits and dots. Recommended value: 45 (9..1) for 80 3606 digits and dots. Recommended value: 45 (9..1) for 80
3599 column displays, 15 (3..1) for 40 column displays. 3607 column displays, 15 (3..1) for 40 column displays.
3600 3608
3601 - CONFIG_FLASH_VERIFY 3609 - CONFIG_FLASH_VERIFY
3602 If defined, the content of the flash (destination) is compared 3610 If defined, the content of the flash (destination) is compared
3603 against the source after the write operation. An error message 3611 against the source after the write operation. An error message
3604 will be printed when the contents are not identical. 3612 will be printed when the contents are not identical.
3605 Please note that this option is useless in nearly all cases, 3613 Please note that this option is useless in nearly all cases,
3606 since such flash programming errors usually are detected earlier 3614 since such flash programming errors usually are detected earlier
3607 while unprotecting/erasing/programming. Please only enable 3615 while unprotecting/erasing/programming. Please only enable
3608 this option if you really know what you are doing. 3616 this option if you really know what you are doing.
3609 3617
3610 - CONFIG_SYS_RX_ETH_BUFFER: 3618 - CONFIG_SYS_RX_ETH_BUFFER:
3611 Defines the number of Ethernet receive buffers. On some 3619 Defines the number of Ethernet receive buffers. On some
3612 Ethernet controllers it is recommended to set this value 3620 Ethernet controllers it is recommended to set this value
3613 to 8 or even higher (EEPRO100 or 405 EMAC), since all 3621 to 8 or even higher (EEPRO100 or 405 EMAC), since all
3614 buffers can be full shortly after enabling the interface 3622 buffers can be full shortly after enabling the interface
3615 on high Ethernet traffic. 3623 on high Ethernet traffic.
3616 Defaults to 4 if not defined. 3624 Defaults to 4 if not defined.
3617 3625
3618 - CONFIG_ENV_MAX_ENTRIES 3626 - CONFIG_ENV_MAX_ENTRIES
3619 3627
3620 Maximum number of entries in the hash table that is used 3628 Maximum number of entries in the hash table that is used
3621 internally to store the environment settings. The default 3629 internally to store the environment settings. The default
3622 setting is supposed to be generous and should work in most 3630 setting is supposed to be generous and should work in most
3623 cases. This setting can be used to tune behaviour; see 3631 cases. This setting can be used to tune behaviour; see
3624 lib/hashtable.c for details. 3632 lib/hashtable.c for details.
3625 3633
3626 - CONFIG_ENV_FLAGS_LIST_DEFAULT 3634 - CONFIG_ENV_FLAGS_LIST_DEFAULT
3627 - CONFIG_ENV_FLAGS_LIST_STATIC 3635 - CONFIG_ENV_FLAGS_LIST_STATIC
3628 Enable validation of the values given to environment variables when 3636 Enable validation of the values given to environment variables when
3629 calling env set. Variables can be restricted to only decimal, 3637 calling env set. Variables can be restricted to only decimal,
3630 hexadecimal, or boolean. If CONFIG_CMD_NET is also defined, 3638 hexadecimal, or boolean. If CONFIG_CMD_NET is also defined,
3631 the variables can also be restricted to IP address or MAC address. 3639 the variables can also be restricted to IP address or MAC address.
3632 3640
3633 The format of the list is: 3641 The format of the list is:
3634 type_attribute = [s|d|x|b|i|m] 3642 type_attribute = [s|d|x|b|i|m]
3635 access_atribute = [a|r|o|c] 3643 access_atribute = [a|r|o|c]
3636 attributes = type_attribute[access_atribute] 3644 attributes = type_attribute[access_atribute]
3637 entry = variable_name[:attributes] 3645 entry = variable_name[:attributes]
3638 list = entry[,list] 3646 list = entry[,list]
3639 3647
3640 The type attributes are: 3648 The type attributes are:
3641 s - String (default) 3649 s - String (default)
3642 d - Decimal 3650 d - Decimal
3643 x - Hexadecimal 3651 x - Hexadecimal
3644 b - Boolean ([1yYtT|0nNfF]) 3652 b - Boolean ([1yYtT|0nNfF])
3645 i - IP address 3653 i - IP address
3646 m - MAC address 3654 m - MAC address
3647 3655
3648 The access attributes are: 3656 The access attributes are:
3649 a - Any (default) 3657 a - Any (default)
3650 r - Read-only 3658 r - Read-only
3651 o - Write-once 3659 o - Write-once
3652 c - Change-default 3660 c - Change-default
3653 3661
3654 - CONFIG_ENV_FLAGS_LIST_DEFAULT 3662 - CONFIG_ENV_FLAGS_LIST_DEFAULT
3655 Define this to a list (string) to define the ".flags" 3663 Define this to a list (string) to define the ".flags"
3656 envirnoment variable in the default or embedded environment. 3664 envirnoment variable in the default or embedded environment.
3657 3665
3658 - CONFIG_ENV_FLAGS_LIST_STATIC 3666 - CONFIG_ENV_FLAGS_LIST_STATIC
3659 Define this to a list (string) to define validation that 3667 Define this to a list (string) to define validation that
3660 should be done if an entry is not found in the ".flags" 3668 should be done if an entry is not found in the ".flags"
3661 environment variable. To override a setting in the static 3669 environment variable. To override a setting in the static
3662 list, simply add an entry for the same variable name to the 3670 list, simply add an entry for the same variable name to the
3663 ".flags" variable. 3671 ".flags" variable.
3664 3672
3665 - CONFIG_ENV_ACCESS_IGNORE_FORCE 3673 - CONFIG_ENV_ACCESS_IGNORE_FORCE
3666 If defined, don't allow the -f switch to env set override variable 3674 If defined, don't allow the -f switch to env set override variable
3667 access flags. 3675 access flags.
3668 3676
3669 - CONFIG_SYS_GENERIC_BOARD 3677 - CONFIG_SYS_GENERIC_BOARD
3670 This selects the architecture-generic board system instead of the 3678 This selects the architecture-generic board system instead of the
3671 architecture-specific board files. It is intended to move boards 3679 architecture-specific board files. It is intended to move boards
3672 to this new framework over time. Defining this will disable the 3680 to this new framework over time. Defining this will disable the
3673 arch/foo/lib/board.c file and use common/board_f.c and 3681 arch/foo/lib/board.c file and use common/board_f.c and
3674 common/board_r.c instead. To use this option your architecture 3682 common/board_r.c instead. To use this option your architecture
3675 must support it (i.e. must define __HAVE_ARCH_GENERIC_BOARD in 3683 must support it (i.e. must define __HAVE_ARCH_GENERIC_BOARD in
3676 its config.mk file). If you find problems enabling this option on 3684 its config.mk file). If you find problems enabling this option on
3677 your board please report the problem and send patches! 3685 your board please report the problem and send patches!
3678 3686
3679 - CONFIG_SYS_SYM_OFFSETS 3687 - CONFIG_SYS_SYM_OFFSETS
3680 This is set by architectures that use offsets for link symbols 3688 This is set by architectures that use offsets for link symbols
3681 instead of absolute values. So bss_start is obtained using an 3689 instead of absolute values. So bss_start is obtained using an
3682 offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than 3690 offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than
3683 directly. You should not need to touch this setting. 3691 directly. You should not need to touch this setting.
3684 3692
3685 - CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only) 3693 - CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
3686 This is set by OMAP boards for the max time that reset should 3694 This is set by OMAP boards for the max time that reset should
3687 be asserted. See doc/README.omap-reset-time for details on how 3695 be asserted. See doc/README.omap-reset-time for details on how
3688 the value can be calulated on a given board. 3696 the value can be calulated on a given board.
3689 3697
3690 The following definitions that deal with the placement and management 3698 The following definitions that deal with the placement and management
3691 of environment data (variable area); in general, we support the 3699 of environment data (variable area); in general, we support the
3692 following configurations: 3700 following configurations:
3693 3701
3694 - CONFIG_BUILD_ENVCRC: 3702 - CONFIG_BUILD_ENVCRC:
3695 3703
3696 Builds up envcrc with the target environment so that external utils 3704 Builds up envcrc with the target environment so that external utils
3697 may easily extract it and embed it in final U-Boot images. 3705 may easily extract it and embed it in final U-Boot images.
3698 3706
3699 - CONFIG_ENV_IS_IN_FLASH: 3707 - CONFIG_ENV_IS_IN_FLASH:
3700 3708
3701 Define this if the environment is in flash memory. 3709 Define this if the environment is in flash memory.
3702 3710
3703 a) The environment occupies one whole flash sector, which is 3711 a) The environment occupies one whole flash sector, which is
3704 "embedded" in the text segment with the U-Boot code. This 3712 "embedded" in the text segment with the U-Boot code. This
3705 happens usually with "bottom boot sector" or "top boot 3713 happens usually with "bottom boot sector" or "top boot
3706 sector" type flash chips, which have several smaller 3714 sector" type flash chips, which have several smaller
3707 sectors at the start or the end. For instance, such a 3715 sectors at the start or the end. For instance, such a
3708 layout can have sector sizes of 8, 2x4, 16, Nx32 kB. In 3716 layout can have sector sizes of 8, 2x4, 16, Nx32 kB. In
3709 such a case you would place the environment in one of the 3717 such a case you would place the environment in one of the
3710 4 kB sectors - with U-Boot code before and after it. With 3718 4 kB sectors - with U-Boot code before and after it. With
3711 "top boot sector" type flash chips, you would put the 3719 "top boot sector" type flash chips, you would put the
3712 environment in one of the last sectors, leaving a gap 3720 environment in one of the last sectors, leaving a gap
3713 between U-Boot and the environment. 3721 between U-Boot and the environment.
3714 3722
3715 - CONFIG_ENV_OFFSET: 3723 - CONFIG_ENV_OFFSET:
3716 3724
3717 Offset of environment data (variable area) to the 3725 Offset of environment data (variable area) to the
3718 beginning of flash memory; for instance, with bottom boot 3726 beginning of flash memory; for instance, with bottom boot
3719 type flash chips the second sector can be used: the offset 3727 type flash chips the second sector can be used: the offset
3720 for this sector is given here. 3728 for this sector is given here.
3721 3729
3722 CONFIG_ENV_OFFSET is used relative to CONFIG_SYS_FLASH_BASE. 3730 CONFIG_ENV_OFFSET is used relative to CONFIG_SYS_FLASH_BASE.
3723 3731
3724 - CONFIG_ENV_ADDR: 3732 - CONFIG_ENV_ADDR:
3725 3733
3726 This is just another way to specify the start address of 3734 This is just another way to specify the start address of
3727 the flash sector containing the environment (instead of 3735 the flash sector containing the environment (instead of
3728 CONFIG_ENV_OFFSET). 3736 CONFIG_ENV_OFFSET).
3729 3737
3730 - CONFIG_ENV_SECT_SIZE: 3738 - CONFIG_ENV_SECT_SIZE:
3731 3739
3732 Size of the sector containing the environment. 3740 Size of the sector containing the environment.
3733 3741
3734 3742
3735 b) Sometimes flash chips have few, equal sized, BIG sectors. 3743 b) Sometimes flash chips have few, equal sized, BIG sectors.
3736 In such a case you don't want to spend a whole sector for 3744 In such a case you don't want to spend a whole sector for
3737 the environment. 3745 the environment.
3738 3746
3739 - CONFIG_ENV_SIZE: 3747 - CONFIG_ENV_SIZE:
3740 3748
3741 If you use this in combination with CONFIG_ENV_IS_IN_FLASH 3749 If you use this in combination with CONFIG_ENV_IS_IN_FLASH
3742 and CONFIG_ENV_SECT_SIZE, you can specify to use only a part 3750 and CONFIG_ENV_SECT_SIZE, you can specify to use only a part
3743 of this flash sector for the environment. This saves 3751 of this flash sector for the environment. This saves
3744 memory for the RAM copy of the environment. 3752 memory for the RAM copy of the environment.
3745 3753
3746 It may also save flash memory if you decide to use this 3754 It may also save flash memory if you decide to use this
3747 when your environment is "embedded" within U-Boot code, 3755 when your environment is "embedded" within U-Boot code,
3748 since then the remainder of the flash sector could be used 3756 since then the remainder of the flash sector could be used
3749 for U-Boot code. It should be pointed out that this is 3757 for U-Boot code. It should be pointed out that this is
3750 STRONGLY DISCOURAGED from a robustness point of view: 3758 STRONGLY DISCOURAGED from a robustness point of view:
3751 updating the environment in flash makes it always 3759 updating the environment in flash makes it always
3752 necessary to erase the WHOLE sector. If something goes 3760 necessary to erase the WHOLE sector. If something goes
3753 wrong before the contents has been restored from a copy in 3761 wrong before the contents has been restored from a copy in
3754 RAM, your target system will be dead. 3762 RAM, your target system will be dead.
3755 3763
3756 - CONFIG_ENV_ADDR_REDUND 3764 - CONFIG_ENV_ADDR_REDUND
3757 CONFIG_ENV_SIZE_REDUND 3765 CONFIG_ENV_SIZE_REDUND
3758 3766
3759 These settings describe a second storage area used to hold 3767 These settings describe a second storage area used to hold
3760 a redundant copy of the environment data, so that there is 3768 a redundant copy of the environment data, so that there is
3761 a valid backup copy in case there is a power failure during 3769 a valid backup copy in case there is a power failure during
3762 a "saveenv" operation. 3770 a "saveenv" operation.
3763 3771
3764 BE CAREFUL! Any changes to the flash layout, and some changes to the 3772 BE CAREFUL! Any changes to the flash layout, and some changes to the
3765 source code will make it necessary to adapt <board>/u-boot.lds* 3773 source code will make it necessary to adapt <board>/u-boot.lds*
3766 accordingly! 3774 accordingly!
3767 3775
3768 3776
3769 - CONFIG_ENV_IS_IN_NVRAM: 3777 - CONFIG_ENV_IS_IN_NVRAM:
3770 3778
3771 Define this if you have some non-volatile memory device 3779 Define this if you have some non-volatile memory device
3772 (NVRAM, battery buffered SRAM) which you want to use for the 3780 (NVRAM, battery buffered SRAM) which you want to use for the
3773 environment. 3781 environment.
3774 3782
3775 - CONFIG_ENV_ADDR: 3783 - CONFIG_ENV_ADDR:
3776 - CONFIG_ENV_SIZE: 3784 - CONFIG_ENV_SIZE:
3777 3785
3778 These two #defines are used to determine the memory area you 3786 These two #defines are used to determine the memory area you
3779 want to use for environment. It is assumed that this memory 3787 want to use for environment. It is assumed that this memory
3780 can just be read and written to, without any special 3788 can just be read and written to, without any special
3781 provision. 3789 provision.
3782 3790
3783 BE CAREFUL! The first access to the environment happens quite early 3791 BE CAREFUL! The first access to the environment happens quite early
3784 in U-Boot initalization (when we try to get the setting of for the 3792 in U-Boot initalization (when we try to get the setting of for the
3785 console baudrate). You *MUST* have mapped your NVRAM area then, or 3793 console baudrate). You *MUST* have mapped your NVRAM area then, or
3786 U-Boot will hang. 3794 U-Boot will hang.
3787 3795
3788 Please note that even with NVRAM we still use a copy of the 3796 Please note that even with NVRAM we still use a copy of the
3789 environment in RAM: we could work on NVRAM directly, but we want to 3797 environment in RAM: we could work on NVRAM directly, but we want to
3790 keep settings there always unmodified except somebody uses "saveenv" 3798 keep settings there always unmodified except somebody uses "saveenv"
3791 to save the current settings. 3799 to save the current settings.
3792 3800
3793 3801
3794 - CONFIG_ENV_IS_IN_EEPROM: 3802 - CONFIG_ENV_IS_IN_EEPROM:
3795 3803
3796 Use this if you have an EEPROM or similar serial access 3804 Use this if you have an EEPROM or similar serial access
3797 device and a driver for it. 3805 device and a driver for it.
3798 3806
3799 - CONFIG_ENV_OFFSET: 3807 - CONFIG_ENV_OFFSET:
3800 - CONFIG_ENV_SIZE: 3808 - CONFIG_ENV_SIZE:
3801 3809
3802 These two #defines specify the offset and size of the 3810 These two #defines specify the offset and size of the
3803 environment area within the total memory of your EEPROM. 3811 environment area within the total memory of your EEPROM.
3804 3812
3805 - CONFIG_SYS_I2C_EEPROM_ADDR: 3813 - CONFIG_SYS_I2C_EEPROM_ADDR:
3806 If defined, specified the chip address of the EEPROM device. 3814 If defined, specified the chip address of the EEPROM device.
3807 The default address is zero. 3815 The default address is zero.
3808 3816
3809 - CONFIG_SYS_EEPROM_PAGE_WRITE_BITS: 3817 - CONFIG_SYS_EEPROM_PAGE_WRITE_BITS:
3810 If defined, the number of bits used to address bytes in a 3818 If defined, the number of bits used to address bytes in a
3811 single page in the EEPROM device. A 64 byte page, for example 3819 single page in the EEPROM device. A 64 byte page, for example
3812 would require six bits. 3820 would require six bits.
3813 3821
3814 - CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS: 3822 - CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS:
3815 If defined, the number of milliseconds to delay between 3823 If defined, the number of milliseconds to delay between
3816 page writes. The default is zero milliseconds. 3824 page writes. The default is zero milliseconds.
3817 3825
3818 - CONFIG_SYS_I2C_EEPROM_ADDR_LEN: 3826 - CONFIG_SYS_I2C_EEPROM_ADDR_LEN:
3819 The length in bytes of the EEPROM memory array address. Note 3827 The length in bytes of the EEPROM memory array address. Note
3820 that this is NOT the chip address length! 3828 that this is NOT the chip address length!
3821 3829
3822 - CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW: 3830 - CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW:
3823 EEPROM chips that implement "address overflow" are ones 3831 EEPROM chips that implement "address overflow" are ones
3824 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 3832 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
3825 address and the extra bits end up in the "chip address" bit 3833 address and the extra bits end up in the "chip address" bit
3826 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 3834 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
3827 byte chips. 3835 byte chips.
3828 3836
3829 Note that we consider the length of the address field to 3837 Note that we consider the length of the address field to
3830 still be one byte because the extra address bits are hidden 3838 still be one byte because the extra address bits are hidden
3831 in the chip address. 3839 in the chip address.
3832 3840
3833 - CONFIG_SYS_EEPROM_SIZE: 3841 - CONFIG_SYS_EEPROM_SIZE:
3834 The size in bytes of the EEPROM device. 3842 The size in bytes of the EEPROM device.
3835 3843
3836 - CONFIG_ENV_EEPROM_IS_ON_I2C 3844 - CONFIG_ENV_EEPROM_IS_ON_I2C
3837 define this, if you have I2C and SPI activated, and your 3845 define this, if you have I2C and SPI activated, and your
3838 EEPROM, which holds the environment, is on the I2C bus. 3846 EEPROM, which holds the environment, is on the I2C bus.
3839 3847
3840 - CONFIG_I2C_ENV_EEPROM_BUS 3848 - CONFIG_I2C_ENV_EEPROM_BUS
3841 if you have an Environment on an EEPROM reached over 3849 if you have an Environment on an EEPROM reached over
3842 I2C muxes, you can define here, how to reach this 3850 I2C muxes, you can define here, how to reach this
3843 EEPROM. For example: 3851 EEPROM. For example:
3844 3852
3845 #define CONFIG_I2C_ENV_EEPROM_BUS 1 3853 #define CONFIG_I2C_ENV_EEPROM_BUS 1
3846 3854
3847 EEPROM which holds the environment, is reached over 3855 EEPROM which holds the environment, is reached over
3848 a pca9547 i2c mux with address 0x70, channel 3. 3856 a pca9547 i2c mux with address 0x70, channel 3.
3849 3857
3850 - CONFIG_ENV_IS_IN_DATAFLASH: 3858 - CONFIG_ENV_IS_IN_DATAFLASH:
3851 3859
3852 Define this if you have a DataFlash memory device which you 3860 Define this if you have a DataFlash memory device which you
3853 want to use for the environment. 3861 want to use for the environment.
3854 3862
3855 - CONFIG_ENV_OFFSET: 3863 - CONFIG_ENV_OFFSET:
3856 - CONFIG_ENV_ADDR: 3864 - CONFIG_ENV_ADDR:
3857 - CONFIG_ENV_SIZE: 3865 - CONFIG_ENV_SIZE:
3858 3866
3859 These three #defines specify the offset and size of the 3867 These three #defines specify the offset and size of the
3860 environment area within the total memory of your DataFlash placed 3868 environment area within the total memory of your DataFlash placed
3861 at the specified address. 3869 at the specified address.
3862 3870
3863 - CONFIG_ENV_IS_IN_REMOTE: 3871 - CONFIG_ENV_IS_IN_REMOTE:
3864 3872
3865 Define this if you have a remote memory space which you 3873 Define this if you have a remote memory space which you
3866 want to use for the local device's environment. 3874 want to use for the local device's environment.
3867 3875
3868 - CONFIG_ENV_ADDR: 3876 - CONFIG_ENV_ADDR:
3869 - CONFIG_ENV_SIZE: 3877 - CONFIG_ENV_SIZE:
3870 3878
3871 These two #defines specify the address and size of the 3879 These two #defines specify the address and size of the
3872 environment area within the remote memory space. The 3880 environment area within the remote memory space. The
3873 local device can get the environment from remote memory 3881 local device can get the environment from remote memory
3874 space by SRIO or PCIE links. 3882 space by SRIO or PCIE links.
3875 3883
3876 BE CAREFUL! For some special cases, the local device can not use 3884 BE CAREFUL! For some special cases, the local device can not use
3877 "saveenv" command. For example, the local device will get the 3885 "saveenv" command. For example, the local device will get the
3878 environment stored in a remote NOR flash by SRIO or PCIE link, 3886 environment stored in a remote NOR flash by SRIO or PCIE link,
3879 but it can not erase, write this NOR flash by SRIO or PCIE interface. 3887 but it can not erase, write this NOR flash by SRIO or PCIE interface.
3880 3888
3881 - CONFIG_ENV_IS_IN_NAND: 3889 - CONFIG_ENV_IS_IN_NAND:
3882 3890
3883 Define this if you have a NAND device which you want to use 3891 Define this if you have a NAND device which you want to use
3884 for the environment. 3892 for the environment.
3885 3893
3886 - CONFIG_ENV_OFFSET: 3894 - CONFIG_ENV_OFFSET:
3887 - CONFIG_ENV_SIZE: 3895 - CONFIG_ENV_SIZE:
3888 3896
3889 These two #defines specify the offset and size of the environment 3897 These two #defines specify the offset and size of the environment
3890 area within the first NAND device. CONFIG_ENV_OFFSET must be 3898 area within the first NAND device. CONFIG_ENV_OFFSET must be
3891 aligned to an erase block boundary. 3899 aligned to an erase block boundary.
3892 3900
3893 - CONFIG_ENV_OFFSET_REDUND (optional): 3901 - CONFIG_ENV_OFFSET_REDUND (optional):
3894 3902
3895 This setting describes a second storage area of CONFIG_ENV_SIZE 3903 This setting describes a second storage area of CONFIG_ENV_SIZE
3896 size used to hold a redundant copy of the environment data, so 3904 size used to hold a redundant copy of the environment data, so
3897 that there is a valid backup copy in case there is a power failure 3905 that there is a valid backup copy in case there is a power failure
3898 during a "saveenv" operation. CONFIG_ENV_OFFSET_RENDUND must be 3906 during a "saveenv" operation. CONFIG_ENV_OFFSET_RENDUND must be
3899 aligned to an erase block boundary. 3907 aligned to an erase block boundary.
3900 3908
3901 - CONFIG_ENV_RANGE (optional): 3909 - CONFIG_ENV_RANGE (optional):
3902 3910
3903 Specifies the length of the region in which the environment 3911 Specifies the length of the region in which the environment
3904 can be written. This should be a multiple of the NAND device's 3912 can be written. This should be a multiple of the NAND device's
3905 block size. Specifying a range with more erase blocks than 3913 block size. Specifying a range with more erase blocks than
3906 are needed to hold CONFIG_ENV_SIZE allows bad blocks within 3914 are needed to hold CONFIG_ENV_SIZE allows bad blocks within
3907 the range to be avoided. 3915 the range to be avoided.
3908 3916
3909 - CONFIG_ENV_OFFSET_OOB (optional): 3917 - CONFIG_ENV_OFFSET_OOB (optional):
3910 3918
3911 Enables support for dynamically retrieving the offset of the 3919 Enables support for dynamically retrieving the offset of the
3912 environment from block zero's out-of-band data. The 3920 environment from block zero's out-of-band data. The
3913 "nand env.oob" command can be used to record this offset. 3921 "nand env.oob" command can be used to record this offset.
3914 Currently, CONFIG_ENV_OFFSET_REDUND is not supported when 3922 Currently, CONFIG_ENV_OFFSET_REDUND is not supported when
3915 using CONFIG_ENV_OFFSET_OOB. 3923 using CONFIG_ENV_OFFSET_OOB.
3916 3924
3917 - CONFIG_NAND_ENV_DST 3925 - CONFIG_NAND_ENV_DST
3918 3926
3919 Defines address in RAM to which the nand_spl code should copy the 3927 Defines address in RAM to which the nand_spl code should copy the
3920 environment. If redundant environment is used, it will be copied to 3928 environment. If redundant environment is used, it will be copied to
3921 CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE. 3929 CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE.
3922 3930
3923 - CONFIG_ENV_IS_IN_UBI: 3931 - CONFIG_ENV_IS_IN_UBI:
3924 3932
3925 Define this if you have an UBI volume that you want to use for the 3933 Define this if you have an UBI volume that you want to use for the
3926 environment. This has the benefit of wear-leveling the environment 3934 environment. This has the benefit of wear-leveling the environment
3927 accesses, which is important on NAND. 3935 accesses, which is important on NAND.
3928 3936
3929 - CONFIG_ENV_UBI_PART: 3937 - CONFIG_ENV_UBI_PART:
3930 3938
3931 Define this to a string that is the mtd partition containing the UBI. 3939 Define this to a string that is the mtd partition containing the UBI.
3932 3940
3933 - CONFIG_ENV_UBI_VOLUME: 3941 - CONFIG_ENV_UBI_VOLUME:
3934 3942
3935 Define this to the name of the volume that you want to store the 3943 Define this to the name of the volume that you want to store the
3936 environment in. 3944 environment in.
3937 3945
3938 - CONFIG_ENV_UBI_VOLUME_REDUND: 3946 - CONFIG_ENV_UBI_VOLUME_REDUND:
3939 3947
3940 Define this to the name of another volume to store a second copy of 3948 Define this to the name of another volume to store a second copy of
3941 the environment in. This will enable redundant environments in UBI. 3949 the environment in. This will enable redundant environments in UBI.
3942 It is assumed that both volumes are in the same MTD partition. 3950 It is assumed that both volumes are in the same MTD partition.
3943 3951
3944 - CONFIG_UBI_SILENCE_MSG 3952 - CONFIG_UBI_SILENCE_MSG
3945 - CONFIG_UBIFS_SILENCE_MSG 3953 - CONFIG_UBIFS_SILENCE_MSG
3946 3954
3947 You will probably want to define these to avoid a really noisy system 3955 You will probably want to define these to avoid a really noisy system
3948 when storing the env in UBI. 3956 when storing the env in UBI.
3949 3957
3950 - CONFIG_ENV_IS_IN_MMC: 3958 - CONFIG_ENV_IS_IN_MMC:
3951 3959
3952 Define this if you have an MMC device which you want to use for the 3960 Define this if you have an MMC device which you want to use for the
3953 environment. 3961 environment.
3954 3962
3955 - CONFIG_SYS_MMC_ENV_DEV: 3963 - CONFIG_SYS_MMC_ENV_DEV:
3956 3964
3957 Specifies which MMC device the environment is stored in. 3965 Specifies which MMC device the environment is stored in.
3958 3966
3959 - CONFIG_SYS_MMC_ENV_PART (optional): 3967 - CONFIG_SYS_MMC_ENV_PART (optional):
3960 3968
3961 Specifies which MMC partition the environment is stored in. If not 3969 Specifies which MMC partition the environment is stored in. If not
3962 set, defaults to partition 0, the user area. Common values might be 3970 set, defaults to partition 0, the user area. Common values might be
3963 1 (first MMC boot partition), 2 (second MMC boot partition). 3971 1 (first MMC boot partition), 2 (second MMC boot partition).
3964 3972
3965 - CONFIG_ENV_OFFSET: 3973 - CONFIG_ENV_OFFSET:
3966 - CONFIG_ENV_SIZE: 3974 - CONFIG_ENV_SIZE:
3967 3975
3968 These two #defines specify the offset and size of the environment 3976 These two #defines specify the offset and size of the environment
3969 area within the specified MMC device. 3977 area within the specified MMC device.
3970 3978
3971 If offset is positive (the usual case), it is treated as relative to 3979 If offset is positive (the usual case), it is treated as relative to
3972 the start of the MMC partition. If offset is negative, it is treated 3980 the start of the MMC partition. If offset is negative, it is treated
3973 as relative to the end of the MMC partition. This can be useful if 3981 as relative to the end of the MMC partition. This can be useful if
3974 your board may be fitted with different MMC devices, which have 3982 your board may be fitted with different MMC devices, which have
3975 different sizes for the MMC partitions, and you always want the 3983 different sizes for the MMC partitions, and you always want the
3976 environment placed at the very end of the partition, to leave the 3984 environment placed at the very end of the partition, to leave the
3977 maximum possible space before it, to store other data. 3985 maximum possible space before it, to store other data.
3978 3986
3979 These two values are in units of bytes, but must be aligned to an 3987 These two values are in units of bytes, but must be aligned to an
3980 MMC sector boundary. 3988 MMC sector boundary.
3981 3989
3982 - CONFIG_ENV_OFFSET_REDUND (optional): 3990 - CONFIG_ENV_OFFSET_REDUND (optional):
3983 3991
3984 Specifies a second storage area, of CONFIG_ENV_SIZE size, used to 3992 Specifies a second storage area, of CONFIG_ENV_SIZE size, used to
3985 hold a redundant copy of the environment data. This provides a 3993 hold a redundant copy of the environment data. This provides a
3986 valid backup copy in case the other copy is corrupted, e.g. due 3994 valid backup copy in case the other copy is corrupted, e.g. due
3987 to a power failure during a "saveenv" operation. 3995 to a power failure during a "saveenv" operation.
3988 3996
3989 This value may also be positive or negative; this is handled in the 3997 This value may also be positive or negative; this is handled in the
3990 same way as CONFIG_ENV_OFFSET. 3998 same way as CONFIG_ENV_OFFSET.
3991 3999
3992 This value is also in units of bytes, but must also be aligned to 4000 This value is also in units of bytes, but must also be aligned to
3993 an MMC sector boundary. 4001 an MMC sector boundary.
3994 4002
3995 - CONFIG_ENV_SIZE_REDUND (optional): 4003 - CONFIG_ENV_SIZE_REDUND (optional):
3996 4004
3997 This value need not be set, even when CONFIG_ENV_OFFSET_REDUND is 4005 This value need not be set, even when CONFIG_ENV_OFFSET_REDUND is
3998 set. If this value is set, it must be set to the same value as 4006 set. If this value is set, it must be set to the same value as
3999 CONFIG_ENV_SIZE. 4007 CONFIG_ENV_SIZE.
4000 4008
4001 - CONFIG_SYS_SPI_INIT_OFFSET 4009 - CONFIG_SYS_SPI_INIT_OFFSET
4002 4010
4003 Defines offset to the initial SPI buffer area in DPRAM. The 4011 Defines offset to the initial SPI buffer area in DPRAM. The
4004 area is used at an early stage (ROM part) if the environment 4012 area is used at an early stage (ROM part) if the environment
4005 is configured to reside in the SPI EEPROM: We need a 520 byte 4013 is configured to reside in the SPI EEPROM: We need a 520 byte
4006 scratch DPRAM area. It is used between the two initialization 4014 scratch DPRAM area. It is used between the two initialization
4007 calls (spi_init_f() and spi_init_r()). A value of 0xB00 seems 4015 calls (spi_init_f() and spi_init_r()). A value of 0xB00 seems
4008 to be a good choice since it makes it far enough from the 4016 to be a good choice since it makes it far enough from the
4009 start of the data area as well as from the stack pointer. 4017 start of the data area as well as from the stack pointer.
4010 4018
4011 Please note that the environment is read-only until the monitor 4019 Please note that the environment is read-only until the monitor
4012 has been relocated to RAM and a RAM copy of the environment has been 4020 has been relocated to RAM and a RAM copy of the environment has been
4013 created; also, when using EEPROM you will have to use getenv_f() 4021 created; also, when using EEPROM you will have to use getenv_f()
4014 until then to read environment variables. 4022 until then to read environment variables.
4015 4023
4016 The environment is protected by a CRC32 checksum. Before the monitor 4024 The environment is protected by a CRC32 checksum. Before the monitor
4017 is relocated into RAM, as a result of a bad CRC you will be working 4025 is relocated into RAM, as a result of a bad CRC you will be working
4018 with the compiled-in default environment - *silently*!!! [This is 4026 with the compiled-in default environment - *silently*!!! [This is
4019 necessary, because the first environment variable we need is the 4027 necessary, because the first environment variable we need is the
4020 "baudrate" setting for the console - if we have a bad CRC, we don't 4028 "baudrate" setting for the console - if we have a bad CRC, we don't
4021 have any device yet where we could complain.] 4029 have any device yet where we could complain.]
4022 4030
4023 Note: once the monitor has been relocated, then it will complain if 4031 Note: once the monitor has been relocated, then it will complain if
4024 the default environment is used; a new CRC is computed as soon as you 4032 the default environment is used; a new CRC is computed as soon as you
4025 use the "saveenv" command to store a valid environment. 4033 use the "saveenv" command to store a valid environment.
4026 4034
4027 - CONFIG_SYS_FAULT_ECHO_LINK_DOWN: 4035 - CONFIG_SYS_FAULT_ECHO_LINK_DOWN:
4028 Echo the inverted Ethernet link state to the fault LED. 4036 Echo the inverted Ethernet link state to the fault LED.
4029 4037
4030 Note: If this option is active, then CONFIG_SYS_FAULT_MII_ADDR 4038 Note: If this option is active, then CONFIG_SYS_FAULT_MII_ADDR
4031 also needs to be defined. 4039 also needs to be defined.
4032 4040
4033 - CONFIG_SYS_FAULT_MII_ADDR: 4041 - CONFIG_SYS_FAULT_MII_ADDR:
4034 MII address of the PHY to check for the Ethernet link state. 4042 MII address of the PHY to check for the Ethernet link state.
4035 4043
4036 - CONFIG_NS16550_MIN_FUNCTIONS: 4044 - CONFIG_NS16550_MIN_FUNCTIONS:
4037 Define this if you desire to only have use of the NS16550_init 4045 Define this if you desire to only have use of the NS16550_init
4038 and NS16550_putc functions for the serial driver located at 4046 and NS16550_putc functions for the serial driver located at
4039 drivers/serial/ns16550.c. This option is useful for saving 4047 drivers/serial/ns16550.c. This option is useful for saving
4040 space for already greatly restricted images, including but not 4048 space for already greatly restricted images, including but not
4041 limited to NAND_SPL configurations. 4049 limited to NAND_SPL configurations.
4042 4050
4043 - CONFIG_DISPLAY_BOARDINFO 4051 - CONFIG_DISPLAY_BOARDINFO
4044 Display information about the board that U-Boot is running on 4052 Display information about the board that U-Boot is running on
4045 when U-Boot starts up. The board function checkboard() is called 4053 when U-Boot starts up. The board function checkboard() is called
4046 to do this. 4054 to do this.
4047 4055
4048 - CONFIG_DISPLAY_BOARDINFO_LATE 4056 - CONFIG_DISPLAY_BOARDINFO_LATE
4049 Similar to the previous option, but display this information 4057 Similar to the previous option, but display this information
4050 later, once stdio is running and output goes to the LCD, if 4058 later, once stdio is running and output goes to the LCD, if
4051 present. 4059 present.
4052 4060
4053 Low Level (hardware related) configuration options: 4061 Low Level (hardware related) configuration options:
4054 --------------------------------------------------- 4062 ---------------------------------------------------
4055 4063
4056 - CONFIG_SYS_CACHELINE_SIZE: 4064 - CONFIG_SYS_CACHELINE_SIZE:
4057 Cache Line Size of the CPU. 4065 Cache Line Size of the CPU.
4058 4066
4059 - CONFIG_SYS_DEFAULT_IMMR: 4067 - CONFIG_SYS_DEFAULT_IMMR:
4060 Default address of the IMMR after system reset. 4068 Default address of the IMMR after system reset.
4061 4069
4062 Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU, 4070 Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
4063 and RPXsuper) to be able to adjust the position of 4071 and RPXsuper) to be able to adjust the position of
4064 the IMMR register after a reset. 4072 the IMMR register after a reset.
4065 4073
4066 - CONFIG_SYS_CCSRBAR_DEFAULT: 4074 - CONFIG_SYS_CCSRBAR_DEFAULT:
4067 Default (power-on reset) physical address of CCSR on Freescale 4075 Default (power-on reset) physical address of CCSR on Freescale
4068 PowerPC SOCs. 4076 PowerPC SOCs.
4069 4077
4070 - CONFIG_SYS_CCSRBAR: 4078 - CONFIG_SYS_CCSRBAR:
4071 Virtual address of CCSR. On a 32-bit build, this is typically 4079 Virtual address of CCSR. On a 32-bit build, this is typically
4072 the same value as CONFIG_SYS_CCSRBAR_DEFAULT. 4080 the same value as CONFIG_SYS_CCSRBAR_DEFAULT.
4073 4081
4074 CONFIG_SYS_DEFAULT_IMMR must also be set to this value, 4082 CONFIG_SYS_DEFAULT_IMMR must also be set to this value,
4075 for cross-platform code that uses that macro instead. 4083 for cross-platform code that uses that macro instead.
4076 4084
4077 - CONFIG_SYS_CCSRBAR_PHYS: 4085 - CONFIG_SYS_CCSRBAR_PHYS:
4078 Physical address of CCSR. CCSR can be relocated to a new 4086 Physical address of CCSR. CCSR can be relocated to a new
4079 physical address, if desired. In this case, this macro should 4087 physical address, if desired. In this case, this macro should
4080 be set to that address. Otherwise, it should be set to the 4088 be set to that address. Otherwise, it should be set to the
4081 same value as CONFIG_SYS_CCSRBAR_DEFAULT. For example, CCSR 4089 same value as CONFIG_SYS_CCSRBAR_DEFAULT. For example, CCSR
4082 is typically relocated on 36-bit builds. It is recommended 4090 is typically relocated on 36-bit builds. It is recommended
4083 that this macro be defined via the _HIGH and _LOW macros: 4091 that this macro be defined via the _HIGH and _LOW macros:
4084 4092
4085 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH 4093 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH
4086 * 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW) 4094 * 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW)
4087 4095
4088 - CONFIG_SYS_CCSRBAR_PHYS_HIGH: 4096 - CONFIG_SYS_CCSRBAR_PHYS_HIGH:
4089 Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS. This value is typically 4097 Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS. This value is typically
4090 either 0 (32-bit build) or 0xF (36-bit build). This macro is 4098 either 0 (32-bit build) or 0xF (36-bit build). This macro is
4091 used in assembly code, so it must not contain typecasts or 4099 used in assembly code, so it must not contain typecasts or
4092 integer size suffixes (e.g. "ULL"). 4100 integer size suffixes (e.g. "ULL").
4093 4101
4094 - CONFIG_SYS_CCSRBAR_PHYS_LOW: 4102 - CONFIG_SYS_CCSRBAR_PHYS_LOW:
4095 Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS. This macro is 4103 Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS. This macro is
4096 used in assembly code, so it must not contain typecasts or 4104 used in assembly code, so it must not contain typecasts or
4097 integer size suffixes (e.g. "ULL"). 4105 integer size suffixes (e.g. "ULL").
4098 4106
4099 - CONFIG_SYS_CCSR_DO_NOT_RELOCATE: 4107 - CONFIG_SYS_CCSR_DO_NOT_RELOCATE:
4100 If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be 4108 If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be
4101 forced to a value that ensures that CCSR is not relocated. 4109 forced to a value that ensures that CCSR is not relocated.
4102 4110
4103 - Floppy Disk Support: 4111 - Floppy Disk Support:
4104 CONFIG_SYS_FDC_DRIVE_NUMBER 4112 CONFIG_SYS_FDC_DRIVE_NUMBER
4105 4113
4106 the default drive number (default value 0) 4114 the default drive number (default value 0)
4107 4115
4108 CONFIG_SYS_ISA_IO_STRIDE 4116 CONFIG_SYS_ISA_IO_STRIDE
4109 4117
4110 defines the spacing between FDC chipset registers 4118 defines the spacing between FDC chipset registers
4111 (default value 1) 4119 (default value 1)
4112 4120
4113 CONFIG_SYS_ISA_IO_OFFSET 4121 CONFIG_SYS_ISA_IO_OFFSET
4114 4122
4115 defines the offset of register from address. It 4123 defines the offset of register from address. It
4116 depends on which part of the data bus is connected to 4124 depends on which part of the data bus is connected to
4117 the FDC chipset. (default value 0) 4125 the FDC chipset. (default value 0)
4118 4126
4119 If CONFIG_SYS_ISA_IO_STRIDE CONFIG_SYS_ISA_IO_OFFSET and 4127 If CONFIG_SYS_ISA_IO_STRIDE CONFIG_SYS_ISA_IO_OFFSET and
4120 CONFIG_SYS_FDC_DRIVE_NUMBER are undefined, they take their 4128 CONFIG_SYS_FDC_DRIVE_NUMBER are undefined, they take their
4121 default value. 4129 default value.
4122 4130
4123 if CONFIG_SYS_FDC_HW_INIT is defined, then the function 4131 if CONFIG_SYS_FDC_HW_INIT is defined, then the function
4124 fdc_hw_init() is called at the beginning of the FDC 4132 fdc_hw_init() is called at the beginning of the FDC
4125 setup. fdc_hw_init() must be provided by the board 4133 setup. fdc_hw_init() must be provided by the board
4126 source code. It is used to make hardware dependant 4134 source code. It is used to make hardware dependant
4127 initializations. 4135 initializations.
4128 4136
4129 - CONFIG_IDE_AHB: 4137 - CONFIG_IDE_AHB:
4130 Most IDE controllers were designed to be connected with PCI 4138 Most IDE controllers were designed to be connected with PCI
4131 interface. Only few of them were designed for AHB interface. 4139 interface. Only few of them were designed for AHB interface.
4132 When software is doing ATA command and data transfer to 4140 When software is doing ATA command and data transfer to
4133 IDE devices through IDE-AHB controller, some additional 4141 IDE devices through IDE-AHB controller, some additional
4134 registers accessing to these kind of IDE-AHB controller 4142 registers accessing to these kind of IDE-AHB controller
4135 is requierd. 4143 is requierd.
4136 4144
4137 - CONFIG_SYS_IMMR: Physical address of the Internal Memory. 4145 - CONFIG_SYS_IMMR: Physical address of the Internal Memory.
4138 DO NOT CHANGE unless you know exactly what you're 4146 DO NOT CHANGE unless you know exactly what you're
4139 doing! (11-4) [MPC8xx/82xx systems only] 4147 doing! (11-4) [MPC8xx/82xx systems only]
4140 4148
4141 - CONFIG_SYS_INIT_RAM_ADDR: 4149 - CONFIG_SYS_INIT_RAM_ADDR:
4142 4150
4143 Start address of memory area that can be used for 4151 Start address of memory area that can be used for
4144 initial data and stack; please note that this must be 4152 initial data and stack; please note that this must be
4145 writable memory that is working WITHOUT special 4153 writable memory that is working WITHOUT special
4146 initialization, i. e. you CANNOT use normal RAM which 4154 initialization, i. e. you CANNOT use normal RAM which
4147 will become available only after programming the 4155 will become available only after programming the
4148 memory controller and running certain initialization 4156 memory controller and running certain initialization
4149 sequences. 4157 sequences.
4150 4158
4151 U-Boot uses the following memory types: 4159 U-Boot uses the following memory types:
4152 - MPC8xx and MPC8260: IMMR (internal memory of the CPU) 4160 - MPC8xx and MPC8260: IMMR (internal memory of the CPU)
4153 - MPC824X: data cache 4161 - MPC824X: data cache
4154 - PPC4xx: data cache 4162 - PPC4xx: data cache
4155 4163
4156 - CONFIG_SYS_GBL_DATA_OFFSET: 4164 - CONFIG_SYS_GBL_DATA_OFFSET:
4157 4165
4158 Offset of the initial data structure in the memory 4166 Offset of the initial data structure in the memory
4159 area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually 4167 area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
4160 CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial 4168 CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
4161 data is located at the end of the available space 4169 data is located at the end of the available space
4162 (sometimes written as (CONFIG_SYS_INIT_RAM_SIZE - 4170 (sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
4163 CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just 4171 CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just
4164 below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR + 4172 below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
4165 CONFIG_SYS_GBL_DATA_OFFSET) downward. 4173 CONFIG_SYS_GBL_DATA_OFFSET) downward.
4166 4174
4167 Note: 4175 Note:
4168 On the MPC824X (or other systems that use the data 4176 On the MPC824X (or other systems that use the data
4169 cache for initial memory) the address chosen for 4177 cache for initial memory) the address chosen for
4170 CONFIG_SYS_INIT_RAM_ADDR is basically arbitrary - it must 4178 CONFIG_SYS_INIT_RAM_ADDR is basically arbitrary - it must
4171 point to an otherwise UNUSED address space between 4179 point to an otherwise UNUSED address space between
4172 the top of RAM and the start of the PCI space. 4180 the top of RAM and the start of the PCI space.
4173 4181
4174 - CONFIG_SYS_SIUMCR: SIU Module Configuration (11-6) 4182 - CONFIG_SYS_SIUMCR: SIU Module Configuration (11-6)
4175 4183
4176 - CONFIG_SYS_SYPCR: System Protection Control (11-9) 4184 - CONFIG_SYS_SYPCR: System Protection Control (11-9)
4177 4185
4178 - CONFIG_SYS_TBSCR: Time Base Status and Control (11-26) 4186 - CONFIG_SYS_TBSCR: Time Base Status and Control (11-26)
4179 4187
4180 - CONFIG_SYS_PISCR: Periodic Interrupt Status and Control (11-31) 4188 - CONFIG_SYS_PISCR: Periodic Interrupt Status and Control (11-31)
4181 4189
4182 - CONFIG_SYS_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30) 4190 - CONFIG_SYS_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30)
4183 4191
4184 - CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27) 4192 - CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)
4185 4193
4186 - CONFIG_SYS_OR_TIMING_SDRAM: 4194 - CONFIG_SYS_OR_TIMING_SDRAM:
4187 SDRAM timing 4195 SDRAM timing
4188 4196
4189 - CONFIG_SYS_MAMR_PTA: 4197 - CONFIG_SYS_MAMR_PTA:
4190 periodic timer for refresh 4198 periodic timer for refresh
4191 4199
4192 - CONFIG_SYS_DER: Debug Event Register (37-47) 4200 - CONFIG_SYS_DER: Debug Event Register (37-47)
4193 4201
4194 - FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM, 4202 - FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
4195 CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP, 4203 CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
4196 CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM, 4204 CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
4197 CONFIG_SYS_BR1_PRELIM: 4205 CONFIG_SYS_BR1_PRELIM:
4198 Memory Controller Definitions: BR0/1 and OR0/1 (FLASH) 4206 Memory Controller Definitions: BR0/1 and OR0/1 (FLASH)
4199 4207
4200 - SDRAM_BASE2_PRELIM, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE, 4208 - SDRAM_BASE2_PRELIM, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE,
4201 CONFIG_SYS_OR_TIMING_SDRAM, CONFIG_SYS_OR2_PRELIM, CONFIG_SYS_BR2_PRELIM, 4209 CONFIG_SYS_OR_TIMING_SDRAM, CONFIG_SYS_OR2_PRELIM, CONFIG_SYS_BR2_PRELIM,
4202 CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM: 4210 CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
4203 Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM) 4211 Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
4204 4212
4205 - CONFIG_SYS_MAMR_PTA, CONFIG_SYS_MPTPR_2BK_4K, CONFIG_SYS_MPTPR_1BK_4K, CONFIG_SYS_MPTPR_2BK_8K, 4213 - CONFIG_SYS_MAMR_PTA, CONFIG_SYS_MPTPR_2BK_4K, CONFIG_SYS_MPTPR_1BK_4K, CONFIG_SYS_MPTPR_2BK_8K,
4206 CONFIG_SYS_MPTPR_1BK_8K, CONFIG_SYS_MAMR_8COL, CONFIG_SYS_MAMR_9COL: 4214 CONFIG_SYS_MPTPR_1BK_8K, CONFIG_SYS_MAMR_8COL, CONFIG_SYS_MAMR_9COL:
4207 Machine Mode Register and Memory Periodic Timer 4215 Machine Mode Register and Memory Periodic Timer
4208 Prescaler definitions (SDRAM timing) 4216 Prescaler definitions (SDRAM timing)
4209 4217
4210 - CONFIG_SYS_I2C_UCODE_PATCH, CONFIG_SYS_I2C_DPMEM_OFFSET [0x1FC0]: 4218 - CONFIG_SYS_I2C_UCODE_PATCH, CONFIG_SYS_I2C_DPMEM_OFFSET [0x1FC0]:
4211 enable I2C microcode relocation patch (MPC8xx); 4219 enable I2C microcode relocation patch (MPC8xx);
4212 define relocation offset in DPRAM [DSP2] 4220 define relocation offset in DPRAM [DSP2]
4213 4221
4214 - CONFIG_SYS_SMC_UCODE_PATCH, CONFIG_SYS_SMC_DPMEM_OFFSET [0x1FC0]: 4222 - CONFIG_SYS_SMC_UCODE_PATCH, CONFIG_SYS_SMC_DPMEM_OFFSET [0x1FC0]:
4215 enable SMC microcode relocation patch (MPC8xx); 4223 enable SMC microcode relocation patch (MPC8xx);
4216 define relocation offset in DPRAM [SMC1] 4224 define relocation offset in DPRAM [SMC1]
4217 4225
4218 - CONFIG_SYS_SPI_UCODE_PATCH, CONFIG_SYS_SPI_DPMEM_OFFSET [0x1FC0]: 4226 - CONFIG_SYS_SPI_UCODE_PATCH, CONFIG_SYS_SPI_DPMEM_OFFSET [0x1FC0]:
4219 enable SPI microcode relocation patch (MPC8xx); 4227 enable SPI microcode relocation patch (MPC8xx);
4220 define relocation offset in DPRAM [SCC4] 4228 define relocation offset in DPRAM [SCC4]
4221 4229
4222 - CONFIG_SYS_USE_OSCCLK: 4230 - CONFIG_SYS_USE_OSCCLK:
4223 Use OSCM clock mode on MBX8xx board. Be careful, 4231 Use OSCM clock mode on MBX8xx board. Be careful,
4224 wrong setting might damage your board. Read 4232 wrong setting might damage your board. Read
4225 doc/README.MBX before setting this variable! 4233 doc/README.MBX before setting this variable!
4226 4234
4227 - CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only) 4235 - CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only)
4228 Offset of the bootmode word in DPRAM used by post 4236 Offset of the bootmode word in DPRAM used by post
4229 (Power On Self Tests). This definition overrides 4237 (Power On Self Tests). This definition overrides
4230 #define'd default value in commproc.h resp. 4238 #define'd default value in commproc.h resp.
4231 cpm_8260.h. 4239 cpm_8260.h.
4232 4240
4233 - CONFIG_SYS_PCI_SLV_MEM_LOCAL, CONFIG_SYS_PCI_SLV_MEM_BUS, CONFIG_SYS_PICMR0_MASK_ATTRIB, 4241 - CONFIG_SYS_PCI_SLV_MEM_LOCAL, CONFIG_SYS_PCI_SLV_MEM_BUS, CONFIG_SYS_PICMR0_MASK_ATTRIB,
4234 CONFIG_SYS_PCI_MSTR0_LOCAL, CONFIG_SYS_PCIMSK0_MASK, CONFIG_SYS_PCI_MSTR1_LOCAL, 4242 CONFIG_SYS_PCI_MSTR0_LOCAL, CONFIG_SYS_PCIMSK0_MASK, CONFIG_SYS_PCI_MSTR1_LOCAL,
4235 CONFIG_SYS_PCIMSK1_MASK, CONFIG_SYS_PCI_MSTR_MEM_LOCAL, CONFIG_SYS_PCI_MSTR_MEM_BUS, 4243 CONFIG_SYS_PCIMSK1_MASK, CONFIG_SYS_PCI_MSTR_MEM_LOCAL, CONFIG_SYS_PCI_MSTR_MEM_BUS,
4236 CONFIG_SYS_CPU_PCI_MEM_START, CONFIG_SYS_PCI_MSTR_MEM_SIZE, CONFIG_SYS_POCMR0_MASK_ATTRIB, 4244 CONFIG_SYS_CPU_PCI_MEM_START, CONFIG_SYS_PCI_MSTR_MEM_SIZE, CONFIG_SYS_POCMR0_MASK_ATTRIB,
4237 CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL, CONFIG_SYS_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START, 4245 CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL, CONFIG_SYS_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START,
4238 CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL, 4246 CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL,
4239 CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE, 4247 CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE,
4240 CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only) 4248 CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
4241 Overrides the default PCI memory map in arch/powerpc/cpu/mpc8260/pci.c if set. 4249 Overrides the default PCI memory map in arch/powerpc/cpu/mpc8260/pci.c if set.
4242 4250
4243 - CONFIG_PCI_DISABLE_PCIE: 4251 - CONFIG_PCI_DISABLE_PCIE:
4244 Disable PCI-Express on systems where it is supported but not 4252 Disable PCI-Express on systems where it is supported but not
4245 required. 4253 required.
4246 4254
4247 - CONFIG_PCI_ENUM_ONLY 4255 - CONFIG_PCI_ENUM_ONLY
4248 Only scan through and get the devices on the busses. 4256 Only scan through and get the devices on the busses.
4249 Don't do any setup work, presumably because someone or 4257 Don't do any setup work, presumably because someone or
4250 something has already done it, and we don't need to do it 4258 something has already done it, and we don't need to do it
4251 a second time. Useful for platforms that are pre-booted 4259 a second time. Useful for platforms that are pre-booted
4252 by coreboot or similar. 4260 by coreboot or similar.
4253 4261
4254 - CONFIG_PCI_INDIRECT_BRIDGE: 4262 - CONFIG_PCI_INDIRECT_BRIDGE:
4255 Enable support for indirect PCI bridges. 4263 Enable support for indirect PCI bridges.
4256 4264
4257 - CONFIG_SYS_SRIO: 4265 - CONFIG_SYS_SRIO:
4258 Chip has SRIO or not 4266 Chip has SRIO or not
4259 4267
4260 - CONFIG_SRIO1: 4268 - CONFIG_SRIO1:
4261 Board has SRIO 1 port available 4269 Board has SRIO 1 port available
4262 4270
4263 - CONFIG_SRIO2: 4271 - CONFIG_SRIO2:
4264 Board has SRIO 2 port available 4272 Board has SRIO 2 port available
4265 4273
4266 - CONFIG_SRIO_PCIE_BOOT_MASTER 4274 - CONFIG_SRIO_PCIE_BOOT_MASTER
4267 Board can support master function for Boot from SRIO and PCIE 4275 Board can support master function for Boot from SRIO and PCIE
4268 4276
4269 - CONFIG_SYS_SRIOn_MEM_VIRT: 4277 - CONFIG_SYS_SRIOn_MEM_VIRT:
4270 Virtual Address of SRIO port 'n' memory region 4278 Virtual Address of SRIO port 'n' memory region
4271 4279
4272 - CONFIG_SYS_SRIOn_MEM_PHYS: 4280 - CONFIG_SYS_SRIOn_MEM_PHYS:
4273 Physical Address of SRIO port 'n' memory region 4281 Physical Address of SRIO port 'n' memory region
4274 4282
4275 - CONFIG_SYS_SRIOn_MEM_SIZE: 4283 - CONFIG_SYS_SRIOn_MEM_SIZE:
4276 Size of SRIO port 'n' memory region 4284 Size of SRIO port 'n' memory region
4277 4285
4278 - CONFIG_SYS_NAND_BUSWIDTH_16BIT 4286 - CONFIG_SYS_NAND_BUSWIDTH_16BIT
4279 Defined to tell the NAND controller that the NAND chip is using 4287 Defined to tell the NAND controller that the NAND chip is using
4280 a 16 bit bus. 4288 a 16 bit bus.
4281 Not all NAND drivers use this symbol. 4289 Not all NAND drivers use this symbol.
4282 Example of drivers that use it: 4290 Example of drivers that use it:
4283 - drivers/mtd/nand/ndfc.c 4291 - drivers/mtd/nand/ndfc.c
4284 - drivers/mtd/nand/mxc_nand.c 4292 - drivers/mtd/nand/mxc_nand.c
4285 4293
4286 - CONFIG_SYS_NDFC_EBC0_CFG 4294 - CONFIG_SYS_NDFC_EBC0_CFG
4287 Sets the EBC0_CFG register for the NDFC. If not defined 4295 Sets the EBC0_CFG register for the NDFC. If not defined
4288 a default value will be used. 4296 a default value will be used.
4289 4297
4290 - CONFIG_SPD_EEPROM 4298 - CONFIG_SPD_EEPROM
4291 Get DDR timing information from an I2C EEPROM. Common 4299 Get DDR timing information from an I2C EEPROM. Common
4292 with pluggable memory modules such as SODIMMs 4300 with pluggable memory modules such as SODIMMs
4293 4301
4294 SPD_EEPROM_ADDRESS 4302 SPD_EEPROM_ADDRESS
4295 I2C address of the SPD EEPROM 4303 I2C address of the SPD EEPROM
4296 4304
4297 - CONFIG_SYS_SPD_BUS_NUM 4305 - CONFIG_SYS_SPD_BUS_NUM
4298 If SPD EEPROM is on an I2C bus other than the first 4306 If SPD EEPROM is on an I2C bus other than the first
4299 one, specify here. Note that the value must resolve 4307 one, specify here. Note that the value must resolve
4300 to something your driver can deal with. 4308 to something your driver can deal with.
4301 4309
4302 - CONFIG_SYS_DDR_RAW_TIMING 4310 - CONFIG_SYS_DDR_RAW_TIMING
4303 Get DDR timing information from other than SPD. Common with 4311 Get DDR timing information from other than SPD. Common with
4304 soldered DDR chips onboard without SPD. DDR raw timing 4312 soldered DDR chips onboard without SPD. DDR raw timing
4305 parameters are extracted from datasheet and hard-coded into 4313 parameters are extracted from datasheet and hard-coded into
4306 header files or board specific files. 4314 header files or board specific files.
4307 4315
4308 - CONFIG_FSL_DDR_INTERACTIVE 4316 - CONFIG_FSL_DDR_INTERACTIVE
4309 Enable interactive DDR debugging. See doc/README.fsl-ddr. 4317 Enable interactive DDR debugging. See doc/README.fsl-ddr.
4310 4318
4311 - CONFIG_SYS_83XX_DDR_USES_CS0 4319 - CONFIG_SYS_83XX_DDR_USES_CS0
4312 Only for 83xx systems. If specified, then DDR should 4320 Only for 83xx systems. If specified, then DDR should
4313 be configured using CS0 and CS1 instead of CS2 and CS3. 4321 be configured using CS0 and CS1 instead of CS2 and CS3.
4314 4322
4315 - CONFIG_ETHER_ON_FEC[12] 4323 - CONFIG_ETHER_ON_FEC[12]
4316 Define to enable FEC[12] on a 8xx series processor. 4324 Define to enable FEC[12] on a 8xx series processor.
4317 4325
4318 - CONFIG_FEC[12]_PHY 4326 - CONFIG_FEC[12]_PHY
4319 Define to the hardcoded PHY address which corresponds 4327 Define to the hardcoded PHY address which corresponds
4320 to the given FEC; i. e. 4328 to the given FEC; i. e.
4321 #define CONFIG_FEC1_PHY 4 4329 #define CONFIG_FEC1_PHY 4
4322 means that the PHY with address 4 is connected to FEC1 4330 means that the PHY with address 4 is connected to FEC1
4323 4331
4324 When set to -1, means to probe for first available. 4332 When set to -1, means to probe for first available.
4325 4333
4326 - CONFIG_FEC[12]_PHY_NORXERR 4334 - CONFIG_FEC[12]_PHY_NORXERR
4327 The PHY does not have a RXERR line (RMII only). 4335 The PHY does not have a RXERR line (RMII only).
4328 (so program the FEC to ignore it). 4336 (so program the FEC to ignore it).
4329 4337
4330 - CONFIG_RMII 4338 - CONFIG_RMII
4331 Enable RMII mode for all FECs. 4339 Enable RMII mode for all FECs.
4332 Note that this is a global option, we can't 4340 Note that this is a global option, we can't
4333 have one FEC in standard MII mode and another in RMII mode. 4341 have one FEC in standard MII mode and another in RMII mode.
4334 4342
4335 - CONFIG_CRC32_VERIFY 4343 - CONFIG_CRC32_VERIFY
4336 Add a verify option to the crc32 command. 4344 Add a verify option to the crc32 command.
4337 The syntax is: 4345 The syntax is:
4338 4346
4339 => crc32 -v <address> <count> <crc32> 4347 => crc32 -v <address> <count> <crc32>
4340 4348
4341 Where address/count indicate a memory area 4349 Where address/count indicate a memory area
4342 and crc32 is the correct crc32 which the 4350 and crc32 is the correct crc32 which the
4343 area should have. 4351 area should have.
4344 4352
4345 - CONFIG_LOOPW 4353 - CONFIG_LOOPW
4346 Add the "loopw" memory command. This only takes effect if 4354 Add the "loopw" memory command. This only takes effect if
4347 the memory commands are activated globally (CONFIG_CMD_MEM). 4355 the memory commands are activated globally (CONFIG_CMD_MEM).
4348 4356
4349 - CONFIG_MX_CYCLIC 4357 - CONFIG_MX_CYCLIC
4350 Add the "mdc" and "mwc" memory commands. These are cyclic 4358 Add the "mdc" and "mwc" memory commands. These are cyclic
4351 "md/mw" commands. 4359 "md/mw" commands.
4352 Examples: 4360 Examples:
4353 4361
4354 => mdc.b 10 4 500 4362 => mdc.b 10 4 500
4355 This command will print 4 bytes (10,11,12,13) each 500 ms. 4363 This command will print 4 bytes (10,11,12,13) each 500 ms.
4356 4364
4357 => mwc.l 100 12345678 10 4365 => mwc.l 100 12345678 10
4358 This command will write 12345678 to address 100 all 10 ms. 4366 This command will write 12345678 to address 100 all 10 ms.
4359 4367
4360 This only takes effect if the memory commands are activated 4368 This only takes effect if the memory commands are activated
4361 globally (CONFIG_CMD_MEM). 4369 globally (CONFIG_CMD_MEM).
4362 4370
4363 - CONFIG_SKIP_LOWLEVEL_INIT 4371 - CONFIG_SKIP_LOWLEVEL_INIT
4364 [ARM, NDS32, MIPS only] If this variable is defined, then certain 4372 [ARM, NDS32, MIPS only] If this variable is defined, then certain
4365 low level initializations (like setting up the memory 4373 low level initializations (like setting up the memory
4366 controller) are omitted and/or U-Boot does not 4374 controller) are omitted and/or U-Boot does not
4367 relocate itself into RAM. 4375 relocate itself into RAM.
4368 4376
4369 Normally this variable MUST NOT be defined. The only 4377 Normally this variable MUST NOT be defined. The only
4370 exception is when U-Boot is loaded (to RAM) by some 4378 exception is when U-Boot is loaded (to RAM) by some
4371 other boot loader or by a debugger which performs 4379 other boot loader or by a debugger which performs
4372 these initializations itself. 4380 these initializations itself.
4373 4381
4374 - CONFIG_SPL_BUILD 4382 - CONFIG_SPL_BUILD
4375 Modifies the behaviour of start.S when compiling a loader 4383 Modifies the behaviour of start.S when compiling a loader
4376 that is executed before the actual U-Boot. E.g. when 4384 that is executed before the actual U-Boot. E.g. when
4377 compiling a NAND SPL. 4385 compiling a NAND SPL.
4378 4386
4379 - CONFIG_TPL_BUILD 4387 - CONFIG_TPL_BUILD
4380 Modifies the behaviour of start.S when compiling a loader 4388 Modifies the behaviour of start.S when compiling a loader
4381 that is executed after the SPL and before the actual U-Boot. 4389 that is executed after the SPL and before the actual U-Boot.
4382 It is loaded by the SPL. 4390 It is loaded by the SPL.
4383 4391
4384 - CONFIG_SYS_MPC85XX_NO_RESETVEC 4392 - CONFIG_SYS_MPC85XX_NO_RESETVEC
4385 Only for 85xx systems. If this variable is specified, the section 4393 Only for 85xx systems. If this variable is specified, the section
4386 .resetvec is not kept and the section .bootpg is placed in the 4394 .resetvec is not kept and the section .bootpg is placed in the
4387 previous 4k of the .text section. 4395 previous 4k of the .text section.
4388 4396
4389 - CONFIG_ARCH_MAP_SYSMEM 4397 - CONFIG_ARCH_MAP_SYSMEM
4390 Generally U-Boot (and in particular the md command) uses 4398 Generally U-Boot (and in particular the md command) uses
4391 effective address. It is therefore not necessary to regard 4399 effective address. It is therefore not necessary to regard
4392 U-Boot address as virtual addresses that need to be translated 4400 U-Boot address as virtual addresses that need to be translated
4393 to physical addresses. However, sandbox requires this, since 4401 to physical addresses. However, sandbox requires this, since
4394 it maintains its own little RAM buffer which contains all 4402 it maintains its own little RAM buffer which contains all
4395 addressable memory. This option causes some memory accesses 4403 addressable memory. This option causes some memory accesses
4396 to be mapped through map_sysmem() / unmap_sysmem(). 4404 to be mapped through map_sysmem() / unmap_sysmem().
4397 4405
4398 - CONFIG_USE_ARCH_MEMCPY 4406 - CONFIG_USE_ARCH_MEMCPY
4399 CONFIG_USE_ARCH_MEMSET 4407 CONFIG_USE_ARCH_MEMSET
4400 If these options are used a optimized version of memcpy/memset will 4408 If these options are used a optimized version of memcpy/memset will
4401 be used if available. These functions may be faster under some 4409 be used if available. These functions may be faster under some
4402 conditions but may increase the binary size. 4410 conditions but may increase the binary size.
4403 4411
4404 - CONFIG_X86_RESET_VECTOR 4412 - CONFIG_X86_RESET_VECTOR
4405 If defined, the x86 reset vector code is included. This is not 4413 If defined, the x86 reset vector code is included. This is not
4406 needed when U-Boot is running from Coreboot. 4414 needed when U-Boot is running from Coreboot.
4407 4415
4408 - CONFIG_SYS_MPUCLK 4416 - CONFIG_SYS_MPUCLK
4409 Defines the MPU clock speed (in MHz). 4417 Defines the MPU clock speed (in MHz).
4410 4418
4411 NOTE : currently only supported on AM335x platforms. 4419 NOTE : currently only supported on AM335x platforms.
4412 4420
4413 - CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC: 4421 - CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC:
4414 Enables the RTC32K OSC on AM33xx based plattforms 4422 Enables the RTC32K OSC on AM33xx based plattforms
4415 4423
4416 Freescale QE/FMAN Firmware Support: 4424 Freescale QE/FMAN Firmware Support:
4417 ----------------------------------- 4425 -----------------------------------
4418 4426
4419 The Freescale QUICCEngine (QE) and Frame Manager (FMAN) both support the 4427 The Freescale QUICCEngine (QE) and Frame Manager (FMAN) both support the
4420 loading of "firmware", which is encoded in the QE firmware binary format. 4428 loading of "firmware", which is encoded in the QE firmware binary format.
4421 This firmware often needs to be loaded during U-Boot booting, so macros 4429 This firmware often needs to be loaded during U-Boot booting, so macros
4422 are used to identify the storage device (NOR flash, SPI, etc) and the address 4430 are used to identify the storage device (NOR flash, SPI, etc) and the address
4423 within that device. 4431 within that device.
4424 4432
4425 - CONFIG_SYS_QE_FMAN_FW_ADDR 4433 - CONFIG_SYS_QE_FMAN_FW_ADDR
4426 The address in the storage device where the firmware is located. The 4434 The address in the storage device where the firmware is located. The
4427 meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro 4435 meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
4428 is also specified. 4436 is also specified.
4429 4437
4430 - CONFIG_SYS_QE_FMAN_FW_LENGTH 4438 - CONFIG_SYS_QE_FMAN_FW_LENGTH
4431 The maximum possible size of the firmware. The firmware binary format 4439 The maximum possible size of the firmware. The firmware binary format
4432 has a field that specifies the actual size of the firmware, but it 4440 has a field that specifies the actual size of the firmware, but it
4433 might not be possible to read any part of the firmware unless some 4441 might not be possible to read any part of the firmware unless some
4434 local storage is allocated to hold the entire firmware first. 4442 local storage is allocated to hold the entire firmware first.
4435 4443
4436 - CONFIG_SYS_QE_FMAN_FW_IN_NOR 4444 - CONFIG_SYS_QE_FMAN_FW_IN_NOR
4437 Specifies that QE/FMAN firmware is located in NOR flash, mapped as 4445 Specifies that QE/FMAN firmware is located in NOR flash, mapped as
4438 normal addressable memory via the LBC. CONFIG_SYS_FMAN_FW_ADDR is the 4446 normal addressable memory via the LBC. CONFIG_SYS_FMAN_FW_ADDR is the
4439 virtual address in NOR flash. 4447 virtual address in NOR flash.
4440 4448
4441 - CONFIG_SYS_QE_FMAN_FW_IN_NAND 4449 - CONFIG_SYS_QE_FMAN_FW_IN_NAND
4442 Specifies that QE/FMAN firmware is located in NAND flash. 4450 Specifies that QE/FMAN firmware is located in NAND flash.
4443 CONFIG_SYS_FMAN_FW_ADDR is the offset within NAND flash. 4451 CONFIG_SYS_FMAN_FW_ADDR is the offset within NAND flash.
4444 4452
4445 - CONFIG_SYS_QE_FMAN_FW_IN_MMC 4453 - CONFIG_SYS_QE_FMAN_FW_IN_MMC
4446 Specifies that QE/FMAN firmware is located on the primary SD/MMC 4454 Specifies that QE/FMAN firmware is located on the primary SD/MMC
4447 device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device. 4455 device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
4448 4456
4449 - CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH 4457 - CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH
4450 Specifies that QE/FMAN firmware is located on the primary SPI 4458 Specifies that QE/FMAN firmware is located on the primary SPI
4451 device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device. 4459 device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
4452 4460
4453 - CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 4461 - CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
4454 Specifies that QE/FMAN firmware is located in the remote (master) 4462 Specifies that QE/FMAN firmware is located in the remote (master)
4455 memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which 4463 memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
4456 can be mapped from slave TLB->slave LAW->slave SRIO or PCIE outbound 4464 can be mapped from slave TLB->slave LAW->slave SRIO or PCIE outbound
4457 window->master inbound window->master LAW->the ucode address in 4465 window->master inbound window->master LAW->the ucode address in
4458 master's memory space. 4466 master's memory space.
4459 4467
4460 Building the Software: 4468 Building the Software:
4461 ====================== 4469 ======================
4462 4470
4463 Building U-Boot has been tested in several native build environments 4471 Building U-Boot has been tested in several native build environments
4464 and in many different cross environments. Of course we cannot support 4472 and in many different cross environments. Of course we cannot support
4465 all possibly existing versions of cross development tools in all 4473 all possibly existing versions of cross development tools in all
4466 (potentially obsolete) versions. In case of tool chain problems we 4474 (potentially obsolete) versions. In case of tool chain problems we
4467 recommend to use the ELDK (see http://www.denx.de/wiki/DULG/ELDK) 4475 recommend to use the ELDK (see http://www.denx.de/wiki/DULG/ELDK)
4468 which is extensively used to build and test U-Boot. 4476 which is extensively used to build and test U-Boot.
4469 4477
4470 If you are not using a native environment, it is assumed that you 4478 If you are not using a native environment, it is assumed that you
4471 have GNU cross compiling tools available in your path. In this case, 4479 have GNU cross compiling tools available in your path. In this case,
4472 you must set the environment variable CROSS_COMPILE in your shell. 4480 you must set the environment variable CROSS_COMPILE in your shell.
4473 Note that no changes to the Makefile or any other source files are 4481 Note that no changes to the Makefile or any other source files are
4474 necessary. For example using the ELDK on a 4xx CPU, please enter: 4482 necessary. For example using the ELDK on a 4xx CPU, please enter:
4475 4483
4476 $ CROSS_COMPILE=ppc_4xx- 4484 $ CROSS_COMPILE=ppc_4xx-
4477 $ export CROSS_COMPILE 4485 $ export CROSS_COMPILE
4478 4486
4479 Note: If you wish to generate Windows versions of the utilities in 4487 Note: If you wish to generate Windows versions of the utilities in
4480 the tools directory you can use the MinGW toolchain 4488 the tools directory you can use the MinGW toolchain
4481 (http://www.mingw.org). Set your HOST tools to the MinGW 4489 (http://www.mingw.org). Set your HOST tools to the MinGW
4482 toolchain and execute 'make tools'. For example: 4490 toolchain and execute 'make tools'. For example:
4483 4491
4484 $ make HOSTCC=i586-mingw32msvc-gcc HOSTSTRIP=i586-mingw32msvc-strip tools 4492 $ make HOSTCC=i586-mingw32msvc-gcc HOSTSTRIP=i586-mingw32msvc-strip tools
4485 4493
4486 Binaries such as tools/mkimage.exe will be created which can 4494 Binaries such as tools/mkimage.exe will be created which can
4487 be executed on computers running Windows. 4495 be executed on computers running Windows.
4488 4496
4489 U-Boot is intended to be simple to build. After installing the 4497 U-Boot is intended to be simple to build. After installing the
4490 sources you must configure U-Boot for one specific board type. This 4498 sources you must configure U-Boot for one specific board type. This
4491 is done by typing: 4499 is done by typing:
4492 4500
4493 make NAME_config 4501 make NAME_config
4494 4502
4495 where "NAME_config" is the name of one of the existing configu- 4503 where "NAME_config" is the name of one of the existing configu-
4496 rations; see boards.cfg for supported names. 4504 rations; see boards.cfg for supported names.
4497 4505
4498 Note: for some board special configuration names may exist; check if 4506 Note: for some board special configuration names may exist; check if
4499 additional information is available from the board vendor; for 4507 additional information is available from the board vendor; for
4500 instance, the TQM823L systems are available without (standard) 4508 instance, the TQM823L systems are available without (standard)
4501 or with LCD support. You can select such additional "features" 4509 or with LCD support. You can select such additional "features"
4502 when choosing the configuration, i. e. 4510 when choosing the configuration, i. e.
4503 4511
4504 make TQM823L_config 4512 make TQM823L_config
4505 - will configure for a plain TQM823L, i. e. no LCD support 4513 - will configure for a plain TQM823L, i. e. no LCD support
4506 4514
4507 make TQM823L_LCD_config 4515 make TQM823L_LCD_config
4508 - will configure for a TQM823L with U-Boot console on LCD 4516 - will configure for a TQM823L with U-Boot console on LCD
4509 4517
4510 etc. 4518 etc.
4511 4519
4512 4520
4513 Finally, type "make all", and you should get some working U-Boot 4521 Finally, type "make all", and you should get some working U-Boot
4514 images ready for download to / installation on your system: 4522 images ready for download to / installation on your system:
4515 4523
4516 - "u-boot.bin" is a raw binary image 4524 - "u-boot.bin" is a raw binary image
4517 - "u-boot" is an image in ELF binary format 4525 - "u-boot" is an image in ELF binary format
4518 - "u-boot.srec" is in Motorola S-Record format 4526 - "u-boot.srec" is in Motorola S-Record format
4519 4527
4520 By default the build is performed locally and the objects are saved 4528 By default the build is performed locally and the objects are saved
4521 in the source directory. One of the two methods can be used to change 4529 in the source directory. One of the two methods can be used to change
4522 this behavior and build U-Boot to some external directory: 4530 this behavior and build U-Boot to some external directory:
4523 4531
4524 1. Add O= to the make command line invocations: 4532 1. Add O= to the make command line invocations:
4525 4533
4526 make O=/tmp/build distclean 4534 make O=/tmp/build distclean
4527 make O=/tmp/build NAME_config 4535 make O=/tmp/build NAME_config
4528 make O=/tmp/build all 4536 make O=/tmp/build all
4529 4537
4530 2. Set environment variable BUILD_DIR to point to the desired location: 4538 2. Set environment variable BUILD_DIR to point to the desired location:
4531 4539
4532 export BUILD_DIR=/tmp/build 4540 export BUILD_DIR=/tmp/build
4533 make distclean 4541 make distclean
4534 make NAME_config 4542 make NAME_config
4535 make all 4543 make all
4536 4544
4537 Note that the command line "O=" setting overrides the BUILD_DIR environment 4545 Note that the command line "O=" setting overrides the BUILD_DIR environment
4538 variable. 4546 variable.
4539 4547
4540 4548
4541 Please be aware that the Makefiles assume you are using GNU make, so 4549 Please be aware that the Makefiles assume you are using GNU make, so
4542 for instance on NetBSD you might need to use "gmake" instead of 4550 for instance on NetBSD you might need to use "gmake" instead of
4543 native "make". 4551 native "make".
4544 4552
4545 4553
4546 If the system board that you have is not listed, then you will need 4554 If the system board that you have is not listed, then you will need
4547 to port U-Boot to your hardware platform. To do this, follow these 4555 to port U-Boot to your hardware platform. To do this, follow these
4548 steps: 4556 steps:
4549 4557
4550 1. Add a new configuration option for your board to the toplevel 4558 1. Add a new configuration option for your board to the toplevel
4551 "boards.cfg" file, using the existing entries as examples. 4559 "boards.cfg" file, using the existing entries as examples.
4552 Follow the instructions there to keep the boards in order. 4560 Follow the instructions there to keep the boards in order.
4553 2. Create a new directory to hold your board specific code. Add any 4561 2. Create a new directory to hold your board specific code. Add any
4554 files you need. In your board directory, you will need at least 4562 files you need. In your board directory, you will need at least
4555 the "Makefile", a "<board>.c", "flash.c" and "u-boot.lds". 4563 the "Makefile", a "<board>.c", "flash.c" and "u-boot.lds".
4556 3. Create a new configuration file "include/configs/<board>.h" for 4564 3. Create a new configuration file "include/configs/<board>.h" for
4557 your board 4565 your board
4558 3. If you're porting U-Boot to a new CPU, then also create a new 4566 3. If you're porting U-Boot to a new CPU, then also create a new
4559 directory to hold your CPU specific code. Add any files you need. 4567 directory to hold your CPU specific code. Add any files you need.
4560 4. Run "make <board>_config" with your new name. 4568 4. Run "make <board>_config" with your new name.
4561 5. Type "make", and you should get a working "u-boot.srec" file 4569 5. Type "make", and you should get a working "u-boot.srec" file
4562 to be installed on your target system. 4570 to be installed on your target system.
4563 6. Debug and solve any problems that might arise. 4571 6. Debug and solve any problems that might arise.
4564 [Of course, this last step is much harder than it sounds.] 4572 [Of course, this last step is much harder than it sounds.]
4565 4573
4566 4574
4567 Testing of U-Boot Modifications, Ports to New Hardware, etc.: 4575 Testing of U-Boot Modifications, Ports to New Hardware, etc.:
4568 ============================================================== 4576 ==============================================================
4569 4577
4570 If you have modified U-Boot sources (for instance added a new board 4578 If you have modified U-Boot sources (for instance added a new board
4571 or support for new devices, a new CPU, etc.) you are expected to 4579 or support for new devices, a new CPU, etc.) you are expected to
4572 provide feedback to the other developers. The feedback normally takes 4580 provide feedback to the other developers. The feedback normally takes
4573 the form of a "patch", i. e. a context diff against a certain (latest 4581 the form of a "patch", i. e. a context diff against a certain (latest
4574 official or latest in the git repository) version of U-Boot sources. 4582 official or latest in the git repository) version of U-Boot sources.
4575 4583
4576 But before you submit such a patch, please verify that your modifi- 4584 But before you submit such a patch, please verify that your modifi-
4577 cation did not break existing code. At least make sure that *ALL* of 4585 cation did not break existing code. At least make sure that *ALL* of
4578 the supported boards compile WITHOUT ANY compiler warnings. To do so, 4586 the supported boards compile WITHOUT ANY compiler warnings. To do so,
4579 just run the "MAKEALL" script, which will configure and build U-Boot 4587 just run the "MAKEALL" script, which will configure and build U-Boot
4580 for ALL supported system. Be warned, this will take a while. You can 4588 for ALL supported system. Be warned, this will take a while. You can
4581 select which (cross) compiler to use by passing a `CROSS_COMPILE' 4589 select which (cross) compiler to use by passing a `CROSS_COMPILE'
4582 environment variable to the script, i. e. to use the ELDK cross tools 4590 environment variable to the script, i. e. to use the ELDK cross tools
4583 you can type 4591 you can type
4584 4592
4585 CROSS_COMPILE=ppc_8xx- MAKEALL 4593 CROSS_COMPILE=ppc_8xx- MAKEALL
4586 4594
4587 or to build on a native PowerPC system you can type 4595 or to build on a native PowerPC system you can type
4588 4596
4589 CROSS_COMPILE=' ' MAKEALL 4597 CROSS_COMPILE=' ' MAKEALL
4590 4598
4591 When using the MAKEALL script, the default behaviour is to build 4599 When using the MAKEALL script, the default behaviour is to build
4592 U-Boot in the source directory. This location can be changed by 4600 U-Boot in the source directory. This location can be changed by
4593 setting the BUILD_DIR environment variable. Also, for each target 4601 setting the BUILD_DIR environment variable. Also, for each target
4594 built, the MAKEALL script saves two log files (<target>.ERR and 4602 built, the MAKEALL script saves two log files (<target>.ERR and
4595 <target>.MAKEALL) in the <source dir>/LOG directory. This default 4603 <target>.MAKEALL) in the <source dir>/LOG directory. This default
4596 location can be changed by setting the MAKEALL_LOGDIR environment 4604 location can be changed by setting the MAKEALL_LOGDIR environment
4597 variable. For example: 4605 variable. For example:
4598 4606
4599 export BUILD_DIR=/tmp/build 4607 export BUILD_DIR=/tmp/build
4600 export MAKEALL_LOGDIR=/tmp/log 4608 export MAKEALL_LOGDIR=/tmp/log
4601 CROSS_COMPILE=ppc_8xx- MAKEALL 4609 CROSS_COMPILE=ppc_8xx- MAKEALL
4602 4610
4603 With the above settings build objects are saved in the /tmp/build, 4611 With the above settings build objects are saved in the /tmp/build,
4604 log files are saved in the /tmp/log and the source tree remains clean 4612 log files are saved in the /tmp/log and the source tree remains clean
4605 during the whole build process. 4613 during the whole build process.
4606 4614
4607 4615
4608 See also "U-Boot Porting Guide" below. 4616 See also "U-Boot Porting Guide" below.
4609 4617
4610 4618
4611 Monitor Commands - Overview: 4619 Monitor Commands - Overview:
4612 ============================ 4620 ============================
4613 4621
4614 go - start application at address 'addr' 4622 go - start application at address 'addr'
4615 run - run commands in an environment variable 4623 run - run commands in an environment variable
4616 bootm - boot application image from memory 4624 bootm - boot application image from memory
4617 bootp - boot image via network using BootP/TFTP protocol 4625 bootp - boot image via network using BootP/TFTP protocol
4618 bootz - boot zImage from memory 4626 bootz - boot zImage from memory
4619 tftpboot- boot image via network using TFTP protocol 4627 tftpboot- boot image via network using TFTP protocol
4620 and env variables "ipaddr" and "serverip" 4628 and env variables "ipaddr" and "serverip"
4621 (and eventually "gatewayip") 4629 (and eventually "gatewayip")
4622 tftpput - upload a file via network using TFTP protocol 4630 tftpput - upload a file via network using TFTP protocol
4623 rarpboot- boot image via network using RARP/TFTP protocol 4631 rarpboot- boot image via network using RARP/TFTP protocol
4624 diskboot- boot from IDE devicebootd - boot default, i.e., run 'bootcmd' 4632 diskboot- boot from IDE devicebootd - boot default, i.e., run 'bootcmd'
4625 loads - load S-Record file over serial line 4633 loads - load S-Record file over serial line
4626 loadb - load binary file over serial line (kermit mode) 4634 loadb - load binary file over serial line (kermit mode)
4627 md - memory display 4635 md - memory display
4628 mm - memory modify (auto-incrementing) 4636 mm - memory modify (auto-incrementing)
4629 nm - memory modify (constant address) 4637 nm - memory modify (constant address)
4630 mw - memory write (fill) 4638 mw - memory write (fill)
4631 cp - memory copy 4639 cp - memory copy
4632 cmp - memory compare 4640 cmp - memory compare
4633 crc32 - checksum calculation 4641 crc32 - checksum calculation
4634 i2c - I2C sub-system 4642 i2c - I2C sub-system
4635 sspi - SPI utility commands 4643 sspi - SPI utility commands
4636 base - print or set address offset 4644 base - print or set address offset
4637 printenv- print environment variables 4645 printenv- print environment variables
4638 setenv - set environment variables 4646 setenv - set environment variables
4639 saveenv - save environment variables to persistent storage 4647 saveenv - save environment variables to persistent storage
4640 protect - enable or disable FLASH write protection 4648 protect - enable or disable FLASH write protection
4641 erase - erase FLASH memory 4649 erase - erase FLASH memory
4642 flinfo - print FLASH memory information 4650 flinfo - print FLASH memory information
4643 nand - NAND memory operations (see doc/README.nand) 4651 nand - NAND memory operations (see doc/README.nand)
4644 bdinfo - print Board Info structure 4652 bdinfo - print Board Info structure
4645 iminfo - print header information for application image 4653 iminfo - print header information for application image
4646 coninfo - print console devices and informations 4654 coninfo - print console devices and informations
4647 ide - IDE sub-system 4655 ide - IDE sub-system
4648 loop - infinite loop on address range 4656 loop - infinite loop on address range
4649 loopw - infinite write loop on address range 4657 loopw - infinite write loop on address range
4650 mtest - simple RAM test 4658 mtest - simple RAM test
4651 icache - enable or disable instruction cache 4659 icache - enable or disable instruction cache
4652 dcache - enable or disable data cache 4660 dcache - enable or disable data cache
4653 reset - Perform RESET of the CPU 4661 reset - Perform RESET of the CPU
4654 echo - echo args to console 4662 echo - echo args to console
4655 version - print monitor version 4663 version - print monitor version
4656 help - print online help 4664 help - print online help
4657 ? - alias for 'help' 4665 ? - alias for 'help'
4658 4666
4659 4667
4660 Monitor Commands - Detailed Description: 4668 Monitor Commands - Detailed Description:
4661 ======================================== 4669 ========================================
4662 4670
4663 TODO. 4671 TODO.
4664 4672
4665 For now: just type "help <command>". 4673 For now: just type "help <command>".
4666 4674
4667 4675
4668 Environment Variables: 4676 Environment Variables:
4669 ====================== 4677 ======================
4670 4678
4671 U-Boot supports user configuration using Environment Variables which 4679 U-Boot supports user configuration using Environment Variables which
4672 can be made persistent by saving to Flash memory. 4680 can be made persistent by saving to Flash memory.
4673 4681
4674 Environment Variables are set using "setenv", printed using 4682 Environment Variables are set using "setenv", printed using
4675 "printenv", and saved to Flash using "saveenv". Using "setenv" 4683 "printenv", and saved to Flash using "saveenv". Using "setenv"
4676 without a value can be used to delete a variable from the 4684 without a value can be used to delete a variable from the
4677 environment. As long as you don't save the environment you are 4685 environment. As long as you don't save the environment you are
4678 working with an in-memory copy. In case the Flash area containing the 4686 working with an in-memory copy. In case the Flash area containing the
4679 environment is erased by accident, a default environment is provided. 4687 environment is erased by accident, a default environment is provided.
4680 4688
4681 Some configuration options can be set using Environment Variables. 4689 Some configuration options can be set using Environment Variables.
4682 4690
4683 List of environment variables (most likely not complete): 4691 List of environment variables (most likely not complete):
4684 4692
4685 baudrate - see CONFIG_BAUDRATE 4693 baudrate - see CONFIG_BAUDRATE
4686 4694
4687 bootdelay - see CONFIG_BOOTDELAY 4695 bootdelay - see CONFIG_BOOTDELAY
4688 4696
4689 bootcmd - see CONFIG_BOOTCOMMAND 4697 bootcmd - see CONFIG_BOOTCOMMAND
4690 4698
4691 bootargs - Boot arguments when booting an RTOS image 4699 bootargs - Boot arguments when booting an RTOS image
4692 4700
4693 bootfile - Name of the image to load with TFTP 4701 bootfile - Name of the image to load with TFTP
4694 4702
4695 bootm_low - Memory range available for image processing in the bootm 4703 bootm_low - Memory range available for image processing in the bootm
4696 command can be restricted. This variable is given as 4704 command can be restricted. This variable is given as
4697 a hexadecimal number and defines lowest address allowed 4705 a hexadecimal number and defines lowest address allowed
4698 for use by the bootm command. See also "bootm_size" 4706 for use by the bootm command. See also "bootm_size"
4699 environment variable. Address defined by "bootm_low" is 4707 environment variable. Address defined by "bootm_low" is
4700 also the base of the initial memory mapping for the Linux 4708 also the base of the initial memory mapping for the Linux
4701 kernel -- see the description of CONFIG_SYS_BOOTMAPSZ and 4709 kernel -- see the description of CONFIG_SYS_BOOTMAPSZ and
4702 bootm_mapsize. 4710 bootm_mapsize.
4703 4711
4704 bootm_mapsize - Size of the initial memory mapping for the Linux kernel. 4712 bootm_mapsize - Size of the initial memory mapping for the Linux kernel.
4705 This variable is given as a hexadecimal number and it 4713 This variable is given as a hexadecimal number and it
4706 defines the size of the memory region starting at base 4714 defines the size of the memory region starting at base
4707 address bootm_low that is accessible by the Linux kernel 4715 address bootm_low that is accessible by the Linux kernel
4708 during early boot. If unset, CONFIG_SYS_BOOTMAPSZ is used 4716 during early boot. If unset, CONFIG_SYS_BOOTMAPSZ is used
4709 as the default value if it is defined, and bootm_size is 4717 as the default value if it is defined, and bootm_size is
4710 used otherwise. 4718 used otherwise.
4711 4719
4712 bootm_size - Memory range available for image processing in the bootm 4720 bootm_size - Memory range available for image processing in the bootm
4713 command can be restricted. This variable is given as 4721 command can be restricted. This variable is given as
4714 a hexadecimal number and defines the size of the region 4722 a hexadecimal number and defines the size of the region
4715 allowed for use by the bootm command. See also "bootm_low" 4723 allowed for use by the bootm command. See also "bootm_low"
4716 environment variable. 4724 environment variable.
4717 4725
4718 updatefile - Location of the software update file on a TFTP server, used 4726 updatefile - Location of the software update file on a TFTP server, used
4719 by the automatic software update feature. Please refer to 4727 by the automatic software update feature. Please refer to
4720 documentation in doc/README.update for more details. 4728 documentation in doc/README.update for more details.
4721 4729
4722 autoload - if set to "no" (any string beginning with 'n'), 4730 autoload - if set to "no" (any string beginning with 'n'),
4723 "bootp" will just load perform a lookup of the 4731 "bootp" will just load perform a lookup of the
4724 configuration from the BOOTP server, but not try to 4732 configuration from the BOOTP server, but not try to
4725 load any image using TFTP 4733 load any image using TFTP
4726 4734
4727 autostart - if set to "yes", an image loaded using the "bootp", 4735 autostart - if set to "yes", an image loaded using the "bootp",
4728 "rarpboot", "tftpboot" or "diskboot" commands will 4736 "rarpboot", "tftpboot" or "diskboot" commands will
4729 be automatically started (by internally calling 4737 be automatically started (by internally calling
4730 "bootm") 4738 "bootm")
4731 4739
4732 If set to "no", a standalone image passed to the 4740 If set to "no", a standalone image passed to the
4733 "bootm" command will be copied to the load address 4741 "bootm" command will be copied to the load address
4734 (and eventually uncompressed), but NOT be started. 4742 (and eventually uncompressed), but NOT be started.
4735 This can be used to load and uncompress arbitrary 4743 This can be used to load and uncompress arbitrary
4736 data. 4744 data.
4737 4745
4738 fdt_high - if set this restricts the maximum address that the 4746 fdt_high - if set this restricts the maximum address that the
4739 flattened device tree will be copied into upon boot. 4747 flattened device tree will be copied into upon boot.
4740 For example, if you have a system with 1 GB memory 4748 For example, if you have a system with 1 GB memory
4741 at physical address 0x10000000, while Linux kernel 4749 at physical address 0x10000000, while Linux kernel
4742 only recognizes the first 704 MB as low memory, you 4750 only recognizes the first 704 MB as low memory, you
4743 may need to set fdt_high as 0x3C000000 to have the 4751 may need to set fdt_high as 0x3C000000 to have the
4744 device tree blob be copied to the maximum address 4752 device tree blob be copied to the maximum address
4745 of the 704 MB low memory, so that Linux kernel can 4753 of the 704 MB low memory, so that Linux kernel can
4746 access it during the boot procedure. 4754 access it during the boot procedure.
4747 4755
4748 If this is set to the special value 0xFFFFFFFF then 4756 If this is set to the special value 0xFFFFFFFF then
4749 the fdt will not be copied at all on boot. For this 4757 the fdt will not be copied at all on boot. For this
4750 to work it must reside in writable memory, have 4758 to work it must reside in writable memory, have
4751 sufficient padding on the end of it for u-boot to 4759 sufficient padding on the end of it for u-boot to
4752 add the information it needs into it, and the memory 4760 add the information it needs into it, and the memory
4753 must be accessible by the kernel. 4761 must be accessible by the kernel.
4754 4762
4755 fdtcontroladdr- if set this is the address of the control flattened 4763 fdtcontroladdr- if set this is the address of the control flattened
4756 device tree used by U-Boot when CONFIG_OF_CONTROL is 4764 device tree used by U-Boot when CONFIG_OF_CONTROL is
4757 defined. 4765 defined.
4758 4766
4759 i2cfast - (PPC405GP|PPC405EP only) 4767 i2cfast - (PPC405GP|PPC405EP only)
4760 if set to 'y' configures Linux I2C driver for fast 4768 if set to 'y' configures Linux I2C driver for fast
4761 mode (400kHZ). This environment variable is used in 4769 mode (400kHZ). This environment variable is used in
4762 initialization code. So, for changes to be effective 4770 initialization code. So, for changes to be effective
4763 it must be saved and board must be reset. 4771 it must be saved and board must be reset.
4764 4772
4765 initrd_high - restrict positioning of initrd images: 4773 initrd_high - restrict positioning of initrd images:
4766 If this variable is not set, initrd images will be 4774 If this variable is not set, initrd images will be
4767 copied to the highest possible address in RAM; this 4775 copied to the highest possible address in RAM; this
4768 is usually what you want since it allows for 4776 is usually what you want since it allows for
4769 maximum initrd size. If for some reason you want to 4777 maximum initrd size. If for some reason you want to
4770 make sure that the initrd image is loaded below the 4778 make sure that the initrd image is loaded below the
4771 CONFIG_SYS_BOOTMAPSZ limit, you can set this environment 4779 CONFIG_SYS_BOOTMAPSZ limit, you can set this environment
4772 variable to a value of "no" or "off" or "0". 4780 variable to a value of "no" or "off" or "0".
4773 Alternatively, you can set it to a maximum upper 4781 Alternatively, you can set it to a maximum upper
4774 address to use (U-Boot will still check that it 4782 address to use (U-Boot will still check that it
4775 does not overwrite the U-Boot stack and data). 4783 does not overwrite the U-Boot stack and data).
4776 4784
4777 For instance, when you have a system with 16 MB 4785 For instance, when you have a system with 16 MB
4778 RAM, and want to reserve 4 MB from use by Linux, 4786 RAM, and want to reserve 4 MB from use by Linux,
4779 you can do this by adding "mem=12M" to the value of 4787 you can do this by adding "mem=12M" to the value of
4780 the "bootargs" variable. However, now you must make 4788 the "bootargs" variable. However, now you must make
4781 sure that the initrd image is placed in the first 4789 sure that the initrd image is placed in the first
4782 12 MB as well - this can be done with 4790 12 MB as well - this can be done with
4783 4791
4784 setenv initrd_high 00c00000 4792 setenv initrd_high 00c00000
4785 4793
4786 If you set initrd_high to 0xFFFFFFFF, this is an 4794 If you set initrd_high to 0xFFFFFFFF, this is an
4787 indication to U-Boot that all addresses are legal 4795 indication to U-Boot that all addresses are legal
4788 for the Linux kernel, including addresses in flash 4796 for the Linux kernel, including addresses in flash
4789 memory. In this case U-Boot will NOT COPY the 4797 memory. In this case U-Boot will NOT COPY the
4790 ramdisk at all. This may be useful to reduce the 4798 ramdisk at all. This may be useful to reduce the
4791 boot time on your system, but requires that this 4799 boot time on your system, but requires that this
4792 feature is supported by your Linux kernel. 4800 feature is supported by your Linux kernel.
4793 4801
4794 ipaddr - IP address; needed for tftpboot command 4802 ipaddr - IP address; needed for tftpboot command
4795 4803
4796 loadaddr - Default load address for commands like "bootp", 4804 loadaddr - Default load address for commands like "bootp",
4797 "rarpboot", "tftpboot", "loadb" or "diskboot" 4805 "rarpboot", "tftpboot", "loadb" or "diskboot"
4798 4806
4799 loads_echo - see CONFIG_LOADS_ECHO 4807 loads_echo - see CONFIG_LOADS_ECHO
4800 4808
4801 serverip - TFTP server IP address; needed for tftpboot command 4809 serverip - TFTP server IP address; needed for tftpboot command
4802 4810
4803 bootretry - see CONFIG_BOOT_RETRY_TIME 4811 bootretry - see CONFIG_BOOT_RETRY_TIME
4804 4812
4805 bootdelaykey - see CONFIG_AUTOBOOT_DELAY_STR 4813 bootdelaykey - see CONFIG_AUTOBOOT_DELAY_STR
4806 4814
4807 bootstopkey - see CONFIG_AUTOBOOT_STOP_STR 4815 bootstopkey - see CONFIG_AUTOBOOT_STOP_STR
4808 4816
4809 ethprime - controls which interface is used first. 4817 ethprime - controls which interface is used first.
4810 4818
4811 ethact - controls which interface is currently active. 4819 ethact - controls which interface is currently active.
4812 For example you can do the following 4820 For example you can do the following
4813 4821
4814 => setenv ethact FEC 4822 => setenv ethact FEC
4815 => ping 192.168.0.1 # traffic sent on FEC 4823 => ping 192.168.0.1 # traffic sent on FEC
4816 => setenv ethact SCC 4824 => setenv ethact SCC
4817 => ping 10.0.0.1 # traffic sent on SCC 4825 => ping 10.0.0.1 # traffic sent on SCC
4818 4826
4819 ethrotate - When set to "no" U-Boot does not go through all 4827 ethrotate - When set to "no" U-Boot does not go through all
4820 available network interfaces. 4828 available network interfaces.
4821 It just stays at the currently selected interface. 4829 It just stays at the currently selected interface.
4822 4830
4823 netretry - When set to "no" each network operation will 4831 netretry - When set to "no" each network operation will
4824 either succeed or fail without retrying. 4832 either succeed or fail without retrying.
4825 When set to "once" the network operation will 4833 When set to "once" the network operation will
4826 fail when all the available network interfaces 4834 fail when all the available network interfaces
4827 are tried once without success. 4835 are tried once without success.
4828 Useful on scripts which control the retry operation 4836 Useful on scripts which control the retry operation
4829 themselves. 4837 themselves.
4830 4838
4831 npe_ucode - set load address for the NPE microcode 4839 npe_ucode - set load address for the NPE microcode
4832 4840
4833 silent_linux - If set then linux will be told to boot silently, by 4841 silent_linux - If set then linux will be told to boot silently, by
4834 changing the console to be empty. If "yes" it will be 4842 changing the console to be empty. If "yes" it will be
4835 made silent. If "no" it will not be made silent. If 4843 made silent. If "no" it will not be made silent. If
4836 unset, then it will be made silent if the U-Boot console 4844 unset, then it will be made silent if the U-Boot console
4837 is silent. 4845 is silent.
4838 4846
4839 tftpsrcport - If this is set, the value is used for TFTP's 4847 tftpsrcport - If this is set, the value is used for TFTP's
4840 UDP source port. 4848 UDP source port.
4841 4849
4842 tftpdstport - If this is set, the value is used for TFTP's UDP 4850 tftpdstport - If this is set, the value is used for TFTP's UDP
4843 destination port instead of the Well Know Port 69. 4851 destination port instead of the Well Know Port 69.
4844 4852
4845 tftpblocksize - Block size to use for TFTP transfers; if not set, 4853 tftpblocksize - Block size to use for TFTP transfers; if not set,
4846 we use the TFTP server's default block size 4854 we use the TFTP server's default block size
4847 4855
4848 tftptimeout - Retransmission timeout for TFTP packets (in milli- 4856 tftptimeout - Retransmission timeout for TFTP packets (in milli-
4849 seconds, minimum value is 1000 = 1 second). Defines 4857 seconds, minimum value is 1000 = 1 second). Defines
4850 when a packet is considered to be lost so it has to 4858 when a packet is considered to be lost so it has to
4851 be retransmitted. The default is 5000 = 5 seconds. 4859 be retransmitted. The default is 5000 = 5 seconds.
4852 Lowering this value may make downloads succeed 4860 Lowering this value may make downloads succeed
4853 faster in networks with high packet loss rates or 4861 faster in networks with high packet loss rates or
4854 with unreliable TFTP servers. 4862 with unreliable TFTP servers.
4855 4863
4856 vlan - When set to a value < 4095 the traffic over 4864 vlan - When set to a value < 4095 the traffic over
4857 Ethernet is encapsulated/received over 802.1q 4865 Ethernet is encapsulated/received over 802.1q
4858 VLAN tagged frames. 4866 VLAN tagged frames.
4859 4867
4860 The following image location variables contain the location of images 4868 The following image location variables contain the location of images
4861 used in booting. The "Image" column gives the role of the image and is 4869 used in booting. The "Image" column gives the role of the image and is
4862 not an environment variable name. The other columns are environment 4870 not an environment variable name. The other columns are environment
4863 variable names. "File Name" gives the name of the file on a TFTP 4871 variable names. "File Name" gives the name of the file on a TFTP
4864 server, "RAM Address" gives the location in RAM the image will be 4872 server, "RAM Address" gives the location in RAM the image will be
4865 loaded to, and "Flash Location" gives the image's address in NOR 4873 loaded to, and "Flash Location" gives the image's address in NOR
4866 flash or offset in NAND flash. 4874 flash or offset in NAND flash.
4867 4875
4868 *Note* - these variables don't have to be defined for all boards, some 4876 *Note* - these variables don't have to be defined for all boards, some
4869 boards currenlty use other variables for these purposes, and some 4877 boards currenlty use other variables for these purposes, and some
4870 boards use these variables for other purposes. 4878 boards use these variables for other purposes.
4871 4879
4872 Image File Name RAM Address Flash Location 4880 Image File Name RAM Address Flash Location
4873 ----- --------- ----------- -------------- 4881 ----- --------- ----------- --------------
4874 u-boot u-boot u-boot_addr_r u-boot_addr 4882 u-boot u-boot u-boot_addr_r u-boot_addr
4875 Linux kernel bootfile kernel_addr_r kernel_addr 4883 Linux kernel bootfile kernel_addr_r kernel_addr
4876 device tree blob fdtfile fdt_addr_r fdt_addr 4884 device tree blob fdtfile fdt_addr_r fdt_addr
4877 ramdisk ramdiskfile ramdisk_addr_r ramdisk_addr 4885 ramdisk ramdiskfile ramdisk_addr_r ramdisk_addr
4878 4886
4879 The following environment variables may be used and automatically 4887 The following environment variables may be used and automatically
4880 updated by the network boot commands ("bootp" and "rarpboot"), 4888 updated by the network boot commands ("bootp" and "rarpboot"),
4881 depending the information provided by your boot server: 4889 depending the information provided by your boot server:
4882 4890
4883 bootfile - see above 4891 bootfile - see above
4884 dnsip - IP address of your Domain Name Server 4892 dnsip - IP address of your Domain Name Server
4885 dnsip2 - IP address of your secondary Domain Name Server 4893 dnsip2 - IP address of your secondary Domain Name Server
4886 gatewayip - IP address of the Gateway (Router) to use 4894 gatewayip - IP address of the Gateway (Router) to use
4887 hostname - Target hostname 4895 hostname - Target hostname
4888 ipaddr - see above 4896 ipaddr - see above
4889 netmask - Subnet Mask 4897 netmask - Subnet Mask
4890 rootpath - Pathname of the root filesystem on the NFS server 4898 rootpath - Pathname of the root filesystem on the NFS server
4891 serverip - see above 4899 serverip - see above
4892 4900
4893 4901
4894 There are two special Environment Variables: 4902 There are two special Environment Variables:
4895 4903
4896 serial# - contains hardware identification information such 4904 serial# - contains hardware identification information such
4897 as type string and/or serial number 4905 as type string and/or serial number
4898 ethaddr - Ethernet address 4906 ethaddr - Ethernet address
4899 4907
4900 These variables can be set only once (usually during manufacturing of 4908 These variables can be set only once (usually during manufacturing of
4901 the board). U-Boot refuses to delete or overwrite these variables 4909 the board). U-Boot refuses to delete or overwrite these variables
4902 once they have been set once. 4910 once they have been set once.
4903 4911
4904 4912
4905 Further special Environment Variables: 4913 Further special Environment Variables:
4906 4914
4907 ver - Contains the U-Boot version string as printed 4915 ver - Contains the U-Boot version string as printed
4908 with the "version" command. This variable is 4916 with the "version" command. This variable is
4909 readonly (see CONFIG_VERSION_VARIABLE). 4917 readonly (see CONFIG_VERSION_VARIABLE).
4910 4918
4911 4919
4912 Please note that changes to some configuration parameters may take 4920 Please note that changes to some configuration parameters may take
4913 only effect after the next boot (yes, that's just like Windoze :-). 4921 only effect after the next boot (yes, that's just like Windoze :-).
4914 4922
4915 4923
4916 Callback functions for environment variables: 4924 Callback functions for environment variables:
4917 --------------------------------------------- 4925 ---------------------------------------------
4918 4926
4919 For some environment variables, the behavior of u-boot needs to change 4927 For some environment variables, the behavior of u-boot needs to change
4920 when their values are changed. This functionailty allows functions to 4928 when their values are changed. This functionailty allows functions to
4921 be associated with arbitrary variables. On creation, overwrite, or 4929 be associated with arbitrary variables. On creation, overwrite, or
4922 deletion, the callback will provide the opportunity for some side 4930 deletion, the callback will provide the opportunity for some side
4923 effect to happen or for the change to be rejected. 4931 effect to happen or for the change to be rejected.
4924 4932
4925 The callbacks are named and associated with a function using the 4933 The callbacks are named and associated with a function using the
4926 U_BOOT_ENV_CALLBACK macro in your board or driver code. 4934 U_BOOT_ENV_CALLBACK macro in your board or driver code.
4927 4935
4928 These callbacks are associated with variables in one of two ways. The 4936 These callbacks are associated with variables in one of two ways. The
4929 static list can be added to by defining CONFIG_ENV_CALLBACK_LIST_STATIC 4937 static list can be added to by defining CONFIG_ENV_CALLBACK_LIST_STATIC
4930 in the board configuration to a string that defines a list of 4938 in the board configuration to a string that defines a list of
4931 associations. The list must be in the following format: 4939 associations. The list must be in the following format:
4932 4940
4933 entry = variable_name[:callback_name] 4941 entry = variable_name[:callback_name]
4934 list = entry[,list] 4942 list = entry[,list]
4935 4943
4936 If the callback name is not specified, then the callback is deleted. 4944 If the callback name is not specified, then the callback is deleted.
4937 Spaces are also allowed anywhere in the list. 4945 Spaces are also allowed anywhere in the list.
4938 4946
4939 Callbacks can also be associated by defining the ".callbacks" variable 4947 Callbacks can also be associated by defining the ".callbacks" variable
4940 with the same list format above. Any association in ".callbacks" will 4948 with the same list format above. Any association in ".callbacks" will
4941 override any association in the static list. You can define 4949 override any association in the static list. You can define
4942 CONFIG_ENV_CALLBACK_LIST_DEFAULT to a list (string) to define the 4950 CONFIG_ENV_CALLBACK_LIST_DEFAULT to a list (string) to define the
4943 ".callbacks" envirnoment variable in the default or embedded environment. 4951 ".callbacks" envirnoment variable in the default or embedded environment.
4944 4952
4945 4953
4946 Command Line Parsing: 4954 Command Line Parsing:
4947 ===================== 4955 =====================
4948 4956
4949 There are two different command line parsers available with U-Boot: 4957 There are two different command line parsers available with U-Boot:
4950 the old "simple" one, and the much more powerful "hush" shell: 4958 the old "simple" one, and the much more powerful "hush" shell:
4951 4959
4952 Old, simple command line parser: 4960 Old, simple command line parser:
4953 -------------------------------- 4961 --------------------------------
4954 4962
4955 - supports environment variables (through setenv / saveenv commands) 4963 - supports environment variables (through setenv / saveenv commands)
4956 - several commands on one line, separated by ';' 4964 - several commands on one line, separated by ';'
4957 - variable substitution using "... ${name} ..." syntax 4965 - variable substitution using "... ${name} ..." syntax
4958 - special characters ('$', ';') can be escaped by prefixing with '\', 4966 - special characters ('$', ';') can be escaped by prefixing with '\',
4959 for example: 4967 for example:
4960 setenv bootcmd bootm \${address} 4968 setenv bootcmd bootm \${address}
4961 - You can also escape text by enclosing in single apostrophes, for example: 4969 - You can also escape text by enclosing in single apostrophes, for example:
4962 setenv addip 'setenv bootargs $bootargs ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off' 4970 setenv addip 'setenv bootargs $bootargs ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off'
4963 4971
4964 Hush shell: 4972 Hush shell:
4965 ----------- 4973 -----------
4966 4974
4967 - similar to Bourne shell, with control structures like 4975 - similar to Bourne shell, with control structures like
4968 if...then...else...fi, for...do...done; while...do...done, 4976 if...then...else...fi, for...do...done; while...do...done,
4969 until...do...done, ... 4977 until...do...done, ...
4970 - supports environment ("global") variables (through setenv / saveenv 4978 - supports environment ("global") variables (through setenv / saveenv
4971 commands) and local shell variables (through standard shell syntax 4979 commands) and local shell variables (through standard shell syntax
4972 "name=value"); only environment variables can be used with "run" 4980 "name=value"); only environment variables can be used with "run"
4973 command 4981 command
4974 4982
4975 General rules: 4983 General rules:
4976 -------------- 4984 --------------
4977 4985
4978 (1) If a command line (or an environment variable executed by a "run" 4986 (1) If a command line (or an environment variable executed by a "run"
4979 command) contains several commands separated by semicolon, and 4987 command) contains several commands separated by semicolon, and
4980 one of these commands fails, then the remaining commands will be 4988 one of these commands fails, then the remaining commands will be
4981 executed anyway. 4989 executed anyway.
4982 4990
4983 (2) If you execute several variables with one call to run (i. e. 4991 (2) If you execute several variables with one call to run (i. e.
4984 calling run with a list of variables as arguments), any failing 4992 calling run with a list of variables as arguments), any failing
4985 command will cause "run" to terminate, i. e. the remaining 4993 command will cause "run" to terminate, i. e. the remaining
4986 variables are not executed. 4994 variables are not executed.
4987 4995
4988 Note for Redundant Ethernet Interfaces: 4996 Note for Redundant Ethernet Interfaces:
4989 ======================================= 4997 =======================================
4990 4998
4991 Some boards come with redundant Ethernet interfaces; U-Boot supports 4999 Some boards come with redundant Ethernet interfaces; U-Boot supports
4992 such configurations and is capable of automatic selection of a 5000 such configurations and is capable of automatic selection of a
4993 "working" interface when needed. MAC assignment works as follows: 5001 "working" interface when needed. MAC assignment works as follows:
4994 5002
4995 Network interfaces are numbered eth0, eth1, eth2, ... Corresponding 5003 Network interfaces are numbered eth0, eth1, eth2, ... Corresponding
4996 MAC addresses can be stored in the environment as "ethaddr" (=>eth0), 5004 MAC addresses can be stored in the environment as "ethaddr" (=>eth0),
4997 "eth1addr" (=>eth1), "eth2addr", ... 5005 "eth1addr" (=>eth1), "eth2addr", ...
4998 5006
4999 If the network interface stores some valid MAC address (for instance 5007 If the network interface stores some valid MAC address (for instance
5000 in SROM), this is used as default address if there is NO correspon- 5008 in SROM), this is used as default address if there is NO correspon-
5001 ding setting in the environment; if the corresponding environment 5009 ding setting in the environment; if the corresponding environment
5002 variable is set, this overrides the settings in the card; that means: 5010 variable is set, this overrides the settings in the card; that means:
5003 5011
5004 o If the SROM has a valid MAC address, and there is no address in the 5012 o If the SROM has a valid MAC address, and there is no address in the
5005 environment, the SROM's address is used. 5013 environment, the SROM's address is used.
5006 5014
5007 o If there is no valid address in the SROM, and a definition in the 5015 o If there is no valid address in the SROM, and a definition in the
5008 environment exists, then the value from the environment variable is 5016 environment exists, then the value from the environment variable is
5009 used. 5017 used.
5010 5018
5011 o If both the SROM and the environment contain a MAC address, and 5019 o If both the SROM and the environment contain a MAC address, and
5012 both addresses are the same, this MAC address is used. 5020 both addresses are the same, this MAC address is used.
5013 5021
5014 o If both the SROM and the environment contain a MAC address, and the 5022 o If both the SROM and the environment contain a MAC address, and the
5015 addresses differ, the value from the environment is used and a 5023 addresses differ, the value from the environment is used and a
5016 warning is printed. 5024 warning is printed.
5017 5025
5018 o If neither SROM nor the environment contain a MAC address, an error 5026 o If neither SROM nor the environment contain a MAC address, an error
5019 is raised. 5027 is raised.
5020 5028
5021 If Ethernet drivers implement the 'write_hwaddr' function, valid MAC addresses 5029 If Ethernet drivers implement the 'write_hwaddr' function, valid MAC addresses
5022 will be programmed into hardware as part of the initialization process. This 5030 will be programmed into hardware as part of the initialization process. This
5023 may be skipped by setting the appropriate 'ethmacskip' environment variable. 5031 may be skipped by setting the appropriate 'ethmacskip' environment variable.
5024 The naming convention is as follows: 5032 The naming convention is as follows:
5025 "ethmacskip" (=>eth0), "eth1macskip" (=>eth1) etc. 5033 "ethmacskip" (=>eth0), "eth1macskip" (=>eth1) etc.
5026 5034
5027 Image Formats: 5035 Image Formats:
5028 ============== 5036 ==============
5029 5037
5030 U-Boot is capable of booting (and performing other auxiliary operations on) 5038 U-Boot is capable of booting (and performing other auxiliary operations on)
5031 images in two formats: 5039 images in two formats:
5032 5040
5033 New uImage format (FIT) 5041 New uImage format (FIT)
5034 ----------------------- 5042 -----------------------
5035 5043
5036 Flexible and powerful format based on Flattened Image Tree -- FIT (similar 5044 Flexible and powerful format based on Flattened Image Tree -- FIT (similar
5037 to Flattened Device Tree). It allows the use of images with multiple 5045 to Flattened Device Tree). It allows the use of images with multiple
5038 components (several kernels, ramdisks, etc.), with contents protected by 5046 components (several kernels, ramdisks, etc.), with contents protected by
5039 SHA1, MD5 or CRC32. More details are found in the doc/uImage.FIT directory. 5047 SHA1, MD5 or CRC32. More details are found in the doc/uImage.FIT directory.
5040 5048
5041 5049
5042 Old uImage format 5050 Old uImage format
5043 ----------------- 5051 -----------------
5044 5052
5045 Old image format is based on binary files which can be basically anything, 5053 Old image format is based on binary files which can be basically anything,
5046 preceded by a special header; see the definitions in include/image.h for 5054 preceded by a special header; see the definitions in include/image.h for
5047 details; basically, the header defines the following image properties: 5055 details; basically, the header defines the following image properties:
5048 5056
5049 * Target Operating System (Provisions for OpenBSD, NetBSD, FreeBSD, 5057 * Target Operating System (Provisions for OpenBSD, NetBSD, FreeBSD,
5050 4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks, 5058 4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks,
5051 LynxOS, pSOS, QNX, RTEMS, INTEGRITY; 5059 LynxOS, pSOS, QNX, RTEMS, INTEGRITY;
5052 Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS, 5060 Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
5053 INTEGRITY). 5061 INTEGRITY).
5054 * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86, 5062 * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
5055 IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit; 5063 IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
5056 Currently supported: ARM, AVR32, Intel x86, MIPS, NDS32, Nios II, PowerPC). 5064 Currently supported: ARM, AVR32, Intel x86, MIPS, NDS32, Nios II, PowerPC).
5057 * Compression Type (uncompressed, gzip, bzip2) 5065 * Compression Type (uncompressed, gzip, bzip2)
5058 * Load Address 5066 * Load Address
5059 * Entry Point 5067 * Entry Point
5060 * Image Name 5068 * Image Name
5061 * Image Timestamp 5069 * Image Timestamp
5062 5070
5063 The header is marked by a special Magic Number, and both the header 5071 The header is marked by a special Magic Number, and both the header
5064 and the data portions of the image are secured against corruption by 5072 and the data portions of the image are secured against corruption by
5065 CRC32 checksums. 5073 CRC32 checksums.
5066 5074
5067 5075
5068 Linux Support: 5076 Linux Support:
5069 ============== 5077 ==============
5070 5078
5071 Although U-Boot should support any OS or standalone application 5079 Although U-Boot should support any OS or standalone application
5072 easily, the main focus has always been on Linux during the design of 5080 easily, the main focus has always been on Linux during the design of
5073 U-Boot. 5081 U-Boot.
5074 5082
5075 U-Boot includes many features that so far have been part of some 5083 U-Boot includes many features that so far have been part of some
5076 special "boot loader" code within the Linux kernel. Also, any 5084 special "boot loader" code within the Linux kernel. Also, any
5077 "initrd" images to be used are no longer part of one big Linux image; 5085 "initrd" images to be used are no longer part of one big Linux image;
5078 instead, kernel and "initrd" are separate images. This implementation 5086 instead, kernel and "initrd" are separate images. This implementation
5079 serves several purposes: 5087 serves several purposes:
5080 5088
5081 - the same features can be used for other OS or standalone 5089 - the same features can be used for other OS or standalone
5082 applications (for instance: using compressed images to reduce the 5090 applications (for instance: using compressed images to reduce the
5083 Flash memory footprint) 5091 Flash memory footprint)
5084 5092
5085 - it becomes much easier to port new Linux kernel versions because 5093 - it becomes much easier to port new Linux kernel versions because
5086 lots of low-level, hardware dependent stuff are done by U-Boot 5094 lots of low-level, hardware dependent stuff are done by U-Boot
5087 5095
5088 - the same Linux kernel image can now be used with different "initrd" 5096 - the same Linux kernel image can now be used with different "initrd"
5089 images; of course this also means that different kernel images can 5097 images; of course this also means that different kernel images can
5090 be run with the same "initrd". This makes testing easier (you don't 5098 be run with the same "initrd". This makes testing easier (you don't
5091 have to build a new "zImage.initrd" Linux image when you just 5099 have to build a new "zImage.initrd" Linux image when you just
5092 change a file in your "initrd"). Also, a field-upgrade of the 5100 change a file in your "initrd"). Also, a field-upgrade of the
5093 software is easier now. 5101 software is easier now.
5094 5102
5095 5103
5096 Linux HOWTO: 5104 Linux HOWTO:
5097 ============ 5105 ============
5098 5106
5099 Porting Linux to U-Boot based systems: 5107 Porting Linux to U-Boot based systems:
5100 --------------------------------------- 5108 ---------------------------------------
5101 5109
5102 U-Boot cannot save you from doing all the necessary modifications to 5110 U-Boot cannot save you from doing all the necessary modifications to
5103 configure the Linux device drivers for use with your target hardware 5111 configure the Linux device drivers for use with your target hardware
5104 (no, we don't intend to provide a full virtual machine interface to 5112 (no, we don't intend to provide a full virtual machine interface to
5105 Linux :-). 5113 Linux :-).
5106 5114
5107 But now you can ignore ALL boot loader code (in arch/powerpc/mbxboot). 5115 But now you can ignore ALL boot loader code (in arch/powerpc/mbxboot).
5108 5116
5109 Just make sure your machine specific header file (for instance 5117 Just make sure your machine specific header file (for instance
5110 include/asm-ppc/tqm8xx.h) includes the same definition of the Board 5118 include/asm-ppc/tqm8xx.h) includes the same definition of the Board
5111 Information structure as we define in include/asm-<arch>/u-boot.h, 5119 Information structure as we define in include/asm-<arch>/u-boot.h,
5112 and make sure that your definition of IMAP_ADDR uses the same value 5120 and make sure that your definition of IMAP_ADDR uses the same value
5113 as your U-Boot configuration in CONFIG_SYS_IMMR. 5121 as your U-Boot configuration in CONFIG_SYS_IMMR.
5114 5122
5115 5123
5116 Configuring the Linux kernel: 5124 Configuring the Linux kernel:
5117 ----------------------------- 5125 -----------------------------
5118 5126
5119 No specific requirements for U-Boot. Make sure you have some root 5127 No specific requirements for U-Boot. Make sure you have some root
5120 device (initial ramdisk, NFS) for your target system. 5128 device (initial ramdisk, NFS) for your target system.
5121 5129
5122 5130
5123 Building a Linux Image: 5131 Building a Linux Image:
5124 ----------------------- 5132 -----------------------
5125 5133
5126 With U-Boot, "normal" build targets like "zImage" or "bzImage" are 5134 With U-Boot, "normal" build targets like "zImage" or "bzImage" are
5127 not used. If you use recent kernel source, a new build target 5135 not used. If you use recent kernel source, a new build target
5128 "uImage" will exist which automatically builds an image usable by 5136 "uImage" will exist which automatically builds an image usable by
5129 U-Boot. Most older kernels also have support for a "pImage" target, 5137 U-Boot. Most older kernels also have support for a "pImage" target,
5130 which was introduced for our predecessor project PPCBoot and uses a 5138 which was introduced for our predecessor project PPCBoot and uses a
5131 100% compatible format. 5139 100% compatible format.
5132 5140
5133 Example: 5141 Example:
5134 5142
5135 make TQM850L_config 5143 make TQM850L_config
5136 make oldconfig 5144 make oldconfig
5137 make dep 5145 make dep
5138 make uImage 5146 make uImage
5139 5147
5140 The "uImage" build target uses a special tool (in 'tools/mkimage') to 5148 The "uImage" build target uses a special tool (in 'tools/mkimage') to
5141 encapsulate a compressed Linux kernel image with header information, 5149 encapsulate a compressed Linux kernel image with header information,
5142 CRC32 checksum etc. for use with U-Boot. This is what we are doing: 5150 CRC32 checksum etc. for use with U-Boot. This is what we are doing:
5143 5151
5144 * build a standard "vmlinux" kernel image (in ELF binary format): 5152 * build a standard "vmlinux" kernel image (in ELF binary format):
5145 5153
5146 * convert the kernel into a raw binary image: 5154 * convert the kernel into a raw binary image:
5147 5155
5148 ${CROSS_COMPILE}-objcopy -O binary \ 5156 ${CROSS_COMPILE}-objcopy -O binary \
5149 -R .note -R .comment \ 5157 -R .note -R .comment \
5150 -S vmlinux linux.bin 5158 -S vmlinux linux.bin
5151 5159
5152 * compress the binary image: 5160 * compress the binary image:
5153 5161
5154 gzip -9 linux.bin 5162 gzip -9 linux.bin
5155 5163
5156 * package compressed binary image for U-Boot: 5164 * package compressed binary image for U-Boot:
5157 5165
5158 mkimage -A ppc -O linux -T kernel -C gzip \ 5166 mkimage -A ppc -O linux -T kernel -C gzip \
5159 -a 0 -e 0 -n "Linux Kernel Image" \ 5167 -a 0 -e 0 -n "Linux Kernel Image" \
5160 -d linux.bin.gz uImage 5168 -d linux.bin.gz uImage
5161 5169
5162 5170
5163 The "mkimage" tool can also be used to create ramdisk images for use 5171 The "mkimage" tool can also be used to create ramdisk images for use
5164 with U-Boot, either separated from the Linux kernel image, or 5172 with U-Boot, either separated from the Linux kernel image, or
5165 combined into one file. "mkimage" encapsulates the images with a 64 5173 combined into one file. "mkimage" encapsulates the images with a 64
5166 byte header containing information about target architecture, 5174 byte header containing information about target architecture,
5167 operating system, image type, compression method, entry points, time 5175 operating system, image type, compression method, entry points, time
5168 stamp, CRC32 checksums, etc. 5176 stamp, CRC32 checksums, etc.
5169 5177
5170 "mkimage" can be called in two ways: to verify existing images and 5178 "mkimage" can be called in two ways: to verify existing images and
5171 print the header information, or to build new images. 5179 print the header information, or to build new images.
5172 5180
5173 In the first form (with "-l" option) mkimage lists the information 5181 In the first form (with "-l" option) mkimage lists the information
5174 contained in the header of an existing U-Boot image; this includes 5182 contained in the header of an existing U-Boot image; this includes
5175 checksum verification: 5183 checksum verification:
5176 5184
5177 tools/mkimage -l image 5185 tools/mkimage -l image
5178 -l ==> list image header information 5186 -l ==> list image header information
5179 5187
5180 The second form (with "-d" option) is used to build a U-Boot image 5188 The second form (with "-d" option) is used to build a U-Boot image
5181 from a "data file" which is used as image payload: 5189 from a "data file" which is used as image payload:
5182 5190
5183 tools/mkimage -A arch -O os -T type -C comp -a addr -e ep \ 5191 tools/mkimage -A arch -O os -T type -C comp -a addr -e ep \
5184 -n name -d data_file image 5192 -n name -d data_file image
5185 -A ==> set architecture to 'arch' 5193 -A ==> set architecture to 'arch'
5186 -O ==> set operating system to 'os' 5194 -O ==> set operating system to 'os'
5187 -T ==> set image type to 'type' 5195 -T ==> set image type to 'type'
5188 -C ==> set compression type 'comp' 5196 -C ==> set compression type 'comp'
5189 -a ==> set load address to 'addr' (hex) 5197 -a ==> set load address to 'addr' (hex)
5190 -e ==> set entry point to 'ep' (hex) 5198 -e ==> set entry point to 'ep' (hex)
5191 -n ==> set image name to 'name' 5199 -n ==> set image name to 'name'
5192 -d ==> use image data from 'datafile' 5200 -d ==> use image data from 'datafile'
5193 5201
5194 Right now, all Linux kernels for PowerPC systems use the same load 5202 Right now, all Linux kernels for PowerPC systems use the same load
5195 address (0x00000000), but the entry point address depends on the 5203 address (0x00000000), but the entry point address depends on the
5196 kernel version: 5204 kernel version:
5197 5205
5198 - 2.2.x kernels have the entry point at 0x0000000C, 5206 - 2.2.x kernels have the entry point at 0x0000000C,
5199 - 2.3.x and later kernels have the entry point at 0x00000000. 5207 - 2.3.x and later kernels have the entry point at 0x00000000.
5200 5208
5201 So a typical call to build a U-Boot image would read: 5209 So a typical call to build a U-Boot image would read:
5202 5210
5203 -> tools/mkimage -n '2.4.4 kernel for TQM850L' \ 5211 -> tools/mkimage -n '2.4.4 kernel for TQM850L' \
5204 > -A ppc -O linux -T kernel -C gzip -a 0 -e 0 \ 5212 > -A ppc -O linux -T kernel -C gzip -a 0 -e 0 \
5205 > -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz \ 5213 > -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz \
5206 > examples/uImage.TQM850L 5214 > examples/uImage.TQM850L
5207 Image Name: 2.4.4 kernel for TQM850L 5215 Image Name: 2.4.4 kernel for TQM850L
5208 Created: Wed Jul 19 02:34:59 2000 5216 Created: Wed Jul 19 02:34:59 2000
5209 Image Type: PowerPC Linux Kernel Image (gzip compressed) 5217 Image Type: PowerPC Linux Kernel Image (gzip compressed)
5210 Data Size: 335725 Bytes = 327.86 kB = 0.32 MB 5218 Data Size: 335725 Bytes = 327.86 kB = 0.32 MB
5211 Load Address: 0x00000000 5219 Load Address: 0x00000000
5212 Entry Point: 0x00000000 5220 Entry Point: 0x00000000
5213 5221
5214 To verify the contents of the image (or check for corruption): 5222 To verify the contents of the image (or check for corruption):
5215 5223
5216 -> tools/mkimage -l examples/uImage.TQM850L 5224 -> tools/mkimage -l examples/uImage.TQM850L
5217 Image Name: 2.4.4 kernel for TQM850L 5225 Image Name: 2.4.4 kernel for TQM850L
5218 Created: Wed Jul 19 02:34:59 2000 5226 Created: Wed Jul 19 02:34:59 2000
5219 Image Type: PowerPC Linux Kernel Image (gzip compressed) 5227 Image Type: PowerPC Linux Kernel Image (gzip compressed)
5220 Data Size: 335725 Bytes = 327.86 kB = 0.32 MB 5228 Data Size: 335725 Bytes = 327.86 kB = 0.32 MB
5221 Load Address: 0x00000000 5229 Load Address: 0x00000000
5222 Entry Point: 0x00000000 5230 Entry Point: 0x00000000
5223 5231
5224 NOTE: for embedded systems where boot time is critical you can trade 5232 NOTE: for embedded systems where boot time is critical you can trade
5225 speed for memory and install an UNCOMPRESSED image instead: this 5233 speed for memory and install an UNCOMPRESSED image instead: this
5226 needs more space in Flash, but boots much faster since it does not 5234 needs more space in Flash, but boots much faster since it does not
5227 need to be uncompressed: 5235 need to be uncompressed:
5228 5236
5229 -> gunzip /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz 5237 -> gunzip /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz
5230 -> tools/mkimage -n '2.4.4 kernel for TQM850L' \ 5238 -> tools/mkimage -n '2.4.4 kernel for TQM850L' \
5231 > -A ppc -O linux -T kernel -C none -a 0 -e 0 \ 5239 > -A ppc -O linux -T kernel -C none -a 0 -e 0 \
5232 > -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux \ 5240 > -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux \
5233 > examples/uImage.TQM850L-uncompressed 5241 > examples/uImage.TQM850L-uncompressed
5234 Image Name: 2.4.4 kernel for TQM850L 5242 Image Name: 2.4.4 kernel for TQM850L
5235 Created: Wed Jul 19 02:34:59 2000 5243 Created: Wed Jul 19 02:34:59 2000
5236 Image Type: PowerPC Linux Kernel Image (uncompressed) 5244 Image Type: PowerPC Linux Kernel Image (uncompressed)
5237 Data Size: 792160 Bytes = 773.59 kB = 0.76 MB 5245 Data Size: 792160 Bytes = 773.59 kB = 0.76 MB
5238 Load Address: 0x00000000 5246 Load Address: 0x00000000
5239 Entry Point: 0x00000000 5247 Entry Point: 0x00000000
5240 5248
5241 5249
5242 Similar you can build U-Boot images from a 'ramdisk.image.gz' file 5250 Similar you can build U-Boot images from a 'ramdisk.image.gz' file
5243 when your kernel is intended to use an initial ramdisk: 5251 when your kernel is intended to use an initial ramdisk:
5244 5252
5245 -> tools/mkimage -n 'Simple Ramdisk Image' \ 5253 -> tools/mkimage -n 'Simple Ramdisk Image' \
5246 > -A ppc -O linux -T ramdisk -C gzip \ 5254 > -A ppc -O linux -T ramdisk -C gzip \
5247 > -d /LinuxPPC/images/SIMPLE-ramdisk.image.gz examples/simple-initrd 5255 > -d /LinuxPPC/images/SIMPLE-ramdisk.image.gz examples/simple-initrd
5248 Image Name: Simple Ramdisk Image 5256 Image Name: Simple Ramdisk Image
5249 Created: Wed Jan 12 14:01:50 2000 5257 Created: Wed Jan 12 14:01:50 2000
5250 Image Type: PowerPC Linux RAMDisk Image (gzip compressed) 5258 Image Type: PowerPC Linux RAMDisk Image (gzip compressed)
5251 Data Size: 566530 Bytes = 553.25 kB = 0.54 MB 5259 Data Size: 566530 Bytes = 553.25 kB = 0.54 MB
5252 Load Address: 0x00000000 5260 Load Address: 0x00000000
5253 Entry Point: 0x00000000 5261 Entry Point: 0x00000000
5254 5262
5255 The "dumpimage" is a tool to disassemble images built by mkimage. Its "-i" 5263 The "dumpimage" is a tool to disassemble images built by mkimage. Its "-i"
5256 option performs the converse operation of the mkimage's second form (the "-d" 5264 option performs the converse operation of the mkimage's second form (the "-d"
5257 option). Given an image built by mkimage, the dumpimage extracts a "data file" 5265 option). Given an image built by mkimage, the dumpimage extracts a "data file"
5258 from the image: 5266 from the image:
5259 5267
5260 tools/dumpimage -i image -p position data_file 5268 tools/dumpimage -i image -p position data_file
5261 -i ==> extract from the 'image' a specific 'data_file', \ 5269 -i ==> extract from the 'image' a specific 'data_file', \
5262 indexed by 'position' 5270 indexed by 'position'
5263 5271
5264 5272
5265 Installing a Linux Image: 5273 Installing a Linux Image:
5266 ------------------------- 5274 -------------------------
5267 5275
5268 To downloading a U-Boot image over the serial (console) interface, 5276 To downloading a U-Boot image over the serial (console) interface,
5269 you must convert the image to S-Record format: 5277 you must convert the image to S-Record format:
5270 5278
5271 objcopy -I binary -O srec examples/image examples/image.srec 5279 objcopy -I binary -O srec examples/image examples/image.srec
5272 5280
5273 The 'objcopy' does not understand the information in the U-Boot 5281 The 'objcopy' does not understand the information in the U-Boot
5274 image header, so the resulting S-Record file will be relative to 5282 image header, so the resulting S-Record file will be relative to
5275 address 0x00000000. To load it to a given address, you need to 5283 address 0x00000000. To load it to a given address, you need to
5276 specify the target address as 'offset' parameter with the 'loads' 5284 specify the target address as 'offset' parameter with the 'loads'
5277 command. 5285 command.
5278 5286
5279 Example: install the image to address 0x40100000 (which on the 5287 Example: install the image to address 0x40100000 (which on the
5280 TQM8xxL is in the first Flash bank): 5288 TQM8xxL is in the first Flash bank):
5281 5289
5282 => erase 40100000 401FFFFF 5290 => erase 40100000 401FFFFF
5283 5291
5284 .......... done 5292 .......... done
5285 Erased 8 sectors 5293 Erased 8 sectors
5286 5294
5287 => loads 40100000 5295 => loads 40100000
5288 ## Ready for S-Record download ... 5296 ## Ready for S-Record download ...
5289 ~>examples/image.srec 5297 ~>examples/image.srec
5290 1 2 3 4 5 6 7 8 9 10 11 12 13 ... 5298 1 2 3 4 5 6 7 8 9 10 11 12 13 ...
5291 ... 5299 ...
5292 15989 15990 15991 15992 5300 15989 15990 15991 15992
5293 [file transfer complete] 5301 [file transfer complete]
5294 [connected] 5302 [connected]
5295 ## Start Addr = 0x00000000 5303 ## Start Addr = 0x00000000
5296 5304
5297 5305
5298 You can check the success of the download using the 'iminfo' command; 5306 You can check the success of the download using the 'iminfo' command;
5299 this includes a checksum verification so you can be sure no data 5307 this includes a checksum verification so you can be sure no data
5300 corruption happened: 5308 corruption happened:
5301 5309
5302 => imi 40100000 5310 => imi 40100000
5303 5311
5304 ## Checking Image at 40100000 ... 5312 ## Checking Image at 40100000 ...
5305 Image Name: 2.2.13 for initrd on TQM850L 5313 Image Name: 2.2.13 for initrd on TQM850L
5306 Image Type: PowerPC Linux Kernel Image (gzip compressed) 5314 Image Type: PowerPC Linux Kernel Image (gzip compressed)
5307 Data Size: 335725 Bytes = 327 kB = 0 MB 5315 Data Size: 335725 Bytes = 327 kB = 0 MB
5308 Load Address: 00000000 5316 Load Address: 00000000
5309 Entry Point: 0000000c 5317 Entry Point: 0000000c
5310 Verifying Checksum ... OK 5318 Verifying Checksum ... OK
5311 5319
5312 5320
5313 Boot Linux: 5321 Boot Linux:
5314 ----------- 5322 -----------
5315 5323
5316 The "bootm" command is used to boot an application that is stored in 5324 The "bootm" command is used to boot an application that is stored in
5317 memory (RAM or Flash). In case of a Linux kernel image, the contents 5325 memory (RAM or Flash). In case of a Linux kernel image, the contents
5318 of the "bootargs" environment variable is passed to the kernel as 5326 of the "bootargs" environment variable is passed to the kernel as
5319 parameters. You can check and modify this variable using the 5327 parameters. You can check and modify this variable using the
5320 "printenv" and "setenv" commands: 5328 "printenv" and "setenv" commands:
5321 5329
5322 5330
5323 => printenv bootargs 5331 => printenv bootargs
5324 bootargs=root=/dev/ram 5332 bootargs=root=/dev/ram
5325 5333
5326 => setenv bootargs root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2 5334 => setenv bootargs root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2
5327 5335
5328 => printenv bootargs 5336 => printenv bootargs
5329 bootargs=root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2 5337 bootargs=root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2
5330 5338
5331 => bootm 40020000 5339 => bootm 40020000
5332 ## Booting Linux kernel at 40020000 ... 5340 ## Booting Linux kernel at 40020000 ...
5333 Image Name: 2.2.13 for NFS on TQM850L 5341 Image Name: 2.2.13 for NFS on TQM850L
5334 Image Type: PowerPC Linux Kernel Image (gzip compressed) 5342 Image Type: PowerPC Linux Kernel Image (gzip compressed)
5335 Data Size: 381681 Bytes = 372 kB = 0 MB 5343 Data Size: 381681 Bytes = 372 kB = 0 MB
5336 Load Address: 00000000 5344 Load Address: 00000000
5337 Entry Point: 0000000c 5345 Entry Point: 0000000c
5338 Verifying Checksum ... OK 5346 Verifying Checksum ... OK
5339 Uncompressing Kernel Image ... OK 5347 Uncompressing Kernel Image ... OK
5340 Linux version 2.2.13 (wd@denx.local.net) (gcc version 2.95.2 19991024 (release)) #1 Wed Jul 19 02:35:17 MEST 2000 5348 Linux version 2.2.13 (wd@denx.local.net) (gcc version 2.95.2 19991024 (release)) #1 Wed Jul 19 02:35:17 MEST 2000
5341 Boot arguments: root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2 5349 Boot arguments: root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2
5342 time_init: decrementer frequency = 187500000/60 5350 time_init: decrementer frequency = 187500000/60
5343 Calibrating delay loop... 49.77 BogoMIPS 5351 Calibrating delay loop... 49.77 BogoMIPS
5344 Memory: 15208k available (700k kernel code, 444k data, 32k init) [c0000000,c1000000] 5352 Memory: 15208k available (700k kernel code, 444k data, 32k init) [c0000000,c1000000]
5345 ... 5353 ...
5346 5354
5347 If you want to boot a Linux kernel with initial RAM disk, you pass 5355 If you want to boot a Linux kernel with initial RAM disk, you pass
5348 the memory addresses of both the kernel and the initrd image (PPBCOOT 5356 the memory addresses of both the kernel and the initrd image (PPBCOOT
5349 format!) to the "bootm" command: 5357 format!) to the "bootm" command:
5350 5358
5351 => imi 40100000 40200000 5359 => imi 40100000 40200000
5352 5360
5353 ## Checking Image at 40100000 ... 5361 ## Checking Image at 40100000 ...
5354 Image Name: 2.2.13 for initrd on TQM850L 5362 Image Name: 2.2.13 for initrd on TQM850L
5355 Image Type: PowerPC Linux Kernel Image (gzip compressed) 5363 Image Type: PowerPC Linux Kernel Image (gzip compressed)
5356 Data Size: 335725 Bytes = 327 kB = 0 MB 5364 Data Size: 335725 Bytes = 327 kB = 0 MB
5357 Load Address: 00000000 5365 Load Address: 00000000
5358 Entry Point: 0000000c 5366 Entry Point: 0000000c
5359 Verifying Checksum ... OK 5367 Verifying Checksum ... OK
5360 5368
5361 ## Checking Image at 40200000 ... 5369 ## Checking Image at 40200000 ...
5362 Image Name: Simple Ramdisk Image 5370 Image Name: Simple Ramdisk Image
5363 Image Type: PowerPC Linux RAMDisk Image (gzip compressed) 5371 Image Type: PowerPC Linux RAMDisk Image (gzip compressed)
5364 Data Size: 566530 Bytes = 553 kB = 0 MB 5372 Data Size: 566530 Bytes = 553 kB = 0 MB
5365 Load Address: 00000000 5373 Load Address: 00000000
5366 Entry Point: 00000000 5374 Entry Point: 00000000
5367 Verifying Checksum ... OK 5375 Verifying Checksum ... OK
5368 5376
5369 => bootm 40100000 40200000 5377 => bootm 40100000 40200000
5370 ## Booting Linux kernel at 40100000 ... 5378 ## Booting Linux kernel at 40100000 ...
5371 Image Name: 2.2.13 for initrd on TQM850L 5379 Image Name: 2.2.13 for initrd on TQM850L
5372 Image Type: PowerPC Linux Kernel Image (gzip compressed) 5380 Image Type: PowerPC Linux Kernel Image (gzip compressed)
5373 Data Size: 335725 Bytes = 327 kB = 0 MB 5381 Data Size: 335725 Bytes = 327 kB = 0 MB
5374 Load Address: 00000000 5382 Load Address: 00000000
5375 Entry Point: 0000000c 5383 Entry Point: 0000000c
5376 Verifying Checksum ... OK 5384 Verifying Checksum ... OK
5377 Uncompressing Kernel Image ... OK 5385 Uncompressing Kernel Image ... OK
5378 ## Loading RAMDisk Image at 40200000 ... 5386 ## Loading RAMDisk Image at 40200000 ...
5379 Image Name: Simple Ramdisk Image 5387 Image Name: Simple Ramdisk Image
5380 Image Type: PowerPC Linux RAMDisk Image (gzip compressed) 5388 Image Type: PowerPC Linux RAMDisk Image (gzip compressed)
5381 Data Size: 566530 Bytes = 553 kB = 0 MB 5389 Data Size: 566530 Bytes = 553 kB = 0 MB
5382 Load Address: 00000000 5390 Load Address: 00000000
5383 Entry Point: 00000000 5391 Entry Point: 00000000
5384 Verifying Checksum ... OK 5392 Verifying Checksum ... OK
5385 Loading Ramdisk ... OK 5393 Loading Ramdisk ... OK
5386 Linux version 2.2.13 (wd@denx.local.net) (gcc version 2.95.2 19991024 (release)) #1 Wed Jul 19 02:32:08 MEST 2000 5394 Linux version 2.2.13 (wd@denx.local.net) (gcc version 2.95.2 19991024 (release)) #1 Wed Jul 19 02:32:08 MEST 2000
5387 Boot arguments: root=/dev/ram 5395 Boot arguments: root=/dev/ram
5388 time_init: decrementer frequency = 187500000/60 5396 time_init: decrementer frequency = 187500000/60
5389 Calibrating delay loop... 49.77 BogoMIPS 5397 Calibrating delay loop... 49.77 BogoMIPS
5390 ... 5398 ...
5391 RAMDISK: Compressed image found at block 0 5399 RAMDISK: Compressed image found at block 0
5392 VFS: Mounted root (ext2 filesystem). 5400 VFS: Mounted root (ext2 filesystem).
5393 5401
5394 bash# 5402 bash#
5395 5403
5396 Boot Linux and pass a flat device tree: 5404 Boot Linux and pass a flat device tree:
5397 ----------- 5405 -----------
5398 5406
5399 First, U-Boot must be compiled with the appropriate defines. See the section 5407 First, U-Boot must be compiled with the appropriate defines. See the section
5400 titled "Linux Kernel Interface" above for a more in depth explanation. The 5408 titled "Linux Kernel Interface" above for a more in depth explanation. The
5401 following is an example of how to start a kernel and pass an updated 5409 following is an example of how to start a kernel and pass an updated
5402 flat device tree: 5410 flat device tree:
5403 5411
5404 => print oftaddr 5412 => print oftaddr
5405 oftaddr=0x300000 5413 oftaddr=0x300000
5406 => print oft 5414 => print oft
5407 oft=oftrees/mpc8540ads.dtb 5415 oft=oftrees/mpc8540ads.dtb
5408 => tftp $oftaddr $oft 5416 => tftp $oftaddr $oft
5409 Speed: 1000, full duplex 5417 Speed: 1000, full duplex
5410 Using TSEC0 device 5418 Using TSEC0 device
5411 TFTP from server 192.168.1.1; our IP address is 192.168.1.101 5419 TFTP from server 192.168.1.1; our IP address is 192.168.1.101
5412 Filename 'oftrees/mpc8540ads.dtb'. 5420 Filename 'oftrees/mpc8540ads.dtb'.
5413 Load address: 0x300000 5421 Load address: 0x300000
5414 Loading: # 5422 Loading: #
5415 done 5423 done
5416 Bytes transferred = 4106 (100a hex) 5424 Bytes transferred = 4106 (100a hex)
5417 => tftp $loadaddr $bootfile 5425 => tftp $loadaddr $bootfile
5418 Speed: 1000, full duplex 5426 Speed: 1000, full duplex
5419 Using TSEC0 device 5427 Using TSEC0 device
5420 TFTP from server 192.168.1.1; our IP address is 192.168.1.2 5428 TFTP from server 192.168.1.1; our IP address is 192.168.1.2
5421 Filename 'uImage'. 5429 Filename 'uImage'.
5422 Load address: 0x200000 5430 Load address: 0x200000
5423 Loading:############ 5431 Loading:############
5424 done 5432 done
5425 Bytes transferred = 1029407 (fb51f hex) 5433 Bytes transferred = 1029407 (fb51f hex)
5426 => print loadaddr 5434 => print loadaddr
5427 loadaddr=200000 5435 loadaddr=200000
5428 => print oftaddr 5436 => print oftaddr
5429 oftaddr=0x300000 5437 oftaddr=0x300000
5430 => bootm $loadaddr - $oftaddr 5438 => bootm $loadaddr - $oftaddr
5431 ## Booting image at 00200000 ... 5439 ## Booting image at 00200000 ...
5432 Image Name: Linux-2.6.17-dirty 5440 Image Name: Linux-2.6.17-dirty
5433 Image Type: PowerPC Linux Kernel Image (gzip compressed) 5441 Image Type: PowerPC Linux Kernel Image (gzip compressed)
5434 Data Size: 1029343 Bytes = 1005.2 kB 5442 Data Size: 1029343 Bytes = 1005.2 kB
5435 Load Address: 00000000 5443 Load Address: 00000000
5436 Entry Point: 00000000 5444 Entry Point: 00000000
5437 Verifying Checksum ... OK 5445 Verifying Checksum ... OK
5438 Uncompressing Kernel Image ... OK 5446 Uncompressing Kernel Image ... OK
5439 Booting using flat device tree at 0x300000 5447 Booting using flat device tree at 0x300000
5440 Using MPC85xx ADS machine description 5448 Using MPC85xx ADS machine description
5441 Memory CAM mapping: CAM0=256Mb, CAM1=256Mb, CAM2=0Mb residual: 0Mb 5449 Memory CAM mapping: CAM0=256Mb, CAM1=256Mb, CAM2=0Mb residual: 0Mb
5442 [snip] 5450 [snip]
5443 5451
5444 5452
5445 More About U-Boot Image Types: 5453 More About U-Boot Image Types:
5446 ------------------------------ 5454 ------------------------------
5447 5455
5448 U-Boot supports the following image types: 5456 U-Boot supports the following image types:
5449 5457
5450 "Standalone Programs" are directly runnable in the environment 5458 "Standalone Programs" are directly runnable in the environment
5451 provided by U-Boot; it is expected that (if they behave 5459 provided by U-Boot; it is expected that (if they behave
5452 well) you can continue to work in U-Boot after return from 5460 well) you can continue to work in U-Boot after return from
5453 the Standalone Program. 5461 the Standalone Program.
5454 "OS Kernel Images" are usually images of some Embedded OS which 5462 "OS Kernel Images" are usually images of some Embedded OS which
5455 will take over control completely. Usually these programs 5463 will take over control completely. Usually these programs
5456 will install their own set of exception handlers, device 5464 will install their own set of exception handlers, device
5457 drivers, set up the MMU, etc. - this means, that you cannot 5465 drivers, set up the MMU, etc. - this means, that you cannot
5458 expect to re-enter U-Boot except by resetting the CPU. 5466 expect to re-enter U-Boot except by resetting the CPU.
5459 "RAMDisk Images" are more or less just data blocks, and their 5467 "RAMDisk Images" are more or less just data blocks, and their
5460 parameters (address, size) are passed to an OS kernel that is 5468 parameters (address, size) are passed to an OS kernel that is
5461 being started. 5469 being started.
5462 "Multi-File Images" contain several images, typically an OS 5470 "Multi-File Images" contain several images, typically an OS
5463 (Linux) kernel image and one or more data images like 5471 (Linux) kernel image and one or more data images like
5464 RAMDisks. This construct is useful for instance when you want 5472 RAMDisks. This construct is useful for instance when you want
5465 to boot over the network using BOOTP etc., where the boot 5473 to boot over the network using BOOTP etc., where the boot
5466 server provides just a single image file, but you want to get 5474 server provides just a single image file, but you want to get
5467 for instance an OS kernel and a RAMDisk image. 5475 for instance an OS kernel and a RAMDisk image.
5468 5476
5469 "Multi-File Images" start with a list of image sizes, each 5477 "Multi-File Images" start with a list of image sizes, each
5470 image size (in bytes) specified by an "uint32_t" in network 5478 image size (in bytes) specified by an "uint32_t" in network
5471 byte order. This list is terminated by an "(uint32_t)0". 5479 byte order. This list is terminated by an "(uint32_t)0".
5472 Immediately after the terminating 0 follow the images, one by 5480 Immediately after the terminating 0 follow the images, one by
5473 one, all aligned on "uint32_t" boundaries (size rounded up to 5481 one, all aligned on "uint32_t" boundaries (size rounded up to
5474 a multiple of 4 bytes). 5482 a multiple of 4 bytes).
5475 5483
5476 "Firmware Images" are binary images containing firmware (like 5484 "Firmware Images" are binary images containing firmware (like
5477 U-Boot or FPGA images) which usually will be programmed to 5485 U-Boot or FPGA images) which usually will be programmed to
5478 flash memory. 5486 flash memory.
5479 5487
5480 "Script files" are command sequences that will be executed by 5488 "Script files" are command sequences that will be executed by
5481 U-Boot's command interpreter; this feature is especially 5489 U-Boot's command interpreter; this feature is especially
5482 useful when you configure U-Boot to use a real shell (hush) 5490 useful when you configure U-Boot to use a real shell (hush)
5483 as command interpreter. 5491 as command interpreter.
5484 5492
5485 Booting the Linux zImage: 5493 Booting the Linux zImage:
5486 ------------------------- 5494 -------------------------
5487 5495
5488 On some platforms, it's possible to boot Linux zImage. This is done 5496 On some platforms, it's possible to boot Linux zImage. This is done
5489 using the "bootz" command. The syntax of "bootz" command is the same 5497 using the "bootz" command. The syntax of "bootz" command is the same
5490 as the syntax of "bootm" command. 5498 as the syntax of "bootm" command.
5491 5499
5492 Note, defining the CONFIG_SUPPORT_RAW_INITRD allows user to supply 5500 Note, defining the CONFIG_SUPPORT_RAW_INITRD allows user to supply
5493 kernel with raw initrd images. The syntax is slightly different, the 5501 kernel with raw initrd images. The syntax is slightly different, the
5494 address of the initrd must be augmented by it's size, in the following 5502 address of the initrd must be augmented by it's size, in the following
5495 format: "<initrd addres>:<initrd size>". 5503 format: "<initrd addres>:<initrd size>".
5496 5504
5497 5505
5498 Standalone HOWTO: 5506 Standalone HOWTO:
5499 ================= 5507 =================
5500 5508
5501 One of the features of U-Boot is that you can dynamically load and 5509 One of the features of U-Boot is that you can dynamically load and
5502 run "standalone" applications, which can use some resources of 5510 run "standalone" applications, which can use some resources of
5503 U-Boot like console I/O functions or interrupt services. 5511 U-Boot like console I/O functions or interrupt services.
5504 5512
5505 Two simple examples are included with the sources: 5513 Two simple examples are included with the sources:
5506 5514
5507 "Hello World" Demo: 5515 "Hello World" Demo:
5508 ------------------- 5516 -------------------
5509 5517
5510 'examples/hello_world.c' contains a small "Hello World" Demo 5518 'examples/hello_world.c' contains a small "Hello World" Demo
5511 application; it is automatically compiled when you build U-Boot. 5519 application; it is automatically compiled when you build U-Boot.
5512 It's configured to run at address 0x00040004, so you can play with it 5520 It's configured to run at address 0x00040004, so you can play with it
5513 like that: 5521 like that:
5514 5522
5515 => loads 5523 => loads
5516 ## Ready for S-Record download ... 5524 ## Ready for S-Record download ...
5517 ~>examples/hello_world.srec 5525 ~>examples/hello_world.srec
5518 1 2 3 4 5 6 7 8 9 10 11 ... 5526 1 2 3 4 5 6 7 8 9 10 11 ...
5519 [file transfer complete] 5527 [file transfer complete]
5520 [connected] 5528 [connected]
5521 ## Start Addr = 0x00040004 5529 ## Start Addr = 0x00040004
5522 5530
5523 => go 40004 Hello World! This is a test. 5531 => go 40004 Hello World! This is a test.
5524 ## Starting application at 0x00040004 ... 5532 ## Starting application at 0x00040004 ...
5525 Hello World 5533 Hello World
5526 argc = 7 5534 argc = 7
5527 argv[0] = "40004" 5535 argv[0] = "40004"
5528 argv[1] = "Hello" 5536 argv[1] = "Hello"
5529 argv[2] = "World!" 5537 argv[2] = "World!"
5530 argv[3] = "This" 5538 argv[3] = "This"
5531 argv[4] = "is" 5539 argv[4] = "is"
5532 argv[5] = "a" 5540 argv[5] = "a"
5533 argv[6] = "test." 5541 argv[6] = "test."
5534 argv[7] = "<NULL>" 5542 argv[7] = "<NULL>"
5535 Hit any key to exit ... 5543 Hit any key to exit ...
5536 5544
5537 ## Application terminated, rc = 0x0 5545 ## Application terminated, rc = 0x0
5538 5546
5539 Another example, which demonstrates how to register a CPM interrupt 5547 Another example, which demonstrates how to register a CPM interrupt
5540 handler with the U-Boot code, can be found in 'examples/timer.c'. 5548 handler with the U-Boot code, can be found in 'examples/timer.c'.
5541 Here, a CPM timer is set up to generate an interrupt every second. 5549 Here, a CPM timer is set up to generate an interrupt every second.
5542 The interrupt service routine is trivial, just printing a '.' 5550 The interrupt service routine is trivial, just printing a '.'
5543 character, but this is just a demo program. The application can be 5551 character, but this is just a demo program. The application can be
5544 controlled by the following keys: 5552 controlled by the following keys:
5545 5553
5546 ? - print current values og the CPM Timer registers 5554 ? - print current values og the CPM Timer registers
5547 b - enable interrupts and start timer 5555 b - enable interrupts and start timer
5548 e - stop timer and disable interrupts 5556 e - stop timer and disable interrupts
5549 q - quit application 5557 q - quit application
5550 5558
5551 => loads 5559 => loads
5552 ## Ready for S-Record download ... 5560 ## Ready for S-Record download ...
5553 ~>examples/timer.srec 5561 ~>examples/timer.srec
5554 1 2 3 4 5 6 7 8 9 10 11 ... 5562 1 2 3 4 5 6 7 8 9 10 11 ...
5555 [file transfer complete] 5563 [file transfer complete]
5556 [connected] 5564 [connected]
5557 ## Start Addr = 0x00040004 5565 ## Start Addr = 0x00040004
5558 5566
5559 => go 40004 5567 => go 40004
5560 ## Starting application at 0x00040004 ... 5568 ## Starting application at 0x00040004 ...
5561 TIMERS=0xfff00980 5569 TIMERS=0xfff00980
5562 Using timer 1 5570 Using timer 1
5563 tgcr @ 0xfff00980, tmr @ 0xfff00990, trr @ 0xfff00994, tcr @ 0xfff00998, tcn @ 0xfff0099c, ter @ 0xfff009b0 5571 tgcr @ 0xfff00980, tmr @ 0xfff00990, trr @ 0xfff00994, tcr @ 0xfff00998, tcn @ 0xfff0099c, ter @ 0xfff009b0
5564 5572
5565 Hit 'b': 5573 Hit 'b':
5566 [q, b, e, ?] Set interval 1000000 us 5574 [q, b, e, ?] Set interval 1000000 us
5567 Enabling timer 5575 Enabling timer
5568 Hit '?': 5576 Hit '?':
5569 [q, b, e, ?] ........ 5577 [q, b, e, ?] ........
5570 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0xef6, ter=0x0 5578 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0xef6, ter=0x0
5571 Hit '?': 5579 Hit '?':
5572 [q, b, e, ?] . 5580 [q, b, e, ?] .
5573 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x2ad4, ter=0x0 5581 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x2ad4, ter=0x0
5574 Hit '?': 5582 Hit '?':
5575 [q, b, e, ?] . 5583 [q, b, e, ?] .
5576 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x1efc, ter=0x0 5584 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x1efc, ter=0x0
5577 Hit '?': 5585 Hit '?':
5578 [q, b, e, ?] . 5586 [q, b, e, ?] .
5579 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x169d, ter=0x0 5587 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x169d, ter=0x0
5580 Hit 'e': 5588 Hit 'e':
5581 [q, b, e, ?] ...Stopping timer 5589 [q, b, e, ?] ...Stopping timer
5582 Hit 'q': 5590 Hit 'q':
5583 [q, b, e, ?] ## Application terminated, rc = 0x0 5591 [q, b, e, ?] ## Application terminated, rc = 0x0
5584 5592
5585 5593
5586 Minicom warning: 5594 Minicom warning:
5587 ================ 5595 ================
5588 5596
5589 Over time, many people have reported problems when trying to use the 5597 Over time, many people have reported problems when trying to use the
5590 "minicom" terminal emulation program for serial download. I (wd) 5598 "minicom" terminal emulation program for serial download. I (wd)
5591 consider minicom to be broken, and recommend not to use it. Under 5599 consider minicom to be broken, and recommend not to use it. Under
5592 Unix, I recommend to use C-Kermit for general purpose use (and 5600 Unix, I recommend to use C-Kermit for general purpose use (and
5593 especially for kermit binary protocol download ("loadb" command), and 5601 especially for kermit binary protocol download ("loadb" command), and
5594 use "cu" for S-Record download ("loads" command). See 5602 use "cu" for S-Record download ("loads" command). See
5595 http://www.denx.de/wiki/view/DULG/SystemSetup#Section_4.3. 5603 http://www.denx.de/wiki/view/DULG/SystemSetup#Section_4.3.
5596 for help with kermit. 5604 for help with kermit.
5597 5605
5598 5606
5599 Nevertheless, if you absolutely want to use it try adding this 5607 Nevertheless, if you absolutely want to use it try adding this
5600 configuration to your "File transfer protocols" section: 5608 configuration to your "File transfer protocols" section:
5601 5609
5602 Name Program Name U/D FullScr IO-Red. Multi 5610 Name Program Name U/D FullScr IO-Red. Multi
5603 X kermit /usr/bin/kermit -i -l %l -s Y U Y N N 5611 X kermit /usr/bin/kermit -i -l %l -s Y U Y N N
5604 Y kermit /usr/bin/kermit -i -l %l -r N D Y N N 5612 Y kermit /usr/bin/kermit -i -l %l -r N D Y N N
5605 5613
5606 5614
5607 NetBSD Notes: 5615 NetBSD Notes:
5608 ============= 5616 =============
5609 5617
5610 Starting at version 0.9.2, U-Boot supports NetBSD both as host 5618 Starting at version 0.9.2, U-Boot supports NetBSD both as host
5611 (build U-Boot) and target system (boots NetBSD/mpc8xx). 5619 (build U-Boot) and target system (boots NetBSD/mpc8xx).
5612 5620
5613 Building requires a cross environment; it is known to work on 5621 Building requires a cross environment; it is known to work on
5614 NetBSD/i386 with the cross-powerpc-netbsd-1.3 package (you will also 5622 NetBSD/i386 with the cross-powerpc-netbsd-1.3 package (you will also
5615 need gmake since the Makefiles are not compatible with BSD make). 5623 need gmake since the Makefiles are not compatible with BSD make).
5616 Note that the cross-powerpc package does not install include files; 5624 Note that the cross-powerpc package does not install include files;
5617 attempting to build U-Boot will fail because <machine/ansi.h> is 5625 attempting to build U-Boot will fail because <machine/ansi.h> is
5618 missing. This file has to be installed and patched manually: 5626 missing. This file has to be installed and patched manually:
5619 5627
5620 # cd /usr/pkg/cross/powerpc-netbsd/include 5628 # cd /usr/pkg/cross/powerpc-netbsd/include
5621 # mkdir powerpc 5629 # mkdir powerpc
5622 # ln -s powerpc machine 5630 # ln -s powerpc machine
5623 # cp /usr/src/sys/arch/powerpc/include/ansi.h powerpc/ansi.h 5631 # cp /usr/src/sys/arch/powerpc/include/ansi.h powerpc/ansi.h
5624 # ${EDIT} powerpc/ansi.h ## must remove __va_list, _BSD_VA_LIST 5632 # ${EDIT} powerpc/ansi.h ## must remove __va_list, _BSD_VA_LIST
5625 5633
5626 Native builds *don't* work due to incompatibilities between native 5634 Native builds *don't* work due to incompatibilities between native
5627 and U-Boot include files. 5635 and U-Boot include files.
5628 5636
5629 Booting assumes that (the first part of) the image booted is a 5637 Booting assumes that (the first part of) the image booted is a
5630 stage-2 loader which in turn loads and then invokes the kernel 5638 stage-2 loader which in turn loads and then invokes the kernel
5631 proper. Loader sources will eventually appear in the NetBSD source 5639 proper. Loader sources will eventually appear in the NetBSD source
5632 tree (probably in sys/arc/mpc8xx/stand/u-boot_stage2/); in the 5640 tree (probably in sys/arc/mpc8xx/stand/u-boot_stage2/); in the
5633 meantime, see ftp://ftp.denx.de/pub/u-boot/ppcboot_stage2.tar.gz 5641 meantime, see ftp://ftp.denx.de/pub/u-boot/ppcboot_stage2.tar.gz
5634 5642
5635 5643
5636 Implementation Internals: 5644 Implementation Internals:
5637 ========================= 5645 =========================
5638 5646
5639 The following is not intended to be a complete description of every 5647 The following is not intended to be a complete description of every
5640 implementation detail. However, it should help to understand the 5648 implementation detail. However, it should help to understand the
5641 inner workings of U-Boot and make it easier to port it to custom 5649 inner workings of U-Boot and make it easier to port it to custom
5642 hardware. 5650 hardware.
5643 5651
5644 5652
5645 Initial Stack, Global Data: 5653 Initial Stack, Global Data:
5646 --------------------------- 5654 ---------------------------
5647 5655
5648 The implementation of U-Boot is complicated by the fact that U-Boot 5656 The implementation of U-Boot is complicated by the fact that U-Boot
5649 starts running out of ROM (flash memory), usually without access to 5657 starts running out of ROM (flash memory), usually without access to
5650 system RAM (because the memory controller is not initialized yet). 5658 system RAM (because the memory controller is not initialized yet).
5651 This means that we don't have writable Data or BSS segments, and BSS 5659 This means that we don't have writable Data or BSS segments, and BSS
5652 is not initialized as zero. To be able to get a C environment working 5660 is not initialized as zero. To be able to get a C environment working
5653 at all, we have to allocate at least a minimal stack. Implementation 5661 at all, we have to allocate at least a minimal stack. Implementation
5654 options for this are defined and restricted by the CPU used: Some CPU 5662 options for this are defined and restricted by the CPU used: Some CPU
5655 models provide on-chip memory (like the IMMR area on MPC8xx and 5663 models provide on-chip memory (like the IMMR area on MPC8xx and
5656 MPC826x processors), on others (parts of) the data cache can be 5664 MPC826x processors), on others (parts of) the data cache can be
5657 locked as (mis-) used as memory, etc. 5665 locked as (mis-) used as memory, etc.
5658 5666
5659 Chris Hallinan posted a good summary of these issues to the 5667 Chris Hallinan posted a good summary of these issues to the
5660 U-Boot mailing list: 5668 U-Boot mailing list:
5661 5669
5662 Subject: RE: [U-Boot-Users] RE: More On Memory Bank x (nothingness)? 5670 Subject: RE: [U-Boot-Users] RE: More On Memory Bank x (nothingness)?
5663 From: "Chris Hallinan" <clh@net1plus.com> 5671 From: "Chris Hallinan" <clh@net1plus.com>
5664 Date: Mon, 10 Feb 2003 16:43:46 -0500 (22:43 MET) 5672 Date: Mon, 10 Feb 2003 16:43:46 -0500 (22:43 MET)
5665 ... 5673 ...
5666 5674
5667 Correct me if I'm wrong, folks, but the way I understand it 5675 Correct me if I'm wrong, folks, but the way I understand it
5668 is this: Using DCACHE as initial RAM for Stack, etc, does not 5676 is this: Using DCACHE as initial RAM for Stack, etc, does not
5669 require any physical RAM backing up the cache. The cleverness 5677 require any physical RAM backing up the cache. The cleverness
5670 is that the cache is being used as a temporary supply of 5678 is that the cache is being used as a temporary supply of
5671 necessary storage before the SDRAM controller is setup. It's 5679 necessary storage before the SDRAM controller is setup. It's
5672 beyond the scope of this list to explain the details, but you 5680 beyond the scope of this list to explain the details, but you
5673 can see how this works by studying the cache architecture and 5681 can see how this works by studying the cache architecture and
5674 operation in the architecture and processor-specific manuals. 5682 operation in the architecture and processor-specific manuals.
5675 5683
5676 OCM is On Chip Memory, which I believe the 405GP has 4K. It 5684 OCM is On Chip Memory, which I believe the 405GP has 4K. It
5677 is another option for the system designer to use as an 5685 is another option for the system designer to use as an
5678 initial stack/RAM area prior to SDRAM being available. Either 5686 initial stack/RAM area prior to SDRAM being available. Either
5679 option should work for you. Using CS 4 should be fine if your 5687 option should work for you. Using CS 4 should be fine if your
5680 board designers haven't used it for something that would 5688 board designers haven't used it for something that would
5681 cause you grief during the initial boot! It is frequently not 5689 cause you grief during the initial boot! It is frequently not
5682 used. 5690 used.
5683 5691
5684 CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere 5692 CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
5685 with your processor/board/system design. The default value 5693 with your processor/board/system design. The default value
5686 you will find in any recent u-boot distribution in 5694 you will find in any recent u-boot distribution in
5687 walnut.h should work for you. I'd set it to a value larger 5695 walnut.h should work for you. I'd set it to a value larger
5688 than your SDRAM module. If you have a 64MB SDRAM module, set 5696 than your SDRAM module. If you have a 64MB SDRAM module, set
5689 it above 400_0000. Just make sure your board has no resources 5697 it above 400_0000. Just make sure your board has no resources
5690 that are supposed to respond to that address! That code in 5698 that are supposed to respond to that address! That code in
5691 start.S has been around a while and should work as is when 5699 start.S has been around a while and should work as is when
5692 you get the config right. 5700 you get the config right.
5693 5701
5694 -Chris Hallinan 5702 -Chris Hallinan
5695 DS4.COM, Inc. 5703 DS4.COM, Inc.
5696 5704
5697 It is essential to remember this, since it has some impact on the C 5705 It is essential to remember this, since it has some impact on the C
5698 code for the initialization procedures: 5706 code for the initialization procedures:
5699 5707
5700 * Initialized global data (data segment) is read-only. Do not attempt 5708 * Initialized global data (data segment) is read-only. Do not attempt
5701 to write it. 5709 to write it.
5702 5710
5703 * Do not use any uninitialized global data (or implicitely initialized 5711 * Do not use any uninitialized global data (or implicitely initialized
5704 as zero data - BSS segment) at all - this is undefined, initiali- 5712 as zero data - BSS segment) at all - this is undefined, initiali-
5705 zation is performed later (when relocating to RAM). 5713 zation is performed later (when relocating to RAM).
5706 5714
5707 * Stack space is very limited. Avoid big data buffers or things like 5715 * Stack space is very limited. Avoid big data buffers or things like
5708 that. 5716 that.
5709 5717
5710 Having only the stack as writable memory limits means we cannot use 5718 Having only the stack as writable memory limits means we cannot use
5711 normal global data to share information beween the code. But it 5719 normal global data to share information beween the code. But it
5712 turned out that the implementation of U-Boot can be greatly 5720 turned out that the implementation of U-Boot can be greatly
5713 simplified by making a global data structure (gd_t) available to all 5721 simplified by making a global data structure (gd_t) available to all
5714 functions. We could pass a pointer to this data as argument to _all_ 5722 functions. We could pass a pointer to this data as argument to _all_
5715 functions, but this would bloat the code. Instead we use a feature of 5723 functions, but this would bloat the code. Instead we use a feature of
5716 the GCC compiler (Global Register Variables) to share the data: we 5724 the GCC compiler (Global Register Variables) to share the data: we
5717 place a pointer (gd) to the global data into a register which we 5725 place a pointer (gd) to the global data into a register which we
5718 reserve for this purpose. 5726 reserve for this purpose.
5719 5727
5720 When choosing a register for such a purpose we are restricted by the 5728 When choosing a register for such a purpose we are restricted by the
5721 relevant (E)ABI specifications for the current architecture, and by 5729 relevant (E)ABI specifications for the current architecture, and by
5722 GCC's implementation. 5730 GCC's implementation.
5723 5731
5724 For PowerPC, the following registers have specific use: 5732 For PowerPC, the following registers have specific use:
5725 R1: stack pointer 5733 R1: stack pointer
5726 R2: reserved for system use 5734 R2: reserved for system use
5727 R3-R4: parameter passing and return values 5735 R3-R4: parameter passing and return values
5728 R5-R10: parameter passing 5736 R5-R10: parameter passing
5729 R13: small data area pointer 5737 R13: small data area pointer
5730 R30: GOT pointer 5738 R30: GOT pointer
5731 R31: frame pointer 5739 R31: frame pointer
5732 5740
5733 (U-Boot also uses R12 as internal GOT pointer. r12 5741 (U-Boot also uses R12 as internal GOT pointer. r12
5734 is a volatile register so r12 needs to be reset when 5742 is a volatile register so r12 needs to be reset when
5735 going back and forth between asm and C) 5743 going back and forth between asm and C)
5736 5744
5737 ==> U-Boot will use R2 to hold a pointer to the global data 5745 ==> U-Boot will use R2 to hold a pointer to the global data
5738 5746
5739 Note: on PPC, we could use a static initializer (since the 5747 Note: on PPC, we could use a static initializer (since the
5740 address of the global data structure is known at compile time), 5748 address of the global data structure is known at compile time),
5741 but it turned out that reserving a register results in somewhat 5749 but it turned out that reserving a register results in somewhat
5742 smaller code - although the code savings are not that big (on 5750 smaller code - although the code savings are not that big (on
5743 average for all boards 752 bytes for the whole U-Boot image, 5751 average for all boards 752 bytes for the whole U-Boot image,
5744 624 text + 127 data). 5752 624 text + 127 data).
5745 5753
5746 On Blackfin, the normal C ABI (except for P3) is followed as documented here: 5754 On Blackfin, the normal C ABI (except for P3) is followed as documented here:
5747 http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface 5755 http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
5748 5756
5749 ==> U-Boot will use P3 to hold a pointer to the global data 5757 ==> U-Boot will use P3 to hold a pointer to the global data
5750 5758
5751 On ARM, the following registers are used: 5759 On ARM, the following registers are used:
5752 5760
5753 R0: function argument word/integer result 5761 R0: function argument word/integer result
5754 R1-R3: function argument word 5762 R1-R3: function argument word
5755 R9: platform specific 5763 R9: platform specific
5756 R10: stack limit (used only if stack checking is enabled) 5764 R10: stack limit (used only if stack checking is enabled)
5757 R11: argument (frame) pointer 5765 R11: argument (frame) pointer
5758 R12: temporary workspace 5766 R12: temporary workspace
5759 R13: stack pointer 5767 R13: stack pointer
5760 R14: link register 5768 R14: link register
5761 R15: program counter 5769 R15: program counter
5762 5770
5763 ==> U-Boot will use R9 to hold a pointer to the global data 5771 ==> U-Boot will use R9 to hold a pointer to the global data
5764 5772
5765 Note: on ARM, only R_ARM_RELATIVE relocations are supported. 5773 Note: on ARM, only R_ARM_RELATIVE relocations are supported.
5766 5774
5767 On Nios II, the ABI is documented here: 5775 On Nios II, the ABI is documented here:
5768 http://www.altera.com/literature/hb/nios2/n2cpu_nii51016.pdf 5776 http://www.altera.com/literature/hb/nios2/n2cpu_nii51016.pdf
5769 5777
5770 ==> U-Boot will use gp to hold a pointer to the global data 5778 ==> U-Boot will use gp to hold a pointer to the global data
5771 5779
5772 Note: on Nios II, we give "-G0" option to gcc and don't use gp 5780 Note: on Nios II, we give "-G0" option to gcc and don't use gp
5773 to access small data sections, so gp is free. 5781 to access small data sections, so gp is free.
5774 5782
5775 On NDS32, the following registers are used: 5783 On NDS32, the following registers are used:
5776 5784
5777 R0-R1: argument/return 5785 R0-R1: argument/return
5778 R2-R5: argument 5786 R2-R5: argument
5779 R15: temporary register for assembler 5787 R15: temporary register for assembler
5780 R16: trampoline register 5788 R16: trampoline register
5781 R28: frame pointer (FP) 5789 R28: frame pointer (FP)
5782 R29: global pointer (GP) 5790 R29: global pointer (GP)
5783 R30: link register (LP) 5791 R30: link register (LP)
5784 R31: stack pointer (SP) 5792 R31: stack pointer (SP)
5785 PC: program counter (PC) 5793 PC: program counter (PC)
5786 5794
5787 ==> U-Boot will use R10 to hold a pointer to the global data 5795 ==> U-Boot will use R10 to hold a pointer to the global data
5788 5796
5789 NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope, 5797 NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
5790 or current versions of GCC may "optimize" the code too much. 5798 or current versions of GCC may "optimize" the code too much.
5791 5799
5792 Memory Management: 5800 Memory Management:
5793 ------------------ 5801 ------------------
5794 5802
5795 U-Boot runs in system state and uses physical addresses, i.e. the 5803 U-Boot runs in system state and uses physical addresses, i.e. the
5796 MMU is not used either for address mapping nor for memory protection. 5804 MMU is not used either for address mapping nor for memory protection.
5797 5805
5798 The available memory is mapped to fixed addresses using the memory 5806 The available memory is mapped to fixed addresses using the memory
5799 controller. In this process, a contiguous block is formed for each 5807 controller. In this process, a contiguous block is formed for each
5800 memory type (Flash, SDRAM, SRAM), even when it consists of several 5808 memory type (Flash, SDRAM, SRAM), even when it consists of several
5801 physical memory banks. 5809 physical memory banks.
5802 5810
5803 U-Boot is installed in the first 128 kB of the first Flash bank (on 5811 U-Boot is installed in the first 128 kB of the first Flash bank (on
5804 TQM8xxL modules this is the range 0x40000000 ... 0x4001FFFF). After 5812 TQM8xxL modules this is the range 0x40000000 ... 0x4001FFFF). After
5805 booting and sizing and initializing DRAM, the code relocates itself 5813 booting and sizing and initializing DRAM, the code relocates itself
5806 to the upper end of DRAM. Immediately below the U-Boot code some 5814 to the upper end of DRAM. Immediately below the U-Boot code some
5807 memory is reserved for use by malloc() [see CONFIG_SYS_MALLOC_LEN 5815 memory is reserved for use by malloc() [see CONFIG_SYS_MALLOC_LEN
5808 configuration setting]. Below that, a structure with global Board 5816 configuration setting]. Below that, a structure with global Board
5809 Info data is placed, followed by the stack (growing downward). 5817 Info data is placed, followed by the stack (growing downward).
5810 5818
5811 Additionally, some exception handler code is copied to the low 8 kB 5819 Additionally, some exception handler code is copied to the low 8 kB
5812 of DRAM (0x00000000 ... 0x00001FFF). 5820 of DRAM (0x00000000 ... 0x00001FFF).
5813 5821
5814 So a typical memory configuration with 16 MB of DRAM could look like 5822 So a typical memory configuration with 16 MB of DRAM could look like
5815 this: 5823 this:
5816 5824
5817 0x0000 0000 Exception Vector code 5825 0x0000 0000 Exception Vector code
5818 : 5826 :
5819 0x0000 1FFF 5827 0x0000 1FFF
5820 0x0000 2000 Free for Application Use 5828 0x0000 2000 Free for Application Use
5821 : 5829 :
5822 : 5830 :
5823 5831
5824 : 5832 :
5825 : 5833 :
5826 0x00FB FF20 Monitor Stack (Growing downward) 5834 0x00FB FF20 Monitor Stack (Growing downward)
5827 0x00FB FFAC Board Info Data and permanent copy of global data 5835 0x00FB FFAC Board Info Data and permanent copy of global data
5828 0x00FC 0000 Malloc Arena 5836 0x00FC 0000 Malloc Arena
5829 : 5837 :
5830 0x00FD FFFF 5838 0x00FD FFFF
5831 0x00FE 0000 RAM Copy of Monitor Code 5839 0x00FE 0000 RAM Copy of Monitor Code
5832 ... eventually: LCD or video framebuffer 5840 ... eventually: LCD or video framebuffer
5833 ... eventually: pRAM (Protected RAM - unchanged by reset) 5841 ... eventually: pRAM (Protected RAM - unchanged by reset)
5834 0x00FF FFFF [End of RAM] 5842 0x00FF FFFF [End of RAM]
5835 5843
5836 5844
5837 System Initialization: 5845 System Initialization:
5838 ---------------------- 5846 ----------------------
5839 5847
5840 In the reset configuration, U-Boot starts at the reset entry point 5848 In the reset configuration, U-Boot starts at the reset entry point
5841 (on most PowerPC systems at address 0x00000100). Because of the reset 5849 (on most PowerPC systems at address 0x00000100). Because of the reset
5842 configuration for CS0# this is a mirror of the onboard Flash memory. 5850 configuration for CS0# this is a mirror of the onboard Flash memory.
5843 To be able to re-map memory U-Boot then jumps to its link address. 5851 To be able to re-map memory U-Boot then jumps to its link address.
5844 To be able to implement the initialization code in C, a (small!) 5852 To be able to implement the initialization code in C, a (small!)
5845 initial stack is set up in the internal Dual Ported RAM (in case CPUs 5853 initial stack is set up in the internal Dual Ported RAM (in case CPUs
5846 which provide such a feature like MPC8xx or MPC8260), or in a locked 5854 which provide such a feature like MPC8xx or MPC8260), or in a locked
5847 part of the data cache. After that, U-Boot initializes the CPU core, 5855 part of the data cache. After that, U-Boot initializes the CPU core,
5848 the caches and the SIU. 5856 the caches and the SIU.
5849 5857
5850 Next, all (potentially) available memory banks are mapped using a 5858 Next, all (potentially) available memory banks are mapped using a
5851 preliminary mapping. For example, we put them on 512 MB boundaries 5859 preliminary mapping. For example, we put them on 512 MB boundaries
5852 (multiples of 0x20000000: SDRAM on 0x00000000 and 0x20000000, Flash 5860 (multiples of 0x20000000: SDRAM on 0x00000000 and 0x20000000, Flash
5853 on 0x40000000 and 0x60000000, SRAM on 0x80000000). Then UPM A is 5861 on 0x40000000 and 0x60000000, SRAM on 0x80000000). Then UPM A is
5854 programmed for SDRAM access. Using the temporary configuration, a 5862 programmed for SDRAM access. Using the temporary configuration, a
5855 simple memory test is run that determines the size of the SDRAM 5863 simple memory test is run that determines the size of the SDRAM
5856 banks. 5864 banks.
5857 5865
5858 When there is more than one SDRAM bank, and the banks are of 5866 When there is more than one SDRAM bank, and the banks are of
5859 different size, the largest is mapped first. For equal size, the first 5867 different size, the largest is mapped first. For equal size, the first
5860 bank (CS2#) is mapped first. The first mapping is always for address 5868 bank (CS2#) is mapped first. The first mapping is always for address
5861 0x00000000, with any additional banks following immediately to create 5869 0x00000000, with any additional banks following immediately to create
5862 contiguous memory starting from 0. 5870 contiguous memory starting from 0.
5863 5871
5864 Then, the monitor installs itself at the upper end of the SDRAM area 5872 Then, the monitor installs itself at the upper end of the SDRAM area
5865 and allocates memory for use by malloc() and for the global Board 5873 and allocates memory for use by malloc() and for the global Board
5866 Info data; also, the exception vector code is copied to the low RAM 5874 Info data; also, the exception vector code is copied to the low RAM
5867 pages, and the final stack is set up. 5875 pages, and the final stack is set up.
5868 5876
5869 Only after this relocation will you have a "normal" C environment; 5877 Only after this relocation will you have a "normal" C environment;
5870 until that you are restricted in several ways, mostly because you are 5878 until that you are restricted in several ways, mostly because you are
5871 running from ROM, and because the code will have to be relocated to a 5879 running from ROM, and because the code will have to be relocated to a
5872 new address in RAM. 5880 new address in RAM.
5873 5881
5874 5882
5875 U-Boot Porting Guide: 5883 U-Boot Porting Guide:
5876 ---------------------- 5884 ----------------------
5877 5885
5878 [Based on messages by Jerry Van Baren in the U-Boot-Users mailing 5886 [Based on messages by Jerry Van Baren in the U-Boot-Users mailing
5879 list, October 2002] 5887 list, October 2002]
5880 5888
5881 5889
5882 int main(int argc, char *argv[]) 5890 int main(int argc, char *argv[])
5883 { 5891 {
5884 sighandler_t no_more_time; 5892 sighandler_t no_more_time;
5885 5893
5886 signal(SIGALRM, no_more_time); 5894 signal(SIGALRM, no_more_time);
5887 alarm(PROJECT_DEADLINE - toSec (3 * WEEK)); 5895 alarm(PROJECT_DEADLINE - toSec (3 * WEEK));
5888 5896
5889 if (available_money > available_manpower) { 5897 if (available_money > available_manpower) {
5890 Pay consultant to port U-Boot; 5898 Pay consultant to port U-Boot;
5891 return 0; 5899 return 0;
5892 } 5900 }
5893 5901
5894 Download latest U-Boot source; 5902 Download latest U-Boot source;
5895 5903
5896 Subscribe to u-boot mailing list; 5904 Subscribe to u-boot mailing list;
5897 5905
5898 if (clueless) 5906 if (clueless)
5899 email("Hi, I am new to U-Boot, how do I get started?"); 5907 email("Hi, I am new to U-Boot, how do I get started?");
5900 5908
5901 while (learning) { 5909 while (learning) {
5902 Read the README file in the top level directory; 5910 Read the README file in the top level directory;
5903 Read http://www.denx.de/twiki/bin/view/DULG/Manual; 5911 Read http://www.denx.de/twiki/bin/view/DULG/Manual;
5904 Read applicable doc/*.README; 5912 Read applicable doc/*.README;
5905 Read the source, Luke; 5913 Read the source, Luke;
5906 /* find . -name "*.[chS]" | xargs grep -i <keyword> */ 5914 /* find . -name "*.[chS]" | xargs grep -i <keyword> */
5907 } 5915 }
5908 5916
5909 if (available_money > toLocalCurrency ($2500)) 5917 if (available_money > toLocalCurrency ($2500))
5910 Buy a BDI3000; 5918 Buy a BDI3000;
5911 else 5919 else
5912 Add a lot of aggravation and time; 5920 Add a lot of aggravation and time;
5913 5921
5914 if (a similar board exists) { /* hopefully... */ 5922 if (a similar board exists) { /* hopefully... */
5915 cp -a board/<similar> board/<myboard> 5923 cp -a board/<similar> board/<myboard>
5916 cp include/configs/<similar>.h include/configs/<myboard>.h 5924 cp include/configs/<similar>.h include/configs/<myboard>.h
5917 } else { 5925 } else {
5918 Create your own board support subdirectory; 5926 Create your own board support subdirectory;
5919 Create your own board include/configs/<myboard>.h file; 5927 Create your own board include/configs/<myboard>.h file;
5920 } 5928 }
5921 Edit new board/<myboard> files 5929 Edit new board/<myboard> files
5922 Edit new include/configs/<myboard>.h 5930 Edit new include/configs/<myboard>.h
5923 5931
5924 while (!accepted) { 5932 while (!accepted) {
5925 while (!running) { 5933 while (!running) {
5926 do { 5934 do {
5927 Add / modify source code; 5935 Add / modify source code;
5928 } until (compiles); 5936 } until (compiles);
5929 Debug; 5937 Debug;
5930 if (clueless) 5938 if (clueless)
5931 email("Hi, I am having problems..."); 5939 email("Hi, I am having problems...");
5932 } 5940 }
5933 Send patch file to the U-Boot email list; 5941 Send patch file to the U-Boot email list;
5934 if (reasonable critiques) 5942 if (reasonable critiques)
5935 Incorporate improvements from email list code review; 5943 Incorporate improvements from email list code review;
5936 else 5944 else
5937 Defend code as written; 5945 Defend code as written;
5938 } 5946 }
5939 5947
5940 return 0; 5948 return 0;
5941 } 5949 }
5942 5950
5943 void no_more_time (int sig) 5951 void no_more_time (int sig)
5944 { 5952 {
5945 hire_a_guru(); 5953 hire_a_guru();
5946 } 5954 }
5947 5955
5948 5956
5949 Coding Standards: 5957 Coding Standards:
5950 ----------------- 5958 -----------------
5951 5959
5952 All contributions to U-Boot should conform to the Linux kernel 5960 All contributions to U-Boot should conform to the Linux kernel
5953 coding style; see the file "Documentation/CodingStyle" and the script 5961 coding style; see the file "Documentation/CodingStyle" and the script
5954 "scripts/Lindent" in your Linux kernel source directory. 5962 "scripts/Lindent" in your Linux kernel source directory.
5955 5963
5956 Source files originating from a different project (for example the 5964 Source files originating from a different project (for example the
5957 MTD subsystem) are generally exempt from these guidelines and are not 5965 MTD subsystem) are generally exempt from these guidelines and are not
5958 reformated to ease subsequent migration to newer versions of those 5966 reformated to ease subsequent migration to newer versions of those
5959 sources. 5967 sources.
5960 5968
5961 Please note that U-Boot is implemented in C (and to some small parts in 5969 Please note that U-Boot is implemented in C (and to some small parts in
5962 Assembler); no C++ is used, so please do not use C++ style comments (//) 5970 Assembler); no C++ is used, so please do not use C++ style comments (//)
5963 in your code. 5971 in your code.
5964 5972
5965 Please also stick to the following formatting rules: 5973 Please also stick to the following formatting rules:
5966 - remove any trailing white space 5974 - remove any trailing white space
5967 - use TAB characters for indentation and vertical alignment, not spaces 5975 - use TAB characters for indentation and vertical alignment, not spaces
5968 - make sure NOT to use DOS '\r\n' line feeds 5976 - make sure NOT to use DOS '\r\n' line feeds
5969 - do not add more than 2 consecutive empty lines to source files 5977 - do not add more than 2 consecutive empty lines to source files
5970 - do not add trailing empty lines to source files 5978 - do not add trailing empty lines to source files
5971 5979
5972 Submissions which do not conform to the standards may be returned 5980 Submissions which do not conform to the standards may be returned
5973 with a request to reformat the changes. 5981 with a request to reformat the changes.
5974 5982
5975 5983
5976 Submitting Patches: 5984 Submitting Patches:
5977 ------------------- 5985 -------------------
5978 5986
5979 Since the number of patches for U-Boot is growing, we need to 5987 Since the number of patches for U-Boot is growing, we need to
5980 establish some rules. Submissions which do not conform to these rules 5988 establish some rules. Submissions which do not conform to these rules
5981 may be rejected, even when they contain important and valuable stuff. 5989 may be rejected, even when they contain important and valuable stuff.
5982 5990
5983 Please see http://www.denx.de/wiki/U-Boot/Patches for details. 5991 Please see http://www.denx.de/wiki/U-Boot/Patches for details.
5984 5992
5985 Patches shall be sent to the u-boot mailing list <u-boot@lists.denx.de>; 5993 Patches shall be sent to the u-boot mailing list <u-boot@lists.denx.de>;
5986 see http://lists.denx.de/mailman/listinfo/u-boot 5994 see http://lists.denx.de/mailman/listinfo/u-boot
5987 5995
5988 When you send a patch, please include the following information with 5996 When you send a patch, please include the following information with
5989 it: 5997 it:
5990 5998
5991 * For bug fixes: a description of the bug and how your patch fixes 5999 * For bug fixes: a description of the bug and how your patch fixes
5992 this bug. Please try to include a way of demonstrating that the 6000 this bug. Please try to include a way of demonstrating that the
5993 patch actually fixes something. 6001 patch actually fixes something.
5994 6002
5995 * For new features: a description of the feature and your 6003 * For new features: a description of the feature and your
5996 implementation. 6004 implementation.
5997 6005
5998 * A CHANGELOG entry as plaintext (separate from the patch) 6006 * A CHANGELOG entry as plaintext (separate from the patch)
5999 6007
6000 * For major contributions, your entry to the CREDITS file 6008 * For major contributions, your entry to the CREDITS file
6001 6009
6002 * When you add support for a new board, don't forget to add a 6010 * When you add support for a new board, don't forget to add a
6003 maintainer e-mail address to the boards.cfg file, too. 6011 maintainer e-mail address to the boards.cfg file, too.
6004 6012
6005 * If your patch adds new configuration options, don't forget to 6013 * If your patch adds new configuration options, don't forget to
6006 document these in the README file. 6014 document these in the README file.
6007 6015
6008 * The patch itself. If you are using git (which is *strongly* 6016 * The patch itself. If you are using git (which is *strongly*
6009 recommended) you can easily generate the patch using the 6017 recommended) you can easily generate the patch using the
6010 "git format-patch". If you then use "git send-email" to send it to 6018 "git format-patch". If you then use "git send-email" to send it to
6011 the U-Boot mailing list, you will avoid most of the common problems 6019 the U-Boot mailing list, you will avoid most of the common problems
6012 with some other mail clients. 6020 with some other mail clients.
6013 6021
6014 If you cannot use git, use "diff -purN OLD NEW". If your version of 6022 If you cannot use git, use "diff -purN OLD NEW". If your version of
6015 diff does not support these options, then get the latest version of 6023 diff does not support these options, then get the latest version of
6016 GNU diff. 6024 GNU diff.
6017 6025
6018 The current directory when running this command shall be the parent 6026 The current directory when running this command shall be the parent
6019 directory of the U-Boot source tree (i. e. please make sure that 6027 directory of the U-Boot source tree (i. e. please make sure that
6020 your patch includes sufficient directory information for the 6028 your patch includes sufficient directory information for the
6021 affected files). 6029 affected files).
6022 6030
6023 We prefer patches as plain text. MIME attachments are discouraged, 6031 We prefer patches as plain text. MIME attachments are discouraged,
6024 and compressed attachments must not be used. 6032 and compressed attachments must not be used.
6025 6033
6026 * If one logical set of modifications affects or creates several 6034 * If one logical set of modifications affects or creates several
6027 files, all these changes shall be submitted in a SINGLE patch file. 6035 files, all these changes shall be submitted in a SINGLE patch file.
6028 6036
6029 * Changesets that contain different, unrelated modifications shall be 6037 * Changesets that contain different, unrelated modifications shall be
6030 submitted as SEPARATE patches, one patch per changeset. 6038 submitted as SEPARATE patches, one patch per changeset.
6031 6039
6032 6040
6033 Notes: 6041 Notes:
6034 6042
6035 * Before sending the patch, run the MAKEALL script on your patched 6043 * Before sending the patch, run the MAKEALL script on your patched
6036 source tree and make sure that no errors or warnings are reported 6044 source tree and make sure that no errors or warnings are reported
6037 for any of the boards. 6045 for any of the boards.
6038 6046
6039 * Keep your modifications to the necessary minimum: A patch 6047 * Keep your modifications to the necessary minimum: A patch
6040 containing several unrelated changes or arbitrary reformats will be 6048 containing several unrelated changes or arbitrary reformats will be
6041 returned with a request to re-formatting / split it. 6049 returned with a request to re-formatting / split it.
6042 6050
6043 * If you modify existing code, make sure that your new code does not 6051 * If you modify existing code, make sure that your new code does not
6044 add to the memory footprint of the code ;-) Small is beautiful! 6052 add to the memory footprint of the code ;-) Small is beautiful!
6045 When adding new features, these should compile conditionally only 6053 When adding new features, these should compile conditionally only
6046 (using #ifdef), and the resulting code with the new feature 6054 (using #ifdef), and the resulting code with the new feature
6047 disabled must not need more memory than the old code without your 6055 disabled must not need more memory than the old code without your
6048 modification. 6056 modification.
6049 6057
6050 * Remember that there is a size limit of 100 kB per message on the 6058 * Remember that there is a size limit of 100 kB per message on the
6051 u-boot mailing list. Bigger patches will be moderated. If they are 6059 u-boot mailing list. Bigger patches will be moderated. If they are
6052 reasonable and not too big, they will be acknowledged. But patches 6060 reasonable and not too big, they will be acknowledged. But patches
6053 bigger than the size limit should be avoided. 6061 bigger than the size limit should be avoided.
6054 6062
arch/powerpc/cpu/mpc85xx/speed.c
1 /* 1 /*
2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. 2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
3 * 3 *
4 * (C) Copyright 2003 Motorola Inc. 4 * (C) Copyright 2003 Motorola Inc.
5 * Xianghua Xiao, (X.Xiao@motorola.com) 5 * Xianghua Xiao, (X.Xiao@motorola.com)
6 * 6 *
7 * (C) Copyright 2000 7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * 9 *
10 * SPDX-License-Identifier: GPL-2.0+ 10 * SPDX-License-Identifier: GPL-2.0+
11 */ 11 */
12 12
13 #include <common.h> 13 #include <common.h>
14 #include <ppc_asm.tmpl> 14 #include <ppc_asm.tmpl>
15 #include <linux/compiler.h> 15 #include <linux/compiler.h>
16 #include <asm/processor.h> 16 #include <asm/processor.h>
17 #include <asm/io.h> 17 #include <asm/io.h>
18 18
19 DECLARE_GLOBAL_DATA_PTR; 19 DECLARE_GLOBAL_DATA_PTR;
20 20
21 21
22 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS 22 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
23 #define CONFIG_SYS_FSL_NUM_CC_PLLS 6 23 #define CONFIG_SYS_FSL_NUM_CC_PLLS 6
24 #endif 24 #endif
25 /* --------------------------------------------------------------- */ 25 /* --------------------------------------------------------------- */
26 26
27 void get_sys_info(sys_info_t *sys_info) 27 void get_sys_info(sys_info_t *sys_info)
28 { 28 {
29 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 29 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
30 #ifdef CONFIG_FSL_IFC 30 #ifdef CONFIG_FSL_IFC
31 struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; 31 struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
32 u32 ccr; 32 u32 ccr;
33 #endif 33 #endif
34 #ifdef CONFIG_FSL_CORENET 34 #ifdef CONFIG_FSL_CORENET
35 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); 35 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
36 unsigned int cpu; 36 unsigned int cpu;
37 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 37 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
38 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; 38 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
39 #endif 39 #endif
40 40
41 const u8 core_cplx_PLL[16] = { 41 const u8 core_cplx_PLL[16] = {
42 [ 0] = 0, /* CC1 PPL / 1 */ 42 [ 0] = 0, /* CC1 PPL / 1 */
43 [ 1] = 0, /* CC1 PPL / 2 */ 43 [ 1] = 0, /* CC1 PPL / 2 */
44 [ 2] = 0, /* CC1 PPL / 4 */ 44 [ 2] = 0, /* CC1 PPL / 4 */
45 [ 4] = 1, /* CC2 PPL / 1 */ 45 [ 4] = 1, /* CC2 PPL / 1 */
46 [ 5] = 1, /* CC2 PPL / 2 */ 46 [ 5] = 1, /* CC2 PPL / 2 */
47 [ 6] = 1, /* CC2 PPL / 4 */ 47 [ 6] = 1, /* CC2 PPL / 4 */
48 [ 8] = 2, /* CC3 PPL / 1 */ 48 [ 8] = 2, /* CC3 PPL / 1 */
49 [ 9] = 2, /* CC3 PPL / 2 */ 49 [ 9] = 2, /* CC3 PPL / 2 */
50 [10] = 2, /* CC3 PPL / 4 */ 50 [10] = 2, /* CC3 PPL / 4 */
51 [12] = 3, /* CC4 PPL / 1 */ 51 [12] = 3, /* CC4 PPL / 1 */
52 [13] = 3, /* CC4 PPL / 2 */ 52 [13] = 3, /* CC4 PPL / 2 */
53 [14] = 3, /* CC4 PPL / 4 */ 53 [14] = 3, /* CC4 PPL / 4 */
54 }; 54 };
55 55
56 const u8 core_cplx_pll_div[16] = { 56 const u8 core_cplx_pll_div[16] = {
57 [ 0] = 1, /* CC1 PPL / 1 */ 57 [ 0] = 1, /* CC1 PPL / 1 */
58 [ 1] = 2, /* CC1 PPL / 2 */ 58 [ 1] = 2, /* CC1 PPL / 2 */
59 [ 2] = 4, /* CC1 PPL / 4 */ 59 [ 2] = 4, /* CC1 PPL / 4 */
60 [ 4] = 1, /* CC2 PPL / 1 */ 60 [ 4] = 1, /* CC2 PPL / 1 */
61 [ 5] = 2, /* CC2 PPL / 2 */ 61 [ 5] = 2, /* CC2 PPL / 2 */
62 [ 6] = 4, /* CC2 PPL / 4 */ 62 [ 6] = 4, /* CC2 PPL / 4 */
63 [ 8] = 1, /* CC3 PPL / 1 */ 63 [ 8] = 1, /* CC3 PPL / 1 */
64 [ 9] = 2, /* CC3 PPL / 2 */ 64 [ 9] = 2, /* CC3 PPL / 2 */
65 [10] = 4, /* CC3 PPL / 4 */ 65 [10] = 4, /* CC3 PPL / 4 */
66 [12] = 1, /* CC4 PPL / 1 */ 66 [12] = 1, /* CC4 PPL / 1 */
67 [13] = 2, /* CC4 PPL / 2 */ 67 [13] = 2, /* CC4 PPL / 2 */
68 [14] = 4, /* CC4 PPL / 4 */ 68 [14] = 4, /* CC4 PPL / 4 */
69 }; 69 };
70 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; 70 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
71 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) 71 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
72 uint rcw_tmp; 72 uint rcw_tmp;
73 #endif 73 #endif
74 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; 74 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
75 unsigned long sysclk = CONFIG_SYS_CLK_FREQ; 75 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
76 uint mem_pll_rat; 76 uint mem_pll_rat;
77 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
78 uint single_src;
79 #endif
77 80
78 sys_info->freq_systembus = sysclk; 81 sys_info->freq_systembus = sysclk;
82 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
83 /*
84 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
85 * are driven by separate DDR Refclock or single source
86 * differential clock.
87 */
88 single_src = (in_be32(&gur->rcwsr[5]) >>
89 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
90 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
91 /*
92 * For single source clocking, both ddrclock and syclock
93 * are driven by differential sysclock.
94 */
95 if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) {
96 printf("Single Source Clock Configuration\n");
97 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
98 } else
99 #endif
79 #ifdef CONFIG_DDR_CLK_FREQ 100 #ifdef CONFIG_DDR_CLK_FREQ
80 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; 101 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
81 #else 102 #else
82 sys_info->freq_ddrbus = sysclk; 103 sys_info->freq_ddrbus = sysclk;
83 #endif 104 #endif
84 105
85 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 106 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
86 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 107 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
87 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) 108 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
88 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 109 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
89 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of 110 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
90 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 111 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
91 * it uses 6. 112 * it uses 6.
92 */ 113 */
93 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 114 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
94 if (SVR_MAJ(get_svr()) >= 2) 115 if (SVR_MAJ(get_svr()) >= 2)
95 mem_pll_rat *= 2; 116 mem_pll_rat *= 2;
96 #endif 117 #endif
97 if (mem_pll_rat > 2) 118 if (mem_pll_rat > 2)
98 sys_info->freq_ddrbus *= mem_pll_rat; 119 sys_info->freq_ddrbus *= mem_pll_rat;
99 else 120 else
100 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat; 121 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
101 122
102 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { 123 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
103 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; 124 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
104 if (ratio[i] > 4) 125 if (ratio[i] > 4)
105 freq_c_pll[i] = sysclk * ratio[i]; 126 freq_c_pll[i] = sysclk * ratio[i];
106 else 127 else
107 freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; 128 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
108 } 129 }
109 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 130 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
110 /* 131 /*
111 * As per CHASSIS2 architeture total 12 clusters are posible and 132 * As per CHASSIS2 architeture total 12 clusters are posible and
112 * Each cluster has up to 4 cores, sharing the same PLL selection. 133 * Each cluster has up to 4 cores, sharing the same PLL selection.
113 * The cluster clock assignment is SoC defined. 134 * The cluster clock assignment is SoC defined.
114 * 135 *
115 * Total 4 clock groups are possible with 3 PLLs each. 136 * Total 4 clock groups are possible with 3 PLLs each.
116 * as per array indices, clock group A has 0, 1, 2 numbered PLLs & 137 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
117 * clock group B has 3, 4, 6 and so on. 138 * clock group B has 3, 4, 6 and so on.
118 * 139 *
119 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster 140 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
120 * depends upon the SoC architeture. Same applies to other 141 * depends upon the SoC architeture. Same applies to other
121 * clock groups and clusters. 142 * clock groups and clusters.
122 * 143 *
123 */ 144 */
124 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 145 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
125 int cluster = fsl_qoriq_core_to_cluster(cpu); 146 int cluster = fsl_qoriq_core_to_cluster(cpu);
126 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) 147 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
127 & 0xf; 148 & 0xf;
128 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 149 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
129 cplx_pll += cc_group[cluster] - 1; 150 cplx_pll += cc_group[cluster] - 1;
130 sys_info->freq_processor[cpu] = 151 sys_info->freq_processor[cpu] =
131 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 152 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
132 } 153 }
133 #if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) 154 #if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080)
134 #define FM1_CLK_SEL 0xe0000000 155 #define FM1_CLK_SEL 0xe0000000
135 #define FM1_CLK_SHIFT 29 156 #define FM1_CLK_SHIFT 29
136 #else 157 #else
137 #define PME_CLK_SEL 0xe0000000 158 #define PME_CLK_SEL 0xe0000000
138 #define PME_CLK_SHIFT 29 159 #define PME_CLK_SHIFT 29
139 #define FM1_CLK_SEL 0x1c000000 160 #define FM1_CLK_SEL 0x1c000000
140 #define FM1_CLK_SHIFT 26 161 #define FM1_CLK_SHIFT 26
141 #endif 162 #endif
142 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) 163 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
143 rcw_tmp = in_be32(&gur->rcwsr[7]); 164 rcw_tmp = in_be32(&gur->rcwsr[7]);
144 #endif 165 #endif
145 166
146 #ifdef CONFIG_SYS_DPAA_PME 167 #ifdef CONFIG_SYS_DPAA_PME
147 #ifndef CONFIG_PME_PLAT_CLK_DIV 168 #ifndef CONFIG_PME_PLAT_CLK_DIV
148 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { 169 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
149 case 1: 170 case 1:
150 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK]; 171 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
151 break; 172 break;
152 case 2: 173 case 2:
153 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2; 174 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
154 break; 175 break;
155 case 3: 176 case 3:
156 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3; 177 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
157 break; 178 break;
158 case 4: 179 case 4:
159 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4; 180 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
160 break; 181 break;
161 case 6: 182 case 6:
162 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2; 183 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
163 break; 184 break;
164 case 7: 185 case 7:
165 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3; 186 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
166 break; 187 break;
167 default: 188 default:
168 printf("Error: Unknown PME clock select!\n"); 189 printf("Error: Unknown PME clock select!\n");
169 case 0: 190 case 0:
170 sys_info->freq_pme = sys_info->freq_systembus / 2; 191 sys_info->freq_pme = sys_info->freq_systembus / 2;
171 break; 192 break;
172 193
173 } 194 }
174 #else 195 #else
175 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK; 196 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
176 197
177 #endif 198 #endif
178 #endif 199 #endif
179 200
180 #ifdef CONFIG_SYS_DPAA_QBMAN 201 #ifdef CONFIG_SYS_DPAA_QBMAN
181 sys_info->freq_qman = sys_info->freq_systembus / 2; 202 sys_info->freq_qman = sys_info->freq_systembus / 2;
182 #endif 203 #endif
183 204
184 #ifdef CONFIG_SYS_DPAA_FMAN 205 #ifdef CONFIG_SYS_DPAA_FMAN
185 #ifndef CONFIG_FM_PLAT_CLK_DIV 206 #ifndef CONFIG_FM_PLAT_CLK_DIV
186 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { 207 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
187 case 1: 208 case 1:
188 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK]; 209 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
189 break; 210 break;
190 case 2: 211 case 2:
191 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2; 212 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
192 break; 213 break;
193 case 3: 214 case 3:
194 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3; 215 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
195 break; 216 break;
196 case 4: 217 case 4:
197 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4; 218 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
198 break; 219 break;
199 case 5: 220 case 5:
200 sys_info->freq_fman[0] = sys_info->freq_systembus; 221 sys_info->freq_fman[0] = sys_info->freq_systembus;
201 break; 222 break;
202 case 6: 223 case 6:
203 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2; 224 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
204 break; 225 break;
205 case 7: 226 case 7:
206 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3; 227 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
207 break; 228 break;
208 default: 229 default:
209 printf("Error: Unknown FMan1 clock select!\n"); 230 printf("Error: Unknown FMan1 clock select!\n");
210 case 0: 231 case 0:
211 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 232 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
212 break; 233 break;
213 } 234 }
214 #if (CONFIG_SYS_NUM_FMAN) == 2 235 #if (CONFIG_SYS_NUM_FMAN) == 2
215 #ifdef CONFIG_SYS_FM2_CLK 236 #ifdef CONFIG_SYS_FM2_CLK
216 #define FM2_CLK_SEL 0x00000038 237 #define FM2_CLK_SEL 0x00000038
217 #define FM2_CLK_SHIFT 3 238 #define FM2_CLK_SHIFT 3
218 rcw_tmp = in_be32(&gur->rcwsr[15]); 239 rcw_tmp = in_be32(&gur->rcwsr[15]);
219 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { 240 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
220 case 1: 241 case 1:
221 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1]; 242 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
222 break; 243 break;
223 case 2: 244 case 2:
224 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2; 245 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
225 break; 246 break;
226 case 3: 247 case 3:
227 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3; 248 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
228 break; 249 break;
229 case 4: 250 case 4:
230 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4; 251 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
231 break; 252 break;
232 case 5: 253 case 5:
233 sys_info->freq_fman[1] = sys_info->freq_systembus; 254 sys_info->freq_fman[1] = sys_info->freq_systembus;
234 break; 255 break;
235 case 6: 256 case 6:
236 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2; 257 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
237 break; 258 break;
238 case 7: 259 case 7:
239 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3; 260 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
240 break; 261 break;
241 default: 262 default:
242 printf("Error: Unknown FMan2 clock select!\n"); 263 printf("Error: Unknown FMan2 clock select!\n");
243 case 0: 264 case 0:
244 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 265 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
245 break; 266 break;
246 } 267 }
247 #endif 268 #endif
248 #endif /* CONFIG_SYS_NUM_FMAN == 2 */ 269 #endif /* CONFIG_SYS_NUM_FMAN == 2 */
249 #else 270 #else
250 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; 271 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
251 #endif 272 #endif
252 #endif 273 #endif
253 274
254 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 275 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
255 276
256 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 277 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
257 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) 278 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
258 & 0xf; 279 & 0xf;
259 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 280 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
260 281
261 sys_info->freq_processor[cpu] = 282 sys_info->freq_processor[cpu] =
262 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 283 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
263 } 284 }
264 #define PME_CLK_SEL 0x80000000 285 #define PME_CLK_SEL 0x80000000
265 #define FM1_CLK_SEL 0x40000000 286 #define FM1_CLK_SEL 0x40000000
266 #define FM2_CLK_SEL 0x20000000 287 #define FM2_CLK_SEL 0x20000000
267 #define HWA_ASYNC_DIV 0x04000000 288 #define HWA_ASYNC_DIV 0x04000000
268 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) 289 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
269 #define HWA_CC_PLL 1 290 #define HWA_CC_PLL 1
270 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3) 291 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
271 #define HWA_CC_PLL 2 292 #define HWA_CC_PLL 2
272 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) 293 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
273 #define HWA_CC_PLL 2 294 #define HWA_CC_PLL 2
274 #else 295 #else
275 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case 296 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
276 #endif 297 #endif
277 rcw_tmp = in_be32(&gur->rcwsr[7]); 298 rcw_tmp = in_be32(&gur->rcwsr[7]);
278 299
279 #ifdef CONFIG_SYS_DPAA_PME 300 #ifdef CONFIG_SYS_DPAA_PME
280 if (rcw_tmp & PME_CLK_SEL) { 301 if (rcw_tmp & PME_CLK_SEL) {
281 if (rcw_tmp & HWA_ASYNC_DIV) 302 if (rcw_tmp & HWA_ASYNC_DIV)
282 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4; 303 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
283 else 304 else
284 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2; 305 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
285 } else { 306 } else {
286 sys_info->freq_pme = sys_info->freq_systembus / 2; 307 sys_info->freq_pme = sys_info->freq_systembus / 2;
287 } 308 }
288 #endif 309 #endif
289 310
290 #ifdef CONFIG_SYS_DPAA_FMAN 311 #ifdef CONFIG_SYS_DPAA_FMAN
291 if (rcw_tmp & FM1_CLK_SEL) { 312 if (rcw_tmp & FM1_CLK_SEL) {
292 if (rcw_tmp & HWA_ASYNC_DIV) 313 if (rcw_tmp & HWA_ASYNC_DIV)
293 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4; 314 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
294 else 315 else
295 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2; 316 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
296 } else { 317 } else {
297 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 318 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
298 } 319 }
299 #if (CONFIG_SYS_NUM_FMAN) == 2 320 #if (CONFIG_SYS_NUM_FMAN) == 2
300 if (rcw_tmp & FM2_CLK_SEL) { 321 if (rcw_tmp & FM2_CLK_SEL) {
301 if (rcw_tmp & HWA_ASYNC_DIV) 322 if (rcw_tmp & HWA_ASYNC_DIV)
302 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4; 323 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
303 else 324 else
304 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2; 325 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
305 } else { 326 } else {
306 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 327 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
307 } 328 }
308 #endif 329 #endif
309 #endif 330 #endif
310 331
311 #ifdef CONFIG_SYS_DPAA_QBMAN 332 #ifdef CONFIG_SYS_DPAA_QBMAN
312 sys_info->freq_qman = sys_info->freq_systembus / 2; 333 sys_info->freq_qman = sys_info->freq_systembus / 2;
313 #endif 334 #endif
314 335
315 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 336 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
316 337
317 #else /* CONFIG_FSL_CORENET */ 338 #else /* CONFIG_FSL_CORENET */
318 uint plat_ratio, e500_ratio, half_freq_systembus; 339 uint plat_ratio, e500_ratio, half_freq_systembus;
319 int i; 340 int i;
320 #ifdef CONFIG_QE 341 #ifdef CONFIG_QE
321 __maybe_unused u32 qe_ratio; 342 __maybe_unused u32 qe_ratio;
322 #endif 343 #endif
323 344
324 plat_ratio = (gur->porpllsr) & 0x0000003e; 345 plat_ratio = (gur->porpllsr) & 0x0000003e;
325 plat_ratio >>= 1; 346 plat_ratio >>= 1;
326 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ; 347 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
327 348
328 /* Divide before multiply to avoid integer 349 /* Divide before multiply to avoid integer
329 * overflow for processor speeds above 2GHz */ 350 * overflow for processor speeds above 2GHz */
330 half_freq_systembus = sys_info->freq_systembus/2; 351 half_freq_systembus = sys_info->freq_systembus/2;
331 for (i = 0; i < cpu_numcores(); i++) { 352 for (i = 0; i < cpu_numcores(); i++) {
332 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; 353 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
333 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus; 354 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
334 } 355 }
335 356
336 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */ 357 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
337 sys_info->freq_ddrbus = sys_info->freq_systembus; 358 sys_info->freq_ddrbus = sys_info->freq_systembus;
338 359
339 #ifdef CONFIG_DDR_CLK_FREQ 360 #ifdef CONFIG_DDR_CLK_FREQ
340 { 361 {
341 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 362 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
342 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 363 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
343 if (ddr_ratio != 0x7) 364 if (ddr_ratio != 0x7)
344 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ; 365 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
345 } 366 }
346 #endif 367 #endif
347 368
348 #ifdef CONFIG_QE 369 #ifdef CONFIG_QE
349 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) 370 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
350 sys_info->freq_qe = sys_info->freq_systembus; 371 sys_info->freq_qe = sys_info->freq_systembus;
351 #else 372 #else
352 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) 373 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
353 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; 374 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
354 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ; 375 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
355 #endif 376 #endif
356 #endif 377 #endif
357 378
358 #ifdef CONFIG_SYS_DPAA_FMAN 379 #ifdef CONFIG_SYS_DPAA_FMAN
359 sys_info->freq_fman[0] = sys_info->freq_systembus; 380 sys_info->freq_fman[0] = sys_info->freq_systembus;
360 #endif 381 #endif
361 382
362 #endif /* CONFIG_FSL_CORENET */ 383 #endif /* CONFIG_FSL_CORENET */
363 384
364 #if defined(CONFIG_FSL_LBC) 385 #if defined(CONFIG_FSL_LBC)
365 uint lcrr_div; 386 uint lcrr_div;
366 #if defined(CONFIG_SYS_LBC_LCRR) 387 #if defined(CONFIG_SYS_LBC_LCRR)
367 /* We will program LCRR to this value later */ 388 /* We will program LCRR to this value later */
368 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; 389 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
369 #else 390 #else
370 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; 391 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
371 #endif 392 #endif
372 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { 393 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
373 #if defined(CONFIG_FSL_CORENET) 394 #if defined(CONFIG_FSL_CORENET)
374 /* If this is corenet based SoC, bit-representation 395 /* If this is corenet based SoC, bit-representation
375 * for four times the clock divider values. 396 * for four times the clock divider values.
376 */ 397 */
377 lcrr_div *= 4; 398 lcrr_div *= 4;
378 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ 399 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
379 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) 400 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
380 /* 401 /*
381 * Yes, the entire PQ38 family use the same 402 * Yes, the entire PQ38 family use the same
382 * bit-representation for twice the clock divider values. 403 * bit-representation for twice the clock divider values.
383 */ 404 */
384 lcrr_div *= 2; 405 lcrr_div *= 2;
385 #endif 406 #endif
386 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div; 407 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
387 } else { 408 } else {
388 /* In case anyone cares what the unknown value is */ 409 /* In case anyone cares what the unknown value is */
389 sys_info->freq_localbus = lcrr_div; 410 sys_info->freq_localbus = lcrr_div;
390 } 411 }
391 #endif 412 #endif
392 413
393 #if defined(CONFIG_FSL_IFC) 414 #if defined(CONFIG_FSL_IFC)
394 ccr = in_be32(&ifc_regs->ifc_ccr); 415 ccr = in_be32(&ifc_regs->ifc_ccr);
395 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; 416 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
396 417
397 sys_info->freq_localbus = sys_info->freq_systembus / ccr; 418 sys_info->freq_localbus = sys_info->freq_systembus / ccr;
398 #endif 419 #endif
399 } 420 }
400 421
401 422
402 int get_clocks (void) 423 int get_clocks (void)
403 { 424 {
404 sys_info_t sys_info; 425 sys_info_t sys_info;
405 #ifdef CONFIG_MPC8544 426 #ifdef CONFIG_MPC8544
406 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; 427 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
407 #endif 428 #endif
408 #if defined(CONFIG_CPM2) 429 #if defined(CONFIG_CPM2)
409 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 430 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
410 uint sccr, dfbrg; 431 uint sccr, dfbrg;
411 432
412 /* set VCO = 4 * BRG */ 433 /* set VCO = 4 * BRG */
413 cpm->im_cpm_intctl.sccr &= 0xfffffffc; 434 cpm->im_cpm_intctl.sccr &= 0xfffffffc;
414 sccr = cpm->im_cpm_intctl.sccr; 435 sccr = cpm->im_cpm_intctl.sccr;
415 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; 436 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
416 #endif 437 #endif
417 get_sys_info (&sys_info); 438 get_sys_info (&sys_info);
418 gd->cpu_clk = sys_info.freq_processor[0]; 439 gd->cpu_clk = sys_info.freq_processor[0];
419 gd->bus_clk = sys_info.freq_systembus; 440 gd->bus_clk = sys_info.freq_systembus;
420 gd->mem_clk = sys_info.freq_ddrbus; 441 gd->mem_clk = sys_info.freq_ddrbus;
421 gd->arch.lbc_clk = sys_info.freq_localbus; 442 gd->arch.lbc_clk = sys_info.freq_localbus;
422 443
423 #ifdef CONFIG_QE 444 #ifdef CONFIG_QE
424 gd->arch.qe_clk = sys_info.freq_qe; 445 gd->arch.qe_clk = sys_info.freq_qe;
425 gd->arch.brg_clk = gd->arch.qe_clk / 2; 446 gd->arch.brg_clk = gd->arch.qe_clk / 2;
426 #endif 447 #endif
427 /* 448 /*
428 * The base clock for I2C depends on the actual SOC. Unfortunately, 449 * The base clock for I2C depends on the actual SOC. Unfortunately,
429 * there is no pattern that can be used to determine the frequency, so 450 * there is no pattern that can be used to determine the frequency, so
430 * the only choice is to look up the actual SOC number and use the value 451 * the only choice is to look up the actual SOC number and use the value
431 * for that SOC. This information is taken from application note 452 * for that SOC. This information is taken from application note
432 * AN2919. 453 * AN2919.
433 */ 454 */
434 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 455 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
435 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \ 456 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
436 defined(CONFIG_P1022) 457 defined(CONFIG_P1022)
437 gd->arch.i2c1_clk = sys_info.freq_systembus; 458 gd->arch.i2c1_clk = sys_info.freq_systembus;
438 #elif defined(CONFIG_MPC8544) 459 #elif defined(CONFIG_MPC8544)
439 /* 460 /*
440 * On the 8544, the I2C clock is the same as the SEC clock. This can be 461 * On the 8544, the I2C clock is the same as the SEC clock. This can be
441 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See 462 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
442 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all 463 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
443 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the 464 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
444 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. 465 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
445 */ 466 */
446 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) 467 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
447 gd->arch.i2c1_clk = sys_info.freq_systembus / 3; 468 gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
448 else 469 else
449 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 470 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
450 #else 471 #else
451 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ 472 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
452 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 473 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
453 #endif 474 #endif
454 gd->arch.i2c2_clk = gd->arch.i2c1_clk; 475 gd->arch.i2c2_clk = gd->arch.i2c1_clk;
455 476
456 #if defined(CONFIG_FSL_ESDHC) 477 #if defined(CONFIG_FSL_ESDHC)
457 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ 478 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
458 defined(CONFIG_P1014) 479 defined(CONFIG_P1014)
459 gd->arch.sdhc_clk = gd->bus_clk; 480 gd->arch.sdhc_clk = gd->bus_clk;
460 #else 481 #else
461 gd->arch.sdhc_clk = gd->bus_clk / 2; 482 gd->arch.sdhc_clk = gd->bus_clk / 2;
462 #endif 483 #endif
463 #endif /* defined(CONFIG_FSL_ESDHC) */ 484 #endif /* defined(CONFIG_FSL_ESDHC) */
464 485
465 #if defined(CONFIG_CPM2) 486 #if defined(CONFIG_CPM2)
466 gd->arch.vco_out = 2*sys_info.freq_systembus; 487 gd->arch.vco_out = 2*sys_info.freq_systembus;
467 gd->arch.cpm_clk = gd->arch.vco_out / 2; 488 gd->arch.cpm_clk = gd->arch.vco_out / 2;
468 gd->arch.scc_clk = gd->arch.vco_out / 4; 489 gd->arch.scc_clk = gd->arch.vco_out / 4;
469 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1))); 490 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
470 #endif 491 #endif
471 492
472 if(gd->cpu_clk != 0) return (0); 493 if(gd->cpu_clk != 0) return (0);
473 else return (1); 494 else return (1);
474 } 495 }
475 496
476 497
477 /******************************************** 498 /********************************************
478 * get_bus_freq 499 * get_bus_freq
479 * return system bus freq in Hz 500 * return system bus freq in Hz
480 *********************************************/ 501 *********************************************/
481 ulong get_bus_freq (ulong dummy) 502 ulong get_bus_freq (ulong dummy)
482 { 503 {
483 return gd->bus_clk; 504 return gd->bus_clk;
484 } 505 }
485 506
486 /******************************************** 507 /********************************************
487 * get_ddr_freq 508 * get_ddr_freq
488 * return ddr bus freq in Hz 509 * return ddr bus freq in Hz
489 *********************************************/ 510 *********************************************/
490 ulong get_ddr_freq (ulong dummy) 511 ulong get_ddr_freq (ulong dummy)
491 { 512 {
492 return gd->mem_clk; 513 return gd->mem_clk;
493 } 514 }
494 515
arch/powerpc/include/asm/config_mpc85xx.h
1 /* 1 /*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef _ASM_MPC85xx_CONFIG_H_ 7 #ifndef _ASM_MPC85xx_CONFIG_H_
8 #define _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_
9 9
10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
11 11
12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
14 #endif 14 #endif
15 15
16 /* 16 /*
17 * This macro should be removed when we no longer care about backwards 17 * This macro should be removed when we no longer care about backwards
18 * compatibility with older operating systems. 18 * compatibility with older operating systems.
19 */ 19 */
20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
21 21
22 #define FSL_DDR_VER_4_7 47 22 #define FSL_DDR_VER_4_7 47
23 #define FSL_DDR_VER_5_0 50 23 #define FSL_DDR_VER_5_0 50
24 24
25 /* Number of TLB CAM entries we have on FSL Book-E chips */ 25 /* Number of TLB CAM entries we have on FSL Book-E chips */
26 #if defined(CONFIG_E500MC) 26 #if defined(CONFIG_E500MC)
27 #define CONFIG_SYS_NUM_TLBCAMS 64 27 #define CONFIG_SYS_NUM_TLBCAMS 64
28 #elif defined(CONFIG_E500) 28 #elif defined(CONFIG_E500)
29 #define CONFIG_SYS_NUM_TLBCAMS 16 29 #define CONFIG_SYS_NUM_TLBCAMS 16
30 #endif 30 #endif
31 31
32 #if defined(CONFIG_MPC8536) 32 #if defined(CONFIG_MPC8536)
33 #define CONFIG_MAX_CPUS 1 33 #define CONFIG_MAX_CPUS 1
34 #define CONFIG_SYS_FSL_NUM_LAWS 12 34 #define CONFIG_SYS_FSL_NUM_LAWS 12
35 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 35 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
36 #define CONFIG_SYS_FSL_SEC_COMPAT 2 36 #define CONFIG_SYS_FSL_SEC_COMPAT 2
37 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 37 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
38 #define CONFIG_SYS_FSL_ERRATUM_A005125 38 #define CONFIG_SYS_FSL_ERRATUM_A005125
39 39
40 #elif defined(CONFIG_MPC8540) 40 #elif defined(CONFIG_MPC8540)
41 #define CONFIG_MAX_CPUS 1 41 #define CONFIG_MAX_CPUS 1
42 #define CONFIG_SYS_FSL_NUM_LAWS 8 42 #define CONFIG_SYS_FSL_NUM_LAWS 8
43 #define CONFIG_SYS_FSL_DDRC_GEN1 43 #define CONFIG_SYS_FSL_DDRC_GEN1
44 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 44 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
45 45
46 #elif defined(CONFIG_MPC8541) 46 #elif defined(CONFIG_MPC8541)
47 #define CONFIG_MAX_CPUS 1 47 #define CONFIG_MAX_CPUS 1
48 #define CONFIG_SYS_FSL_NUM_LAWS 8 48 #define CONFIG_SYS_FSL_NUM_LAWS 8
49 #define CONFIG_SYS_FSL_DDRC_GEN1 49 #define CONFIG_SYS_FSL_DDRC_GEN1
50 #define CONFIG_SYS_FSL_SEC_COMPAT 2 50 #define CONFIG_SYS_FSL_SEC_COMPAT 2
51 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 51 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
52 52
53 #elif defined(CONFIG_MPC8544) 53 #elif defined(CONFIG_MPC8544)
54 #define CONFIG_MAX_CPUS 1 54 #define CONFIG_MAX_CPUS 1
55 #define CONFIG_SYS_FSL_NUM_LAWS 10 55 #define CONFIG_SYS_FSL_NUM_LAWS 10
56 #define CONFIG_SYS_FSL_DDRC_GEN2 56 #define CONFIG_SYS_FSL_DDRC_GEN2
57 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 57 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
58 #define CONFIG_SYS_FSL_SEC_COMPAT 2 58 #define CONFIG_SYS_FSL_SEC_COMPAT 2
59 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 59 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
60 #define CONFIG_SYS_FSL_ERRATUM_A005125 60 #define CONFIG_SYS_FSL_ERRATUM_A005125
61 61
62 #elif defined(CONFIG_MPC8548) 62 #elif defined(CONFIG_MPC8548)
63 #define CONFIG_MAX_CPUS 1 63 #define CONFIG_MAX_CPUS 1
64 #define CONFIG_SYS_FSL_NUM_LAWS 10 64 #define CONFIG_SYS_FSL_NUM_LAWS 10
65 #define CONFIG_SYS_FSL_DDRC_GEN2 65 #define CONFIG_SYS_FSL_DDRC_GEN2
66 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 66 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
67 #define CONFIG_SYS_FSL_SEC_COMPAT 2 67 #define CONFIG_SYS_FSL_SEC_COMPAT 2
68 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 68 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
69 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 69 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
70 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 70 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
71 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 71 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
72 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 72 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
73 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 73 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
74 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 74 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
75 #define CONFIG_SYS_FSL_RMU 75 #define CONFIG_SYS_FSL_RMU
76 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 76 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
77 #define CONFIG_SYS_FSL_ERRATUM_A005125 77 #define CONFIG_SYS_FSL_ERRATUM_A005125
78 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 78 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
79 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 79 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
80 80
81 #elif defined(CONFIG_MPC8555) 81 #elif defined(CONFIG_MPC8555)
82 #define CONFIG_MAX_CPUS 1 82 #define CONFIG_MAX_CPUS 1
83 #define CONFIG_SYS_FSL_NUM_LAWS 8 83 #define CONFIG_SYS_FSL_NUM_LAWS 8
84 #define CONFIG_SYS_FSL_DDRC_GEN1 84 #define CONFIG_SYS_FSL_DDRC_GEN1
85 #define CONFIG_SYS_FSL_SEC_COMPAT 2 85 #define CONFIG_SYS_FSL_SEC_COMPAT 2
86 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 86 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
87 87
88 #elif defined(CONFIG_MPC8560) 88 #elif defined(CONFIG_MPC8560)
89 #define CONFIG_MAX_CPUS 1 89 #define CONFIG_MAX_CPUS 1
90 #define CONFIG_SYS_FSL_NUM_LAWS 8 90 #define CONFIG_SYS_FSL_NUM_LAWS 8
91 #define CONFIG_SYS_FSL_DDRC_GEN1 91 #define CONFIG_SYS_FSL_DDRC_GEN1
92 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 92 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
93 93
94 #elif defined(CONFIG_MPC8568) 94 #elif defined(CONFIG_MPC8568)
95 #define CONFIG_MAX_CPUS 1 95 #define CONFIG_MAX_CPUS 1
96 #define CONFIG_SYS_FSL_NUM_LAWS 10 96 #define CONFIG_SYS_FSL_NUM_LAWS 10
97 #define CONFIG_SYS_FSL_DDRC_GEN2 97 #define CONFIG_SYS_FSL_DDRC_GEN2
98 #define CONFIG_SYS_FSL_SEC_COMPAT 2 98 #define CONFIG_SYS_FSL_SEC_COMPAT 2
99 #define QE_MURAM_SIZE 0x10000UL 99 #define QE_MURAM_SIZE 0x10000UL
100 #define MAX_QE_RISC 2 100 #define MAX_QE_RISC 2
101 #define QE_NUM_OF_SNUM 28 101 #define QE_NUM_OF_SNUM 28
102 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 102 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
103 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 103 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
104 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 104 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
105 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 105 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
106 #define CONFIG_SYS_FSL_RMU 106 #define CONFIG_SYS_FSL_RMU
107 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 107 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
108 108
109 #elif defined(CONFIG_MPC8569) 109 #elif defined(CONFIG_MPC8569)
110 #define CONFIG_MAX_CPUS 1 110 #define CONFIG_MAX_CPUS 1
111 #define CONFIG_SYS_FSL_NUM_LAWS 10 111 #define CONFIG_SYS_FSL_NUM_LAWS 10
112 #define CONFIG_SYS_FSL_SEC_COMPAT 2 112 #define CONFIG_SYS_FSL_SEC_COMPAT 2
113 #define QE_MURAM_SIZE 0x20000UL 113 #define QE_MURAM_SIZE 0x20000UL
114 #define MAX_QE_RISC 4 114 #define MAX_QE_RISC 4
115 #define QE_NUM_OF_SNUM 46 115 #define QE_NUM_OF_SNUM 46
116 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 116 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
117 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 117 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
118 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 118 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
119 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 119 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
120 #define CONFIG_SYS_FSL_RMU 120 #define CONFIG_SYS_FSL_RMU
121 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 121 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
122 #define CONFIG_SYS_FSL_ERRATUM_A005125 122 #define CONFIG_SYS_FSL_ERRATUM_A005125
123 123
124 #elif defined(CONFIG_MPC8572) 124 #elif defined(CONFIG_MPC8572)
125 #define CONFIG_MAX_CPUS 2 125 #define CONFIG_MAX_CPUS 2
126 #define CONFIG_SYS_FSL_NUM_LAWS 12 126 #define CONFIG_SYS_FSL_NUM_LAWS 12
127 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 127 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
128 #define CONFIG_SYS_FSL_SEC_COMPAT 2 128 #define CONFIG_SYS_FSL_SEC_COMPAT 2
129 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 129 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
130 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 130 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
131 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 131 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
132 #define CONFIG_SYS_FSL_ERRATUM_A005125 132 #define CONFIG_SYS_FSL_ERRATUM_A005125
133 133
134 #elif defined(CONFIG_P1010) 134 #elif defined(CONFIG_P1010)
135 #define CONFIG_MAX_CPUS 1 135 #define CONFIG_MAX_CPUS 1
136 #define CONFIG_FSL_SDHC_V2_3 136 #define CONFIG_FSL_SDHC_V2_3
137 #define CONFIG_SYS_FSL_NUM_LAWS 12 137 #define CONFIG_SYS_FSL_NUM_LAWS 12
138 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 138 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
139 #define CONFIG_TSECV2 139 #define CONFIG_TSECV2
140 #define CONFIG_SYS_FSL_SEC_COMPAT 4 140 #define CONFIG_SYS_FSL_SEC_COMPAT 4
141 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 141 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
142 #define CONFIG_NUM_DDR_CONTROLLERS 1 142 #define CONFIG_NUM_DDR_CONTROLLERS 1
143 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 143 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
144 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 144 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
145 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 145 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
146 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 146 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
147 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 147 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
148 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 148 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
149 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 149 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
150 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 150 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
151 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 151 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
152 #define CONFIG_SYS_FSL_ERRATUM_A005125 152 #define CONFIG_SYS_FSL_ERRATUM_A005125
153 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 153 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
154 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 154 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
155 155
156 /* P1011 is single core version of P1020 */ 156 /* P1011 is single core version of P1020 */
157 #elif defined(CONFIG_P1011) 157 #elif defined(CONFIG_P1011)
158 #define CONFIG_MAX_CPUS 1 158 #define CONFIG_MAX_CPUS 1
159 #define CONFIG_SYS_FSL_NUM_LAWS 12 159 #define CONFIG_SYS_FSL_NUM_LAWS 12
160 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 160 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
161 #define CONFIG_TSECV2 161 #define CONFIG_TSECV2
162 #define CONFIG_FSL_PCIE_DISABLE_ASPM 162 #define CONFIG_FSL_PCIE_DISABLE_ASPM
163 #define CONFIG_SYS_FSL_SEC_COMPAT 2 163 #define CONFIG_SYS_FSL_SEC_COMPAT 2
164 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 164 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
165 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 165 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
166 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 166 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
167 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 167 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
168 #define CONFIG_SYS_FSL_ERRATUM_A005125 168 #define CONFIG_SYS_FSL_ERRATUM_A005125
169 169
170 /* P1012 is single core version of P1021 */ 170 /* P1012 is single core version of P1021 */
171 #elif defined(CONFIG_P1012) 171 #elif defined(CONFIG_P1012)
172 #define CONFIG_MAX_CPUS 1 172 #define CONFIG_MAX_CPUS 1
173 #define CONFIG_SYS_FSL_NUM_LAWS 12 173 #define CONFIG_SYS_FSL_NUM_LAWS 12
174 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 174 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
175 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 175 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
176 #define CONFIG_TSECV2 176 #define CONFIG_TSECV2
177 #define CONFIG_FSL_PCIE_DISABLE_ASPM 177 #define CONFIG_FSL_PCIE_DISABLE_ASPM
178 #define CONFIG_SYS_FSL_SEC_COMPAT 2 178 #define CONFIG_SYS_FSL_SEC_COMPAT 2
179 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 179 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
180 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 180 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
181 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 181 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
182 #define QE_MURAM_SIZE 0x6000UL 182 #define QE_MURAM_SIZE 0x6000UL
183 #define MAX_QE_RISC 1 183 #define MAX_QE_RISC 1
184 #define QE_NUM_OF_SNUM 28 184 #define QE_NUM_OF_SNUM 28
185 #define CONFIG_SYS_FSL_ERRATUM_A005125 185 #define CONFIG_SYS_FSL_ERRATUM_A005125
186 186
187 /* P1013 is single core version of P1022 */ 187 /* P1013 is single core version of P1022 */
188 #elif defined(CONFIG_P1013) 188 #elif defined(CONFIG_P1013)
189 #define CONFIG_MAX_CPUS 1 189 #define CONFIG_MAX_CPUS 1
190 #define CONFIG_SYS_FSL_NUM_LAWS 12 190 #define CONFIG_SYS_FSL_NUM_LAWS 12
191 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 191 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
192 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 192 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
193 #define CONFIG_TSECV2 193 #define CONFIG_TSECV2
194 #define CONFIG_SYS_FSL_SEC_COMPAT 2 194 #define CONFIG_SYS_FSL_SEC_COMPAT 2
195 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 195 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
196 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 196 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
197 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 197 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
198 #define CONFIG_FSL_SATA_ERRATUM_A001 198 #define CONFIG_FSL_SATA_ERRATUM_A001
199 #define CONFIG_SYS_FSL_ERRATUM_A005125 199 #define CONFIG_SYS_FSL_ERRATUM_A005125
200 200
201 #elif defined(CONFIG_P1014) 201 #elif defined(CONFIG_P1014)
202 #define CONFIG_MAX_CPUS 1 202 #define CONFIG_MAX_CPUS 1
203 #define CONFIG_FSL_SDHC_V2_3 203 #define CONFIG_FSL_SDHC_V2_3
204 #define CONFIG_SYS_FSL_NUM_LAWS 12 204 #define CONFIG_SYS_FSL_NUM_LAWS 12
205 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 205 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
206 #define CONFIG_TSECV2 206 #define CONFIG_TSECV2
207 #define CONFIG_SYS_FSL_SEC_COMPAT 4 207 #define CONFIG_SYS_FSL_SEC_COMPAT 4
208 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 208 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
209 #define CONFIG_NUM_DDR_CONTROLLERS 1 209 #define CONFIG_NUM_DDR_CONTROLLERS 1
210 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 210 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
211 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 211 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
212 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 212 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
213 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 213 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
214 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 214 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
215 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 215 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
216 216
217 /* P1017 is single core version of P1023 */ 217 /* P1017 is single core version of P1023 */
218 #elif defined(CONFIG_P1017) 218 #elif defined(CONFIG_P1017)
219 #define CONFIG_MAX_CPUS 1 219 #define CONFIG_MAX_CPUS 1
220 #define CONFIG_SYS_FSL_NUM_LAWS 12 220 #define CONFIG_SYS_FSL_NUM_LAWS 12
221 #define CONFIG_SYS_FSL_SEC_COMPAT 4 221 #define CONFIG_SYS_FSL_SEC_COMPAT 4
222 #define CONFIG_SYS_NUM_FMAN 1 222 #define CONFIG_SYS_NUM_FMAN 1
223 #define CONFIG_SYS_NUM_FM1_DTSEC 2 223 #define CONFIG_SYS_NUM_FM1_DTSEC 2
224 #define CONFIG_NUM_DDR_CONTROLLERS 1 224 #define CONFIG_NUM_DDR_CONTROLLERS 1
225 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 225 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
226 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 226 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
227 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 227 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
228 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 228 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
229 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 229 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
230 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 230 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
231 #define CONFIG_SYS_FSL_ERRATUM_A005125 231 #define CONFIG_SYS_FSL_ERRATUM_A005125
232 232
233 #elif defined(CONFIG_P1020) 233 #elif defined(CONFIG_P1020)
234 #define CONFIG_MAX_CPUS 2 234 #define CONFIG_MAX_CPUS 2
235 #define CONFIG_SYS_FSL_NUM_LAWS 12 235 #define CONFIG_SYS_FSL_NUM_LAWS 12
236 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 236 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
237 #define CONFIG_TSECV2 237 #define CONFIG_TSECV2
238 #define CONFIG_FSL_PCIE_DISABLE_ASPM 238 #define CONFIG_FSL_PCIE_DISABLE_ASPM
239 #define CONFIG_SYS_FSL_SEC_COMPAT 2 239 #define CONFIG_SYS_FSL_SEC_COMPAT 2
240 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 240 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
241 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 241 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
242 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 242 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
243 #define CONFIG_SYS_FSL_ERRATUM_A005125 243 #define CONFIG_SYS_FSL_ERRATUM_A005125
244 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 244 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
245 245
246 #elif defined(CONFIG_P1021) 246 #elif defined(CONFIG_P1021)
247 #define CONFIG_MAX_CPUS 2 247 #define CONFIG_MAX_CPUS 2
248 #define CONFIG_SYS_FSL_NUM_LAWS 12 248 #define CONFIG_SYS_FSL_NUM_LAWS 12
249 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 249 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
250 #define CONFIG_TSECV2 250 #define CONFIG_TSECV2
251 #define CONFIG_FSL_PCIE_DISABLE_ASPM 251 #define CONFIG_FSL_PCIE_DISABLE_ASPM
252 #define CONFIG_SYS_FSL_SEC_COMPAT 2 252 #define CONFIG_SYS_FSL_SEC_COMPAT 2
253 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 253 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
254 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 254 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
255 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 255 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
256 #define QE_MURAM_SIZE 0x6000UL 256 #define QE_MURAM_SIZE 0x6000UL
257 #define MAX_QE_RISC 1 257 #define MAX_QE_RISC 1
258 #define QE_NUM_OF_SNUM 28 258 #define QE_NUM_OF_SNUM 28
259 #define CONFIG_SYS_FSL_ERRATUM_A005125 259 #define CONFIG_SYS_FSL_ERRATUM_A005125
260 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 260 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
261 261
262 #elif defined(CONFIG_P1022) 262 #elif defined(CONFIG_P1022)
263 #define CONFIG_MAX_CPUS 2 263 #define CONFIG_MAX_CPUS 2
264 #define CONFIG_SYS_FSL_NUM_LAWS 12 264 #define CONFIG_SYS_FSL_NUM_LAWS 12
265 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 265 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
266 #define CONFIG_TSECV2 266 #define CONFIG_TSECV2
267 #define CONFIG_SYS_FSL_SEC_COMPAT 2 267 #define CONFIG_SYS_FSL_SEC_COMPAT 2
268 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 268 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
269 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 269 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
270 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 270 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
271 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 271 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
272 #define CONFIG_FSL_SATA_ERRATUM_A001 272 #define CONFIG_FSL_SATA_ERRATUM_A001
273 #define CONFIG_SYS_FSL_ERRATUM_A005125 273 #define CONFIG_SYS_FSL_ERRATUM_A005125
274 274
275 #elif defined(CONFIG_P1023) 275 #elif defined(CONFIG_P1023)
276 #define CONFIG_MAX_CPUS 2 276 #define CONFIG_MAX_CPUS 2
277 #define CONFIG_SYS_FSL_NUM_LAWS 12 277 #define CONFIG_SYS_FSL_NUM_LAWS 12
278 #define CONFIG_SYS_FSL_SEC_COMPAT 4 278 #define CONFIG_SYS_FSL_SEC_COMPAT 4
279 #define CONFIG_SYS_NUM_FMAN 1 279 #define CONFIG_SYS_NUM_FMAN 1
280 #define CONFIG_SYS_NUM_FM1_DTSEC 2 280 #define CONFIG_SYS_NUM_FM1_DTSEC 2
281 #define CONFIG_NUM_DDR_CONTROLLERS 1 281 #define CONFIG_NUM_DDR_CONTROLLERS 1
282 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 282 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
283 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 283 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
284 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 284 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
285 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 285 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
286 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 286 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
287 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 287 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
288 #define CONFIG_SYS_FSL_ERRATUM_A005125 288 #define CONFIG_SYS_FSL_ERRATUM_A005125
289 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 289 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
290 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 290 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
291 291
292 /* P1024 is lower end variant of P1020 */ 292 /* P1024 is lower end variant of P1020 */
293 #elif defined(CONFIG_P1024) 293 #elif defined(CONFIG_P1024)
294 #define CONFIG_MAX_CPUS 2 294 #define CONFIG_MAX_CPUS 2
295 #define CONFIG_SYS_FSL_NUM_LAWS 12 295 #define CONFIG_SYS_FSL_NUM_LAWS 12
296 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 296 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
297 #define CONFIG_TSECV2 297 #define CONFIG_TSECV2
298 #define CONFIG_FSL_PCIE_DISABLE_ASPM 298 #define CONFIG_FSL_PCIE_DISABLE_ASPM
299 #define CONFIG_SYS_FSL_SEC_COMPAT 2 299 #define CONFIG_SYS_FSL_SEC_COMPAT 2
300 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 300 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
301 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 301 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
302 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 302 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
303 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 303 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
304 #define CONFIG_SYS_FSL_ERRATUM_A005125 304 #define CONFIG_SYS_FSL_ERRATUM_A005125
305 305
306 /* P1025 is lower end variant of P1021 */ 306 /* P1025 is lower end variant of P1021 */
307 #elif defined(CONFIG_P1025) 307 #elif defined(CONFIG_P1025)
308 #define CONFIG_MAX_CPUS 2 308 #define CONFIG_MAX_CPUS 2
309 #define CONFIG_SYS_FSL_NUM_LAWS 12 309 #define CONFIG_SYS_FSL_NUM_LAWS 12
310 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 310 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
311 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 311 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
312 #define CONFIG_TSECV2 312 #define CONFIG_TSECV2
313 #define CONFIG_FSL_PCIE_DISABLE_ASPM 313 #define CONFIG_FSL_PCIE_DISABLE_ASPM
314 #define CONFIG_SYS_FSL_SEC_COMPAT 2 314 #define CONFIG_SYS_FSL_SEC_COMPAT 2
315 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 315 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
316 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 316 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
317 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 317 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
318 #define QE_MURAM_SIZE 0x6000UL 318 #define QE_MURAM_SIZE 0x6000UL
319 #define MAX_QE_RISC 1 319 #define MAX_QE_RISC 1
320 #define QE_NUM_OF_SNUM 28 320 #define QE_NUM_OF_SNUM 28
321 #define CONFIG_SYS_FSL_ERRATUM_A005125 321 #define CONFIG_SYS_FSL_ERRATUM_A005125
322 322
323 /* P2010 is single core version of P2020 */ 323 /* P2010 is single core version of P2020 */
324 #elif defined(CONFIG_P2010) 324 #elif defined(CONFIG_P2010)
325 #define CONFIG_MAX_CPUS 1 325 #define CONFIG_MAX_CPUS 1
326 #define CONFIG_SYS_FSL_NUM_LAWS 12 326 #define CONFIG_SYS_FSL_NUM_LAWS 12
327 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 327 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
328 #define CONFIG_SYS_FSL_SEC_COMPAT 2 328 #define CONFIG_SYS_FSL_SEC_COMPAT 2
329 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 329 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
330 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 330 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
331 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 331 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
332 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 332 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
333 #define CONFIG_SYS_FSL_ERRATUM_A005125 333 #define CONFIG_SYS_FSL_ERRATUM_A005125
334 334
335 #elif defined(CONFIG_P2020) 335 #elif defined(CONFIG_P2020)
336 #define CONFIG_MAX_CPUS 2 336 #define CONFIG_MAX_CPUS 2
337 #define CONFIG_SYS_FSL_NUM_LAWS 12 337 #define CONFIG_SYS_FSL_NUM_LAWS 12
338 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 338 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
339 #define CONFIG_SYS_FSL_SEC_COMPAT 2 339 #define CONFIG_SYS_FSL_SEC_COMPAT 2
340 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 340 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
341 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 341 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
342 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 342 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
343 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 343 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
344 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 344 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
345 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 345 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
346 #define CONFIG_SYS_FSL_RMU 346 #define CONFIG_SYS_FSL_RMU
347 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 347 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
348 #define CONFIG_SYS_FSL_ERRATUM_A005125 348 #define CONFIG_SYS_FSL_ERRATUM_A005125
349 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 349 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
350 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 350 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
351 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 351 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
352 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 352 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
353 #define CONFIG_MAX_CPUS 4 353 #define CONFIG_MAX_CPUS 4
354 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 354 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
355 #define CONFIG_SYS_FSL_NUM_LAWS 32 355 #define CONFIG_SYS_FSL_NUM_LAWS 32
356 #define CONFIG_SYS_FSL_SEC_COMPAT 4 356 #define CONFIG_SYS_FSL_SEC_COMPAT 4
357 #define CONFIG_SYS_NUM_FMAN 1 357 #define CONFIG_SYS_NUM_FMAN 1
358 #define CONFIG_SYS_NUM_FM1_DTSEC 5 358 #define CONFIG_SYS_NUM_FM1_DTSEC 5
359 #define CONFIG_SYS_NUM_FM1_10GEC 1 359 #define CONFIG_SYS_NUM_FM1_10GEC 1
360 #define CONFIG_NUM_DDR_CONTROLLERS 1 360 #define CONFIG_NUM_DDR_CONTROLLERS 1
361 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 361 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
362 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 362 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
363 #define CONFIG_SYS_FSL_TBCLK_DIV 32 363 #define CONFIG_SYS_FSL_TBCLK_DIV 32
364 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 364 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
365 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 365 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
366 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 366 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
367 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 367 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
368 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 368 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
369 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 369 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
370 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 370 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
371 #define CONFIG_SYS_FSL_ERRATUM_USB14 371 #define CONFIG_SYS_FSL_ERRATUM_USB14
372 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 372 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
373 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 373 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
374 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 374 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
375 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 375 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
376 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 376 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
377 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 377 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
378 #define CONFIG_SYS_FSL_ERRATUM_A004510 378 #define CONFIG_SYS_FSL_ERRATUM_A004510
379 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 379 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
380 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 380 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
381 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 381 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
382 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 382 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
383 #define CONFIG_SYS_FSL_ERRATUM_A004849 383 #define CONFIG_SYS_FSL_ERRATUM_A004849
384 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 384 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
385 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 385 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
386 386
387 #elif defined(CONFIG_PPC_P3041) 387 #elif defined(CONFIG_PPC_P3041)
388 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 388 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
389 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 389 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
390 #define CONFIG_MAX_CPUS 4 390 #define CONFIG_MAX_CPUS 4
391 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 391 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
392 #define CONFIG_SYS_FSL_NUM_LAWS 32 392 #define CONFIG_SYS_FSL_NUM_LAWS 32
393 #define CONFIG_SYS_FSL_SEC_COMPAT 4 393 #define CONFIG_SYS_FSL_SEC_COMPAT 4
394 #define CONFIG_SYS_NUM_FMAN 1 394 #define CONFIG_SYS_NUM_FMAN 1
395 #define CONFIG_SYS_NUM_FM1_DTSEC 5 395 #define CONFIG_SYS_NUM_FM1_DTSEC 5
396 #define CONFIG_SYS_NUM_FM1_10GEC 1 396 #define CONFIG_SYS_NUM_FM1_10GEC 1
397 #define CONFIG_NUM_DDR_CONTROLLERS 1 397 #define CONFIG_NUM_DDR_CONTROLLERS 1
398 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 398 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
399 #define CONFIG_SYS_FSL_TBCLK_DIV 32 399 #define CONFIG_SYS_FSL_TBCLK_DIV 32
400 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 400 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
401 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 401 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
402 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 402 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
403 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 403 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
404 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 404 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
405 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 405 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
406 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 406 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
407 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 407 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
408 #define CONFIG_SYS_FSL_ERRATUM_USB14 408 #define CONFIG_SYS_FSL_ERRATUM_USB14
409 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 409 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
410 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 410 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
411 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 411 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
412 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 412 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
413 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 413 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
414 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 414 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
415 #define CONFIG_SYS_FSL_ERRATUM_A004510 415 #define CONFIG_SYS_FSL_ERRATUM_A004510
416 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 416 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
417 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 417 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
418 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 418 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
419 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 419 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
420 #define CONFIG_SYS_FSL_ERRATUM_A004849 420 #define CONFIG_SYS_FSL_ERRATUM_A004849
421 #define CONFIG_SYS_FSL_ERRATUM_A005812 421 #define CONFIG_SYS_FSL_ERRATUM_A005812
422 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 422 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
423 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 423 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
424 424
425 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 425 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
426 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 426 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
427 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 427 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
428 #define CONFIG_MAX_CPUS 8 428 #define CONFIG_MAX_CPUS 8
429 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 429 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
430 #define CONFIG_SYS_FSL_NUM_LAWS 32 430 #define CONFIG_SYS_FSL_NUM_LAWS 32
431 #define CONFIG_SYS_FSL_SEC_COMPAT 4 431 #define CONFIG_SYS_FSL_SEC_COMPAT 4
432 #define CONFIG_SYS_NUM_FMAN 2 432 #define CONFIG_SYS_NUM_FMAN 2
433 #define CONFIG_SYS_NUM_FM1_DTSEC 4 433 #define CONFIG_SYS_NUM_FM1_DTSEC 4
434 #define CONFIG_SYS_NUM_FM2_DTSEC 4 434 #define CONFIG_SYS_NUM_FM2_DTSEC 4
435 #define CONFIG_SYS_NUM_FM1_10GEC 1 435 #define CONFIG_SYS_NUM_FM1_10GEC 1
436 #define CONFIG_SYS_NUM_FM2_10GEC 1 436 #define CONFIG_SYS_NUM_FM2_10GEC 1
437 #define CONFIG_NUM_DDR_CONTROLLERS 2 437 #define CONFIG_NUM_DDR_CONTROLLERS 2
438 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 438 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
439 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 439 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
440 #define CONFIG_SYS_FSL_TBCLK_DIV 16 440 #define CONFIG_SYS_FSL_TBCLK_DIV 16
441 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 441 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
442 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 442 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
443 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 443 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
444 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 444 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
445 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 445 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
446 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 446 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
447 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 447 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
448 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 448 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
449 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 449 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
450 #define CONFIG_SYS_P4080_ERRATUM_CPU22 450 #define CONFIG_SYS_P4080_ERRATUM_CPU22
451 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 451 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
452 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 452 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
453 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 453 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
454 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 454 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
455 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 455 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
456 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 456 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
457 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 457 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
458 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 458 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
459 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 459 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
460 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 460 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
461 #define CONFIG_SYS_FSL_RMU 461 #define CONFIG_SYS_FSL_RMU
462 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 462 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
463 #define CONFIG_SYS_FSL_ERRATUM_A004510 463 #define CONFIG_SYS_FSL_ERRATUM_A004510
464 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 464 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
465 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 465 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
466 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 466 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
467 #define CONFIG_SYS_FSL_ERRATUM_A004849 467 #define CONFIG_SYS_FSL_ERRATUM_A004849
468 #define CONFIG_SYS_FSL_ERRATUM_A004580 468 #define CONFIG_SYS_FSL_ERRATUM_A004580
469 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 469 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
470 #define CONFIG_SYS_FSL_ERRATUM_A005812 470 #define CONFIG_SYS_FSL_ERRATUM_A005812
471 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 471 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
472 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 472 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
473 473
474 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 474 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
475 #define CONFIG_SYS_PPC64 /* 64-bit core */ 475 #define CONFIG_SYS_PPC64 /* 64-bit core */
476 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 476 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
477 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 477 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
478 #define CONFIG_MAX_CPUS 2 478 #define CONFIG_MAX_CPUS 2
479 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 479 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
480 #define CONFIG_SYS_FSL_NUM_LAWS 32 480 #define CONFIG_SYS_FSL_NUM_LAWS 32
481 #define CONFIG_SYS_FSL_SEC_COMPAT 4 481 #define CONFIG_SYS_FSL_SEC_COMPAT 4
482 #define CONFIG_SYS_NUM_FMAN 1 482 #define CONFIG_SYS_NUM_FMAN 1
483 #define CONFIG_SYS_NUM_FM1_DTSEC 5 483 #define CONFIG_SYS_NUM_FM1_DTSEC 5
484 #define CONFIG_SYS_NUM_FM1_10GEC 1 484 #define CONFIG_SYS_NUM_FM1_10GEC 1
485 #define CONFIG_NUM_DDR_CONTROLLERS 2 485 #define CONFIG_NUM_DDR_CONTROLLERS 2
486 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 486 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
487 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 487 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
488 #define CONFIG_SYS_FSL_TBCLK_DIV 32 488 #define CONFIG_SYS_FSL_TBCLK_DIV 32
489 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 489 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
490 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 490 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
491 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 491 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
492 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 492 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
493 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 493 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
494 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 494 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
495 #define CONFIG_SYS_FSL_ERRATUM_USB14 495 #define CONFIG_SYS_FSL_ERRATUM_USB14
496 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 496 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
497 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 497 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
498 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 498 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
499 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 499 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
500 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 500 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
501 #define CONFIG_SYS_FSL_ERRATUM_A004510 501 #define CONFIG_SYS_FSL_ERRATUM_A004510
502 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 502 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
503 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 503 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
504 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 504 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
505 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 505 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
506 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 506 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
507 507
508 #elif defined(CONFIG_PPC_P5040) 508 #elif defined(CONFIG_PPC_P5040)
509 #define CONFIG_SYS_PPC64 509 #define CONFIG_SYS_PPC64
510 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 510 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
511 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 511 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
512 #define CONFIG_MAX_CPUS 4 512 #define CONFIG_MAX_CPUS 4
513 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 513 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
514 #define CONFIG_SYS_FSL_NUM_LAWS 32 514 #define CONFIG_SYS_FSL_NUM_LAWS 32
515 #define CONFIG_SYS_FSL_SEC_COMPAT 4 515 #define CONFIG_SYS_FSL_SEC_COMPAT 4
516 #define CONFIG_SYS_NUM_FMAN 2 516 #define CONFIG_SYS_NUM_FMAN 2
517 #define CONFIG_SYS_NUM_FM1_DTSEC 5 517 #define CONFIG_SYS_NUM_FM1_DTSEC 5
518 #define CONFIG_SYS_NUM_FM1_10GEC 1 518 #define CONFIG_SYS_NUM_FM1_10GEC 1
519 #define CONFIG_SYS_NUM_FM2_DTSEC 5 519 #define CONFIG_SYS_NUM_FM2_DTSEC 5
520 #define CONFIG_SYS_NUM_FM2_10GEC 1 520 #define CONFIG_SYS_NUM_FM2_10GEC 1
521 #define CONFIG_NUM_DDR_CONTROLLERS 2 521 #define CONFIG_NUM_DDR_CONTROLLERS 2
522 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 522 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
523 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 523 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
524 #define CONFIG_SYS_FSL_TBCLK_DIV 16 524 #define CONFIG_SYS_FSL_TBCLK_DIV 16
525 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 525 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
526 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 526 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
527 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 527 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
528 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 528 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
529 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 529 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
530 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 530 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
531 #define CONFIG_SYS_FSL_ERRATUM_USB14 531 #define CONFIG_SYS_FSL_ERRATUM_USB14
532 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 532 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
533 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 533 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
534 #define CONFIG_SYS_FSL_ERRATUM_A004699 534 #define CONFIG_SYS_FSL_ERRATUM_A004699
535 #define CONFIG_SYS_FSL_ERRATUM_A004510 535 #define CONFIG_SYS_FSL_ERRATUM_A004510
536 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 536 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
537 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 537 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
538 #define CONFIG_SYS_FSL_ERRATUM_A005812 538 #define CONFIG_SYS_FSL_ERRATUM_A005812
539 539
540 #elif defined(CONFIG_BSC9131) 540 #elif defined(CONFIG_BSC9131)
541 #define CONFIG_MAX_CPUS 1 541 #define CONFIG_MAX_CPUS 1
542 #define CONFIG_FSL_SDHC_V2_3 542 #define CONFIG_FSL_SDHC_V2_3
543 #define CONFIG_SYS_FSL_NUM_LAWS 12 543 #define CONFIG_SYS_FSL_NUM_LAWS 12
544 #define CONFIG_TSECV2 544 #define CONFIG_TSECV2
545 #define CONFIG_SYS_FSL_SEC_COMPAT 4 545 #define CONFIG_SYS_FSL_SEC_COMPAT 4
546 #define CONFIG_NUM_DDR_CONTROLLERS 1 546 #define CONFIG_NUM_DDR_CONTROLLERS 1
547 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 547 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
548 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 548 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
549 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 549 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
550 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 550 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
551 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 551 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
552 #define CONFIG_NAND_FSL_IFC 552 #define CONFIG_NAND_FSL_IFC
553 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 553 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
554 #define CONFIG_SYS_FSL_ERRATUM_A005125 554 #define CONFIG_SYS_FSL_ERRATUM_A005125
555 555
556 #elif defined(CONFIG_BSC9132) 556 #elif defined(CONFIG_BSC9132)
557 #define CONFIG_MAX_CPUS 2 557 #define CONFIG_MAX_CPUS 2
558 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 558 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
559 #define CONFIG_FSL_SDHC_V2_3 559 #define CONFIG_FSL_SDHC_V2_3
560 #define CONFIG_SYS_FSL_NUM_LAWS 12 560 #define CONFIG_SYS_FSL_NUM_LAWS 12
561 #define CONFIG_TSECV2 561 #define CONFIG_TSECV2
562 #define CONFIG_SYS_FSL_SEC_COMPAT 4 562 #define CONFIG_SYS_FSL_SEC_COMPAT 4
563 #define CONFIG_NUM_DDR_CONTROLLERS 2 563 #define CONFIG_NUM_DDR_CONTROLLERS 2
564 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 564 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
565 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 565 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
566 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 566 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
567 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 567 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
568 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 568 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
569 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 569 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
570 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 570 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
571 #define CONFIG_NAND_FSL_IFC 571 #define CONFIG_NAND_FSL_IFC
572 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 572 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
573 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 573 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
574 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 574 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
575 #define CONFIG_SYS_FSL_ERRATUM_A005125 575 #define CONFIG_SYS_FSL_ERRATUM_A005125
576 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 576 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
577 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 577 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
578 578
579 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 579 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
580 #define CONFIG_E6500 580 #define CONFIG_E6500
581 #define CONFIG_SYS_PPC64 /* 64-bit core */ 581 #define CONFIG_SYS_PPC64 /* 64-bit core */
582 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 582 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
583 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 583 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
584 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 584 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
585 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 585 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
586 #ifdef CONFIG_PPC_T4240 586 #ifdef CONFIG_PPC_T4240
587 #define CONFIG_MAX_CPUS 12 587 #define CONFIG_MAX_CPUS 12
588 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 588 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
589 #define CONFIG_SYS_NUM_FM1_DTSEC 8 589 #define CONFIG_SYS_NUM_FM1_DTSEC 8
590 #define CONFIG_SYS_NUM_FM1_10GEC 2 590 #define CONFIG_SYS_NUM_FM1_10GEC 2
591 #define CONFIG_SYS_NUM_FM2_DTSEC 8 591 #define CONFIG_SYS_NUM_FM2_DTSEC 8
592 #define CONFIG_SYS_NUM_FM2_10GEC 2 592 #define CONFIG_SYS_NUM_FM2_10GEC 2
593 #define CONFIG_NUM_DDR_CONTROLLERS 3 593 #define CONFIG_NUM_DDR_CONTROLLERS 3
594 #else 594 #else
595 #define CONFIG_MAX_CPUS 8 595 #define CONFIG_MAX_CPUS 8
596 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 596 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
597 #define CONFIG_SYS_NUM_FM1_DTSEC 7 597 #define CONFIG_SYS_NUM_FM1_DTSEC 7
598 #define CONFIG_SYS_NUM_FM1_10GEC 1 598 #define CONFIG_SYS_NUM_FM1_10GEC 1
599 #define CONFIG_SYS_NUM_FM2_DTSEC 7 599 #define CONFIG_SYS_NUM_FM2_DTSEC 7
600 #define CONFIG_SYS_NUM_FM2_10GEC 1 600 #define CONFIG_SYS_NUM_FM2_10GEC 1
601 #define CONFIG_NUM_DDR_CONTROLLERS 2 601 #define CONFIG_NUM_DDR_CONTROLLERS 2
602 #endif 602 #endif
603 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 603 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
604 #define CONFIG_SYS_FSL_NUM_LAWS 32 604 #define CONFIG_SYS_FSL_NUM_LAWS 32
605 #define CONFIG_SYS_FSL_SRDS_1 605 #define CONFIG_SYS_FSL_SRDS_1
606 #define CONFIG_SYS_FSL_SRDS_2 606 #define CONFIG_SYS_FSL_SRDS_2
607 #define CONFIG_SYS_FSL_SRDS_3 607 #define CONFIG_SYS_FSL_SRDS_3
608 #define CONFIG_SYS_FSL_SRDS_4 608 #define CONFIG_SYS_FSL_SRDS_4
609 #define CONFIG_SYS_FSL_SEC_COMPAT 4 609 #define CONFIG_SYS_FSL_SEC_COMPAT 4
610 #define CONFIG_SYS_NUM_FMAN 2 610 #define CONFIG_SYS_NUM_FMAN 2
611 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 611 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
612 #define CONFIG_SYS_PME_CLK 0 612 #define CONFIG_SYS_PME_CLK 0
613 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 613 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
614 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 614 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
615 #define CONFIG_SYS_FMAN_V3 615 #define CONFIG_SYS_FMAN_V3
616 #define CONFIG_SYS_FM1_CLK 3 616 #define CONFIG_SYS_FM1_CLK 3
617 #define CONFIG_SYS_FM2_CLK 3 617 #define CONFIG_SYS_FM2_CLK 3
618 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 618 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
619 #define CONFIG_SYS_FSL_TBCLK_DIV 16 619 #define CONFIG_SYS_FSL_TBCLK_DIV 16
620 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 620 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
621 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 621 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
622 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 622 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
623 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 623 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
624 #define CONFIG_SYS_FSL_SRIO_LIODN 624 #define CONFIG_SYS_FSL_SRIO_LIODN
625 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 625 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
626 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 626 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
627 #define CONFIG_SYS_FSL_ERRATUM_A004468 627 #define CONFIG_SYS_FSL_ERRATUM_A004468
628 #define CONFIG_SYS_FSL_ERRATUM_A_004934 628 #define CONFIG_SYS_FSL_ERRATUM_A_004934
629 #define CONFIG_SYS_FSL_ERRATUM_A005871 629 #define CONFIG_SYS_FSL_ERRATUM_A005871
630 #define CONFIG_SYS_FSL_ERRATUM_A006379 630 #define CONFIG_SYS_FSL_ERRATUM_A006379
631 #define CONFIG_SYS_FSL_ERRATUM_A006593 631 #define CONFIG_SYS_FSL_ERRATUM_A006593
632 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 632 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
633 #define CONFIG_SYS_FSL_PCI_VER_3_X 633 #define CONFIG_SYS_FSL_PCI_VER_3_X
634 634
635 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 635 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
636 #define CONFIG_E6500 636 #define CONFIG_E6500
637 #define CONFIG_SYS_PPC64 /* 64-bit core */ 637 #define CONFIG_SYS_PPC64 /* 64-bit core */
638 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 638 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
639 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 639 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
640 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 640 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
641 #define CONFIG_SYS_FSL_NUM_LAWS 32 641 #define CONFIG_SYS_FSL_NUM_LAWS 32
642 #define CONFIG_SYS_FSL_SRDS_1 642 #define CONFIG_SYS_FSL_SRDS_1
643 #define CONFIG_SYS_FSL_SRDS_2 643 #define CONFIG_SYS_FSL_SRDS_2
644 #define CONFIG_SYS_FSL_SEC_COMPAT 4 644 #define CONFIG_SYS_FSL_SEC_COMPAT 4
645 #define CONFIG_SYS_NUM_FMAN 1 645 #define CONFIG_SYS_NUM_FMAN 1
646 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 646 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
647 #define CONFIG_SYS_FM1_CLK 0 647 #define CONFIG_SYS_FM1_CLK 0
648 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 648 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
649 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 649 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
650 #define CONFIG_SYS_FMAN_V3 650 #define CONFIG_SYS_FMAN_V3
651 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 651 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
652 #define CONFIG_SYS_FSL_TBCLK_DIV 16 652 #define CONFIG_SYS_FSL_TBCLK_DIV 16
653 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 653 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
654 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 654 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
655 #define CONFIG_SYS_FSL_ERRATUM_A_004934 655 #define CONFIG_SYS_FSL_ERRATUM_A_004934
656 #define CONFIG_SYS_FSL_ERRATUM_A005871 656 #define CONFIG_SYS_FSL_ERRATUM_A005871
657 #define CONFIG_SYS_FSL_ERRATUM_A006379 657 #define CONFIG_SYS_FSL_ERRATUM_A006379
658 #define CONFIG_SYS_FSL_ERRATUM_A006593 658 #define CONFIG_SYS_FSL_ERRATUM_A006593
659 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 659 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
660 660
661 #ifdef CONFIG_PPC_B4860 661 #ifdef CONFIG_PPC_B4860
662 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 662 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
663 #define CONFIG_MAX_CPUS 4 663 #define CONFIG_MAX_CPUS 4
664 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 664 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
665 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 665 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
666 #define CONFIG_SYS_NUM_FM1_DTSEC 6 666 #define CONFIG_SYS_NUM_FM1_DTSEC 6
667 #define CONFIG_SYS_NUM_FM1_10GEC 2 667 #define CONFIG_SYS_NUM_FM1_10GEC 2
668 #define CONFIG_NUM_DDR_CONTROLLERS 2 668 #define CONFIG_NUM_DDR_CONTROLLERS 2
669 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 669 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
670 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 670 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
671 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 671 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
672 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 672 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
673 #define CONFIG_SYS_FSL_SRIO_LIODN 673 #define CONFIG_SYS_FSL_SRIO_LIODN
674 #else 674 #else
675 #define CONFIG_MAX_CPUS 2 675 #define CONFIG_MAX_CPUS 2
676 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 676 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
677 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 677 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
678 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 678 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
679 #define CONFIG_SYS_NUM_FM1_DTSEC 4 679 #define CONFIG_SYS_NUM_FM1_DTSEC 4
680 #define CONFIG_SYS_NUM_FM1_10GEC 0 680 #define CONFIG_SYS_NUM_FM1_10GEC 0
681 #define CONFIG_NUM_DDR_CONTROLLERS 1 681 #define CONFIG_NUM_DDR_CONTROLLERS 1
682 #endif 682 #endif
683 683
684 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ 684 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
685 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 685 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
686 #define CONFIG_E5500 686 #define CONFIG_E5500
687 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 687 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
688 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 688 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
689 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 689 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
690 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 690 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
691 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) 691 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
692 #define CONFIG_MAX_CPUS 4 692 #define CONFIG_MAX_CPUS 4
693 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 693 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
694 #define CONFIG_MAX_CPUS 2 694 #define CONFIG_MAX_CPUS 2
695 #endif 695 #endif
696 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 696 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
697 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 697 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
698 #define CONFIG_SYS_SDHC_CLOCK 0 698 #define CONFIG_SYS_SDHC_CLOCK 0
699 #define CONFIG_SYS_FSL_NUM_LAWS 16 699 #define CONFIG_SYS_FSL_NUM_LAWS 16
700 #define CONFIG_SYS_FSL_SRDS_1 700 #define CONFIG_SYS_FSL_SRDS_1
701 #define CONFIG_SYS_FSL_SEC_COMPAT 5 701 #define CONFIG_SYS_FSL_SEC_COMPAT 5
702 #define CONFIG_SYS_NUM_FMAN 1 702 #define CONFIG_SYS_NUM_FMAN 1
703 #define CONFIG_SYS_NUM_FM1_DTSEC 5 703 #define CONFIG_SYS_NUM_FM1_DTSEC 5
704 #define CONFIG_NUM_DDR_CONTROLLERS 1 704 #define CONFIG_NUM_DDR_CONTROLLERS 1
705 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 705 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
706 #define CONFIG_PME_PLAT_CLK_DIV 2 706 #define CONFIG_PME_PLAT_CLK_DIV 2
707 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 707 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
708 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 708 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
709 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 709 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
710 #define CONFIG_SYS_FMAN_V3 710 #define CONFIG_SYS_FMAN_V3
711 #define CONFIG_FM_PLAT_CLK_DIV 1 711 #define CONFIG_FM_PLAT_CLK_DIV 1
712 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 712 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
713 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 713 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
714 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
714 #define CONFIG_SYS_FSL_TBCLK_DIV 16 715 #define CONFIG_SYS_FSL_TBCLK_DIV 16
715 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 716 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
716 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 717 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
717 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 718 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
718 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 719 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
719 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 720 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
720 721
721 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 722 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
722 #define CONFIG_E6500 723 #define CONFIG_E6500
723 #define CONFIG_SYS_PPC64 /* 64-bit core */ 724 #define CONFIG_SYS_PPC64 /* 64-bit core */
724 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 725 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
725 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 726 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
726 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 727 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
727 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 728 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
728 #define CONFIG_SYS_FSL_QMAN_V3 729 #define CONFIG_SYS_FSL_QMAN_V3
729 #define CONFIG_MAX_CPUS 4 730 #define CONFIG_MAX_CPUS 4
730 #define CONFIG_SYS_FSL_NUM_LAWS 32 731 #define CONFIG_SYS_FSL_NUM_LAWS 32
731 #define CONFIG_SYS_FSL_SEC_COMPAT 4 732 #define CONFIG_SYS_FSL_SEC_COMPAT 4
732 #define CONFIG_SYS_NUM_FMAN 1 733 #define CONFIG_SYS_NUM_FMAN 1
733 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 734 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
734 #define CONFIG_SYS_FSL_SRDS_1 735 #define CONFIG_SYS_FSL_SRDS_1
735 #define CONFIG_SYS_FSL_PCI_VER_3_X 736 #define CONFIG_SYS_FSL_PCI_VER_3_X
736 #if defined(CONFIG_PPC_T2080) 737 #if defined(CONFIG_PPC_T2080)
737 #define CONFIG_SYS_NUM_FM1_DTSEC 8 738 #define CONFIG_SYS_NUM_FM1_DTSEC 8
738 #define CONFIG_SYS_NUM_FM1_10GEC 4 739 #define CONFIG_SYS_NUM_FM1_10GEC 4
739 #define CONFIG_SYS_FSL_SRDS_2 740 #define CONFIG_SYS_FSL_SRDS_2
740 #define CONFIG_SYS_FSL_SRIO_LIODN 741 #define CONFIG_SYS_FSL_SRIO_LIODN
741 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 742 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
742 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 743 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
743 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 744 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
744 #elif defined(CONFIG_PPC_T2081) 745 #elif defined(CONFIG_PPC_T2081)
745 #define CONFIG_SYS_NUM_FM1_DTSEC 6 746 #define CONFIG_SYS_NUM_FM1_DTSEC 6
746 #define CONFIG_SYS_NUM_FM1_10GEC 2 747 #define CONFIG_SYS_NUM_FM1_10GEC 2
747 #endif 748 #endif
748 #define CONFIG_SYS_FSL_NUM_USB_CTRLS 2 749 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
749 #define CONFIG_NUM_DDR_CONTROLLERS 1 750 #define CONFIG_NUM_DDR_CONTROLLERS 1
750 #define CONFIG_PME_PLAT_CLK_DIV 1 751 #define CONFIG_PME_PLAT_CLK_DIV 1
751 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 752 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
752 #define CONFIG_SYS_FM1_CLK 0 753 #define CONFIG_SYS_FM1_CLK 0
753 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 754 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
754 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 755 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
755 #define CONFIG_SYS_FMAN_V3 756 #define CONFIG_SYS_FMAN_V3
756 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 757 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
757 #define CONFIG_SYS_FSL_TBCLK_DIV 16 758 #define CONFIG_SYS_FSL_TBCLK_DIV 16
758 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 759 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
759 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 760 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
760 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 761 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
761 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 762 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
762 #define CONFIG_SYS_FSL_SFP_VER_3_0 763 #define CONFIG_SYS_FSL_SFP_VER_3_0
763 #define CONFIG_SYS_FSL_ISBC_VER 2 764 #define CONFIG_SYS_FSL_ISBC_VER 2
764 765
765 #elif defined(CONFIG_PPC_C29X) 766 #elif defined(CONFIG_PPC_C29X)
766 #define CONFIG_MAX_CPUS 1 767 #define CONFIG_MAX_CPUS 1
767 #define CONFIG_FSL_SDHC_V2_3 768 #define CONFIG_FSL_SDHC_V2_3
768 #define CONFIG_SYS_FSL_NUM_LAWS 12 769 #define CONFIG_SYS_FSL_NUM_LAWS 12
769 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 770 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
770 #define CONFIG_TSECV2_1 771 #define CONFIG_TSECV2_1
771 #define CONFIG_SYS_FSL_SEC_COMPAT 6 772 #define CONFIG_SYS_FSL_SEC_COMPAT 6
772 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 773 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
773 #define CONFIG_NUM_DDR_CONTROLLERS 1 774 #define CONFIG_NUM_DDR_CONTROLLERS 1
774 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 775 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
775 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 776 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
776 #define CONFIG_SYS_FSL_ERRATUM_A005125 777 #define CONFIG_SYS_FSL_ERRATUM_A005125
777 778
778 #else 779 #else
779 #error Processor type not defined for this platform 780 #error Processor type not defined for this platform
780 #endif 781 #endif
781 782
782 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 783 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
783 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 784 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
784 #endif 785 #endif
785 786
786 #ifdef CONFIG_E6500 787 #ifdef CONFIG_E6500
787 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 788 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
788 #else 789 #else
789 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 790 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
790 #endif 791 #endif
791 792
792 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ 793 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
793 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ 794 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
794 !defined(CONFIG_SYS_FSL_DDRC_GEN3) 795 !defined(CONFIG_SYS_FSL_DDRC_GEN3)
795 #define CONFIG_SYS_FSL_DDRC_GEN3 796 #define CONFIG_SYS_FSL_DDRC_GEN3
796 #endif 797 #endif
797 798
798 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 799 #endif /* _ASM_MPC85xx_CONFIG_H_ */
799 800
arch/powerpc/include/asm/immap_85xx.h
1 /* 1 /*
2 * MPC85xx Internal Memory Map 2 * MPC85xx Internal Memory Map
3 * 3 *
4 * Copyright 2007-2012 Freescale Semiconductor, Inc. 4 * Copyright 2007-2012 Freescale Semiconductor, Inc.
5 * 5 *
6 * Copyright(c) 2002,2003 Motorola Inc. 6 * Copyright(c) 2002,2003 Motorola Inc.
7 * Xianghua Xiao (x.xiao@motorola.com) 7 * Xianghua Xiao (x.xiao@motorola.com)
8 * 8 *
9 * SPDX-License-Identifier: GPL-2.0+ 9 * SPDX-License-Identifier: GPL-2.0+
10 */ 10 */
11 11
12 #ifndef __IMMAP_85xx__ 12 #ifndef __IMMAP_85xx__
13 #define __IMMAP_85xx__ 13 #define __IMMAP_85xx__
14 14
15 #include <asm/types.h> 15 #include <asm/types.h>
16 #include <asm/fsl_dma.h> 16 #include <asm/fsl_dma.h>
17 #include <asm/fsl_i2c.h> 17 #include <asm/fsl_i2c.h>
18 #include <fsl_ifc.h> 18 #include <fsl_ifc.h>
19 #include <asm/fsl_lbc.h> 19 #include <asm/fsl_lbc.h>
20 #include <asm/fsl_fman.h> 20 #include <asm/fsl_fman.h>
21 #include <fsl_immap.h> 21 #include <fsl_immap.h>
22 22
23 typedef struct ccsr_local { 23 typedef struct ccsr_local {
24 u32 ccsrbarh; /* CCSR Base Addr High */ 24 u32 ccsrbarh; /* CCSR Base Addr High */
25 u32 ccsrbarl; /* CCSR Base Addr Low */ 25 u32 ccsrbarl; /* CCSR Base Addr Low */
26 u32 ccsrar; /* CCSR Attr */ 26 u32 ccsrar; /* CCSR Attr */
27 #define CCSRAR_C 0x80000000 /* Commit */ 27 #define CCSRAR_C 0x80000000 /* Commit */
28 u8 res1[4]; 28 u8 res1[4];
29 u32 altcbarh; /* Alternate Configuration Base Addr High */ 29 u32 altcbarh; /* Alternate Configuration Base Addr High */
30 u32 altcbarl; /* Alternate Configuration Base Addr Low */ 30 u32 altcbarl; /* Alternate Configuration Base Addr Low */
31 u32 altcar; /* Alternate Configuration Attr */ 31 u32 altcar; /* Alternate Configuration Attr */
32 u8 res2[4]; 32 u8 res2[4];
33 u32 bstrh; /* Boot space translation high */ 33 u32 bstrh; /* Boot space translation high */
34 u32 bstrl; /* Boot space translation Low */ 34 u32 bstrl; /* Boot space translation Low */
35 u32 bstrar; /* Boot space translation attributes */ 35 u32 bstrar; /* Boot space translation attributes */
36 u8 res3[0xbd4]; 36 u8 res3[0xbd4];
37 struct { 37 struct {
38 u32 lawbarh; /* LAWn base addr high */ 38 u32 lawbarh; /* LAWn base addr high */
39 u32 lawbarl; /* LAWn base addr low */ 39 u32 lawbarl; /* LAWn base addr low */
40 u32 lawar; /* LAWn attributes */ 40 u32 lawar; /* LAWn attributes */
41 u8 res4[4]; 41 u8 res4[4];
42 } law[32]; 42 } law[32];
43 u8 res35[0x204]; 43 u8 res35[0x204];
44 } ccsr_local_t; 44 } ccsr_local_t;
45 45
46 /* Local-Access Registers & ECM Registers */ 46 /* Local-Access Registers & ECM Registers */
47 typedef struct ccsr_local_ecm { 47 typedef struct ccsr_local_ecm {
48 u32 ccsrbar; /* CCSR Base Addr */ 48 u32 ccsrbar; /* CCSR Base Addr */
49 u8 res1[4]; 49 u8 res1[4];
50 u32 altcbar; /* Alternate Configuration Base Addr */ 50 u32 altcbar; /* Alternate Configuration Base Addr */
51 u8 res2[4]; 51 u8 res2[4];
52 u32 altcar; /* Alternate Configuration Attr */ 52 u32 altcar; /* Alternate Configuration Attr */
53 u8 res3[12]; 53 u8 res3[12];
54 u32 bptr; /* Boot Page Translation */ 54 u32 bptr; /* Boot Page Translation */
55 u8 res4[3044]; 55 u8 res4[3044];
56 u32 lawbar0; /* Local Access Window 0 Base Addr */ 56 u32 lawbar0; /* Local Access Window 0 Base Addr */
57 u8 res5[4]; 57 u8 res5[4];
58 u32 lawar0; /* Local Access Window 0 Attrs */ 58 u32 lawar0; /* Local Access Window 0 Attrs */
59 u8 res6[20]; 59 u8 res6[20];
60 u32 lawbar1; /* Local Access Window 1 Base Addr */ 60 u32 lawbar1; /* Local Access Window 1 Base Addr */
61 u8 res7[4]; 61 u8 res7[4];
62 u32 lawar1; /* Local Access Window 1 Attrs */ 62 u32 lawar1; /* Local Access Window 1 Attrs */
63 u8 res8[20]; 63 u8 res8[20];
64 u32 lawbar2; /* Local Access Window 2 Base Addr */ 64 u32 lawbar2; /* Local Access Window 2 Base Addr */
65 u8 res9[4]; 65 u8 res9[4];
66 u32 lawar2; /* Local Access Window 2 Attrs */ 66 u32 lawar2; /* Local Access Window 2 Attrs */
67 u8 res10[20]; 67 u8 res10[20];
68 u32 lawbar3; /* Local Access Window 3 Base Addr */ 68 u32 lawbar3; /* Local Access Window 3 Base Addr */
69 u8 res11[4]; 69 u8 res11[4];
70 u32 lawar3; /* Local Access Window 3 Attrs */ 70 u32 lawar3; /* Local Access Window 3 Attrs */
71 u8 res12[20]; 71 u8 res12[20];
72 u32 lawbar4; /* Local Access Window 4 Base Addr */ 72 u32 lawbar4; /* Local Access Window 4 Base Addr */
73 u8 res13[4]; 73 u8 res13[4];
74 u32 lawar4; /* Local Access Window 4 Attrs */ 74 u32 lawar4; /* Local Access Window 4 Attrs */
75 u8 res14[20]; 75 u8 res14[20];
76 u32 lawbar5; /* Local Access Window 5 Base Addr */ 76 u32 lawbar5; /* Local Access Window 5 Base Addr */
77 u8 res15[4]; 77 u8 res15[4];
78 u32 lawar5; /* Local Access Window 5 Attrs */ 78 u32 lawar5; /* Local Access Window 5 Attrs */
79 u8 res16[20]; 79 u8 res16[20];
80 u32 lawbar6; /* Local Access Window 6 Base Addr */ 80 u32 lawbar6; /* Local Access Window 6 Base Addr */
81 u8 res17[4]; 81 u8 res17[4];
82 u32 lawar6; /* Local Access Window 6 Attrs */ 82 u32 lawar6; /* Local Access Window 6 Attrs */
83 u8 res18[20]; 83 u8 res18[20];
84 u32 lawbar7; /* Local Access Window 7 Base Addr */ 84 u32 lawbar7; /* Local Access Window 7 Base Addr */
85 u8 res19[4]; 85 u8 res19[4];
86 u32 lawar7; /* Local Access Window 7 Attrs */ 86 u32 lawar7; /* Local Access Window 7 Attrs */
87 u8 res19_8a[20]; 87 u8 res19_8a[20];
88 u32 lawbar8; /* Local Access Window 8 Base Addr */ 88 u32 lawbar8; /* Local Access Window 8 Base Addr */
89 u8 res19_8b[4]; 89 u8 res19_8b[4];
90 u32 lawar8; /* Local Access Window 8 Attrs */ 90 u32 lawar8; /* Local Access Window 8 Attrs */
91 u8 res19_9a[20]; 91 u8 res19_9a[20];
92 u32 lawbar9; /* Local Access Window 9 Base Addr */ 92 u32 lawbar9; /* Local Access Window 9 Base Addr */
93 u8 res19_9b[4]; 93 u8 res19_9b[4];
94 u32 lawar9; /* Local Access Window 9 Attrs */ 94 u32 lawar9; /* Local Access Window 9 Attrs */
95 u8 res19_10a[20]; 95 u8 res19_10a[20];
96 u32 lawbar10; /* Local Access Window 10 Base Addr */ 96 u32 lawbar10; /* Local Access Window 10 Base Addr */
97 u8 res19_10b[4]; 97 u8 res19_10b[4];
98 u32 lawar10; /* Local Access Window 10 Attrs */ 98 u32 lawar10; /* Local Access Window 10 Attrs */
99 u8 res19_11a[20]; 99 u8 res19_11a[20];
100 u32 lawbar11; /* Local Access Window 11 Base Addr */ 100 u32 lawbar11; /* Local Access Window 11 Base Addr */
101 u8 res19_11b[4]; 101 u8 res19_11b[4];
102 u32 lawar11; /* Local Access Window 11 Attrs */ 102 u32 lawar11; /* Local Access Window 11 Attrs */
103 u8 res20[652]; 103 u8 res20[652];
104 u32 eebacr; /* ECM CCB Addr Configuration */ 104 u32 eebacr; /* ECM CCB Addr Configuration */
105 u8 res21[12]; 105 u8 res21[12];
106 u32 eebpcr; /* ECM CCB Port Configuration */ 106 u32 eebpcr; /* ECM CCB Port Configuration */
107 u8 res22[3564]; 107 u8 res22[3564];
108 u32 eedr; /* ECM Error Detect */ 108 u32 eedr; /* ECM Error Detect */
109 u8 res23[4]; 109 u8 res23[4];
110 u32 eeer; /* ECM Error Enable */ 110 u32 eeer; /* ECM Error Enable */
111 u32 eeatr; /* ECM Error Attrs Capture */ 111 u32 eeatr; /* ECM Error Attrs Capture */
112 u32 eeadr; /* ECM Error Addr Capture */ 112 u32 eeadr; /* ECM Error Addr Capture */
113 u8 res24[492]; 113 u8 res24[492];
114 } ccsr_local_ecm_t; 114 } ccsr_local_ecm_t;
115 115
116 #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */ 116 #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
117 #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */ 117 #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
118 118
119 /* I2C Registers */ 119 /* I2C Registers */
120 typedef struct ccsr_i2c { 120 typedef struct ccsr_i2c {
121 struct fsl_i2c i2c[1]; 121 struct fsl_i2c i2c[1];
122 u8 res[4096 - 1 * sizeof(struct fsl_i2c)]; 122 u8 res[4096 - 1 * sizeof(struct fsl_i2c)];
123 } ccsr_i2c_t; 123 } ccsr_i2c_t;
124 124
125 #if defined(CONFIG_MPC8540) \ 125 #if defined(CONFIG_MPC8540) \
126 || defined(CONFIG_MPC8541) \ 126 || defined(CONFIG_MPC8541) \
127 || defined(CONFIG_MPC8548) \ 127 || defined(CONFIG_MPC8548) \
128 || defined(CONFIG_MPC8555) 128 || defined(CONFIG_MPC8555)
129 /* DUART Registers */ 129 /* DUART Registers */
130 typedef struct ccsr_duart { 130 typedef struct ccsr_duart {
131 u8 res1[1280]; 131 u8 res1[1280];
132 /* URBR1, UTHR1, UDLB1 with the same addr */ 132 /* URBR1, UTHR1, UDLB1 with the same addr */
133 u8 urbr1_uthr1_udlb1; 133 u8 urbr1_uthr1_udlb1;
134 /* UIER1, UDMB1 with the same addr01 */ 134 /* UIER1, UDMB1 with the same addr01 */
135 u8 uier1_udmb1; 135 u8 uier1_udmb1;
136 /* UIIR1, UFCR1, UAFR1 with the same addr */ 136 /* UIIR1, UFCR1, UAFR1 with the same addr */
137 u8 uiir1_ufcr1_uafr1; 137 u8 uiir1_ufcr1_uafr1;
138 u8 ulcr1; /* UART1 Line Control */ 138 u8 ulcr1; /* UART1 Line Control */
139 u8 umcr1; /* UART1 Modem Control */ 139 u8 umcr1; /* UART1 Modem Control */
140 u8 ulsr1; /* UART1 Line Status */ 140 u8 ulsr1; /* UART1 Line Status */
141 u8 umsr1; /* UART1 Modem Status */ 141 u8 umsr1; /* UART1 Modem Status */
142 u8 uscr1; /* UART1 Scratch */ 142 u8 uscr1; /* UART1 Scratch */
143 u8 res2[8]; 143 u8 res2[8];
144 u8 udsr1; /* UART1 DMA Status */ 144 u8 udsr1; /* UART1 DMA Status */
145 u8 res3[239]; 145 u8 res3[239];
146 /* URBR2, UTHR2, UDLB2 with the same addr */ 146 /* URBR2, UTHR2, UDLB2 with the same addr */
147 u8 urbr2_uthr2_udlb2; 147 u8 urbr2_uthr2_udlb2;
148 /* UIER2, UDMB2 with the same addr */ 148 /* UIER2, UDMB2 with the same addr */
149 u8 uier2_udmb2; 149 u8 uier2_udmb2;
150 /* UIIR2, UFCR2, UAFR2 with the same addr */ 150 /* UIIR2, UFCR2, UAFR2 with the same addr */
151 u8 uiir2_ufcr2_uafr2; 151 u8 uiir2_ufcr2_uafr2;
152 u8 ulcr2; /* UART2 Line Control */ 152 u8 ulcr2; /* UART2 Line Control */
153 u8 umcr2; /* UART2 Modem Control */ 153 u8 umcr2; /* UART2 Modem Control */
154 u8 ulsr2; /* UART2 Line Status */ 154 u8 ulsr2; /* UART2 Line Status */
155 u8 umsr2; /* UART2 Modem Status */ 155 u8 umsr2; /* UART2 Modem Status */
156 u8 uscr2; /* UART2 Scratch */ 156 u8 uscr2; /* UART2 Scratch */
157 u8 res4[8]; 157 u8 res4[8];
158 u8 udsr2; /* UART2 DMA Status */ 158 u8 udsr2; /* UART2 DMA Status */
159 u8 res5[2543]; 159 u8 res5[2543];
160 } ccsr_duart_t; 160 } ccsr_duart_t;
161 #else /* MPC8560 uses UART on its CPM */ 161 #else /* MPC8560 uses UART on its CPM */
162 typedef struct ccsr_duart { 162 typedef struct ccsr_duart {
163 u8 res[4096]; 163 u8 res[4096];
164 } ccsr_duart_t; 164 } ccsr_duart_t;
165 #endif 165 #endif
166 166
167 /* eSPI Registers */ 167 /* eSPI Registers */
168 typedef struct ccsr_espi { 168 typedef struct ccsr_espi {
169 u32 mode; /* eSPI mode */ 169 u32 mode; /* eSPI mode */
170 u32 event; /* eSPI event */ 170 u32 event; /* eSPI event */
171 u32 mask; /* eSPI mask */ 171 u32 mask; /* eSPI mask */
172 u32 com; /* eSPI command */ 172 u32 com; /* eSPI command */
173 u32 tx; /* eSPI transmit FIFO access */ 173 u32 tx; /* eSPI transmit FIFO access */
174 u32 rx; /* eSPI receive FIFO access */ 174 u32 rx; /* eSPI receive FIFO access */
175 u8 res1[8]; /* reserved */ 175 u8 res1[8]; /* reserved */
176 u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */ 176 u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */
177 u8 res2[4048]; /* fill up to 0x1000 */ 177 u8 res2[4048]; /* fill up to 0x1000 */
178 } ccsr_espi_t; 178 } ccsr_espi_t;
179 179
180 /* PCI Registers */ 180 /* PCI Registers */
181 typedef struct ccsr_pcix { 181 typedef struct ccsr_pcix {
182 u32 cfg_addr; /* PCIX Configuration Addr */ 182 u32 cfg_addr; /* PCIX Configuration Addr */
183 u32 cfg_data; /* PCIX Configuration Data */ 183 u32 cfg_data; /* PCIX Configuration Data */
184 u32 int_ack; /* PCIX IRQ Acknowledge */ 184 u32 int_ack; /* PCIX IRQ Acknowledge */
185 u8 res000c[52]; 185 u8 res000c[52];
186 u32 liodn_base; /* PCIX LIODN base register */ 186 u32 liodn_base; /* PCIX LIODN base register */
187 u8 res0044[2996]; 187 u8 res0044[2996];
188 u32 ipver1; /* PCIX IP block revision register 1 */ 188 u32 ipver1; /* PCIX IP block revision register 1 */
189 u32 ipver2; /* PCIX IP block revision register 2 */ 189 u32 ipver2; /* PCIX IP block revision register 2 */
190 u32 potar0; /* PCIX Outbound Transaction Addr 0 */ 190 u32 potar0; /* PCIX Outbound Transaction Addr 0 */
191 u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */ 191 u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */
192 u32 powbar0; /* PCIX Outbound Window Base Addr 0 */ 192 u32 powbar0; /* PCIX Outbound Window Base Addr 0 */
193 u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */ 193 u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */
194 u32 powar0; /* PCIX Outbound Window Attrs 0 */ 194 u32 powar0; /* PCIX Outbound Window Attrs 0 */
195 u8 res2[12]; 195 u8 res2[12];
196 u32 potar1; /* PCIX Outbound Transaction Addr 1 */ 196 u32 potar1; /* PCIX Outbound Transaction Addr 1 */
197 u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */ 197 u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */
198 u32 powbar1; /* PCIX Outbound Window Base Addr 1 */ 198 u32 powbar1; /* PCIX Outbound Window Base Addr 1 */
199 u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */ 199 u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */
200 u32 powar1; /* PCIX Outbound Window Attrs 1 */ 200 u32 powar1; /* PCIX Outbound Window Attrs 1 */
201 u8 res3[12]; 201 u8 res3[12];
202 u32 potar2; /* PCIX Outbound Transaction Addr 2 */ 202 u32 potar2; /* PCIX Outbound Transaction Addr 2 */
203 u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */ 203 u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */
204 u32 powbar2; /* PCIX Outbound Window Base Addr 2 */ 204 u32 powbar2; /* PCIX Outbound Window Base Addr 2 */
205 u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */ 205 u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */
206 u32 powar2; /* PCIX Outbound Window Attrs 2 */ 206 u32 powar2; /* PCIX Outbound Window Attrs 2 */
207 u8 res4[12]; 207 u8 res4[12];
208 u32 potar3; /* PCIX Outbound Transaction Addr 3 */ 208 u32 potar3; /* PCIX Outbound Transaction Addr 3 */
209 u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */ 209 u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */
210 u32 powbar3; /* PCIX Outbound Window Base Addr 3 */ 210 u32 powbar3; /* PCIX Outbound Window Base Addr 3 */
211 u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */ 211 u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */
212 u32 powar3; /* PCIX Outbound Window Attrs 3 */ 212 u32 powar3; /* PCIX Outbound Window Attrs 3 */
213 u8 res5[12]; 213 u8 res5[12];
214 u32 potar4; /* PCIX Outbound Transaction Addr 4 */ 214 u32 potar4; /* PCIX Outbound Transaction Addr 4 */
215 u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */ 215 u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */
216 u32 powbar4; /* PCIX Outbound Window Base Addr 4 */ 216 u32 powbar4; /* PCIX Outbound Window Base Addr 4 */
217 u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */ 217 u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */
218 u32 powar4; /* PCIX Outbound Window Attrs 4 */ 218 u32 powar4; /* PCIX Outbound Window Attrs 4 */
219 u8 res6[268]; 219 u8 res6[268];
220 u32 pitar3; /* PCIX Inbound Translation Addr 3 */ 220 u32 pitar3; /* PCIX Inbound Translation Addr 3 */
221 u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */ 221 u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */
222 u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */ 222 u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */
223 u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */ 223 u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */
224 u32 piwar3; /* PCIX Inbound Window Attrs 3 */ 224 u32 piwar3; /* PCIX Inbound Window Attrs 3 */
225 u8 res7[12]; 225 u8 res7[12];
226 u32 pitar2; /* PCIX Inbound Translation Addr 2 */ 226 u32 pitar2; /* PCIX Inbound Translation Addr 2 */
227 u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */ 227 u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */
228 u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */ 228 u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */
229 u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */ 229 u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */
230 u32 piwar2; /* PCIX Inbound Window Attrs 2 */ 230 u32 piwar2; /* PCIX Inbound Window Attrs 2 */
231 u8 res8[12]; 231 u8 res8[12];
232 u32 pitar1; /* PCIX Inbound Translation Addr 1 */ 232 u32 pitar1; /* PCIX Inbound Translation Addr 1 */
233 u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */ 233 u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */
234 u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */ 234 u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */
235 u8 res9[4]; 235 u8 res9[4];
236 u32 piwar1; /* PCIX Inbound Window Attrs 1 */ 236 u32 piwar1; /* PCIX Inbound Window Attrs 1 */
237 u8 res10[12]; 237 u8 res10[12];
238 u32 pedr; /* PCIX Error Detect */ 238 u32 pedr; /* PCIX Error Detect */
239 u32 pecdr; /* PCIX Error Capture Disable */ 239 u32 pecdr; /* PCIX Error Capture Disable */
240 u32 peer; /* PCIX Error Enable */ 240 u32 peer; /* PCIX Error Enable */
241 u32 peattrcr; /* PCIX Error Attrs Capture */ 241 u32 peattrcr; /* PCIX Error Attrs Capture */
242 u32 peaddrcr; /* PCIX Error Addr Capture */ 242 u32 peaddrcr; /* PCIX Error Addr Capture */
243 u32 peextaddrcr; /* PCIX Error Extended Addr Capture */ 243 u32 peextaddrcr; /* PCIX Error Extended Addr Capture */
244 u32 pedlcr; /* PCIX Error Data Low Capture */ 244 u32 pedlcr; /* PCIX Error Data Low Capture */
245 u32 pedhcr; /* PCIX Error Error Data High Capture */ 245 u32 pedhcr; /* PCIX Error Error Data High Capture */
246 u32 gas_timr; /* PCIX Gasket Timer */ 246 u32 gas_timr; /* PCIX Gasket Timer */
247 u8 res11[476]; 247 u8 res11[476];
248 } ccsr_pcix_t; 248 } ccsr_pcix_t;
249 249
250 #define PCIX_COMMAND 0x62 250 #define PCIX_COMMAND 0x62
251 #define POWAR_EN 0x80000000 251 #define POWAR_EN 0x80000000
252 #define POWAR_IO_READ 0x00080000 252 #define POWAR_IO_READ 0x00080000
253 #define POWAR_MEM_READ 0x00040000 253 #define POWAR_MEM_READ 0x00040000
254 #define POWAR_IO_WRITE 0x00008000 254 #define POWAR_IO_WRITE 0x00008000
255 #define POWAR_MEM_WRITE 0x00004000 255 #define POWAR_MEM_WRITE 0x00004000
256 #define POWAR_MEM_512M 0x0000001c 256 #define POWAR_MEM_512M 0x0000001c
257 #define POWAR_IO_1M 0x00000013 257 #define POWAR_IO_1M 0x00000013
258 258
259 #define PIWAR_EN 0x80000000 259 #define PIWAR_EN 0x80000000
260 #define PIWAR_PF 0x20000000 260 #define PIWAR_PF 0x20000000
261 #define PIWAR_LOCAL 0x00f00000 261 #define PIWAR_LOCAL 0x00f00000
262 #define PIWAR_READ_SNOOP 0x00050000 262 #define PIWAR_READ_SNOOP 0x00050000
263 #define PIWAR_WRITE_SNOOP 0x00005000 263 #define PIWAR_WRITE_SNOOP 0x00005000
264 #define PIWAR_MEM_2G 0x0000001e 264 #define PIWAR_MEM_2G 0x0000001e
265 265
266 typedef struct ccsr_gpio { 266 typedef struct ccsr_gpio {
267 u32 gpdir; 267 u32 gpdir;
268 u32 gpodr; 268 u32 gpodr;
269 u32 gpdat; 269 u32 gpdat;
270 u32 gpier; 270 u32 gpier;
271 u32 gpimr; 271 u32 gpimr;
272 u32 gpicr; 272 u32 gpicr;
273 } ccsr_gpio_t; 273 } ccsr_gpio_t;
274 274
275 /* L2 Cache Registers */ 275 /* L2 Cache Registers */
276 typedef struct ccsr_l2cache { 276 typedef struct ccsr_l2cache {
277 u32 l2ctl; /* L2 configuration 0 */ 277 u32 l2ctl; /* L2 configuration 0 */
278 u8 res1[12]; 278 u8 res1[12];
279 u32 l2cewar0; /* L2 cache external write addr 0 */ 279 u32 l2cewar0; /* L2 cache external write addr 0 */
280 u8 res2[4]; 280 u8 res2[4];
281 u32 l2cewcr0; /* L2 cache external write control 0 */ 281 u32 l2cewcr0; /* L2 cache external write control 0 */
282 u8 res3[4]; 282 u8 res3[4];
283 u32 l2cewar1; /* L2 cache external write addr 1 */ 283 u32 l2cewar1; /* L2 cache external write addr 1 */
284 u8 res4[4]; 284 u8 res4[4];
285 u32 l2cewcr1; /* L2 cache external write control 1 */ 285 u32 l2cewcr1; /* L2 cache external write control 1 */
286 u8 res5[4]; 286 u8 res5[4];
287 u32 l2cewar2; /* L2 cache external write addr 2 */ 287 u32 l2cewar2; /* L2 cache external write addr 2 */
288 u8 res6[4]; 288 u8 res6[4];
289 u32 l2cewcr2; /* L2 cache external write control 2 */ 289 u32 l2cewcr2; /* L2 cache external write control 2 */
290 u8 res7[4]; 290 u8 res7[4];
291 u32 l2cewar3; /* L2 cache external write addr 3 */ 291 u32 l2cewar3; /* L2 cache external write addr 3 */
292 u8 res8[4]; 292 u8 res8[4];
293 u32 l2cewcr3; /* L2 cache external write control 3 */ 293 u32 l2cewcr3; /* L2 cache external write control 3 */
294 u8 res9[180]; 294 u8 res9[180];
295 u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */ 295 u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */
296 u8 res10[4]; 296 u8 res10[4];
297 u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */ 297 u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */
298 u8 res11[3316]; 298 u8 res11[3316];
299 u32 l2errinjhi; /* L2 error injection mask high */ 299 u32 l2errinjhi; /* L2 error injection mask high */
300 u32 l2errinjlo; /* L2 error injection mask low */ 300 u32 l2errinjlo; /* L2 error injection mask low */
301 u32 l2errinjctl; /* L2 error injection tag/ECC control */ 301 u32 l2errinjctl; /* L2 error injection tag/ECC control */
302 u8 res12[20]; 302 u8 res12[20];
303 u32 l2captdatahi; /* L2 error data high capture */ 303 u32 l2captdatahi; /* L2 error data high capture */
304 u32 l2captdatalo; /* L2 error data low capture */ 304 u32 l2captdatalo; /* L2 error data low capture */
305 u32 l2captecc; /* L2 error ECC capture */ 305 u32 l2captecc; /* L2 error ECC capture */
306 u8 res13[20]; 306 u8 res13[20];
307 u32 l2errdet; /* L2 error detect */ 307 u32 l2errdet; /* L2 error detect */
308 u32 l2errdis; /* L2 error disable */ 308 u32 l2errdis; /* L2 error disable */
309 u32 l2errinten; /* L2 error interrupt enable */ 309 u32 l2errinten; /* L2 error interrupt enable */
310 u32 l2errattr; /* L2 error attributes capture */ 310 u32 l2errattr; /* L2 error attributes capture */
311 u32 l2erraddr; /* L2 error addr capture */ 311 u32 l2erraddr; /* L2 error addr capture */
312 u8 res14[4]; 312 u8 res14[4];
313 u32 l2errctl; /* L2 error control */ 313 u32 l2errctl; /* L2 error control */
314 u8 res15[420]; 314 u8 res15[420];
315 } ccsr_l2cache_t; 315 } ccsr_l2cache_t;
316 316
317 #define MPC85xx_L2CTL_L2E 0x80000000 317 #define MPC85xx_L2CTL_L2E 0x80000000
318 #define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000 318 #define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
319 #define MPC85xx_L2ERRDIS_MBECC 0x00000008 319 #define MPC85xx_L2ERRDIS_MBECC 0x00000008
320 #define MPC85xx_L2ERRDIS_SBECC 0x00000004 320 #define MPC85xx_L2ERRDIS_SBECC 0x00000004
321 321
322 /* DMA Registers */ 322 /* DMA Registers */
323 typedef struct ccsr_dma { 323 typedef struct ccsr_dma {
324 u8 res1[256]; 324 u8 res1[256];
325 struct fsl_dma dma[4]; 325 struct fsl_dma dma[4];
326 u32 dgsr; /* DMA General Status */ 326 u32 dgsr; /* DMA General Status */
327 u8 res2[11516]; 327 u8 res2[11516];
328 } ccsr_dma_t; 328 } ccsr_dma_t;
329 329
330 /* tsec */ 330 /* tsec */
331 typedef struct ccsr_tsec { 331 typedef struct ccsr_tsec {
332 u8 res1[16]; 332 u8 res1[16];
333 u32 ievent; /* IRQ Event */ 333 u32 ievent; /* IRQ Event */
334 u32 imask; /* IRQ Mask */ 334 u32 imask; /* IRQ Mask */
335 u32 edis; /* Error Disabled */ 335 u32 edis; /* Error Disabled */
336 u8 res2[4]; 336 u8 res2[4];
337 u32 ecntrl; /* Ethernet Control */ 337 u32 ecntrl; /* Ethernet Control */
338 u32 minflr; /* Minimum Frame Len */ 338 u32 minflr; /* Minimum Frame Len */
339 u32 ptv; /* Pause Time Value */ 339 u32 ptv; /* Pause Time Value */
340 u32 dmactrl; /* DMA Control */ 340 u32 dmactrl; /* DMA Control */
341 u32 tbipa; /* TBI PHY Addr */ 341 u32 tbipa; /* TBI PHY Addr */
342 u8 res3[88]; 342 u8 res3[88];
343 u32 fifo_tx_thr; /* FIFO transmit threshold */ 343 u32 fifo_tx_thr; /* FIFO transmit threshold */
344 u8 res4[8]; 344 u8 res4[8];
345 u32 fifo_tx_starve; /* FIFO transmit starve */ 345 u32 fifo_tx_starve; /* FIFO transmit starve */
346 u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */ 346 u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */
347 u8 res5[96]; 347 u8 res5[96];
348 u32 tctrl; /* TX Control */ 348 u32 tctrl; /* TX Control */
349 u32 tstat; /* TX Status */ 349 u32 tstat; /* TX Status */
350 u8 res6[4]; 350 u8 res6[4];
351 u32 tbdlen; /* TX Buffer Desc Data Len */ 351 u32 tbdlen; /* TX Buffer Desc Data Len */
352 u8 res7[16]; 352 u8 res7[16];
353 u32 ctbptrh; /* Current TX Buffer Desc Ptr High */ 353 u32 ctbptrh; /* Current TX Buffer Desc Ptr High */
354 u32 ctbptr; /* Current TX Buffer Desc Ptr */ 354 u32 ctbptr; /* Current TX Buffer Desc Ptr */
355 u8 res8[88]; 355 u8 res8[88];
356 u32 tbptrh; /* TX Buffer Desc Ptr High */ 356 u32 tbptrh; /* TX Buffer Desc Ptr High */
357 u32 tbptr; /* TX Buffer Desc Ptr Low */ 357 u32 tbptr; /* TX Buffer Desc Ptr Low */
358 u8 res9[120]; 358 u8 res9[120];
359 u32 tbaseh; /* TX Desc Base Addr High */ 359 u32 tbaseh; /* TX Desc Base Addr High */
360 u32 tbase; /* TX Desc Base Addr */ 360 u32 tbase; /* TX Desc Base Addr */
361 u8 res10[168]; 361 u8 res10[168];
362 u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */ 362 u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */
363 u32 ostbdp; /* OOS TX Data Buffer Ptr */ 363 u32 ostbdp; /* OOS TX Data Buffer Ptr */
364 u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */ 364 u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */
365 u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */ 365 u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */
366 u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */ 366 u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */
367 u32 os32tbdr; /* OOS 32 Bytes TX Reserved */ 367 u32 os32tbdr; /* OOS 32 Bytes TX Reserved */
368 u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */ 368 u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */
369 u8 res11[52]; 369 u8 res11[52];
370 u32 rctrl; /* RX Control */ 370 u32 rctrl; /* RX Control */
371 u32 rstat; /* RX Status */ 371 u32 rstat; /* RX Status */
372 u8 res12[4]; 372 u8 res12[4];
373 u32 rbdlen; /* RxBD Data Len */ 373 u32 rbdlen; /* RxBD Data Len */
374 u8 res13[16]; 374 u8 res13[16];
375 u32 crbptrh; /* Current RX Buffer Desc Ptr High */ 375 u32 crbptrh; /* Current RX Buffer Desc Ptr High */
376 u32 crbptr; /* Current RX Buffer Desc Ptr */ 376 u32 crbptr; /* Current RX Buffer Desc Ptr */
377 u8 res14[24]; 377 u8 res14[24];
378 u32 mrblr; /* Maximum RX Buffer Len */ 378 u32 mrblr; /* Maximum RX Buffer Len */
379 u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */ 379 u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */
380 u8 res15[56]; 380 u8 res15[56];
381 u32 rbptrh; /* RX Buffer Desc Ptr High 0 */ 381 u32 rbptrh; /* RX Buffer Desc Ptr High 0 */
382 u32 rbptr; /* RX Buffer Desc Ptr */ 382 u32 rbptr; /* RX Buffer Desc Ptr */
383 u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */ 383 u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */
384 u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */ 384 u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */
385 u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */ 385 u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */
386 u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */ 386 u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */
387 u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */ 387 u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */
388 u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */ 388 u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */
389 u8 res16[96]; 389 u8 res16[96];
390 u32 rbaseh; /* RX Desc Base Addr High 0 */ 390 u32 rbaseh; /* RX Desc Base Addr High 0 */
391 u32 rbase; /* RX Desc Base Addr */ 391 u32 rbase; /* RX Desc Base Addr */
392 u32 rbaseh1; /* RX Desc Base Addr High 1 */ 392 u32 rbaseh1; /* RX Desc Base Addr High 1 */
393 u32 rbasel1; /* RX Desc Base Addr Low 1 */ 393 u32 rbasel1; /* RX Desc Base Addr Low 1 */
394 u32 rbaseh2; /* RX Desc Base Addr High 2 */ 394 u32 rbaseh2; /* RX Desc Base Addr High 2 */
395 u32 rbasel2; /* RX Desc Base Addr Low 2 */ 395 u32 rbasel2; /* RX Desc Base Addr Low 2 */
396 u32 rbaseh3; /* RX Desc Base Addr High 3 */ 396 u32 rbaseh3; /* RX Desc Base Addr High 3 */
397 u32 rbasel3; /* RX Desc Base Addr Low 3 */ 397 u32 rbasel3; /* RX Desc Base Addr Low 3 */
398 u8 res17[224]; 398 u8 res17[224];
399 u32 maccfg1; /* MAC Configuration 1 */ 399 u32 maccfg1; /* MAC Configuration 1 */
400 u32 maccfg2; /* MAC Configuration 2 */ 400 u32 maccfg2; /* MAC Configuration 2 */
401 u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */ 401 u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
402 u32 hafdup; /* Half Duplex */ 402 u32 hafdup; /* Half Duplex */
403 u32 maxfrm; /* Maximum Frame Len */ 403 u32 maxfrm; /* Maximum Frame Len */
404 u8 res18[12]; 404 u8 res18[12];
405 u32 miimcfg; /* MII Management Configuration */ 405 u32 miimcfg; /* MII Management Configuration */
406 u32 miimcom; /* MII Management Cmd */ 406 u32 miimcom; /* MII Management Cmd */
407 u32 miimadd; /* MII Management Addr */ 407 u32 miimadd; /* MII Management Addr */
408 u32 miimcon; /* MII Management Control */ 408 u32 miimcon; /* MII Management Control */
409 u32 miimstat; /* MII Management Status */ 409 u32 miimstat; /* MII Management Status */
410 u32 miimind; /* MII Management Indicator */ 410 u32 miimind; /* MII Management Indicator */
411 u8 res19[4]; 411 u8 res19[4];
412 u32 ifstat; /* Interface Status */ 412 u32 ifstat; /* Interface Status */
413 u32 macstnaddr1; /* Station Addr Part 1 */ 413 u32 macstnaddr1; /* Station Addr Part 1 */
414 u32 macstnaddr2; /* Station Addr Part 2 */ 414 u32 macstnaddr2; /* Station Addr Part 2 */
415 u8 res20[312]; 415 u8 res20[312];
416 u32 tr64; /* TX & RX 64-byte Frame Counter */ 416 u32 tr64; /* TX & RX 64-byte Frame Counter */
417 u32 tr127; /* TX & RX 65-127 byte Frame Counter */ 417 u32 tr127; /* TX & RX 65-127 byte Frame Counter */
418 u32 tr255; /* TX & RX 128-255 byte Frame Counter */ 418 u32 tr255; /* TX & RX 128-255 byte Frame Counter */
419 u32 tr511; /* TX & RX 256-511 byte Frame Counter */ 419 u32 tr511; /* TX & RX 256-511 byte Frame Counter */
420 u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */ 420 u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */
421 u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */ 421 u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */
422 u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */ 422 u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */
423 u32 rbyt; /* RX Byte Counter */ 423 u32 rbyt; /* RX Byte Counter */
424 u32 rpkt; /* RX Packet Counter */ 424 u32 rpkt; /* RX Packet Counter */
425 u32 rfcs; /* RX FCS Error Counter */ 425 u32 rfcs; /* RX FCS Error Counter */
426 u32 rmca; /* RX Multicast Packet Counter */ 426 u32 rmca; /* RX Multicast Packet Counter */
427 u32 rbca; /* RX Broadcast Packet Counter */ 427 u32 rbca; /* RX Broadcast Packet Counter */
428 u32 rxcf; /* RX Control Frame Packet Counter */ 428 u32 rxcf; /* RX Control Frame Packet Counter */
429 u32 rxpf; /* RX Pause Frame Packet Counter */ 429 u32 rxpf; /* RX Pause Frame Packet Counter */
430 u32 rxuo; /* RX Unknown OP Code Counter */ 430 u32 rxuo; /* RX Unknown OP Code Counter */
431 u32 raln; /* RX Alignment Error Counter */ 431 u32 raln; /* RX Alignment Error Counter */
432 u32 rflr; /* RX Frame Len Error Counter */ 432 u32 rflr; /* RX Frame Len Error Counter */
433 u32 rcde; /* RX Code Error Counter */ 433 u32 rcde; /* RX Code Error Counter */
434 u32 rcse; /* RX Carrier Sense Error Counter */ 434 u32 rcse; /* RX Carrier Sense Error Counter */
435 u32 rund; /* RX Undersize Packet Counter */ 435 u32 rund; /* RX Undersize Packet Counter */
436 u32 rovr; /* RX Oversize Packet Counter */ 436 u32 rovr; /* RX Oversize Packet Counter */
437 u32 rfrg; /* RX Fragments Counter */ 437 u32 rfrg; /* RX Fragments Counter */
438 u32 rjbr; /* RX Jabber Counter */ 438 u32 rjbr; /* RX Jabber Counter */
439 u32 rdrp; /* RX Drop Counter */ 439 u32 rdrp; /* RX Drop Counter */
440 u32 tbyt; /* TX Byte Counter Counter */ 440 u32 tbyt; /* TX Byte Counter Counter */
441 u32 tpkt; /* TX Packet Counter */ 441 u32 tpkt; /* TX Packet Counter */
442 u32 tmca; /* TX Multicast Packet Counter */ 442 u32 tmca; /* TX Multicast Packet Counter */
443 u32 tbca; /* TX Broadcast Packet Counter */ 443 u32 tbca; /* TX Broadcast Packet Counter */
444 u32 txpf; /* TX Pause Control Frame Counter */ 444 u32 txpf; /* TX Pause Control Frame Counter */
445 u32 tdfr; /* TX Deferral Packet Counter */ 445 u32 tdfr; /* TX Deferral Packet Counter */
446 u32 tedf; /* TX Excessive Deferral Packet Counter */ 446 u32 tedf; /* TX Excessive Deferral Packet Counter */
447 u32 tscl; /* TX Single Collision Packet Counter */ 447 u32 tscl; /* TX Single Collision Packet Counter */
448 u32 tmcl; /* TX Multiple Collision Packet Counter */ 448 u32 tmcl; /* TX Multiple Collision Packet Counter */
449 u32 tlcl; /* TX Late Collision Packet Counter */ 449 u32 tlcl; /* TX Late Collision Packet Counter */
450 u32 txcl; /* TX Excessive Collision Packet Counter */ 450 u32 txcl; /* TX Excessive Collision Packet Counter */
451 u32 tncl; /* TX Total Collision Counter */ 451 u32 tncl; /* TX Total Collision Counter */
452 u8 res21[4]; 452 u8 res21[4];
453 u32 tdrp; /* TX Drop Frame Counter */ 453 u32 tdrp; /* TX Drop Frame Counter */
454 u32 tjbr; /* TX Jabber Frame Counter */ 454 u32 tjbr; /* TX Jabber Frame Counter */
455 u32 tfcs; /* TX FCS Error Counter */ 455 u32 tfcs; /* TX FCS Error Counter */
456 u32 txcf; /* TX Control Frame Counter */ 456 u32 txcf; /* TX Control Frame Counter */
457 u32 tovr; /* TX Oversize Frame Counter */ 457 u32 tovr; /* TX Oversize Frame Counter */
458 u32 tund; /* TX Undersize Frame Counter */ 458 u32 tund; /* TX Undersize Frame Counter */
459 u32 tfrg; /* TX Fragments Frame Counter */ 459 u32 tfrg; /* TX Fragments Frame Counter */
460 u32 car1; /* Carry One */ 460 u32 car1; /* Carry One */
461 u32 car2; /* Carry Two */ 461 u32 car2; /* Carry Two */
462 u32 cam1; /* Carry Mask One */ 462 u32 cam1; /* Carry Mask One */
463 u32 cam2; /* Carry Mask Two */ 463 u32 cam2; /* Carry Mask Two */
464 u8 res22[192]; 464 u8 res22[192];
465 u32 iaddr0; /* Indivdual addr 0 */ 465 u32 iaddr0; /* Indivdual addr 0 */
466 u32 iaddr1; /* Indivdual addr 1 */ 466 u32 iaddr1; /* Indivdual addr 1 */
467 u32 iaddr2; /* Indivdual addr 2 */ 467 u32 iaddr2; /* Indivdual addr 2 */
468 u32 iaddr3; /* Indivdual addr 3 */ 468 u32 iaddr3; /* Indivdual addr 3 */
469 u32 iaddr4; /* Indivdual addr 4 */ 469 u32 iaddr4; /* Indivdual addr 4 */
470 u32 iaddr5; /* Indivdual addr 5 */ 470 u32 iaddr5; /* Indivdual addr 5 */
471 u32 iaddr6; /* Indivdual addr 6 */ 471 u32 iaddr6; /* Indivdual addr 6 */
472 u32 iaddr7; /* Indivdual addr 7 */ 472 u32 iaddr7; /* Indivdual addr 7 */
473 u8 res23[96]; 473 u8 res23[96];
474 u32 gaddr0; /* Global addr 0 */ 474 u32 gaddr0; /* Global addr 0 */
475 u32 gaddr1; /* Global addr 1 */ 475 u32 gaddr1; /* Global addr 1 */
476 u32 gaddr2; /* Global addr 2 */ 476 u32 gaddr2; /* Global addr 2 */
477 u32 gaddr3; /* Global addr 3 */ 477 u32 gaddr3; /* Global addr 3 */
478 u32 gaddr4; /* Global addr 4 */ 478 u32 gaddr4; /* Global addr 4 */
479 u32 gaddr5; /* Global addr 5 */ 479 u32 gaddr5; /* Global addr 5 */
480 u32 gaddr6; /* Global addr 6 */ 480 u32 gaddr6; /* Global addr 6 */
481 u32 gaddr7; /* Global addr 7 */ 481 u32 gaddr7; /* Global addr 7 */
482 u8 res24[96]; 482 u8 res24[96];
483 u32 pmd0; /* Pattern Match Data */ 483 u32 pmd0; /* Pattern Match Data */
484 u8 res25[4]; 484 u8 res25[4];
485 u32 pmask0; /* Pattern Mask */ 485 u32 pmask0; /* Pattern Mask */
486 u8 res26[4]; 486 u8 res26[4];
487 u32 pcntrl0; /* Pattern Match Control */ 487 u32 pcntrl0; /* Pattern Match Control */
488 u8 res27[4]; 488 u8 res27[4];
489 u32 pattrb0; /* Pattern Match Attrs */ 489 u32 pattrb0; /* Pattern Match Attrs */
490 u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */ 490 u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */
491 u32 pmd1; /* Pattern Match Data */ 491 u32 pmd1; /* Pattern Match Data */
492 u8 res28[4]; 492 u8 res28[4];
493 u32 pmask1; /* Pattern Mask */ 493 u32 pmask1; /* Pattern Mask */
494 u8 res29[4]; 494 u8 res29[4];
495 u32 pcntrl1; /* Pattern Match Control */ 495 u32 pcntrl1; /* Pattern Match Control */
496 u8 res30[4]; 496 u8 res30[4];
497 u32 pattrb1; /* Pattern Match Attrs */ 497 u32 pattrb1; /* Pattern Match Attrs */
498 u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */ 498 u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */
499 u32 pmd2; /* Pattern Match Data */ 499 u32 pmd2; /* Pattern Match Data */
500 u8 res31[4]; 500 u8 res31[4];
501 u32 pmask2; /* Pattern Mask */ 501 u32 pmask2; /* Pattern Mask */
502 u8 res32[4]; 502 u8 res32[4];
503 u32 pcntrl2; /* Pattern Match Control */ 503 u32 pcntrl2; /* Pattern Match Control */
504 u8 res33[4]; 504 u8 res33[4];
505 u32 pattrb2; /* Pattern Match Attrs */ 505 u32 pattrb2; /* Pattern Match Attrs */
506 u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */ 506 u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */
507 u32 pmd3; /* Pattern Match Data */ 507 u32 pmd3; /* Pattern Match Data */
508 u8 res34[4]; 508 u8 res34[4];
509 u32 pmask3; /* Pattern Mask */ 509 u32 pmask3; /* Pattern Mask */
510 u8 res35[4]; 510 u8 res35[4];
511 u32 pcntrl3; /* Pattern Match Control */ 511 u32 pcntrl3; /* Pattern Match Control */
512 u8 res36[4]; 512 u8 res36[4];
513 u32 pattrb3; /* Pattern Match Attrs */ 513 u32 pattrb3; /* Pattern Match Attrs */
514 u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */ 514 u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */
515 u32 pmd4; /* Pattern Match Data */ 515 u32 pmd4; /* Pattern Match Data */
516 u8 res37[4]; 516 u8 res37[4];
517 u32 pmask4; /* Pattern Mask */ 517 u32 pmask4; /* Pattern Mask */
518 u8 res38[4]; 518 u8 res38[4];
519 u32 pcntrl4; /* Pattern Match Control */ 519 u32 pcntrl4; /* Pattern Match Control */
520 u8 res39[4]; 520 u8 res39[4];
521 u32 pattrb4; /* Pattern Match Attrs */ 521 u32 pattrb4; /* Pattern Match Attrs */
522 u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */ 522 u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */
523 u32 pmd5; /* Pattern Match Data */ 523 u32 pmd5; /* Pattern Match Data */
524 u8 res40[4]; 524 u8 res40[4];
525 u32 pmask5; /* Pattern Mask */ 525 u32 pmask5; /* Pattern Mask */
526 u8 res41[4]; 526 u8 res41[4];
527 u32 pcntrl5; /* Pattern Match Control */ 527 u32 pcntrl5; /* Pattern Match Control */
528 u8 res42[4]; 528 u8 res42[4];
529 u32 pattrb5; /* Pattern Match Attrs */ 529 u32 pattrb5; /* Pattern Match Attrs */
530 u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */ 530 u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */
531 u32 pmd6; /* Pattern Match Data */ 531 u32 pmd6; /* Pattern Match Data */
532 u8 res43[4]; 532 u8 res43[4];
533 u32 pmask6; /* Pattern Mask */ 533 u32 pmask6; /* Pattern Mask */
534 u8 res44[4]; 534 u8 res44[4];
535 u32 pcntrl6; /* Pattern Match Control */ 535 u32 pcntrl6; /* Pattern Match Control */
536 u8 res45[4]; 536 u8 res45[4];
537 u32 pattrb6; /* Pattern Match Attrs */ 537 u32 pattrb6; /* Pattern Match Attrs */
538 u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */ 538 u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */
539 u32 pmd7; /* Pattern Match Data */ 539 u32 pmd7; /* Pattern Match Data */
540 u8 res46[4]; 540 u8 res46[4];
541 u32 pmask7; /* Pattern Mask */ 541 u32 pmask7; /* Pattern Mask */
542 u8 res47[4]; 542 u8 res47[4];
543 u32 pcntrl7; /* Pattern Match Control */ 543 u32 pcntrl7; /* Pattern Match Control */
544 u8 res48[4]; 544 u8 res48[4];
545 u32 pattrb7; /* Pattern Match Attrs */ 545 u32 pattrb7; /* Pattern Match Attrs */
546 u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */ 546 u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */
547 u32 pmd8; /* Pattern Match Data */ 547 u32 pmd8; /* Pattern Match Data */
548 u8 res49[4]; 548 u8 res49[4];
549 u32 pmask8; /* Pattern Mask */ 549 u32 pmask8; /* Pattern Mask */
550 u8 res50[4]; 550 u8 res50[4];
551 u32 pcntrl8; /* Pattern Match Control */ 551 u32 pcntrl8; /* Pattern Match Control */
552 u8 res51[4]; 552 u8 res51[4];
553 u32 pattrb8; /* Pattern Match Attrs */ 553 u32 pattrb8; /* Pattern Match Attrs */
554 u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */ 554 u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */
555 u32 pmd9; /* Pattern Match Data */ 555 u32 pmd9; /* Pattern Match Data */
556 u8 res52[4]; 556 u8 res52[4];
557 u32 pmask9; /* Pattern Mask */ 557 u32 pmask9; /* Pattern Mask */
558 u8 res53[4]; 558 u8 res53[4];
559 u32 pcntrl9; /* Pattern Match Control */ 559 u32 pcntrl9; /* Pattern Match Control */
560 u8 res54[4]; 560 u8 res54[4];
561 u32 pattrb9; /* Pattern Match Attrs */ 561 u32 pattrb9; /* Pattern Match Attrs */
562 u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */ 562 u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */
563 u32 pmd10; /* Pattern Match Data */ 563 u32 pmd10; /* Pattern Match Data */
564 u8 res55[4]; 564 u8 res55[4];
565 u32 pmask10; /* Pattern Mask */ 565 u32 pmask10; /* Pattern Mask */
566 u8 res56[4]; 566 u8 res56[4];
567 u32 pcntrl10; /* Pattern Match Control */ 567 u32 pcntrl10; /* Pattern Match Control */
568 u8 res57[4]; 568 u8 res57[4];
569 u32 pattrb10; /* Pattern Match Attrs */ 569 u32 pattrb10; /* Pattern Match Attrs */
570 u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */ 570 u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */
571 u32 pmd11; /* Pattern Match Data */ 571 u32 pmd11; /* Pattern Match Data */
572 u8 res58[4]; 572 u8 res58[4];
573 u32 pmask11; /* Pattern Mask */ 573 u32 pmask11; /* Pattern Mask */
574 u8 res59[4]; 574 u8 res59[4];
575 u32 pcntrl11; /* Pattern Match Control */ 575 u32 pcntrl11; /* Pattern Match Control */
576 u8 res60[4]; 576 u8 res60[4];
577 u32 pattrb11; /* Pattern Match Attrs */ 577 u32 pattrb11; /* Pattern Match Attrs */
578 u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */ 578 u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */
579 u32 pmd12; /* Pattern Match Data */ 579 u32 pmd12; /* Pattern Match Data */
580 u8 res61[4]; 580 u8 res61[4];
581 u32 pmask12; /* Pattern Mask */ 581 u32 pmask12; /* Pattern Mask */
582 u8 res62[4]; 582 u8 res62[4];
583 u32 pcntrl12; /* Pattern Match Control */ 583 u32 pcntrl12; /* Pattern Match Control */
584 u8 res63[4]; 584 u8 res63[4];
585 u32 pattrb12; /* Pattern Match Attrs */ 585 u32 pattrb12; /* Pattern Match Attrs */
586 u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */ 586 u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */
587 u32 pmd13; /* Pattern Match Data */ 587 u32 pmd13; /* Pattern Match Data */
588 u8 res64[4]; 588 u8 res64[4];
589 u32 pmask13; /* Pattern Mask */ 589 u32 pmask13; /* Pattern Mask */
590 u8 res65[4]; 590 u8 res65[4];
591 u32 pcntrl13; /* Pattern Match Control */ 591 u32 pcntrl13; /* Pattern Match Control */
592 u8 res66[4]; 592 u8 res66[4];
593 u32 pattrb13; /* Pattern Match Attrs */ 593 u32 pattrb13; /* Pattern Match Attrs */
594 u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */ 594 u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */
595 u32 pmd14; /* Pattern Match Data */ 595 u32 pmd14; /* Pattern Match Data */
596 u8 res67[4]; 596 u8 res67[4];
597 u32 pmask14; /* Pattern Mask */ 597 u32 pmask14; /* Pattern Mask */
598 u8 res68[4]; 598 u8 res68[4];
599 u32 pcntrl14; /* Pattern Match Control */ 599 u32 pcntrl14; /* Pattern Match Control */
600 u8 res69[4]; 600 u8 res69[4];
601 u32 pattrb14; /* Pattern Match Attrs */ 601 u32 pattrb14; /* Pattern Match Attrs */
602 u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */ 602 u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */
603 u32 pmd15; /* Pattern Match Data */ 603 u32 pmd15; /* Pattern Match Data */
604 u8 res70[4]; 604 u8 res70[4];
605 u32 pmask15; /* Pattern Mask */ 605 u32 pmask15; /* Pattern Mask */
606 u8 res71[4]; 606 u8 res71[4];
607 u32 pcntrl15; /* Pattern Match Control */ 607 u32 pcntrl15; /* Pattern Match Control */
608 u8 res72[4]; 608 u8 res72[4];
609 u32 pattrb15; /* Pattern Match Attrs */ 609 u32 pattrb15; /* Pattern Match Attrs */
610 u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */ 610 u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */
611 u8 res73[248]; 611 u8 res73[248];
612 u32 attr; /* Attrs */ 612 u32 attr; /* Attrs */
613 u32 attreli; /* Attrs Extract Len & Idx */ 613 u32 attreli; /* Attrs Extract Len & Idx */
614 u8 res74[1024]; 614 u8 res74[1024];
615 } ccsr_tsec_t; 615 } ccsr_tsec_t;
616 616
617 /* PIC Registers */ 617 /* PIC Registers */
618 typedef struct ccsr_pic { 618 typedef struct ccsr_pic {
619 u8 res1[64]; 619 u8 res1[64];
620 u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */ 620 u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */
621 u8 res2[12]; 621 u8 res2[12];
622 u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */ 622 u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */
623 u8 res3[12]; 623 u8 res3[12];
624 u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */ 624 u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */
625 u8 res4[12]; 625 u8 res4[12];
626 u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */ 626 u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */
627 u8 res5[12]; 627 u8 res5[12];
628 u32 ctpr; /* Current Task Priority */ 628 u32 ctpr; /* Current Task Priority */
629 u8 res6[12]; 629 u8 res6[12];
630 u32 whoami; /* Who Am I */ 630 u32 whoami; /* Who Am I */
631 u8 res7[12]; 631 u8 res7[12];
632 u32 iack; /* IRQ Acknowledge */ 632 u32 iack; /* IRQ Acknowledge */
633 u8 res8[12]; 633 u8 res8[12];
634 u32 eoi; /* End Of IRQ */ 634 u32 eoi; /* End Of IRQ */
635 u8 res9[3916]; 635 u8 res9[3916];
636 u32 frr; /* Feature Reporting */ 636 u32 frr; /* Feature Reporting */
637 u8 res10[28]; 637 u8 res10[28];
638 u32 gcr; /* Global Configuration */ 638 u32 gcr; /* Global Configuration */
639 #define MPC85xx_PICGCR_RST 0x80000000 639 #define MPC85xx_PICGCR_RST 0x80000000
640 #define MPC85xx_PICGCR_M 0x20000000 640 #define MPC85xx_PICGCR_M 0x20000000
641 u8 res11[92]; 641 u8 res11[92];
642 u32 vir; /* Vendor Identification */ 642 u32 vir; /* Vendor Identification */
643 u8 res12[12]; 643 u8 res12[12];
644 u32 pir; /* Processor Initialization */ 644 u32 pir; /* Processor Initialization */
645 u8 res13[12]; 645 u8 res13[12];
646 u32 ipivpr0; /* IPI Vector/Priority 0 */ 646 u32 ipivpr0; /* IPI Vector/Priority 0 */
647 u8 res14[12]; 647 u8 res14[12];
648 u32 ipivpr1; /* IPI Vector/Priority 1 */ 648 u32 ipivpr1; /* IPI Vector/Priority 1 */
649 u8 res15[12]; 649 u8 res15[12];
650 u32 ipivpr2; /* IPI Vector/Priority 2 */ 650 u32 ipivpr2; /* IPI Vector/Priority 2 */
651 u8 res16[12]; 651 u8 res16[12];
652 u32 ipivpr3; /* IPI Vector/Priority 3 */ 652 u32 ipivpr3; /* IPI Vector/Priority 3 */
653 u8 res17[12]; 653 u8 res17[12];
654 u32 svr; /* Spurious Vector */ 654 u32 svr; /* Spurious Vector */
655 u8 res18[12]; 655 u8 res18[12];
656 u32 tfrr; /* Timer Frequency Reporting */ 656 u32 tfrr; /* Timer Frequency Reporting */
657 u8 res19[12]; 657 u8 res19[12];
658 u32 gtccr0; /* Global Timer Current Count 0 */ 658 u32 gtccr0; /* Global Timer Current Count 0 */
659 u8 res20[12]; 659 u8 res20[12];
660 u32 gtbcr0; /* Global Timer Base Count 0 */ 660 u32 gtbcr0; /* Global Timer Base Count 0 */
661 u8 res21[12]; 661 u8 res21[12];
662 u32 gtvpr0; /* Global Timer Vector/Priority 0 */ 662 u32 gtvpr0; /* Global Timer Vector/Priority 0 */
663 u8 res22[12]; 663 u8 res22[12];
664 u32 gtdr0; /* Global Timer Destination 0 */ 664 u32 gtdr0; /* Global Timer Destination 0 */
665 u8 res23[12]; 665 u8 res23[12];
666 u32 gtccr1; /* Global Timer Current Count 1 */ 666 u32 gtccr1; /* Global Timer Current Count 1 */
667 u8 res24[12]; 667 u8 res24[12];
668 u32 gtbcr1; /* Global Timer Base Count 1 */ 668 u32 gtbcr1; /* Global Timer Base Count 1 */
669 u8 res25[12]; 669 u8 res25[12];
670 u32 gtvpr1; /* Global Timer Vector/Priority 1 */ 670 u32 gtvpr1; /* Global Timer Vector/Priority 1 */
671 u8 res26[12]; 671 u8 res26[12];
672 u32 gtdr1; /* Global Timer Destination 1 */ 672 u32 gtdr1; /* Global Timer Destination 1 */
673 u8 res27[12]; 673 u8 res27[12];
674 u32 gtccr2; /* Global Timer Current Count 2 */ 674 u32 gtccr2; /* Global Timer Current Count 2 */
675 u8 res28[12]; 675 u8 res28[12];
676 u32 gtbcr2; /* Global Timer Base Count 2 */ 676 u32 gtbcr2; /* Global Timer Base Count 2 */
677 u8 res29[12]; 677 u8 res29[12];
678 u32 gtvpr2; /* Global Timer Vector/Priority 2 */ 678 u32 gtvpr2; /* Global Timer Vector/Priority 2 */
679 u8 res30[12]; 679 u8 res30[12];
680 u32 gtdr2; /* Global Timer Destination 2 */ 680 u32 gtdr2; /* Global Timer Destination 2 */
681 u8 res31[12]; 681 u8 res31[12];
682 u32 gtccr3; /* Global Timer Current Count 3 */ 682 u32 gtccr3; /* Global Timer Current Count 3 */
683 u8 res32[12]; 683 u8 res32[12];
684 u32 gtbcr3; /* Global Timer Base Count 3 */ 684 u32 gtbcr3; /* Global Timer Base Count 3 */
685 u8 res33[12]; 685 u8 res33[12];
686 u32 gtvpr3; /* Global Timer Vector/Priority 3 */ 686 u32 gtvpr3; /* Global Timer Vector/Priority 3 */
687 u8 res34[12]; 687 u8 res34[12];
688 u32 gtdr3; /* Global Timer Destination 3 */ 688 u32 gtdr3; /* Global Timer Destination 3 */
689 u8 res35[268]; 689 u8 res35[268];
690 u32 tcr; /* Timer Control */ 690 u32 tcr; /* Timer Control */
691 u8 res36[12]; 691 u8 res36[12];
692 u32 irqsr0; /* IRQ_OUT Summary 0 */ 692 u32 irqsr0; /* IRQ_OUT Summary 0 */
693 u8 res37[12]; 693 u8 res37[12];
694 u32 irqsr1; /* IRQ_OUT Summary 1 */ 694 u32 irqsr1; /* IRQ_OUT Summary 1 */
695 u8 res38[12]; 695 u8 res38[12];
696 u32 cisr0; /* Critical IRQ Summary 0 */ 696 u32 cisr0; /* Critical IRQ Summary 0 */
697 u8 res39[12]; 697 u8 res39[12];
698 u32 cisr1; /* Critical IRQ Summary 1 */ 698 u32 cisr1; /* Critical IRQ Summary 1 */
699 u8 res40[188]; 699 u8 res40[188];
700 u32 msgr0; /* Message 0 */ 700 u32 msgr0; /* Message 0 */
701 u8 res41[12]; 701 u8 res41[12];
702 u32 msgr1; /* Message 1 */ 702 u32 msgr1; /* Message 1 */
703 u8 res42[12]; 703 u8 res42[12];
704 u32 msgr2; /* Message 2 */ 704 u32 msgr2; /* Message 2 */
705 u8 res43[12]; 705 u8 res43[12];
706 u32 msgr3; /* Message 3 */ 706 u32 msgr3; /* Message 3 */
707 u8 res44[204]; 707 u8 res44[204];
708 u32 mer; /* Message Enable */ 708 u32 mer; /* Message Enable */
709 u8 res45[12]; 709 u8 res45[12];
710 u32 msr; /* Message Status */ 710 u32 msr; /* Message Status */
711 u8 res46[60140]; 711 u8 res46[60140];
712 u32 eivpr0; /* External IRQ Vector/Priority 0 */ 712 u32 eivpr0; /* External IRQ Vector/Priority 0 */
713 u8 res47[12]; 713 u8 res47[12];
714 u32 eidr0; /* External IRQ Destination 0 */ 714 u32 eidr0; /* External IRQ Destination 0 */
715 u8 res48[12]; 715 u8 res48[12];
716 u32 eivpr1; /* External IRQ Vector/Priority 1 */ 716 u32 eivpr1; /* External IRQ Vector/Priority 1 */
717 u8 res49[12]; 717 u8 res49[12];
718 u32 eidr1; /* External IRQ Destination 1 */ 718 u32 eidr1; /* External IRQ Destination 1 */
719 u8 res50[12]; 719 u8 res50[12];
720 u32 eivpr2; /* External IRQ Vector/Priority 2 */ 720 u32 eivpr2; /* External IRQ Vector/Priority 2 */
721 u8 res51[12]; 721 u8 res51[12];
722 u32 eidr2; /* External IRQ Destination 2 */ 722 u32 eidr2; /* External IRQ Destination 2 */
723 u8 res52[12]; 723 u8 res52[12];
724 u32 eivpr3; /* External IRQ Vector/Priority 3 */ 724 u32 eivpr3; /* External IRQ Vector/Priority 3 */
725 u8 res53[12]; 725 u8 res53[12];
726 u32 eidr3; /* External IRQ Destination 3 */ 726 u32 eidr3; /* External IRQ Destination 3 */
727 u8 res54[12]; 727 u8 res54[12];
728 u32 eivpr4; /* External IRQ Vector/Priority 4 */ 728 u32 eivpr4; /* External IRQ Vector/Priority 4 */
729 u8 res55[12]; 729 u8 res55[12];
730 u32 eidr4; /* External IRQ Destination 4 */ 730 u32 eidr4; /* External IRQ Destination 4 */
731 u8 res56[12]; 731 u8 res56[12];
732 u32 eivpr5; /* External IRQ Vector/Priority 5 */ 732 u32 eivpr5; /* External IRQ Vector/Priority 5 */
733 u8 res57[12]; 733 u8 res57[12];
734 u32 eidr5; /* External IRQ Destination 5 */ 734 u32 eidr5; /* External IRQ Destination 5 */
735 u8 res58[12]; 735 u8 res58[12];
736 u32 eivpr6; /* External IRQ Vector/Priority 6 */ 736 u32 eivpr6; /* External IRQ Vector/Priority 6 */
737 u8 res59[12]; 737 u8 res59[12];
738 u32 eidr6; /* External IRQ Destination 6 */ 738 u32 eidr6; /* External IRQ Destination 6 */
739 u8 res60[12]; 739 u8 res60[12];
740 u32 eivpr7; /* External IRQ Vector/Priority 7 */ 740 u32 eivpr7; /* External IRQ Vector/Priority 7 */
741 u8 res61[12]; 741 u8 res61[12];
742 u32 eidr7; /* External IRQ Destination 7 */ 742 u32 eidr7; /* External IRQ Destination 7 */
743 u8 res62[12]; 743 u8 res62[12];
744 u32 eivpr8; /* External IRQ Vector/Priority 8 */ 744 u32 eivpr8; /* External IRQ Vector/Priority 8 */
745 u8 res63[12]; 745 u8 res63[12];
746 u32 eidr8; /* External IRQ Destination 8 */ 746 u32 eidr8; /* External IRQ Destination 8 */
747 u8 res64[12]; 747 u8 res64[12];
748 u32 eivpr9; /* External IRQ Vector/Priority 9 */ 748 u32 eivpr9; /* External IRQ Vector/Priority 9 */
749 u8 res65[12]; 749 u8 res65[12];
750 u32 eidr9; /* External IRQ Destination 9 */ 750 u32 eidr9; /* External IRQ Destination 9 */
751 u8 res66[12]; 751 u8 res66[12];
752 u32 eivpr10; /* External IRQ Vector/Priority 10 */ 752 u32 eivpr10; /* External IRQ Vector/Priority 10 */
753 u8 res67[12]; 753 u8 res67[12];
754 u32 eidr10; /* External IRQ Destination 10 */ 754 u32 eidr10; /* External IRQ Destination 10 */
755 u8 res68[12]; 755 u8 res68[12];
756 u32 eivpr11; /* External IRQ Vector/Priority 11 */ 756 u32 eivpr11; /* External IRQ Vector/Priority 11 */
757 u8 res69[12]; 757 u8 res69[12];
758 u32 eidr11; /* External IRQ Destination 11 */ 758 u32 eidr11; /* External IRQ Destination 11 */
759 u8 res70[140]; 759 u8 res70[140];
760 u32 iivpr0; /* Internal IRQ Vector/Priority 0 */ 760 u32 iivpr0; /* Internal IRQ Vector/Priority 0 */
761 u8 res71[12]; 761 u8 res71[12];
762 u32 iidr0; /* Internal IRQ Destination 0 */ 762 u32 iidr0; /* Internal IRQ Destination 0 */
763 u8 res72[12]; 763 u8 res72[12];
764 u32 iivpr1; /* Internal IRQ Vector/Priority 1 */ 764 u32 iivpr1; /* Internal IRQ Vector/Priority 1 */
765 u8 res73[12]; 765 u8 res73[12];
766 u32 iidr1; /* Internal IRQ Destination 1 */ 766 u32 iidr1; /* Internal IRQ Destination 1 */
767 u8 res74[12]; 767 u8 res74[12];
768 u32 iivpr2; /* Internal IRQ Vector/Priority 2 */ 768 u32 iivpr2; /* Internal IRQ Vector/Priority 2 */
769 u8 res75[12]; 769 u8 res75[12];
770 u32 iidr2; /* Internal IRQ Destination 2 */ 770 u32 iidr2; /* Internal IRQ Destination 2 */
771 u8 res76[12]; 771 u8 res76[12];
772 u32 iivpr3; /* Internal IRQ Vector/Priority 3 */ 772 u32 iivpr3; /* Internal IRQ Vector/Priority 3 */
773 u8 res77[12]; 773 u8 res77[12];
774 u32 iidr3; /* Internal IRQ Destination 3 */ 774 u32 iidr3; /* Internal IRQ Destination 3 */
775 u8 res78[12]; 775 u8 res78[12];
776 u32 iivpr4; /* Internal IRQ Vector/Priority 4 */ 776 u32 iivpr4; /* Internal IRQ Vector/Priority 4 */
777 u8 res79[12]; 777 u8 res79[12];
778 u32 iidr4; /* Internal IRQ Destination 4 */ 778 u32 iidr4; /* Internal IRQ Destination 4 */
779 u8 res80[12]; 779 u8 res80[12];
780 u32 iivpr5; /* Internal IRQ Vector/Priority 5 */ 780 u32 iivpr5; /* Internal IRQ Vector/Priority 5 */
781 u8 res81[12]; 781 u8 res81[12];
782 u32 iidr5; /* Internal IRQ Destination 5 */ 782 u32 iidr5; /* Internal IRQ Destination 5 */
783 u8 res82[12]; 783 u8 res82[12];
784 u32 iivpr6; /* Internal IRQ Vector/Priority 6 */ 784 u32 iivpr6; /* Internal IRQ Vector/Priority 6 */
785 u8 res83[12]; 785 u8 res83[12];
786 u32 iidr6; /* Internal IRQ Destination 6 */ 786 u32 iidr6; /* Internal IRQ Destination 6 */
787 u8 res84[12]; 787 u8 res84[12];
788 u32 iivpr7; /* Internal IRQ Vector/Priority 7 */ 788 u32 iivpr7; /* Internal IRQ Vector/Priority 7 */
789 u8 res85[12]; 789 u8 res85[12];
790 u32 iidr7; /* Internal IRQ Destination 7 */ 790 u32 iidr7; /* Internal IRQ Destination 7 */
791 u8 res86[12]; 791 u8 res86[12];
792 u32 iivpr8; /* Internal IRQ Vector/Priority 8 */ 792 u32 iivpr8; /* Internal IRQ Vector/Priority 8 */
793 u8 res87[12]; 793 u8 res87[12];
794 u32 iidr8; /* Internal IRQ Destination 8 */ 794 u32 iidr8; /* Internal IRQ Destination 8 */
795 u8 res88[12]; 795 u8 res88[12];
796 u32 iivpr9; /* Internal IRQ Vector/Priority 9 */ 796 u32 iivpr9; /* Internal IRQ Vector/Priority 9 */
797 u8 res89[12]; 797 u8 res89[12];
798 u32 iidr9; /* Internal IRQ Destination 9 */ 798 u32 iidr9; /* Internal IRQ Destination 9 */
799 u8 res90[12]; 799 u8 res90[12];
800 u32 iivpr10; /* Internal IRQ Vector/Priority 10 */ 800 u32 iivpr10; /* Internal IRQ Vector/Priority 10 */
801 u8 res91[12]; 801 u8 res91[12];
802 u32 iidr10; /* Internal IRQ Destination 10 */ 802 u32 iidr10; /* Internal IRQ Destination 10 */
803 u8 res92[12]; 803 u8 res92[12];
804 u32 iivpr11; /* Internal IRQ Vector/Priority 11 */ 804 u32 iivpr11; /* Internal IRQ Vector/Priority 11 */
805 u8 res93[12]; 805 u8 res93[12];
806 u32 iidr11; /* Internal IRQ Destination 11 */ 806 u32 iidr11; /* Internal IRQ Destination 11 */
807 u8 res94[12]; 807 u8 res94[12];
808 u32 iivpr12; /* Internal IRQ Vector/Priority 12 */ 808 u32 iivpr12; /* Internal IRQ Vector/Priority 12 */
809 u8 res95[12]; 809 u8 res95[12];
810 u32 iidr12; /* Internal IRQ Destination 12 */ 810 u32 iidr12; /* Internal IRQ Destination 12 */
811 u8 res96[12]; 811 u8 res96[12];
812 u32 iivpr13; /* Internal IRQ Vector/Priority 13 */ 812 u32 iivpr13; /* Internal IRQ Vector/Priority 13 */
813 u8 res97[12]; 813 u8 res97[12];
814 u32 iidr13; /* Internal IRQ Destination 13 */ 814 u32 iidr13; /* Internal IRQ Destination 13 */
815 u8 res98[12]; 815 u8 res98[12];
816 u32 iivpr14; /* Internal IRQ Vector/Priority 14 */ 816 u32 iivpr14; /* Internal IRQ Vector/Priority 14 */
817 u8 res99[12]; 817 u8 res99[12];
818 u32 iidr14; /* Internal IRQ Destination 14 */ 818 u32 iidr14; /* Internal IRQ Destination 14 */
819 u8 res100[12]; 819 u8 res100[12];
820 u32 iivpr15; /* Internal IRQ Vector/Priority 15 */ 820 u32 iivpr15; /* Internal IRQ Vector/Priority 15 */
821 u8 res101[12]; 821 u8 res101[12];
822 u32 iidr15; /* Internal IRQ Destination 15 */ 822 u32 iidr15; /* Internal IRQ Destination 15 */
823 u8 res102[12]; 823 u8 res102[12];
824 u32 iivpr16; /* Internal IRQ Vector/Priority 16 */ 824 u32 iivpr16; /* Internal IRQ Vector/Priority 16 */
825 u8 res103[12]; 825 u8 res103[12];
826 u32 iidr16; /* Internal IRQ Destination 16 */ 826 u32 iidr16; /* Internal IRQ Destination 16 */
827 u8 res104[12]; 827 u8 res104[12];
828 u32 iivpr17; /* Internal IRQ Vector/Priority 17 */ 828 u32 iivpr17; /* Internal IRQ Vector/Priority 17 */
829 u8 res105[12]; 829 u8 res105[12];
830 u32 iidr17; /* Internal IRQ Destination 17 */ 830 u32 iidr17; /* Internal IRQ Destination 17 */
831 u8 res106[12]; 831 u8 res106[12];
832 u32 iivpr18; /* Internal IRQ Vector/Priority 18 */ 832 u32 iivpr18; /* Internal IRQ Vector/Priority 18 */
833 u8 res107[12]; 833 u8 res107[12];
834 u32 iidr18; /* Internal IRQ Destination 18 */ 834 u32 iidr18; /* Internal IRQ Destination 18 */
835 u8 res108[12]; 835 u8 res108[12];
836 u32 iivpr19; /* Internal IRQ Vector/Priority 19 */ 836 u32 iivpr19; /* Internal IRQ Vector/Priority 19 */
837 u8 res109[12]; 837 u8 res109[12];
838 u32 iidr19; /* Internal IRQ Destination 19 */ 838 u32 iidr19; /* Internal IRQ Destination 19 */
839 u8 res110[12]; 839 u8 res110[12];
840 u32 iivpr20; /* Internal IRQ Vector/Priority 20 */ 840 u32 iivpr20; /* Internal IRQ Vector/Priority 20 */
841 u8 res111[12]; 841 u8 res111[12];
842 u32 iidr20; /* Internal IRQ Destination 20 */ 842 u32 iidr20; /* Internal IRQ Destination 20 */
843 u8 res112[12]; 843 u8 res112[12];
844 u32 iivpr21; /* Internal IRQ Vector/Priority 21 */ 844 u32 iivpr21; /* Internal IRQ Vector/Priority 21 */
845 u8 res113[12]; 845 u8 res113[12];
846 u32 iidr21; /* Internal IRQ Destination 21 */ 846 u32 iidr21; /* Internal IRQ Destination 21 */
847 u8 res114[12]; 847 u8 res114[12];
848 u32 iivpr22; /* Internal IRQ Vector/Priority 22 */ 848 u32 iivpr22; /* Internal IRQ Vector/Priority 22 */
849 u8 res115[12]; 849 u8 res115[12];
850 u32 iidr22; /* Internal IRQ Destination 22 */ 850 u32 iidr22; /* Internal IRQ Destination 22 */
851 u8 res116[12]; 851 u8 res116[12];
852 u32 iivpr23; /* Internal IRQ Vector/Priority 23 */ 852 u32 iivpr23; /* Internal IRQ Vector/Priority 23 */
853 u8 res117[12]; 853 u8 res117[12];
854 u32 iidr23; /* Internal IRQ Destination 23 */ 854 u32 iidr23; /* Internal IRQ Destination 23 */
855 u8 res118[12]; 855 u8 res118[12];
856 u32 iivpr24; /* Internal IRQ Vector/Priority 24 */ 856 u32 iivpr24; /* Internal IRQ Vector/Priority 24 */
857 u8 res119[12]; 857 u8 res119[12];
858 u32 iidr24; /* Internal IRQ Destination 24 */ 858 u32 iidr24; /* Internal IRQ Destination 24 */
859 u8 res120[12]; 859 u8 res120[12];
860 u32 iivpr25; /* Internal IRQ Vector/Priority 25 */ 860 u32 iivpr25; /* Internal IRQ Vector/Priority 25 */
861 u8 res121[12]; 861 u8 res121[12];
862 u32 iidr25; /* Internal IRQ Destination 25 */ 862 u32 iidr25; /* Internal IRQ Destination 25 */
863 u8 res122[12]; 863 u8 res122[12];
864 u32 iivpr26; /* Internal IRQ Vector/Priority 26 */ 864 u32 iivpr26; /* Internal IRQ Vector/Priority 26 */
865 u8 res123[12]; 865 u8 res123[12];
866 u32 iidr26; /* Internal IRQ Destination 26 */ 866 u32 iidr26; /* Internal IRQ Destination 26 */
867 u8 res124[12]; 867 u8 res124[12];
868 u32 iivpr27; /* Internal IRQ Vector/Priority 27 */ 868 u32 iivpr27; /* Internal IRQ Vector/Priority 27 */
869 u8 res125[12]; 869 u8 res125[12];
870 u32 iidr27; /* Internal IRQ Destination 27 */ 870 u32 iidr27; /* Internal IRQ Destination 27 */
871 u8 res126[12]; 871 u8 res126[12];
872 u32 iivpr28; /* Internal IRQ Vector/Priority 28 */ 872 u32 iivpr28; /* Internal IRQ Vector/Priority 28 */
873 u8 res127[12]; 873 u8 res127[12];
874 u32 iidr28; /* Internal IRQ Destination 28 */ 874 u32 iidr28; /* Internal IRQ Destination 28 */
875 u8 res128[12]; 875 u8 res128[12];
876 u32 iivpr29; /* Internal IRQ Vector/Priority 29 */ 876 u32 iivpr29; /* Internal IRQ Vector/Priority 29 */
877 u8 res129[12]; 877 u8 res129[12];
878 u32 iidr29; /* Internal IRQ Destination 29 */ 878 u32 iidr29; /* Internal IRQ Destination 29 */
879 u8 res130[12]; 879 u8 res130[12];
880 u32 iivpr30; /* Internal IRQ Vector/Priority 30 */ 880 u32 iivpr30; /* Internal IRQ Vector/Priority 30 */
881 u8 res131[12]; 881 u8 res131[12];
882 u32 iidr30; /* Internal IRQ Destination 30 */ 882 u32 iidr30; /* Internal IRQ Destination 30 */
883 u8 res132[12]; 883 u8 res132[12];
884 u32 iivpr31; /* Internal IRQ Vector/Priority 31 */ 884 u32 iivpr31; /* Internal IRQ Vector/Priority 31 */
885 u8 res133[12]; 885 u8 res133[12];
886 u32 iidr31; /* Internal IRQ Destination 31 */ 886 u32 iidr31; /* Internal IRQ Destination 31 */
887 u8 res134[4108]; 887 u8 res134[4108];
888 u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */ 888 u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */
889 u8 res135[12]; 889 u8 res135[12];
890 u32 midr0; /* Messaging IRQ Destination 0 */ 890 u32 midr0; /* Messaging IRQ Destination 0 */
891 u8 res136[12]; 891 u8 res136[12];
892 u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */ 892 u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */
893 u8 res137[12]; 893 u8 res137[12];
894 u32 midr1; /* Messaging IRQ Destination 1 */ 894 u32 midr1; /* Messaging IRQ Destination 1 */
895 u8 res138[12]; 895 u8 res138[12];
896 u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */ 896 u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */
897 u8 res139[12]; 897 u8 res139[12];
898 u32 midr2; /* Messaging IRQ Destination 2 */ 898 u32 midr2; /* Messaging IRQ Destination 2 */
899 u8 res140[12]; 899 u8 res140[12];
900 u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */ 900 u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */
901 u8 res141[12]; 901 u8 res141[12];
902 u32 midr3; /* Messaging IRQ Destination 3 */ 902 u32 midr3; /* Messaging IRQ Destination 3 */
903 u8 res142[59852]; 903 u8 res142[59852];
904 u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */ 904 u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */
905 u8 res143[12]; 905 u8 res143[12];
906 u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */ 906 u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */
907 u8 res144[12]; 907 u8 res144[12];
908 u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */ 908 u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */
909 u8 res145[12]; 909 u8 res145[12];
910 u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */ 910 u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */
911 u8 res146[12]; 911 u8 res146[12];
912 u32 ctpr0; /* Current Task Priority for Processor 0 */ 912 u32 ctpr0; /* Current Task Priority for Processor 0 */
913 u8 res147[12]; 913 u8 res147[12];
914 u32 whoami0; /* Who Am I for Processor 0 */ 914 u32 whoami0; /* Who Am I for Processor 0 */
915 u8 res148[12]; 915 u8 res148[12];
916 u32 iack0; /* IRQ Acknowledge for Processor 0 */ 916 u32 iack0; /* IRQ Acknowledge for Processor 0 */
917 u8 res149[12]; 917 u8 res149[12];
918 u32 eoi0; /* End Of IRQ for Processor 0 */ 918 u32 eoi0; /* End Of IRQ for Processor 0 */
919 u8 res150[130892]; 919 u8 res150[130892];
920 } ccsr_pic_t; 920 } ccsr_pic_t;
921 921
922 /* CPM Block */ 922 /* CPM Block */
923 #ifndef CONFIG_CPM2 923 #ifndef CONFIG_CPM2
924 typedef struct ccsr_cpm { 924 typedef struct ccsr_cpm {
925 u8 res[262144]; 925 u8 res[262144];
926 } ccsr_cpm_t; 926 } ccsr_cpm_t;
927 #else 927 #else
928 /* 928 /*
929 * DPARM 929 * DPARM
930 * General SIU 930 * General SIU
931 */ 931 */
932 typedef struct ccsr_cpm_siu { 932 typedef struct ccsr_cpm_siu {
933 u8 res1[80]; 933 u8 res1[80];
934 u32 smaer; 934 u32 smaer;
935 u32 smser; 935 u32 smser;
936 u32 smevr; 936 u32 smevr;
937 u8 res2[4]; 937 u8 res2[4];
938 u32 lmaer; 938 u32 lmaer;
939 u32 lmser; 939 u32 lmser;
940 u32 lmevr; 940 u32 lmevr;
941 u8 res3[2964]; 941 u8 res3[2964];
942 } ccsr_cpm_siu_t; 942 } ccsr_cpm_siu_t;
943 943
944 /* IRQ Controller */ 944 /* IRQ Controller */
945 typedef struct ccsr_cpm_intctl { 945 typedef struct ccsr_cpm_intctl {
946 u16 sicr; 946 u16 sicr;
947 u8 res1[2]; 947 u8 res1[2];
948 u32 sivec; 948 u32 sivec;
949 u32 sipnrh; 949 u32 sipnrh;
950 u32 sipnrl; 950 u32 sipnrl;
951 u32 siprr; 951 u32 siprr;
952 u32 scprrh; 952 u32 scprrh;
953 u32 scprrl; 953 u32 scprrl;
954 u32 simrh; 954 u32 simrh;
955 u32 simrl; 955 u32 simrl;
956 u32 siexr; 956 u32 siexr;
957 u8 res2[88]; 957 u8 res2[88];
958 u32 sccr; 958 u32 sccr;
959 u8 res3[124]; 959 u8 res3[124];
960 } ccsr_cpm_intctl_t; 960 } ccsr_cpm_intctl_t;
961 961
962 /* input/output port */ 962 /* input/output port */
963 typedef struct ccsr_cpm_iop { 963 typedef struct ccsr_cpm_iop {
964 u32 pdira; 964 u32 pdira;
965 u32 ppara; 965 u32 ppara;
966 u32 psora; 966 u32 psora;
967 u32 podra; 967 u32 podra;
968 u32 pdata; 968 u32 pdata;
969 u8 res1[12]; 969 u8 res1[12];
970 u32 pdirb; 970 u32 pdirb;
971 u32 pparb; 971 u32 pparb;
972 u32 psorb; 972 u32 psorb;
973 u32 podrb; 973 u32 podrb;
974 u32 pdatb; 974 u32 pdatb;
975 u8 res2[12]; 975 u8 res2[12];
976 u32 pdirc; 976 u32 pdirc;
977 u32 pparc; 977 u32 pparc;
978 u32 psorc; 978 u32 psorc;
979 u32 podrc; 979 u32 podrc;
980 u32 pdatc; 980 u32 pdatc;
981 u8 res3[12]; 981 u8 res3[12];
982 u32 pdird; 982 u32 pdird;
983 u32 ppard; 983 u32 ppard;
984 u32 psord; 984 u32 psord;
985 u32 podrd; 985 u32 podrd;
986 u32 pdatd; 986 u32 pdatd;
987 u8 res4[12]; 987 u8 res4[12];
988 } ccsr_cpm_iop_t; 988 } ccsr_cpm_iop_t;
989 989
990 /* CPM timers */ 990 /* CPM timers */
991 typedef struct ccsr_cpm_timer { 991 typedef struct ccsr_cpm_timer {
992 u8 tgcr1; 992 u8 tgcr1;
993 u8 res1[3]; 993 u8 res1[3];
994 u8 tgcr2; 994 u8 tgcr2;
995 u8 res2[11]; 995 u8 res2[11];
996 u16 tmr1; 996 u16 tmr1;
997 u16 tmr2; 997 u16 tmr2;
998 u16 trr1; 998 u16 trr1;
999 u16 trr2; 999 u16 trr2;
1000 u16 tcr1; 1000 u16 tcr1;
1001 u16 tcr2; 1001 u16 tcr2;
1002 u16 tcn1; 1002 u16 tcn1;
1003 u16 tcn2; 1003 u16 tcn2;
1004 u16 tmr3; 1004 u16 tmr3;
1005 u16 tmr4; 1005 u16 tmr4;
1006 u16 trr3; 1006 u16 trr3;
1007 u16 trr4; 1007 u16 trr4;
1008 u16 tcr3; 1008 u16 tcr3;
1009 u16 tcr4; 1009 u16 tcr4;
1010 u16 tcn3; 1010 u16 tcn3;
1011 u16 tcn4; 1011 u16 tcn4;
1012 u16 ter1; 1012 u16 ter1;
1013 u16 ter2; 1013 u16 ter2;
1014 u16 ter3; 1014 u16 ter3;
1015 u16 ter4; 1015 u16 ter4;
1016 u8 res3[608]; 1016 u8 res3[608];
1017 } ccsr_cpm_timer_t; 1017 } ccsr_cpm_timer_t;
1018 1018
1019 /* SDMA */ 1019 /* SDMA */
1020 typedef struct ccsr_cpm_sdma { 1020 typedef struct ccsr_cpm_sdma {
1021 u8 sdsr; 1021 u8 sdsr;
1022 u8 res1[3]; 1022 u8 res1[3];
1023 u8 sdmr; 1023 u8 sdmr;
1024 u8 res2[739]; 1024 u8 res2[739];
1025 } ccsr_cpm_sdma_t; 1025 } ccsr_cpm_sdma_t;
1026 1026
1027 /* FCC1 */ 1027 /* FCC1 */
1028 typedef struct ccsr_cpm_fcc1 { 1028 typedef struct ccsr_cpm_fcc1 {
1029 u32 gfmr; 1029 u32 gfmr;
1030 u32 fpsmr; 1030 u32 fpsmr;
1031 u16 ftodr; 1031 u16 ftodr;
1032 u8 res1[2]; 1032 u8 res1[2];
1033 u16 fdsr; 1033 u16 fdsr;
1034 u8 res2[2]; 1034 u8 res2[2];
1035 u16 fcce; 1035 u16 fcce;
1036 u8 res3[2]; 1036 u8 res3[2];
1037 u16 fccm; 1037 u16 fccm;
1038 u8 res4[2]; 1038 u8 res4[2];
1039 u8 fccs; 1039 u8 fccs;
1040 u8 res5[3]; 1040 u8 res5[3];
1041 u8 ftirr_phy[4]; 1041 u8 ftirr_phy[4];
1042 } ccsr_cpm_fcc1_t; 1042 } ccsr_cpm_fcc1_t;
1043 1043
1044 /* FCC2 */ 1044 /* FCC2 */
1045 typedef struct ccsr_cpm_fcc2 { 1045 typedef struct ccsr_cpm_fcc2 {
1046 u32 gfmr; 1046 u32 gfmr;
1047 u32 fpsmr; 1047 u32 fpsmr;
1048 u16 ftodr; 1048 u16 ftodr;
1049 u8 res1[2]; 1049 u8 res1[2];
1050 u16 fdsr; 1050 u16 fdsr;
1051 u8 res2[2]; 1051 u8 res2[2];
1052 u16 fcce; 1052 u16 fcce;
1053 u8 res3[2]; 1053 u8 res3[2];
1054 u16 fccm; 1054 u16 fccm;
1055 u8 res4[2]; 1055 u8 res4[2];
1056 u8 fccs; 1056 u8 fccs;
1057 u8 res5[3]; 1057 u8 res5[3];
1058 u8 ftirr_phy[4]; 1058 u8 ftirr_phy[4];
1059 } ccsr_cpm_fcc2_t; 1059 } ccsr_cpm_fcc2_t;
1060 1060
1061 /* FCC3 */ 1061 /* FCC3 */
1062 typedef struct ccsr_cpm_fcc3 { 1062 typedef struct ccsr_cpm_fcc3 {
1063 u32 gfmr; 1063 u32 gfmr;
1064 u32 fpsmr; 1064 u32 fpsmr;
1065 u16 ftodr; 1065 u16 ftodr;
1066 u8 res1[2]; 1066 u8 res1[2];
1067 u16 fdsr; 1067 u16 fdsr;
1068 u8 res2[2]; 1068 u8 res2[2];
1069 u16 fcce; 1069 u16 fcce;
1070 u8 res3[2]; 1070 u8 res3[2];
1071 u16 fccm; 1071 u16 fccm;
1072 u8 res4[2]; 1072 u8 res4[2];
1073 u8 fccs; 1073 u8 fccs;
1074 u8 res5[3]; 1074 u8 res5[3];
1075 u8 res[36]; 1075 u8 res[36];
1076 } ccsr_cpm_fcc3_t; 1076 } ccsr_cpm_fcc3_t;
1077 1077
1078 /* FCC1 extended */ 1078 /* FCC1 extended */
1079 typedef struct ccsr_cpm_fcc1_ext { 1079 typedef struct ccsr_cpm_fcc1_ext {
1080 u32 firper; 1080 u32 firper;
1081 u32 firer; 1081 u32 firer;
1082 u32 firsr_h; 1082 u32 firsr_h;
1083 u32 firsr_l; 1083 u32 firsr_l;
1084 u8 gfemr; 1084 u8 gfemr;
1085 u8 res[15]; 1085 u8 res[15];
1086 1086
1087 } ccsr_cpm_fcc1_ext_t; 1087 } ccsr_cpm_fcc1_ext_t;
1088 1088
1089 /* FCC2 extended */ 1089 /* FCC2 extended */
1090 typedef struct ccsr_cpm_fcc2_ext { 1090 typedef struct ccsr_cpm_fcc2_ext {
1091 u32 firper; 1091 u32 firper;
1092 u32 firer; 1092 u32 firer;
1093 u32 firsr_h; 1093 u32 firsr_h;
1094 u32 firsr_l; 1094 u32 firsr_l;
1095 u8 gfemr; 1095 u8 gfemr;
1096 u8 res[31]; 1096 u8 res[31];
1097 } ccsr_cpm_fcc2_ext_t; 1097 } ccsr_cpm_fcc2_ext_t;
1098 1098
1099 /* FCC3 extended */ 1099 /* FCC3 extended */
1100 typedef struct ccsr_cpm_fcc3_ext { 1100 typedef struct ccsr_cpm_fcc3_ext {
1101 u8 gfemr; 1101 u8 gfemr;
1102 u8 res[47]; 1102 u8 res[47];
1103 } ccsr_cpm_fcc3_ext_t; 1103 } ccsr_cpm_fcc3_ext_t;
1104 1104
1105 /* TC layers */ 1105 /* TC layers */
1106 typedef struct ccsr_cpm_tmp1 { 1106 typedef struct ccsr_cpm_tmp1 {
1107 u8 res[496]; 1107 u8 res[496];
1108 } ccsr_cpm_tmp1_t; 1108 } ccsr_cpm_tmp1_t;
1109 1109
1110 /* BRGs:5,6,7,8 */ 1110 /* BRGs:5,6,7,8 */
1111 typedef struct ccsr_cpm_brg2 { 1111 typedef struct ccsr_cpm_brg2 {
1112 u32 brgc5; 1112 u32 brgc5;
1113 u32 brgc6; 1113 u32 brgc6;
1114 u32 brgc7; 1114 u32 brgc7;
1115 u32 brgc8; 1115 u32 brgc8;
1116 u8 res[608]; 1116 u8 res[608];
1117 } ccsr_cpm_brg2_t; 1117 } ccsr_cpm_brg2_t;
1118 1118
1119 /* I2C */ 1119 /* I2C */
1120 typedef struct ccsr_cpm_i2c { 1120 typedef struct ccsr_cpm_i2c {
1121 u8 i2mod; 1121 u8 i2mod;
1122 u8 res1[3]; 1122 u8 res1[3];
1123 u8 i2add; 1123 u8 i2add;
1124 u8 res2[3]; 1124 u8 res2[3];
1125 u8 i2brg; 1125 u8 i2brg;
1126 u8 res3[3]; 1126 u8 res3[3];
1127 u8 i2com; 1127 u8 i2com;
1128 u8 res4[3]; 1128 u8 res4[3];
1129 u8 i2cer; 1129 u8 i2cer;
1130 u8 res5[3]; 1130 u8 res5[3];
1131 u8 i2cmr; 1131 u8 i2cmr;
1132 u8 res6[331]; 1132 u8 res6[331];
1133 } ccsr_cpm_i2c_t; 1133 } ccsr_cpm_i2c_t;
1134 1134
1135 /* CPM core */ 1135 /* CPM core */
1136 typedef struct ccsr_cpm_cp { 1136 typedef struct ccsr_cpm_cp {
1137 u32 cpcr; 1137 u32 cpcr;
1138 u32 rccr; 1138 u32 rccr;
1139 u8 res1[14]; 1139 u8 res1[14];
1140 u16 rter; 1140 u16 rter;
1141 u8 res2[2]; 1141 u8 res2[2];
1142 u16 rtmr; 1142 u16 rtmr;
1143 u16 rtscr; 1143 u16 rtscr;
1144 u8 res3[2]; 1144 u8 res3[2];
1145 u32 rtsr; 1145 u32 rtsr;
1146 u8 res4[12]; 1146 u8 res4[12];
1147 } ccsr_cpm_cp_t; 1147 } ccsr_cpm_cp_t;
1148 1148
1149 /* BRGs:1,2,3,4 */ 1149 /* BRGs:1,2,3,4 */
1150 typedef struct ccsr_cpm_brg1 { 1150 typedef struct ccsr_cpm_brg1 {
1151 u32 brgc1; 1151 u32 brgc1;
1152 u32 brgc2; 1152 u32 brgc2;
1153 u32 brgc3; 1153 u32 brgc3;
1154 u32 brgc4; 1154 u32 brgc4;
1155 } ccsr_cpm_brg1_t; 1155 } ccsr_cpm_brg1_t;
1156 1156
1157 /* SCC1-SCC4 */ 1157 /* SCC1-SCC4 */
1158 typedef struct ccsr_cpm_scc { 1158 typedef struct ccsr_cpm_scc {
1159 u32 gsmrl; 1159 u32 gsmrl;
1160 u32 gsmrh; 1160 u32 gsmrh;
1161 u16 psmr; 1161 u16 psmr;
1162 u8 res1[2]; 1162 u8 res1[2];
1163 u16 todr; 1163 u16 todr;
1164 u16 dsr; 1164 u16 dsr;
1165 u16 scce; 1165 u16 scce;
1166 u8 res2[2]; 1166 u8 res2[2];
1167 u16 sccm; 1167 u16 sccm;
1168 u8 res3; 1168 u8 res3;
1169 u8 sccs; 1169 u8 sccs;
1170 u8 res4[8]; 1170 u8 res4[8];
1171 } ccsr_cpm_scc_t; 1171 } ccsr_cpm_scc_t;
1172 1172
1173 typedef struct ccsr_cpm_tmp2 { 1173 typedef struct ccsr_cpm_tmp2 {
1174 u8 res[32]; 1174 u8 res[32];
1175 } ccsr_cpm_tmp2_t; 1175 } ccsr_cpm_tmp2_t;
1176 1176
1177 /* SPI */ 1177 /* SPI */
1178 typedef struct ccsr_cpm_spi { 1178 typedef struct ccsr_cpm_spi {
1179 u16 spmode; 1179 u16 spmode;
1180 u8 res1[4]; 1180 u8 res1[4];
1181 u8 spie; 1181 u8 spie;
1182 u8 res2[3]; 1182 u8 res2[3];
1183 u8 spim; 1183 u8 spim;
1184 u8 res3[2]; 1184 u8 res3[2];
1185 u8 spcom; 1185 u8 spcom;
1186 u8 res4[82]; 1186 u8 res4[82];
1187 } ccsr_cpm_spi_t; 1187 } ccsr_cpm_spi_t;
1188 1188
1189 /* CPM MUX */ 1189 /* CPM MUX */
1190 typedef struct ccsr_cpm_mux { 1190 typedef struct ccsr_cpm_mux {
1191 u8 cmxsi1cr; 1191 u8 cmxsi1cr;
1192 u8 res1; 1192 u8 res1;
1193 u8 cmxsi2cr; 1193 u8 cmxsi2cr;
1194 u8 res2; 1194 u8 res2;
1195 u32 cmxfcr; 1195 u32 cmxfcr;
1196 u32 cmxscr; 1196 u32 cmxscr;
1197 u8 res3[2]; 1197 u8 res3[2];
1198 u16 cmxuar; 1198 u16 cmxuar;
1199 u8 res4[16]; 1199 u8 res4[16];
1200 } ccsr_cpm_mux_t; 1200 } ccsr_cpm_mux_t;
1201 1201
1202 /* SI,MCC,etc */ 1202 /* SI,MCC,etc */
1203 typedef struct ccsr_cpm_tmp3 { 1203 typedef struct ccsr_cpm_tmp3 {
1204 u8 res[58592]; 1204 u8 res[58592];
1205 } ccsr_cpm_tmp3_t; 1205 } ccsr_cpm_tmp3_t;
1206 1206
1207 typedef struct ccsr_cpm_iram { 1207 typedef struct ccsr_cpm_iram {
1208 u32 iram[8192]; 1208 u32 iram[8192];
1209 u8 res[98304]; 1209 u8 res[98304];
1210 } ccsr_cpm_iram_t; 1210 } ccsr_cpm_iram_t;
1211 1211
1212 typedef struct ccsr_cpm { 1212 typedef struct ccsr_cpm {
1213 /* Some references are into the unique & known dpram spaces, 1213 /* Some references are into the unique & known dpram spaces,
1214 * others are from the generic base. 1214 * others are from the generic base.
1215 */ 1215 */
1216 #define im_dprambase im_dpram1 1216 #define im_dprambase im_dpram1
1217 u8 im_dpram1[16*1024]; 1217 u8 im_dpram1[16*1024];
1218 u8 res1[16*1024]; 1218 u8 res1[16*1024];
1219 u8 im_dpram2[16*1024]; 1219 u8 im_dpram2[16*1024];
1220 u8 res2[16*1024]; 1220 u8 res2[16*1024];
1221 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ 1221 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
1222 ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */ 1222 ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */
1223 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ 1223 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
1224 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ 1224 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
1225 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ 1225 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
1226 ccsr_cpm_fcc1_t im_cpm_fcc1; 1226 ccsr_cpm_fcc1_t im_cpm_fcc1;
1227 ccsr_cpm_fcc2_t im_cpm_fcc2; 1227 ccsr_cpm_fcc2_t im_cpm_fcc2;
1228 ccsr_cpm_fcc3_t im_cpm_fcc3; 1228 ccsr_cpm_fcc3_t im_cpm_fcc3;
1229 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext; 1229 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
1230 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext; 1230 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
1231 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext; 1231 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
1232 ccsr_cpm_tmp1_t im_cpm_tmp1; 1232 ccsr_cpm_tmp1_t im_cpm_tmp1;
1233 ccsr_cpm_brg2_t im_cpm_brg2; 1233 ccsr_cpm_brg2_t im_cpm_brg2;
1234 ccsr_cpm_i2c_t im_cpm_i2c; 1234 ccsr_cpm_i2c_t im_cpm_i2c;
1235 ccsr_cpm_cp_t im_cpm_cp; 1235 ccsr_cpm_cp_t im_cpm_cp;
1236 ccsr_cpm_brg1_t im_cpm_brg1; 1236 ccsr_cpm_brg1_t im_cpm_brg1;
1237 ccsr_cpm_scc_t im_cpm_scc[4]; 1237 ccsr_cpm_scc_t im_cpm_scc[4];
1238 ccsr_cpm_tmp2_t im_cpm_tmp2; 1238 ccsr_cpm_tmp2_t im_cpm_tmp2;
1239 ccsr_cpm_spi_t im_cpm_spi; 1239 ccsr_cpm_spi_t im_cpm_spi;
1240 ccsr_cpm_mux_t im_cpm_mux; 1240 ccsr_cpm_mux_t im_cpm_mux;
1241 ccsr_cpm_tmp3_t im_cpm_tmp3; 1241 ccsr_cpm_tmp3_t im_cpm_tmp3;
1242 ccsr_cpm_iram_t im_cpm_iram; 1242 ccsr_cpm_iram_t im_cpm_iram;
1243 } ccsr_cpm_t; 1243 } ccsr_cpm_t;
1244 #endif 1244 #endif
1245 1245
1246 #ifdef CONFIG_SYS_SRIO 1246 #ifdef CONFIG_SYS_SRIO
1247 /* Architectural regsiters */ 1247 /* Architectural regsiters */
1248 struct rio_arch { 1248 struct rio_arch {
1249 u32 didcar; /* Device Identity CAR */ 1249 u32 didcar; /* Device Identity CAR */
1250 u32 dicar; /* Device Information CAR */ 1250 u32 dicar; /* Device Information CAR */
1251 u32 aidcar; /* Assembly Identity CAR */ 1251 u32 aidcar; /* Assembly Identity CAR */
1252 u32 aicar; /* Assembly Information CAR */ 1252 u32 aicar; /* Assembly Information CAR */
1253 u32 pefcar; /* Processing Element Features CAR */ 1253 u32 pefcar; /* Processing Element Features CAR */
1254 u8 res0[4]; 1254 u8 res0[4];
1255 u32 socar; /* Source Operations CAR */ 1255 u32 socar; /* Source Operations CAR */
1256 u32 docar; /* Destination Operations CAR */ 1256 u32 docar; /* Destination Operations CAR */
1257 u8 res1[32]; 1257 u8 res1[32];
1258 u32 mcsr; /* Mailbox CSR */ 1258 u32 mcsr; /* Mailbox CSR */
1259 u32 pwdcsr; /* Port-Write and Doorbell CSR */ 1259 u32 pwdcsr; /* Port-Write and Doorbell CSR */
1260 u8 res2[4]; 1260 u8 res2[4];
1261 u32 pellccsr; /* Processing Element Logic Layer CCSR */ 1261 u32 pellccsr; /* Processing Element Logic Layer CCSR */
1262 u8 res3[12]; 1262 u8 res3[12];
1263 u32 lcsbacsr; /* Local Configuration Space BACSR */ 1263 u32 lcsbacsr; /* Local Configuration Space BACSR */
1264 u32 bdidcsr; /* Base Device ID CSR */ 1264 u32 bdidcsr; /* Base Device ID CSR */
1265 u8 res4[4]; 1265 u8 res4[4];
1266 u32 hbdidlcsr; /* Host Base Device ID Lock CSR */ 1266 u32 hbdidlcsr; /* Host Base Device ID Lock CSR */
1267 u32 ctcsr; /* Component Tag CSR */ 1267 u32 ctcsr; /* Component Tag CSR */
1268 }; 1268 };
1269 1269
1270 /* Extended Features Space: 1x/4x LP-Serial Port registers */ 1270 /* Extended Features Space: 1x/4x LP-Serial Port registers */
1271 struct rio_lp_serial_port { 1271 struct rio_lp_serial_port {
1272 u32 plmreqcsr; /* Port Link Maintenance Request CSR */ 1272 u32 plmreqcsr; /* Port Link Maintenance Request CSR */
1273 u32 plmrespcsr; /* Port Link Maintenance Response CS */ 1273 u32 plmrespcsr; /* Port Link Maintenance Response CS */
1274 u32 plascsr; /* Port Local Ackid Status CSR */ 1274 u32 plascsr; /* Port Local Ackid Status CSR */
1275 u8 res0[12]; 1275 u8 res0[12];
1276 u32 pescsr; /* Port Error and Status CSR */ 1276 u32 pescsr; /* Port Error and Status CSR */
1277 u32 pccsr; /* Port Control CSR */ 1277 u32 pccsr; /* Port Control CSR */
1278 }; 1278 };
1279 1279
1280 /* Extended Features Space: 1x/4x LP-Serial registers */ 1280 /* Extended Features Space: 1x/4x LP-Serial registers */
1281 struct rio_lp_serial { 1281 struct rio_lp_serial {
1282 u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */ 1282 u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */
1283 u8 res0[28]; 1283 u8 res0[28];
1284 u32 pltoccsr; /* Port Link Time-out CCSR */ 1284 u32 pltoccsr; /* Port Link Time-out CCSR */
1285 u32 prtoccsr; /* Port Response Time-out CCSR */ 1285 u32 prtoccsr; /* Port Response Time-out CCSR */
1286 u8 res1[20]; 1286 u8 res1[20];
1287 u32 pgccsr; /* Port General CSR */ 1287 u32 pgccsr; /* Port General CSR */
1288 struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 1288 struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1289 }; 1289 };
1290 1290
1291 /* Logical error reporting registers */ 1291 /* Logical error reporting registers */
1292 struct rio_logical_err { 1292 struct rio_logical_err {
1293 u32 erbh; /* Error Reporting Block Header Register */ 1293 u32 erbh; /* Error Reporting Block Header Register */
1294 u8 res0[4]; 1294 u8 res0[4];
1295 u32 ltledcsr; /* Logical/Transport layer error DCSR */ 1295 u32 ltledcsr; /* Logical/Transport layer error DCSR */
1296 u32 ltleecsr; /* Logical/Transport layer error ECSR */ 1296 u32 ltleecsr; /* Logical/Transport layer error ECSR */
1297 u8 res1[4]; 1297 u8 res1[4];
1298 u32 ltlaccsr; /* Logical/Transport layer ACCSR */ 1298 u32 ltlaccsr; /* Logical/Transport layer ACCSR */
1299 u32 ltldidccsr; /* Logical/Transport layer DID CCSR */ 1299 u32 ltldidccsr; /* Logical/Transport layer DID CCSR */
1300 u32 ltlcccsr; /* Logical/Transport layer control CCSR */ 1300 u32 ltlcccsr; /* Logical/Transport layer control CCSR */
1301 }; 1301 };
1302 1302
1303 /* Physical error reporting port registers */ 1303 /* Physical error reporting port registers */
1304 struct rio_phys_err_port { 1304 struct rio_phys_err_port {
1305 u32 edcsr; /* Port error detect CSR */ 1305 u32 edcsr; /* Port error detect CSR */
1306 u32 erecsr; /* Port error rate enable CSR */ 1306 u32 erecsr; /* Port error rate enable CSR */
1307 u32 ecacsr; /* Port error capture attributes CSR */ 1307 u32 ecacsr; /* Port error capture attributes CSR */
1308 u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */ 1308 u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */
1309 u32 peccsr[3]; /* Port error capture CSR */ 1309 u32 peccsr[3]; /* Port error capture CSR */
1310 u8 res0[12]; 1310 u8 res0[12];
1311 u32 ercsr; /* Port error rate CSR */ 1311 u32 ercsr; /* Port error rate CSR */
1312 u32 ertcsr; /* Port error rate threshold CSR */ 1312 u32 ertcsr; /* Port error rate threshold CSR */
1313 u8 res1[16]; 1313 u8 res1[16];
1314 }; 1314 };
1315 1315
1316 /* Physical error reporting registers */ 1316 /* Physical error reporting registers */
1317 struct rio_phys_err { 1317 struct rio_phys_err {
1318 struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 1318 struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1319 }; 1319 };
1320 1320
1321 /* Implementation Space: General Port-Common */ 1321 /* Implementation Space: General Port-Common */
1322 struct rio_impl_common { 1322 struct rio_impl_common {
1323 u8 res0[4]; 1323 u8 res0[4];
1324 u32 llcr; /* Logical Layer Configuration Register */ 1324 u32 llcr; /* Logical Layer Configuration Register */
1325 u8 res1[8]; 1325 u8 res1[8];
1326 u32 epwisr; /* Error / Port-Write Interrupt SR */ 1326 u32 epwisr; /* Error / Port-Write Interrupt SR */
1327 u8 res2[12]; 1327 u8 res2[12];
1328 u32 lretcr; /* Logical Retry Error Threshold CR */ 1328 u32 lretcr; /* Logical Retry Error Threshold CR */
1329 u8 res3[92]; 1329 u8 res3[92];
1330 u32 pretcr; /* Physical Retry Erorr Threshold CR */ 1330 u32 pretcr; /* Physical Retry Erorr Threshold CR */
1331 u8 res4[124]; 1331 u8 res4[124];
1332 }; 1332 };
1333 1333
1334 /* Implementation Space: Port Specific */ 1334 /* Implementation Space: Port Specific */
1335 struct rio_impl_port_spec { 1335 struct rio_impl_port_spec {
1336 u32 adidcsr; /* Port Alt. Device ID CSR */ 1336 u32 adidcsr; /* Port Alt. Device ID CSR */
1337 u8 res0[28]; 1337 u8 res0[28];
1338 u32 ptaacr; /* Port Pass-Through/Accept-All CR */ 1338 u32 ptaacr; /* Port Pass-Through/Accept-All CR */
1339 u32 lopttlcr; 1339 u32 lopttlcr;
1340 u8 res1[8]; 1340 u8 res1[8];
1341 u32 iecsr; /* Port Implementation Error CSR */ 1341 u32 iecsr; /* Port Implementation Error CSR */
1342 u8 res2[12]; 1342 u8 res2[12];
1343 u32 pcr; /* Port Phsyical Configuration Register */ 1343 u32 pcr; /* Port Phsyical Configuration Register */
1344 u8 res3[20]; 1344 u8 res3[20];
1345 u32 slcsr; /* Port Serial Link CSR */ 1345 u32 slcsr; /* Port Serial Link CSR */
1346 u8 res4[4]; 1346 u8 res4[4];
1347 u32 sleicr; /* Port Serial Link Error Injection */ 1347 u32 sleicr; /* Port Serial Link Error Injection */
1348 u32 a0txcr; /* Port Arbitration 0 Tx CR */ 1348 u32 a0txcr; /* Port Arbitration 0 Tx CR */
1349 u32 a1txcr; /* Port Arbitration 1 Tx CR */ 1349 u32 a1txcr; /* Port Arbitration 1 Tx CR */
1350 u32 a2txcr; /* Port Arbitration 2 Tx CR */ 1350 u32 a2txcr; /* Port Arbitration 2 Tx CR */
1351 u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */ 1351 u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */
1352 u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */ 1352 u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */
1353 }; 1353 };
1354 1354
1355 /* Implementation Space: register */ 1355 /* Implementation Space: register */
1356 struct rio_implement { 1356 struct rio_implement {
1357 struct rio_impl_common com; 1357 struct rio_impl_common com;
1358 struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 1358 struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1359 }; 1359 };
1360 1360
1361 /* Revision Control Register */ 1361 /* Revision Control Register */
1362 struct rio_rev_ctrl { 1362 struct rio_rev_ctrl {
1363 u32 ipbrr[2]; /* IP Block Revision Register */ 1363 u32 ipbrr[2]; /* IP Block Revision Register */
1364 }; 1364 };
1365 1365
1366 struct rio_atmu_row { 1366 struct rio_atmu_row {
1367 u32 rowtar; /* RapidIO Outbound Window TAR */ 1367 u32 rowtar; /* RapidIO Outbound Window TAR */
1368 u32 rowtear; /* RapidIO Outbound Window TEAR */ 1368 u32 rowtear; /* RapidIO Outbound Window TEAR */
1369 u32 rowbar; 1369 u32 rowbar;
1370 u8 res0[4]; 1370 u8 res0[4];
1371 u32 rowar; /* RapidIO Outbound Attributes Register */ 1371 u32 rowar; /* RapidIO Outbound Attributes Register */
1372 u32 rowsr[3]; /* Port RapidIO outbound window segment register */ 1372 u32 rowsr[3]; /* Port RapidIO outbound window segment register */
1373 }; 1373 };
1374 1374
1375 struct rio_atmu_riw { 1375 struct rio_atmu_riw {
1376 u32 riwtar; /* RapidIO Inbound Window Translation AR */ 1376 u32 riwtar; /* RapidIO Inbound Window Translation AR */
1377 u8 res0[4]; 1377 u8 res0[4];
1378 u32 riwbar; /* RapidIO Inbound Window Base AR */ 1378 u32 riwbar; /* RapidIO Inbound Window Base AR */
1379 u8 res1[4]; 1379 u8 res1[4];
1380 u32 riwar; /* RapidIO Inbound Attributes Register */ 1380 u32 riwar; /* RapidIO Inbound Attributes Register */
1381 u8 res2[12]; 1381 u8 res2[12];
1382 }; 1382 };
1383 1383
1384 /* ATMU window registers */ 1384 /* ATMU window registers */
1385 struct rio_atmu_win { 1385 struct rio_atmu_win {
1386 struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM]; 1386 struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
1387 u8 res0[64]; 1387 u8 res0[64];
1388 struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM]; 1388 struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
1389 }; 1389 };
1390 1390
1391 struct rio_atmu { 1391 struct rio_atmu {
1392 struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 1392 struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1393 }; 1393 };
1394 1394
1395 #ifdef CONFIG_SYS_FSL_RMU 1395 #ifdef CONFIG_SYS_FSL_RMU
1396 struct rio_msg { 1396 struct rio_msg {
1397 u32 omr; /* Outbound Mode Register */ 1397 u32 omr; /* Outbound Mode Register */
1398 u32 osr; /* Outbound Status Register */ 1398 u32 osr; /* Outbound Status Register */
1399 u32 eodqdpar; /* Extended Outbound DQ DPAR */ 1399 u32 eodqdpar; /* Extended Outbound DQ DPAR */
1400 u32 odqdpar; /* Outbound Descriptor Queue DPAR */ 1400 u32 odqdpar; /* Outbound Descriptor Queue DPAR */
1401 u32 eosar; /* Extended Outbound Unit Source AR */ 1401 u32 eosar; /* Extended Outbound Unit Source AR */
1402 u32 osar; /* Outbound Unit Source AR */ 1402 u32 osar; /* Outbound Unit Source AR */
1403 u32 odpr; /* Outbound Destination Port Register */ 1403 u32 odpr; /* Outbound Destination Port Register */
1404 u32 odatr; /* Outbound Destination Attributes Register */ 1404 u32 odatr; /* Outbound Destination Attributes Register */
1405 u32 odcr; /* Outbound Doubleword Count Register */ 1405 u32 odcr; /* Outbound Doubleword Count Register */
1406 u32 eodqepar; /* Extended Outbound DQ EPAR */ 1406 u32 eodqepar; /* Extended Outbound DQ EPAR */
1407 u32 odqepar; /* Outbound Descriptor Queue EPAR */ 1407 u32 odqepar; /* Outbound Descriptor Queue EPAR */
1408 u32 oretr; /* Outbound Retry Error Threshold Register */ 1408 u32 oretr; /* Outbound Retry Error Threshold Register */
1409 u32 omgr; /* Outbound Multicast Group Register */ 1409 u32 omgr; /* Outbound Multicast Group Register */
1410 u32 omlr; /* Outbound Multicast List Register */ 1410 u32 omlr; /* Outbound Multicast List Register */
1411 u8 res0[40]; 1411 u8 res0[40];
1412 u32 imr; /* Outbound Mode Register */ 1412 u32 imr; /* Outbound Mode Register */
1413 u32 isr; /* Inbound Status Register */ 1413 u32 isr; /* Inbound Status Register */
1414 u32 eidqdpar; /* Extended Inbound Descriptor Queue DPAR */ 1414 u32 eidqdpar; /* Extended Inbound Descriptor Queue DPAR */
1415 u32 idqdpar; /* Inbound Descriptor Queue DPAR */ 1415 u32 idqdpar; /* Inbound Descriptor Queue DPAR */
1416 u32 eifqepar; /* Extended Inbound Frame Queue EPAR */ 1416 u32 eifqepar; /* Extended Inbound Frame Queue EPAR */
1417 u32 ifqepar; /* Inbound Frame Queue EPAR */ 1417 u32 ifqepar; /* Inbound Frame Queue EPAR */
1418 u32 imirir; /* Inbound Maximum Interrutp RIR */ 1418 u32 imirir; /* Inbound Maximum Interrutp RIR */
1419 u8 res1[4]; 1419 u8 res1[4];
1420 u32 eihqepar; /* Extended inbound message header queue EPAR */ 1420 u32 eihqepar; /* Extended inbound message header queue EPAR */
1421 u32 ihqepar; /* Inbound message header queue EPAR */ 1421 u32 ihqepar; /* Inbound message header queue EPAR */
1422 u8 res2[120]; 1422 u8 res2[120];
1423 }; 1423 };
1424 1424
1425 struct rio_dbell { 1425 struct rio_dbell {
1426 u32 odmr; /* Outbound Doorbell Mode Register */ 1426 u32 odmr; /* Outbound Doorbell Mode Register */
1427 u32 odsr; /* Outbound Doorbell Status Register */ 1427 u32 odsr; /* Outbound Doorbell Status Register */
1428 u8 res0[16]; 1428 u8 res0[16];
1429 u32 oddpr; /* Outbound Doorbell Destination Port */ 1429 u32 oddpr; /* Outbound Doorbell Destination Port */
1430 u32 oddatr; /* Outbound Doorbell Destination AR */ 1430 u32 oddatr; /* Outbound Doorbell Destination AR */
1431 u8 res1[12]; 1431 u8 res1[12];
1432 u32 oddretr; /* Outbound Doorbell Retry Threshold CR */ 1432 u32 oddretr; /* Outbound Doorbell Retry Threshold CR */
1433 u8 res2[48]; 1433 u8 res2[48];
1434 u32 idmr; /* Inbound Doorbell Mode Register */ 1434 u32 idmr; /* Inbound Doorbell Mode Register */
1435 u32 idsr; /* Inbound Doorbell Status Register */ 1435 u32 idsr; /* Inbound Doorbell Status Register */
1436 u32 iedqdpar; /* Extended Inbound Doorbell Queue DPAR */ 1436 u32 iedqdpar; /* Extended Inbound Doorbell Queue DPAR */
1437 u32 iqdpar; /* Inbound Doorbell Queue DPAR */ 1437 u32 iqdpar; /* Inbound Doorbell Queue DPAR */
1438 u32 iedqepar; /* Extended Inbound Doorbell Queue EPAR */ 1438 u32 iedqepar; /* Extended Inbound Doorbell Queue EPAR */
1439 u32 idqepar; /* Inbound Doorbell Queue EPAR */ 1439 u32 idqepar; /* Inbound Doorbell Queue EPAR */
1440 u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */ 1440 u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */
1441 }; 1441 };
1442 1442
1443 struct rio_pw { 1443 struct rio_pw {
1444 u32 pwmr; /* Port-Write Mode Register */ 1444 u32 pwmr; /* Port-Write Mode Register */
1445 u32 pwsr; /* Port-Write Status Register */ 1445 u32 pwsr; /* Port-Write Status Register */
1446 u32 epwqbar; /* Extended Port-Write Queue BAR */ 1446 u32 epwqbar; /* Extended Port-Write Queue BAR */
1447 u32 pwqbar; /* Port-Write Queue Base Address Register */ 1447 u32 pwqbar; /* Port-Write Queue Base Address Register */
1448 }; 1448 };
1449 #endif 1449 #endif
1450 1450
1451 #ifdef CONFIG_SYS_FSL_SRIO_LIODN 1451 #ifdef CONFIG_SYS_FSL_SRIO_LIODN
1452 struct rio_liodn { 1452 struct rio_liodn {
1453 u32 plbr; 1453 u32 plbr;
1454 u8 res0[28]; 1454 u8 res0[28];
1455 u32 plaor; 1455 u32 plaor;
1456 u8 res1[12]; 1456 u8 res1[12];
1457 u32 pludr; 1457 u32 pludr;
1458 u32 plldr; 1458 u32 plldr;
1459 u8 res2[456]; 1459 u8 res2[456];
1460 }; 1460 };
1461 #endif 1461 #endif
1462 1462
1463 /* RapidIO Registers */ 1463 /* RapidIO Registers */
1464 struct ccsr_rio { 1464 struct ccsr_rio {
1465 struct rio_arch arch; 1465 struct rio_arch arch;
1466 u8 res0[144]; 1466 u8 res0[144];
1467 struct rio_lp_serial lp_serial; 1467 struct rio_lp_serial lp_serial;
1468 u8 res1[1152]; 1468 u8 res1[1152];
1469 struct rio_logical_err logical_err; 1469 struct rio_logical_err logical_err;
1470 u8 res2[32]; 1470 u8 res2[32];
1471 struct rio_phys_err phys_err; 1471 struct rio_phys_err phys_err;
1472 u8 res3[63808]; 1472 u8 res3[63808];
1473 struct rio_implement impl; 1473 struct rio_implement impl;
1474 u8 res4[2552]; 1474 u8 res4[2552];
1475 struct rio_rev_ctrl rev; 1475 struct rio_rev_ctrl rev;
1476 struct rio_atmu atmu; 1476 struct rio_atmu atmu;
1477 #ifdef CONFIG_SYS_FSL_RMU 1477 #ifdef CONFIG_SYS_FSL_RMU
1478 u8 res5[8192]; 1478 u8 res5[8192];
1479 struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM]; 1479 struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
1480 u8 res6[512]; 1480 u8 res6[512];
1481 struct rio_dbell dbell; 1481 struct rio_dbell dbell;
1482 u8 res7[100]; 1482 u8 res7[100];
1483 struct rio_pw pw; 1483 struct rio_pw pw;
1484 #endif 1484 #endif
1485 #ifdef CONFIG_SYS_FSL_SRIO_LIODN 1485 #ifdef CONFIG_SYS_FSL_SRIO_LIODN
1486 u8 res5[8192]; 1486 u8 res5[8192];
1487 struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 1487 struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1488 #endif 1488 #endif
1489 }; 1489 };
1490 #endif 1490 #endif
1491 1491
1492 /* Quick Engine Block Pin Muxing Registers */ 1492 /* Quick Engine Block Pin Muxing Registers */
1493 typedef struct par_io { 1493 typedef struct par_io {
1494 u32 cpodr; 1494 u32 cpodr;
1495 u32 cpdat; 1495 u32 cpdat;
1496 u32 cpdir1; 1496 u32 cpdir1;
1497 u32 cpdir2; 1497 u32 cpdir2;
1498 u32 cppar1; 1498 u32 cppar1;
1499 u32 cppar2; 1499 u32 cppar2;
1500 u8 res[8]; 1500 u8 res[8];
1501 } par_io_t; 1501 } par_io_t;
1502 1502
1503 #ifdef CONFIG_SYS_FSL_CPC 1503 #ifdef CONFIG_SYS_FSL_CPC
1504 /* 1504 /*
1505 * Define a single offset that is the start of all the CPC register 1505 * Define a single offset that is the start of all the CPC register
1506 * blocks - if there is more than one CPC, we expect these to be 1506 * blocks - if there is more than one CPC, we expect these to be
1507 * contiguous 4k regions 1507 * contiguous 4k regions
1508 */ 1508 */
1509 1509
1510 typedef struct cpc_corenet { 1510 typedef struct cpc_corenet {
1511 u32 cpccsr0; /* Config/status reg */ 1511 u32 cpccsr0; /* Config/status reg */
1512 u32 res1; 1512 u32 res1;
1513 u32 cpccfg0; /* Configuration register */ 1513 u32 cpccfg0; /* Configuration register */
1514 u32 res2; 1514 u32 res2;
1515 u32 cpcewcr0; /* External Write reg 0 */ 1515 u32 cpcewcr0; /* External Write reg 0 */
1516 u32 cpcewabr0; /* External write base reg 0 */ 1516 u32 cpcewabr0; /* External write base reg 0 */
1517 u32 res3[2]; 1517 u32 res3[2];
1518 u32 cpcewcr1; /* External Write reg 1 */ 1518 u32 cpcewcr1; /* External Write reg 1 */
1519 u32 cpcewabr1; /* External write base reg 1 */ 1519 u32 cpcewabr1; /* External write base reg 1 */
1520 u32 res4[54]; 1520 u32 res4[54];
1521 u32 cpcsrcr1; /* SRAM control reg 1 */ 1521 u32 cpcsrcr1; /* SRAM control reg 1 */
1522 u32 cpcsrcr0; /* SRAM control reg 0 */ 1522 u32 cpcsrcr0; /* SRAM control reg 0 */
1523 u32 res5[62]; 1523 u32 res5[62];
1524 struct { 1524 struct {
1525 u32 id; /* partition ID */ 1525 u32 id; /* partition ID */
1526 u32 res; 1526 u32 res;
1527 u32 alloc; /* partition allocation */ 1527 u32 alloc; /* partition allocation */
1528 u32 way; /* partition way */ 1528 u32 way; /* partition way */
1529 } partition_regs[16]; 1529 } partition_regs[16];
1530 u32 res6[704]; 1530 u32 res6[704];
1531 u32 cpcerrinjhi; /* Error injection high */ 1531 u32 cpcerrinjhi; /* Error injection high */
1532 u32 cpcerrinjlo; /* Error injection lo */ 1532 u32 cpcerrinjlo; /* Error injection lo */
1533 u32 cpcerrinjctl; /* Error injection control */ 1533 u32 cpcerrinjctl; /* Error injection control */
1534 u32 res7[5]; 1534 u32 res7[5];
1535 u32 cpccaptdatahi; /* capture data high */ 1535 u32 cpccaptdatahi; /* capture data high */
1536 u32 cpccaptdatalo; /* capture data low */ 1536 u32 cpccaptdatalo; /* capture data low */
1537 u32 cpcaptecc; /* capture ECC */ 1537 u32 cpcaptecc; /* capture ECC */
1538 u32 res8[5]; 1538 u32 res8[5];
1539 u32 cpcerrdet; /* error detect */ 1539 u32 cpcerrdet; /* error detect */
1540 u32 cpcerrdis; /* error disable */ 1540 u32 cpcerrdis; /* error disable */
1541 u32 cpcerrinten; /* errir interrupt enable */ 1541 u32 cpcerrinten; /* errir interrupt enable */
1542 u32 cpcerrattr; /* error attribute */ 1542 u32 cpcerrattr; /* error attribute */
1543 u32 cpcerreaddr; /* error extended address */ 1543 u32 cpcerreaddr; /* error extended address */
1544 u32 cpcerraddr; /* error address */ 1544 u32 cpcerraddr; /* error address */
1545 u32 cpcerrctl; /* error control */ 1545 u32 cpcerrctl; /* error control */
1546 u32 res9[41]; /* pad out to 4k */ 1546 u32 res9[41]; /* pad out to 4k */
1547 u32 cpchdbcr0; /* hardware debug control register 0 */ 1547 u32 cpchdbcr0; /* hardware debug control register 0 */
1548 u32 res10[63]; /* pad out to 4k */ 1548 u32 res10[63]; /* pad out to 4k */
1549 } cpc_corenet_t; 1549 } cpc_corenet_t;
1550 1550
1551 #define CPC_CSR0_CE 0x80000000 /* Cache Enable */ 1551 #define CPC_CSR0_CE 0x80000000 /* Cache Enable */
1552 #define CPC_CSR0_PE 0x40000000 /* Enable ECC */ 1552 #define CPC_CSR0_PE 0x40000000 /* Enable ECC */
1553 #define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */ 1553 #define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */
1554 #define CPC_CSR0_WT 0x00080000 /* Write-through mode */ 1554 #define CPC_CSR0_WT 0x00080000 /* Write-through mode */
1555 #define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */ 1555 #define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */
1556 #define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */ 1556 #define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */
1557 #define CPC_CFG0_SZ_MASK 0x00003fff 1557 #define CPC_CFG0_SZ_MASK 0x00003fff
1558 #define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6) 1558 #define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6)
1559 #define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1) 1559 #define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1)
1560 #define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32) 1560 #define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32)
1561 #define CPC_SRCR1_SRBARU_MASK 0x0000ffff 1561 #define CPC_SRCR1_SRBARU_MASK 0x0000ffff
1562 #define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \ 1562 #define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \
1563 & CPC_SRCR1_SRBARU_MASK) 1563 & CPC_SRCR1_SRBARU_MASK)
1564 #define CPC_SRCR0_SRBARL_MASK 0xffff8000 1564 #define CPC_SRCR0_SRBARL_MASK 0xffff8000
1565 #define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK) 1565 #define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK)
1566 #define CPC_SRCR0_INTLVEN 0x00000100 1566 #define CPC_SRCR0_INTLVEN 0x00000100
1567 #define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000 1567 #define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000
1568 #define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002 1568 #define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002
1569 #define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004 1569 #define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004
1570 #define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006 1570 #define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006
1571 #define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008 1571 #define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
1572 #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a 1572 #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
1573 #define CPC_SRCR0_SRAMEN 0x00000001 1573 #define CPC_SRCR0_SRAMEN 0x00000001
1574 #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ 1574 #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
1575 #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 1575 #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
1576 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000 1576 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
1577 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000 1577 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
1578 #define CPC_HDBCR0_SPLRU_LEVEL_EN 0x003c0000 1578 #define CPC_HDBCR0_SPLRU_LEVEL_EN 0x003c0000
1579 #endif /* CONFIG_SYS_FSL_CPC */ 1579 #endif /* CONFIG_SYS_FSL_CPC */
1580 1580
1581 /* Global Utilities Block */ 1581 /* Global Utilities Block */
1582 #ifdef CONFIG_FSL_CORENET 1582 #ifdef CONFIG_FSL_CORENET
1583 typedef struct ccsr_gur { 1583 typedef struct ccsr_gur {
1584 u32 porsr1; /* POR status 1 */ 1584 u32 porsr1; /* POR status 1 */
1585 u32 porsr2; /* POR status 2 */ 1585 u32 porsr2; /* POR status 2 */
1586 u8 res_008[0x20-0x8]; 1586 u8 res_008[0x20-0x8];
1587 u32 gpporcr1; /* General-purpose POR configuration */ 1587 u32 gpporcr1; /* General-purpose POR configuration */
1588 u32 gpporcr2; /* General-purpose POR configuration 2 */ 1588 u32 gpporcr2; /* General-purpose POR configuration 2 */
1589 u32 dcfg_fusesr; /* Fuse status register */ 1589 u32 dcfg_fusesr; /* Fuse status register */
1590 #define FSL_CORENET_DCFG_FUSESR_VID_SHIFT 25 1590 #define FSL_CORENET_DCFG_FUSESR_VID_SHIFT 25
1591 #define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F 1591 #define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F
1592 #define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT 20 1592 #define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT 20
1593 #define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F 1593 #define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F
1594 u8 res_02c[0x70-0x2c]; 1594 u8 res_02c[0x70-0x2c];
1595 u32 devdisr; /* Device disable control */ 1595 u32 devdisr; /* Device disable control */
1596 u32 devdisr2; /* Device disable control 2 */ 1596 u32 devdisr2; /* Device disable control 2 */
1597 u32 devdisr3; /* Device disable control 3 */ 1597 u32 devdisr3; /* Device disable control 3 */
1598 u32 devdisr4; /* Device disable control 4 */ 1598 u32 devdisr4; /* Device disable control 4 */
1599 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 1599 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1600 u32 devdisr5; /* Device disable control 5 */ 1600 u32 devdisr5; /* Device disable control 5 */
1601 #define FSL_CORENET_DEVDISR_PBL 0x80000000 1601 #define FSL_CORENET_DEVDISR_PBL 0x80000000
1602 #define FSL_CORENET_DEVDISR_PMAN 0x40000000 1602 #define FSL_CORENET_DEVDISR_PMAN 0x40000000
1603 #define FSL_CORENET_DEVDISR_ESDHC 0x20000000 1603 #define FSL_CORENET_DEVDISR_ESDHC 0x20000000
1604 #define FSL_CORENET_DEVDISR_DMA1 0x00800000 1604 #define FSL_CORENET_DEVDISR_DMA1 0x00800000
1605 #define FSL_CORENET_DEVDISR_DMA2 0x00400000 1605 #define FSL_CORENET_DEVDISR_DMA2 0x00400000
1606 #define FSL_CORENET_DEVDISR_USB1 0x00080000 1606 #define FSL_CORENET_DEVDISR_USB1 0x00080000
1607 #define FSL_CORENET_DEVDISR_USB2 0x00040000 1607 #define FSL_CORENET_DEVDISR_USB2 0x00040000
1608 #define FSL_CORENET_DEVDISR_SATA1 0x00008000 1608 #define FSL_CORENET_DEVDISR_SATA1 0x00008000
1609 #define FSL_CORENET_DEVDISR_SATA2 0x00004000 1609 #define FSL_CORENET_DEVDISR_SATA2 0x00004000
1610 #define FSL_CORENET_DEVDISR_PME 0x00000800 1610 #define FSL_CORENET_DEVDISR_PME 0x00000800
1611 #define FSL_CORENET_DEVDISR_SEC 0x00000200 1611 #define FSL_CORENET_DEVDISR_SEC 0x00000200
1612 #define FSL_CORENET_DEVDISR_RMU 0x00000080 1612 #define FSL_CORENET_DEVDISR_RMU 0x00000080
1613 #define FSL_CORENET_DEVDISR_DCE 0x00000040 1613 #define FSL_CORENET_DEVDISR_DCE 0x00000040
1614 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000 1614 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000
1615 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000 1615 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000
1616 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000 1616 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000
1617 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000 1617 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000
1618 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000 1618 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000
1619 #define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000 1619 #define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000
1620 #define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000 1620 #define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000
1621 #define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000 1621 #define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
1622 #define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000 1622 #define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000
1623 #define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000 1623 #define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000
1624 #define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000 1624 #define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000
1625 #define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000 1625 #define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000
1626 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000 1626 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000
1627 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000 1627 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000
1628 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000 1628 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000
1629 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000 1629 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000
1630 #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000 1630 #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000
1631 #define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000 1631 #define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000
1632 #define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800 1632 #define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800
1633 #define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400 1633 #define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400
1634 #define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800 1634 #define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800
1635 #define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400 1635 #define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400
1636 #define FSL_CORENET_DEVDISR2_FM1 0x00000080 1636 #define FSL_CORENET_DEVDISR2_FM1 0x00000080
1637 #define FSL_CORENET_DEVDISR2_FM2 0x00000040 1637 #define FSL_CORENET_DEVDISR2_FM2 0x00000040
1638 #define FSL_CORENET_DEVDISR2_CPRI 0x00000008 1638 #define FSL_CORENET_DEVDISR2_CPRI 0x00000008
1639 #define FSL_CORENET_DEVDISR3_PCIE1 0x80000000 1639 #define FSL_CORENET_DEVDISR3_PCIE1 0x80000000
1640 #define FSL_CORENET_DEVDISR3_PCIE2 0x40000000 1640 #define FSL_CORENET_DEVDISR3_PCIE2 0x40000000
1641 #define FSL_CORENET_DEVDISR3_PCIE3 0x20000000 1641 #define FSL_CORENET_DEVDISR3_PCIE3 0x20000000
1642 #define FSL_CORENET_DEVDISR3_PCIE4 0x10000000 1642 #define FSL_CORENET_DEVDISR3_PCIE4 0x10000000
1643 #define FSL_CORENET_DEVDISR3_SRIO1 0x08000000 1643 #define FSL_CORENET_DEVDISR3_SRIO1 0x08000000
1644 #define FSL_CORENET_DEVDISR3_SRIO2 0x04000000 1644 #define FSL_CORENET_DEVDISR3_SRIO2 0x04000000
1645 #define FSL_CORENET_DEVDISR3_QMAN 0x00080000 1645 #define FSL_CORENET_DEVDISR3_QMAN 0x00080000
1646 #define FSL_CORENET_DEVDISR3_BMAN 0x00040000 1646 #define FSL_CORENET_DEVDISR3_BMAN 0x00040000
1647 #define FSL_CORENET_DEVDISR3_LA1 0x00008000 1647 #define FSL_CORENET_DEVDISR3_LA1 0x00008000
1648 #define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800 1648 #define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800
1649 #define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400 1649 #define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400
1650 #define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200 1650 #define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200
1651 #define FSL_CORENET_DEVDISR4_I2C1 0x80000000 1651 #define FSL_CORENET_DEVDISR4_I2C1 0x80000000
1652 #define FSL_CORENET_DEVDISR4_I2C2 0x40000000 1652 #define FSL_CORENET_DEVDISR4_I2C2 0x40000000
1653 #define FSL_CORENET_DEVDISR4_DUART1 0x20000000 1653 #define FSL_CORENET_DEVDISR4_DUART1 0x20000000
1654 #define FSL_CORENET_DEVDISR4_DUART2 0x10000000 1654 #define FSL_CORENET_DEVDISR4_DUART2 0x10000000
1655 #define FSL_CORENET_DEVDISR4_ESPI 0x08000000 1655 #define FSL_CORENET_DEVDISR4_ESPI 0x08000000
1656 #define FSL_CORENET_DEVDISR5_DDR1 0x80000000 1656 #define FSL_CORENET_DEVDISR5_DDR1 0x80000000
1657 #define FSL_CORENET_DEVDISR5_DDR2 0x40000000 1657 #define FSL_CORENET_DEVDISR5_DDR2 0x40000000
1658 #define FSL_CORENET_DEVDISR5_DDR3 0x20000000 1658 #define FSL_CORENET_DEVDISR5_DDR3 0x20000000
1659 #define FSL_CORENET_DEVDISR5_CPC1 0x08000000 1659 #define FSL_CORENET_DEVDISR5_CPC1 0x08000000
1660 #define FSL_CORENET_DEVDISR5_CPC2 0x04000000 1660 #define FSL_CORENET_DEVDISR5_CPC2 0x04000000
1661 #define FSL_CORENET_DEVDISR5_CPC3 0x02000000 1661 #define FSL_CORENET_DEVDISR5_CPC3 0x02000000
1662 #define FSL_CORENET_DEVDISR5_IFC 0x00800000 1662 #define FSL_CORENET_DEVDISR5_IFC 0x00800000
1663 #define FSL_CORENET_DEVDISR5_GPIO 0x00400000 1663 #define FSL_CORENET_DEVDISR5_GPIO 0x00400000
1664 #define FSL_CORENET_DEVDISR5_DBG 0x00200000 1664 #define FSL_CORENET_DEVDISR5_DBG 0x00200000
1665 #define FSL_CORENET_DEVDISR5_NAL 0x00100000 1665 #define FSL_CORENET_DEVDISR5_NAL 0x00100000
1666 #define FSL_CORENET_DEVDISR5_TIMERS 0x00020000 1666 #define FSL_CORENET_DEVDISR5_TIMERS 0x00020000
1667 #define FSL_CORENET_NUM_DEVDISR 5 1667 #define FSL_CORENET_NUM_DEVDISR 5
1668 #else 1668 #else
1669 #define FSL_CORENET_DEVDISR_PCIE1 0x80000000 1669 #define FSL_CORENET_DEVDISR_PCIE1 0x80000000
1670 #define FSL_CORENET_DEVDISR_PCIE2 0x40000000 1670 #define FSL_CORENET_DEVDISR_PCIE2 0x40000000
1671 #define FSL_CORENET_DEVDISR_PCIE3 0x20000000 1671 #define FSL_CORENET_DEVDISR_PCIE3 0x20000000
1672 #define FSL_CORENET_DEVDISR_PCIE4 0x10000000 1672 #define FSL_CORENET_DEVDISR_PCIE4 0x10000000
1673 #define FSL_CORENET_DEVDISR_RMU 0x08000000 1673 #define FSL_CORENET_DEVDISR_RMU 0x08000000
1674 #define FSL_CORENET_DEVDISR_SRIO1 0x04000000 1674 #define FSL_CORENET_DEVDISR_SRIO1 0x04000000
1675 #define FSL_CORENET_DEVDISR_SRIO2 0x02000000 1675 #define FSL_CORENET_DEVDISR_SRIO2 0x02000000
1676 #define FSL_CORENET_DEVDISR_DMA1 0x00400000 1676 #define FSL_CORENET_DEVDISR_DMA1 0x00400000
1677 #define FSL_CORENET_DEVDISR_DMA2 0x00200000 1677 #define FSL_CORENET_DEVDISR_DMA2 0x00200000
1678 #define FSL_CORENET_DEVDISR_DDR1 0x00100000 1678 #define FSL_CORENET_DEVDISR_DDR1 0x00100000
1679 #define FSL_CORENET_DEVDISR_DDR2 0x00080000 1679 #define FSL_CORENET_DEVDISR_DDR2 0x00080000
1680 #define FSL_CORENET_DEVDISR_DBG 0x00010000 1680 #define FSL_CORENET_DEVDISR_DBG 0x00010000
1681 #define FSL_CORENET_DEVDISR_NAL 0x00008000 1681 #define FSL_CORENET_DEVDISR_NAL 0x00008000
1682 #define FSL_CORENET_DEVDISR_SATA1 0x00004000 1682 #define FSL_CORENET_DEVDISR_SATA1 0x00004000
1683 #define FSL_CORENET_DEVDISR_SATA2 0x00002000 1683 #define FSL_CORENET_DEVDISR_SATA2 0x00002000
1684 #define FSL_CORENET_DEVDISR_ELBC 0x00001000 1684 #define FSL_CORENET_DEVDISR_ELBC 0x00001000
1685 #define FSL_CORENET_DEVDISR_USB1 0x00000800 1685 #define FSL_CORENET_DEVDISR_USB1 0x00000800
1686 #define FSL_CORENET_DEVDISR_USB2 0x00000400 1686 #define FSL_CORENET_DEVDISR_USB2 0x00000400
1687 #define FSL_CORENET_DEVDISR_ESDHC 0x00000100 1687 #define FSL_CORENET_DEVDISR_ESDHC 0x00000100
1688 #define FSL_CORENET_DEVDISR_GPIO 0x00000080 1688 #define FSL_CORENET_DEVDISR_GPIO 0x00000080
1689 #define FSL_CORENET_DEVDISR_ESPI 0x00000040 1689 #define FSL_CORENET_DEVDISR_ESPI 0x00000040
1690 #define FSL_CORENET_DEVDISR_I2C1 0x00000020 1690 #define FSL_CORENET_DEVDISR_I2C1 0x00000020
1691 #define FSL_CORENET_DEVDISR_I2C2 0x00000010 1691 #define FSL_CORENET_DEVDISR_I2C2 0x00000010
1692 #define FSL_CORENET_DEVDISR_DUART1 0x00000002 1692 #define FSL_CORENET_DEVDISR_DUART1 0x00000002
1693 #define FSL_CORENET_DEVDISR_DUART2 0x00000001 1693 #define FSL_CORENET_DEVDISR_DUART2 0x00000001
1694 #define FSL_CORENET_DEVDISR2_PME 0x80000000 1694 #define FSL_CORENET_DEVDISR2_PME 0x80000000
1695 #define FSL_CORENET_DEVDISR2_SEC 0x40000000 1695 #define FSL_CORENET_DEVDISR2_SEC 0x40000000
1696 #define FSL_CORENET_DEVDISR2_QMBM 0x08000000 1696 #define FSL_CORENET_DEVDISR2_QMBM 0x08000000
1697 #define FSL_CORENET_DEVDISR2_FM1 0x02000000 1697 #define FSL_CORENET_DEVDISR2_FM1 0x02000000
1698 #define FSL_CORENET_DEVDISR2_10GEC1 0x01000000 1698 #define FSL_CORENET_DEVDISR2_10GEC1 0x01000000
1699 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000 1699 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000
1700 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000 1700 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
1701 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000 1701 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
1702 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000 1702 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
1703 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000 1703 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000
1704 #define FSL_CORENET_DEVDISR2_FM2 0x00020000 1704 #define FSL_CORENET_DEVDISR2_FM2 0x00020000
1705 #define FSL_CORENET_DEVDISR2_10GEC2 0x00010000 1705 #define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
1706 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000 1706 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
1707 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000 1707 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
1708 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000 1708 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
1709 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000 1709 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
1710 #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800 1710 #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
1711 #define FSL_CORENET_NUM_DEVDISR 2 1711 #define FSL_CORENET_NUM_DEVDISR 2
1712 u32 powmgtcsr; /* Power management status & control */ 1712 u32 powmgtcsr; /* Power management status & control */
1713 #endif 1713 #endif
1714 u8 res8[12]; 1714 u8 res8[12];
1715 u32 coredisru; /* uppper portion for support of 64 cores */ 1715 u32 coredisru; /* uppper portion for support of 64 cores */
1716 u32 coredisrl; /* lower portion for support of 64 cores */ 1716 u32 coredisrl; /* lower portion for support of 64 cores */
1717 u8 res9[8]; 1717 u8 res9[8];
1718 u32 pvr; /* Processor version */ 1718 u32 pvr; /* Processor version */
1719 u32 svr; /* System version */ 1719 u32 svr; /* System version */
1720 u8 res10[8]; 1720 u8 res10[8];
1721 u32 rstcr; /* Reset control */ 1721 u32 rstcr; /* Reset control */
1722 u32 rstrqpblsr; /* Reset request preboot loader status */ 1722 u32 rstrqpblsr; /* Reset request preboot loader status */
1723 u8 res11[8]; 1723 u8 res11[8];
1724 u32 rstrqmr1; /* Reset request mask */ 1724 u32 rstrqmr1; /* Reset request mask */
1725 u8 res12[4]; 1725 u8 res12[4];
1726 u32 rstrqsr1; /* Reset request status */ 1726 u32 rstrqsr1; /* Reset request status */
1727 u8 res13[4]; 1727 u8 res13[4];
1728 u8 res14[4]; 1728 u8 res14[4];
1729 u32 rstrqwdtmrl; /* Reset request WDT mask */ 1729 u32 rstrqwdtmrl; /* Reset request WDT mask */
1730 u8 res15[4]; 1730 u8 res15[4];
1731 u32 rstrqwdtsrl; /* Reset request WDT status */ 1731 u32 rstrqwdtsrl; /* Reset request WDT status */
1732 u8 res16[4]; 1732 u8 res16[4];
1733 u32 brrl; /* Boot release */ 1733 u32 brrl; /* Boot release */
1734 u8 res17[24]; 1734 u8 res17[24];
1735 u32 rcwsr[16]; /* Reset control word status */ 1735 u32 rcwsr[16]; /* Reset control word status */
1736 1736
1737 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 1737 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1738 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16 1738 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
1739 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f 1739 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
1740 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 1740 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
1741 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 1741 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
1742 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 1742 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
1743 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 1743 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1744 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17 1744 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
1745 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800 1745 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800
1746 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11 1746 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11
1747 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8 1747 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
1748 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3 1748 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
1749 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 1749 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1750 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 1750 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
1751 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000 1751 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
1752 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25 1752 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
1753 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 1753 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1754 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 1754 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
1755 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 1755 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1756 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ 1756 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
1757 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 1757 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
1758 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 1758 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1759 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 1759 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
1760 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 1760 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1761 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17 1761 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
1762 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 1762 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
1763 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 1763 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1764 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 1764 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
1765 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 1765 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1766 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 1766 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
1767 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 1767 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1768 #endif 1768 #endif
1769 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000 1769 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
1770 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000 1770 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
1771 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000 1771 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000
1772 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000 1772 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000
1773 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000 1773 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000
1774 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000 1774 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000
1775 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000 1775 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000
1776 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000 1776 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000
1777 #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
1778 #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011
1779 #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1
1777 1780
1778 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 1781 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
1779 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17 1782 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17
1780 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f 1783 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f
1781 #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000 1784 #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
1782 #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080 1785 #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
1783 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7 1786 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
1784 #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000 1787 #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
1785 #define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000 1788 #define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000
1786 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 1789 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1787 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */ 1790 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
1788 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */ 1791 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
1789 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 1792 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
1790 1793
1791 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000 1794 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
1792 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 1795 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
1793 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 1796 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
1794 #define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */ 1797 #define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
1795 #ifdef CONFIG_PPC_P4080 1798 #ifdef CONFIG_PPC_P4080
1796 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000 1799 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
1797 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000 1800 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
1798 #define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */ 1801 #define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
1799 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000 1802 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
1800 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000 1803 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
1801 #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000 1804 #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
1802 #endif 1805 #endif
1803 #if defined(CONFIG_PPC_P2041) \ 1806 #if defined(CONFIG_PPC_P2041) \
1804 || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020) 1807 || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
1805 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000 1808 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
1806 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000 1809 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
1807 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000 1810 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
1808 #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */ 1811 #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
1809 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000 1812 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000
1810 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000 1813 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
1811 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000 1814 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
1812 #endif 1815 #endif
1813 #if defined(CONFIG_PPC_P5040) 1816 #if defined(CONFIG_PPC_P5040)
1814 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000 1817 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
1815 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000 1818 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
1816 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000 1819 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
1817 #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */ 1820 #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
1818 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000 1821 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000
1819 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 1822 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
1820 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 1823 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
1821 #endif 1824 #endif
1822 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 1825 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
1823 #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ 1826 #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
1824 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 1827 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
1825 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 1828 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
1826 #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */ 1829 #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
1827 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 1830 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
1828 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000 1831 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
1829 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 1832 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
1830 #endif 1833 #endif
1831 #if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 1834 #if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
1832 #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ 1835 #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
1833 #define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000 1836 #define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
1834 #define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000 1837 #define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
1835 #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */ 1838 #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
1836 #define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000 1839 #define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
1837 #define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000 1840 #define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000
1838 #define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000 1841 #define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000
1839 #endif 1842 #endif
1840 u8 res18[192]; 1843 u8 res18[192];
1841 u32 scratchrw[4]; /* Scratch Read/Write */ 1844 u32 scratchrw[4]; /* Scratch Read/Write */
1842 u8 res19[240]; 1845 u8 res19[240];
1843 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 1846 u32 scratchw1r[4]; /* Scratch Read (Write once) */
1844 u8 res20[240]; 1847 u8 res20[240];
1845 u32 scrtsr[8]; /* Core reset status */ 1848 u32 scrtsr[8]; /* Core reset status */
1846 u8 res21[224]; 1849 u8 res21[224];
1847 u32 pex1liodnr; /* PCI Express 1 LIODN */ 1850 u32 pex1liodnr; /* PCI Express 1 LIODN */
1848 u32 pex2liodnr; /* PCI Express 2 LIODN */ 1851 u32 pex2liodnr; /* PCI Express 2 LIODN */
1849 u32 pex3liodnr; /* PCI Express 3 LIODN */ 1852 u32 pex3liodnr; /* PCI Express 3 LIODN */
1850 u32 pex4liodnr; /* PCI Express 4 LIODN */ 1853 u32 pex4liodnr; /* PCI Express 4 LIODN */
1851 u32 rio1liodnr; /* RIO 1 LIODN */ 1854 u32 rio1liodnr; /* RIO 1 LIODN */
1852 u32 rio2liodnr; /* RIO 2 LIODN */ 1855 u32 rio2liodnr; /* RIO 2 LIODN */
1853 u32 rio3liodnr; /* RIO 3 LIODN */ 1856 u32 rio3liodnr; /* RIO 3 LIODN */
1854 u32 rio4liodnr; /* RIO 4 LIODN */ 1857 u32 rio4liodnr; /* RIO 4 LIODN */
1855 u32 usb1liodnr; /* USB 1 LIODN */ 1858 u32 usb1liodnr; /* USB 1 LIODN */
1856 u32 usb2liodnr; /* USB 2 LIODN */ 1859 u32 usb2liodnr; /* USB 2 LIODN */
1857 u32 usb3liodnr; /* USB 3 LIODN */ 1860 u32 usb3liodnr; /* USB 3 LIODN */
1858 u32 usb4liodnr; /* USB 4 LIODN */ 1861 u32 usb4liodnr; /* USB 4 LIODN */
1859 u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */ 1862 u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */
1860 u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */ 1863 u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */
1861 u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */ 1864 u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */
1862 u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */ 1865 u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */
1863 u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */ 1866 u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */
1864 u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */ 1867 u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */
1865 u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */ 1868 u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */
1866 u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */ 1869 u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */
1867 u32 sata1liodnr; /* SATA 1 LIODN */ 1870 u32 sata1liodnr; /* SATA 1 LIODN */
1868 u32 sata2liodnr; /* SATA 2 LIODN */ 1871 u32 sata2liodnr; /* SATA 2 LIODN */
1869 u32 sata3liodnr; /* SATA 3 LIODN */ 1872 u32 sata3liodnr; /* SATA 3 LIODN */
1870 u32 sata4liodnr; /* SATA 4 LIODN */ 1873 u32 sata4liodnr; /* SATA 4 LIODN */
1871 u8 res22[32]; 1874 u8 res22[32];
1872 u32 dma1liodnr; /* DMA 1 LIODN */ 1875 u32 dma1liodnr; /* DMA 1 LIODN */
1873 u32 dma2liodnr; /* DMA 2 LIODN */ 1876 u32 dma2liodnr; /* DMA 2 LIODN */
1874 u32 dma3liodnr; /* DMA 3 LIODN */ 1877 u32 dma3liodnr; /* DMA 3 LIODN */
1875 u32 dma4liodnr; /* DMA 4 LIODN */ 1878 u32 dma4liodnr; /* DMA 4 LIODN */
1876 u8 res23[48]; 1879 u8 res23[48];
1877 u8 res24[64]; 1880 u8 res24[64];
1878 u32 pblsr; /* Preboot loader status */ 1881 u32 pblsr; /* Preboot loader status */
1879 u32 pamubypenr; /* PAMU bypass enable */ 1882 u32 pamubypenr; /* PAMU bypass enable */
1880 u32 dmacr1; /* DMA control */ 1883 u32 dmacr1; /* DMA control */
1881 u8 res25[4]; 1884 u8 res25[4];
1882 u32 gensr1; /* General status */ 1885 u32 gensr1; /* General status */
1883 u8 res26[12]; 1886 u8 res26[12];
1884 u32 gencr1; /* General control */ 1887 u32 gencr1; /* General control */
1885 u8 res27[12]; 1888 u8 res27[12];
1886 u8 res28[4]; 1889 u8 res28[4];
1887 u32 cgensrl; /* Core general status */ 1890 u32 cgensrl; /* Core general status */
1888 u8 res29[8]; 1891 u8 res29[8];
1889 u8 res30[4]; 1892 u8 res30[4];
1890 u32 cgencrl; /* Core general control */ 1893 u32 cgencrl; /* Core general control */
1891 u8 res31[184]; 1894 u8 res31[184];
1892 u32 sriopstecr; /* SRIO prescaler timer enable control */ 1895 u32 sriopstecr; /* SRIO prescaler timer enable control */
1893 u32 dcsrcr; /* DCSR Control register */ 1896 u32 dcsrcr; /* DCSR Control register */
1894 u8 res31a[56]; 1897 u8 res31a[56];
1895 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 1898 u32 tp_ityp[64]; /* Topology Initiator Type Register */
1896 struct { 1899 struct {
1897 u32 upper; 1900 u32 upper;
1898 u32 lower; 1901 u32 lower;
1899 } tp_cluster[16]; /* Core Cluster n Topology Register */ 1902 } tp_cluster[16]; /* Core Cluster n Topology Register */
1900 u8 res32[1344]; 1903 u8 res32[1344];
1901 u32 pmuxcr; /* Pin multiplexing control */ 1904 u32 pmuxcr; /* Pin multiplexing control */
1902 u8 res33[60]; 1905 u8 res33[60];
1903 u32 iovselsr; /* I/O voltage selection status */ 1906 u32 iovselsr; /* I/O voltage selection status */
1904 u8 res34[28]; 1907 u8 res34[28];
1905 u32 ddrclkdr; /* DDR clock disable */ 1908 u32 ddrclkdr; /* DDR clock disable */
1906 u8 res35; 1909 u8 res35;
1907 u32 elbcclkdr; /* eLBC clock disable */ 1910 u32 elbcclkdr; /* eLBC clock disable */
1908 u8 res36[20]; 1911 u8 res36[20];
1909 u32 sdhcpcr; /* eSDHC polarity configuration */ 1912 u32 sdhcpcr; /* eSDHC polarity configuration */
1910 u8 res37[380]; 1913 u8 res37[380];
1911 } ccsr_gur_t; 1914 } ccsr_gur_t;
1912 1915
1913 #define TP_ITYP_AV 0x00000001 /* Initiator available */ 1916 #define TP_ITYP_AV 0x00000001 /* Initiator available */
1914 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ 1917 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
1915 #define TP_ITYP_TYPE_OTHER 0x0 1918 #define TP_ITYP_TYPE_OTHER 0x0
1916 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ 1919 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
1917 #define TP_ITYP_TYPE_SC 0x2 /* StarCore DSP */ 1920 #define TP_ITYP_TYPE_SC 0x2 /* StarCore DSP */
1918 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ 1921 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
1919 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ 1922 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
1920 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ 1923 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
1921 1924
1922 #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ 1925 #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
1923 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ 1926 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
1924 #define TP_INIT_PER_CLUSTER 4 1927 #define TP_INIT_PER_CLUSTER 4
1925 1928
1926 #define FSL_CORENET_DCSR_SZ_MASK 0x00000003 1929 #define FSL_CORENET_DCSR_SZ_MASK 0x00000003
1927 #define FSL_CORENET_DCSR_SZ_4M 0x0 1930 #define FSL_CORENET_DCSR_SZ_4M 0x0
1928 #define FSL_CORENET_DCSR_SZ_1G 0x3 1931 #define FSL_CORENET_DCSR_SZ_1G 0x3
1929 1932
1930 /* 1933 /*
1931 * On p4080 we have an LIODN for msg unit (rmu) but not maintenance 1934 * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
1932 * everything after has RMan thus msg unit LIODN is used for maintenance 1935 * everything after has RMan thus msg unit LIODN is used for maintenance
1933 */ 1936 */
1934 #define rmuliodnr rio1maintliodnr 1937 #define rmuliodnr rio1maintliodnr
1935 1938
1936 typedef struct ccsr_clk { 1939 typedef struct ccsr_clk {
1937 struct { 1940 struct {
1938 u32 clkcncsr; /* core cluster n clock control status */ 1941 u32 clkcncsr; /* core cluster n clock control status */
1939 u8 res_004[0x0c]; 1942 u8 res_004[0x0c];
1940 u32 clkcgnhwacsr;/* clock generator n hardware accelerator */ 1943 u32 clkcgnhwacsr;/* clock generator n hardware accelerator */
1941 u8 res_014[0x0c]; 1944 u8 res_014[0x0c];
1942 } clkcsr[12]; 1945 } clkcsr[12];
1943 u8 res_100[0x680]; /* 0x100 */ 1946 u8 res_100[0x680]; /* 0x100 */
1944 struct { 1947 struct {
1945 u32 pllcngsr; 1948 u32 pllcngsr;
1946 u8 res10[0x1c]; 1949 u8 res10[0x1c];
1947 } pllcgsr[12]; 1950 } pllcgsr[12];
1948 u8 res21[0x280]; 1951 u8 res21[0x280];
1949 u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 1952 u32 pllpgsr; /* 0xc00 Platform PLL General Status */
1950 u8 res16[0x1c]; 1953 u8 res16[0x1c];
1951 u32 plldgsr; /* 0xc20 DDR PLL General Status */ 1954 u32 plldgsr; /* 0xc20 DDR PLL General Status */
1952 u8 res17[0x3dc]; 1955 u8 res17[0x3dc];
1953 } ccsr_clk_t; 1956 } ccsr_clk_t;
1954 1957
1955 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 1958 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1956 typedef struct ccsr_rcpm { 1959 typedef struct ccsr_rcpm {
1957 u8 res_00[12]; 1960 u8 res_00[12];
1958 u32 tph10sr0; /* Thread PH10 Status Register */ 1961 u32 tph10sr0; /* Thread PH10 Status Register */
1959 u8 res_10[12]; 1962 u8 res_10[12];
1960 u32 tph10setr0; /* Thread PH10 Set Control Register */ 1963 u32 tph10setr0; /* Thread PH10 Set Control Register */
1961 u8 res_20[12]; 1964 u8 res_20[12];
1962 u32 tph10clrr0; /* Thread PH10 Clear Control Register */ 1965 u32 tph10clrr0; /* Thread PH10 Clear Control Register */
1963 u8 res_30[12]; 1966 u8 res_30[12];
1964 u32 tph10psr0; /* Thread PH10 Previous Status Register */ 1967 u32 tph10psr0; /* Thread PH10 Previous Status Register */
1965 u8 res_40[12]; 1968 u8 res_40[12];
1966 u32 twaitsr0; /* Thread Wait Status Register */ 1969 u32 twaitsr0; /* Thread Wait Status Register */
1967 u8 res_50[96]; 1970 u8 res_50[96];
1968 u32 pcph15sr; /* Physical Core PH15 Status Register */ 1971 u32 pcph15sr; /* Physical Core PH15 Status Register */
1969 u32 pcph15setr; /* Physical Core PH15 Set Control Register */ 1972 u32 pcph15setr; /* Physical Core PH15 Set Control Register */
1970 u32 pcph15clrr; /* Physical Core PH15 Clear Control Register */ 1973 u32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
1971 u32 pcph15psr; /* Physical Core PH15 Prev Status Register */ 1974 u32 pcph15psr; /* Physical Core PH15 Prev Status Register */
1972 u8 res_c0[16]; 1975 u8 res_c0[16];
1973 u32 pcph20sr; /* Physical Core PH20 Status Register */ 1976 u32 pcph20sr; /* Physical Core PH20 Status Register */
1974 u32 pcph20setr; /* Physical Core PH20 Set Control Register */ 1977 u32 pcph20setr; /* Physical Core PH20 Set Control Register */
1975 u32 pcph20clrr; /* Physical Core PH20 Clear Control Register */ 1978 u32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
1976 u32 pcph20psr; /* Physical Core PH20 Prev Status Register */ 1979 u32 pcph20psr; /* Physical Core PH20 Prev Status Register */
1977 u32 pcpw20sr; /* Physical Core PW20 Status Register */ 1980 u32 pcpw20sr; /* Physical Core PW20 Status Register */
1978 u8 res_e0[12]; 1981 u8 res_e0[12];
1979 u32 pcph30sr; /* Physical Core PH30 Status Register */ 1982 u32 pcph30sr; /* Physical Core PH30 Status Register */
1980 u32 pcph30setr; /* Physical Core PH30 Set Control Register */ 1983 u32 pcph30setr; /* Physical Core PH30 Set Control Register */
1981 u32 pcph30clrr; /* Physical Core PH30 Clear Control Register */ 1984 u32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
1982 u32 pcph30psr; /* Physical Core PH30 Prev Status Register */ 1985 u32 pcph30psr; /* Physical Core PH30 Prev Status Register */
1983 u8 res_100[32]; 1986 u8 res_100[32];
1984 u32 ippwrgatecr; /* IP Power Gating Control Register */ 1987 u32 ippwrgatecr; /* IP Power Gating Control Register */
1985 u8 res_124[12]; 1988 u8 res_124[12];
1986 u32 powmgtcsr; /* Power Management Control & Status Reg */ 1989 u32 powmgtcsr; /* Power Management Control & Status Reg */
1987 u8 res_134[12]; 1990 u8 res_134[12];
1988 u32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */ 1991 u32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
1989 u8 res_150[12]; 1992 u8 res_150[12];
1990 u32 tpmimr0; /* Thread PM Interrupt Mask Reg */ 1993 u32 tpmimr0; /* Thread PM Interrupt Mask Reg */
1991 u8 res_160[12]; 1994 u8 res_160[12];
1992 u32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */ 1995 u32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */
1993 u8 res_170[12]; 1996 u8 res_170[12];
1994 u32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */ 1997 u32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */
1995 u8 res_180[12]; 1998 u8 res_180[12];
1996 u32 tpmnmimr0; /* Thread PM NMI Mask Reg */ 1999 u32 tpmnmimr0; /* Thread PM NMI Mask Reg */
1997 u8 res_190[12]; 2000 u8 res_190[12];
1998 u32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */ 2001 u32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */
1999 u32 pctbenr; /* Physical Core Time Base Enable Reg */ 2002 u32 pctbenr; /* Physical Core Time Base Enable Reg */
2000 u32 pctbclkselr; /* Physical Core Time Base Clock Select */ 2003 u32 pctbclkselr; /* Physical Core Time Base Clock Select */
2001 u32 tbclkdivr; /* Time Base Clock Divider Register */ 2004 u32 tbclkdivr; /* Time Base Clock Divider Register */
2002 u8 res_1ac[4]; 2005 u8 res_1ac[4];
2003 u32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */ 2006 u32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
2004 u32 clpcl10sr; /* Cluster PCL10 Status Register */ 2007 u32 clpcl10sr; /* Cluster PCL10 Status Register */
2005 u32 clpcl10setr; /* Cluster PCL30 Set Control Register */ 2008 u32 clpcl10setr; /* Cluster PCL30 Set Control Register */
2006 u32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */ 2009 u32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */
2007 u32 clpcl10psr; /* Cluster PCL30 Prev Status Register */ 2010 u32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
2008 u32 cddslpsetr; /* Core Domain Deep Sleep Set Register */ 2011 u32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
2009 u32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */ 2012 u32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
2010 u32 cdpwroksetr; /* Core Domain Power OK Set Register */ 2013 u32 cdpwroksetr; /* Core Domain Power OK Set Register */
2011 u32 cdpwrokclrr; /* Core Domain Power OK Clear Register */ 2014 u32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
2012 u32 cdpwrensr; /* Core Domain Power Enable Status Register */ 2015 u32 cdpwrensr; /* Core Domain Power Enable Status Register */
2013 u32 cddslsr; /* Core Domain Deep Sleep Status Register */ 2016 u32 cddslsr; /* Core Domain Deep Sleep Status Register */
2014 u8 res_1e8[8]; 2017 u8 res_1e8[8];
2015 u32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */ 2018 u32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */
2016 u8 res_300[3568]; 2019 u8 res_300[3568];
2017 } ccsr_rcpm_t; 2020 } ccsr_rcpm_t;
2018 2021
2019 #define ctbenrl pctbenr 2022 #define ctbenrl pctbenr
2020 2023
2021 #else 2024 #else
2022 typedef struct ccsr_rcpm { 2025 typedef struct ccsr_rcpm {
2023 u8 res1[4]; 2026 u8 res1[4];
2024 u32 cdozsrl; /* Core Doze Status */ 2027 u32 cdozsrl; /* Core Doze Status */
2025 u8 res2[4]; 2028 u8 res2[4];
2026 u32 cdozcrl; /* Core Doze Control */ 2029 u32 cdozcrl; /* Core Doze Control */
2027 u8 res3[4]; 2030 u8 res3[4];
2028 u32 cnapsrl; /* Core Nap Status */ 2031 u32 cnapsrl; /* Core Nap Status */
2029 u8 res4[4]; 2032 u8 res4[4];
2030 u32 cnapcrl; /* Core Nap Control */ 2033 u32 cnapcrl; /* Core Nap Control */
2031 u8 res5[4]; 2034 u8 res5[4];
2032 u32 cdozpsrl; /* Core Doze Previous Status */ 2035 u32 cdozpsrl; /* Core Doze Previous Status */
2033 u8 res6[4]; 2036 u8 res6[4];
2034 u32 cdozpcrl; /* Core Doze Previous Control */ 2037 u32 cdozpcrl; /* Core Doze Previous Control */
2035 u8 res7[4]; 2038 u8 res7[4];
2036 u32 cwaitsrl; /* Core Wait Status */ 2039 u32 cwaitsrl; /* Core Wait Status */
2037 u8 res8[8]; 2040 u8 res8[8];
2038 u32 powmgtcsr; /* Power Mangement Control & Status */ 2041 u32 powmgtcsr; /* Power Mangement Control & Status */
2039 u8 res9[12]; 2042 u8 res9[12];
2040 u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */ 2043 u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */
2041 u8 res10[12]; 2044 u8 res10[12];
2042 u8 res11[4]; 2045 u8 res11[4];
2043 u32 cpmimrl; /* Core PM IRQ Masking */ 2046 u32 cpmimrl; /* Core PM IRQ Masking */
2044 u8 res12[4]; 2047 u8 res12[4];
2045 u32 cpmcimrl; /* Core PM Critical IRQ Masking */ 2048 u32 cpmcimrl; /* Core PM Critical IRQ Masking */
2046 u8 res13[4]; 2049 u8 res13[4];
2047 u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */ 2050 u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */
2048 u8 res14[4]; 2051 u8 res14[4];
2049 u32 cpmnmimrl; /* Core PM NMI Masking */ 2052 u32 cpmnmimrl; /* Core PM NMI Masking */
2050 u8 res15[4]; 2053 u8 res15[4];
2051 u32 ctbenrl; /* Core Time Base Enable */ 2054 u32 ctbenrl; /* Core Time Base Enable */
2052 u8 res16[4]; 2055 u8 res16[4];
2053 u32 ctbclkselrl; /* Core Time Base Clock Select */ 2056 u32 ctbclkselrl; /* Core Time Base Clock Select */
2054 u8 res17[4]; 2057 u8 res17[4];
2055 u32 ctbhltcrl; /* Core Time Base Halt Control */ 2058 u32 ctbhltcrl; /* Core Time Base Halt Control */
2056 u8 res18[0xf68]; 2059 u8 res18[0xf68];
2057 } ccsr_rcpm_t; 2060 } ccsr_rcpm_t;
2058 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 2061 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
2059 2062
2060 #else 2063 #else
2061 typedef struct ccsr_gur { 2064 typedef struct ccsr_gur {
2062 u32 porpllsr; /* POR PLL ratio status */ 2065 u32 porpllsr; /* POR PLL ratio status */
2063 #ifdef CONFIG_MPC8536 2066 #ifdef CONFIG_MPC8536
2064 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 2067 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
2065 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 2068 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
2066 #elif defined(CONFIG_PPC_C29X) 2069 #elif defined(CONFIG_PPC_C29X)
2067 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 2070 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2068 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \ 2071 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
2069 & MPC85xx_PORDEVSR2_DDR_SPD_0) \ 2072 & MPC85xx_PORDEVSR2_DDR_SPD_0) \
2070 >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT)) 2073 >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
2071 #else 2074 #else
2072 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132) 2075 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
2073 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 2076 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2074 #else 2077 #else
2075 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 2078 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
2076 #endif 2079 #endif
2077 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 2080 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
2078 #endif 2081 #endif
2079 #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 2082 #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
2080 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25 2083 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
2081 #define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e 2084 #define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
2082 #define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1 2085 #define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
2083 u32 porbmsr; /* POR boot mode status */ 2086 u32 porbmsr; /* POR boot mode status */
2084 #define MPC85xx_PORBMSR_HA 0x00070000 2087 #define MPC85xx_PORBMSR_HA 0x00070000
2085 #define MPC85xx_PORBMSR_HA_SHIFT 16 2088 #define MPC85xx_PORBMSR_HA_SHIFT 16
2086 #define MPC85xx_PORBMSR_ROMLOC_SHIFT 24 2089 #define MPC85xx_PORBMSR_ROMLOC_SHIFT 24
2087 #define PORBMSR_ROMLOC_SPI 0x6 2090 #define PORBMSR_ROMLOC_SPI 0x6
2088 #define PORBMSR_ROMLOC_SDHC 0x7 2091 #define PORBMSR_ROMLOC_SDHC 0x7
2089 #define PORBMSR_ROMLOC_NAND_2K 0x9 2092 #define PORBMSR_ROMLOC_NAND_2K 0x9
2090 #define PORBMSR_ROMLOC_NOR 0xf 2093 #define PORBMSR_ROMLOC_NOR 0xf
2091 u32 porimpscr; /* POR I/O impedance status & control */ 2094 u32 porimpscr; /* POR I/O impedance status & control */
2092 u32 pordevsr; /* POR I/O device status regsiter */ 2095 u32 pordevsr; /* POR I/O device status regsiter */
2093 #if defined(CONFIG_P1017) || defined(CONFIG_P1023) 2096 #if defined(CONFIG_P1017) || defined(CONFIG_P1023)
2094 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000 2097 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
2095 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000 2098 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
2096 #define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000 2099 #define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000
2097 #else 2100 #else
2098 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 2101 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
2099 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000 2102 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
2100 #endif 2103 #endif
2101 #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 2104 #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
2102 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 2105 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
2103 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 2106 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
2104 #define MPC85xx_PORDEVSR_PCI1 0x00800000 2107 #define MPC85xx_PORDEVSR_PCI1 0x00800000
2105 #if defined(CONFIG_P1013) || defined(CONFIG_P1022) 2108 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
2106 #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000 2109 #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
2107 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18 2110 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
2108 #elif defined(CONFIG_P1017) || defined(CONFIG_P1023) 2111 #elif defined(CONFIG_P1017) || defined(CONFIG_P1023)
2109 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 2112 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2110 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 2113 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2111 #else 2114 #else
2112 #if defined(CONFIG_P1010) 2115 #if defined(CONFIG_P1010)
2113 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 2116 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2114 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 2117 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2115 #elif defined(CONFIG_BSC9132) 2118 #elif defined(CONFIG_BSC9132)
2116 #define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000 2119 #define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
2117 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17 2120 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
2118 #elif defined(CONFIG_PPC_C29X) 2121 #elif defined(CONFIG_PPC_C29X)
2119 #define MPC85xx_PORDEVSR_IO_SEL 0x00e00000 2122 #define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
2120 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 2123 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2121 #else 2124 #else
2122 #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 2125 #define MPC85xx_PORDEVSR_IO_SEL 0x00780000
2123 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 2126 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
2124 #endif /* if defined(CONFIG_P1010) */ 2127 #endif /* if defined(CONFIG_P1010) */
2125 #endif 2128 #endif
2126 #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 2129 #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
2127 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 2130 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
2128 #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000 2131 #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
2129 #define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000 2132 #define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
2130 #define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000 2133 #define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
2131 #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060 2134 #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
2132 #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 2135 #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
2133 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 2136 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
2134 u32 pordbgmsr; /* POR debug mode status */ 2137 u32 pordbgmsr; /* POR debug mode status */
2135 u32 pordevsr2; /* POR I/O device status 2 */ 2138 u32 pordevsr2; /* POR I/O device status 2 */
2136 #if defined(CONFIG_PPC_C29X) 2139 #if defined(CONFIG_PPC_C29X)
2137 #define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008 2140 #define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
2138 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3 2141 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
2139 #endif 2142 #endif
2140 /* The 8544 RM says this is bit 26, but it's really bit 24 */ 2143 /* The 8544 RM says this is bit 26, but it's really bit 24 */
2141 #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 2144 #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
2142 u8 res1[8]; 2145 u8 res1[8];
2143 u32 gpporcr; /* General-purpose POR configuration */ 2146 u32 gpporcr; /* General-purpose POR configuration */
2144 u8 res2[12]; 2147 u8 res2[12];
2145 #if defined(CONFIG_MPC8536) 2148 #if defined(CONFIG_MPC8536)
2146 u32 gencfgr; /* General Configuration Register */ 2149 u32 gencfgr; /* General Configuration Register */
2147 #define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000 2150 #define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
2148 #else 2151 #else
2149 u32 gpiocr; /* GPIO control */ 2152 u32 gpiocr; /* GPIO control */
2150 #endif 2153 #endif
2151 u8 res3[12]; 2154 u8 res3[12];
2152 #if defined(CONFIG_MPC8569) 2155 #if defined(CONFIG_MPC8569)
2153 u32 plppar1; /* Platform port pin assignment 1 */ 2156 u32 plppar1; /* Platform port pin assignment 1 */
2154 u32 plppar2; /* Platform port pin assignment 2 */ 2157 u32 plppar2; /* Platform port pin assignment 2 */
2155 u32 plpdir1; /* Platform port pin direction 1 */ 2158 u32 plpdir1; /* Platform port pin direction 1 */
2156 u32 plpdir2; /* Platform port pin direction 2 */ 2159 u32 plpdir2; /* Platform port pin direction 2 */
2157 #else 2160 #else
2158 u32 gpoutdr; /* General-purpose output data */ 2161 u32 gpoutdr; /* General-purpose output data */
2159 u8 res4[12]; 2162 u8 res4[12];
2160 #endif 2163 #endif
2161 u32 gpindr; /* General-purpose input data */ 2164 u32 gpindr; /* General-purpose input data */
2162 u8 res5[12]; 2165 u8 res5[12];
2163 u32 pmuxcr; /* Alt. function signal multiplex control */ 2166 u32 pmuxcr; /* Alt. function signal multiplex control */
2164 #if defined(CONFIG_P1010) || defined(CONFIG_P1014) 2167 #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
2165 #define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000 2168 #define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000
2166 #define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000 2169 #define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000
2167 #define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000 2170 #define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000
2168 #define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000 2171 #define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000
2169 #define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000 2172 #define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000
2170 #define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000 2173 #define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000
2171 #define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000 2174 #define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000
2172 #define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000 2175 #define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000
2173 #define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000 2176 #define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000
2174 #define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000 2177 #define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000
2175 #define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000 2178 #define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000
2176 #define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000 2179 #define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000
2177 #define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000 2180 #define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000
2178 #define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000 2181 #define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000
2179 #define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000 2182 #define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000
2180 #define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000 2183 #define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000
2181 #define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000 2184 #define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000
2182 #define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000 2185 #define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000
2183 #define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000 2186 #define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000
2184 #define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000 2187 #define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000
2185 #define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000 2188 #define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000
2186 #define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000 2189 #define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000
2187 #define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000 2190 #define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000
2188 #define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000 2191 #define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000
2189 #define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000 2192 #define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000
2190 #define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000 2193 #define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000
2191 #define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000 2194 #define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000
2192 #define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000 2195 #define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000
2193 #define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400 2196 #define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400
2194 #define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800 2197 #define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800
2195 #define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00 2198 #define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00
2196 #define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300 2199 #define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300
2197 #define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200 2200 #define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200
2198 #define MPC85xx_PMUXCR_LCLK_RES 0x00000040 2201 #define MPC85xx_PMUXCR_LCLK_RES 0x00000040
2199 #define MPC85xx_PMUXCR_LCLK_USB 0x00000080 2202 #define MPC85xx_PMUXCR_LCLK_USB 0x00000080
2200 #define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0 2203 #define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0
2201 #define MPC85xx_PMUXCR_SPI_RES 0x00000030 2204 #define MPC85xx_PMUXCR_SPI_RES 0x00000030
2202 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000020 2205 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000020
2203 #define MPC85xx_PMUXCR_CAN1_UART 0x00000004 2206 #define MPC85xx_PMUXCR_CAN1_UART 0x00000004
2204 #define MPC85xx_PMUXCR_CAN1_TDM 0x00000008 2207 #define MPC85xx_PMUXCR_CAN1_TDM 0x00000008
2205 #define MPC85xx_PMUXCR_CAN1_RES 0x0000000C 2208 #define MPC85xx_PMUXCR_CAN1_RES 0x0000000C
2206 #define MPC85xx_PMUXCR_CAN2_UART 0x00000001 2209 #define MPC85xx_PMUXCR_CAN2_UART 0x00000001
2207 #define MPC85xx_PMUXCR_CAN2_TDM 0x00000002 2210 #define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
2208 #define MPC85xx_PMUXCR_CAN2_RES 0x00000003 2211 #define MPC85xx_PMUXCR_CAN2_RES 0x00000003
2209 #endif 2212 #endif
2210 #if defined(CONFIG_P1017) || defined(CONFIG_P1023) 2213 #if defined(CONFIG_P1017) || defined(CONFIG_P1023)
2211 #define MPC85xx_PMUXCR_TSEC1_1 0x10000000 2214 #define MPC85xx_PMUXCR_TSEC1_1 0x10000000
2212 #else 2215 #else
2213 #define MPC85xx_PMUXCR_SD_DATA 0x80000000 2216 #define MPC85xx_PMUXCR_SD_DATA 0x80000000
2214 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000 2217 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000
2215 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000 2218 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000
2216 #define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000 2219 #define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000
2217 #define MPC85xx_PMUXCR_TDM_ENA 0x00800000 2220 #define MPC85xx_PMUXCR_TDM_ENA 0x00800000
2218 #define MPC85xx_PMUXCR_QE0 0x00008000 2221 #define MPC85xx_PMUXCR_QE0 0x00008000
2219 #define MPC85xx_PMUXCR_QE1 0x00004000 2222 #define MPC85xx_PMUXCR_QE1 0x00004000
2220 #define MPC85xx_PMUXCR_QE2 0x00002000 2223 #define MPC85xx_PMUXCR_QE2 0x00002000
2221 #define MPC85xx_PMUXCR_QE3 0x00001000 2224 #define MPC85xx_PMUXCR_QE3 0x00001000
2222 #define MPC85xx_PMUXCR_QE4 0x00000800 2225 #define MPC85xx_PMUXCR_QE4 0x00000800
2223 #define MPC85xx_PMUXCR_QE5 0x00000400 2226 #define MPC85xx_PMUXCR_QE5 0x00000400
2224 #define MPC85xx_PMUXCR_QE6 0x00000200 2227 #define MPC85xx_PMUXCR_QE6 0x00000200
2225 #define MPC85xx_PMUXCR_QE7 0x00000100 2228 #define MPC85xx_PMUXCR_QE7 0x00000100
2226 #define MPC85xx_PMUXCR_QE8 0x00000080 2229 #define MPC85xx_PMUXCR_QE8 0x00000080
2227 #define MPC85xx_PMUXCR_QE9 0x00000040 2230 #define MPC85xx_PMUXCR_QE9 0x00000040
2228 #define MPC85xx_PMUXCR_QE10 0x00000020 2231 #define MPC85xx_PMUXCR_QE10 0x00000020
2229 #define MPC85xx_PMUXCR_QE11 0x00000010 2232 #define MPC85xx_PMUXCR_QE11 0x00000010
2230 #define MPC85xx_PMUXCR_QE12 0x00000008 2233 #define MPC85xx_PMUXCR_QE12 0x00000008
2231 #endif 2234 #endif
2232 #if defined(CONFIG_P1013) || defined(CONFIG_P1022) 2235 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
2233 #define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00 2236 #define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
2234 #define MPC85xx_PMUXCR_TDM 0x00014800 2237 #define MPC85xx_PMUXCR_TDM 0x00014800
2235 #define MPC85xx_PMUXCR_SPI_MASK 0x00600000 2238 #define MPC85xx_PMUXCR_SPI_MASK 0x00600000
2236 #define MPC85xx_PMUXCR_SPI 0x00000000 2239 #define MPC85xx_PMUXCR_SPI 0x00000000
2237 #endif 2240 #endif
2238 #if defined(CONFIG_BSC9131) 2241 #if defined(CONFIG_BSC9131)
2239 #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000 2242 #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
2240 #define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000 2243 #define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
2241 #define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000 2244 #define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000
2242 #define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000 2245 #define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000
2243 #define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000 2246 #define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000
2244 #define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000 2247 #define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000
2245 #define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000 2248 #define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000
2246 #define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000 2249 #define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000
2247 #define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000 2250 #define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000
2248 #define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000 2251 #define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000
2249 #define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000 2252 #define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000
2250 #define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000 2253 #define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000
2251 #define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000 2254 #define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000
2252 #define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000 2255 #define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000
2253 #define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000 2256 #define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000
2254 #define MPC85xx_PMUXCR_SDHC_USIM 0x00010000 2257 #define MPC85xx_PMUXCR_SDHC_USIM 0x00010000
2255 #define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000 2258 #define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000
2256 #define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000 2259 #define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000
2257 #define MPC85xx_PMUXCR_SDHC_RESV 0x00004000 2260 #define MPC85xx_PMUXCR_SDHC_RESV 0x00004000
2258 #define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000 2261 #define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000
2259 #define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000 2262 #define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000
2260 #define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000 2263 #define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000
2261 #define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000 2264 #define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000
2262 #define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000 2265 #define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000
2263 #define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400 2266 #define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400
2264 #define MPC85xx_PMUXCR_USB_RSVD 0x00000C00 2267 #define MPC85xx_PMUXCR_USB_RSVD 0x00000C00
2265 #define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800 2268 #define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800
2266 #define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100 2269 #define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100
2267 #define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200 2270 #define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200
2268 #define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300 2271 #define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300
2269 #define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040 2272 #define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040
2270 #define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080 2273 #define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080
2271 #define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0 2274 #define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0
2272 #define MPC85xx_PMUXCR_SPI1_UART3 0x00000010 2275 #define MPC85xx_PMUXCR_SPI1_UART3 0x00000010
2273 #define MPC85xx_PMUXCR_SPI1_SIM 0x00000020 2276 #define MPC85xx_PMUXCR_SPI1_SIM 0x00000020
2274 #define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030 2277 #define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030
2275 #define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004 2278 #define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004
2276 #define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008 2279 #define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008
2277 #define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C 2280 #define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C
2278 #define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001 2281 #define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001
2279 #define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002 2282 #define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
2280 #define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003 2283 #define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
2281 #endif 2284 #endif
2282 #ifdef CONFIG_BSC9132 2285 #ifdef CONFIG_BSC9132
2283 #define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000 2286 #define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
2284 #define MPC85xx_PMUXCR0_SIM_SEL 0x00014000 2287 #define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
2285 #endif 2288 #endif
2286 #if defined(CONFIG_PPC_C29X) 2289 #if defined(CONFIG_PPC_C29X)
2287 #define MPC85xx_PMUXCR_SPI_MASK 0x00000300 2290 #define MPC85xx_PMUXCR_SPI_MASK 0x00000300
2288 #define MPC85xx_PMUXCR_SPI 0x00000000 2291 #define MPC85xx_PMUXCR_SPI 0x00000000
2289 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000100 2292 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
2290 #endif 2293 #endif
2291 u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ 2294 u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
2292 #if defined(CONFIG_P1010) || defined(CONFIG_P1014) 2295 #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
2293 #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000 2296 #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
2294 #define MPC85xx_PMUXCR2_UART_TDM 0x80000000 2297 #define MPC85xx_PMUXCR2_UART_TDM 0x80000000
2295 #define MPC85xx_PMUXCR2_UART_RES 0xC0000000 2298 #define MPC85xx_PMUXCR2_UART_RES 0xC0000000
2296 #define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000 2299 #define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000
2297 #define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000 2300 #define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000
2298 #define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000 2301 #define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000
2299 #define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000 2302 #define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000
2300 #define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000 2303 #define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000
2301 #define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000 2304 #define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000
2302 #define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000 2305 #define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000
2303 #define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000 2306 #define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000
2304 #define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000 2307 #define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000
2305 #define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000 2308 #define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000
2306 #define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000 2309 #define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000
2307 #define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000 2310 #define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000
2308 #define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000 2311 #define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000
2309 #define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000 2312 #define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000
2310 #define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000 2313 #define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000
2311 #define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000 2314 #define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000
2312 #define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000 2315 #define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000
2313 #define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000 2316 #define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000
2314 #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000 2317 #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
2315 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000 2318 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
2316 #endif 2319 #endif
2317 #if defined(CONFIG_P1013) || defined(CONFIG_P1022) 2320 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
2318 #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000 2321 #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
2319 #define MPC85xx_PMUXCR2_USB 0x00150000 2322 #define MPC85xx_PMUXCR2_USB 0x00150000
2320 #endif 2323 #endif
2321 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132) 2324 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
2322 #if defined(CONFIG_BSC9131) 2325 #if defined(CONFIG_BSC9131)
2323 #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000 2326 #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
2324 #define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000 2327 #define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000
2325 #define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000 2328 #define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000
2326 #define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000 2329 #define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000
2327 #define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000 2330 #define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000
2328 #define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000 2331 #define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000
2329 #define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000 2332 #define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000
2330 #define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000 2333 #define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000
2331 #define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000 2334 #define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000
2332 #define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000 2335 #define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000
2333 #define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000 2336 #define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000
2334 #define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000 2337 #define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000
2335 #define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000 2338 #define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000
2336 #define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000 2339 #define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000
2337 #define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000 2340 #define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000
2338 #define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000 2341 #define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000
2339 #define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000 2342 #define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000
2340 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000 2343 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000
2341 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000 2344 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000
2342 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000 2345 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000
2343 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000 2346 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000
2344 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000 2347 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000
2345 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000 2348 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000
2346 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000 2349 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000
2347 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000 2350 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000
2348 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000 2351 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000
2349 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000 2352 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000
2350 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000 2353 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000
2351 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000 2354 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000
2352 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400 2355 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400
2353 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800 2356 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800
2354 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00 2357 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00
2355 #define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100 2358 #define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100
2356 #define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300 2359 #define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300
2357 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040 2360 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040
2358 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0 2361 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0
2359 #define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010 2362 #define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010
2360 #define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020 2363 #define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020
2361 #define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030 2364 #define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030
2362 #define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004 2365 #define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004
2363 #define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001 2366 #define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001
2364 #define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002 2367 #define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
2365 #endif 2368 #endif
2366 u32 pmuxcr3; 2369 u32 pmuxcr3;
2367 #if defined(CONFIG_BSC9131) 2370 #if defined(CONFIG_BSC9131)
2368 #define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000 2371 #define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
2369 #define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000 2372 #define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
2370 #define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000 2373 #define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
2371 #define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000 2374 #define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000
2372 #define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000 2375 #define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000
2373 #define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000 2376 #define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000
2374 #define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000 2377 #define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000
2375 #define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000 2378 #define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000
2376 #define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000 2379 #define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000
2377 #define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000 2380 #define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000
2378 #define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000 2381 #define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000
2379 #define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000 2382 #define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000
2380 #define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000 2383 #define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
2381 #define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000 2384 #define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
2382 #endif 2385 #endif
2383 #ifdef CONFIG_BSC9132 2386 #ifdef CONFIG_BSC9132
2384 #define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00 2387 #define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00
2385 #define MPC85xx_PMUXCR3_UART2_SEL 0x00005000 2388 #define MPC85xx_PMUXCR3_UART2_SEL 0x00005000
2386 #define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000 2389 #define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
2387 #define MPC85xx_PMUXCR3_UART3_SEL 0x40000000 2390 #define MPC85xx_PMUXCR3_UART3_SEL 0x40000000
2388 #endif 2391 #endif
2389 u32 pmuxcr4; 2392 u32 pmuxcr4;
2390 #else 2393 #else
2391 u8 res6[8]; 2394 u8 res6[8];
2392 #endif 2395 #endif
2393 u32 devdisr; /* Device disable control */ 2396 u32 devdisr; /* Device disable control */
2394 #define MPC85xx_DEVDISR_PCI1 0x80000000 2397 #define MPC85xx_DEVDISR_PCI1 0x80000000
2395 #define MPC85xx_DEVDISR_PCI2 0x40000000 2398 #define MPC85xx_DEVDISR_PCI2 0x40000000
2396 #define MPC85xx_DEVDISR_PCIE 0x20000000 2399 #define MPC85xx_DEVDISR_PCIE 0x20000000
2397 #define MPC85xx_DEVDISR_LBC 0x08000000 2400 #define MPC85xx_DEVDISR_LBC 0x08000000
2398 #define MPC85xx_DEVDISR_PCIE2 0x04000000 2401 #define MPC85xx_DEVDISR_PCIE2 0x04000000
2399 #define MPC85xx_DEVDISR_PCIE3 0x02000000 2402 #define MPC85xx_DEVDISR_PCIE3 0x02000000
2400 #define MPC85xx_DEVDISR_SEC 0x01000000 2403 #define MPC85xx_DEVDISR_SEC 0x01000000
2401 #define MPC85xx_DEVDISR_SRIO 0x00080000 2404 #define MPC85xx_DEVDISR_SRIO 0x00080000
2402 #define MPC85xx_DEVDISR_RMSG 0x00040000 2405 #define MPC85xx_DEVDISR_RMSG 0x00040000
2403 #define MPC85xx_DEVDISR_DDR 0x00010000 2406 #define MPC85xx_DEVDISR_DDR 0x00010000
2404 #define MPC85xx_DEVDISR_CPU 0x00008000 2407 #define MPC85xx_DEVDISR_CPU 0x00008000
2405 #define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU 2408 #define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
2406 #define MPC85xx_DEVDISR_TB 0x00004000 2409 #define MPC85xx_DEVDISR_TB 0x00004000
2407 #define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB 2410 #define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
2408 #define MPC85xx_DEVDISR_CPU1 0x00002000 2411 #define MPC85xx_DEVDISR_CPU1 0x00002000
2409 #define MPC85xx_DEVDISR_TB1 0x00001000 2412 #define MPC85xx_DEVDISR_TB1 0x00001000
2410 #define MPC85xx_DEVDISR_DMA 0x00000400 2413 #define MPC85xx_DEVDISR_DMA 0x00000400
2411 #define MPC85xx_DEVDISR_TSEC1 0x00000080 2414 #define MPC85xx_DEVDISR_TSEC1 0x00000080
2412 #define MPC85xx_DEVDISR_TSEC2 0x00000040 2415 #define MPC85xx_DEVDISR_TSEC2 0x00000040
2413 #define MPC85xx_DEVDISR_TSEC3 0x00000020 2416 #define MPC85xx_DEVDISR_TSEC3 0x00000020
2414 #define MPC85xx_DEVDISR_TSEC4 0x00000010 2417 #define MPC85xx_DEVDISR_TSEC4 0x00000010
2415 #define MPC85xx_DEVDISR_I2C 0x00000004 2418 #define MPC85xx_DEVDISR_I2C 0x00000004
2416 #define MPC85xx_DEVDISR_DUART 0x00000002 2419 #define MPC85xx_DEVDISR_DUART 0x00000002
2417 u8 res7[12]; 2420 u8 res7[12];
2418 u32 powmgtcsr; /* Power management status & control */ 2421 u32 powmgtcsr; /* Power management status & control */
2419 u8 res8[12]; 2422 u8 res8[12];
2420 u32 mcpsumr; /* Machine check summary */ 2423 u32 mcpsumr; /* Machine check summary */
2421 u8 res9[12]; 2424 u8 res9[12];
2422 u32 pvr; /* Processor version */ 2425 u32 pvr; /* Processor version */
2423 u32 svr; /* System version */ 2426 u32 svr; /* System version */
2424 u8 res10[8]; 2427 u8 res10[8];
2425 u32 rstcr; /* Reset control */ 2428 u32 rstcr; /* Reset control */
2426 #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569) 2429 #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
2427 u8 res11a[76]; 2430 u8 res11a[76];
2428 par_io_t qe_par_io[7]; 2431 par_io_t qe_par_io[7];
2429 u8 res11b[1600]; 2432 u8 res11b[1600];
2430 #elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) 2433 #elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
2431 u8 res11a[12]; 2434 u8 res11a[12];
2432 u32 iovselsr; 2435 u32 iovselsr;
2433 u8 res11b[60]; 2436 u8 res11b[60];
2434 par_io_t qe_par_io[3]; 2437 par_io_t qe_par_io[3];
2435 u8 res11c[1496]; 2438 u8 res11c[1496];
2436 #else 2439 #else
2437 u8 res11a[1868]; 2440 u8 res11a[1868];
2438 #endif 2441 #endif
2439 u32 clkdvdr; /* Clock Divide register */ 2442 u32 clkdvdr; /* Clock Divide register */
2440 u8 res12[1532]; 2443 u8 res12[1532];
2441 u32 clkocr; /* Clock out select */ 2444 u32 clkocr; /* Clock out select */
2442 u8 res13[12]; 2445 u8 res13[12];
2443 u32 ddrdllcr; /* DDR DLL control */ 2446 u32 ddrdllcr; /* DDR DLL control */
2444 u8 res14[12]; 2447 u8 res14[12];
2445 u32 lbcdllcr; /* LBC DLL control */ 2448 u32 lbcdllcr; /* LBC DLL control */
2446 #if defined(CONFIG_BSC9131) 2449 #if defined(CONFIG_BSC9131)
2447 u8 res15[12]; 2450 u8 res15[12];
2448 u32 halt_req_mask; 2451 u32 halt_req_mask;
2449 #define HALTED_TO_HALT_REQ_MASK_0 0x80000000 2452 #define HALTED_TO_HALT_REQ_MASK_0 0x80000000
2450 u8 res18[232]; 2453 u8 res18[232];
2451 #else 2454 #else
2452 u8 res15[248]; 2455 u8 res15[248];
2453 #endif 2456 #endif
2454 u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */ 2457 u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */
2455 u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */ 2458 u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */
2456 u32 ddrioovcr; /* DDR IO Override Control */ 2459 u32 ddrioovcr; /* DDR IO Override Control */
2457 u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */ 2460 u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */
2458 u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */ 2461 u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */
2459 u8 res16[52]; 2462 u8 res16[52];
2460 u32 sdhcdcr; /* SDHC debug control register */ 2463 u32 sdhcdcr; /* SDHC debug control register */
2461 u8 res17[61592]; 2464 u8 res17[61592];
2462 } ccsr_gur_t; 2465 } ccsr_gur_t;
2463 #endif 2466 #endif
2464 2467
2465 #define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */ 2468 #define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */
2466 2469
2467 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 2470 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
2468 #define MAX_SERDES 4 2471 #define MAX_SERDES 4
2469 #define SRDS_MAX_LANES 8 2472 #define SRDS_MAX_LANES 8
2470 #define SRDS_MAX_BANK 2 2473 #define SRDS_MAX_BANK 2
2471 typedef struct serdes_corenet { 2474 typedef struct serdes_corenet {
2472 struct { 2475 struct {
2473 u32 rstctl; /* Reset Control Register */ 2476 u32 rstctl; /* Reset Control Register */
2474 #define SRDS_RSTCTL_RST 0x80000000 2477 #define SRDS_RSTCTL_RST 0x80000000
2475 #define SRDS_RSTCTL_RSTDONE 0x40000000 2478 #define SRDS_RSTCTL_RSTDONE 0x40000000
2476 #define SRDS_RSTCTL_RSTERR 0x20000000 2479 #define SRDS_RSTCTL_RSTERR 0x20000000
2477 #define SRDS_RSTCTL_SWRST 0x10000000 2480 #define SRDS_RSTCTL_SWRST 0x10000000
2478 #define SRDS_RSTCTL_SDEN 0x00000020 2481 #define SRDS_RSTCTL_SDEN 0x00000020
2479 #define SRDS_RSTCTL_SDRST_B 0x00000040 2482 #define SRDS_RSTCTL_SDRST_B 0x00000040
2480 #define SRDS_RSTCTL_PLLRST_B 0x00000080 2483 #define SRDS_RSTCTL_PLLRST_B 0x00000080
2481 u32 pllcr0; /* PLL Control Register 0 */ 2484 u32 pllcr0; /* PLL Control Register 0 */
2482 #define SRDS_PLLCR0_POFF 0x80000000 2485 #define SRDS_PLLCR0_POFF 0x80000000
2483 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 2486 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2484 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 2487 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2485 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 2488 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2486 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 2489 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2487 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 2490 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2488 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 2491 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2489 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 2492 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
2490 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 2493 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
2491 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 2494 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2492 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 2495 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
2493 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 2496 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
2494 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 2497 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
2495 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 2498 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
2496 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 2499 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
2497 u32 pllcr1; /* PLL Control Register 1 */ 2500 u32 pllcr1; /* PLL Control Register 1 */
2498 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 2501 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2499 u32 res_0c; /* 0x00c */ 2502 u32 res_0c; /* 0x00c */
2500 u32 pllcr3; 2503 u32 pllcr3;
2501 u32 pllcr4; 2504 u32 pllcr4;
2502 u8 res_18[0x20-0x18]; 2505 u8 res_18[0x20-0x18];
2503 } bank[2]; 2506 } bank[2];
2504 u8 res_40[0x90-0x40]; 2507 u8 res_40[0x90-0x40];
2505 u32 srdstcalcr; /* 0x90 TX Calibration Control */ 2508 u32 srdstcalcr; /* 0x90 TX Calibration Control */
2506 u8 res_94[0xa0-0x94]; 2509 u8 res_94[0xa0-0x94];
2507 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 2510 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
2508 u8 res_a4[0xb0-0xa4]; 2511 u8 res_a4[0xb0-0xa4];
2509 u32 srdsgr0; /* 0xb0 General Register 0 */ 2512 u32 srdsgr0; /* 0xb0 General Register 0 */
2510 u8 res_b4[0xe0-0xb4]; 2513 u8 res_b4[0xe0-0xb4];
2511 u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ 2514 u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
2512 u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ 2515 u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
2513 u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ 2516 u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
2514 u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ 2517 u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
2515 u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ 2518 u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
2516 u8 res_f4[0x100-0xf4]; 2519 u8 res_f4[0x100-0xf4];
2517 struct { 2520 struct {
2518 u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ 2521 u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
2519 u8 res_104[0x120-0x104]; 2522 u8 res_104[0x120-0x104];
2520 } srdslnpssr[8]; 2523 } srdslnpssr[8];
2521 u8 res_200[0x800-0x200]; 2524 u8 res_200[0x800-0x200];
2522 struct { 2525 struct {
2523 u32 gcr0; /* 0x800 General Control Register 0 */ 2526 u32 gcr0; /* 0x800 General Control Register 0 */
2524 u32 gcr1; /* 0x804 General Control Register 1 */ 2527 u32 gcr1; /* 0x804 General Control Register 1 */
2525 u32 gcr2; /* 0x808 General Control Register 2 */ 2528 u32 gcr2; /* 0x808 General Control Register 2 */
2526 u32 res_80c; 2529 u32 res_80c;
2527 u32 recr0; /* 0x810 Receive Equalization Control */ 2530 u32 recr0; /* 0x810 Receive Equalization Control */
2528 u32 res_814; 2531 u32 res_814;
2529 u32 tecr0; /* 0x818 Transmit Equalization Control */ 2532 u32 tecr0; /* 0x818 Transmit Equalization Control */
2530 u32 res_81c; 2533 u32 res_81c;
2531 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 2534 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
2532 u8 res_824[0x840-0x824]; 2535 u8 res_824[0x840-0x824];
2533 } lane[8]; /* Lane A, B, C, D, E, F, G, H */ 2536 } lane[8]; /* Lane A, B, C, D, E, F, G, H */
2534 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ 2537 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
2535 } serdes_corenet_t; 2538 } serdes_corenet_t;
2536 2539
2537 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 2540 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
2538 2541
2539 #define SRDS_MAX_LANES 18 2542 #define SRDS_MAX_LANES 18
2540 #define SRDS_MAX_BANK 3 2543 #define SRDS_MAX_BANK 3
2541 typedef struct serdes_corenet { 2544 typedef struct serdes_corenet {
2542 struct { 2545 struct {
2543 u32 rstctl; /* Reset Control Register */ 2546 u32 rstctl; /* Reset Control Register */
2544 #define SRDS_RSTCTL_RST 0x80000000 2547 #define SRDS_RSTCTL_RST 0x80000000
2545 #define SRDS_RSTCTL_RSTDONE 0x40000000 2548 #define SRDS_RSTCTL_RSTDONE 0x40000000
2546 #define SRDS_RSTCTL_RSTERR 0x20000000 2549 #define SRDS_RSTCTL_RSTERR 0x20000000
2547 #define SRDS_RSTCTL_SDPD 0x00000020 2550 #define SRDS_RSTCTL_SDPD 0x00000020
2548 u32 pllcr0; /* PLL Control Register 0 */ 2551 u32 pllcr0; /* PLL Control Register 0 */
2549 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 2552 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2550 #define SRDS_PLLCR0_PVCOCNT_EN 0x02000000 2553 #define SRDS_PLLCR0_PVCOCNT_EN 0x02000000
2551 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 2554 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2552 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 2555 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2553 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 2556 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2554 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 2557 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2555 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 2558 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2556 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000 2559 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
2557 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 2560 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2558 #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000 2561 #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
2559 u32 pllcr1; /* PLL Control Register 1 */ 2562 u32 pllcr1; /* PLL Control Register 1 */
2560 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 2563 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2561 u32 res[5]; 2564 u32 res[5];
2562 } bank[3]; 2565 } bank[3];
2563 u32 res1[12]; 2566 u32 res1[12];
2564 u32 srdstcalcr; /* TX Calibration Control */ 2567 u32 srdstcalcr; /* TX Calibration Control */
2565 u32 res2[3]; 2568 u32 res2[3];
2566 u32 srdsrcalcr; /* RX Calibration Control */ 2569 u32 srdsrcalcr; /* RX Calibration Control */
2567 u32 res3[3]; 2570 u32 res3[3];
2568 u32 srdsgr0; /* General Register 0 */ 2571 u32 srdsgr0; /* General Register 0 */
2569 u32 res4[11]; 2572 u32 res4[11];
2570 u32 srdspccr0; /* Protocol Converter Config 0 */ 2573 u32 srdspccr0; /* Protocol Converter Config 0 */
2571 u32 srdspccr1; /* Protocol Converter Config 1 */ 2574 u32 srdspccr1; /* Protocol Converter Config 1 */
2572 u32 srdspccr2; /* Protocol Converter Config 2 */ 2575 u32 srdspccr2; /* Protocol Converter Config 2 */
2573 #define SRDS_PCCR2_RST_XGMII1 0x00800000 2576 #define SRDS_PCCR2_RST_XGMII1 0x00800000
2574 #define SRDS_PCCR2_RST_XGMII2 0x00400000 2577 #define SRDS_PCCR2_RST_XGMII2 0x00400000
2575 u32 res5[197]; 2578 u32 res5[197];
2576 struct serdes_lane { 2579 struct serdes_lane {
2577 u32 gcr0; /* General Control Register 0 */ 2580 u32 gcr0; /* General Control Register 0 */
2578 #define SRDS_GCR0_RRST 0x00400000 2581 #define SRDS_GCR0_RRST 0x00400000
2579 #define SRDS_GCR0_1STLANE 0x00010000 2582 #define SRDS_GCR0_1STLANE 0x00010000
2580 #define SRDS_GCR0_UOTHL 0x00100000 2583 #define SRDS_GCR0_UOTHL 0x00100000
2581 u32 gcr1; /* General Control Register 1 */ 2584 u32 gcr1; /* General Control Register 1 */
2582 #define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000 2585 #define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
2583 #define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000 2586 #define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
2584 #define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000 2587 #define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000
2585 #define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000 2588 #define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000
2586 #define SRDS_GCR1_OPAD_CTL 0x04000000 2589 #define SRDS_GCR1_OPAD_CTL 0x04000000
2587 u32 res1[4]; 2590 u32 res1[4];
2588 u32 tecr0; /* TX Equalization Control Reg 0 */ 2591 u32 tecr0; /* TX Equalization Control Reg 0 */
2589 #define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000 2592 #define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000
2590 #define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000 2593 #define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
2591 u32 res3; 2594 u32 res3;
2592 u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */ 2595 u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
2593 #define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000 2596 #define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
2594 #define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000 2597 #define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000
2595 #define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000 2598 #define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000
2596 #define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000 2599 #define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
2597 #define SRDS_TTLCR0_PM_DIS 0x00004000 2600 #define SRDS_TTLCR0_PM_DIS 0x00004000
2598 #define SRDS_TTLCR0_FREQOVD_EN 0x00000001 2601 #define SRDS_TTLCR0_FREQOVD_EN 0x00000001
2599 u32 res4[7]; 2602 u32 res4[7];
2600 } lane[24]; 2603 } lane[24];
2601 u32 res6[384]; 2604 u32 res6[384];
2602 } serdes_corenet_t; 2605 } serdes_corenet_t;
2603 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 2606 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
2604 2607
2605 enum { 2608 enum {
2606 FSL_SRDS_B1_LANE_A = 0, 2609 FSL_SRDS_B1_LANE_A = 0,
2607 FSL_SRDS_B1_LANE_B = 1, 2610 FSL_SRDS_B1_LANE_B = 1,
2608 FSL_SRDS_B1_LANE_C = 2, 2611 FSL_SRDS_B1_LANE_C = 2,
2609 FSL_SRDS_B1_LANE_D = 3, 2612 FSL_SRDS_B1_LANE_D = 3,
2610 FSL_SRDS_B1_LANE_E = 4, 2613 FSL_SRDS_B1_LANE_E = 4,
2611 FSL_SRDS_B1_LANE_F = 5, 2614 FSL_SRDS_B1_LANE_F = 5,
2612 FSL_SRDS_B1_LANE_G = 6, 2615 FSL_SRDS_B1_LANE_G = 6,
2613 FSL_SRDS_B1_LANE_H = 7, 2616 FSL_SRDS_B1_LANE_H = 7,
2614 FSL_SRDS_B1_LANE_I = 8, 2617 FSL_SRDS_B1_LANE_I = 8,
2615 FSL_SRDS_B1_LANE_J = 9, 2618 FSL_SRDS_B1_LANE_J = 9,
2616 FSL_SRDS_B2_LANE_A = 16, 2619 FSL_SRDS_B2_LANE_A = 16,
2617 FSL_SRDS_B2_LANE_B = 17, 2620 FSL_SRDS_B2_LANE_B = 17,
2618 FSL_SRDS_B2_LANE_C = 18, 2621 FSL_SRDS_B2_LANE_C = 18,
2619 FSL_SRDS_B2_LANE_D = 19, 2622 FSL_SRDS_B2_LANE_D = 19,
2620 FSL_SRDS_B3_LANE_A = 20, 2623 FSL_SRDS_B3_LANE_A = 20,
2621 FSL_SRDS_B3_LANE_B = 21, 2624 FSL_SRDS_B3_LANE_B = 21,
2622 FSL_SRDS_B3_LANE_C = 22, 2625 FSL_SRDS_B3_LANE_C = 22,
2623 FSL_SRDS_B3_LANE_D = 23, 2626 FSL_SRDS_B3_LANE_D = 23,
2624 }; 2627 };
2625 2628
2626 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ 2629 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
2627 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 2630 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
2628 typedef struct ccsr_sec { 2631 typedef struct ccsr_sec {
2629 u32 res0; 2632 u32 res0;
2630 u32 mcfgr; /* Master CFG Register */ 2633 u32 mcfgr; /* Master CFG Register */
2631 u8 res1[0x8]; 2634 u8 res1[0x8];
2632 struct { 2635 struct {
2633 u32 ms; /* Job Ring LIODN Register, MS */ 2636 u32 ms; /* Job Ring LIODN Register, MS */
2634 u32 ls; /* Job Ring LIODN Register, LS */ 2637 u32 ls; /* Job Ring LIODN Register, LS */
2635 } jrliodnr[4]; 2638 } jrliodnr[4];
2636 u8 res2[0x30]; 2639 u8 res2[0x30];
2637 struct { 2640 struct {
2638 u32 ms; /* RTIC LIODN Register, MS */ 2641 u32 ms; /* RTIC LIODN Register, MS */
2639 u32 ls; /* RTIC LIODN Register, LS */ 2642 u32 ls; /* RTIC LIODN Register, LS */
2640 } rticliodnr[4]; 2643 } rticliodnr[4];
2641 u8 res3[0x1c]; 2644 u8 res3[0x1c];
2642 u32 decorr; /* DECO Request Register */ 2645 u32 decorr; /* DECO Request Register */
2643 struct { 2646 struct {
2644 u32 ms; /* DECO LIODN Register, MS */ 2647 u32 ms; /* DECO LIODN Register, MS */
2645 u32 ls; /* DECO LIODN Register, LS */ 2648 u32 ls; /* DECO LIODN Register, LS */
2646 } decoliodnr[8]; 2649 } decoliodnr[8];
2647 u8 res4[0x40]; 2650 u8 res4[0x40];
2648 u32 dar; /* DECO Avail Register */ 2651 u32 dar; /* DECO Avail Register */
2649 u32 drr; /* DECO Reset Register */ 2652 u32 drr; /* DECO Reset Register */
2650 u8 res5[0xe78]; 2653 u8 res5[0xe78];
2651 u32 crnr_ms; /* CHA Revision Number Register, MS */ 2654 u32 crnr_ms; /* CHA Revision Number Register, MS */
2652 u32 crnr_ls; /* CHA Revision Number Register, LS */ 2655 u32 crnr_ls; /* CHA Revision Number Register, LS */
2653 u32 ctpr_ms; /* Compile Time Parameters Register, MS */ 2656 u32 ctpr_ms; /* Compile Time Parameters Register, MS */
2654 u32 ctpr_ls; /* Compile Time Parameters Register, LS */ 2657 u32 ctpr_ls; /* Compile Time Parameters Register, LS */
2655 u8 res6[0x10]; 2658 u8 res6[0x10];
2656 u32 far_ms; /* Fault Address Register, MS */ 2659 u32 far_ms; /* Fault Address Register, MS */
2657 u32 far_ls; /* Fault Address Register, LS */ 2660 u32 far_ls; /* Fault Address Register, LS */
2658 u32 falr; /* Fault Address LIODN Register */ 2661 u32 falr; /* Fault Address LIODN Register */
2659 u32 fadr; /* Fault Address Detail Register */ 2662 u32 fadr; /* Fault Address Detail Register */
2660 u8 res7[0x4]; 2663 u8 res7[0x4];
2661 u32 csta; /* CAAM Status Register */ 2664 u32 csta; /* CAAM Status Register */
2662 u8 res8[0x8]; 2665 u8 res8[0x8];
2663 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ 2666 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
2664 u32 ccbvid; /* CHA Cluster Block Version ID Register */ 2667 u32 ccbvid; /* CHA Cluster Block Version ID Register */
2665 u32 chavid_ms; /* CHA Version ID Register, MS */ 2668 u32 chavid_ms; /* CHA Version ID Register, MS */
2666 u32 chavid_ls; /* CHA Version ID Register, LS */ 2669 u32 chavid_ls; /* CHA Version ID Register, LS */
2667 u32 chanum_ms; /* CHA Number Register, MS */ 2670 u32 chanum_ms; /* CHA Number Register, MS */
2668 u32 chanum_ls; /* CHA Number Register, LS */ 2671 u32 chanum_ls; /* CHA Number Register, LS */
2669 u32 secvid_ms; /* SEC Version ID Register, MS */ 2672 u32 secvid_ms; /* SEC Version ID Register, MS */
2670 u32 secvid_ls; /* SEC Version ID Register, LS */ 2673 u32 secvid_ls; /* SEC Version ID Register, LS */
2671 u8 res9[0x6020]; 2674 u8 res9[0x6020];
2672 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ 2675 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
2673 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ 2676 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
2674 u8 res10[0x8fd8]; 2677 u8 res10[0x8fd8];
2675 } ccsr_sec_t; 2678 } ccsr_sec_t;
2676 2679
2677 #define SEC_CTPR_MS_AXI_LIODN 0x08000000 2680 #define SEC_CTPR_MS_AXI_LIODN 0x08000000
2678 #define SEC_CTPR_MS_QI 0x02000000 2681 #define SEC_CTPR_MS_QI 0x02000000
2679 #define SEC_RVID_MA 0x0f000000 2682 #define SEC_RVID_MA 0x0f000000
2680 #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000 2683 #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
2681 #define SEC_CHANUM_MS_JRNUM_SHIFT 28 2684 #define SEC_CHANUM_MS_JRNUM_SHIFT 28
2682 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 2685 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
2683 #define SEC_CHANUM_MS_DECONUM_SHIFT 24 2686 #define SEC_CHANUM_MS_DECONUM_SHIFT 24
2684 #define SEC_SECVID_MS_IPID_MASK 0xffff0000 2687 #define SEC_SECVID_MS_IPID_MASK 0xffff0000
2685 #define SEC_SECVID_MS_IPID_SHIFT 16 2688 #define SEC_SECVID_MS_IPID_SHIFT 16
2686 #define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00 2689 #define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
2687 #define SEC_SECVID_MS_MAJ_REV_SHIFT 8 2690 #define SEC_SECVID_MS_MAJ_REV_SHIFT 8
2688 #define SEC_CCBVID_ERA_MASK 0xff000000 2691 #define SEC_CCBVID_ERA_MASK 0xff000000
2689 #define SEC_CCBVID_ERA_SHIFT 24 2692 #define SEC_CCBVID_ERA_SHIFT 24
2690 #endif 2693 #endif
2691 2694
2692 typedef struct ccsr_qman { 2695 typedef struct ccsr_qman {
2693 #ifdef CONFIG_SYS_FSL_QMAN_V3 2696 #ifdef CONFIG_SYS_FSL_QMAN_V3
2694 u8 res0[0x200]; 2697 u8 res0[0x200];
2695 #else 2698 #else
2696 struct { 2699 struct {
2697 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ 2700 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
2698 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ 2701 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
2699 u32 res; 2702 u32 res;
2700 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */ 2703 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */
2701 } qcsp[32]; 2704 } qcsp[32];
2702 #endif 2705 #endif
2703 /* Not actually reserved, but irrelevant to u-boot */ 2706 /* Not actually reserved, but irrelevant to u-boot */
2704 u8 res[0xbf8 - 0x200]; 2707 u8 res[0xbf8 - 0x200];
2705 u32 ip_rev_1; 2708 u32 ip_rev_1;
2706 u32 ip_rev_2; 2709 u32 ip_rev_2;
2707 u32 fqd_bare; /* FQD Extended Base Addr Register */ 2710 u32 fqd_bare; /* FQD Extended Base Addr Register */
2708 u32 fqd_bar; /* FQD Base Addr Register */ 2711 u32 fqd_bar; /* FQD Base Addr Register */
2709 u8 res1[0x8]; 2712 u8 res1[0x8];
2710 u32 fqd_ar; /* FQD Attributes Register */ 2713 u32 fqd_ar; /* FQD Attributes Register */
2711 u8 res2[0xc]; 2714 u8 res2[0xc];
2712 u32 pfdr_bare; /* PFDR Extended Base Addr Register */ 2715 u32 pfdr_bare; /* PFDR Extended Base Addr Register */
2713 u32 pfdr_bar; /* PFDR Base Addr Register */ 2716 u32 pfdr_bar; /* PFDR Base Addr Register */
2714 u8 res3[0x8]; 2717 u8 res3[0x8];
2715 u32 pfdr_ar; /* PFDR Attributes Register */ 2718 u32 pfdr_ar; /* PFDR Attributes Register */
2716 u8 res4[0x4c]; 2719 u8 res4[0x4c];
2717 u32 qcsp_bare; /* QCSP Extended Base Addr Register */ 2720 u32 qcsp_bare; /* QCSP Extended Base Addr Register */
2718 u32 qcsp_bar; /* QCSP Base Addr Register */ 2721 u32 qcsp_bar; /* QCSP Base Addr Register */
2719 u8 res5[0x78]; 2722 u8 res5[0x78];
2720 u32 ci_sched_cfg; /* Initiator Scheduling Configuration */ 2723 u32 ci_sched_cfg; /* Initiator Scheduling Configuration */
2721 u32 srcidr; /* Source ID Register */ 2724 u32 srcidr; /* Source ID Register */
2722 u32 liodnr; /* LIODN Register */ 2725 u32 liodnr; /* LIODN Register */
2723 u8 res6[4]; 2726 u8 res6[4];
2724 u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */ 2727 u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
2725 u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */ 2728 u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
2726 u8 res7[0x2e8]; 2729 u8 res7[0x2e8];
2727 #ifdef CONFIG_SYS_FSL_QMAN_V3 2730 #ifdef CONFIG_SYS_FSL_QMAN_V3
2728 struct { 2731 struct {
2729 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ 2732 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
2730 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ 2733 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
2731 u32 res; 2734 u32 res;
2732 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/ 2735 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/
2733 } qcsp[50]; 2736 } qcsp[50];
2734 #endif 2737 #endif
2735 } ccsr_qman_t; 2738 } ccsr_qman_t;
2736 2739
2737 typedef struct ccsr_bman { 2740 typedef struct ccsr_bman {
2738 /* Not actually reserved, but irrelevant to u-boot */ 2741 /* Not actually reserved, but irrelevant to u-boot */
2739 u8 res[0xbf8]; 2742 u8 res[0xbf8];
2740 u32 ip_rev_1; 2743 u32 ip_rev_1;
2741 u32 ip_rev_2; 2744 u32 ip_rev_2;
2742 u32 fbpr_bare; /* FBPR Extended Base Addr Register */ 2745 u32 fbpr_bare; /* FBPR Extended Base Addr Register */
2743 u32 fbpr_bar; /* FBPR Base Addr Register */ 2746 u32 fbpr_bar; /* FBPR Base Addr Register */
2744 u8 res1[0x8]; 2747 u8 res1[0x8];
2745 u32 fbpr_ar; /* FBPR Attributes Register */ 2748 u32 fbpr_ar; /* FBPR Attributes Register */
2746 u8 res2[0xf0]; 2749 u8 res2[0xf0];
2747 u32 srcidr; /* Source ID Register */ 2750 u32 srcidr; /* Source ID Register */
2748 u32 liodnr; /* LIODN Register */ 2751 u32 liodnr; /* LIODN Register */
2749 u8 res7[0x2f4]; 2752 u8 res7[0x2f4];
2750 } ccsr_bman_t; 2753 } ccsr_bman_t;
2751 2754
2752 typedef struct ccsr_pme { 2755 typedef struct ccsr_pme {
2753 u8 res0[0x804]; 2756 u8 res0[0x804];
2754 u32 liodnbr; /* LIODN Base Register */ 2757 u32 liodnbr; /* LIODN Base Register */
2755 u8 res1[0x1f8]; 2758 u8 res1[0x1f8];
2756 u32 srcidr; /* Source ID Register */ 2759 u32 srcidr; /* Source ID Register */
2757 u8 res2[8]; 2760 u8 res2[8];
2758 u32 liodnr; /* LIODN Register */ 2761 u32 liodnr; /* LIODN Register */
2759 u8 res3[0x1e8]; 2762 u8 res3[0x1e8];
2760 u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/ 2763 u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/
2761 u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/ 2764 u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/
2762 u8 res4[0x400]; 2765 u8 res4[0x400];
2763 } ccsr_pme_t; 2766 } ccsr_pme_t;
2764 2767
2765 #ifdef CONFIG_SYS_FSL_RAID_ENGINE 2768 #ifdef CONFIG_SYS_FSL_RAID_ENGINE
2766 struct ccsr_raide { 2769 struct ccsr_raide {
2767 u8 res0[0x543]; 2770 u8 res0[0x543];
2768 u32 liodnbr; /* LIODN Base Register */ 2771 u32 liodnbr; /* LIODN Base Register */
2769 u8 res1[0xab8]; 2772 u8 res1[0xab8];
2770 struct { 2773 struct {
2771 struct { 2774 struct {
2772 u32 cfg0; /* cfg register 0 */ 2775 u32 cfg0; /* cfg register 0 */
2773 u32 cfg1; /* cfg register 1 */ 2776 u32 cfg1; /* cfg register 1 */
2774 u8 res1[0x3f8]; 2777 u8 res1[0x3f8];
2775 } ring[2]; 2778 } ring[2];
2776 u8 res[0x800]; 2779 u8 res[0x800];
2777 } jq[2]; 2780 } jq[2];
2778 }; 2781 };
2779 #endif 2782 #endif
2780 2783
2781 #ifdef CONFIG_SYS_DPAA_RMAN 2784 #ifdef CONFIG_SYS_DPAA_RMAN
2782 struct ccsr_rman { 2785 struct ccsr_rman {
2783 u8 res0[0xf64]; 2786 u8 res0[0xf64];
2784 u32 mmliodnbr; /* Message Manager LIODN Base Register */ 2787 u32 mmliodnbr; /* Message Manager LIODN Base Register */
2785 u32 mmitar; /* RMAN Inbound Translation Address Register */ 2788 u32 mmitar; /* RMAN Inbound Translation Address Register */
2786 u32 mmitdr; /* RMAN Inbound Translation Data Register */ 2789 u32 mmitdr; /* RMAN Inbound Translation Data Register */
2787 u8 res4[0x1f090]; 2790 u8 res4[0x1f090];
2788 }; 2791 };
2789 #endif 2792 #endif
2790 2793
2791 #ifdef CONFIG_SYS_PMAN 2794 #ifdef CONFIG_SYS_PMAN
2792 struct ccsr_pman { 2795 struct ccsr_pman {
2793 u8 res_00[0x40]; 2796 u8 res_00[0x40];
2794 u32 poes1; /* PMAN Operation Error Status Register 1 */ 2797 u32 poes1; /* PMAN Operation Error Status Register 1 */
2795 u32 poes2; /* PMAN Operation Error Status Register 2 */ 2798 u32 poes2; /* PMAN Operation Error Status Register 2 */
2796 u32 poeah; /* PMAN Operation Error Address High */ 2799 u32 poeah; /* PMAN Operation Error Address High */
2797 u32 poeal; /* PMAN Operation Error Address Low */ 2800 u32 poeal; /* PMAN Operation Error Address Low */
2798 u8 res_50[0x50]; 2801 u8 res_50[0x50];
2799 u32 pr1; /* PMAN Revision Register 1 */ 2802 u32 pr1; /* PMAN Revision Register 1 */
2800 u32 pr2; /* PMAN Revision Register 2 */ 2803 u32 pr2; /* PMAN Revision Register 2 */
2801 u8 res_a8[0x8]; 2804 u8 res_a8[0x8];
2802 u32 pcap; /* PMAN Capabilities Register */ 2805 u32 pcap; /* PMAN Capabilities Register */
2803 u8 res_b4[0xc]; 2806 u8 res_b4[0xc];
2804 u32 pc1; /* PMAN Control Register 1 */ 2807 u32 pc1; /* PMAN Control Register 1 */
2805 u32 pc2; /* PMAN Control Register 2 */ 2808 u32 pc2; /* PMAN Control Register 2 */
2806 u32 pc3; /* PMAN Control Register 3 */ 2809 u32 pc3; /* PMAN Control Register 3 */
2807 u32 pc4; /* PMAN Control Register 4 */ 2810 u32 pc4; /* PMAN Control Register 4 */
2808 u32 pc5; /* PMAN Control Register 5 */ 2811 u32 pc5; /* PMAN Control Register 5 */
2809 u32 pc6; /* PMAN Control Register 6 */ 2812 u32 pc6; /* PMAN Control Register 6 */
2810 u8 res_d8[0x8]; 2813 u8 res_d8[0x8];
2811 u32 ppa1; /* PMAN Prefetch Attributes Register 1 */ 2814 u32 ppa1; /* PMAN Prefetch Attributes Register 1 */
2812 u32 ppa2; /* PMAN Prefetch Attributes Register 2 */ 2815 u32 ppa2; /* PMAN Prefetch Attributes Register 2 */
2813 u8 res_e8[0x8]; 2816 u8 res_e8[0x8];
2814 u32 pics; /* PMAN Interrupt Control and Status */ 2817 u32 pics; /* PMAN Interrupt Control and Status */
2815 u8 res_f4[0xf0c]; 2818 u8 res_f4[0xf0c];
2816 }; 2819 };
2817 #endif 2820 #endif
2818 2821
2819 #ifdef CONFIG_FSL_CORENET 2822 #ifdef CONFIG_FSL_CORENET
2820 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 2823 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
2821 #ifdef CONFIG_SYS_PMAN 2824 #ifdef CONFIG_SYS_PMAN
2822 #define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000 2825 #define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
2823 #define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000 2826 #define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
2824 #define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000 2827 #define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
2825 #endif 2828 #endif
2826 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000 2829 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000
2827 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000 2830 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
2828 #define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000 2831 #define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
2829 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 2832 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
2830 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 2833 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
2831 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 2834 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
2832 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000 2835 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
2833 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 2836 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
2834 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000 2837 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
2835 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000 2838 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
2836 #define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000 2839 #define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
2837 #define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET 2840 #define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
2838 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 2841 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
2839 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 2842 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
2840 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 2843 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
2841 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000 2844 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
2842 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 2845 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
2843 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 2846 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
2844 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\ 2847 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
2845 && !defined(CONFIG_PPC_B4420) 2848 && !defined(CONFIG_PPC_B4420)
2846 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000 2849 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
2847 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000 2850 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
2848 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000 2851 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
2849 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000 2852 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
2850 #else 2853 #else
2851 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 2854 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
2852 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000 2855 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
2853 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000 2856 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
2854 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000 2857 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
2855 #endif 2858 #endif
2856 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000 2859 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
2857 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000 2860 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
2858 #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000 2861 #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
2859 #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100 2862 #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
2860 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000 2863 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
2861 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000 2864 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
2862 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 2865 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
2863 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000 2866 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
2864 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000 2867 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
2865 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000 2868 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
2866 #define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000 2869 #define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
2867 #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000 2870 #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
2868 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000 2871 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
2869 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000 2872 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
2870 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000 2873 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
2871 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000 2874 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
2872 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000 2875 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
2873 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000 2876 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
2874 #define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000 2877 #define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
2875 #define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000 2878 #define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
2876 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000 2879 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
2877 #define CONFIG_SYS_FSL_FM2_OFFSET 0x500000 2880 #define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
2878 #define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000 2881 #define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
2879 #define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000 2882 #define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
2880 #define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000 2883 #define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
2881 #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000 2884 #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
2882 #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000 2885 #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
2883 #define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000 2886 #define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
2884 #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000 2887 #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
2885 #define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000 2888 #define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
2886 #define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000 2889 #define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
2887 #else 2890 #else
2888 #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000 2891 #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
2889 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000 2892 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
2890 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000 2893 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
2891 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000 2894 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
2892 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000 2895 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
2893 #define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000 2896 #define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
2894 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000 2897 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
2895 #define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000 2898 #define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
2896 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000 2899 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
2897 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000 2900 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
2898 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000 2901 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
2899 #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) 2902 #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
2900 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000 2903 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
2901 #else 2904 #else
2902 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000 2905 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
2903 #endif 2906 #endif
2904 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000 2907 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
2905 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000 2908 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
2906 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000 2909 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
2907 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000 2910 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
2908 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 2911 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
2909 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 2912 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
2910 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000 2913 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000
2911 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000 2914 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
2912 #ifdef CONFIG_TSECV2 2915 #ifdef CONFIG_TSECV2
2913 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000 2916 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000
2914 #elif defined(CONFIG_TSECV2_1) 2917 #elif defined(CONFIG_TSECV2_1)
2915 #define CONFIG_SYS_TSEC1_OFFSET 0x10000 2918 #define CONFIG_SYS_TSEC1_OFFSET 0x10000
2916 #else 2919 #else
2917 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 2920 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
2918 #endif 2921 #endif
2919 #define CONFIG_SYS_MDIO1_OFFSET 0x24000 2922 #define CONFIG_SYS_MDIO1_OFFSET 0x24000
2920 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 2923 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
2921 #if defined(CONFIG_PPC_C29X) 2924 #if defined(CONFIG_PPC_C29X)
2922 #define CONFIG_SYS_FSL_SEC_OFFSET 0x80000 2925 #define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
2923 #else 2926 #else
2924 #define CONFIG_SYS_FSL_SEC_OFFSET 0x30000 2927 #define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
2925 #endif 2928 #endif
2926 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 2929 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
2927 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 2930 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
2928 #define CONFIG_SYS_SNVS_OFFSET 0xE6000 2931 #define CONFIG_SYS_SNVS_OFFSET 0xE6000
2929 #define CONFIG_SYS_SFP_OFFSET 0xE7000 2932 #define CONFIG_SYS_SFP_OFFSET 0xE7000
2930 #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000 2933 #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
2931 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000 2934 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
2932 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000 2935 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
2933 #define CONFIG_SYS_FSL_FM1_OFFSET 0x100000 2936 #define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
2934 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000 2937 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
2935 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000 2938 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
2936 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000 2939 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
2937 #endif 2940 #endif
2938 2941
2939 #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 2942 #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
2940 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 2943 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
2941 #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000 2944 #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
2942 2945
2943 #if defined(CONFIG_BSC9132) 2946 #if defined(CONFIG_BSC9132)
2944 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000 2947 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
2945 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \ 2948 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
2946 (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET) 2949 (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
2947 #endif 2950 #endif
2948 2951
2949 #define CONFIG_SYS_FSL_CPC_ADDR \ 2952 #define CONFIG_SYS_FSL_CPC_ADDR \
2950 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) 2953 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
2951 #define CONFIG_SYS_FSL_QMAN_ADDR \ 2954 #define CONFIG_SYS_FSL_QMAN_ADDR \
2952 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET) 2955 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
2953 #define CONFIG_SYS_FSL_BMAN_ADDR \ 2956 #define CONFIG_SYS_FSL_BMAN_ADDR \
2954 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET) 2957 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
2955 #define CONFIG_SYS_FSL_CORENET_PME_ADDR \ 2958 #define CONFIG_SYS_FSL_CORENET_PME_ADDR \
2956 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET) 2959 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
2957 #define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \ 2960 #define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
2958 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET) 2961 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
2959 #define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \ 2962 #define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
2960 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET) 2963 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
2961 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \ 2964 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \
2962 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) 2965 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
2963 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \ 2966 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
2964 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET) 2967 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
2965 #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \ 2968 #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
2966 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET) 2969 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
2967 #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \ 2970 #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
2968 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) 2971 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
2969 #define CONFIG_SYS_MPC85xx_ECM_ADDR \ 2972 #define CONFIG_SYS_MPC85xx_ECM_ADDR \
2970 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) 2973 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
2971 #define CONFIG_SYS_FSL_DDR_ADDR \ 2974 #define CONFIG_SYS_FSL_DDR_ADDR \
2972 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) 2975 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
2973 #define CONFIG_SYS_FSL_DDR2_ADDR \ 2976 #define CONFIG_SYS_FSL_DDR2_ADDR \
2974 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET) 2977 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
2975 #define CONFIG_SYS_FSL_DDR3_ADDR \ 2978 #define CONFIG_SYS_FSL_DDR3_ADDR \
2976 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET) 2979 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
2977 #define CONFIG_SYS_LBC_ADDR \ 2980 #define CONFIG_SYS_LBC_ADDR \
2978 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) 2981 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
2979 #define CONFIG_SYS_IFC_ADDR \ 2982 #define CONFIG_SYS_IFC_ADDR \
2980 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET) 2983 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
2981 #define CONFIG_SYS_MPC85xx_ESPI_ADDR \ 2984 #define CONFIG_SYS_MPC85xx_ESPI_ADDR \
2982 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) 2985 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
2983 #define CONFIG_SYS_MPC85xx_PCIX_ADDR \ 2986 #define CONFIG_SYS_MPC85xx_PCIX_ADDR \
2984 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) 2987 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
2985 #define CONFIG_SYS_MPC85xx_PCIX2_ADDR \ 2988 #define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
2986 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) 2989 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
2987 #define CONFIG_SYS_MPC85xx_GPIO_ADDR \ 2990 #define CONFIG_SYS_MPC85xx_GPIO_ADDR \
2988 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) 2991 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
2989 #define CONFIG_SYS_MPC85xx_SATA1_ADDR \ 2992 #define CONFIG_SYS_MPC85xx_SATA1_ADDR \
2990 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) 2993 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
2991 #define CONFIG_SYS_MPC85xx_SATA2_ADDR \ 2994 #define CONFIG_SYS_MPC85xx_SATA2_ADDR \
2992 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) 2995 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
2993 #define CONFIG_SYS_MPC85xx_L2_ADDR \ 2996 #define CONFIG_SYS_MPC85xx_L2_ADDR \
2994 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) 2997 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
2995 #define CONFIG_SYS_MPC85xx_DMA_ADDR \ 2998 #define CONFIG_SYS_MPC85xx_DMA_ADDR \
2996 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) 2999 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
2997 #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \ 3000 #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
2998 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) 3001 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
2999 #define CONFIG_SYS_MPC8xxx_PIC_ADDR \ 3002 #define CONFIG_SYS_MPC8xxx_PIC_ADDR \
3000 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) 3003 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
3001 #define CONFIG_SYS_MPC85xx_CPM_ADDR \ 3004 #define CONFIG_SYS_MPC85xx_CPM_ADDR \
3002 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) 3005 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
3003 #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \ 3006 #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
3004 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET) 3007 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
3005 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \ 3008 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
3006 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) 3009 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
3007 #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \ 3010 #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
3008 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) 3011 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
3009 #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \ 3012 #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
3010 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET) 3013 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
3011 #define CONFIG_SYS_MPC85xx_USB1_ADDR \ 3014 #define CONFIG_SYS_MPC85xx_USB1_ADDR \
3012 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET) 3015 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
3013 #define CONFIG_SYS_MPC85xx_USB2_ADDR \ 3016 #define CONFIG_SYS_MPC85xx_USB2_ADDR \
3014 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET) 3017 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
3015 #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \ 3018 #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
3016 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET) 3019 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
3017 #define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \ 3020 #define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
3018 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET) 3021 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
3019 #define CONFIG_SYS_FSL_SEC_ADDR \ 3022 #define CONFIG_SYS_FSL_SEC_ADDR \
3020 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) 3023 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
3021 #define CONFIG_SYS_FSL_FM1_ADDR \ 3024 #define CONFIG_SYS_FSL_FM1_ADDR \
3022 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) 3025 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
3023 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ 3026 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
3024 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) 3027 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
3025 #define CONFIG_SYS_FSL_FM2_ADDR \ 3028 #define CONFIG_SYS_FSL_FM2_ADDR \
3026 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET) 3029 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
3027 #define CONFIG_SYS_FSL_SRIO_ADDR \ 3030 #define CONFIG_SYS_FSL_SRIO_ADDR \
3028 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET) 3031 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
3029 3032
3030 #define CONFIG_SYS_PCI1_ADDR \ 3033 #define CONFIG_SYS_PCI1_ADDR \
3031 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET) 3034 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
3032 #define CONFIG_SYS_PCI2_ADDR \ 3035 #define CONFIG_SYS_PCI2_ADDR \
3033 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET) 3036 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
3034 #define CONFIG_SYS_PCIE1_ADDR \ 3037 #define CONFIG_SYS_PCIE1_ADDR \
3035 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET) 3038 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
3036 #define CONFIG_SYS_PCIE2_ADDR \ 3039 #define CONFIG_SYS_PCIE2_ADDR \
3037 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET) 3040 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
3038 #define CONFIG_SYS_PCIE3_ADDR \ 3041 #define CONFIG_SYS_PCIE3_ADDR \
3039 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET) 3042 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
3040 #define CONFIG_SYS_PCIE4_ADDR \ 3043 #define CONFIG_SYS_PCIE4_ADDR \
3041 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET) 3044 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
3042 3045
3043 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 3046 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
3044 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) 3047 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
3045 3048
3046 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 3049 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
3047 struct ccsr_cluster_l2 { 3050 struct ccsr_cluster_l2 {
3048 u32 l2csr0; /* 0x000 L2 cache control and status register 0 */ 3051 u32 l2csr0; /* 0x000 L2 cache control and status register 0 */
3049 u32 l2csr1; /* 0x004 L2 cache control and status register 1 */ 3052 u32 l2csr1; /* 0x004 L2 cache control and status register 1 */
3050 u32 l2cfg0; /* 0x008 L2 cache configuration register 0 */ 3053 u32 l2cfg0; /* 0x008 L2 cache configuration register 0 */
3051 u8 res_0c[500];/* 0x00c - 0x1ff */ 3054 u8 res_0c[500];/* 0x00c - 0x1ff */
3052 u32 l2pir0; /* 0x200 L2 cache partitioning ID register 0 */ 3055 u32 l2pir0; /* 0x200 L2 cache partitioning ID register 0 */
3053 u8 res_204[4]; 3056 u8 res_204[4];
3054 u32 l2par0; /* 0x208 L2 cache partitioning allocation register 0 */ 3057 u32 l2par0; /* 0x208 L2 cache partitioning allocation register 0 */
3055 u32 l2pwr0; /* 0x20c L2 cache partitioning way register 0 */ 3058 u32 l2pwr0; /* 0x20c L2 cache partitioning way register 0 */
3056 u32 l2pir1; /* 0x210 L2 cache partitioning ID register 1 */ 3059 u32 l2pir1; /* 0x210 L2 cache partitioning ID register 1 */
3057 u8 res_214[4]; 3060 u8 res_214[4];
3058 u32 l2par1; /* 0x218 L2 cache partitioning allocation register 1 */ 3061 u32 l2par1; /* 0x218 L2 cache partitioning allocation register 1 */
3059 u32 l2pwr1; /* 0x21c L2 cache partitioning way register 1 */ 3062 u32 l2pwr1; /* 0x21c L2 cache partitioning way register 1 */
3060 u32 u2pir2; /* 0x220 L2 cache partitioning ID register 2 */ 3063 u32 u2pir2; /* 0x220 L2 cache partitioning ID register 2 */
3061 u8 res_224[4]; 3064 u8 res_224[4];
3062 u32 l2par2; /* 0x228 L2 cache partitioning allocation register 2 */ 3065 u32 l2par2; /* 0x228 L2 cache partitioning allocation register 2 */
3063 u32 l2pwr2; /* 0x22c L2 cache partitioning way register 2 */ 3066 u32 l2pwr2; /* 0x22c L2 cache partitioning way register 2 */
3064 u32 l2pir3; /* 0x230 L2 cache partitioning ID register 3 */ 3067 u32 l2pir3; /* 0x230 L2 cache partitioning ID register 3 */
3065 u8 res_234[4]; 3068 u8 res_234[4];
3066 u32 l2par3; /* 0x238 L2 cache partitining allocation register 3 */ 3069 u32 l2par3; /* 0x238 L2 cache partitining allocation register 3 */
3067 u32 l2pwr3; /* 0x23c L2 cache partitining way register 3 */ 3070 u32 l2pwr3; /* 0x23c L2 cache partitining way register 3 */
3068 u32 l2pir4; /* 0x240 L2 cache partitioning ID register 3 */ 3071 u32 l2pir4; /* 0x240 L2 cache partitioning ID register 3 */
3069 u8 res244[4]; 3072 u8 res244[4];
3070 u32 l2par4; /* 0x248 L2 cache partitioning allocation register 3 */ 3073 u32 l2par4; /* 0x248 L2 cache partitioning allocation register 3 */
3071 u32 l2pwr4; /* 0x24c L2 cache partitioning way register 3 */ 3074 u32 l2pwr4; /* 0x24c L2 cache partitioning way register 3 */
3072 u32 l2pir5; /* 0x250 L2 cache partitioning ID register 3 */ 3075 u32 l2pir5; /* 0x250 L2 cache partitioning ID register 3 */
3073 u8 res_254[4]; 3076 u8 res_254[4];
3074 u32 l2par5; /* 0x258 L2 cache partitioning allocation register 3 */ 3077 u32 l2par5; /* 0x258 L2 cache partitioning allocation register 3 */
3075 u32 l2pwr5; /* 0x25c L2 cache partitioning way register 3 */ 3078 u32 l2pwr5; /* 0x25c L2 cache partitioning way register 3 */
3076 u32 l2pir6; /* 0x260 L2 cache partitioning ID register 3 */ 3079 u32 l2pir6; /* 0x260 L2 cache partitioning ID register 3 */
3077 u8 res_264[4]; 3080 u8 res_264[4];
3078 u32 l2par6; /* 0x268 L2 cache partitioning allocation register 3 */ 3081 u32 l2par6; /* 0x268 L2 cache partitioning allocation register 3 */
3079 u32 l2pwr6; /* 0x26c L2 cache partitioning way register 3 */ 3082 u32 l2pwr6; /* 0x26c L2 cache partitioning way register 3 */
3080 u32 l2pir7; /* 0x270 L2 cache partitioning ID register 3 */ 3083 u32 l2pir7; /* 0x270 L2 cache partitioning ID register 3 */
3081 u8 res274[4]; 3084 u8 res274[4];
3082 u32 l2par7; /* 0x278 L2 cache partitioning allocation register 3 */ 3085 u32 l2par7; /* 0x278 L2 cache partitioning allocation register 3 */
3083 u32 l2pwr7; /* 0x27c L2 cache partitioning way register 3 */ 3086 u32 l2pwr7; /* 0x27c L2 cache partitioning way register 3 */
3084 u8 res_280[0xb80]; /* 0x280 - 0xdff */ 3087 u8 res_280[0xb80]; /* 0x280 - 0xdff */
3085 u32 l2errinjhi; /* 0xe00 L2 cache error injection mask high */ 3088 u32 l2errinjhi; /* 0xe00 L2 cache error injection mask high */
3086 u32 l2errinjlo; /* 0xe04 L2 cache error injection mask low */ 3089 u32 l2errinjlo; /* 0xe04 L2 cache error injection mask low */
3087 u32 l2errinjctl;/* 0xe08 L2 cache error injection control */ 3090 u32 l2errinjctl;/* 0xe08 L2 cache error injection control */
3088 u8 res_e0c[20]; /* 0xe0c - 0x01f */ 3091 u8 res_e0c[20]; /* 0xe0c - 0x01f */
3089 u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */ 3092 u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */
3090 u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */ 3093 u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */
3091 u32 l2captecc; /* 0xe28 L2 cache error capture ECC syndrome */ 3094 u32 l2captecc; /* 0xe28 L2 cache error capture ECC syndrome */
3092 u8 res_e2c[20]; /* 0xe2c - 0xe3f */ 3095 u8 res_e2c[20]; /* 0xe2c - 0xe3f */
3093 u32 l2errdet; /* 0xe40 L2 cache error detect */ 3096 u32 l2errdet; /* 0xe40 L2 cache error detect */
3094 u32 l2errdis; /* 0xe44 L2 cache error disable */ 3097 u32 l2errdis; /* 0xe44 L2 cache error disable */
3095 u32 l2errinten; /* 0xe48 L2 cache error interrupt enable */ 3098 u32 l2errinten; /* 0xe48 L2 cache error interrupt enable */
3096 u32 l2errattr; /* 0xe4c L2 cache error attribute */ 3099 u32 l2errattr; /* 0xe4c L2 cache error attribute */
3097 u32 l2erreaddr; /* 0xe50 L2 cache error extended address */ 3100 u32 l2erreaddr; /* 0xe50 L2 cache error extended address */
3098 u32 l2erraddr; /* 0xe54 L2 cache error address */ 3101 u32 l2erraddr; /* 0xe54 L2 cache error address */
3099 u32 l2errctl; /* 0xe58 L2 cache error control */ 3102 u32 l2errctl; /* 0xe58 L2 cache error control */
3100 }; 3103 };
3101 #define CONFIG_SYS_FSL_CLUSTER_1_L2 \ 3104 #define CONFIG_SYS_FSL_CLUSTER_1_L2 \
3102 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET) 3105 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
3103 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 3106 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
3104 3107
3105 #define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000 3108 #define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
3106 struct dcsr_dcfg_regs { 3109 struct dcsr_dcfg_regs {
3107 u8 res_0[0x520]; 3110 u8 res_0[0x520];
3108 u32 ecccr1; 3111 u32 ecccr1;
3109 #define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000 3112 #define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000
3110 #define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000 3113 #define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
3111 u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */ 3114 u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
3112 }; 3115 };
3113 #endif /*__IMMAP_85xx__*/ 3116 #endif /*__IMMAP_85xx__*/
3114 3117
board/freescale/b4860qds/b4_rcw.cfg
1 #PBL preamble and RCW header 1 #PBL preamble and RCW header
2 aa55aa55 010e0100 2 aa55aa55 010e0100
3 # serdes protocol 0x2A_0x98 3 # serdes protocol 0x2A_0x98
4 140e0018 0f001218 00000000 00000000 4 140e0018 0f001218 00000000 00000000
5 54980000 9000a000 f8025000 a9000000 5 54980000 9000a000 e8104000 a9000000
6 01000000 00000000 00000000 0001b1f8 6 01000000 00000000 00000000 0001b1f8
7 00000000 14000020 00000000 00000011 7 00000000 14000020 00000000 00000011
8 8
board/freescale/bsc9131rdb/tlb.c
1 /* 1 /*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <asm/mmu.h> 8 #include <asm/mmu.h>
9 9
10 struct fsl_e_tlb_entry tlb_table[] = { 10 struct fsl_e_tlb_entry tlb_table[] = {
11 /* TLB 0 - for temp stack in cache */ 11 /* TLB 0 - for temp stack in cache */
12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
13 MAS3_SX|MAS3_SW|MAS3_SR, 0, 13 MAS3_SX|MAS3_SW|MAS3_SR, 0,
14 0, 0, BOOKE_PAGESZ_4K, 0), 14 0, 0, BOOKE_PAGESZ_4K, 0),
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
16 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 16 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
17 MAS3_SX|MAS3_SW|MAS3_SR, 0, 17 MAS3_SX|MAS3_SW|MAS3_SR, 0,
18 0, 0, BOOKE_PAGESZ_4K, 0), 18 0, 0, BOOKE_PAGESZ_4K, 0),
19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
20 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 20 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
21 MAS3_SX|MAS3_SW|MAS3_SR, 0, 21 MAS3_SX|MAS3_SW|MAS3_SR, 0,
22 0, 0, BOOKE_PAGESZ_4K, 0), 22 0, 0, BOOKE_PAGESZ_4K, 0),
23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
24 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 24 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
25 MAS3_SX|MAS3_SW|MAS3_SR, 0, 25 MAS3_SX|MAS3_SW|MAS3_SR, 0,
26 0, 0, BOOKE_PAGESZ_4K, 0), 26 0, 0, BOOKE_PAGESZ_4K, 0),
27 27
28 /* TLB 1 */ 28 /* TLB 1 */
29 /* *I*** - Covers boot page */ 29 /* *I*** - Covers boot page */
30 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 30 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
31 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 31 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
32 0, 0, BOOKE_PAGESZ_4K, 1), 32 0, 0, BOOKE_PAGESZ_4K, 1),
33 #ifdef CONFIG_SPL_NAND_MINIMAL 33 #ifdef CONFIG_SPL_NAND_BOOT
34 SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, 34 SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
35 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 35 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
36 0, 10, BOOKE_PAGESZ_4K, 1), 36 0, 10, BOOKE_PAGESZ_4K, 1),
37 #endif 37 #endif
38 38
39 /* *I*G* - CCSRBAR (PA) */ 39 /* *I*G* - CCSRBAR (PA) */
40 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 40 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
41 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 41 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
42 0, 1, BOOKE_PAGESZ_1M, 1), 42 0, 1, BOOKE_PAGESZ_1M, 1),
43 43
44 /* CCSRBAR (DSP) */ 44 /* CCSRBAR (DSP) */
45 SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR, 45 SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
46 CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, 46 CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS,
47 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 47 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
48 0, 2, BOOKE_PAGESZ_1M, 1), 48 0, 2, BOOKE_PAGESZ_1M, 1),
49 49
50 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) 50 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
51 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 51 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
52 MAS3_SX|MAS3_SW|MAS3_SR, 0, 52 MAS3_SX|MAS3_SW|MAS3_SR, 0,
53 0, 8, BOOKE_PAGESZ_1G, 1), 53 0, 8, BOOKE_PAGESZ_1G, 1),
54 #endif 54 #endif
55 55
56 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 56 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
57 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 57 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
58 0, 3, BOOKE_PAGESZ_1M, 1) 58 0, 3, BOOKE_PAGESZ_1M, 1)
59 59
60 }; 60 };
61 61
62 int num_tlb_entries = ARRAY_SIZE(tlb_table); 62 int num_tlb_entries = ARRAY_SIZE(tlb_table);
63 63
board/freescale/bsc9132qds/tlb.c
1 /* 1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc. 2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <asm/mmu.h> 8 #include <asm/mmu.h>
9 9
10 struct fsl_e_tlb_entry tlb_table[] = { 10 struct fsl_e_tlb_entry tlb_table[] = {
11 /* TLB 0 - for temp stack in cache */ 11 /* TLB 0 - for temp stack in cache */
12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
13 MAS3_SX|MAS3_SW|MAS3_SR, 0, 13 MAS3_SX|MAS3_SW|MAS3_SR, 0,
14 0, 0, BOOKE_PAGESZ_4K, 0), 14 0, 0, BOOKE_PAGESZ_4K, 0),
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
16 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 16 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
17 MAS3_SX|MAS3_SW|MAS3_SR, 0, 17 MAS3_SX|MAS3_SW|MAS3_SR, 0,
18 0, 0, BOOKE_PAGESZ_4K, 0), 18 0, 0, BOOKE_PAGESZ_4K, 0),
19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
20 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 20 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
21 MAS3_SX|MAS3_SW|MAS3_SR, 0, 21 MAS3_SX|MAS3_SW|MAS3_SR, 0,
22 0, 0, BOOKE_PAGESZ_4K, 0), 22 0, 0, BOOKE_PAGESZ_4K, 0),
23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
24 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 24 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
25 MAS3_SX|MAS3_SW|MAS3_SR, 0, 25 MAS3_SX|MAS3_SW|MAS3_SR, 0,
26 0, 0, BOOKE_PAGESZ_4K, 0), 26 0, 0, BOOKE_PAGESZ_4K, 0),
27 27
28 /* TLB 1 */ 28 /* TLB 1 */
29 /* *I*** - Covers boot page */ 29 /* *I*** - Covers boot page */
30 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 30 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
31 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 31 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
32 0, 0, BOOKE_PAGESZ_4K, 1), 32 0, 0, BOOKE_PAGESZ_4K, 1),
33 #ifdef CONFIG_SPL_NAND_MINIMAL 33 #ifdef CONFIG_SPL_NAND_BOOT
34 SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, 34 SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
35 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 35 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
36 0, 10, BOOKE_PAGESZ_4K, 1), 36 0, 10, BOOKE_PAGESZ_4K, 1),
37 #endif 37 #endif
38 38
39 /* *I*G* - CCSRBAR (PA) */ 39 /* *I*G* - CCSRBAR (PA) */
40 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 40 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
41 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 41 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
42 0, 1, BOOKE_PAGESZ_1M, 1), 42 0, 1, BOOKE_PAGESZ_1M, 1),
43 43
44 /* CCSRBAR (DSP) */ 44 /* CCSRBAR (DSP) */
45 SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR, 45 SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
46 CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, MAS3_SW|MAS3_SR, 46 CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, MAS3_SW|MAS3_SR,
47 MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1M, 1), 47 MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1M, 1),
48 48
49 #ifndef CONFIG_SPL_BUILD 49 #ifndef CONFIG_SPL_BUILD
50 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 50 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
51 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 51 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
52 0, 3, BOOKE_PAGESZ_64M, 1), 52 0, 3, BOOKE_PAGESZ_64M, 1),
53 53
54 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000, 54 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000,
55 CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000, 55 CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
56 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 56 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
57 0, 4, BOOKE_PAGESZ_64M, 1), 57 0, 4, BOOKE_PAGESZ_64M, 1),
58 58
59 #ifdef CONFIG_PCI 59 #ifdef CONFIG_PCI
60 /* *I*G* - PCI */ 60 /* *I*G* - PCI */
61 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 61 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
62 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 62 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
63 0, 6, BOOKE_PAGESZ_256M, 1), 63 0, 6, BOOKE_PAGESZ_256M, 1),
64 64
65 /* *I*G* - PCI I/O */ 65 /* *I*G* - PCI I/O */
66 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 66 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
67 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 67 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
68 0, 7, BOOKE_PAGESZ_64K, 1), 68 0, 7, BOOKE_PAGESZ_64K, 1),
69 #endif 69 #endif
70 #endif 70 #endif
71 71
72 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) 72 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
73 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 73 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
74 MAS3_SX|MAS3_SW|MAS3_SR, 0, 74 MAS3_SX|MAS3_SW|MAS3_SR, 0,
75 0, 8, BOOKE_PAGESZ_1G, 1), 75 0, 8, BOOKE_PAGESZ_1G, 1),
76 #endif 76 #endif
77 77
78 #ifdef CONFIG_SYS_FPGA_BASE 78 #ifdef CONFIG_SYS_FPGA_BASE
79 /* *I*G - Board FPGA */ 79 /* *I*G - Board FPGA */
80 SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS, 80 SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS,
81 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 81 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
82 0, 9, BOOKE_PAGESZ_256K, 1), 82 0, 9, BOOKE_PAGESZ_256K, 1),
83 #endif 83 #endif
84 84
85 #ifdef CONFIG_SYS_NAND_BASE_PHYS 85 #ifdef CONFIG_SYS_NAND_BASE_PHYS
86 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 86 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
87 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 87 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
88 0, 5, BOOKE_PAGESZ_1M, 1), 88 0, 5, BOOKE_PAGESZ_1M, 1),
89 #endif 89 #endif
90 }; 90 };
91 91
92 int num_tlb_entries = ARRAY_SIZE(tlb_table); 92 int num_tlb_entries = ARRAY_SIZE(tlb_table);
93 93
board/freescale/p1010rdb/tlb.c
1 /* 1 /*
2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <asm/mmu.h> 8 #include <asm/mmu.h>
9 9
10 struct fsl_e_tlb_entry tlb_table[] = { 10 struct fsl_e_tlb_entry tlb_table[] = {
11 /* TLB 0 - for temp stack in cache */ 11 /* TLB 0 - for temp stack in cache */
12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
13 MAS3_SX|MAS3_SW|MAS3_SR, 0, 13 MAS3_SX|MAS3_SW|MAS3_SR, 0,
14 0, 0, BOOKE_PAGESZ_4K, 0), 14 0, 0, BOOKE_PAGESZ_4K, 0),
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
16 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 16 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
17 MAS3_SX|MAS3_SW|MAS3_SR, 0, 17 MAS3_SX|MAS3_SW|MAS3_SR, 0,
18 0, 0, BOOKE_PAGESZ_4K, 0), 18 0, 0, BOOKE_PAGESZ_4K, 0),
19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
20 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 20 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
21 MAS3_SX|MAS3_SW|MAS3_SR, 0, 21 MAS3_SX|MAS3_SW|MAS3_SR, 0,
22 0, 0, BOOKE_PAGESZ_4K, 0), 22 0, 0, BOOKE_PAGESZ_4K, 0),
23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
24 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 24 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
25 MAS3_SX|MAS3_SW|MAS3_SR, 0, 25 MAS3_SX|MAS3_SW|MAS3_SR, 0,
26 0, 0, BOOKE_PAGESZ_4K, 0), 26 0, 0, BOOKE_PAGESZ_4K, 0),
27 27
28 /* TLB 1 */ 28 /* TLB 1 */
29 /* *I*** - Covers boot page */ 29 /* *I*** - Covers boot page */
30 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 30 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
31 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 31 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
32 0, 0, BOOKE_PAGESZ_4K, 1), 32 0, 0, BOOKE_PAGESZ_4K, 1),
33 #ifdef CONFIG_SPL_NAND_MINIMAL 33 #ifdef CONFIG_SPL_NAND_BOOT
34 SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, 34 SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
35 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 35 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
36 0, 10, BOOKE_PAGESZ_4K, 1), 36 0, 10, BOOKE_PAGESZ_4K, 1),
37 #endif 37 #endif
38 38
39 /* *I*G* - CCSRBAR */ 39 /* *I*G* - CCSRBAR */
40 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 40 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
41 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 41 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
42 0, 1, BOOKE_PAGESZ_1M, 1), 42 0, 1, BOOKE_PAGESZ_1M, 1),
43 43
44 #ifndef CONFIG_SPL_BUILD 44 #ifndef CONFIG_SPL_BUILD
45 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 45 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
46 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 46 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
47 0, 2, BOOKE_PAGESZ_16M, 1), 47 0, 2, BOOKE_PAGESZ_16M, 1),
48 48
49 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, 49 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
50 CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, 50 CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
51 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 51 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
52 0, 3, BOOKE_PAGESZ_16M, 1), 52 0, 3, BOOKE_PAGESZ_16M, 1),
53 53
54 #ifdef CONFIG_PCI 54 #ifdef CONFIG_PCI
55 /* *I*G* - PCI */ 55 /* *I*G* - PCI */
56 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 56 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
57 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 57 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
58 0, 4, BOOKE_PAGESZ_1G, 1), 58 0, 4, BOOKE_PAGESZ_1G, 1),
59 59
60 /* *I*G* - PCI I/O */ 60 /* *I*G* - PCI I/O */
61 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 61 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
62 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 62 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
63 0, 5, BOOKE_PAGESZ_256K, 1), 63 0, 5, BOOKE_PAGESZ_256K, 1),
64 #endif 64 #endif
65 #endif 65 #endif
66 66
67 /* *I*G - Board CPLD */ 67 /* *I*G - Board CPLD */
68 SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, 68 SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
69 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 69 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
70 0, 6, BOOKE_PAGESZ_256K, 1), 70 0, 6, BOOKE_PAGESZ_256K, 1),
71 71
72 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 72 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
73 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 73 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
74 0, 7, BOOKE_PAGESZ_1M, 1), 74 0, 7, BOOKE_PAGESZ_1M, 1),
75 75
76 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) 76 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
77 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 77 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
78 MAS3_SX|MAS3_SW|MAS3_SR, 0, 78 MAS3_SX|MAS3_SW|MAS3_SR, 0,
79 0, 8, BOOKE_PAGESZ_1G, 1) 79 0, 8, BOOKE_PAGESZ_1G, 1)
80 #endif 80 #endif
81 }; 81 };
82 82
83 int num_tlb_entries = ARRAY_SIZE(tlb_table); 83 int num_tlb_entries = ARRAY_SIZE(tlb_table);
84 84
board/freescale/t1040qds/t1040_pbi.cfg
1 #PBI commands 1 #PBI commands
2 #Initialize CPC1 2 #Initialize CPC1
3 09010000 00200400 3 09010000 00200400
4 09138000 00000000 4 09138000 00000000
5 091380c0 00000100 5 091380c0 00000100
6 #Configure CPC1 as 512KB SRAM 6 #Configure CPC1 as 256KB SRAM
7 09010100 00000000 7 09010100 00000000
8 09010104 fffc0007 8 09010104 fffc0007
9 09010f00 08000000 9 09010f00 08000000
10 09010000 80000000 10 09010000 80000000
11 #Configure LAW for CPC1 11 #Configure LAW for CPC1
12 09000cf0 00000000 12 09000cf0 00000000
13 09000cf4 fffc0000 13 09000cf4 fffc0000
14 09000cf8 81000011 14 09000cf8 81000011
15 #Configure alternate space 15 #Configure alternate space
16 09000010 00000000 16 09000010 00000000
17 09000014 ff000000 17 09000014 ff000000
18 09000018 81000000 18 09000018 81000000
19 #Configure SPI controller 19 #Configure SPI controller
20 09110000 80000403 20 09110000 80000403
21 09110020 2d170008 21 09110020 2d170008
22 09110024 00100008 22 09110024 00100008
23 09110028 00100008 23 09110028 00100008
24 0911002c 00100008 24 0911002c 00100008
25 #Flush PBL data 25 #Flush PBL data
26 09138000 00000000 26 09138000 00000000
27 091380c0 00000000 27 091380c0 00000000
28 28
board/freescale/t1040qds/t1040qds.c
1 /* 1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc. 2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <command.h> 8 #include <command.h>
9 #include <i2c.h> 9 #include <i2c.h>
10 #include <netdev.h> 10 #include <netdev.h>
11 #include <linux/compiler.h> 11 #include <linux/compiler.h>
12 #include <asm/mmu.h> 12 #include <asm/mmu.h>
13 #include <asm/processor.h> 13 #include <asm/processor.h>
14 #include <asm/cache.h> 14 #include <asm/cache.h>
15 #include <asm/immap_85xx.h> 15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h> 16 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h> 17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_portals.h> 18 #include <asm/fsl_portals.h>
19 #include <asm/fsl_liodn.h> 19 #include <asm/fsl_liodn.h>
20 #include <fm_eth.h> 20 #include <fm_eth.h>
21 21
22 #include "../common/qixis.h" 22 #include "../common/qixis.h"
23 #include "t1040qds.h" 23 #include "t1040qds.h"
24 #include "t1040qds_qixis.h" 24 #include "t1040qds_qixis.h"
25 25
26 DECLARE_GLOBAL_DATA_PTR; 26 DECLARE_GLOBAL_DATA_PTR;
27 27
28 int checkboard(void) 28 int checkboard(void)
29 { 29 {
30 char buf[64]; 30 char buf[64];
31 u8 sw; 31 u8 sw;
32 struct cpu_type *cpu = gd->arch.cpu; 32 struct cpu_type *cpu = gd->arch.cpu;
33 static const char *const freq[] = {"100", "125", "156.25", "161.13", 33 static const char *const freq[] = {"100", "125", "156.25", "161.13",
34 "122.88", "122.88", "122.88"}; 34 "122.88", "122.88", "122.88"};
35 int clock; 35 int clock;
36 36
37 printf("Board: %sQDS, ", cpu->name); 37 printf("Board: %sQDS, ", cpu->name);
38 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", 38 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
39 QIXIS_READ(id), QIXIS_READ(arch)); 39 QIXIS_READ(id), QIXIS_READ(arch));
40 40
41 sw = QIXIS_READ(brdcfg[0]); 41 sw = QIXIS_READ(brdcfg[0]);
42 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 42 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
43 43
44 if (sw < 0x8) 44 if (sw < 0x8)
45 printf("vBank: %d\n", sw); 45 printf("vBank: %d\n", sw);
46 else if (sw == 0x8) 46 else if (sw == 0x8)
47 puts("PromJet\n"); 47 puts("PromJet\n");
48 else if (sw == 0x9) 48 else if (sw == 0x9)
49 puts("NAND\n"); 49 puts("NAND\n");
50 else if (sw == 0x15) 50 else if (sw == 0x15)
51 printf("IFCCard\n"); 51 printf("IFCCard\n");
52 else 52 else
53 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 53 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
54 54
55 printf("FPGA: v%d (%s), build %d", 55 printf("FPGA: v%d (%s), build %d",
56 (int)QIXIS_READ(scver), qixis_read_tag(buf), 56 (int)QIXIS_READ(scver), qixis_read_tag(buf),
57 (int)qixis_read_minor()); 57 (int)qixis_read_minor());
58 /* the timestamp string contains "\n" at the end */ 58 /* the timestamp string contains "\n" at the end */
59 printf(" on %s", qixis_read_time(buf)); 59 printf(" on %s", qixis_read_time(buf));
60 60
61 /* 61 /*
62 * Display the actual SERDES reference clocks as configured by the 62 * Display the actual SERDES reference clocks as configured by the
63 * dip switches on the board. Note that the SWx registers could 63 * dip switches on the board. Note that the SWx registers could
64 * technically be set to force the reference clocks to match the 64 * technically be set to force the reference clocks to match the
65 * values that the SERDES expects (or vice versa). For now, however, 65 * values that the SERDES expects (or vice versa). For now, however,
66 * we just display both values and hope the user notices when they 66 * we just display both values and hope the user notices when they
67 * don't match. 67 * don't match.
68 */ 68 */
69 puts("SERDES Reference: "); 69 puts("SERDES Reference: ");
70 sw = QIXIS_READ(brdcfg[2]); 70 sw = QIXIS_READ(brdcfg[2]);
71 clock = (sw >> 6) & 3; 71 clock = (sw >> 6) & 3;
72 printf("Clock1=%sMHz ", freq[clock]); 72 printf("Clock1=%sMHz ", freq[clock]);
73 clock = (sw >> 4) & 3; 73 clock = (sw >> 4) & 3;
74 printf("Clock2=%sMHz\n", freq[clock]); 74 printf("Clock2=%sMHz\n", freq[clock]);
75 75
76 return 0; 76 return 0;
77 } 77 }
78 78
79 int select_i2c_ch_pca9547(u8 ch) 79 int select_i2c_ch_pca9547(u8 ch)
80 { 80 {
81 int ret; 81 int ret;
82 82
83 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 83 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
84 if (ret) { 84 if (ret) {
85 puts("PCA: failed to select proper channel\n"); 85 puts("PCA: failed to select proper channel\n");
86 return ret; 86 return ret;
87 } 87 }
88 88
89 return 0; 89 return 0;
90 } 90 }
91 91
92 int board_early_init_r(void) 92 int board_early_init_r(void)
93 { 93 {
94 #ifdef CONFIG_SYS_FLASH_BASE 94 #ifdef CONFIG_SYS_FLASH_BASE
95 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 95 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
96 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 96 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
97 97
98 /* 98 /*
99 * Remap Boot flash + PROMJET region to caching-inhibited 99 * Remap Boot flash + PROMJET region to caching-inhibited
100 * so that flash can be erased properly. 100 * so that flash can be erased properly.
101 */ 101 */
102 102
103 /* Flush d-cache and invalidate i-cache of any FLASH data */ 103 /* Flush d-cache and invalidate i-cache of any FLASH data */
104 flush_dcache(); 104 flush_dcache();
105 invalidate_icache(); 105 invalidate_icache();
106 106
107 /* invalidate existing TLB entry for flash + promjet */ 107 /* invalidate existing TLB entry for flash + promjet */
108 disable_tlb(flash_esel); 108 disable_tlb(flash_esel);
109 109
110 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 110 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
111 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 111 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
112 0, flash_esel, BOOKE_PAGESZ_256M, 1); 112 0, flash_esel, BOOKE_PAGESZ_256M, 1);
113 #endif 113 #endif
114 set_liodns(); 114 set_liodns();
115 #ifdef CONFIG_SYS_DPAA_QBMAN 115 #ifdef CONFIG_SYS_DPAA_QBMAN
116 setup_portals(); 116 setup_portals();
117 #endif 117 #endif
118 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 118 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
119 119
120 return 0; 120 return 0;
121 } 121 }
122 122
123 unsigned long get_board_sys_clk(void) 123 unsigned long get_board_sys_clk(void)
124 { 124 {
125 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 125 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
126 126
127 switch (sysclk_conf & 0x0F) { 127 switch (sysclk_conf & 0x0F) {
128 case QIXIS_SYSCLK_64: 128 case QIXIS_SYSCLK_64:
129 return 64000000; 129 return 64000000;
130 case QIXIS_SYSCLK_83: 130 case QIXIS_SYSCLK_83:
131 return 83333333; 131 return 83333333;
132 case QIXIS_SYSCLK_100: 132 case QIXIS_SYSCLK_100:
133 return 100000000; 133 return 100000000;
134 case QIXIS_SYSCLK_125: 134 case QIXIS_SYSCLK_125:
135 return 125000000; 135 return 125000000;
136 case QIXIS_SYSCLK_133: 136 case QIXIS_SYSCLK_133:
137 return 133333333; 137 return 133333333;
138 case QIXIS_SYSCLK_150: 138 case QIXIS_SYSCLK_150:
139 return 150000000; 139 return 150000000;
140 case QIXIS_SYSCLK_160: 140 case QIXIS_SYSCLK_160:
141 return 160000000; 141 return 160000000;
142 case QIXIS_SYSCLK_166: 142 case QIXIS_SYSCLK_166:
143 return 166666666; 143 return 166666666;
144 } 144 }
145 return 66666666; 145 return 66666666;
146 } 146 }
147 147
148 unsigned long get_board_ddr_clk(void) 148 unsigned long get_board_ddr_clk(void)
149 { 149 {
150 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 150 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
151 151
152 switch ((ddrclk_conf & 0x30) >> 4) { 152 switch ((ddrclk_conf & 0x30) >> 4) {
153 case QIXIS_DDRCLK_100: 153 case QIXIS_DDRCLK_100:
154 return 100000000; 154 return 100000000;
155 case QIXIS_DDRCLK_125: 155 case QIXIS_DDRCLK_125:
156 return 125000000; 156 return 125000000;
157 case QIXIS_DDRCLK_133: 157 case QIXIS_DDRCLK_133:
158 return 133333333; 158 return 133333333;
159 } 159 }
160 return 66666666; 160 return 66666666;
161 } 161 }
162 162
163 #define NUM_SRDS_BANKS 2 163 #define NUM_SRDS_BANKS 2
164 int misc_init_r(void) 164 int misc_init_r(void)
165 { 165 {
166 u8 sw; 166 u8 sw;
167 serdes_corenet_t *srds_regs = 167 serdes_corenet_t *srds_regs =
168 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 168 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
169 u32 actual[NUM_SRDS_BANKS] = { 0 }; 169 u32 actual[NUM_SRDS_BANKS] = { 0 };
170 int i; 170 int i;
171 171
172 sw = QIXIS_READ(brdcfg[2]); 172 sw = QIXIS_READ(brdcfg[2]);
173 for (i = 0; i < NUM_SRDS_BANKS; i++) { 173 for (i = 0; i < NUM_SRDS_BANKS; i++) {
174 unsigned int clock = (sw >> (6 - 2 * i)) & 3; 174 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
175 switch (clock) { 175 switch (clock) {
176 case 0: 176 case 0:
177 actual[i] = SRDS_PLLCR0_RFCK_SEL_100; 177 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
178 break; 178 break;
179 case 1: 179 case 1:
180 actual[i] = SRDS_PLLCR0_RFCK_SEL_125; 180 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
181 break; 181 break;
182 case 2: 182 case 2:
183 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; 183 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
184 break; 184 break;
185 } 185 }
186 } 186 }
187 187
188 puts("SerDes1"); 188 puts("SerDes1");
189 for (i = 0; i < NUM_SRDS_BANKS; i++) { 189 for (i = 0; i < NUM_SRDS_BANKS; i++) {
190 u32 pllcr0 = srds_regs->bank[i].pllcr0; 190 u32 pllcr0 = srds_regs->bank[i].pllcr0;
191 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 191 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
192 if (expected != actual[i]) { 192 if (expected != actual[i]) {
193 printf("expects ref clk%d %sMHz, but actual is %sMHz\n", 193 printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
194 i + 1, serdes_clock_to_string(expected), 194 i + 1, serdes_clock_to_string(expected),
195 serdes_clock_to_string(actual[i])); 195 serdes_clock_to_string(actual[i]));
196 } 196 }
197 } 197 }
198 198
199 return 0; 199 return 0;
200 } 200 }
201 201
202 void ft_board_setup(void *blob, bd_t *bd) 202 void ft_board_setup(void *blob, bd_t *bd)
203 { 203 {
204 phys_addr_t base; 204 phys_addr_t base;
205 phys_size_t size; 205 phys_size_t size;
206 206
207 ft_cpu_setup(blob, bd); 207 ft_cpu_setup(blob, bd);
208 208
209 base = getenv_bootm_low(); 209 base = getenv_bootm_low();
210 size = getenv_bootm_size(); 210 size = getenv_bootm_size();
211 211
212 fdt_fixup_memory(blob, (u64)base, (u64)size); 212 fdt_fixup_memory(blob, (u64)base, (u64)size);
213 213
214 #ifdef CONFIG_PCI 214 #ifdef CONFIG_PCI
215 pci_of_setup(blob, bd); 215 pci_of_setup(blob, bd);
216 #endif 216 #endif
217 217
218 fdt_fixup_liodn(blob); 218 fdt_fixup_liodn(blob);
219 219
220 #ifdef CONFIG_HAS_FSL_DR_USB 220 #ifdef CONFIG_HAS_FSL_DR_USB
221 fdt_fixup_dr_usb(blob, bd); 221 fdt_fixup_dr_usb(blob, bd);
222 #endif 222 #endif
223 223
224 #ifdef CONFIG_SYS_DPAA_FMAN 224 #ifdef CONFIG_SYS_DPAA_FMAN
225 fdt_fixup_fman_ethernet(blob); 225 fdt_fixup_fman_ethernet(blob);
226 #endif 226 #endif
227 } 227 }
228 228
229 void qixis_dump_switch(void) 229 void qixis_dump_switch(void)
230 { 230 {
231 int i, nr_of_cfgsw; 231 int i, nr_of_cfgsw;
232 232
233 QIXIS_WRITE(cms[0], 0x00); 233 QIXIS_WRITE(cms[0], 0x00);
234 nr_of_cfgsw = QIXIS_READ(cms[1]); 234 nr_of_cfgsw = QIXIS_READ(cms[1]);
235 235
236 puts("DIP switch settings dump:\n"); 236 puts("DIP switch settings dump:\n");
237 for (i = 1; i <= nr_of_cfgsw; i++) { 237 for (i = 1; i <= nr_of_cfgsw; i++) {
238 QIXIS_WRITE(cms[0], i); 238 QIXIS_WRITE(cms[0], i);
239 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); 239 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
240 } 240 }
241 } 241 }
242
243 int board_need_mem_reset(void)
244 {
245 return 1;
246 }
242 247
1 # 1 #
2 # List of boards 2 # List of boards
3 # 3 #
4 # Syntax: 4 # Syntax:
5 # white-space separated list of entries; 5 # white-space separated list of entries;
6 # each entry has the fields documented below. 6 # each entry has the fields documented below.
7 # 7 #
8 # Unused fields can be specified as "-", or omitted if they 8 # Unused fields can be specified as "-", or omitted if they
9 # are the last field on the line. 9 # are the last field on the line.
10 # 10 #
11 # Lines starting with '#' are comments. 11 # Lines starting with '#' are comments.
12 # Blank lines are ignored. 12 # Blank lines are ignored.
13 # 13 #
14 # The CPU field takes the form: 14 # The CPU field takes the form:
15 # cpu[:spl_cpu] 15 # cpu[:spl_cpu]
16 # If spl_cpu is specified the make variable CPU will be set to this 16 # If spl_cpu is specified the make variable CPU will be set to this
17 # during the SPL build. 17 # during the SPL build.
18 # 18 #
19 # The options field takes the form: 19 # The options field takes the form:
20 # <board config name>[:comma separated config options] 20 # <board config name>[:comma separated config options]
21 # Each config option has the form (value defaults to "1"): 21 # Each config option has the form (value defaults to "1"):
22 # option[=value] 22 # option[=value]
23 # So if you have: 23 # So if you have:
24 # FOO:HAS_BAR,BAZ=64 24 # FOO:HAS_BAR,BAZ=64
25 # The file include/configs/FOO.h will be used, and these defines created: 25 # The file include/configs/FOO.h will be used, and these defines created:
26 # #define CONFIG_HAS_BAR 1 26 # #define CONFIG_HAS_BAR 1
27 # #define CONFIG_BAZ 64 27 # #define CONFIG_BAZ 64
28 # 28 #
29 # The maintainers field lists the e-mail addresses of the board's 29 # The maintainers field lists the e-mail addresses of the board's
30 # maintainers, separated by colons. NOTE: there are spaces in this field! 30 # maintainers, separated by colons. NOTE: there are spaces in this field!
31 # For any board without permanent maintainer, please contact 31 # For any board without permanent maintainer, please contact
32 # Wolfgang Denk <wd@denx.de> 32 # Wolfgang Denk <wd@denx.de>
33 # And Cc: the <u-boot@lists.denx.de> mailing list. 33 # And Cc: the <u-boot@lists.denx.de> mailing list.
34 34
35 # The list should be ordered according to the C locale. 35 # The list should be ordered according to the C locale.
36 # 36 #
37 # To keep the list formatted and sorted, script tools/reformat.py is available. 37 # To keep the list formatted and sorted, script tools/reformat.py is available.
38 # It can be used from a shell: 38 # It can be used from a shell:
39 # tools/reformat.py -i -d '-' -s 8 <boards.cfg >boards0.cfg && mv boards0.cfg boards.cfg 39 # tools/reformat.py -i -d '-' -s 8 <boards.cfg >boards0.cfg && mv boards0.cfg boards.cfg
40 # It can directly be invoked from vim: 40 # It can directly be invoked from vim:
41 # :%!tools/reformat.py -i -d '-' -s 8 41 # :%!tools/reformat.py -i -d '-' -s 8
42 # 42 #
43 # Status, Arch, CPU:SPLCPU, SoC, Vendor, Board name, Target, Options, Maintainers 43 # Status, Arch, CPU:SPLCPU, SoC, Vendor, Board name, Target, Options, Maintainers
44 ########################################################################################################### 44 ###########################################################################################################
45 45
46 Active arm arm1136 - armltd integrator integratorcp_cm1136 integratorcp:CM1136 Linus Walleij <linus.walleij@linaro.org> 46 Active arm arm1136 - armltd integrator integratorcp_cm1136 integratorcp:CM1136 Linus Walleij <linus.walleij@linaro.org>
47 Active arm arm1136 mx31 - - imx31_phycore - - 47 Active arm arm1136 mx31 - - imx31_phycore - -
48 Active arm arm1136 mx31 davedenx - qong - Wolfgang Denk <wd@denx.de> 48 Active arm arm1136 mx31 davedenx - qong - Wolfgang Denk <wd@denx.de>
49 Active arm arm1136 mx31 freescale - mx31pdk - Fabio Estevam <fabio.estevam@freescale.com> 49 Active arm arm1136 mx31 freescale - mx31pdk - Fabio Estevam <fabio.estevam@freescale.com>
50 Active arm arm1136 mx31 hale - tt01 - Helmut Raiger <helmut.raiger@hale.at> 50 Active arm arm1136 mx31 hale - tt01 - Helmut Raiger <helmut.raiger@hale.at>
51 Active arm arm1136 mx31 logicpd - imx31_litekit - - 51 Active arm arm1136 mx31 logicpd - imx31_litekit - -
52 Active arm arm1136 mx35 - - woodburn - Stefano Babic <sbabic@denx.de> 52 Active arm arm1136 mx35 - - woodburn - Stefano Babic <sbabic@denx.de>
53 Active arm arm1136 mx35 - woodburn woodburn_sd woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg - 53 Active arm arm1136 mx35 - woodburn woodburn_sd woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg -
54 Active arm arm1136 mx35 CarMediaLab - flea3 - Stefano Babic <sbabic@denx.de> 54 Active arm arm1136 mx35 CarMediaLab - flea3 - Stefano Babic <sbabic@denx.de>
55 Active arm arm1136 mx35 freescale - mx35pdk - Stefano Babic <sbabic@denx.de> 55 Active arm arm1136 mx35 freescale - mx35pdk - Stefano Babic <sbabic@denx.de>
56 Active arm arm1176 bcm2835 raspberrypi rpi_b rpi_b - Stephen Warren <swarren@wwwdotorg.org> 56 Active arm arm1176 bcm2835 raspberrypi rpi_b rpi_b - Stephen Warren <swarren@wwwdotorg.org>
57 Active arm arm1176 tnetv107x ti tnetv107xevm tnetv107x_evm - Chan-Taek Park <c-park@ti.com> 57 Active arm arm1176 tnetv107x ti tnetv107xevm tnetv107x_evm - Chan-Taek Park <c-park@ti.com>
58 Active arm arm720t - armltd integrator integratorap_cm720t integratorap:CM720T Linus Walleij <linus.walleij@linaro.org> 58 Active arm arm720t - armltd integrator integratorap_cm720t integratorap:CM720T Linus Walleij <linus.walleij@linaro.org>
59 Active arm arm920t - armltd integrator integratorap_cm920t integratorap:CM920T Linus Walleij <linus.walleij@linaro.org> 59 Active arm arm920t - armltd integrator integratorap_cm920t integratorap:CM920T Linus Walleij <linus.walleij@linaro.org>
60 Active arm arm920t - armltd integrator integratorcp_cm920t integratorcp:CM920T Linus Walleij <linus.walleij@linaro.org> 60 Active arm arm920t - armltd integrator integratorcp_cm920t integratorcp:CM920T Linus Walleij <linus.walleij@linaro.org>
61 Active arm arm920t a320 faraday - a320evb - Po-Yu Chuang <ratbert@faraday-tech.com> 61 Active arm arm920t a320 faraday - a320evb - Po-Yu Chuang <ratbert@faraday-tech.com>
62 Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek at91rm9200ek Andreas BieรŸmann <andreas.devel@gmail.com> 62 Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek at91rm9200ek Andreas BieรŸmann <andreas.devel@gmail.com>
63 Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek_ram at91rm9200ek:RAMBOOT Andreas BieรŸmann <andreas.devel@gmail.com> 63 Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek_ram at91rm9200ek:RAMBOOT Andreas BieรŸmann <andreas.devel@gmail.com>
64 Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2 eb_cpux9k2 Jens Scharsig <esw@bus-elektronik.de> 64 Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2 eb_cpux9k2 Jens Scharsig <esw@bus-elektronik.de>
65 Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2_ram eb_cpux9k2:RAMBOOT Jens Scharsig <esw@bus-elektronik.de> 65 Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2_ram eb_cpux9k2:RAMBOOT Jens Scharsig <esw@bus-elektronik.de>
66 Active arm arm920t at91 eukrea cpuat91 cpuat91 cpuat91 Eric Benard <eric@eukrea.com> 66 Active arm arm920t at91 eukrea cpuat91 cpuat91 cpuat91 Eric Benard <eric@eukrea.com>
67 Active arm arm920t at91 eukrea cpuat91 cpuat91_ram cpuat91:RAMBOOT Eric Benard <eric@eukrea.com> 67 Active arm arm920t at91 eukrea cpuat91 cpuat91_ram cpuat91:RAMBOOT Eric Benard <eric@eukrea.com>
68 Active arm arm920t imx - - mx1ads - - 68 Active arm arm920t imx - - mx1ads - -
69 Active arm arm920t imx - - scb9328 - Torsten Koschorrek <koschorrek@synertronixx.de> 69 Active arm arm920t imx - - scb9328 - Torsten Koschorrek <koschorrek@synertronixx.de>
70 Active arm arm920t ks8695 - - cm4008 - Greg Ungerer <greg.ungerer@opengear.com> 70 Active arm arm920t ks8695 - - cm4008 - Greg Ungerer <greg.ungerer@opengear.com>
71 Active arm arm920t ks8695 - - cm41xx - - 71 Active arm arm920t ks8695 - - cm41xx - -
72 Active arm arm920t s3c24x0 friendlyarm mini2440 mini2440 - Gabriel Huau <contact@huau-gabriel.fr> 72 Active arm arm920t s3c24x0 friendlyarm mini2440 mini2440 - Gabriel Huau <contact@huau-gabriel.fr>
73 Active arm arm920t s3c24x0 mpl vcma9 VCMA9 - David Mรผller <d.mueller@elsoft.ch> 73 Active arm arm920t s3c24x0 mpl vcma9 VCMA9 - David Mรผller <d.mueller@elsoft.ch>
74 Active arm arm920t s3c24x0 samsung - smdk2410 - David Mรผller <d.mueller@elsoft.ch> 74 Active arm arm920t s3c24x0 samsung - smdk2410 - David Mรผller <d.mueller@elsoft.ch>
75 Active arm arm926ejs - armltd integrator integratorap_cm926ejs integratorap:CM926EJ_S Linus Walleij <linus.walleij@linaro.org> 75 Active arm arm926ejs - armltd integrator integratorap_cm926ejs integratorap:CM926EJ_S Linus Walleij <linus.walleij@linaro.org>
76 Active arm arm926ejs - armltd integrator integratorcp_cm926ejs integratorcp:CM924EJ_S Linus Walleij <linus.walleij@linaro.org> 76 Active arm arm926ejs - armltd integrator integratorcp_cm926ejs integratorcp:CM924EJ_S Linus Walleij <linus.walleij@linaro.org>
77 Active arm arm926ejs armada100 Marvell - aspenite - Prafulla Wadaskar <prafulla@marvell.com> 77 Active arm arm926ejs armada100 Marvell - aspenite - Prafulla Wadaskar <prafulla@marvell.com>
78 Active arm arm926ejs armada100 Marvell - gplugd - Ajay Bhargav <ajay.bhargav@einfochips.com> 78 Active arm arm926ejs armada100 Marvell - gplugd - Ajay Bhargav <ajay.bhargav@einfochips.com>
79 Active arm arm926ejs at91 - - afeb9260 - Sergey Lapin <slapin@ossfans.org> 79 Active arm arm926ejs at91 - - afeb9260 - Sergey Lapin <slapin@ossfans.org>
80 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs0 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net> 80 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs0 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
81 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs1 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net> 81 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs1 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net>
82 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_nandflash at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net> 82 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_nandflash at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
83 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_2mmc_nandflash at91sam9260ek:AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net> 83 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_2mmc_nandflash at91sam9260ek:AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
84 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_dataflash_cs0 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net> 84 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_dataflash_cs0 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
85 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_dataflash_cs1 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net> 85 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_dataflash_cs1 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net>
86 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_mmc at91sam9260ek:AT91SAM9G20,SYS_USE_MMC Stelian Pop <stelian@popies.net> 86 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_mmc at91sam9260ek:AT91SAM9G20,SYS_USE_MMC Stelian Pop <stelian@popies.net>
87 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_nandflash at91sam9260ek:AT91SAM9G20,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net> 87 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_nandflash at91sam9260ek:AT91SAM9G20,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
88 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_dataflash_cs0 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net> 88 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_dataflash_cs0 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
89 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_dataflash_cs1 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net> 89 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_dataflash_cs1 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net>
90 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_nandflash at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net> 90 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_nandflash at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
91 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_dataflash_cs0 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net> 91 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_dataflash_cs0 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
92 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_dataflash_cs3 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS3 Stelian Pop <stelian@popies.net> 92 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_dataflash_cs3 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS3 Stelian Pop <stelian@popies.net>
93 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_nandflash at91sam9261ek:AT91SAM9261,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net> 93 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_nandflash at91sam9261ek:AT91SAM9261,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
94 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_dataflash_cs0 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net> 94 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_dataflash_cs0 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
95 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_dataflash_cs3 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS3 Stelian Pop <stelian@popies.net> 95 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_dataflash_cs3 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS3 Stelian Pop <stelian@popies.net>
96 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_nandflash at91sam9261ek:AT91SAM9G10,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net> 96 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_nandflash at91sam9261ek:AT91SAM9G10,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
97 Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_dataflash at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net> 97 Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_dataflash at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net>
98 Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_dataflash_cs0 at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net> 98 Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_dataflash_cs0 at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net>
99 Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_nandflash at91sam9263ek:AT91SAM9263,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net> 99 Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_nandflash at91sam9263ek:AT91SAM9263,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
100 Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash at91sam9263ek:AT91SAM9263,SYS_USE_NORFLASH Stelian Pop <stelian@popies.net> 100 Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash at91sam9263ek:AT91SAM9263,SYS_USE_NORFLASH Stelian Pop <stelian@popies.net>
101 Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash_boot at91sam9263ek:AT91SAM9263,SYS_USE_BOOT_NORFLASH Stelian Pop <stelian@popies.net> 101 Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash_boot at91sam9263ek:AT91SAM9263,SYS_USE_BOOT_NORFLASH Stelian Pop <stelian@popies.net>
102 Active arm arm926ejs at91 atmel at91sam9m10g45ek at91sam9m10g45ek_nandflash at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH Bo Shen<voice.shen@atmel.com> 102 Active arm arm926ejs at91 atmel at91sam9m10g45ek at91sam9m10g45ek_nandflash at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH Bo Shen<voice.shen@atmel.com>
103 Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_mmc at91sam9n12ek:AT91SAM9N12,SYS_USE_MMC Josh Wu <josh.wu@atmel.com> 103 Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_mmc at91sam9n12ek:AT91SAM9N12,SYS_USE_MMC Josh Wu <josh.wu@atmel.com>
104 Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_nandflash at91sam9n12ek:AT91SAM9N12,SYS_USE_NANDFLASH Josh Wu <josh.wu@atmel.com> 104 Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_nandflash at91sam9n12ek:AT91SAM9N12,SYS_USE_NANDFLASH Josh Wu <josh.wu@atmel.com>
105 Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_spiflash at91sam9n12ek:AT91SAM9N12,SYS_USE_SPIFLASH Josh Wu <josh.wu@atmel.com> 105 Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_spiflash at91sam9n12ek:AT91SAM9N12,SYS_USE_SPIFLASH Josh Wu <josh.wu@atmel.com>
106 Active arm arm926ejs at91 atmel at91sam9rlek at91sam9rlek_dataflash at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net> 106 Active arm arm926ejs at91 atmel at91sam9rlek at91sam9rlek_dataflash at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net>
107 Active arm arm926ejs at91 atmel at91sam9rlek at91sam9rlek_nandflash at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net> 107 Active arm arm926ejs at91 atmel at91sam9rlek at91sam9rlek_nandflash at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
108 Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_dataflash at91sam9x5ek:AT91SAM9X5,SYS_USE_DATAFLASH Bo Shen <voice.shen@atmel.com> 108 Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_dataflash at91sam9x5ek:AT91SAM9X5,SYS_USE_DATAFLASH Bo Shen <voice.shen@atmel.com>
109 Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_mmc at91sam9x5ek:AT91SAM9X5,SYS_USE_MMC Bo Shen <voice.shen@atmel.com> 109 Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_mmc at91sam9x5ek:AT91SAM9X5,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
110 Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_nandflash at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com> 110 Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_nandflash at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com>
111 Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_spiflash at91sam9x5ek:AT91SAM9X5,SYS_USE_SPIFLASH Bo Shen <voice.shen@atmel.com> 111 Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_spiflash at91sam9x5ek:AT91SAM9X5,SYS_USE_SPIFLASH Bo Shen <voice.shen@atmel.com>
112 Active arm arm926ejs at91 bluewater - snapper9260 snapper9260:AT91SAM9260 Ryan Mallon <ryan@bluewatersys.com> 112 Active arm arm926ejs at91 bluewater - snapper9260 snapper9260:AT91SAM9260 Ryan Mallon <ryan@bluewatersys.com>
113 Active arm arm926ejs at91 bluewater snapper9260 snapper9g20 snapper9260:AT91SAM9G20 Ryan Mallon <ryan@bluewatersys.com> 113 Active arm arm926ejs at91 bluewater snapper9260 snapper9g20 snapper9260:AT91SAM9G20 Ryan Mallon <ryan@bluewatersys.com>
114 Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc - Jens Scharsig <esw@bus-elektronik.de> 114 Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc - Jens Scharsig <esw@bus-elektronik.de>
115 Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc_ram vl_ma2sc:RAMLOAD Jens Scharsig <esw@bus-elektronik.de> 115 Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc_ram vl_ma2sc:RAMLOAD Jens Scharsig <esw@bus-elektronik.de>
116 Active arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_eeprom sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com> 116 Active arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_eeprom sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
117 Active arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_nandflash sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com> 117 Active arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_nandflash sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
118 Active arm arm926ejs at91 calao tny_a9260 tny_a9260_eeprom tny_a9260:AT91SAM9260,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com> 118 Active arm arm926ejs at91 calao tny_a9260 tny_a9260_eeprom tny_a9260:AT91SAM9260,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
119 Active arm arm926ejs at91 calao tny_a9260 tny_a9260_nandflash tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com> 119 Active arm arm926ejs at91 calao tny_a9260 tny_a9260_nandflash tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
120 Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_eeprom tny_a9260:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com> 120 Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_eeprom tny_a9260:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
121 Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_nandflash tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com> 121 Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_nandflash tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
122 Active arm arm926ejs at91 calao usb_a9263 usb_a9263_dataflash usb_a9263:AT91SAM9263,SYS_USE_DATAFLASH Mateusz Kulikowski <mateusz.kulikowski@gmail.com> 122 Active arm arm926ejs at91 calao usb_a9263 usb_a9263_dataflash usb_a9263:AT91SAM9263,SYS_USE_DATAFLASH Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
123 Active arm arm926ejs at91 egnite ethernut5 ethernut5 ethernut5:AT91SAM9XE egnite GmbH <info@egnite.de> 123 Active arm arm926ejs at91 egnite ethernut5 ethernut5 ethernut5:AT91SAM9XE egnite GmbH <info@egnite.de>
124 Active arm arm926ejs at91 emk top9000 top9000eval_xe top9000:EVAL9000 Reinhard Meyer <reinhard.meyer@emk-elektronik.de> 124 Active arm arm926ejs at91 emk top9000 top9000eval_xe top9000:EVAL9000 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
125 Active arm arm926ejs at91 emk top9000 top9000su_xe top9000:SU9000 Reinhard Meyer <reinhard.meyer@emk-elektronik.de> 125 Active arm arm926ejs at91 emk top9000 top9000su_xe top9000:SU9000 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
126 Active arm arm926ejs at91 esd meesc meesc meesc:AT91SAM9263,SYS_USE_NANDFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu> 126 Active arm arm926ejs at91 esd meesc meesc meesc:AT91SAM9263,SYS_USE_NANDFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
127 Active arm arm926ejs at91 esd meesc meesc_dataflash meesc:AT91SAM9263,SYS_USE_DATAFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu> 127 Active arm arm926ejs at91 esd meesc meesc_dataflash meesc:AT91SAM9263,SYS_USE_DATAFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
128 Active arm arm926ejs at91 esd otc570 otc570 otc570:AT91SAM9263,SYS_USE_NANDFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu> 128 Active arm arm926ejs at91 esd otc570 otc570 otc570:AT91SAM9263,SYS_USE_NANDFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
129 Active arm arm926ejs at91 esd otc570 otc570_dataflash otc570:AT91SAM9263,SYS_USE_DATAFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu> 129 Active arm arm926ejs at91 esd otc570 otc570_dataflash otc570:AT91SAM9263,SYS_USE_DATAFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
130 Active arm arm926ejs at91 eukrea cpu9260 cpu9260 cpu9260:CPU9260 Eric Benard <eric@eukrea.com> 130 Active arm arm926ejs at91 eukrea cpu9260 cpu9260 cpu9260:CPU9260 Eric Benard <eric@eukrea.com>
131 Active arm arm926ejs at91 eukrea cpu9260 cpu9260_128M cpu9260:CPU9260,CPU9260_128M Eric Benard <eric@eukrea.com> 131 Active arm arm926ejs at91 eukrea cpu9260 cpu9260_128M cpu9260:CPU9260,CPU9260_128M Eric Benard <eric@eukrea.com>
132 Active arm arm926ejs at91 eukrea cpu9260 cpu9260_nand cpu9260:CPU9260,NANDBOOT Eric Benard <eric@eukrea.com> 132 Active arm arm926ejs at91 eukrea cpu9260 cpu9260_nand cpu9260:CPU9260,NANDBOOT Eric Benard <eric@eukrea.com>
133 Active arm arm926ejs at91 eukrea cpu9260 cpu9260_nand_128M cpu9260:CPU9260,CPU9260_128M,NANDBOOT Eric Benard <eric@eukrea.com> 133 Active arm arm926ejs at91 eukrea cpu9260 cpu9260_nand_128M cpu9260:CPU9260,CPU9260_128M,NANDBOOT Eric Benard <eric@eukrea.com>
134 Active arm arm926ejs at91 eukrea cpu9260 cpu9G20 cpu9260:CPU9G20 Eric Benard <eric@eukrea.com> 134 Active arm arm926ejs at91 eukrea cpu9260 cpu9G20 cpu9260:CPU9G20 Eric Benard <eric@eukrea.com>
135 Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_128M cpu9260:CPU9G20,CPU9G20_128M Eric Benard <eric@eukrea.com> 135 Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_128M cpu9260:CPU9G20,CPU9G20_128M Eric Benard <eric@eukrea.com>
136 Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_nand cpu9260:CPU9G20,NANDBOOT Eric Benard <eric@eukrea.com> 136 Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_nand cpu9260:CPU9G20,NANDBOOT Eric Benard <eric@eukrea.com>
137 Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_nand_128M cpu9260:CPU9G20,CPU9G20_128M,NANDBOOT Eric Benard <eric@eukrea.com> 137 Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_nand_128M cpu9260:CPU9G20,CPU9G20_128M,NANDBOOT Eric Benard <eric@eukrea.com>
138 Active arm arm926ejs at91 ronetix pm9261 pm9261 pm9261:AT91SAM9261 Ilko Iliev <iliev@ronetix.at> 138 Active arm arm926ejs at91 ronetix pm9261 pm9261 pm9261:AT91SAM9261 Ilko Iliev <iliev@ronetix.at>
139 Active arm arm926ejs at91 ronetix pm9263 pm9263 pm9263:AT91SAM9263 Ilko Iliev <iliev@ronetix.at> 139 Active arm arm926ejs at91 ronetix pm9263 pm9263 pm9263:AT91SAM9263 Ilko Iliev <iliev@ronetix.at>
140 Active arm arm926ejs at91 ronetix pm9g45 pm9g45 pm9g45:AT91SAM9G45 Ilko Iliev <iliev@ronetix.at> 140 Active arm arm926ejs at91 ronetix pm9g45 pm9g45 pm9g45:AT91SAM9G45 Ilko Iliev <iliev@ronetix.at>
141 Active arm arm926ejs at91 taskit stamp9g20 portuxg20 stamp9g20:AT91SAM9G20,PORTUXG20 Markus Hubig <mhubig@imko.de> 141 Active arm arm926ejs at91 taskit stamp9g20 portuxg20 stamp9g20:AT91SAM9G20,PORTUXG20 Markus Hubig <mhubig@imko.de>
142 Active arm arm926ejs at91 taskit stamp9g20 stamp9g20 stamp9g20:AT91SAM9G20 Markus Hubig <mhubig@imko.de> 142 Active arm arm926ejs at91 taskit stamp9g20 stamp9g20 stamp9g20:AT91SAM9G20 Markus Hubig <mhubig@imko.de>
143 Active arm arm926ejs at91 siemens taurus axm taurus:AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM Heiko Schocher <hs@denx.de> 143 Active arm arm926ejs at91 siemens taurus axm taurus:AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM Heiko Schocher <hs@denx.de>
144 Active arm arm926ejs at91 siemens corvus corvus corvus:AT91SAM9M10G45,SYS_USE_NANDFLASH Heiko Schocher <hs@denx.de> 144 Active arm arm926ejs at91 siemens corvus corvus corvus:AT91SAM9M10G45,SYS_USE_NANDFLASH Heiko Schocher <hs@denx.de>
145 Active arm arm926ejs at91 siemens taurus taurus taurus:AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS Heiko Schocher <hs@denx.de> 145 Active arm arm926ejs at91 siemens taurus taurus taurus:AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS Heiko Schocher <hs@denx.de>
146 Active arm arm926ejs davinci ait cam_enc_4xx cam_enc_4xx cam_enc_4xx Heiko Schocher <hs@denx.de> 146 Active arm arm926ejs davinci ait cam_enc_4xx cam_enc_4xx cam_enc_4xx Heiko Schocher <hs@denx.de>
147 Active arm arm926ejs davinci Barix ipam390 ipam390 - Heiko Schocher <hs@denx.de> 147 Active arm arm926ejs davinci Barix ipam390 ipam390 - Heiko Schocher <hs@denx.de>
148 Active arm arm926ejs davinci davinci da8xxevm da830evm - Nick Thompson <nick.thompson@gefanuc.com> 148 Active arm arm926ejs davinci davinci da8xxevm da830evm - Nick Thompson <nick.thompson@gefanuc.com>
149 Active arm arm926ejs davinci davinci da8xxevm da850_am18xxevm da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50 Sudhakar Rajashekhara <sudhakar.raj@ti.com> 149 Active arm arm926ejs davinci davinci da8xxevm da850_am18xxevm da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50 Sudhakar Rajashekhara <sudhakar.raj@ti.com>
150 Active arm arm926ejs davinci davinci da8xxevm da850evm da850evm:MAC_ADDR_IN_SPIFLASH Sudhakar Rajashekhara <sudhakar.raj@ti.com> 150 Active arm arm926ejs davinci davinci da8xxevm da850evm da850evm:MAC_ADDR_IN_SPIFLASH Sudhakar Rajashekhara <sudhakar.raj@ti.com>
151 Active arm arm926ejs davinci davinci da8xxevm da850evm_direct_nor da850evm:MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT Sudhakar Rajashekhara <sudhakar.raj@ti.com> 151 Active arm arm926ejs davinci davinci da8xxevm da850evm_direct_nor da850evm:MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT Sudhakar Rajashekhara <sudhakar.raj@ti.com>
152 Active arm arm926ejs davinci davinci da8xxevm hawkboard - Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com> 152 Active arm arm926ejs davinci davinci da8xxevm hawkboard - Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
153 Active arm arm926ejs davinci davinci da8xxevm hawkboard_uart hawkboard:UART_U_BOOT Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com> 153 Active arm arm926ejs davinci davinci da8xxevm hawkboard_uart hawkboard:UART_U_BOOT Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
154 Active arm arm926ejs davinci davinci dm355evm davinci_dm355evm - Sandeep Paulraj <s-paulraj@ti.com> 154 Active arm arm926ejs davinci davinci dm355evm davinci_dm355evm - Sandeep Paulraj <s-paulraj@ti.com>
155 Active arm arm926ejs davinci davinci dm355leopard davinci_dm355leopard - Sandeep Paulraj <s-paulraj@ti.com> 155 Active arm arm926ejs davinci davinci dm355leopard davinci_dm355leopard - Sandeep Paulraj <s-paulraj@ti.com>
156 Active arm arm926ejs davinci davinci dm365evm davinci_dm365evm - Sandeep Paulraj <s-paulraj@ti.com> 156 Active arm arm926ejs davinci davinci dm365evm davinci_dm365evm - Sandeep Paulraj <s-paulraj@ti.com>
157 Active arm arm926ejs davinci davinci dm6467evm davinci_dm6467evm davinci_dm6467evm:REFCLK_FREQ=27000000 Sandeep Paulraj <s-paulraj@ti.com> 157 Active arm arm926ejs davinci davinci dm6467evm davinci_dm6467evm davinci_dm6467evm:REFCLK_FREQ=27000000 Sandeep Paulraj <s-paulraj@ti.com>
158 Active arm arm926ejs davinci davinci dm6467evm davinci_dm6467Tevm davinci_dm6467evm:DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000 Sandeep Paulraj <s-paulraj@ti.com> 158 Active arm arm926ejs davinci davinci dm6467evm davinci_dm6467Tevm davinci_dm6467evm:DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000 Sandeep Paulraj <s-paulraj@ti.com>
159 Active arm arm926ejs davinci davinci dvevm davinci_dvevm - - 159 Active arm arm926ejs davinci davinci dvevm davinci_dvevm - -
160 Active arm arm926ejs davinci davinci ea20 ea20 - Stefano Babic <sbabic@denx.de> 160 Active arm arm926ejs davinci davinci ea20 ea20 - Stefano Babic <sbabic@denx.de>
161 Active arm arm926ejs davinci davinci schmoogie davinci_schmoogie - - 161 Active arm arm926ejs davinci davinci schmoogie davinci_schmoogie - -
162 Active arm arm926ejs davinci davinci sffsdr davinci_sffsdr - - 162 Active arm arm926ejs davinci davinci sffsdr davinci_sffsdr - -
163 Active arm arm926ejs davinci davinci sonata davinci_sonata - - 163 Active arm arm926ejs davinci davinci sonata davinci_sonata - -
164 Active arm arm926ejs davinci enbw enbw_cmc enbw_cmc - Heiko Schocher <hs@denx.de> 164 Active arm arm926ejs davinci enbw enbw_cmc enbw_cmc - Heiko Schocher <hs@denx.de>
165 Active arm arm926ejs davinci omicron calimain calimain - Manfred Rudigier <manfred.rudigier@omicron.at>:Christian Riesch <christian.riesch@omicron.at> 165 Active arm arm926ejs davinci omicron calimain calimain - Manfred Rudigier <manfred.rudigier@omicron.at>:Christian Riesch <christian.riesch@omicron.at>
166 Active arm arm926ejs kirkwood buffalo lsxl lschlv2 lsxl:LSCHLV2 Michael Walle <michael@walle.cc> 166 Active arm arm926ejs kirkwood buffalo lsxl lschlv2 lsxl:LSCHLV2 Michael Walle <michael@walle.cc>
167 Active arm arm926ejs kirkwood buffalo lsxl lsxhl lsxl:LSXHL Michael Walle <michael@walle.cc> 167 Active arm arm926ejs kirkwood buffalo lsxl lsxhl lsxl:LSXHL Michael Walle <michael@walle.cc>
168 Active arm arm926ejs kirkwood cloudengines - pogo_e02 - Dave Purdy <david.c.purdy@gmail.com> 168 Active arm arm926ejs kirkwood cloudengines - pogo_e02 - Dave Purdy <david.c.purdy@gmail.com>
169 Active arm arm926ejs kirkwood d-link - dns325 - Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net> 169 Active arm arm926ejs kirkwood d-link - dns325 - Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
170 Active arm arm926ejs kirkwood iomega - iconnect - Luka Perkov <luka@openwrt.org> 170 Active arm arm926ejs kirkwood iomega - iconnect - Luka Perkov <luka@openwrt.org>
171 Active arm arm926ejs kirkwood karo tk71 tk71 - - 171 Active arm arm926ejs kirkwood karo tk71 tk71 - -
172 Active arm arm926ejs kirkwood keymile km_arm km_kirkwood km_kirkwood:KM_KIRKWOOD Valentin Longchamp <valentin.longchamp@keymile.com> 172 Active arm arm926ejs kirkwood keymile km_arm km_kirkwood km_kirkwood:KM_KIRKWOOD Valentin Longchamp <valentin.longchamp@keymile.com>
173 Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_pci km_kirkwood:KM_KIRKWOOD_PCI Valentin Longchamp <valentin.longchamp@keymile.com> 173 Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_pci km_kirkwood:KM_KIRKWOOD_PCI Valentin Longchamp <valentin.longchamp@keymile.com>
174 Active arm arm926ejs kirkwood keymile km_arm kmcoge5un km_kirkwood:KM_COGE5UN Valentin Longchamp <valentin.longchamp@keymile.com> 174 Active arm arm926ejs kirkwood keymile km_arm kmcoge5un km_kirkwood:KM_COGE5UN Valentin Longchamp <valentin.longchamp@keymile.com>
175 Active arm arm926ejs kirkwood keymile km_arm kmnusa km_kirkwood:KM_NUSA Valentin Longchamp <valentin.longchamp@keymile.com> 175 Active arm arm926ejs kirkwood keymile km_arm kmnusa km_kirkwood:KM_NUSA Valentin Longchamp <valentin.longchamp@keymile.com>
176 Active arm arm926ejs kirkwood keymile km_arm kmsuv31 km_kirkwood:KM_SUV31 Valentin Longchamp <valentin.longchamp@keymile.com> 176 Active arm arm926ejs kirkwood keymile km_arm kmsuv31 km_kirkwood:KM_SUV31 Valentin Longchamp <valentin.longchamp@keymile.com>
177 Active arm arm926ejs kirkwood keymile km_arm mgcoge3un km_kirkwood:KM_MGCOGE3UN Valentin Longchamp <valentin.longchamp@keymile.com> 177 Active arm arm926ejs kirkwood keymile km_arm mgcoge3un km_kirkwood:KM_MGCOGE3UN Valentin Longchamp <valentin.longchamp@keymile.com>
178 Active arm arm926ejs kirkwood keymile km_arm portl2 km_kirkwood:KM_PORTL2 Valentin Longchamp <valentin.longchamp@keymile.com> 178 Active arm arm926ejs kirkwood keymile km_arm portl2 km_kirkwood:KM_PORTL2 Valentin Longchamp <valentin.longchamp@keymile.com>
179 Active arm arm926ejs kirkwood LaCie net2big_v2 d2net_v2 lacie_kw:D2NET_V2 - 179 Active arm arm926ejs kirkwood LaCie net2big_v2 d2net_v2 lacie_kw:D2NET_V2 -
180 Active arm arm926ejs kirkwood LaCie net2big_v2 net2big_v2 lacie_kw:NET2BIG_V2 Simon Guinot <simon.guinot@sequanux.org> 180 Active arm arm926ejs kirkwood LaCie net2big_v2 net2big_v2 lacie_kw:NET2BIG_V2 Simon Guinot <simon.guinot@sequanux.org>
181 Active arm arm926ejs kirkwood LaCie netspace_v2 inetspace_v2 lacie_kw:INETSPACE_V2 Simon Guinot <simon.guinot@sequanux.org> 181 Active arm arm926ejs kirkwood LaCie netspace_v2 inetspace_v2 lacie_kw:INETSPACE_V2 Simon Guinot <simon.guinot@sequanux.org>
182 Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_lite_v2 lacie_kw:NETSPACE_LITE_V2 - 182 Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_lite_v2 lacie_kw:NETSPACE_LITE_V2 -
183 Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_max_v2 lacie_kw:NETSPACE_MAX_V2 Simon Guinot <simon.guinot@sequanux.org> 183 Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_max_v2 lacie_kw:NETSPACE_MAX_V2 Simon Guinot <simon.guinot@sequanux.org>
184 Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_mini_v2 lacie_kw:NETSPACE_MINI_V2 - 184 Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_mini_v2 lacie_kw:NETSPACE_MINI_V2 -
185 Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_v2 lacie_kw:NETSPACE_V2 Simon Guinot <simon.guinot@sequanux.org> 185 Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_v2 lacie_kw:NETSPACE_V2 Simon Guinot <simon.guinot@sequanux.org>
186 Active arm arm926ejs kirkwood LaCie wireless_space wireless_space - - 186 Active arm arm926ejs kirkwood LaCie wireless_space wireless_space - -
187 Active arm arm926ejs kirkwood Marvell - dreamplug - Jason Cooper <u-boot@lakedaemon.net> 187 Active arm arm926ejs kirkwood Marvell - dreamplug - Jason Cooper <u-boot@lakedaemon.net>
188 Active arm arm926ejs kirkwood Marvell - guruplug - Siddarth Gore <gores@marvell.com> 188 Active arm arm926ejs kirkwood Marvell - guruplug - Siddarth Gore <gores@marvell.com>
189 Active arm arm926ejs kirkwood Marvell - mv88f6281gtw_ge - Prafulla Wadaskar <prafulla@marvell.com> 189 Active arm arm926ejs kirkwood Marvell - mv88f6281gtw_ge - Prafulla Wadaskar <prafulla@marvell.com>
190 Active arm arm926ejs kirkwood Marvell - rd6281a - Prafulla Wadaskar <prafulla@marvell.com> 190 Active arm arm926ejs kirkwood Marvell - rd6281a - Prafulla Wadaskar <prafulla@marvell.com>
191 Active arm arm926ejs kirkwood Marvell - sheevaplug - Prafulla Wadaskar <prafulla@marvell.com> 191 Active arm arm926ejs kirkwood Marvell - sheevaplug - Prafulla Wadaskar <prafulla@marvell.com>
192 Active arm arm926ejs kirkwood Marvell openrd openrd_base openrd:BOARD_IS_OPENRD_BASE Prafulla Wadaskar <prafulla@marvell.com> 192 Active arm arm926ejs kirkwood Marvell openrd openrd_base openrd:BOARD_IS_OPENRD_BASE Prafulla Wadaskar <prafulla@marvell.com>
193 Active arm arm926ejs kirkwood Marvell openrd openrd_client openrd:BOARD_IS_OPENRD_CLIENT - 193 Active arm arm926ejs kirkwood Marvell openrd openrd_client openrd:BOARD_IS_OPENRD_CLIENT -
194 Active arm arm926ejs kirkwood Marvell openrd openrd_ultimate openrd:BOARD_IS_OPENRD_ULTIMATE - 194 Active arm arm926ejs kirkwood Marvell openrd openrd_ultimate openrd:BOARD_IS_OPENRD_ULTIMATE -
195 Active arm arm926ejs kirkwood raidsonic ib62x0 ib62x0 - Luka Perkov <luka@openwrt.org> 195 Active arm arm926ejs kirkwood raidsonic ib62x0 ib62x0 - Luka Perkov <luka@openwrt.org>
196 Active arm arm926ejs kirkwood Seagate - dockstar - Eric Cooper <ecc@cmu.edu> 196 Active arm arm926ejs kirkwood Seagate - dockstar - Eric Cooper <ecc@cmu.edu>
197 Active arm arm926ejs kirkwood Seagate - goflexhome - Suriyan Ramasami <suriyan.r@gmail.com> 197 Active arm arm926ejs kirkwood Seagate - goflexhome - Suriyan Ramasami <suriyan.r@gmail.com>
198 Active arm arm926ejs lpc32xx timll devkit3250 devkit3250 - Vladimir Zapolskiy <vz@mleia.com> 198 Active arm arm926ejs lpc32xx timll devkit3250 devkit3250 - Vladimir Zapolskiy <vz@mleia.com>
199 Active arm arm926ejs mb86r0x syteco jadecpu jadecpu - Matthias Weisser <weisserm@arcor.de> 199 Active arm arm926ejs mb86r0x syteco jadecpu jadecpu - Matthias Weisser <weisserm@arcor.de>
200 Active arm arm926ejs mx25 freescale mx25pdk mx25pdk mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg Fabio Estevam <fabio.estevam@freescale.com> 200 Active arm arm926ejs mx25 freescale mx25pdk mx25pdk mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg Fabio Estevam <fabio.estevam@freescale.com>
201 Active arm arm926ejs mx25 karo tx25 tx25 - John Rigby <jcrigby@gmail.com> 201 Active arm arm926ejs mx25 karo tx25 tx25 - John Rigby <jcrigby@gmail.com>
202 Active arm arm926ejs mx25 syteco zmx25 zmx25 - Matthias Weisser <weisserm@arcor.de> 202 Active arm arm926ejs mx25 syteco zmx25 zmx25 - Matthias Weisser <weisserm@arcor.de>
203 Active arm arm926ejs mx27 armadeus apf27 apf27 - Philippe Reynes <tremyfr@yahoo.fr>:Eric Jarrige <eric.jarrige@armadeus.org> 203 Active arm arm926ejs mx27 armadeus apf27 apf27 - Philippe Reynes <tremyfr@yahoo.fr>:Eric Jarrige <eric.jarrige@armadeus.org>
204 Active arm arm926ejs mx27 logicpd imx27lite imx27lite - Wolfgang Denk <wd@denx.de> 204 Active arm arm926ejs mx27 logicpd imx27lite imx27lite - Wolfgang Denk <wd@denx.de>
205 Active arm arm926ejs mx27 logicpd imx27lite magnesium - Heiko Schocher <hs@denx.de> 205 Active arm arm926ejs mx27 logicpd imx27lite magnesium - Heiko Schocher <hs@denx.de>
206 Active arm arm926ejs mxs bluegiga apx4devkit apx4devkit apx4devkit Lauri Hintsala <lauri.hintsala@bluegiga.com> 206 Active arm arm926ejs mxs bluegiga apx4devkit apx4devkit apx4devkit Lauri Hintsala <lauri.hintsala@bluegiga.com>
207 Active arm arm926ejs mxs creative xfi3 xfi3 - Marek Vasut <marek.vasut@gmail.com> 207 Active arm arm926ejs mxs creative xfi3 xfi3 - Marek Vasut <marek.vasut@gmail.com>
208 Active arm arm926ejs mxs denx m28evk m28evk m28evk Marek Vasut <marek.vasut@gmail.com> 208 Active arm arm926ejs mxs denx m28evk m28evk m28evk Marek Vasut <marek.vasut@gmail.com>
209 Active arm arm926ejs mxs freescale mx23evk mx23evk mx23evk Otavio Salvador <otavio@ossystems.com.br> 209 Active arm arm926ejs mxs freescale mx23evk mx23evk mx23evk Otavio Salvador <otavio@ossystems.com.br>
210 Active arm arm926ejs mxs freescale mx28evk mx28evk mx28evk:ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com> 210 Active arm arm926ejs mxs freescale mx28evk mx28evk mx28evk:ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com>
211 Active arm arm926ejs mxs freescale mx28evk mx28evk_auart_console mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com> 211 Active arm arm926ejs mxs freescale mx28evk mx28evk_auart_console mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com>
212 Active arm arm926ejs mxs freescale mx28evk mx28evk_nand mx28evk:ENV_IS_IN_NAND Fabio Estevam <fabio.estevam@freescale.com> 212 Active arm arm926ejs mxs freescale mx28evk mx28evk_nand mx28evk:ENV_IS_IN_NAND Fabio Estevam <fabio.estevam@freescale.com>
213 Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino mx23_olinuxino Marek Vasut <marek.vasut@gmail.com> 213 Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino mx23_olinuxino Marek Vasut <marek.vasut@gmail.com>
214 Active arm arm926ejs mxs ppcag bg0900 bg0900 bg0900 Marek Vasut <marex@denx.de> 214 Active arm arm926ejs mxs ppcag bg0900 bg0900 bg0900 Marek Vasut <marex@denx.de>
215 Active arm arm926ejs mxs sandisk sansa_fuze_plus sansa_fuze_plus - Marek Vasut <marek.vasut@gmail.com> 215 Active arm arm926ejs mxs sandisk sansa_fuze_plus sansa_fuze_plus - Marek Vasut <marek.vasut@gmail.com>
216 Active arm arm926ejs mxs schulercontrol sc_sps_1 sc_sps_1 - Marek Vasut <marek.vasut@gmail.com> 216 Active arm arm926ejs mxs schulercontrol sc_sps_1 sc_sps_1 - Marek Vasut <marek.vasut@gmail.com>
217 Active arm arm926ejs nomadik st nhk8815 nhk8815 - Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it> 217 Active arm arm926ejs nomadik st nhk8815 nhk8815 - Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
218 Active arm arm926ejs nomadik st nhk8815 nhk8815_onenand nhk8815:BOOT_ONENAND Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it> 218 Active arm arm926ejs nomadik st nhk8815 nhk8815_onenand nhk8815:BOOT_ONENAND Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
219 Active arm arm926ejs omap ti - omap5912osk - Rishi Bhattacharya <rishi@ti.com> 219 Active arm arm926ejs omap ti - omap5912osk - Rishi Bhattacharya <rishi@ti.com>
220 Active arm arm926ejs orion5x LaCie - edminiv2 - Albert ARIBAUD <albert.u.boot@aribaud.net> 220 Active arm arm926ejs orion5x LaCie - edminiv2 - Albert ARIBAUD <albert.u.boot@aribaud.net>
221 Active arm arm926ejs pantheon Marvell - dkb - Lei Wen <leiwen@marvell.com> 221 Active arm arm926ejs pantheon Marvell - dkb - Lei Wen <leiwen@marvell.com>
222 Active arm arm926ejs spear spear - x600 x600 Stefan Roese <sr@denx.de> 222 Active arm arm926ejs spear spear - x600 x600 Stefan Roese <sr@denx.de>
223 Active arm arm926ejs spear spear spear300 spear300 spear3xx_evb:spear300 Vipin Kumar <vipin.kumar@st.com> 223 Active arm arm926ejs spear spear spear300 spear300 spear3xx_evb:spear300 Vipin Kumar <vipin.kumar@st.com>
224 Active arm arm926ejs spear spear spear300 spear300_nand spear3xx_evb:spear300,nand - 224 Active arm arm926ejs spear spear spear300 spear300_nand spear3xx_evb:spear300,nand -
225 Active arm arm926ejs spear spear spear300 spear300_usbtty spear3xx_evb:spear300,usbtty - 225 Active arm arm926ejs spear spear spear300 spear300_usbtty spear3xx_evb:spear300,usbtty -
226 Active arm arm926ejs spear spear spear300 spear300_usbtty_nand spear3xx_evb:spear300,usbtty,nand - 226 Active arm arm926ejs spear spear spear300 spear300_usbtty_nand spear3xx_evb:spear300,usbtty,nand -
227 Active arm arm926ejs spear spear spear310 spear310 spear3xx_evb:spear310 Vipin Kumar <vipin.kumar@st.com> 227 Active arm arm926ejs spear spear spear310 spear310 spear3xx_evb:spear310 Vipin Kumar <vipin.kumar@st.com>
228 Active arm arm926ejs spear spear spear310 spear310_nand spear3xx_evb:spear310,nand - 228 Active arm arm926ejs spear spear spear310 spear310_nand spear3xx_evb:spear310,nand -
229 Active arm arm926ejs spear spear spear310 spear310_pnor spear3xx_evb:spear310,FLASH_PNOR - 229 Active arm arm926ejs spear spear spear310 spear310_pnor spear3xx_evb:spear310,FLASH_PNOR -
230 Active arm arm926ejs spear spear spear310 spear310_usbtty spear3xx_evb:spear310,usbtty - 230 Active arm arm926ejs spear spear spear310 spear310_usbtty spear3xx_evb:spear310,usbtty -
231 Active arm arm926ejs spear spear spear310 spear310_usbtty_nand spear3xx_evb:spear310,usbtty,nand - 231 Active arm arm926ejs spear spear spear310 spear310_usbtty_nand spear3xx_evb:spear310,usbtty,nand -
232 Active arm arm926ejs spear spear spear310 spear310_usbtty_pnor spear3xx_evb:spear310,usbtty,FLASH_PNOR - 232 Active arm arm926ejs spear spear spear310 spear310_usbtty_pnor spear3xx_evb:spear310,usbtty,FLASH_PNOR -
233 Active arm arm926ejs spear spear spear320 spear320 spear3xx_evb:spear320 Vipin Kumar <vipin.kumar@st.com> 233 Active arm arm926ejs spear spear spear320 spear320 spear3xx_evb:spear320 Vipin Kumar <vipin.kumar@st.com>
234 Active arm arm926ejs spear spear spear320 spear320_nand spear3xx_evb:spear320,nand - 234 Active arm arm926ejs spear spear spear320 spear320_nand spear3xx_evb:spear320,nand -
235 Active arm arm926ejs spear spear spear320 spear320_pnor spear3xx_evb:spear320,FLASH_PNOR - 235 Active arm arm926ejs spear spear spear320 spear320_pnor spear3xx_evb:spear320,FLASH_PNOR -
236 Active arm arm926ejs spear spear spear320 spear320_usbtty spear3xx_evb:spear320,usbtty - 236 Active arm arm926ejs spear spear spear320 spear320_usbtty spear3xx_evb:spear320,usbtty -
237 Active arm arm926ejs spear spear spear320 spear320_usbtty_nand spear3xx_evb:spear320,usbtty,nand - 237 Active arm arm926ejs spear spear spear320 spear320_usbtty_nand spear3xx_evb:spear320,usbtty,nand -
238 Active arm arm926ejs spear spear spear320 spear320_usbtty_pnor spear3xx_evb:spear320,usbtty,FLASH_PNOR - 238 Active arm arm926ejs spear spear spear320 spear320_usbtty_pnor spear3xx_evb:spear320,usbtty,FLASH_PNOR -
239 Active arm arm926ejs spear spear spear600 spear600 spear6xx_evb:spear600 Vipin Kumar <vipin.kumar@st.com> 239 Active arm arm926ejs spear spear spear600 spear600 spear6xx_evb:spear600 Vipin Kumar <vipin.kumar@st.com>
240 Active arm arm926ejs spear spear spear600 spear600_nand spear6xx_evb:spear600,nand - 240 Active arm arm926ejs spear spear spear600 spear600_nand spear6xx_evb:spear600,nand -
241 Active arm arm926ejs spear spear spear600 spear600_usbtty spear6xx_evb:spear600,usbtty - 241 Active arm arm926ejs spear spear spear600 spear600_usbtty spear6xx_evb:spear600,usbtty -
242 Active arm arm926ejs spear spear spear600 spear600_usbtty_nand spear6xx_evb:spear600,usbtty,nand - 242 Active arm arm926ejs spear spear spear600 spear600_usbtty_nand spear6xx_evb:spear600,usbtty,nand -
243 Active arm arm926ejs versatile armltd versatile versatileab versatile:ARCH_VERSATILE_AB - 243 Active arm arm926ejs versatile armltd versatile versatileab versatile:ARCH_VERSATILE_AB -
244 Active arm arm926ejs versatile armltd versatile versatilepb versatile:ARCH_VERSATILE_PB - 244 Active arm arm926ejs versatile armltd versatile versatilepb versatile:ARCH_VERSATILE_PB -
245 Active arm arm926ejs versatile armltd versatile versatileqemu versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB - 245 Active arm arm926ejs versatile armltd versatile versatileqemu versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB -
246 Active arm arm946es - armltd integrator integratorap_cm946es integratorap:CM946ES Linus Walleij <linus.walleij@linaro.org> 246 Active arm arm946es - armltd integrator integratorap_cm946es integratorap:CM946ES Linus Walleij <linus.walleij@linaro.org>
247 Active arm arm946es - armltd integrator integratorcp_cm946es integratorcp:CM946ES Linus Walleij <linus.walleij@linaro.org> 247 Active arm arm946es - armltd integrator integratorcp_cm946es integratorcp:CM946ES Linus Walleij <linus.walleij@linaro.org>
248 Active arm armv7 - armltd vexpress vexpress_ca15_tc2 - - 248 Active arm armv7 - armltd vexpress vexpress_ca15_tc2 - -
249 Active arm armv7 - armltd vexpress vexpress_ca5x2 - Matt Waddel <matt.waddel@linaro.org> 249 Active arm armv7 - armltd vexpress vexpress_ca5x2 - Matt Waddel <matt.waddel@linaro.org>
250 Active arm armv7 - armltd vexpress vexpress_ca9x4 - Matt Waddel <matt.waddel@linaro.org> 250 Active arm armv7 - armltd vexpress vexpress_ca9x4 - Matt Waddel <matt.waddel@linaro.org>
251 Active arm armv7 am33xx compulab cm_t335 cm_t335 cm_t335 Igor Grinberg <grinberg@compulab.co.il> 251 Active arm armv7 am33xx compulab cm_t335 cm_t335 cm_t335 Igor Grinberg <grinberg@compulab.co.il>
252 Active arm armv7 am33xx isee igep0033 am335x_igep0033 - Enric Balletbo i Serra <eballetbo@iseebcn.com> 252 Active arm armv7 am33xx isee igep0033 am335x_igep0033 - Enric Balletbo i Serra <eballetbo@iseebcn.com>
253 Active arm armv7 am33xx phytec pcm051 pcm051_rev1 pcm051:REV1 Lars Poeschel <poeschel@lemonage.de> 253 Active arm armv7 am33xx phytec pcm051 pcm051_rev1 pcm051:REV1 Lars Poeschel <poeschel@lemonage.de>
254 Active arm armv7 am33xx phytec pcm051 pcm051_rev3 pcm051:REV3 Lars Poeschel <poeschel@lemonage.de> 254 Active arm armv7 am33xx phytec pcm051 pcm051_rev3 pcm051:REV3 Lars Poeschel <poeschel@lemonage.de>
255 Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier@siemens.com> 255 Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier@siemens.com>
256 Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier@siemens.com> 256 Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier@siemens.com>
257 Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier@siemens.com> 257 Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier@siemens.com>
258 Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini <trini@ti.com> 258 Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini <trini@ti.com>
259 Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini <trini@ti.com> 259 Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini <trini@ti.com>
260 Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini <trini@ti.com> 260 Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini <trini@ti.com>
261 Active arm armv7 am33xx ti am335x am335x_evm_norboot am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT Tom Rini <trini@ti.com> 261 Active arm armv7 am33xx ti am335x am335x_evm_norboot am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT Tom Rini <trini@ti.com>
262 Active arm armv7 am33xx ti am335x am335x_evm_spiboot am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT Tom Rini <trini@ti.com> 262 Active arm armv7 am33xx ti am335x am335x_evm_spiboot am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT Tom Rini <trini@ti.com>
263 Active arm armv7 am33xx ti am335x am335x_evm_uart1 am335x_evm:SERIAL2,CONS_INDEX=2,NAND Tom Rini <trini@ti.com> 263 Active arm armv7 am33xx ti am335x am335x_evm_uart1 am335x_evm:SERIAL2,CONS_INDEX=2,NAND Tom Rini <trini@ti.com>
264 Active arm armv7 am33xx ti am335x am335x_evm_uart2 am335x_evm:SERIAL3,CONS_INDEX=3,NAND Tom Rini <trini@ti.com> 264 Active arm armv7 am33xx ti am335x am335x_evm_uart2 am335x_evm:SERIAL3,CONS_INDEX=3,NAND Tom Rini <trini@ti.com>
265 Active arm armv7 am33xx ti am335x am335x_evm_uart3 am335x_evm:SERIAL4,CONS_INDEX=4,NAND Tom Rini <trini@ti.com> 265 Active arm armv7 am33xx ti am335x am335x_evm_uart3 am335x_evm:SERIAL4,CONS_INDEX=4,NAND Tom Rini <trini@ti.com>
266 Active arm armv7 am33xx ti am335x am335x_evm_uart4 am335x_evm:SERIAL5,CONS_INDEX=5,NAND Tom Rini <trini@ti.com> 266 Active arm armv7 am33xx ti am335x am335x_evm_uart4 am335x_evm:SERIAL5,CONS_INDEX=5,NAND Tom Rini <trini@ti.com>
267 Active arm armv7 am33xx ti am335x am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=6,NAND Tom Rini <trini@ti.com> 267 Active arm armv7 am33xx ti am335x am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=6,NAND Tom Rini <trini@ti.com>
268 Active arm armv7 am33xx ti am335x am335x_evm_usbspl am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT Tom Rini <trini@ti.com> 268 Active arm armv7 am33xx ti am335x am335x_evm_usbspl am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT Tom Rini <trini@ti.com>
269 Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 - 269 Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 -
270 Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter <matt.porter@linaro.org> 270 Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter <matt.porter@linaro.org>
271 Active arm armv7 am33xx ti ti816x ti816x_evm - - 271 Active arm armv7 am33xx ti ti816x ti816x_evm - -
272 Active arm armv7 at91 atmel sama5d3xek sama5d3xek_mmc sama5d3xek:SAMA5D3,SYS_USE_MMC Bo Shen <voice.shen@atmel.com> 272 Active arm armv7 at91 atmel sama5d3xek sama5d3xek_mmc sama5d3xek:SAMA5D3,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
273 Active arm armv7 at91 atmel sama5d3xek sama5d3xek_nandflash sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com> 273 Active arm armv7 at91 atmel sama5d3xek sama5d3xek_nandflash sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com>
274 Active arm armv7 at91 atmel sama5d3xek sama5d3xek_spiflash sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH Bo Shen <voice.shen@atmel.com> 274 Active arm armv7 at91 atmel sama5d3xek sama5d3xek_spiflash sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH Bo Shen <voice.shen@atmel.com>
275 Active arm armv7 exynos samsung arndale arndale - Inderpal Singh <inderpal.singh@linaro.org> 275 Active arm armv7 exynos samsung arndale arndale - Inderpal Singh <inderpal.singh@linaro.org>
276 Active arm armv7 exynos samsung origen origen - Chander Kashyap <k.chander@samsung.com> 276 Active arm armv7 exynos samsung origen origen - Chander Kashyap <k.chander@samsung.com>
277 Active arm armv7 exynos samsung smdk5250 smdk5250 - Chander Kashyap <k.chander@samsung.com> 277 Active arm armv7 exynos samsung smdk5250 smdk5250 - Chander Kashyap <k.chander@samsung.com>
278 Active arm armv7 exynos samsung smdk5250 snow - Rajeshwari Shinde <rajeshwari.s@samsung.com> 278 Active arm armv7 exynos samsung smdk5250 snow - Rajeshwari Shinde <rajeshwari.s@samsung.com>
279 Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap <k.chander@samsung.com> 279 Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap <k.chander@samsung.com>
280 Active arm armv7 exynos samsung trats trats - Lukasz Majewski <l.majewski@samsung.com> 280 Active arm armv7 exynos samsung trats trats - Lukasz Majewski <l.majewski@samsung.com>
281 Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek <p.wilczek@samsung.com> 281 Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek <p.wilczek@samsung.com>
282 Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Przemyslaw Marczak <p.marczak@samsung.com> 282 Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Przemyslaw Marczak <p.marczak@samsung.com>
283 Active arm armv7 highbank - highbank highbank - Rob Herring <rob.herring@calxeda.com> 283 Active arm armv7 highbank - highbank highbank - Rob Herring <rob.herring@calxeda.com>
284 Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut <marek.vasut@gmail.com> 284 Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut <marek.vasut@gmail.com>
285 Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg - 285 Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg -
286 Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic <sbabic@denx.de> 286 Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic <sbabic@denx.de>
287 Active arm armv7 mx5 freescale mx53ard mx53ard mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg Fabio Estevam <fabio.estevam@freescale.com> 287 Active arm armv7 mx5 freescale mx53ard mx53ard mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg Fabio Estevam <fabio.estevam@freescale.com>
288 Active arm armv7 mx5 freescale mx53evk mx53evk mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg Jason Liu <r64343@freescale.com> 288 Active arm armv7 mx5 freescale mx53evk mx53evk mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg Jason Liu <r64343@freescale.com>
289 Active arm armv7 mx5 freescale mx53loco mx53loco mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg Jason Liu <r64343@freescale.com> 289 Active arm armv7 mx5 freescale mx53loco mx53loco mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg Jason Liu <r64343@freescale.com>
290 Active arm armv7 mx5 freescale mx53smd mx53smd mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg Fabio Estevam <fabio.estevam@freescale.com> 290 Active arm armv7 mx5 freescale mx53smd mx53smd mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg Fabio Estevam <fabio.estevam@freescale.com>
291 Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg - 291 Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg -
292 Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg - 292 Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg -
293 Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic <sbabic@denx.de> 293 Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic <sbabic@denx.de>
294 Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com> 294 Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com>
295 Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com> 295 Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com>
296 Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam <fabio.estevam@freescale.com> 296 Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam <fabio.estevam@freescale.com>
297 Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam <fabio.estevam@freescale.com> 297 Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam <fabio.estevam@freescale.com>
298 Active arm armv7 mx6 boundary nitrogen6x mx6qsabrelite nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE Eric Nelson <eric.nelson@boundarydevices.com> 298 Active arm armv7 mx6 boundary nitrogen6x mx6qsabrelite nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE Eric Nelson <eric.nelson@boundarydevices.com>
299 Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com> 299 Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com>
300 Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 Eric Nelson <eric.nelson@boundarydevices.com> 300 Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 Eric Nelson <eric.nelson@boundarydevices.com>
301 Active arm armv7 mx6 boundary nitrogen6x nitrogen6q nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com> 301 Active arm armv7 mx6 boundary nitrogen6x nitrogen6q nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com>
302 Active arm armv7 mx6 boundary nitrogen6x nitrogen6q2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Eric Nelson <eric.nelson@boundarydevices.com> 302 Active arm armv7 mx6 boundary nitrogen6x nitrogen6q2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Eric Nelson <eric.nelson@boundarydevices.com>
303 Active arm armv7 mx6 boundary nitrogen6x nitrogen6s nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Eric Nelson <eric.nelson@boundarydevices.com> 303 Active arm armv7 mx6 boundary nitrogen6x nitrogen6s nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Eric Nelson <eric.nelson@boundarydevices.com>
304 Active arm armv7 mx6 boundary nitrogen6x nitrogen6s1g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com> 304 Active arm armv7 mx6 boundary nitrogen6x nitrogen6s1g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com>
305 Active arm armv7 mx6 congatec cgtqmx6eval cgtqmx6qeval cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Leo Sartre <lsartre@adeneo-embedded.com> 305 Active arm armv7 mx6 congatec cgtqmx6eval cgtqmx6qeval cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Leo Sartre <lsartre@adeneo-embedded.com>
306 Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg Jason Liu <r64343@freescale.com> 306 Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg Jason Liu <r64343@freescale.com>
307 Active arm armv7 mx6 freescale mx6qsabreauto mx6qsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com> 307 Active arm armv7 mx6 freescale mx6qsabreauto mx6qsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
308 Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com> 308 Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com>
309 Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com> 309 Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
310 Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam@freescale.com> 310 Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam@freescale.com>
311 Active arm armv7 mx6 freescale titanium titanium titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg Stefan Roese <sr@denx.de> 311 Active arm armv7 mx6 freescale titanium titanium titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg Stefan Roese <sr@denx.de>
312 Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman@gmail.com> 312 Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman@gmail.com>
313 Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas@gmail.com> 313 Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas@gmail.com>
314 Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat <raph@8d.com> 314 Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat <raph@8d.com>
315 Active arm armv7 omap3 comelit dig297 dig297 - Luca Ceresoli <luca.ceresoli@comelit.it> 315 Active arm armv7 omap3 comelit dig297 dig297 - Luca Ceresoli <luca.ceresoli@comelit.it>
316 Active arm armv7 omap3 compulab cm_t35 cm_t35 - Igor Grinberg <grinberg@compulab.co.il> 316 Active arm armv7 omap3 compulab cm_t35 cm_t35 - Igor Grinberg <grinberg@compulab.co.il>
317 Active arm armv7 omap3 corscience tricorder tricorder - Thomas Weber <weber@corscience.de> 317 Active arm armv7 omap3 corscience tricorder tricorder - Thomas Weber <weber@corscience.de>
318 Active arm armv7 omap3 corscience tricorder tricorder_flash tricorder:FLASHCARD Thomas Weber <weber@corscience.de> 318 Active arm armv7 omap3 corscience tricorder tricorder_flash tricorder:FLASHCARD Thomas Weber <weber@corscience.de>
319 Active arm armv7 omap3 htkw mcx mcx - Ilya Yanok <yanok@emcraft.com> 319 Active arm armv7 omap3 htkw mcx mcx - Ilya Yanok <yanok@emcraft.com>
320 Active arm armv7 omap3 isee igep00x0 igep0020 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com> 320 Active arm armv7 omap3 isee igep00x0 igep0020 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com>
321 Active arm armv7 omap3 isee igep00x0 igep0020_nand omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND - 321 Active arm armv7 omap3 isee igep00x0 igep0020_nand omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND -
322 Active arm armv7 omap3 isee igep00x0 igep0030 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com> 322 Active arm armv7 omap3 isee igep00x0 igep0030 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com>
323 Active arm armv7 omap3 isee igep00x0 igep0030_nand omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND - 323 Active arm armv7 omap3 isee igep00x0 igep0030_nand omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND -
324 Active arm armv7 omap3 isee igep00x0 igep0032 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com> 324 Active arm armv7 omap3 isee igep00x0 igep0032 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com>
325 Active arm armv7 omap3 logicpd am3517evm am3517_evm - Vaibhav Hiremath <hvaibhav@ti.com> 325 Active arm armv7 omap3 logicpd am3517evm am3517_evm - Vaibhav Hiremath <hvaibhav@ti.com>
326 Active arm armv7 omap3 logicpd omap3som omap3_logic - Peter Barada <peter.barada@logicpd.com> 326 Active arm armv7 omap3 logicpd omap3som omap3_logic - Peter Barada <peter.barada@logicpd.com>
327 Active arm armv7 omap3 logicpd zoom1 omap3_zoom1 - Nishanth Menon <nm@ti.com> 327 Active arm armv7 omap3 logicpd zoom1 omap3_zoom1 - Nishanth Menon <nm@ti.com>
328 Active arm armv7 omap3 logicpd zoom2 omap3_zoom2 - Tom Rix <Tom.Rix@windriver.com> 328 Active arm armv7 omap3 logicpd zoom2 omap3_zoom2 - Tom Rix <Tom.Rix@windriver.com>
329 Active arm armv7 omap3 matrix_vision mvblx omap3_mvblx - Michael Jones <michael.jones@matrix-vision.de> 329 Active arm armv7 omap3 matrix_vision mvblx omap3_mvblx - Michael Jones <michael.jones@matrix-vision.de>
330 Active arm armv7 omap3 nokia rx51 nokia_rx51 - Pali Rohรกr <pali.rohar@gmail.com> 330 Active arm armv7 omap3 nokia rx51 nokia_rx51 - Pali Rohรกr <pali.rohar@gmail.com>
331 Active arm armv7 omap3 technexion twister twister - Stefano Babic <sbabic@denx.de> 331 Active arm armv7 omap3 technexion twister twister - Stefano Babic <sbabic@denx.de>
332 Active arm armv7 omap3 teejet mt_ventoux mt_ventoux - Stefano Babic <sbabic@denx.de> 332 Active arm armv7 omap3 teejet mt_ventoux mt_ventoux - Stefano Babic <sbabic@denx.de>
333 Active arm armv7 omap3 ti am3517crane am3517_crane - Nagendra T S <nagendra@mistralsolutions.com> 333 Active arm armv7 omap3 ti am3517crane am3517_crane - Nagendra T S <nagendra@mistralsolutions.com>
334 Active arm armv7 omap3 ti beagle omap3_beagle - Tom Rini <trini@ti.com> 334 Active arm armv7 omap3 ti beagle omap3_beagle - Tom Rini <trini@ti.com>
335 Active arm armv7 omap3 ti evm omap3_evm - Tom Rini <trini@ti.com> 335 Active arm armv7 omap3 ti evm omap3_evm - Tom Rini <trini@ti.com>
336 Active arm armv7 omap3 ti evm omap3_evm_quick_mmc - - 336 Active arm armv7 omap3 ti evm omap3_evm_quick_mmc - -
337 Active arm armv7 omap3 ti evm omap3_evm_quick_nand - - 337 Active arm armv7 omap3 ti evm omap3_evm_quick_nand - -
338 Active arm armv7 omap3 ti sdp3430 omap3_sdp3430 - Nishanth Menon <nm@ti.com> 338 Active arm armv7 omap3 ti sdp3430 omap3_sdp3430 - Nishanth Menon <nm@ti.com>
339 Active arm armv7 omap3 timll devkit8000 devkit8000 - Thomas Weber <weber@corscience.de> 339 Active arm armv7 omap3 timll devkit8000 devkit8000 - Thomas Weber <weber@corscience.de>
340 Active arm armv7 omap4 ti panda omap4_panda - Sricharan R <r.sricharan@ti.com> 340 Active arm armv7 omap4 ti panda omap4_panda - Sricharan R <r.sricharan@ti.com>
341 Active arm armv7 omap4 ti sdp4430 omap4_sdp4430 - Sricharan R <r.sricharan@ti.com> 341 Active arm armv7 omap4 ti sdp4430 omap4_sdp4430 - Sricharan R <r.sricharan@ti.com>
342 Active arm armv7 omap5 ti dra7xx dra7xx_evm dra7xx_evm:CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com> 342 Active arm armv7 omap5 ti dra7xx dra7xx_evm dra7xx_evm:CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com>
343 Active arm armv7 omap5 ti dra7xx dra7xx_evm_uart3 dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT Lokesh Vutla <lokeshvutla@ti.com> 343 Active arm armv7 omap5 ti dra7xx dra7xx_evm_uart3 dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT Lokesh Vutla <lokeshvutla@ti.com>
344 Active arm armv7 omap5 ti omap5_uevm omap5_uevm - - 344 Active arm armv7 omap5 ti omap5_uevm omap5_uevm - -
345 Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 345 Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
346 Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp> 346 Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
347 Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 347 Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
348 Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 348 Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
349 Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 349 Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
350 Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 350 Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
351 Active arm armv7 s5pc1xx samsung goni s5p_goni - Mateusz Zalega <m.zalega@samsung.com> 351 Active arm armv7 s5pc1xx samsung goni s5p_goni - Mateusz Zalega <m.zalega@samsung.com>
352 Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com> 352 Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
353 Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - 353 Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
354 Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org> 354 Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org>
355 Active arm armv7 u8500 st-ericsson u8500 u8500_href - - 355 Active arm armv7 u8500 st-ericsson u8500 u8500_href - -
356 Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com> 356 Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com>
357 Active arm armv7 zynq xilinx zynq zynq - Michal Simek <monstr@monstr.eu> 357 Active arm armv7 zynq xilinx zynq zynq - Michal Simek <monstr@monstr.eu>
358 Active arm armv7 zynq xilinx zynq zynq_dcc zynq:ZYNQ_DCC Michal Simek <monstr@monstr.eu> 358 Active arm armv7 zynq xilinx zynq zynq_dcc zynq:ZYNQ_DCC Michal Simek <monstr@monstr.eu>
359 Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren@nvidia.com> 359 Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren@nvidia.com>
360 Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Thierry Reding <thierry.reding@avionic-design.de> 360 Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Thierry Reding <thierry.reding@avionic-design.de>
361 Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Thierry Reding <thierry.reding@avionic-design.de> 361 Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Thierry Reding <thierry.reding@avionic-design.de>
362 Active arm armv7:arm720t tegra20 avionic-design tec tec - Thierry Reding <thierry.reding@avionic-design.de> 362 Active arm armv7:arm720t tegra20 avionic-design tec tec - Thierry Reding <thierry.reding@avionic-design.de>
363 Active arm armv7:arm720t tegra20 compal paz00 paz00 - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com> 363 Active arm armv7:arm720t tegra20 compal paz00 paz00 - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
364 Active arm armv7:arm720t tegra20 compulab trimslice trimslice - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com> 364 Active arm armv7:arm720t tegra20 compulab trimslice trimslice - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
365 Active arm armv7:arm720t tegra20 nvidia harmony harmony - Tom Warren <twarren@nvidia.com> 365 Active arm armv7:arm720t tegra20 nvidia harmony harmony - Tom Warren <twarren@nvidia.com>
366 Active arm armv7:arm720t tegra20 nvidia seaboard seaboard - Tom Warren <twarren@nvidia.com> 366 Active arm armv7:arm720t tegra20 nvidia seaboard seaboard - Tom Warren <twarren@nvidia.com>
367 Active arm armv7:arm720t tegra20 nvidia ventana ventana - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com> 367 Active arm armv7:arm720t tegra20 nvidia ventana ventana - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
368 Active arm armv7:arm720t tegra20 nvidia whistler whistler - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com> 368 Active arm armv7:arm720t tegra20 nvidia whistler whistler - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
369 Active arm armv7:arm720t tegra20 toradex colibri_t20_iris colibri_t20_iris - Lucas Stach <dev@lynxeye.de> 369 Active arm armv7:arm720t tegra20 toradex colibri_t20_iris colibri_t20_iris - Lucas Stach <dev@lynxeye.de>
370 Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com> 370 Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
371 Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren <twarren@nvidia.com> 371 Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren <twarren@nvidia.com>
372 Active arm ixp - - - actux2 - Michael Schwingen <michael@schwingen.org> 372 Active arm ixp - - - actux2 - Michael Schwingen <michael@schwingen.org>
373 Active arm ixp - - - actux3 - Michael Schwingen <michael@schwingen.org> 373 Active arm ixp - - - actux3 - Michael Schwingen <michael@schwingen.org>
374 Active arm ixp - - - actux4 - Michael Schwingen <michael@schwingen.org> 374 Active arm ixp - - - actux4 - Michael Schwingen <michael@schwingen.org>
375 Active arm ixp - - - dvlhost - Michael Schwingen <michael@schwingen.org> 375 Active arm ixp - - - dvlhost - Michael Schwingen <michael@schwingen.org>
376 Active arm ixp - - actux1 actux1_4_16 actux1:FLASH2X2 Michael Schwingen <michael@schwingen.org> 376 Active arm ixp - - actux1 actux1_4_16 actux1:FLASH2X2 Michael Schwingen <michael@schwingen.org>
377 Active arm ixp - - actux1 actux1_4_32 actux1:FLASH2X2,RAM_32MB Michael Schwingen <michael@schwingen.org> 377 Active arm ixp - - actux1 actux1_4_32 actux1:FLASH2X2,RAM_32MB Michael Schwingen <michael@schwingen.org>
378 Active arm ixp - - actux1 actux1_8_16 actux1:FLASH1X8 Michael Schwingen <michael@schwingen.org> 378 Active arm ixp - - actux1 actux1_8_16 actux1:FLASH1X8 Michael Schwingen <michael@schwingen.org>
379 Active arm ixp - - actux1 actux1_8_32 actux1:FLASH1X8,RAM_32MB Michael Schwingen <michael@schwingen.org> 379 Active arm ixp - - actux1 actux1_8_32 actux1:FLASH1X8,RAM_32MB Michael Schwingen <michael@schwingen.org>
380 Active arm pxa - - - balloon3 - Marek Vasut <marek.vasut@gmail.com> 380 Active arm pxa - - - balloon3 - Marek Vasut <marek.vasut@gmail.com>
381 Active arm pxa - - - h2200 - Lukasz Dalek <luk0104@gmail.com> 381 Active arm pxa - - - h2200 - Lukasz Dalek <luk0104@gmail.com>
382 Active arm pxa - - - palmld - Marek Vasut <marek.vasut@gmail.com> 382 Active arm pxa - - - palmld - Marek Vasut <marek.vasut@gmail.com>
383 Active arm pxa - - - palmtc - Marek Vasut <marek.vasut@gmail.com> 383 Active arm pxa - - - palmtc - Marek Vasut <marek.vasut@gmail.com>
384 Active arm pxa - - - palmtreo680 - Mike Dunn <mikedunn@newsguy.com> 384 Active arm pxa - - - palmtreo680 - Mike Dunn <mikedunn@newsguy.com>
385 Active arm pxa - - - pxa255_idp - Cliff Brake <cliff.brake@gmail.com> 385 Active arm pxa - - - pxa255_idp - Cliff Brake <cliff.brake@gmail.com>
386 Active arm pxa - - - trizepsiv - Stefano Babic <sbabic@denx.de> 386 Active arm pxa - - - trizepsiv - Stefano Babic <sbabic@denx.de>
387 Active arm pxa - - - xaeniax - - 387 Active arm pxa - - - xaeniax - -
388 Active arm pxa - - - zipitz2 - Marek Vasut <marek.vasut@gmail.com> 388 Active arm pxa - - - zipitz2 - Marek Vasut <marek.vasut@gmail.com>
389 Active arm pxa - - trizepsiv polaris trizepsiv:POLARIS Stefano Babic <sbabic@denx.de> 389 Active arm pxa - - trizepsiv polaris trizepsiv:POLARIS Stefano Babic <sbabic@denx.de>
390 Active arm pxa - - vpac270 vpac270_nor_128 vpac270:NOR,RAM_128M Marek Vasut <marek.vasut@gmail.com> 390 Active arm pxa - - vpac270 vpac270_nor_128 vpac270:NOR,RAM_128M Marek Vasut <marek.vasut@gmail.com>
391 Active arm pxa - - vpac270 vpac270_nor_256 vpac270:NOR,RAM_256M Marek Vasut <marek.vasut@gmail.com> 391 Active arm pxa - - vpac270 vpac270_nor_256 vpac270:NOR,RAM_256M Marek Vasut <marek.vasut@gmail.com>
392 Active arm pxa - - vpac270 vpac270_ond_256 vpac270:ONENAND,RAM_256M Marek Vasut <marek.vasut@gmail.com> 392 Active arm pxa - - vpac270 vpac270_ond_256 vpac270:ONENAND,RAM_256M Marek Vasut <marek.vasut@gmail.com>
393 Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich <ynvich@gmail.com> 393 Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich <ynvich@gmail.com>
394 Active arm pxa - toradex - colibri_pxa270 - Marek Vasut <marek.vasut@gmail.com> 394 Active arm pxa - toradex - colibri_pxa270 - Marek Vasut <marek.vasut@gmail.com>
395 Active arm sa1100 - - - jornada - Kristoffer Ericson <kristoffer.ericson@gmail.com> 395 Active arm sa1100 - - - jornada - Kristoffer Ericson <kristoffer.ericson@gmail.com>
396 Active avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com> 396 Active avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
397 Active avr32 at32ap at32ap700x atmel - atngw100mkii - Andreas BieรŸmann <andreas.devel@googlemail.com> 397 Active avr32 at32ap at32ap700x atmel - atngw100mkii - Andreas BieรŸmann <andreas.devel@googlemail.com>
398 Active avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com> 398 Active avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
399 Active avr32 at32ap at32ap700x atmel atstk1000 atstk1003 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com> 399 Active avr32 at32ap at32ap700x atmel atstk1000 atstk1003 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
400 Active avr32 at32ap at32ap700x atmel atstk1000 atstk1004 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com> 400 Active avr32 at32ap at32ap700x atmel atstk1000 atstk1004 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
401 Active avr32 at32ap at32ap700x atmel atstk1000 atstk1006 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com> 401 Active avr32 at32ap at32ap700x atmel atstk1000 atstk1006 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
402 Active avr32 at32ap at32ap700x earthlcd - favr-32-ezkit - Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> 402 Active avr32 at32ap at32ap700x earthlcd - favr-32-ezkit - Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
403 Active avr32 at32ap at32ap700x in-circuit - grasshopper - Andreas BieรŸmann <andreas.devel@googlemail.com> 403 Active avr32 at32ap at32ap700x in-circuit - grasshopper - Andreas BieรŸmann <andreas.devel@googlemail.com>
404 Active avr32 at32ap at32ap700x mimc - mimc200 - Mark Jackson <mpfj@mimc.co.uk> 404 Active avr32 at32ap at32ap700x mimc - mimc200 - Mark Jackson <mpfj@mimc.co.uk>
405 Active avr32 at32ap at32ap700x miromico - hammerhead - Julien May <julien.may@miromico.ch>:Alex Raimondi <alex.raimondi@miromico.ch> 405 Active avr32 at32ap at32ap700x miromico - hammerhead - Julien May <julien.may@miromico.ch>:Alex Raimondi <alex.raimondi@miromico.ch>
406 Active blackfin blackfin - - - bct-brettl2 - Peter Meerwald <devel@bct-electronic.com> 406 Active blackfin blackfin - - - bct-brettl2 - Peter Meerwald <devel@bct-electronic.com>
407 Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 407 Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
408 Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 408 Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
409 Active blackfin blackfin - - - bf525-ucr2 - Haitao Zhang <hzhang@ucrobotics.com>:Chong Huang <chuang@ucrobotics.com> 409 Active blackfin blackfin - - - bf525-ucr2 - Haitao Zhang <hzhang@ucrobotics.com>:Chong Huang <chuang@ucrobotics.com>
410 Active blackfin blackfin - - - bf526-ezbrd - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 410 Active blackfin blackfin - - - bf526-ezbrd - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
411 Active blackfin blackfin - - - bf527-ad7160-eval - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 411 Active blackfin blackfin - - - bf527-ad7160-eval - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
412 Active blackfin blackfin - - - bf527-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 412 Active blackfin blackfin - - - bf527-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
413 Active blackfin blackfin - - - bf527-sdp - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 413 Active blackfin blackfin - - - bf527-sdp - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
414 Active blackfin blackfin - - - bf533-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 414 Active blackfin blackfin - - - bf533-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
415 Active blackfin blackfin - - - bf533-stamp - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 415 Active blackfin blackfin - - - bf533-stamp - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
416 Active blackfin blackfin - - - bf537-minotaur - Martin Strubel <strubel@section5.ch> 416 Active blackfin blackfin - - - bf537-minotaur - Martin Strubel <strubel@section5.ch>
417 Active blackfin blackfin - - - bf537-pnav - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 417 Active blackfin blackfin - - - bf537-pnav - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
418 Active blackfin blackfin - - - bf537-srv1 - Martin Strubel <strubel@section5.ch> 418 Active blackfin blackfin - - - bf537-srv1 - Martin Strubel <strubel@section5.ch>
419 Active blackfin blackfin - - - bf537-stamp - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 419 Active blackfin blackfin - - - bf537-stamp - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
420 Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 420 Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
421 Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 421 Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
422 Active blackfin blackfin - - - bf561-acvilon - Anton Shurpin <shurpin.aa@niistt.ru>:Valentin Yakovenkov <yakovenkov@niistt.ru> 422 Active blackfin blackfin - - - bf561-acvilon - Anton Shurpin <shurpin.aa@niistt.ru>:Valentin Yakovenkov <yakovenkov@niistt.ru>
423 Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 423 Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
424 Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 424 Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
425 Active blackfin blackfin - - - blackstamp - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com> 425 Active blackfin blackfin - - - blackstamp - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
426 Active blackfin blackfin - - - blackvme - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com> 426 Active blackfin blackfin - - - blackvme - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
427 Active blackfin blackfin - - - br4 - Dimitar Penev <dpn@switchfin.org> 427 Active blackfin blackfin - - - br4 - Dimitar Penev <dpn@switchfin.org>
428 Active blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> 428 Active blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
429 Active blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> 429 Active blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
430 Active blackfin blackfin - - - cm-bf537e - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> 430 Active blackfin blackfin - - - cm-bf537e - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
431 Active blackfin blackfin - - - cm-bf537u - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> 431 Active blackfin blackfin - - - cm-bf537u - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
432 Active blackfin blackfin - - - cm-bf548 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> 432 Active blackfin blackfin - - - cm-bf548 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
433 Active blackfin blackfin - - - cm-bf561 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> 433 Active blackfin blackfin - - - cm-bf561 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
434 Active blackfin blackfin - - - dnp5370 - M.Hasewinkel (MHA) <info@ssv-embedded.de> 434 Active blackfin blackfin - - - dnp5370 - M.Hasewinkel (MHA) <info@ssv-embedded.de>
435 Active blackfin blackfin - - - ibf-dsp561 - I-SYST Micromodule <support@i-syst.com> 435 Active blackfin blackfin - - - ibf-dsp561 - I-SYST Micromodule <support@i-syst.com>
436 Active blackfin blackfin - - - ip04 - Brent Kandetzki <brentk@teleco.com> 436 Active blackfin blackfin - - - ip04 - Brent Kandetzki <brentk@teleco.com>
437 Active blackfin blackfin - - - pr1 - Dimitar Penev <dpn@switchfin.org> 437 Active blackfin blackfin - - - pr1 - Dimitar Penev <dpn@switchfin.org>
438 Active blackfin blackfin - - - tcm-bf518 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> 438 Active blackfin blackfin - - - tcm-bf518 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
439 Active blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> 439 Active blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
440 Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 440 Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
441 Active m68k mcf5227x - freescale m52277evb M52277EVB M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 441 Active m68k mcf5227x - freescale m52277evb M52277EVB M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
442 Active m68k mcf5227x - freescale m52277evb M52277EVB_stmicro M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 442 Active m68k mcf5227x - freescale m52277evb M52277EVB_stmicro M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
443 Active m68k mcf523x - freescale m5235evb M5235EVB M5235EVB:SYS_TEXT_BASE=0xFFE00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 443 Active m68k mcf523x - freescale m5235evb M5235EVB M5235EVB:SYS_TEXT_BASE=0xFFE00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
444 Active m68k mcf523x - freescale m5235evb M5235EVB_Flash32 M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 444 Active m68k mcf523x - freescale m5235evb M5235EVB_Flash32 M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
445 Active m68k mcf52x2 - - - idmr - - 445 Active m68k mcf52x2 - - - idmr - -
446 Active m68k mcf52x2 - - cobra5272 cobra5272 - - 446 Active m68k mcf52x2 - - cobra5272 cobra5272 - -
447 Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282 eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400 Jens Scharsig <esw@bus-elektronik.de> 447 Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282 eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400 Jens Scharsig <esw@bus-elektronik.de>
448 Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282_internal eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418 Jens Scharsig <esw@bus-elektronik.de> 448 Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282_internal eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418 Jens Scharsig <esw@bus-elektronik.de>
449 Active m68k mcf52x2 - esd tasreg TASREG - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 449 Active m68k mcf52x2 - esd tasreg TASREG - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
450 Active m68k mcf52x2 - freescale m5208evbe M5208EVBE - - 450 Active m68k mcf52x2 - freescale m5208evbe M5208EVBE - -
451 Active m68k mcf52x2 - freescale m5249evb M5249EVB - - 451 Active m68k mcf52x2 - freescale m5249evb M5249EVB - -
452 Active m68k mcf52x2 - freescale m5253demo M5253DEMO - TsiChung Liew <Tsi-Chung.Liew@freescale.com> 452 Active m68k mcf52x2 - freescale m5253demo M5253DEMO - TsiChung Liew <Tsi-Chung.Liew@freescale.com>
453 Active m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser <Hayden.Fraser@freescale.com> 453 Active m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser <Hayden.Fraser@freescale.com>
454 Active m68k mcf52x2 - freescale m5271evb M5271EVB - - 454 Active m68k mcf52x2 - freescale m5271evb M5271EVB - -
455 Active m68k mcf52x2 - freescale m5272c3 M5272C3 - - 455 Active m68k mcf52x2 - freescale m5272c3 M5272C3 - -
456 Active m68k mcf52x2 - freescale m5275evb M5275EVB - - 456 Active m68k mcf52x2 - freescale m5275evb M5275EVB - -
457 Active m68k mcf52x2 - freescale m5282evb M5282EVB - - 457 Active m68k mcf52x2 - freescale m5282evb M5282EVB - -
458 Active m68k mcf532x - astro mcf5373l astro_mcf5373l - Wolfgang Wegner <w.wegner@astro-kom.de> 458 Active m68k mcf532x - astro mcf5373l astro_mcf5373l - Wolfgang Wegner <w.wegner@astro-kom.de>
459 Active m68k mcf532x - freescale m53017evb M53017EVB - TsiChung Liew <Tsi-Chung.Liew@freescale.com> 459 Active m68k mcf532x - freescale m53017evb M53017EVB - TsiChung Liew <Tsi-Chung.Liew@freescale.com>
460 Active m68k mcf532x - freescale m5329evb M5329AFEE M5329EVB:NANDFLASH_SIZE=0 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 460 Active m68k mcf532x - freescale m5329evb M5329AFEE M5329EVB:NANDFLASH_SIZE=0 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
461 Active m68k mcf532x - freescale m5329evb M5329BFEE M5329EVB:NANDFLASH_SIZE=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 461 Active m68k mcf532x - freescale m5329evb M5329BFEE M5329EVB:NANDFLASH_SIZE=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
462 Active m68k mcf532x - freescale m5373evb M5373EVB M5373EVB:NANDFLASH_SIZE=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 462 Active m68k mcf532x - freescale m5373evb M5373EVB M5373EVB:NANDFLASH_SIZE=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
463 Active m68k mcf5445x - freescale m54418twr M54418TWR M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 - 463 Active m68k mcf5445x - freescale m54418twr M54418TWR M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -
464 Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_mii M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 - 464 Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_mii M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 -
465 Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_rmii M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 - 465 Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_rmii M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -
466 Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_rmii_lowfreq M54418TWR:SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 - 466 Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_rmii_lowfreq M54418TWR:SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -
467 Active m68k mcf5445x - freescale m54418twr M54418TWR_serial_mii M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 - 467 Active m68k mcf5445x - freescale m54418twr M54418TWR_serial_mii M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 -
468 Active m68k mcf5445x - freescale m54418twr M54418TWR_serial_rmii M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 - 468 Active m68k mcf5445x - freescale m54418twr M54418TWR_serial_rmii M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -
469 Active m68k mcf5445x - freescale m54451evb M54451EVB M54451EVB:SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000 - 469 Active m68k mcf5445x - freescale m54451evb M54451EVB M54451EVB:SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000 -
470 Active m68k mcf5445x - freescale m54451evb M54451EVB_stmicro M54451EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000 - 470 Active m68k mcf5445x - freescale m54451evb M54451EVB_stmicro M54451EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000 -
471 Active m68k mcf5445x - freescale m54455evb M54455EVB M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 471 Active m68k mcf5445x - freescale m54455evb M54455EVB M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
472 Active m68k mcf5445x - freescale m54455evb M54455EVB_a66 M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=66666666 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 472 Active m68k mcf5445x - freescale m54455evb M54455EVB_a66 M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=66666666 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
473 Active m68k mcf5445x - freescale m54455evb M54455EVB_i66 M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=66666666 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 473 Active m68k mcf5445x - freescale m54455evb M54455EVB_i66 M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=66666666 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
474 Active m68k mcf5445x - freescale m54455evb M54455EVB_intel M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 474 Active m68k mcf5445x - freescale m54455evb M54455EVB_intel M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
475 Active m68k mcf5445x - freescale m54455evb M54455EVB_stm33 M54455EVB:SYS_STMICRO_BOOT,CF_SBF,SYS_TEXT_BASE=0x4FE00000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 475 Active m68k mcf5445x - freescale m54455evb M54455EVB_stm33 M54455EVB:SYS_STMICRO_BOOT,CF_SBF,SYS_TEXT_BASE=0x4FE00000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
476 Active m68k mcf547x_8x - freescale m547xevb M5475AFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 476 Active m68k mcf547x_8x - freescale m547xevb M5475AFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
477 Active m68k mcf547x_8x - freescale m547xevb M5475BFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 477 Active m68k mcf547x_8x - freescale m547xevb M5475BFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
478 Active m68k mcf547x_8x - freescale m547xevb M5475CFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com> 478 Active m68k mcf547x_8x - freescale m547xevb M5475CFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
479 Active m68k mcf547x_8x - freescale m547xevb M5475DFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com> 479 Active m68k mcf547x_8x - freescale m547xevb M5475DFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
480 Active m68k mcf547x_8x - freescale m547xevb M5475EFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com> 480 Active m68k mcf547x_8x - freescale m547xevb M5475EFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
481 Active m68k mcf547x_8x - freescale m547xevb M5475FFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 481 Active m68k mcf547x_8x - freescale m547xevb M5475FFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
482 Active m68k mcf547x_8x - freescale m547xevb M5475GFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 482 Active m68k mcf547x_8x - freescale m547xevb M5475GFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
483 Active m68k mcf547x_8x - freescale m548xevb M5485AFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 483 Active m68k mcf547x_8x - freescale m548xevb M5485AFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
484 Active m68k mcf547x_8x - freescale m548xevb M5485BFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 484 Active m68k mcf547x_8x - freescale m548xevb M5485BFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
485 Active m68k mcf547x_8x - freescale m548xevb M5485CFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com> 485 Active m68k mcf547x_8x - freescale m548xevb M5485CFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
486 Active m68k mcf547x_8x - freescale m548xevb M5485DFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com> 486 Active m68k mcf547x_8x - freescale m548xevb M5485DFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
487 Active m68k mcf547x_8x - freescale m548xevb M5485EFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com> 487 Active m68k mcf547x_8x - freescale m548xevb M5485EFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
488 Active m68k mcf547x_8x - freescale m548xevb M5485FFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 488 Active m68k mcf547x_8x - freescale m548xevb M5485FFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
489 Active m68k mcf547x_8x - freescale m548xevb M5485GFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 489 Active m68k mcf547x_8x - freescale m548xevb M5485GFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
490 Active m68k mcf547x_8x - freescale m548xevb M5485HFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO TsiChung Liew <Tsi-Chung.Liew@freescale.com> 490 Active m68k mcf547x_8x - freescale m548xevb M5485HFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO TsiChung Liew <Tsi-Chung.Liew@freescale.com>
491 Active microblaze microblaze - xilinx microblaze-generic microblaze-generic - Michal Simek <monstr@monstr.eu> 491 Active microblaze microblaze - xilinx microblaze-generic microblaze-generic - Michal Simek <monstr@monstr.eu>
492 Active mips mips32 - - qemu-mips qemu_mips qemu-mips:SYS_BIG_ENDIAN Vlad Lungu <vlad.lungu@windriver.com> 492 Active mips mips32 - - qemu-mips qemu_mips qemu-mips:SYS_BIG_ENDIAN Vlad Lungu <vlad.lungu@windriver.com>
493 Active mips mips32 - - qemu-mips qemu_mipsel qemu-mips:SYS_LITTLE_ENDIAN - 493 Active mips mips32 - - qemu-mips qemu_mipsel qemu-mips:SYS_LITTLE_ENDIAN -
494 Active mips mips32 - imgtec malta malta malta:MIPS32,SYS_BIG_ENDIAN Paul Burton <paul.burton@imgtec.com> 494 Active mips mips32 - imgtec malta malta malta:MIPS32,SYS_BIG_ENDIAN Paul Burton <paul.burton@imgtec.com>
495 Active mips mips32 - imgtec malta maltael malta:MIPS32,SYS_LITTLE_ENDIAN Paul Burton <paul.burton@imgtec.com> 495 Active mips mips32 - imgtec malta maltael malta:MIPS32,SYS_LITTLE_ENDIAN Paul Burton <paul.burton@imgtec.com>
496 Active mips mips32 - micronas vct vct_platinum vct:VCT_PLATINUM - 496 Active mips mips32 - micronas vct vct_platinum vct:VCT_PLATINUM -
497 Active mips mips32 - micronas vct vct_platinum_onenand vct:VCT_PLATINUM,VCT_ONENAND - 497 Active mips mips32 - micronas vct vct_platinum_onenand vct:VCT_PLATINUM,VCT_ONENAND -
498 Active mips mips32 - micronas vct vct_platinum_onenand_small vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE - 498 Active mips mips32 - micronas vct vct_platinum_onenand_small vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE -
499 Active mips mips32 - micronas vct vct_platinum_small vct:VCT_PLATINUM,VCT_SMALL_IMAGE - 499 Active mips mips32 - micronas vct vct_platinum_small vct:VCT_PLATINUM,VCT_SMALL_IMAGE -
500 Active mips mips32 - micronas vct vct_platinumavc vct:VCT_PLATINUMAVC - 500 Active mips mips32 - micronas vct vct_platinumavc vct:VCT_PLATINUMAVC -
501 Active mips mips32 - micronas vct vct_platinumavc_onenand vct:VCT_PLATINUMAVC,VCT_ONENAND - 501 Active mips mips32 - micronas vct vct_platinumavc_onenand vct:VCT_PLATINUMAVC,VCT_ONENAND -
502 Active mips mips32 - micronas vct vct_platinumavc_onenand_small vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE - 502 Active mips mips32 - micronas vct vct_platinumavc_onenand_small vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE -
503 Active mips mips32 - micronas vct vct_platinumavc_small vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE - 503 Active mips mips32 - micronas vct vct_platinumavc_small vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE -
504 Active mips mips32 - micronas vct vct_premium vct:VCT_PREMIUM - 504 Active mips mips32 - micronas vct vct_premium vct:VCT_PREMIUM -
505 Active mips mips32 - micronas vct vct_premium_onenand vct:VCT_PREMIUM,VCT_ONENAND - 505 Active mips mips32 - micronas vct vct_premium_onenand vct:VCT_PREMIUM,VCT_ONENAND -
506 Active mips mips32 - micronas vct vct_premium_onenand_small vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE - 506 Active mips mips32 - micronas vct vct_premium_onenand_small vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE -
507 Active mips mips32 - micronas vct vct_premium_small vct:VCT_PREMIUM,VCT_SMALL_IMAGE - 507 Active mips mips32 - micronas vct vct_premium_small vct:VCT_PREMIUM,VCT_SMALL_IMAGE -
508 Active mips mips32 au1x00 - dbau1x00 dbau1000 dbau1x00:DBAU1000 Thomas Lange <thomas@corelatus.se> 508 Active mips mips32 au1x00 - dbau1x00 dbau1000 dbau1x00:DBAU1000 Thomas Lange <thomas@corelatus.se>
509 Active mips mips32 au1x00 - dbau1x00 dbau1100 dbau1x00:DBAU1100 Thomas Lange <thomas@corelatus.se> 509 Active mips mips32 au1x00 - dbau1x00 dbau1100 dbau1x00:DBAU1100 Thomas Lange <thomas@corelatus.se>
510 Active mips mips32 au1x00 - dbau1x00 dbau1500 dbau1x00:DBAU1500 Thomas Lange <thomas@corelatus.se> 510 Active mips mips32 au1x00 - dbau1x00 dbau1500 dbau1x00:DBAU1500 Thomas Lange <thomas@corelatus.se>
511 Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange <thomas@corelatus.se> 511 Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange <thomas@corelatus.se>
512 Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange <thomas@corelatus.se> 512 Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange <thomas@corelatus.se>
513 Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 - 513 Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 -
514 Active mips mips32 incaip - incaip incaip - Wolfgang Denk <wd@denx.de> 514 Active mips mips32 incaip - incaip incaip - Wolfgang Denk <wd@denx.de>
515 Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de> 515 Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
516 Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de> 516 Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
517 Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de> 517 Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
518 Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN - 518 Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN -
519 Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN - 519 Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN -
520 Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com> 520 Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com>
521 Active nds32 n1213 ag101 AndesTech adp-ag101p adp-ag101p - Andes <uboot@andestech.com> 521 Active nds32 n1213 ag101 AndesTech adp-ag101p adp-ag101p - Andes <uboot@andestech.com>
522 Active nds32 n1213 ag102 AndesTech adp-ag102 adp-ag102 - Andes <uboot@andestech.com> 522 Active nds32 n1213 ag102 AndesTech adp-ag102 adp-ag102 - Andes <uboot@andestech.com>
523 Active nios2 nios2 - altera nios2-generic nios2-generic - Scott McNutt <smcnutt@psyent.com> 523 Active nios2 nios2 - altera nios2-generic nios2-generic - Scott McNutt <smcnutt@psyent.com>
524 Active nios2 nios2 - psyent pci5441 PCI5441 - Scott McNutt <smcnutt@psyent.com> 524 Active nios2 nios2 - psyent pci5441 PCI5441 - Scott McNutt <smcnutt@psyent.com>
525 Active nios2 nios2 - psyent pk1c20 PK1C20 - Scott McNutt <smcnutt@psyent.com> 525 Active nios2 nios2 - psyent pk1c20 PK1C20 - Scott McNutt <smcnutt@psyent.com>
526 Active openrisc or1200 - openrisc openrisc-generic openrisc-generic - Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> 526 Active openrisc or1200 - openrisc openrisc-generic openrisc-generic - Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
527 Active powerpc 74xx_7xx - - - ppmc7xx - - 527 Active powerpc 74xx_7xx - - - ppmc7xx - -
528 Active powerpc 74xx_7xx - - evb64260 P3G4 - Wolfgang Denk <wd@denx.de> 528 Active powerpc 74xx_7xx - - evb64260 P3G4 - Wolfgang Denk <wd@denx.de>
529 Active powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu <nyet@zumanetworks.com> 529 Active powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu <nyet@zumanetworks.com>
530 Active powerpc 74xx_7xx - eltec elppc ELPPC - - 530 Active powerpc 74xx_7xx - eltec elppc ELPPC - -
531 Active powerpc 74xx_7xx - esd cpci750 CPCI750 - Reinhard Arlt <reinhard.arlt@esd-electronics.com> 531 Active powerpc 74xx_7xx - esd cpci750 CPCI750 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
532 Active powerpc 74xx_7xx - freescale mpc7448hpc2 mpc7448hpc2 - Roy Zang <tie-fei.zang@freescale.com> 532 Active powerpc 74xx_7xx - freescale mpc7448hpc2 mpc7448hpc2 - Roy Zang <tie-fei.zang@freescale.com>
533 Active powerpc 74xx_7xx - Marvell db64360 DB64360 - - 533 Active powerpc 74xx_7xx - Marvell db64360 DB64360 - -
534 Active powerpc 74xx_7xx - Marvell db64460 DB64460 - - 534 Active powerpc 74xx_7xx - Marvell db64460 DB64460 - -
535 Active powerpc 74xx_7xx - prodrive p3mx p3m7448 p3mx:P3M7448 Stefan Roese <sr@denx.de> 535 Active powerpc 74xx_7xx - prodrive p3mx p3m7448 p3mx:P3M7448 Stefan Roese <sr@denx.de>
536 Active powerpc 74xx_7xx - prodrive p3mx p3m750 p3mx:P3M750 Stefan Roese <sr@denx.de> 536 Active powerpc 74xx_7xx - prodrive p3mx p3m750 p3mx:P3M750 Stefan Roese <sr@denx.de>
537 Active powerpc mpc512x - - - pdm360ng - Michael Weiss <michael.weiss@ifm.com> 537 Active powerpc mpc512x - - - pdm360ng - Michael Weiss <michael.weiss@ifm.com>
538 Active powerpc mpc512x - davedenx - aria - Wolfgang Denk <wd@denx.de> 538 Active powerpc mpc512x - davedenx - aria - Wolfgang Denk <wd@denx.de>
539 Active powerpc mpc512x - esd - mecp5123 - Reinhard Arlt <reinhard.arlt@esd-electronics.com> 539 Active powerpc mpc512x - esd - mecp5123 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
540 Active powerpc mpc512x - freescale mpc5121ads mpc5121ads - - 540 Active powerpc mpc512x - freescale mpc5121ads mpc5121ads - -
541 Active powerpc mpc512x - freescale mpc5121ads mpc5121ads_rev2 mpc5121ads:MPC5121ADS_REV2 - 541 Active powerpc mpc512x - freescale mpc5121ads mpc5121ads_rev2 mpc5121ads:MPC5121ADS_REV2 -
542 Active powerpc mpc512x - ifm ac14xx ac14xx - Anatolij Gustschin <agust@denx.de> 542 Active powerpc mpc512x - ifm ac14xx ac14xx - Anatolij Gustschin <agust@denx.de>
543 Active powerpc mpc5xx - - cmi cmi_mpc5xx - - 543 Active powerpc mpc5xx - - cmi cmi_mpc5xx - -
544 Active powerpc mpc5xx - mpl pati PATI - - 544 Active powerpc mpc5xx - mpl pati PATI - -
545 Active powerpc mpc5xxx - - - canmb - - 545 Active powerpc mpc5xxx - - - canmb - -
546 Active powerpc mpc5xxx - - - cm5200 - - 546 Active powerpc mpc5xxx - - - cm5200 - -
547 Active powerpc mpc5xxx - - - inka4x0 - Detlev Zundel <dzu@denx.de> 547 Active powerpc mpc5xxx - - - inka4x0 - Detlev Zundel <dzu@denx.de>
548 Active powerpc mpc5xxx - - - ipek01 - Wolfgang Grandegger <wg@denx.de> 548 Active powerpc mpc5xxx - - - ipek01 - Wolfgang Grandegger <wg@denx.de>
549 Active powerpc mpc5xxx - - - jupiter - Heiko Schocher <hs@denx.de> 549 Active powerpc mpc5xxx - - - jupiter - Heiko Schocher <hs@denx.de>
550 Active powerpc mpc5xxx - - - motionpro - - 550 Active powerpc mpc5xxx - - - motionpro - -
551 Active powerpc mpc5xxx - - - munices - - 551 Active powerpc mpc5xxx - - - munices - -
552 Active powerpc mpc5xxx - - - v38b - - 552 Active powerpc mpc5xxx - - - v38b - -
553 Active powerpc mpc5xxx - - a3m071 a3m071 - Stefan Roese <sr@denx.de> 553 Active powerpc mpc5xxx - - a3m071 a3m071 - Stefan Roese <sr@denx.de>
554 Active powerpc mpc5xxx - - a3m071 a4m2k a3m071:A4M2K Stefan Roese <sr@denx.de> 554 Active powerpc mpc5xxx - - a3m071 a4m2k a3m071:A4M2K Stefan Roese <sr@denx.de>
555 Active powerpc mpc5xxx - - a4m072 a4m072 - Sergei Poselenov <sposelenov@emcraft.com> 555 Active powerpc mpc5xxx - - a4m072 a4m072 - Sergei Poselenov <sposelenov@emcraft.com>
556 Active powerpc mpc5xxx - - bc3450 BC3450 - - 556 Active powerpc mpc5xxx - - bc3450 BC3450 - -
557 Active powerpc mpc5xxx - - galaxy5200 galaxy5200 galaxy5200:galaxy5200 Eric Millbrandt <emillbrandt@dekaresearch.com> 557 Active powerpc mpc5xxx - - galaxy5200 galaxy5200 galaxy5200:galaxy5200 Eric Millbrandt <emillbrandt@dekaresearch.com>
558 Active powerpc mpc5xxx - - galaxy5200 galaxy5200_LOWBOOT galaxy5200:galaxy5200_LOWBOOT Eric Millbrandt <emillbrandt@dekaresearch.com> 558 Active powerpc mpc5xxx - - galaxy5200 galaxy5200_LOWBOOT galaxy5200:galaxy5200_LOWBOOT Eric Millbrandt <emillbrandt@dekaresearch.com>
559 Active powerpc mpc5xxx - - icecube icecube_5200 IceCube Wolfgang Denk <wd@denx.de> 559 Active powerpc mpc5xxx - - icecube icecube_5200 IceCube Wolfgang Denk <wd@denx.de>
560 Active powerpc mpc5xxx - - icecube icecube_5200_DDR IceCube:MPC5200_DDR - 560 Active powerpc mpc5xxx - - icecube icecube_5200_DDR IceCube:MPC5200_DDR -
561 Active powerpc mpc5xxx - - icecube icecube_5200_DDR_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR - 561 Active powerpc mpc5xxx - - icecube icecube_5200_DDR_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR -
562 Active powerpc mpc5xxx - - icecube icecube_5200_DDR_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR - 562 Active powerpc mpc5xxx - - icecube icecube_5200_DDR_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR -
563 Active powerpc mpc5xxx - - icecube icecube_5200_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF000000 - 563 Active powerpc mpc5xxx - - icecube icecube_5200_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF000000 -
564 Active powerpc mpc5xxx - - icecube icecube_5200_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000 - 564 Active powerpc mpc5xxx - - icecube icecube_5200_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000 -
565 Active powerpc mpc5xxx - - icecube Lite5200 IceCube - 565 Active powerpc mpc5xxx - - icecube Lite5200 IceCube -
566 Active powerpc mpc5xxx - - icecube Lite5200_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF000000 - 566 Active powerpc mpc5xxx - - icecube Lite5200_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF000000 -
567 Active powerpc mpc5xxx - - icecube Lite5200_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000 - 567 Active powerpc mpc5xxx - - icecube Lite5200_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000 -
568 Active powerpc mpc5xxx - - icecube lite5200b IceCube:MPC5200_DDR,LITE5200B - 568 Active powerpc mpc5xxx - - icecube lite5200b IceCube:MPC5200_DDR,LITE5200B -
569 Active powerpc mpc5xxx - - icecube lite5200b_LOWBOOT IceCube:MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000 - 569 Active powerpc mpc5xxx - - icecube lite5200b_LOWBOOT IceCube:MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000 -
570 Active powerpc mpc5xxx - - icecube lite5200b_PM IceCube:MPC5200_DDR,LITE5200B,LITE5200B_PM - 570 Active powerpc mpc5xxx - - icecube lite5200b_PM IceCube:MPC5200_DDR,LITE5200B,LITE5200B_PM -
571 Active powerpc mpc5xxx - - mcc200 mcc200 mcc200 - 571 Active powerpc mpc5xxx - - mcc200 mcc200 mcc200 -
572 Active powerpc mpc5xxx - - mcc200 mcc200_COM12 mcc200:CONSOLE_COM12 - 572 Active powerpc mpc5xxx - - mcc200 mcc200_COM12 mcc200:CONSOLE_COM12 -
573 Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000 - 573 Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000 -
574 Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot_SDRAM mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM - 574 Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot_SDRAM mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM -
575 Active powerpc mpc5xxx - - mcc200 mcc200_COM12_SDRAM mcc200:CONSOLE_COM12,MCC200_SDRAM - 575 Active powerpc mpc5xxx - - mcc200 mcc200_COM12_SDRAM mcc200:CONSOLE_COM12,MCC200_SDRAM -
576 Active powerpc mpc5xxx - - mcc200 mcc200_highboot mcc200:SYS_TEXT_BASE=0xFFF00000 - 576 Active powerpc mpc5xxx - - mcc200 mcc200_highboot mcc200:SYS_TEXT_BASE=0xFFF00000 -
577 Active powerpc mpc5xxx - - mcc200 mcc200_highboot_SDRAM mcc200:SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM - 577 Active powerpc mpc5xxx - - mcc200 mcc200_highboot_SDRAM mcc200:SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM -
578 Active powerpc mpc5xxx - - mcc200 mcc200_SDRAM mcc200:MCC200_SDRAM - 578 Active powerpc mpc5xxx - - mcc200 mcc200_SDRAM mcc200:MCC200_SDRAM -
579 Active powerpc mpc5xxx - - mcc200 prs200 mcc200:PRS200,MCC200_SDRAM - 579 Active powerpc mpc5xxx - - mcc200 prs200 mcc200:PRS200,MCC200_SDRAM -
580 Active powerpc mpc5xxx - - mcc200 prs200_DDR mcc200:PRS200 - 580 Active powerpc mpc5xxx - - mcc200 prs200_DDR mcc200:PRS200 -
581 Active powerpc mpc5xxx - - mcc200 prs200_highboot mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM - 581 Active powerpc mpc5xxx - - mcc200 prs200_highboot mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM -
582 Active powerpc mpc5xxx - - mcc200 prs200_highboot_DDR mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000 - 582 Active powerpc mpc5xxx - - mcc200 prs200_highboot_DDR mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000 -
583 Active powerpc mpc5xxx - - pm520 PM520 - Josef Wagner <Wagner@Microsys.de> 583 Active powerpc mpc5xxx - - pm520 PM520 - Josef Wagner <Wagner@Microsys.de>
584 Active powerpc mpc5xxx - - pm520 PM520_DDR PM520:MPC5200_DDR Josef Wagner <Wagner@Microsys.de> 584 Active powerpc mpc5xxx - - pm520 PM520_DDR PM520:MPC5200_DDR Josef Wagner <Wagner@Microsys.de>
585 Active powerpc mpc5xxx - - pm520 PM520_ROMBOOT PM520:BOOT_ROM Josef Wagner <Wagner@Microsys.de> 585 Active powerpc mpc5xxx - - pm520 PM520_ROMBOOT PM520:BOOT_ROM Josef Wagner <Wagner@Microsys.de>
586 Active powerpc mpc5xxx - - pm520 PM520_ROMBOOT_DDR PM520:MPC5200_DDR,BOOT_ROM Josef Wagner <Wagner@Microsys.de> 586 Active powerpc mpc5xxx - - pm520 PM520_ROMBOOT_DDR PM520:MPC5200_DDR,BOOT_ROM Josef Wagner <Wagner@Microsys.de>
587 Active powerpc mpc5xxx - - total5200 Total5200 Total5200:TOTAL5200_REV=1 - 587 Active powerpc mpc5xxx - - total5200 Total5200 Total5200:TOTAL5200_REV=1 -
588 Active powerpc mpc5xxx - - total5200 Total5200_lowboot Total5200:TOTAL5200_REV=1,SYS_TEXT_BASE=0xFE000000 - 588 Active powerpc mpc5xxx - - total5200 Total5200_lowboot Total5200:TOTAL5200_REV=1,SYS_TEXT_BASE=0xFE000000 -
589 Active powerpc mpc5xxx - - total5200 Total5200_Rev2 Total5200:TOTAL5200_REV=2 - 589 Active powerpc mpc5xxx - - total5200 Total5200_Rev2 Total5200:TOTAL5200_REV=2 -
590 Active powerpc mpc5xxx - - total5200 Total5200_Rev2_lowboot Total5200:TOTAL5200_REV=2,SYS_TEXT_BASE=0xFE000000 - 590 Active powerpc mpc5xxx - - total5200 Total5200_Rev2_lowboot Total5200:TOTAL5200_REV=2,SYS_TEXT_BASE=0xFE000000 -
591 Active powerpc mpc5xxx - emk top5200 EVAL5200 TOP5200:EVAL5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de> 591 Active powerpc mpc5xxx - emk top5200 EVAL5200 TOP5200:EVAL5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
592 Active powerpc mpc5xxx - emk top5200 MINI5200 TOP5200:MINI5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de> 592 Active powerpc mpc5xxx - emk top5200 MINI5200 TOP5200:MINI5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
593 Active powerpc mpc5xxx - emk top5200 TOP5200 TOP5200:TOP5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de> 593 Active powerpc mpc5xxx - emk top5200 TOP5200 TOP5200:TOP5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
594 Active powerpc mpc5xxx - esd - cpci5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com> 594 Active powerpc mpc5xxx - esd - cpci5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
595 Active powerpc mpc5xxx - esd - mecp5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com> 595 Active powerpc mpc5xxx - esd - mecp5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
596 Active powerpc mpc5xxx - esd - pf5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com> 596 Active powerpc mpc5xxx - esd - pf5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
597 Active powerpc mpc5xxx - ifm o2dnt2 O2D o2d Anatolij Gustschin <agust@denx.de> 597 Active powerpc mpc5xxx - ifm o2dnt2 O2D o2d Anatolij Gustschin <agust@denx.de>
598 Active powerpc mpc5xxx - ifm o2dnt2 O2D300 o2d300 Anatolij Gustschin <agust@denx.de> 598 Active powerpc mpc5xxx - ifm o2dnt2 O2D300 o2d300 Anatolij Gustschin <agust@denx.de>
599 Active powerpc mpc5xxx - ifm o2dnt2 O2DNT2 o2dnt2 Anatolij Gustschin <agust@denx.de> 599 Active powerpc mpc5xxx - ifm o2dnt2 O2DNT2 o2dnt2 Anatolij Gustschin <agust@denx.de>
600 Active powerpc mpc5xxx - ifm o2dnt2 O2DNT2_RAMBOOT o2dnt2:SYS_TEXT_BASE=0x00100000 Anatolij Gustschin <agust@denx.de> 600 Active powerpc mpc5xxx - ifm o2dnt2 O2DNT2_RAMBOOT o2dnt2:SYS_TEXT_BASE=0x00100000 Anatolij Gustschin <agust@denx.de>
601 Active powerpc mpc5xxx - ifm o2dnt2 O2I o2i Anatolij Gustschin <agust@denx.de> 601 Active powerpc mpc5xxx - ifm o2dnt2 O2I o2i Anatolij Gustschin <agust@denx.de>
602 Active powerpc mpc5xxx - ifm o2dnt2 O2MNT o2mnt Anatolij Gustschin <agust@denx.de> 602 Active powerpc mpc5xxx - ifm o2dnt2 O2MNT o2mnt Anatolij Gustschin <agust@denx.de>
603 Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M110 o2mnt:IFM_SENSOR_TYPE="O2M110" Anatolij Gustschin <agust@denx.de> 603 Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M110 o2mnt:IFM_SENSOR_TYPE="O2M110" Anatolij Gustschin <agust@denx.de>
604 Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M112 o2mnt:IFM_SENSOR_TYPE="O2M112" Anatolij Gustschin <agust@denx.de> 604 Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M112 o2mnt:IFM_SENSOR_TYPE="O2M112" Anatolij Gustschin <agust@denx.de>
605 Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M113 o2mnt:IFM_SENSOR_TYPE="O2M113" Anatolij Gustschin <agust@denx.de> 605 Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M113 o2mnt:IFM_SENSOR_TYPE="O2M113" Anatolij Gustschin <agust@denx.de>
606 Active powerpc mpc5xxx - ifm o2dnt2 O3DNT o3dnt Anatolij Gustschin <agust@denx.de> 606 Active powerpc mpc5xxx - ifm o2dnt2 O3DNT o3dnt Anatolij Gustschin <agust@denx.de>
607 Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc - Werner Pfister <Pfister_Werner@intercontrol.de> 607 Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc - Werner Pfister <Pfister_Werner@intercontrol.de>
608 Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_RAMBOOT digsy_mtc:SYS_TEXT_BASE=0x00100000 Werner Pfister <Pfister_Werner@intercontrol.de> 608 Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_RAMBOOT digsy_mtc:SYS_TEXT_BASE=0x00100000 Werner Pfister <Pfister_Werner@intercontrol.de>
609 Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_rev5 digsy_mtc:DIGSY_REV5 Werner Pfister <Pfister_Werner@intercontrol.de> 609 Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_rev5 digsy_mtc:DIGSY_REV5 Werner Pfister <Pfister_Werner@intercontrol.de>
610 Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_rev5_RAMBOOT digsy_mtc:SYS_TEXT_BASE=0x00100000,DIGSY_REV5 Werner Pfister <Pfister_Werner@intercontrol.de> 610 Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_rev5_RAMBOOT digsy_mtc:SYS_TEXT_BASE=0x00100000,DIGSY_REV5 Werner Pfister <Pfister_Werner@intercontrol.de>
611 Active powerpc mpc5xxx - manroland - hmi1001 - - 611 Active powerpc mpc5xxx - manroland - hmi1001 - -
612 Active powerpc mpc5xxx - manroland - mucmc52 - Heiko Schocher <hs@denx.de> 612 Active powerpc mpc5xxx - manroland - mucmc52 - Heiko Schocher <hs@denx.de>
613 Active powerpc mpc5xxx - manroland - uc101 - Heiko Schocher <hs@denx.de> 613 Active powerpc mpc5xxx - manroland - uc101 - Heiko Schocher <hs@denx.de>
614 Active powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz <andre.schwarz@matrix-vision.de> 614 Active powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz <andre.schwarz@matrix-vision.de>
615 Active powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz <andre.schwarz@matrix-vision.de> 615 Active powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz <andre.schwarz@matrix-vision.de>
616 Active powerpc mpc5xxx - phytec pcm030 pcm030 pcm030 Jon Smirl <jonsmirl@gmail.com> 616 Active powerpc mpc5xxx - phytec pcm030 pcm030 pcm030 Jon Smirl <jonsmirl@gmail.com>
617 Active powerpc mpc5xxx - phytec pcm030 pcm030_LOWBOOT pcm030:SYS_TEXT_BASE=0xFF000000 Jon Smirl <jonsmirl@gmail.com> 617 Active powerpc mpc5xxx - phytec pcm030 pcm030_LOWBOOT pcm030:SYS_TEXT_BASE=0xFF000000 Jon Smirl <jonsmirl@gmail.com>
618 Active powerpc mpc5xxx - tqc tqm5200 aev - - 618 Active powerpc mpc5xxx - tqc tqm5200 aev - -
619 Active powerpc mpc5xxx - tqc tqm5200 cam5200 TQM5200:CAM5200,TQM5200S,TQM5200_B - 619 Active powerpc mpc5xxx - tqc tqm5200 cam5200 TQM5200:CAM5200,TQM5200S,TQM5200_B -
620 Active powerpc mpc5xxx - tqc tqm5200 cam5200_niosflash TQM5200:CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH - 620 Active powerpc mpc5xxx - tqc tqm5200 cam5200_niosflash TQM5200:CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH -
621 Active powerpc mpc5xxx - tqc tqm5200 charon charon Heiko Schocher <hs@denx.de> 621 Active powerpc mpc5xxx - tqc tqm5200 charon charon Heiko Schocher <hs@denx.de>
622 Active powerpc mpc5xxx - tqc tqm5200 fo300 TQM5200:FO300 - 622 Active powerpc mpc5xxx - tqc tqm5200 fo300 TQM5200:FO300 -
623 Active powerpc mpc5xxx - tqc tqm5200 MiniFAP TQM5200:MINIFAP - 623 Active powerpc mpc5xxx - tqc tqm5200 MiniFAP TQM5200:MINIFAP -
624 Active powerpc mpc5xxx - tqc tqm5200 TB5200 - - 624 Active powerpc mpc5xxx - tqc tqm5200 TB5200 - -
625 Active powerpc mpc5xxx - tqc tqm5200 TB5200_B TB5200:TQM5200_B - 625 Active powerpc mpc5xxx - tqc tqm5200 TB5200_B TB5200:TQM5200_B -
626 Active powerpc mpc5xxx - tqc tqm5200 TQM5200 TQM5200: - 626 Active powerpc mpc5xxx - tqc tqm5200 TQM5200 TQM5200: -
627 Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B TQM5200:TQM5200_B - 627 Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B TQM5200:TQM5200_B -
628 Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B_HIGHBOOT TQM5200:TQM5200_B,SYS_TEXT_BASE=0xFFF00000 - 628 Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B_HIGHBOOT TQM5200:TQM5200_B,SYS_TEXT_BASE=0xFFF00000 -
629 Active powerpc mpc5xxx - tqc tqm5200 TQM5200_STK100 TQM5200:STK52XX_REV100 - 629 Active powerpc mpc5xxx - tqc tqm5200 TQM5200_STK100 TQM5200:STK52XX_REV100 -
630 Active powerpc mpc5xxx - tqc tqm5200 TQM5200S TQM5200:TQM5200_B,TQM5200S - 630 Active powerpc mpc5xxx - tqc tqm5200 TQM5200S TQM5200:TQM5200_B,TQM5200S -
631 Active powerpc mpc5xxx - tqc tqm5200 TQM5200S_HIGHBOOT TQM5200:TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000 - 631 Active powerpc mpc5xxx - tqc tqm5200 TQM5200S_HIGHBOOT TQM5200:TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000 -
632 Active powerpc mpc824x - - - utx8245 - Greg Allen <gallen@arlut.utexas.edu> 632 Active powerpc mpc824x - - - utx8245 - Greg Allen <gallen@arlut.utexas.edu>
633 Active powerpc mpc824x - - a3000 A3000 - - 633 Active powerpc mpc824x - - a3000 A3000 - -
634 Active powerpc mpc824x - - cpc45 CPC45 CPC45 Josef Wagner <Wagner@Microsys.de> 634 Active powerpc mpc824x - - cpc45 CPC45 CPC45 Josef Wagner <Wagner@Microsys.de>
635 Active powerpc mpc824x - - cpc45 CPC45_ROMBOOT CPC45:BOOT_ROM Josef Wagner <Wagner@Microsys.de> 635 Active powerpc mpc824x - - cpc45 CPC45_ROMBOOT CPC45:BOOT_ROM Josef Wagner <Wagner@Microsys.de>
636 Active powerpc mpc824x - - cu824 CU824 - Wolfgang Denk <wd@denx.de> 636 Active powerpc mpc824x - - cu824 CU824 - Wolfgang Denk <wd@denx.de>
637 Active powerpc mpc824x - - eXalion eXalion - Torsten Demke <torsten.demke@fci.com> 637 Active powerpc mpc824x - - eXalion eXalion - Torsten Demke <torsten.demke@fci.com>
638 Active powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso <yusdi_santoso@adaptec.com> 638 Active powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso <yusdi_santoso@adaptec.com>
639 Active powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim@musenki.com> 639 Active powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim@musenki.com>
640 Active powerpc mpc824x - - mvblue MVBLUE - - 640 Active powerpc mpc824x - - mvblue MVBLUE - -
641 Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk <wd@denx.de> 641 Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk <wd@denx.de>
642 Active powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson <jim@musenki.com> 642 Active powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson <jim@musenki.com>
643 Active powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil@etinsys.com> 643 Active powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil@etinsys.com>
644 Active powerpc mpc824x - etin - kvme080 - Sangmoon Kim <dogoil@etinsys.com> 644 Active powerpc mpc824x - etin - kvme080 - Sangmoon Kim <dogoil@etinsys.com>
645 Active powerpc mpc8260 - - - atc - Wolfgang Denk <wd@denx.de> 645 Active powerpc mpc8260 - - - atc - Wolfgang Denk <wd@denx.de>
646 Active powerpc mpc8260 - - - ep8260 - Frank Panno <fpanno@delphintech.com> 646 Active powerpc mpc8260 - - - ep8260 - Frank Panno <fpanno@delphintech.com>
647 Active powerpc mpc8260 - - - ep82xxm - - 647 Active powerpc mpc8260 - - - ep82xxm - -
648 Active powerpc mpc8260 - - - gw8260 - Oliver Brown <obrown@adventnetworks.com> 648 Active powerpc mpc8260 - - - gw8260 - Oliver Brown <obrown@adventnetworks.com>
649 Active powerpc mpc8260 - - - hymod - Murray Jensen <Murray.Jensen@csiro.au> 649 Active powerpc mpc8260 - - - hymod - Murray Jensen <Murray.Jensen@csiro.au>
650 Active powerpc mpc8260 - - - ppmc8260 - Brad Kemp <Brad.Kemp@seranoa.com> 650 Active powerpc mpc8260 - - - ppmc8260 - Brad Kemp <Brad.Kemp@seranoa.com>
651 Active powerpc mpc8260 - - - sacsng - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com> 651 Active powerpc mpc8260 - - - sacsng - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
652 Active powerpc mpc8260 - - cogent cogent_mpc8260 - Murray Jensen <Murray.Jensen@csiro.au> 652 Active powerpc mpc8260 - - cogent cogent_mpc8260 - Murray Jensen <Murray.Jensen@csiro.au>
653 Active powerpc mpc8260 - - cpu86 CPU86 CPU86 Wolfgang Denk <wd@denx.de> 653 Active powerpc mpc8260 - - cpu86 CPU86 CPU86 Wolfgang Denk <wd@denx.de>
654 Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk <wd@denx.de> 654 Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk <wd@denx.de>
655 Active powerpc mpc8260 - - cpu87 CPU87 CPU87 - 655 Active powerpc mpc8260 - - cpu87 CPU87 CPU87 -
656 Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM - 656 Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM -
657 Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli@arabellasw.com> 657 Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli@arabellasw.com>
658 Active powerpc mpc8260 - - ep8248 ep8248E ep8248 Yuli Barcohen <yuli@arabellasw.com> 658 Active powerpc mpc8260 - - ep8248 ep8248E ep8248 Yuli Barcohen <yuli@arabellasw.com>
659 Active powerpc mpc8260 - - ids8247 IDS8247 - Heiko Schocher <hs@denx.de> 659 Active powerpc mpc8260 - - ids8247 IDS8247 - Heiko Schocher <hs@denx.de>
660 Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger <wg@denx.de> 660 Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger <wg@denx.de>
661 Active powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen <yuli@arabellasw.com> 661 Active powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen <yuli@arabellasw.com>
662 Active powerpc mpc8260 - - ispan ISPAN_REVB ISPAN:SYS_REV_B Yuli Barcohen <yuli@arabellasw.com> 662 Active powerpc mpc8260 - - ispan ISPAN_REVB ISPAN:SYS_REV_B Yuli Barcohen <yuli@arabellasw.com>
663 Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher <hs@denx.de> 663 Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher <hs@denx.de>
664 Active powerpc mpc8260 - - muas3001 muas3001_dev muas3001:MUAS_DEV_BOARD Heiko Schocher <hs@denx.de> 664 Active powerpc mpc8260 - - muas3001 muas3001_dev muas3001:MUAS_DEV_BOARD Heiko Schocher <hs@denx.de>
665 Active powerpc mpc8260 - - pm826 PM825 PM826:PCI,SYS_TEXT_BASE=0xFF000000 Wolfgang Denk <wd@denx.de> 665 Active powerpc mpc8260 - - pm826 PM825 PM826:PCI,SYS_TEXT_BASE=0xFF000000 Wolfgang Denk <wd@denx.de>
666 Active powerpc mpc8260 - - pm826 PM825_BIGFLASH PM826:PCI,FLASH_32MB,SYS_TEXT_BASE=0x40000000 Wolfgang Denk <wd@denx.de> 666 Active powerpc mpc8260 - - pm826 PM825_BIGFLASH PM826:PCI,FLASH_32MB,SYS_TEXT_BASE=0x40000000 Wolfgang Denk <wd@denx.de>
667 Active powerpc mpc8260 - - pm826 PM825_ROMBOOT PM826:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de> 667 Active powerpc mpc8260 - - pm826 PM825_ROMBOOT PM826:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
668 Active powerpc mpc8260 - - pm826 PM825_ROMBOOT_BIGFLASH PM826:PCI,BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de> 668 Active powerpc mpc8260 - - pm826 PM825_ROMBOOT_BIGFLASH PM826:PCI,BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
669 Active powerpc mpc8260 - - pm826 PM826 PM826:SYS_TEXT_BASE=0xFF000000 Wolfgang Denk <wd@denx.de> 669 Active powerpc mpc8260 - - pm826 PM826 PM826:SYS_TEXT_BASE=0xFF000000 Wolfgang Denk <wd@denx.de>
670 Active powerpc mpc8260 - - pm826 PM826_BIGFLASH PM826:FLASH_32MB,SYS_TEXT_BASE=0x40000000 Wolfgang Denk <wd@denx.de> 670 Active powerpc mpc8260 - - pm826 PM826_BIGFLASH PM826:FLASH_32MB,SYS_TEXT_BASE=0x40000000 Wolfgang Denk <wd@denx.de>
671 Active powerpc mpc8260 - - pm826 PM826_ROMBOOT PM826:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de> 671 Active powerpc mpc8260 - - pm826 PM826_ROMBOOT PM826:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
672 Active powerpc mpc8260 - - pm826 PM826_ROMBOOT_BIGFLASH PM826:BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de> 672 Active powerpc mpc8260 - - pm826 PM826_ROMBOOT_BIGFLASH PM826:BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
673 Active powerpc mpc8260 - - pm828 PM828 PM828 - 673 Active powerpc mpc8260 - - pm828 PM828 PM828 -
674 Active powerpc mpc8260 - - pm828 PM828_PCI PM828:PCI - 674 Active powerpc mpc8260 - - pm828 PM828_PCI PM828:PCI -
675 Active powerpc mpc8260 - - pm828 PM828_ROMBOOT PM828:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 - 675 Active powerpc mpc8260 - - pm828 PM828_ROMBOOT PM828:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 -
676 Active powerpc mpc8260 - - pm828 PM828_ROMBOOT_PCI PM828:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 - 676 Active powerpc mpc8260 - - pm828 PM828_ROMBOOT_PCI PM828:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 -
677 Active powerpc mpc8260 - - rattler Rattler Rattler Yuli Barcohen <yuli@arabellasw.com> 677 Active powerpc mpc8260 - - rattler Rattler Rattler Yuli Barcohen <yuli@arabellasw.com>
678 Active powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen <yuli@arabellasw.com> 678 Active powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen <yuli@arabellasw.com>
679 Active powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen <yuli@arabellasw.com> 679 Active powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen <yuli@arabellasw.com>
680 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen <yuli@arabellasw.com> 680 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen <yuli@arabellasw.com>
681 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 Yuli Barcohen <yuli@arabellasw.com> 681 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 Yuli Barcohen <yuli@arabellasw.com>
682 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com> 682 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
683 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 Yuli Barcohen <yuli@arabellasw.com> 683 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 Yuli Barcohen <yuli@arabellasw.com>
684 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com> 684 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
685 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com> 685 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
686 Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS Yuli Barcohen <yuli@arabellasw.com> 686 Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS Yuli Barcohen <yuli@arabellasw.com>
687 Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com> 687 Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
688 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com> 688 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com>
689 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com> 689 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com>
690 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com> 690 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
691 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com> 691 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com>
692 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com> 692 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com>
693 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com> 693 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
694 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com> 694 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
695 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com> 695 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
696 Active powerpc mpc8260 - freescale mpc8266ads MPC8266ADS - Rune Torgersen <runet@innovsys.com> 696 Active powerpc mpc8260 - freescale mpc8266ads MPC8266ADS - Rune Torgersen <runet@innovsys.com>
697 Active powerpc mpc8260 - funkwerk vovpn-gw VoVPN-GW_66MHz VoVPN-GW:CLKIN_66MHz - 697 Active powerpc mpc8260 - funkwerk vovpn-gw VoVPN-GW_66MHz VoVPN-GW:CLKIN_66MHz -
698 Active powerpc mpc8260 - keymile km82xx mgcoge km82xx:MGCOGE Holger Brunck <holger.brunck@keymile.com> 698 Active powerpc mpc8260 - keymile km82xx mgcoge km82xx:MGCOGE Holger Brunck <holger.brunck@keymile.com>
699 Active powerpc mpc8260 - keymile km82xx mgcoge3ne km82xx:MGCOGE3NE Holger Brunck <holger.brunck@keymile.com> 699 Active powerpc mpc8260 - keymile km82xx mgcoge3ne km82xx:MGCOGE3NE Holger Brunck <holger.brunck@keymile.com>
700 Active powerpc mpc8260 - tqc tqm8260 TQM8255_AA TQM8260:MPC8255,300MHz Wolfgang Denk <wd@denx.de> 700 Active powerpc mpc8260 - tqc tqm8260 TQM8255_AA TQM8260:MPC8255,300MHz Wolfgang Denk <wd@denx.de>
701 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AA TQM8260:MPC8260,200MHz Wolfgang Denk <wd@denx.de> 701 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AA TQM8260:MPC8260,200MHz Wolfgang Denk <wd@denx.de>
702 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AB TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de> 702 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AB TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de>
703 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AC TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de> 703 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AC TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de>
704 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AD TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de> 704 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AD TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
705 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AE TQM8260:MPC8260,266MHz Wolfgang Denk <wd@denx.de> 705 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AE TQM8260:MPC8260,266MHz Wolfgang Denk <wd@denx.de>
706 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AF TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de> 706 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AF TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
707 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AG TQM8260:MPC8260,300MHz Wolfgang Denk <wd@denx.de> 707 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AG TQM8260:MPC8260,300MHz Wolfgang Denk <wd@denx.de>
708 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AH TQM8260:MPC8260,300MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de> 708 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AH TQM8260:MPC8260,300MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de>
709 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AI TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de> 709 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AI TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
710 Active powerpc mpc8260 - tqc tqm8260 TQM8265_AA TQM8260:MPC8265,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de> 710 Active powerpc mpc8260 - tqc tqm8260 TQM8265_AA TQM8260:MPC8265,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
711 Active powerpc mpc8260 - tqc tqm8272 TQM8272 - - 711 Active powerpc mpc8260 - tqc tqm8272 TQM8272 - -
712 Active powerpc mpc83xx - - - mpc8308_p1m - Ilya Yanok <yanok@emcraft.com> 712 Active powerpc mpc83xx - - - mpc8308_p1m - Ilya Yanok <yanok@emcraft.com>
713 Active powerpc mpc83xx - - sbc8349 sbc8349 sbc8349 Paul Gortmaker <paul.gortmaker@windriver.com> 713 Active powerpc mpc83xx - - sbc8349 sbc8349 sbc8349 Paul Gortmaker <paul.gortmaker@windriver.com>
714 Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_33 sbc8349:PCI,PCI_33M Paul Gortmaker <paul.gortmaker@windriver.com> 714 Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_33 sbc8349:PCI,PCI_33M Paul Gortmaker <paul.gortmaker@windriver.com>
715 Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_66 sbc8349:PCI,PCI_66M Paul Gortmaker <paul.gortmaker@windriver.com> 715 Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_66 sbc8349:PCI,PCI_66M Paul Gortmaker <paul.gortmaker@windriver.com>
716 Active powerpc mpc83xx - - ve8313 ve8313 - Heiko Schocher <hs@denx.de> 716 Active powerpc mpc83xx - - ve8313 ve8313 - Heiko Schocher <hs@denx.de>
717 Active powerpc mpc83xx - esd vme8349 caddy2 vme8349:CADDY2 Reinhard Arlt <reinhard.arlt@esd-electronics.com> 717 Active powerpc mpc83xx - esd vme8349 caddy2 vme8349:CADDY2 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
718 Active powerpc mpc83xx - esd vme8349 vme8349 vme8349 Reinhard Arlt <reinhard.arlt@esd-electronics.com> 718 Active powerpc mpc83xx - esd vme8349 vme8349 vme8349 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
719 Active powerpc mpc83xx - freescale mpc8308rdb MPC8308RDB - Ilya Yanok <yanok@emcraft.com> 719 Active powerpc mpc83xx - freescale mpc8308rdb MPC8308RDB - Ilya Yanok <yanok@emcraft.com>
720 Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_33 MPC8313ERDB:SYS_33MHZ - 720 Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_33 MPC8313ERDB:SYS_33MHZ -
721 Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_66 MPC8313ERDB:SYS_66MHZ - 721 Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_66 MPC8313ERDB:SYS_66MHZ -
722 Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_33 MPC8313ERDB:SYS_33MHZ,NAND - 722 Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_33 MPC8313ERDB:SYS_33MHZ,NAND -
723 Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_66 MPC8313ERDB:SYS_66MHZ,NAND - 723 Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_66 MPC8313ERDB:SYS_66MHZ,NAND -
724 Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB MPC8315ERDB Dave Liu <daveliu@freescale.com> 724 Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB MPC8315ERDB Dave Liu <daveliu@freescale.com>
725 Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB_NAND MPC8315ERDB:NAND_U_BOOT Dave Liu <daveliu@freescale.com> 725 Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB_NAND MPC8315ERDB:NAND_U_BOOT Dave Liu <daveliu@freescale.com>
726 Active powerpc mpc83xx - freescale mpc8323erdb MPC8323ERDB - Michael Barkowski <michael.barkowski@freescale.com> 726 Active powerpc mpc83xx - freescale mpc8323erdb MPC8323ERDB - Michael Barkowski <michael.barkowski@freescale.com>
727 Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS MPC832XEMDS: Dave Liu <daveliu@freescale.com> 727 Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS MPC832XEMDS: Dave Liu <daveliu@freescale.com>
728 Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_ATM MPC832XEMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com> 728 Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_ATM MPC832XEMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com>
729 Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_33 MPC832XEMDS:PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com> 729 Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_33 MPC832XEMDS:PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
730 Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_66 MPC832XEMDS:PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com> 730 Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_66 MPC832XEMDS:PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
731 Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_SLAVE MPC832XEMDS:PCI,PCISLAVE Dave Liu <daveliu@freescale.com> 731 Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_SLAVE MPC832XEMDS:PCI,PCISLAVE Dave Liu <daveliu@freescale.com>
732 Active powerpc mpc83xx - freescale mpc8349emds MPC8349EMDS - Kim Phillips <kim.phillips@freescale.com> 732 Active powerpc mpc83xx - freescale mpc8349emds MPC8349EMDS - Kim Phillips <kim.phillips@freescale.com>
733 Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITX MPC8349ITX:MPC8349ITX - 733 Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITX MPC8349ITX:MPC8349ITX -
734 Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITX_LOWBOOT MPC8349ITX:MPC8349ITX,SYS_TEXT_BASE=0xFE000000 - 734 Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITX_LOWBOOT MPC8349ITX:MPC8349ITX,SYS_TEXT_BASE=0xFE000000 -
735 Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITXGP MPC8349ITX:MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000 - 735 Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITXGP MPC8349ITX:MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000 -
736 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33 MPC8360EMDS:CLKIN_33MHZ Dave Liu <daveliu@freescale.com> 736 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33 MPC8360EMDS:CLKIN_33MHZ Dave Liu <daveliu@freescale.com>
737 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_ATM MPC8360EMDS:CLKIN_33MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com> 737 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_ATM MPC8360EMDS:CLKIN_33MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com>
738 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_HOST_33 MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com> 738 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_HOST_33 MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
739 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_HOST_66 MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com> 739 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_HOST_66 MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
740 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_SLAVE MPC8360EMDS:CLKIN_33MHZ,PCI,PCISLAVE Dave Liu <daveliu@freescale.com> 740 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_SLAVE MPC8360EMDS:CLKIN_33MHZ,PCI,PCISLAVE Dave Liu <daveliu@freescale.com>
741 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66 MPC8360EMDS:CLKIN_66MHZ Dave Liu <daveliu@freescale.com> 741 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66 MPC8360EMDS:CLKIN_66MHZ Dave Liu <daveliu@freescale.com>
742 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_ATM MPC8360EMDS:CLKIN_66MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com> 742 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_ATM MPC8360EMDS:CLKIN_66MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com>
743 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_33 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com> 743 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_33 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
744 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_66 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com> 744 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_66 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
745 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_SLAVE MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE Dave Liu <daveliu@freescale.com> 745 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_SLAVE MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE Dave Liu <daveliu@freescale.com>
746 Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK MPC8360ERDK Anton Vorontsov <avorontsov@ru.mvista.com> 746 Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK MPC8360ERDK Anton Vorontsov <avorontsov@ru.mvista.com>
747 Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov <avorontsov@ru.mvista.com> 747 Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov <avorontsov@ru.mvista.com>
748 Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_66 MPC8360ERDK Anton Vorontsov <avorontsov@ru.mvista.com> 748 Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_66 MPC8360ERDK Anton Vorontsov <avorontsov@ru.mvista.com>
749 Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS MPC837XEMDS Dave Liu <daveliu@freescale.com> 749 Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS MPC837XEMDS Dave Liu <daveliu@freescale.com>
750 Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS_HOST MPC837XEMDS:PCI Dave Liu <daveliu@freescale.com> 750 Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS_HOST MPC837XEMDS:PCI Dave Liu <daveliu@freescale.com>
751 Active powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015@freescale.com> 751 Active powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015@freescale.com>
752 Active powerpc mpc83xx - keymile km83xx kmcoge5ne km8360:KMCOGE5NE Holger Brunck <holger.brunck@keymile.com> 752 Active powerpc mpc83xx - keymile km83xx kmcoge5ne km8360:KMCOGE5NE Holger Brunck <holger.brunck@keymile.com>
753 Active powerpc mpc83xx - keymile km83xx kmeter1 km8360:KMETER1 Holger Brunck <holger.brunck@keymile.com> 753 Active powerpc mpc83xx - keymile km83xx kmeter1 km8360:KMETER1 Holger Brunck <holger.brunck@keymile.com>
754 Active powerpc mpc83xx - keymile km83xx kmopti2 tuxx1:KMOPTI2 Holger Brunck <holger.brunck@keymile.com> 754 Active powerpc mpc83xx - keymile km83xx kmopti2 tuxx1:KMOPTI2 Holger Brunck <holger.brunck@keymile.com>
755 Active powerpc mpc83xx - keymile km83xx kmsupx5 tuxx1:KMSUPX5 Heiko Schocher <hs@denx.de> 755 Active powerpc mpc83xx - keymile km83xx kmsupx5 tuxx1:KMSUPX5 Heiko Schocher <hs@denx.de>
756 Active powerpc mpc83xx - keymile km83xx kmvect1 suvd3:KMVECT1 Holger Brunck <holger.brunck@keymile.com> 756 Active powerpc mpc83xx - keymile km83xx kmvect1 suvd3:KMVECT1 Holger Brunck <holger.brunck@keymile.com>
757 Active powerpc mpc83xx - keymile km83xx suvd3 suvd3:SUVD3 Holger Brunck <holger.brunck@keymile.com> 757 Active powerpc mpc83xx - keymile km83xx suvd3 suvd3:SUVD3 Holger Brunck <holger.brunck@keymile.com>
758 Active powerpc mpc83xx - keymile km83xx tuge1 tuxx1:TUGE1 Holger Brunck <holger.brunck@keymile.com> 758 Active powerpc mpc83xx - keymile km83xx tuge1 tuxx1:TUGE1 Holger Brunck <holger.brunck@keymile.com>
759 Active powerpc mpc83xx - keymile km83xx tuxx1 tuxx1:TUXX1 Holger Brunck <holger.brunck@keymile.com> 759 Active powerpc mpc83xx - keymile km83xx tuxx1 tuxx1:TUXX1 Holger Brunck <holger.brunck@keymile.com>
760 Active powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz <andre.schwarz@matrix-vision.de> 760 Active powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz <andre.schwarz@matrix-vision.de>
761 Active powerpc mpc83xx - matrix_vision mvblm7 MVBLM7 - Andre Schwarz <andre.schwarz@matrix-vision.de> 761 Active powerpc mpc83xx - matrix_vision mvblm7 MVBLM7 - Andre Schwarz <andre.schwarz@matrix-vision.de>
762 Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_LP SIMPC8313:NAND_LP Ron Madrid <info@sheldoninst.com> 762 Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_LP SIMPC8313:NAND_LP Ron Madrid <info@sheldoninst.com>
763 Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_SP SIMPC8313:NAND_SP Ron Madrid <info@sheldoninst.com> 763 Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_SP SIMPC8313:NAND_SP Ron Madrid <info@sheldoninst.com>
764 Active powerpc mpc83xx - tqc tqm834x TQM834x - - 764 Active powerpc mpc83xx - tqc tqm834x TQM834x - -
765 Active powerpc mpc85xx - - sbc8548 sbc8548 sbc8548 Paul Gortmaker <paul.gortmaker@windriver.com> 765 Active powerpc mpc85xx - - sbc8548 sbc8548 sbc8548 Paul Gortmaker <paul.gortmaker@windriver.com>
766 Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33 sbc8548:PCI,33 Paul Gortmaker <paul.gortmaker@windriver.com> 766 Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33 sbc8548:PCI,33 Paul Gortmaker <paul.gortmaker@windriver.com>
767 Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33_PCIE sbc8548:PCI,33,PCIE Paul Gortmaker <paul.gortmaker@windriver.com> 767 Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33_PCIE sbc8548:PCI,33,PCIE Paul Gortmaker <paul.gortmaker@windriver.com>
768 Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66 sbc8548:PCI,66 Paul Gortmaker <paul.gortmaker@windriver.com> 768 Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66 sbc8548:PCI,66 Paul Gortmaker <paul.gortmaker@windriver.com>
769 Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66_PCIE sbc8548:PCI,66,PCIE Paul Gortmaker <paul.gortmaker@windriver.com> 769 Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66_PCIE sbc8548:PCI,66,PCIE Paul Gortmaker <paul.gortmaker@windriver.com>
770 Active powerpc mpc85xx - - socrates socrates - - 770 Active powerpc mpc85xx - - socrates socrates - -
771 Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett@boeing.com> 771 Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett@boeing.com>
772 Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 - 772 Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 -
773 Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - 773 Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
774 Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - 774 Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
775 Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 - 775 Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 -
776 Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - 776 Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
777 Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - 777 Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
778 Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - 778 Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
779 Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND BSC9131RDB:BSC9131RDB,NAND Poonam Aggrwal <poonam.aggrwal@freescale.com> 779 Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND BSC9131RDB:BSC9131RDB,NAND Poonam Aggrwal <poonam.aggrwal@freescale.com>
780 Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND_SYSCLK100 BSC9131RDB:BSC9131RDB,NAND,SYS_CLK_100 Poonam Aggrwal <poonam.aggrwal@freescale.com> 780 Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND_SYSCLK100 BSC9131RDB:BSC9131RDB,NAND,SYS_CLK_100 Poonam Aggrwal <poonam.aggrwal@freescale.com>
781 Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_SPIFLASH BSC9131RDB:BSC9131RDB,SPIFLASH Poonam Aggrwal <poonam.aggrwal@freescale.com> 781 Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_SPIFLASH BSC9131RDB:BSC9131RDB,SPIFLASH Poonam Aggrwal <poonam.aggrwal@freescale.com>
782 Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_SPIFLASH_SYSCLK100 BSC9131RDB:BSC9131RDB,SPIFLASH,SYS_CLK_100 Poonam Aggrwal <poonam.aggrwal@freescale.com> 782 Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_SPIFLASH_SYSCLK100 BSC9131RDB:BSC9131RDB,SPIFLASH,SYS_CLK_100 Poonam Aggrwal <poonam.aggrwal@freescale.com>
783 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK100 BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com> 783 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK100 BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
784 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK133 BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com> 784 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK133 BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
785 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK100 BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com> 785 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK100 BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
786 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK133 BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com> 786 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK133 BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
787 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK100 BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com> 787 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK100 BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
788 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK133 BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com> 788 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK133 BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
789 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com> 789 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
790 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com> 790 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
791 Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu <po.liu@freescale.com> 791 Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu <po.liu@freescale.com>
792 Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu <po.liu@freescale.com> 792 Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu <po.liu@freescale.com>
793 Active powerpc mpc85xx - freescale corenet_ds P3041DS - - 793 Active powerpc mpc85xx - freescale corenet_ds P3041DS - -
794 Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - 794 Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
795 Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - 795 Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
796 Active powerpc mpc85xx - freescale corenet_ds P3041DS_SECURE_BOOT P3041DS:SECURE_BOOT - 796 Active powerpc mpc85xx - freescale corenet_ds P3041DS_SECURE_BOOT P3041DS:SECURE_BOOT -
797 Active powerpc mpc85xx - freescale corenet_ds P3041DS_SPIFLASH P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - 797 Active powerpc mpc85xx - freescale corenet_ds P3041DS_SPIFLASH P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
798 Active powerpc mpc85xx - freescale corenet_ds P3041DS_SRIO_PCIE_BOOT P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - 798 Active powerpc mpc85xx - freescale corenet_ds P3041DS_SRIO_PCIE_BOOT P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
799 Active powerpc mpc85xx - freescale corenet_ds P4080DS - - 799 Active powerpc mpc85xx - freescale corenet_ds P4080DS - -
800 Active powerpc mpc85xx - freescale corenet_ds P4080DS_SDCARD P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - 800 Active powerpc mpc85xx - freescale corenet_ds P4080DS_SDCARD P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
801 Active powerpc mpc85xx - freescale corenet_ds P4080DS_SECURE_BOOT P4080DS:SECURE_BOOT - 801 Active powerpc mpc85xx - freescale corenet_ds P4080DS_SECURE_BOOT P4080DS:SECURE_BOOT -
802 Active powerpc mpc85xx - freescale corenet_ds P4080DS_SPIFLASH P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - 802 Active powerpc mpc85xx - freescale corenet_ds P4080DS_SPIFLASH P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
803 Active powerpc mpc85xx - freescale corenet_ds P4080DS_SRIO_PCIE_BOOT P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - 803 Active powerpc mpc85xx - freescale corenet_ds P4080DS_SRIO_PCIE_BOOT P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
804 Active powerpc mpc85xx - freescale corenet_ds P5020DS - - 804 Active powerpc mpc85xx - freescale corenet_ds P5020DS - -
805 Active powerpc mpc85xx - freescale corenet_ds P5020DS_NAND P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - 805 Active powerpc mpc85xx - freescale corenet_ds P5020DS_NAND P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
806 Active powerpc mpc85xx - freescale corenet_ds P5020DS_SDCARD P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - 806 Active powerpc mpc85xx - freescale corenet_ds P5020DS_SDCARD P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
807 Active powerpc mpc85xx - freescale corenet_ds P5020DS_SECURE_BOOT P5020DS:SECURE_BOOT - 807 Active powerpc mpc85xx - freescale corenet_ds P5020DS_SECURE_BOOT P5020DS:SECURE_BOOT -
808 Active powerpc mpc85xx - freescale corenet_ds P5020DS_SPIFLASH P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - 808 Active powerpc mpc85xx - freescale corenet_ds P5020DS_SPIFLASH P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
809 Active powerpc mpc85xx - freescale corenet_ds P5020DS_SRIO_PCIE_BOOT P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - 809 Active powerpc mpc85xx - freescale corenet_ds P5020DS_SRIO_PCIE_BOOT P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
810 Active powerpc mpc85xx - freescale corenet_ds P5040DS - - 810 Active powerpc mpc85xx - freescale corenet_ds P5040DS - -
811 Active powerpc mpc85xx - freescale corenet_ds P5040DS_NAND P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - 811 Active powerpc mpc85xx - freescale corenet_ds P5040DS_NAND P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
812 Active powerpc mpc85xx - freescale corenet_ds P5040DS_SDCARD P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - 812 Active powerpc mpc85xx - freescale corenet_ds P5040DS_SDCARD P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
813 Active powerpc mpc85xx - freescale corenet_ds P5040DS_SPIFLASH P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - 813 Active powerpc mpc85xx - freescale corenet_ds P5040DS_SPIFLASH P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
814 Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS MPC8536DS - 814 Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS MPC8536DS -
815 Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_36BIT MPC8536DS:36BIT - 815 Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_36BIT MPC8536DS:36BIT -
816 Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_NAND MPC8536DS:NAND - 816 Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_NAND MPC8536DS:NAND -
817 Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SDCARD MPC8536DS:SDCARD - 817 Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SDCARD MPC8536DS:SDCARD -
818 Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SPIFLASH MPC8536DS:SPIFLASH - 818 Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SPIFLASH MPC8536DS:SPIFLASH -
819 Active powerpc mpc85xx - freescale mpc8540ads MPC8540ADS - Kumar Gala <kumar.gala@freescale.com> 819 Active powerpc mpc85xx - freescale mpc8540ads MPC8540ADS - Kumar Gala <kumar.gala@freescale.com>
820 Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS MPC8541CDS Kumar Gala <kumar.gala@freescale.com> 820 Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS MPC8541CDS Kumar Gala <kumar.gala@freescale.com>
821 Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS_legacy MPC8541CDS:LEGACY Kumar Gala <kumar.gala@freescale.com> 821 Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS_legacy MPC8541CDS:LEGACY Kumar Gala <kumar.gala@freescale.com>
822 Active powerpc mpc85xx - freescale mpc8544ds MPC8544DS - - 822 Active powerpc mpc85xx - freescale mpc8544ds MPC8544DS - -
823 Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS MPC8548CDS - 823 Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS MPC8548CDS -
824 Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_36BIT MPC8548CDS:36BIT - 824 Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_36BIT MPC8548CDS:36BIT -
825 Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_legacy MPC8548CDS:LEGACY - 825 Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_legacy MPC8548CDS:LEGACY -
826 Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS MPC8555CDS Kumar Gala <kumar.gala@freescale.com> 826 Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS MPC8555CDS Kumar Gala <kumar.gala@freescale.com>
827 Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS_legacy MPC8555CDS:LEGACY Kumar Gala <kumar.gala@freescale.com> 827 Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS_legacy MPC8555CDS:LEGACY Kumar Gala <kumar.gala@freescale.com>
828 Active powerpc mpc85xx - freescale mpc8560ads MPC8560ADS - Kumar Gala <kumar.gala@freescale.com> 828 Active powerpc mpc85xx - freescale mpc8560ads MPC8560ADS - Kumar Gala <kumar.gala@freescale.com>
829 Active powerpc mpc85xx - freescale mpc8568mds MPC8568MDS - - 829 Active powerpc mpc85xx - freescale mpc8568mds MPC8568MDS - -
830 Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS MPC8569MDS - 830 Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS MPC8569MDS -
831 Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_ATM MPC8569MDS:ATM - 831 Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_ATM MPC8569MDS:ATM -
832 Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_NAND MPC8569MDS:NAND - 832 Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_NAND MPC8569MDS:NAND -
833 Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS MPC8572DS - 833 Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS MPC8572DS -
834 Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT - 834 Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT -
835 Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_NAND MPC8572DS:NAND - 835 Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_NAND MPC8572DS:NAND -
836 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND P1010RDB:P1010RDB_PA,36BIT,NAND - 836 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND P1010RDB:P1010RDB_PA,36BIT,NAND -
837 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB:P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT - 837 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB:P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT -
838 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NOR P1010RDB:P1010RDB_PA,36BIT - 838 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NOR P1010RDB:P1010RDB_PA,36BIT -
839 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NOR_SECBOOT P1010RDB:P1010RDB_PA,36BIT,SECURE_BOOT - 839 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NOR_SECBOOT P1010RDB:P1010RDB_PA,36BIT,SECURE_BOOT -
840 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SDCARD P1010RDB:P1010RDB_PA,36BIT,SDCARD - 840 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SDCARD P1010RDB:P1010RDB_PA,36BIT,SDCARD -
841 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SPIFLASH P1010RDB:P1010RDB_PA,36BIT,SPIFLASH - 841 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SPIFLASH P1010RDB:P1010RDB_PA,36BIT,SPIFLASH -
842 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT - 842 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT -
843 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NAND P1010RDB:P1010RDB_PA,NAND - 843 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NAND P1010RDB:P1010RDB_PA,NAND -
844 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NAND_SECBOOT P1010RDB:P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT - 844 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NAND_SECBOOT P1010RDB:P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT -
845 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NOR P1010RDB:P1010RDB_PA - 845 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NOR P1010RDB:P1010RDB_PA -
846 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NOR_SECBOOT P1010RDB:P1010RDB_PA,SECURE_BOOT - 846 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NOR_SECBOOT P1010RDB:P1010RDB_PA,SECURE_BOOT -
847 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SDCARD P1010RDB:P1010RDB_PA,SDCARD - 847 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SDCARD P1010RDB:P1010RDB_PA,SDCARD -
848 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SPIFLASH P1010RDB:P1010RDB_PA,SPIFLASH - 848 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SPIFLASH P1010RDB:P1010RDB_PA,SPIFLASH -
849 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PA,SPIFLASH,SECURE_BOOT - 849 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PA,SPIFLASH,SECURE_BOOT -
850 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NAND P1010RDB:P1010RDB_PB,36BIT,NAND - 850 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NAND P1010RDB:P1010RDB_PB,36BIT,NAND -
851 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NAND_SECBOOT P1010RDB:P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT - 851 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NAND_SECBOOT P1010RDB:P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT -
852 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NOR P1010RDB:P1010RDB_PB,36BIT - 852 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NOR P1010RDB:P1010RDB_PB,36BIT -
853 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB:P1010RDB_PB,36BIT,SECURE_BOOT - 853 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB:P1010RDB_PB,36BIT,SECURE_BOOT -
854 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SDCARD P1010RDB:P1010RDB_PB,36BIT,SDCARD - 854 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SDCARD P1010RDB:P1010RDB_PB,36BIT,SDCARD -
855 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SPIFLASH P1010RDB:P1010RDB_PB,36BIT,SPIFLASH - 855 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SPIFLASH P1010RDB:P1010RDB_PB,36BIT,SPIFLASH -
856 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT - 856 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT -
857 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NAND P1010RDB:P1010RDB_PB,NAND - 857 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NAND P1010RDB:P1010RDB_PB,NAND -
858 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NAND_SECBOOT P1010RDB:P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT - 858 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NAND_SECBOOT P1010RDB:P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT -
859 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NOR P1010RDB:P1010RDB_PB - 859 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NOR P1010RDB:P1010RDB_PB -
860 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NOR_SECBOOT P1010RDB:P1010RDB_PB,SECURE_BOOT - 860 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NOR_SECBOOT P1010RDB:P1010RDB_PB,SECURE_BOOT -
861 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SDCARD P1010RDB:P1010RDB_PB,SDCARD - 861 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SDCARD P1010RDB:P1010RDB_PB,SDCARD -
862 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SPIFLASH P1010RDB:P1010RDB_PB,SPIFLASH - 862 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SPIFLASH P1010RDB:P1010RDB_PB,SPIFLASH -
863 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PB,SPIFLASH,SECURE_BOOT - 863 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PB,SPIFLASH,SECURE_BOOT -
864 Active powerpc mpc85xx - freescale p1022ds P1022DS - Timur Tabi <timur@freescale.com> 864 Active powerpc mpc85xx - freescale p1022ds P1022DS - Timur Tabi <timur@freescale.com>
865 Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT P1022DS:36BIT Timur Tabi <timur@freescale.com> 865 Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT P1022DS:36BIT Timur Tabi <timur@freescale.com>
866 Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_NAND P1022DS:36BIT,NAND Timur Tabi <timur@freescale.com> 866 Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_NAND P1022DS:36BIT,NAND Timur Tabi <timur@freescale.com>
867 Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_SDCARD P1022DS:36BIT,SDCARD Timur Tabi <timur@freescale.com> 867 Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_SDCARD P1022DS:36BIT,SDCARD Timur Tabi <timur@freescale.com>
868 Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_SPIFLASH P1022DS:36BIT,SPIFLASH Timur Tabi <timur@freescale.com> 868 Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_SPIFLASH P1022DS:36BIT,SPIFLASH Timur Tabi <timur@freescale.com>
869 Active powerpc mpc85xx - freescale p1022ds P1022DS_NAND P1022DS:NAND Timur Tabi <timur@freescale.com> 869 Active powerpc mpc85xx - freescale p1022ds P1022DS_NAND P1022DS:NAND Timur Tabi <timur@freescale.com>
870 Active powerpc mpc85xx - freescale p1022ds P1022DS_SDCARD P1022DS:SDCARD Timur Tabi <timur@freescale.com> 870 Active powerpc mpc85xx - freescale p1022ds P1022DS_SDCARD P1022DS:SDCARD Timur Tabi <timur@freescale.com>
871 Active powerpc mpc85xx - freescale p1022ds P1022DS_SPIFLASH P1022DS:SPIFLASH Timur Tabi <timur@freescale.com> 871 Active powerpc mpc85xx - freescale p1022ds P1022DS_SPIFLASH P1022DS:SPIFLASH Timur Tabi <timur@freescale.com>
872 Active powerpc mpc85xx - freescale p1023rdb P1023RDB P1023RDB - 872 Active powerpc mpc85xx - freescale p1023rdb P1023RDB P1023RDB -
873 Active powerpc mpc85xx - freescale p1023rds P1023RDS P1023RDS Roy Zang <tie-fei.zang@freescale.com> 873 Active powerpc mpc85xx - freescale p1023rds P1023RDS P1023RDS Roy Zang <tie-fei.zang@freescale.com>
874 Active powerpc mpc85xx - freescale p1023rds P1023RDS_NAND P1023RDS:NAND Roy Zang <tie-fei.zang@freescale.com> 874 Active powerpc mpc85xx - freescale p1023rds P1023RDS_NAND P1023RDS:NAND Roy Zang <tie-fei.zang@freescale.com>
875 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB P1_P2_RDB:P1011RDB - 875 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB P1_P2_RDB:P1011RDB -
876 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT P1_P2_RDB:P1011RDB,36BIT - 876 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT P1_P2_RDB:P1011RDB,36BIT -
877 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SDCARD P1_P2_RDB:P1011RDB,36BIT,SDCARD - 877 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SDCARD P1_P2_RDB:P1011RDB,36BIT,SDCARD -
878 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SPIFLASH P1_P2_RDB:P1011RDB,36BIT,SPIFLASH - 878 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SPIFLASH P1_P2_RDB:P1011RDB,36BIT,SPIFLASH -
879 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_NAND P1_P2_RDB:P1011RDB,NAND - 879 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_NAND P1_P2_RDB:P1011RDB,NAND -
880 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_SDCARD P1_P2_RDB:P1011RDB,SDCARD - 880 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_SDCARD P1_P2_RDB:P1011RDB,SDCARD -
881 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_SPIFLASH P1_P2_RDB:P1011RDB,SPIFLASH - 881 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_SPIFLASH P1_P2_RDB:P1011RDB,SPIFLASH -
882 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB P1_P2_RDB:P1020RDB - 882 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB P1_P2_RDB:P1020RDB -
883 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT P1_P2_RDB:P1020RDB,36BIT - 883 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT P1_P2_RDB:P1020RDB,36BIT -
884 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT_SDCARD P1_P2_RDB:P1020RDB,36BIT,SDCARD - 884 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT_SDCARD P1_P2_RDB:P1020RDB,36BIT,SDCARD -
885 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT_SPIFLASH P1_P2_RDB:P1020RDB,36BIT,SPIFLASH - 885 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT_SPIFLASH P1_P2_RDB:P1020RDB,36BIT,SPIFLASH -
886 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_NAND P1_P2_RDB:P1020RDB,NAND - 886 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_NAND P1_P2_RDB:P1020RDB,NAND -
887 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_SDCARD P1_P2_RDB:P1020RDB,SDCARD - 887 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_SDCARD P1_P2_RDB:P1020RDB,SDCARD -
888 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_SPIFLASH P1_P2_RDB:P1020RDB,SPIFLASH - 888 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_SPIFLASH P1_P2_RDB:P1020RDB,SPIFLASH -
889 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB P1_P2_RDB:P2010RDB - 889 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB P1_P2_RDB:P2010RDB -
890 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT P1_P2_RDB:P2010RDB,36BIT - 890 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT P1_P2_RDB:P2010RDB,36BIT -
891 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT_SDCARD P1_P2_RDB:P2010RDB,36BIT,SDCARD - 891 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT_SDCARD P1_P2_RDB:P2010RDB,36BIT,SDCARD -
892 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT_SPIFLASH P1_P2_RDB:P2010RDB,36BIT,SPIFLASH - 892 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT_SPIFLASH P1_P2_RDB:P2010RDB,36BIT,SPIFLASH -
893 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_NAND P1_P2_RDB:P2010RDB,NAND - 893 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_NAND P1_P2_RDB:P2010RDB,NAND -
894 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_SDCARD P1_P2_RDB:P2010RDB,SDCARD - 894 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_SDCARD P1_P2_RDB:P2010RDB,SDCARD -
895 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_SPIFLASH P1_P2_RDB:P2010RDB,SPIFLASH - 895 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_SPIFLASH P1_P2_RDB:P2010RDB,SPIFLASH -
896 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB P1_P2_RDB:P2020RDB Poonam Aggrwal <poonam.aggrwal@freescale.com> 896 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB P1_P2_RDB:P2020RDB Poonam Aggrwal <poonam.aggrwal@freescale.com>
897 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT P1_P2_RDB:P2020RDB,36BIT - 897 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT P1_P2_RDB:P2020RDB,36BIT -
898 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT_SDCARD P1_P2_RDB:P2020RDB,36BIT,SDCARD - 898 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT_SDCARD P1_P2_RDB:P2020RDB,36BIT,SDCARD -
899 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT_SPIFLASH P1_P2_RDB:P2020RDB,36BIT,SPIFLASH - 899 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT_SPIFLASH P1_P2_RDB:P2020RDB,36BIT,SPIFLASH -
900 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_NAND P1_P2_RDB:P2020RDB,NAND - 900 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_NAND P1_P2_RDB:P2020RDB,NAND -
901 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_SDCARD P1_P2_RDB:P2020RDB,SDCARD - 901 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_SDCARD P1_P2_RDB:P2020RDB,SDCARD -
902 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_SPIFLASH P1_P2_RDB:P2020RDB,SPIFLASH - 902 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_SPIFLASH P1_P2_RDB:P2020RDB,SPIFLASH -
903 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC p1_p2_rdb_pc:P1020MBG - 903 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC p1_p2_rdb_pc:P1020MBG -
904 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_36BIT p1_p2_rdb_pc:P1020MBG,36BIT - 904 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_36BIT p1_p2_rdb_pc:P1020MBG,36BIT -
905 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020MBG,SDCARD,36BIT - 905 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020MBG,SDCARD,36BIT -
906 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_SDCARD p1_p2_rdb_pc:P1020MBG,SDCARD - 906 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_SDCARD p1_p2_rdb_pc:P1020MBG,SDCARD -
907 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC p1_p2_rdb_pc:P1020RDB_PC - 907 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC p1_p2_rdb_pc:P1020RDB_PC -
908 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT p1_p2_rdb_pc:P1020RDB_PC,36BIT - 908 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT p1_p2_rdb_pc:P1020RDB_PC,36BIT -
909 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_NAND p1_p2_rdb_pc:P1020RDB_PC,36BIT,NAND - 909 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_NAND p1_p2_rdb_pc:P1020RDB_PC,36BIT,NAND -
910 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020RDB_PC,36BIT,SDCARD - 910 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020RDB_PC,36BIT,SDCARD -
911 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P1020RDB_PC,36BIT,SPIFLASH - 911 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P1020RDB_PC,36BIT,SPIFLASH -
912 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_NAND p1_p2_rdb_pc:P1020RDB_PC,NAND - 912 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_NAND p1_p2_rdb_pc:P1020RDB_PC,NAND -
913 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_SDCARD p1_p2_rdb_pc:P1020RDB_PC,SDCARD - 913 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_SDCARD p1_p2_rdb_pc:P1020RDB_PC,SDCARD -
914 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_SPIFLASH p1_p2_rdb_pc:P1020RDB_PC,SPIFLASH - 914 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_SPIFLASH p1_p2_rdb_pc:P1020RDB_PC,SPIFLASH -
915 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD p1_p2_rdb_pc:P1020RDB_PD - 915 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD p1_p2_rdb_pc:P1020RDB_PD -
916 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_NAND p1_p2_rdb_pc:P1020RDB_PD,NAND - 916 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_NAND p1_p2_rdb_pc:P1020RDB_PD,NAND -
917 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_SDCARD p1_p2_rdb_pc:P1020RDB_PD,SDCARD - 917 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_SDCARD p1_p2_rdb_pc:P1020RDB_PD,SDCARD -
918 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_SPIFLASH p1_p2_rdb_pc:P1020RDB_PD,SPIFLASH - 918 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_SPIFLASH p1_p2_rdb_pc:P1020RDB_PD,SPIFLASH -
919 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC p1_p2_rdb_pc:P1020UTM - 919 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC p1_p2_rdb_pc:P1020UTM -
920 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_36BIT p1_p2_rdb_pc:P1020UTM,36BIT - 920 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_36BIT p1_p2_rdb_pc:P1020UTM,36BIT -
921 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020UTM,36BIT,SDCARD - 921 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020UTM,36BIT,SDCARD -
922 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_SDCARD p1_p2_rdb_pc:P1020UTM,SDCARD - 922 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_SDCARD p1_p2_rdb_pc:P1020UTM,SDCARD -
923 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC p1_p2_rdb_pc:P1021RDB - 923 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC p1_p2_rdb_pc:P1021RDB -
924 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT p1_p2_rdb_pc:P1021RDB,36BIT - 924 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT p1_p2_rdb_pc:P1021RDB,36BIT -
925 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_NAND p1_p2_rdb_pc:P1021RDB,36BIT,NAND - 925 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_NAND p1_p2_rdb_pc:P1021RDB,36BIT,NAND -
926 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P1021RDB,36BIT,SDCARD - 926 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P1021RDB,36BIT,SDCARD -
927 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P1021RDB,36BIT,SPIFLASH - 927 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P1021RDB,36BIT,SPIFLASH -
928 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_NAND p1_p2_rdb_pc:P1021RDB,NAND - 928 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_NAND p1_p2_rdb_pc:P1021RDB,NAND -
929 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_SDCARD p1_p2_rdb_pc:P1021RDB,SDCARD - 929 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_SDCARD p1_p2_rdb_pc:P1021RDB,SDCARD -
930 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_SPIFLASH p1_p2_rdb_pc:P1021RDB,SPIFLASH - 930 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_SPIFLASH p1_p2_rdb_pc:P1021RDB,SPIFLASH -
931 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB p1_p2_rdb_pc:P1024RDB - 931 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB p1_p2_rdb_pc:P1024RDB -
932 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_36BIT p1_p2_rdb_pc:P1024RDB,36BIT - 932 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_36BIT p1_p2_rdb_pc:P1024RDB,36BIT -
933 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_NAND p1_p2_rdb_pc:P1024RDB,NAND - 933 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_NAND p1_p2_rdb_pc:P1024RDB,NAND -
934 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_SDCARD p1_p2_rdb_pc:P1024RDB,SDCARD - 934 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_SDCARD p1_p2_rdb_pc:P1024RDB,SDCARD -
935 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_SPIFLASH p1_p2_rdb_pc:P1024RDB,SPIFLASH - 935 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_SPIFLASH p1_p2_rdb_pc:P1024RDB,SPIFLASH -
936 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB p1_p2_rdb_pc:P1025RDB - 936 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB p1_p2_rdb_pc:P1025RDB -
937 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_36BIT p1_p2_rdb_pc:P1025RDB,36BIT - 937 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_36BIT p1_p2_rdb_pc:P1025RDB,36BIT -
938 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_NAND p1_p2_rdb_pc:P1025RDB,NAND - 938 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_NAND p1_p2_rdb_pc:P1025RDB,NAND -
939 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_SDCARD p1_p2_rdb_pc:P1025RDB,SDCARD - 939 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_SDCARD p1_p2_rdb_pc:P1025RDB,SDCARD -
940 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_SPIFLASH p1_p2_rdb_pc:P1025RDB,SPIFLASH - 940 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_SPIFLASH p1_p2_rdb_pc:P1025RDB,SPIFLASH -
941 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC p1_p2_rdb_pc:P2020RDB - 941 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC p1_p2_rdb_pc:P2020RDB -
942 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT p1_p2_rdb_pc:P2020RDB,36BIT - 942 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT p1_p2_rdb_pc:P2020RDB,36BIT -
943 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_NAND p1_p2_rdb_pc:P2020RDB,36BIT,NAND - 943 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_NAND p1_p2_rdb_pc:P2020RDB,36BIT,NAND -
944 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P2020RDB,36BIT,SDCARD - 944 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P2020RDB,36BIT,SDCARD -
945 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P2020RDB,36BIT,SPIFLASH - 945 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P2020RDB,36BIT,SPIFLASH -
946 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_NAND p1_p2_rdb_pc:P2020RDB,NAND - 946 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_NAND p1_p2_rdb_pc:P2020RDB,NAND -
947 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_SDCARD p1_p2_rdb_pc:P2020RDB,SDCARD - 947 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_SDCARD p1_p2_rdb_pc:P2020RDB,SDCARD -
948 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_SPIFLASH p1_p2_rdb_pc:P2020RDB,SPIFLASH - 948 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_SPIFLASH p1_p2_rdb_pc:P2020RDB,SPIFLASH -
949 Active powerpc mpc85xx - freescale p1_twr TWR-P1025 p1_twr:TWR_P1025 - 949 Active powerpc mpc85xx - freescale p1_twr TWR-P1025 p1_twr:TWR_P1025 -
950 Active powerpc mpc85xx - freescale p2020come P2020COME_SDCARD P2020COME:SDCARD Ira W. Snyder <iws@ovro.caltech.edu> 950 Active powerpc mpc85xx - freescale p2020come P2020COME_SDCARD P2020COME:SDCARD Ira W. Snyder <iws@ovro.caltech.edu>
951 Active powerpc mpc85xx - freescale p2020come P2020COME_SPIFLASH P2020COME:SPIFLASH Ira W. Snyder <iws@ovro.caltech.edu> 951 Active powerpc mpc85xx - freescale p2020come P2020COME_SPIFLASH P2020COME:SPIFLASH Ira W. Snyder <iws@ovro.caltech.edu>
952 Active powerpc mpc85xx - freescale p2020ds P2020DS - - 952 Active powerpc mpc85xx - freescale p2020ds P2020DS - -
953 Active powerpc mpc85xx - freescale p2020ds P2020DS_36BIT P2020DS:36BIT - 953 Active powerpc mpc85xx - freescale p2020ds P2020DS_36BIT P2020DS:36BIT -
954 Active powerpc mpc85xx - freescale p2020ds P2020DS_DDR2 P2020DS:DDR2 - 954 Active powerpc mpc85xx - freescale p2020ds P2020DS_DDR2 P2020DS:DDR2 -
955 Active powerpc mpc85xx - freescale p2020ds P2020DS_SDCARD P2020DS:SDCARD - 955 Active powerpc mpc85xx - freescale p2020ds P2020DS_SDCARD P2020DS:SDCARD -
956 Active powerpc mpc85xx - freescale p2020ds P2020DS_SPIFLASH P2020DS:SPIFLASH - 956 Active powerpc mpc85xx - freescale p2020ds P2020DS_SPIFLASH P2020DS:SPIFLASH -
957 Active powerpc mpc85xx - freescale p2041rdb P2041RDB - - 957 Active powerpc mpc85xx - freescale p2041rdb P2041RDB - -
958 Active powerpc mpc85xx - freescale p2041rdb P2041RDB_NAND P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - 958 Active powerpc mpc85xx - freescale p2041rdb P2041RDB_NAND P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
959 Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SDCARD P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - 959 Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SDCARD P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
960 Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SECURE_BOOT P2041RDB:SECURE_BOOT - 960 Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SECURE_BOOT P2041RDB:SECURE_BOOT -
961 Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - 961 Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
962 Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - 962 Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
963 Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 - 963 Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 -
964 Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - 964 Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
965 Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - 965 Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
966 Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun <yorksun@freescale.com> 966 Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun <yorksun@freescale.com>
967 Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 - 967 Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 -
968 Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
968 Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - 969 Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
969 Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - 970 Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
970 Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - 971 Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
971 Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com> 972 Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
972 Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com> 973 Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
973 Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal <poonam.aggrwal@freescale.com> 974 Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal <poonam.aggrwal@freescale.com>
974 Active powerpc mpc85xx - freescale t2080qds T2080QDS T2080QDS:PPC_T2080 975 Active powerpc mpc85xx - freescale t2080qds T2080QDS T2080QDS:PPC_T2080
975 Active powerpc mpc85xx - freescale t2080qds T2080QDS_SDCARD T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 976 Active powerpc mpc85xx - freescale t2080qds T2080QDS_SDCARD T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
976 Active powerpc mpc85xx - freescale t2080qds T2080QDS_SPIFLASH T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 977 Active powerpc mpc85xx - freescale t2080qds T2080QDS_SPIFLASH T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
977 Active powerpc mpc85xx - freescale t2080qds T2080QDS_NAND T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 978 Active powerpc mpc85xx - freescale t2080qds T2080QDS_NAND T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
978 Active powerpc mpc85xx - freescale t2080qds T2080QDS_SRIO_PCIE_BOOT T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 979 Active powerpc mpc85xx - freescale t2080qds T2080QDS_SRIO_PCIE_BOOT T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
979 Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach@gdsys.de> 980 Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach@gdsys.de>
980 Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de> 981 Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de>
981 Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach@gdsys.de> 982 Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach@gdsys.de>
982 Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER_DEVELOP controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP Dirk Eibach <eibach@gdsys.de> 983 Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER_DEVELOP controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP Dirk Eibach <eibach@gdsys.de>
983 Active powerpc mpc85xx - keymile kmp204x kmlion1 kmp204x:KMLION1 Valentin Longchamp <valentin.longchamp@keymile.com> 984 Active powerpc mpc85xx - keymile kmp204x kmlion1 kmp204x:KMLION1 Valentin Longchamp <valentin.longchamp@keymile.com>
984 Active powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek <dan@embeddedalley.com> 985 Active powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek <dan@embeddedalley.com>
985 Active powerpc mpc85xx - stx stxssa stxssa stxssa Dan Malek <dan@embeddedalley.com> 986 Active powerpc mpc85xx - stx stxssa stxssa stxssa Dan Malek <dan@embeddedalley.com>
986 Active powerpc mpc85xx - stx stxssa stxssa_4M stxssa:STXSSA_4M Dan Malek <dan@embeddedalley.com> 987 Active powerpc mpc85xx - stx stxssa stxssa_4M stxssa:STXSSA_4M Dan Malek <dan@embeddedalley.com>
987 Active powerpc mpc85xx - xes - xpedite520x - - 988 Active powerpc mpc85xx - xes - xpedite520x - -
988 Active powerpc mpc85xx - xes - xpedite537x - - 989 Active powerpc mpc85xx - xes - xpedite537x - -
989 Active powerpc mpc85xx - xes - xpedite550x - - 990 Active powerpc mpc85xx - xes - xpedite550x - -
990 Active powerpc mpc86xx - - - sbc8641d - Paul Gortmaker <paul.gortmaker@windriver.com> 991 Active powerpc mpc86xx - - - sbc8641d - Paul Gortmaker <paul.gortmaker@windriver.com>
991 Active powerpc mpc86xx - freescale mpc8610hpcd MPC8610HPCD - - 992 Active powerpc mpc86xx - freescale mpc8610hpcd MPC8610HPCD - -
992 Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN MPC8641HPCN Kumar Gala <kumar.gala@freescale.com> 993 Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN MPC8641HPCN Kumar Gala <kumar.gala@freescale.com>
993 Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN_36BIT MPC8641HPCN:PHYS_64BIT Kumar Gala <kumar.gala@freescale.com> 994 Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN_36BIT MPC8641HPCN:PHYS_64BIT Kumar Gala <kumar.gala@freescale.com>
994 Active powerpc mpc86xx - xes - xpedite517x - - 995 Active powerpc mpc86xx - xes - xpedite517x - -
995 Active powerpc mpc8xx - - - hermes - Wolfgang Denk <wd@denx.de> 996 Active powerpc mpc8xx - - - hermes - Wolfgang Denk <wd@denx.de>
996 Active powerpc mpc8xx - - - lwmon - Wolfgang Denk <wd@denx.de> 997 Active powerpc mpc8xx - - - lwmon - Wolfgang Denk <wd@denx.de>
997 Active powerpc mpc8xx - - - quantum - - 998 Active powerpc mpc8xx - - - quantum - -
998 Active powerpc mpc8xx - - - RRvision - Wolfgang Denk <wd@denx.de> 999 Active powerpc mpc8xx - - - RRvision - Wolfgang Denk <wd@denx.de>
999 Active powerpc mpc8xx - - - spc1920 - - 1000 Active powerpc mpc8xx - - - spc1920 - -
1000 Active powerpc mpc8xx - - - svm_sc8xx - John Zhan <zhanz@sinovee.com> 1001 Active powerpc mpc8xx - - - svm_sc8xx - John Zhan <zhanz@sinovee.com>
1001 Active powerpc mpc8xx - - - v37 - - 1002 Active powerpc mpc8xx - - - v37 - -
1002 Active powerpc mpc8xx - - adder Adder - Yuli Barcohen <yuli@arabellasw.com> 1003 Active powerpc mpc8xx - - adder Adder - Yuli Barcohen <yuli@arabellasw.com>
1003 Active powerpc mpc8xx - - adder Adder87x Adder Yuli Barcohen <yuli@arabellasw.com> 1004 Active powerpc mpc8xx - - adder Adder87x Adder Yuli Barcohen <yuli@arabellasw.com>
1004 Active powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen <yuli@arabellasw.com> 1005 Active powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen <yuli@arabellasw.com>
1005 Active powerpc mpc8xx - - adder AdderUSB Adder Yuli Barcohen <yuli@arabellasw.com> 1006 Active powerpc mpc8xx - - adder AdderUSB Adder Yuli Barcohen <yuli@arabellasw.com>
1006 Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen <Murray.Jensen@csiro.au> 1007 Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen <Murray.Jensen@csiro.au>
1007 Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark <clark@esteem.com> 1008 Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark <clark@esteem.com>
1008 Active powerpc mpc8xx - - fads MPC86xADS - - 1009 Active powerpc mpc8xx - - fads MPC86xADS - -
1009 Active powerpc mpc8xx - - fads MPC885ADS - - 1010 Active powerpc mpc8xx - - fads MPC885ADS - -
1010 Active powerpc mpc8xx - - flagadm FLAGADM - Kรกri Davรญรฐsson <kd@flaga.is> 1011 Active powerpc mpc8xx - - flagadm FLAGADM - Kรกri Davรญรฐsson <kd@flaga.is>
1011 Active powerpc mpc8xx - - gen860t GEN860T - Keith Outwater <Keith_Outwater@mvis.com> 1012 Active powerpc mpc8xx - - gen860t GEN860T - Keith Outwater <Keith_Outwater@mvis.com>
1012 Active powerpc mpc8xx - - gen860t GEN860T_SC GEN860T:SC Keith Outwater <Keith_Outwater@mvis.com> 1013 Active powerpc mpc8xx - - gen860t GEN860T_SC GEN860T:SC Keith Outwater <Keith_Outwater@mvis.com>
1013 Active powerpc mpc8xx - - icu862 ICU862 - Wolfgang Denk <wd@denx.de> 1014 Active powerpc mpc8xx - - icu862 ICU862 - Wolfgang Denk <wd@denx.de>
1014 Active powerpc mpc8xx - - icu862 ICU862_100MHz ICU862:100MHz Wolfgang Denk <wd@denx.de> 1015 Active powerpc mpc8xx - - icu862 ICU862_100MHz ICU862:100MHz Wolfgang Denk <wd@denx.de>
1015 Active powerpc mpc8xx - - ip860 IP860 - Wolfgang Denk <wd@denx.de> 1016 Active powerpc mpc8xx - - ip860 IP860 - Wolfgang Denk <wd@denx.de>
1016 Active powerpc mpc8xx - - ivm IVML24 IVML24:IVML24_16M Wolfgang Denk <wd@denx.de> 1017 Active powerpc mpc8xx - - ivm IVML24 IVML24:IVML24_16M Wolfgang Denk <wd@denx.de>
1017 Active powerpc mpc8xx - - ivm IVML24_128 IVML24:IVML24_32M Wolfgang Denk <wd@denx.de> 1018 Active powerpc mpc8xx - - ivm IVML24_128 IVML24:IVML24_32M Wolfgang Denk <wd@denx.de>
1018 Active powerpc mpc8xx - - ivm IVML24_256 IVML24:IVML24_64M Wolfgang Denk <wd@denx.de> 1019 Active powerpc mpc8xx - - ivm IVML24_256 IVML24:IVML24_64M Wolfgang Denk <wd@denx.de>
1019 Active powerpc mpc8xx - - ivm IVMS8 IVMS8:IVMS8_16M Wolfgang Denk <wd@denx.de> 1020 Active powerpc mpc8xx - - ivm IVMS8 IVMS8:IVMS8_16M Wolfgang Denk <wd@denx.de>
1020 Active powerpc mpc8xx - - ivm IVMS8_128 IVMS8:IVMS8_32M Wolfgang Denk <wd@denx.de> 1021 Active powerpc mpc8xx - - ivm IVMS8_128 IVMS8:IVMS8_32M Wolfgang Denk <wd@denx.de>
1021 Active powerpc mpc8xx - - ivm IVMS8_256 IVMS8:IVMS8_64M Wolfgang Denk <wd@denx.de> 1022 Active powerpc mpc8xx - - ivm IVMS8_256 IVMS8:IVMS8_64M Wolfgang Denk <wd@denx.de>
1022 Active powerpc mpc8xx - - netphone NETPHONE NETPHONE:NETPHONE_VERSION=1 - 1023 Active powerpc mpc8xx - - netphone NETPHONE NETPHONE:NETPHONE_VERSION=1 -
1023 Active powerpc mpc8xx - - netphone NETPHONE_V2 NETPHONE:NETPHONE_VERSION=2 - 1024 Active powerpc mpc8xx - - netphone NETPHONE_V2 NETPHONE:NETPHONE_VERSION=2 -
1024 Active powerpc mpc8xx - - netta NETTA NETTA - 1025 Active powerpc mpc8xx - - netta NETTA NETTA -
1025 Active powerpc mpc8xx - - netta NETTA_6412 NETTA:NETTA_6412=1 - 1026 Active powerpc mpc8xx - - netta NETTA_6412 NETTA:NETTA_6412=1 -
1026 Active powerpc mpc8xx - - netta NETTA_6412_SWAPHOOK NETTA:NETTA_6412=1,NETTA_SWAPHOOK=1 - 1027 Active powerpc mpc8xx - - netta NETTA_6412_SWAPHOOK NETTA:NETTA_6412=1,NETTA_SWAPHOOK=1 -
1027 Active powerpc mpc8xx - - netta NETTA_ISDN NETTA:NETTA_ISDN=1 - 1028 Active powerpc mpc8xx - - netta NETTA_ISDN NETTA:NETTA_ISDN=1 -
1028 Active powerpc mpc8xx - - netta NETTA_ISDN_6412 NETTA:NETTA_ISDN=1,NETTA_6412=1 - 1029 Active powerpc mpc8xx - - netta NETTA_ISDN_6412 NETTA:NETTA_ISDN=1,NETTA_6412=1 -
1029 Active powerpc mpc8xx - - netta NETTA_ISDN_6412_SWAPHOOK NETTA:NETTA_ISDN=1,NETTA_6412=1,NETTA_SWAPHOOK=1 - 1030 Active powerpc mpc8xx - - netta NETTA_ISDN_6412_SWAPHOOK NETTA:NETTA_ISDN=1,NETTA_6412=1,NETTA_SWAPHOOK=1 -
1030 Active powerpc mpc8xx - - netta NETTA_ISDN_SWAPHOOK NETTA:NETTA_ISDN=1,NETTA_SWAPHOOK=1 - 1031 Active powerpc mpc8xx - - netta NETTA_ISDN_SWAPHOOK NETTA:NETTA_ISDN=1,NETTA_SWAPHOOK=1 -
1031 Active powerpc mpc8xx - - netta NETTA_SWAPHOOK NETTA:NETTA_SWAPHOOK=1 - 1032 Active powerpc mpc8xx - - netta NETTA_SWAPHOOK NETTA:NETTA_SWAPHOOK=1 -
1032 Active powerpc mpc8xx - - netta2 NETTA2 NETTA2:NETTA2_VERSION=1 - 1033 Active powerpc mpc8xx - - netta2 NETTA2 NETTA2:NETTA2_VERSION=1 -
1033 Active powerpc mpc8xx - - netta2 NETTA2_V2 NETTA2:NETTA2_VERSION=2 - 1034 Active powerpc mpc8xx - - netta2 NETTA2_V2 NETTA2:NETTA2_VERSION=2 -
1034 Active powerpc mpc8xx - - netvia NETVIA NETVIA:NETVIA_VERSION=1 Pantelis Antoniou <panto@intracom.gr> 1035 Active powerpc mpc8xx - - netvia NETVIA NETVIA:NETVIA_VERSION=1 Pantelis Antoniou <panto@intracom.gr>
1035 Active powerpc mpc8xx - - netvia NETVIA_V2 NETVIA:NETVIA_VERSION=2 Pantelis Antoniou <panto@intracom.gr> 1036 Active powerpc mpc8xx - - netvia NETVIA_V2 NETVIA:NETVIA_VERSION=2 Pantelis Antoniou <panto@intracom.gr>
1036 Active powerpc mpc8xx - - r360mpi R360MPI - Wolfgang Denk <wd@denx.de> 1037 Active powerpc mpc8xx - - r360mpi R360MPI - Wolfgang Denk <wd@denx.de>
1037 Active powerpc mpc8xx - - rbc823 RBC823 - - 1038 Active powerpc mpc8xx - - rbc823 RBC823 - -
1038 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW RPXlite_DW - 1039 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW RPXlite_DW -
1039 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64 RPXlite_DW:RPXlite_64MHz - 1040 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64 RPXlite_DW:RPXlite_64MHz -
1040 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20 - 1041 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20 -
1041 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_LCD RPXlite_DW:LCD,NEC_NL6448BC20 - 1042 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_LCD RPXlite_DW:LCD,NEC_NL6448BC20 -
1042 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM RPXlite_DW:ENV_IS_IN_NVRAM - 1043 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM RPXlite_DW:ENV_IS_IN_NVRAM -
1043 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64 RPXlite_DW:RPXlite_64MHz,ENV_IS_IN_NVRAM - 1044 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64 RPXlite_DW:RPXlite_64MHz,ENV_IS_IN_NVRAM -
1044 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM - 1045 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM -
1045 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_LCD RPXlite_DW:LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM - 1046 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_LCD RPXlite_DW:LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM -
1046 Active powerpc mpc8xx - - RRvision RRvision_LCD RRvision:LCD,SHARP_LQ104V7DS01 Wolfgang Denk <wd@denx.de> 1047 Active powerpc mpc8xx - - RRvision RRvision_LCD RRvision:LCD,SHARP_LQ104V7DS01 Wolfgang Denk <wd@denx.de>
1047 Active powerpc mpc8xx - - sixnet SXNI855T - Dave Ellis <DGE@sixnetio.com> 1048 Active powerpc mpc8xx - - sixnet SXNI855T - Dave Ellis <DGE@sixnetio.com>
1048 Active powerpc mpc8xx - - spd8xx SPD823TS - Wolfgang Denk <wd@denx.de> 1049 Active powerpc mpc8xx - - spd8xx SPD823TS - Wolfgang Denk <wd@denx.de>
1049 Active powerpc mpc8xx - eltec mhpc MHPC - Frank Gottschling <fgottschling@eltec.de> 1050 Active powerpc mpc8xx - eltec mhpc MHPC - Frank Gottschling <fgottschling@eltec.de>
1050 Active powerpc mpc8xx - emk top860 TOP860 - Reinhard Meyer <reinhard.meyer@emk-elektronik.de> 1051 Active powerpc mpc8xx - emk top860 TOP860 - Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
1051 Active powerpc mpc8xx - kup kup4k KUP4K - Klaus Heydeck <heydeck@kieback-peter.de> 1052 Active powerpc mpc8xx - kup kup4k KUP4K - Klaus Heydeck <heydeck@kieback-peter.de>
1052 Active powerpc mpc8xx - kup kup4x KUP4X - Klaus Heydeck <heydeck@kieback-peter.de> 1053 Active powerpc mpc8xx - kup kup4x KUP4X - Klaus Heydeck <heydeck@kieback-peter.de>
1053 Active powerpc mpc8xx - LEOX elpt860 ELPT860 - The LEOX team <team@leox.org> 1054 Active powerpc mpc8xx - LEOX elpt860 ELPT860 - The LEOX team <team@leox.org>
1054 Active powerpc mpc8xx - manroland - uc100 - Stefan Roese <sr@denx.de> 1055 Active powerpc mpc8xx - manroland - uc100 - Stefan Roese <sr@denx.de>
1055 Active powerpc mpc8xx - snmc qs850 QS823 - - 1056 Active powerpc mpc8xx - snmc qs850 QS823 - -
1056 Active powerpc mpc8xx - snmc qs850 QS850 - - 1057 Active powerpc mpc8xx - snmc qs850 QS850 - -
1057 Active powerpc mpc8xx - snmc qs860t QS860T - - 1058 Active powerpc mpc8xx - snmc qs860t QS860T - -
1058 Active powerpc mpc8xx - stx stxxtc stxxtc - Dan Malek <dan@embeddedalley.com> 1059 Active powerpc mpc8xx - stx stxxtc stxxtc - Dan Malek <dan@embeddedalley.com>
1059 Active powerpc mpc8xx - tqc tqm8xx FPS850L - Wolfgang Denk <wd@denx.de> 1060 Active powerpc mpc8xx - tqc tqm8xx FPS850L - Wolfgang Denk <wd@denx.de>
1060 Active powerpc mpc8xx - tqc tqm8xx FPS860L - Wolfgang Denk <wd@denx.de> 1061 Active powerpc mpc8xx - tqc tqm8xx FPS860L - Wolfgang Denk <wd@denx.de>
1061 Active powerpc mpc8xx - tqc tqm8xx NSCU - - 1062 Active powerpc mpc8xx - tqc tqm8xx NSCU - -
1062 Active powerpc mpc8xx - tqc tqm8xx SM850 - Wolfgang Denk <wd@denx.de> 1063 Active powerpc mpc8xx - tqc tqm8xx SM850 - Wolfgang Denk <wd@denx.de>
1063 Active powerpc mpc8xx - tqc tqm8xx TK885D - - 1064 Active powerpc mpc8xx - tqc tqm8xx TK885D - -
1064 Active powerpc mpc8xx - tqc tqm8xx TQM823L - Wolfgang Denk <wd@denx.de> 1065 Active powerpc mpc8xx - tqc tqm8xx TQM823L - Wolfgang Denk <wd@denx.de>
1065 Active powerpc mpc8xx - tqc tqm8xx TQM823L_LCD TQM823L:LCD,NEC_NL6448BC20 Wolfgang Denk <wd@denx.de> 1066 Active powerpc mpc8xx - tqc tqm8xx TQM823L_LCD TQM823L:LCD,NEC_NL6448BC20 Wolfgang Denk <wd@denx.de>
1066 Active powerpc mpc8xx - tqc tqm8xx TQM823M - - 1067 Active powerpc mpc8xx - tqc tqm8xx TQM823M - -
1067 Active powerpc mpc8xx - tqc tqm8xx TQM850L - Wolfgang Denk <wd@denx.de> 1068 Active powerpc mpc8xx - tqc tqm8xx TQM850L - Wolfgang Denk <wd@denx.de>
1068 Active powerpc mpc8xx - tqc tqm8xx TQM850M - - 1069 Active powerpc mpc8xx - tqc tqm8xx TQM850M - -
1069 Active powerpc mpc8xx - tqc tqm8xx TQM855L - Wolfgang Denk <wd@denx.de> 1070 Active powerpc mpc8xx - tqc tqm8xx TQM855L - Wolfgang Denk <wd@denx.de>
1070 Active powerpc mpc8xx - tqc tqm8xx TQM855M - - 1071 Active powerpc mpc8xx - tqc tqm8xx TQM855M - -
1071 Active powerpc mpc8xx - tqc tqm8xx TQM860L - Wolfgang Denk <wd@denx.de> 1072 Active powerpc mpc8xx - tqc tqm8xx TQM860L - Wolfgang Denk <wd@denx.de>
1072 Active powerpc mpc8xx - tqc tqm8xx TQM860M - - 1073 Active powerpc mpc8xx - tqc tqm8xx TQM860M - -
1073 Active powerpc mpc8xx - tqc tqm8xx TQM862L - - 1074 Active powerpc mpc8xx - tqc tqm8xx TQM862L - -
1074 Active powerpc mpc8xx - tqc tqm8xx TQM862M - - 1075 Active powerpc mpc8xx - tqc tqm8xx TQM862M - -
1075 Active powerpc mpc8xx - tqc tqm8xx TQM866M - - 1076 Active powerpc mpc8xx - tqc tqm8xx TQM866M - -
1076 Active powerpc mpc8xx - tqc tqm8xx TQM885D - - 1077 Active powerpc mpc8xx - tqc tqm8xx TQM885D - -
1077 Active powerpc mpc8xx - tqc tqm8xx TTTech TQM823L:LCD,SHARP_LQ104V7DS01 Wolfgang Denk <wd@denx.de> 1078 Active powerpc mpc8xx - tqc tqm8xx TTTech TQM823L:LCD,SHARP_LQ104V7DS01 Wolfgang Denk <wd@denx.de>
1078 Active powerpc mpc8xx - tqc tqm8xx virtlab2 - - 1079 Active powerpc mpc8xx - tqc tqm8xx virtlab2 - -
1079 Active powerpc mpc8xx - tqc tqm8xx wtk TQM823L:LCD,SHARP_LQ065T9DR51U Wolfgang Denk <wd@denx.de> 1080 Active powerpc mpc8xx - tqc tqm8xx wtk TQM823L:LCD,SHARP_LQ065T9DR51U Wolfgang Denk <wd@denx.de>
1080 Active powerpc ppc4xx - - - csb272 - Tolunay Orkun <torkun@nextio.com> 1081 Active powerpc ppc4xx - - - csb272 - Tolunay Orkun <torkun@nextio.com>
1081 Active powerpc ppc4xx - - - csb472 - Tolunay Orkun <torkun@nextio.com> 1082 Active powerpc ppc4xx - - - csb472 - Tolunay Orkun <torkun@nextio.com>
1082 Active powerpc ppc4xx - - - korat - Larry Johnson <lrj@acm.org> 1083 Active powerpc ppc4xx - - - korat - Larry Johnson <lrj@acm.org>
1083 Active powerpc ppc4xx - - - lwmon5 - Stefan Roese <sr@denx.de> 1084 Active powerpc ppc4xx - - - lwmon5 - Stefan Roese <sr@denx.de>
1084 Active powerpc ppc4xx - - - pcs440ep - Stefan Roese <sr@denx.de> 1085 Active powerpc ppc4xx - - - pcs440ep - Stefan Roese <sr@denx.de>
1085 Active powerpc ppc4xx - - - quad100hd - Gary Jennejohn <garyj@denx.de> 1086 Active powerpc ppc4xx - - - quad100hd - Gary Jennejohn <garyj@denx.de>
1086 Active powerpc ppc4xx - - - sbc405 - - 1087 Active powerpc ppc4xx - - - sbc405 - -
1087 Active powerpc ppc4xx - - - sc3 - Heiko Schocher <hs@denx.de> 1088 Active powerpc ppc4xx - - - sc3 - Heiko Schocher <hs@denx.de>
1088 Active powerpc ppc4xx - - - t3corp - Stefan Roese <sr@denx.de> 1089 Active powerpc ppc4xx - - - t3corp - Stefan Roese <sr@denx.de>
1089 Active powerpc ppc4xx - - - zeus - Stefan Roese <sr@denx.de> 1090 Active powerpc ppc4xx - - - zeus - Stefan Roese <sr@denx.de>
1090 Active powerpc ppc4xx - - g2000 G2000 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1091 Active powerpc ppc4xx - - g2000 G2000 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1091 Active powerpc ppc4xx - - jse JSE - Stephen Williams <steve@icarus.com> 1092 Active powerpc ppc4xx - - jse JSE - Stephen Williams <steve@icarus.com>
1092 Active powerpc ppc4xx - - korat korat_perm korat:KORAT_PERMANENT Larry Johnson <lrj@acm.org> 1093 Active powerpc ppc4xx - - korat korat_perm korat:KORAT_PERMANENT Larry Johnson <lrj@acm.org>
1093 Active powerpc ppc4xx - - lwmon5 lcd4_lwmon5 lwmon5:LCD4_LWMON5 Stefan Roese <sr@denx.de> 1094 Active powerpc ppc4xx - - lwmon5 lcd4_lwmon5 lwmon5:LCD4_LWMON5 Stefan Roese <sr@denx.de>
1094 Active powerpc ppc4xx - - w7o W7OLMC - Erik Theisen <etheisen@mindspring.com> 1095 Active powerpc ppc4xx - - w7o W7OLMC - Erik Theisen <etheisen@mindspring.com>
1095 Active powerpc ppc4xx - - w7o W7OLMG - Erik Theisen <etheisen@mindspring.com> 1096 Active powerpc ppc4xx - - w7o W7OLMG - Erik Theisen <etheisen@mindspring.com>
1096 Active powerpc ppc4xx - amcc - acadia - Stefan Roese <sr@denx.de> 1097 Active powerpc ppc4xx - amcc - acadia - Stefan Roese <sr@denx.de>
1097 Active powerpc ppc4xx - amcc - bamboo - Stefan Roese <sr@denx.de> 1098 Active powerpc ppc4xx - amcc - bamboo - Stefan Roese <sr@denx.de>
1098 Active powerpc ppc4xx - amcc - bluestone - Tirumala Marri <tmarri@apm.com> 1099 Active powerpc ppc4xx - amcc - bluestone - Tirumala Marri <tmarri@apm.com>
1099 Active powerpc ppc4xx - amcc - bubinga - - 1100 Active powerpc ppc4xx - amcc - bubinga - -
1100 Active powerpc ppc4xx - amcc - ebony - Stefan Roese <sr@denx.de> 1101 Active powerpc ppc4xx - amcc - ebony - Stefan Roese <sr@denx.de>
1101 Active powerpc ppc4xx - amcc - katmai - Stefan Roese <sr@denx.de> 1102 Active powerpc ppc4xx - amcc - katmai - Stefan Roese <sr@denx.de>
1102 Active powerpc ppc4xx - amcc - luan - John Otken <jotken@softadvances.com> 1103 Active powerpc ppc4xx - amcc - luan - John Otken <jotken@softadvances.com>
1103 Active powerpc ppc4xx - amcc - makalu - Stefan Roese <sr@denx.de> 1104 Active powerpc ppc4xx - amcc - makalu - Stefan Roese <sr@denx.de>
1104 Active powerpc ppc4xx - amcc - ocotea - Stefan Roese <sr@denx.de> 1105 Active powerpc ppc4xx - amcc - ocotea - Stefan Roese <sr@denx.de>
1105 Active powerpc ppc4xx - amcc - redwood - Feng Kan <fkan@amcc.com> 1106 Active powerpc ppc4xx - amcc - redwood - Feng Kan <fkan@amcc.com>
1106 Active powerpc ppc4xx - amcc - taihu - John Otken <jotken@softadvances.com> 1107 Active powerpc ppc4xx - amcc - taihu - John Otken <jotken@softadvances.com>
1107 Active powerpc ppc4xx - amcc - taishan - Stefan Roese <sr@denx.de> 1108 Active powerpc ppc4xx - amcc - taishan - Stefan Roese <sr@denx.de>
1108 Active powerpc ppc4xx - amcc - yucca - - 1109 Active powerpc ppc4xx - amcc - yucca - -
1109 Active powerpc ppc4xx - amcc acadia acadia_nand acadia:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de> 1110 Active powerpc ppc4xx - amcc acadia acadia_nand acadia:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
1110 Active powerpc ppc4xx - amcc bamboo bamboo_nand bamboo:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de> 1111 Active powerpc ppc4xx - amcc bamboo bamboo_nand bamboo:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
1111 Active powerpc ppc4xx - amcc canyonlands arches canyonlands:ARCHES Stefan Roese <sr@denx.de> 1112 Active powerpc ppc4xx - amcc canyonlands arches canyonlands:ARCHES Stefan Roese <sr@denx.de>
1112 Active powerpc ppc4xx - amcc canyonlands canyonlands canyonlands:CANYONLANDS Stefan Roese <sr@denx.de> 1113 Active powerpc ppc4xx - amcc canyonlands canyonlands canyonlands:CANYONLANDS Stefan Roese <sr@denx.de>
1113 Active powerpc ppc4xx - amcc canyonlands canyonlands_nand canyonlands:CANYONLANDS,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de> 1114 Active powerpc ppc4xx - amcc canyonlands canyonlands_nand canyonlands:CANYONLANDS,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
1114 Active powerpc ppc4xx - amcc canyonlands glacier canyonlands:GLACIER Stefan Roese <sr@denx.de> 1115 Active powerpc ppc4xx - amcc canyonlands glacier canyonlands:GLACIER Stefan Roese <sr@denx.de>
1115 Active powerpc ppc4xx - amcc canyonlands glacier_nand canyonlands:GLACIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de> 1116 Active powerpc ppc4xx - amcc canyonlands glacier_nand canyonlands:GLACIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
1116 Active powerpc ppc4xx - amcc kilauea haleakala kilauea:HALEAKALA Stefan Roese <sr@denx.de> 1117 Active powerpc ppc4xx - amcc kilauea haleakala kilauea:HALEAKALA Stefan Roese <sr@denx.de>
1117 Active powerpc ppc4xx - amcc kilauea haleakala_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de> 1118 Active powerpc ppc4xx - amcc kilauea haleakala_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
1118 Active powerpc ppc4xx - amcc kilauea kilauea kilauea:KILAUEA Stefan Roese <sr@denx.de> 1119 Active powerpc ppc4xx - amcc kilauea kilauea kilauea:KILAUEA Stefan Roese <sr@denx.de>
1119 Active powerpc ppc4xx - amcc kilauea kilauea_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de> 1120 Active powerpc ppc4xx - amcc kilauea kilauea_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
1120 Active powerpc ppc4xx - amcc sequoia rainier sequoia:RAINIER Stefan Roese <sr@denx.de> 1121 Active powerpc ppc4xx - amcc sequoia rainier sequoia:RAINIER Stefan Roese <sr@denx.de>
1121 Active powerpc ppc4xx - amcc sequoia rainier_nand sequoia:RAINIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de> 1122 Active powerpc ppc4xx - amcc sequoia rainier_nand sequoia:RAINIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
1122 Active powerpc ppc4xx - amcc sequoia rainier_ramboot sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de> 1123 Active powerpc ppc4xx - amcc sequoia rainier_ramboot sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de>
1123 Active powerpc ppc4xx - amcc sequoia sequoia sequoia:SEQUOIA Stefan Roese <sr@denx.de> 1124 Active powerpc ppc4xx - amcc sequoia sequoia sequoia:SEQUOIA Stefan Roese <sr@denx.de>
1124 Active powerpc ppc4xx - amcc sequoia sequoia_nand sequoia:SEQUOIA,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de> 1125 Active powerpc ppc4xx - amcc sequoia sequoia_nand sequoia:SEQUOIA,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
1125 Active powerpc ppc4xx - amcc sequoia sequoia_ramboot sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de> 1126 Active powerpc ppc4xx - amcc sequoia sequoia_ramboot sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de>
1126 Active powerpc ppc4xx - amcc walnut sycamore walnut Stefan Roese <sr@denx.de> 1127 Active powerpc ppc4xx - amcc walnut sycamore walnut Stefan Roese <sr@denx.de>
1127 Active powerpc ppc4xx - amcc walnut walnut - Stefan Roese <sr@denx.de> 1128 Active powerpc ppc4xx - amcc walnut walnut - Stefan Roese <sr@denx.de>
1128 Active powerpc ppc4xx - amcc yosemite yellowstone yosemite:YELLOWSTONE Stefan Roese <sr@denx.de> 1129 Active powerpc ppc4xx - amcc yosemite yellowstone yosemite:YELLOWSTONE Stefan Roese <sr@denx.de>
1129 Active powerpc ppc4xx - amcc yosemite yosemite yosemite:YOSEMITE Stefan Roese <sr@denx.de> 1130 Active powerpc ppc4xx - amcc yosemite yosemite yosemite:YOSEMITE Stefan Roese <sr@denx.de>
1130 Active powerpc ppc4xx - avnet fx12mm fx12mm fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt <schardt@team-ctech.de> 1131 Active powerpc ppc4xx - avnet fx12mm fx12mm fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt <schardt@team-ctech.de>
1131 Active powerpc ppc4xx - avnet fx12mm fx12mm_flash fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt <schardt@team-ctech.de> 1132 Active powerpc ppc4xx - avnet fx12mm fx12mm_flash fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt <schardt@team-ctech.de>
1132 Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es> 1133 Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
1133 Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval_flash v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es> 1134 Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval_flash v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
1134 Active powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff <dave@cray.com> 1135 Active powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff <dave@cray.com>
1135 Active powerpc ppc4xx - dave PPChameleonEVB CATcenter CATcenter:PPCHAMELEON_MODULE_MODEL=1 - 1136 Active powerpc ppc4xx - dave PPChameleonEVB CATcenter CATcenter:PPCHAMELEON_MODULE_MODEL=1 -
1136 Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_25 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 - 1137 Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_25 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 -
1137 Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_33 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 - 1138 Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_33 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 -
1138 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB - Andrea "llandre" Marson <andrea.marson@dave-tech.it> 1139 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB - Andrea "llandre" Marson <andrea.marson@dave-tech.it>
1139 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_BA_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it> 1140 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_BA_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
1140 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_BA_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it> 1141 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_BA_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
1141 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_HI_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it> 1142 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_HI_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
1142 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_HI_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it> 1143 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_HI_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
1143 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_ME_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it> 1144 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_ME_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
1144 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_ME_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it> 1145 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_ME_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
1145 Active powerpc ppc4xx - esd apc405 APC405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1146 Active powerpc ppc4xx - esd apc405 APC405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1146 Active powerpc ppc4xx - esd ar405 AR405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1147 Active powerpc ppc4xx - esd ar405 AR405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1147 Active powerpc ppc4xx - esd ash405 ASH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1148 Active powerpc ppc4xx - esd ash405 ASH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1148 Active powerpc ppc4xx - esd cms700 CMS700 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1149 Active powerpc ppc4xx - esd cms700 CMS700 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1149 Active powerpc ppc4xx - esd cpci2dp CPCI2DP - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1150 Active powerpc ppc4xx - esd cpci2dp CPCI2DP - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1150 Active powerpc ppc4xx - esd cpci405 CPCI405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1151 Active powerpc ppc4xx - esd cpci405 CPCI405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1151 Active powerpc ppc4xx - esd cpci405 CPCI4052 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1152 Active powerpc ppc4xx - esd cpci405 CPCI4052 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1152 Active powerpc ppc4xx - esd cpci405 CPCI405AB - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1153 Active powerpc ppc4xx - esd cpci405 CPCI405AB - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1153 Active powerpc ppc4xx - esd cpci405 CPCI405DT - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1154 Active powerpc ppc4xx - esd cpci405 CPCI405DT - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1154 Active powerpc ppc4xx - esd cpciiser4 CPCIISER4 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1155 Active powerpc ppc4xx - esd cpciiser4 CPCIISER4 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1155 Active powerpc ppc4xx - esd dp405 DP405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1156 Active powerpc ppc4xx - esd dp405 DP405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1156 Active powerpc ppc4xx - esd du405 DU405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1157 Active powerpc ppc4xx - esd du405 DU405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1157 Active powerpc ppc4xx - esd du440 DU440 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1158 Active powerpc ppc4xx - esd du440 DU440 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1158 Active powerpc ppc4xx - esd hh405 HH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1159 Active powerpc ppc4xx - esd hh405 HH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1159 Active powerpc ppc4xx - esd hub405 HUB405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1160 Active powerpc ppc4xx - esd hub405 HUB405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1160 Active powerpc ppc4xx - esd ocrtc OCRTC - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1161 Active powerpc ppc4xx - esd ocrtc OCRTC - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1161 Active powerpc ppc4xx - esd pci405 PCI405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1162 Active powerpc ppc4xx - esd pci405 PCI405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1162 Active powerpc ppc4xx - esd plu405 PLU405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1163 Active powerpc ppc4xx - esd plu405 PLU405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1163 Active powerpc ppc4xx - esd pmc405 PMC405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1164 Active powerpc ppc4xx - esd pmc405 PMC405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1164 Active powerpc ppc4xx - esd pmc405de PMC405DE - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1165 Active powerpc ppc4xx - esd pmc405de PMC405DE - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1165 Active powerpc ppc4xx - esd pmc440 PMC440 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1166 Active powerpc ppc4xx - esd pmc440 PMC440 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1166 Active powerpc ppc4xx - esd voh405 VOH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1167 Active powerpc ppc4xx - esd voh405 VOH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1167 Active powerpc ppc4xx - esd vom405 VOM405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1168 Active powerpc ppc4xx - esd vom405 VOM405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1168 Active powerpc ppc4xx - esd wuh405 WUH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1169 Active powerpc ppc4xx - esd wuh405 WUH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1169 Active powerpc ppc4xx - gdsys - dlvision - Dirk Eibach <eibach@gdsys.de> 1170 Active powerpc ppc4xx - gdsys - dlvision - Dirk Eibach <eibach@gdsys.de>
1170 Active powerpc ppc4xx - gdsys - gdppc440etx - Dirk Eibach <eibach@gdsys.de> 1171 Active powerpc ppc4xx - gdsys - gdppc440etx - Dirk Eibach <eibach@gdsys.de>
1171 Active powerpc ppc4xx - gdsys 405ep dlvision-10g - Dirk Eibach <eibach@gdsys.de> 1172 Active powerpc ppc4xx - gdsys 405ep dlvision-10g - Dirk Eibach <eibach@gdsys.de>
1172 Active powerpc ppc4xx - gdsys 405ep io - Dirk Eibach <eibach@gdsys.de> 1173 Active powerpc ppc4xx - gdsys 405ep io - Dirk Eibach <eibach@gdsys.de>
1173 Active powerpc ppc4xx - gdsys 405ep iocon - Dirk Eibach <eibach@gdsys.de> 1174 Active powerpc ppc4xx - gdsys 405ep iocon - Dirk Eibach <eibach@gdsys.de>
1174 Active powerpc ppc4xx - gdsys 405ep neo - Dirk Eibach <eibach@gdsys.de> 1175 Active powerpc ppc4xx - gdsys 405ep neo - Dirk Eibach <eibach@gdsys.de>
1175 Active powerpc ppc4xx - gdsys 405ex io64 - Dirk Eibach <eibach@gdsys.de> 1176 Active powerpc ppc4xx - gdsys 405ex io64 - Dirk Eibach <eibach@gdsys.de>
1176 Active powerpc ppc4xx - gdsys intip devconcenter intip:DEVCONCENTER Dirk Eibach <eibach@gdsys.de> 1177 Active powerpc ppc4xx - gdsys intip devconcenter intip:DEVCONCENTER Dirk Eibach <eibach@gdsys.de>
1177 Active powerpc ppc4xx - gdsys intip intip intip:INTIB Dirk Eibach <eibach@gdsys.de> 1178 Active powerpc ppc4xx - gdsys intip intip intip:INTIB Dirk Eibach <eibach@gdsys.de>
1178 Active powerpc ppc4xx - mosaixtech - icon - Stefan Roese <sr@denx.de> 1179 Active powerpc ppc4xx - mosaixtech - icon - Stefan Roese <sr@denx.de>
1179 Active powerpc ppc4xx - mpl mip405 MIP405 - Denis Peter <d.peter@mpl.ch> 1180 Active powerpc ppc4xx - mpl mip405 MIP405 - Denis Peter <d.peter@mpl.ch>
1180 Active powerpc ppc4xx - mpl mip405 MIP405T MIP405:MIP405T Denis Peter <d.peter@mpl.ch> 1181 Active powerpc ppc4xx - mpl mip405 MIP405T MIP405:MIP405T Denis Peter <d.peter@mpl.ch>
1181 Active powerpc ppc4xx - mpl pip405 PIP405 - Denis Peter <d.peter@mpl.ch> 1182 Active powerpc ppc4xx - mpl pip405 PIP405 - Denis Peter <d.peter@mpl.ch>
1182 Active powerpc ppc4xx - prodrive - alpr - Stefan Roese <sr@denx.de> 1183 Active powerpc ppc4xx - prodrive - alpr - Stefan Roese <sr@denx.de>
1183 Active powerpc ppc4xx - prodrive - p3p440 - Stefan Roese <sr@denx.de> 1184 Active powerpc ppc4xx - prodrive - p3p440 - Stefan Roese <sr@denx.de>
1184 Active powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer (travis.sawyer@sandburst.com> 1185 Active powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer (travis.sawyer@sandburst.com>
1185 Active powerpc ppc4xx - sandburst metrobox METROBOX - Travis Sawyer (travis.sawyer@sandburst.com> 1186 Active powerpc ppc4xx - sandburst metrobox METROBOX - Travis Sawyer (travis.sawyer@sandburst.com>
1186 Active powerpc ppc4xx - xes - xpedite1000 - Peter Tyser <ptyser@xes-inc.com> 1187 Active powerpc ppc4xx - xes - xpedite1000 - Peter Tyser <ptyser@xes-inc.com>
1187 Active powerpc ppc4xx - xilinx ml507 ml507 ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es> 1188 Active powerpc ppc4xx - xilinx ml507 ml507 ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
1188 Active powerpc ppc4xx - xilinx ml507 ml507_flash ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es> 1189 Active powerpc ppc4xx - xilinx ml507 ml507_flash ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
1189 Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic xilinx-ppc405-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000 Ricardo Ribalda <ricardo.ribalda@uam.es> 1190 Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic xilinx-ppc405-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000 Ricardo Ribalda <ricardo.ribalda@uam.es>
1190 Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic_flash xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es> 1191 Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic_flash xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es>
1191 Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1 Ricardo Ribalda <ricardo.ribalda@uam.es> 1192 Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1 Ricardo Ribalda <ricardo.ribalda@uam.es>
1192 Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic_flash xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es> 1193 Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic_flash xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es>
1193 Active sandbox sandbox - sandbox sandbox sandbox - Simon Glass <sjg@chromium.org> 1194 Active sandbox sandbox - sandbox sandbox sandbox - Simon Glass <sjg@chromium.org>
1194 Active sh sh2 - renesas rsk7203 rsk7203 - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1195 Active sh sh2 - renesas rsk7203 rsk7203 - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1195 Active sh sh2 - renesas rsk7264 rsk7264 - Phil Edworthy <phil.edworthy@renesas.com> 1196 Active sh sh2 - renesas rsk7264 rsk7264 - Phil Edworthy <phil.edworthy@renesas.com>
1196 Active sh sh2 - renesas rsk7269 rsk7269 - - 1197 Active sh sh2 - renesas rsk7269 rsk7269 - -
1197 Active sh sh3 - - mpr2 mpr2 - Mark Jonas <mark.jonas@de.bosch.com> 1198 Active sh sh3 - - mpr2 mpr2 - Mark Jonas <mark.jonas@de.bosch.com>
1198 Active sh sh3 - - ms7720se ms7720se - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 1199 Active sh sh3 - - ms7720se ms7720se - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
1199 Active sh sh3 - - shmin shmin - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1200 Active sh sh3 - - shmin shmin - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1200 Active sh sh4 - - espt espt - - 1201 Active sh sh4 - - espt espt - -
1201 Active sh sh4 - - ms7722se ms7722se - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1202 Active sh sh4 - - ms7722se ms7722se - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1202 Active sh sh4 - - ms7750se ms7750se - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1203 Active sh sh4 - - ms7750se ms7750se - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1203 Active sh sh4 - alphaproject ap_sh4a_4a ap_sh4a_4a - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1204 Active sh sh4 - alphaproject ap_sh4a_4a ap_sh4a_4a - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1204 Active sh sh4 - renesas ap325rxa ap325rxa - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1205 Active sh sh4 - renesas ap325rxa ap325rxa - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1205 Active sh sh4 - renesas ecovec ecovec - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1206 Active sh sh4 - renesas ecovec ecovec - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1206 Active sh sh4 - renesas MigoR MigoR - - 1207 Active sh sh4 - renesas MigoR MigoR - -
1207 Active sh sh4 - renesas r0p7734 r0p7734 - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1208 Active sh sh4 - renesas r0p7734 r0p7734 - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1208 Active sh sh4 - renesas r2dplus r2dplus - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1209 Active sh sh4 - renesas r2dplus r2dplus - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1209 Active sh sh4 - renesas r7780mp r7780mp - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1210 Active sh sh4 - renesas r7780mp r7780mp - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1210 Active sh sh4 - renesas sh7752evb sh7752evb - - 1211 Active sh sh4 - renesas sh7752evb sh7752evb - -
1211 Active sh sh4 - renesas sh7753evb sh7753evb - - 1212 Active sh sh4 - renesas sh7753evb sh7753evb - -
1212 Active sh sh4 - renesas sh7757lcr sh7757lcr - - 1213 Active sh sh4 - renesas sh7757lcr sh7757lcr - -
1213 Active sh sh4 - renesas sh7763rdp sh7763rdp - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1214 Active sh sh4 - renesas sh7763rdp sh7763rdp - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1214 Active sh sh4 - renesas sh7785lcr sh7785lcr - - 1215 Active sh sh4 - renesas sh7785lcr sh7785lcr - -
1215 Active sh sh4 - renesas sh7785lcr sh7785lcr_32bit sh7785lcr:SH_32BIT=1 - 1216 Active sh sh4 - renesas sh7785lcr sh7785lcr_32bit sh7785lcr:SH_32BIT=1 -
1216 Active sparc leon2 - gaisler - grsim_leon2 - - 1217 Active sparc leon2 - gaisler - grsim_leon2 - -
1217 Active sparc leon3 - gaisler - gr_cpci_ax2000 - - 1218 Active sparc leon3 - gaisler - gr_cpci_ax2000 - -
1218 Active sparc leon3 - gaisler - gr_ep2s60 - - 1219 Active sparc leon3 - gaisler - gr_ep2s60 - -
1219 Active sparc leon3 - gaisler - gr_xc3s_1500 - - 1220 Active sparc leon3 - gaisler - gr_xc3s_1500 - -
1220 Active sparc leon3 - gaisler - grsim - - 1221 Active sparc leon3 - gaisler - grsim - -
1221 Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 - 1222 Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 -
1222 Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de> 1223 Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
1223 Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de> 1224 Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
1224 Orphan arm pxa - - - lubbock - (dead address) Kyle Harris <kharris@nexus-tech.net> 1225 Orphan arm pxa - - - lubbock - (dead address) Kyle Harris <kharris@nexus-tech.net>
1225 Orphan powerpc 74xx_7xx - - evb64260 EVB64260 EVB64260 - 1226 Orphan powerpc 74xx_7xx - - evb64260 EVB64260 EVB64260 -
1226 Orphan powerpc 74xx_7xx - - evb64260 EVB64260_750CX EVB64260 Eran Man <eran@nbase.co.il> 1227 Orphan powerpc 74xx_7xx - - evb64260 EVB64260_750CX EVB64260 Eran Man <eran@nbase.co.il>
1227 Orphan powerpc mpc824x - - mousse MOUSSE - - 1228 Orphan powerpc mpc824x - - mousse MOUSSE - -
1228 Orphan powerpc mpc8260 - - - rsdproto - - 1229 Orphan powerpc mpc8260 - - - rsdproto - -
1229 Orphan powerpc mpc8260 - - rpxsuper RPXsuper - - 1230 Orphan powerpc mpc8260 - - rpxsuper RPXsuper - -
1230 Orphan powerpc mpc8xx - - - RPXClassic - - 1231 Orphan powerpc mpc8xx - - - RPXClassic - -
1231 Orphan powerpc mpc8xx - - - RPXlite - - 1232 Orphan powerpc mpc8xx - - - RPXlite - -
1232 Orphan powerpc mpc8xx - - fads ADS860 - - 1233 Orphan powerpc mpc8xx - - fads ADS860 - -
1233 Orphan powerpc mpc8xx - - fads FADS823 - - 1234 Orphan powerpc mpc8xx - - fads FADS823 - -
1234 Orphan powerpc mpc8xx - - fads FADS850SAR - - 1235 Orphan powerpc mpc8xx - - fads FADS850SAR - -
1235 Orphan powerpc mpc8xx - - fads FADS860T - - 1236 Orphan powerpc mpc8xx - - fads FADS860T - -
1236 Orphan powerpc mpc8xx - - genietv GENIETV - - 1237 Orphan powerpc mpc8xx - - genietv GENIETV - -
1237 Orphan powerpc mpc8xx - - mbx8xx MBX - - 1238 Orphan powerpc mpc8xx - - mbx8xx MBX - -
1238 Orphan powerpc mpc8xx - - mbx8xx MBX860T - - 1239 Orphan powerpc mpc8xx - - mbx8xx MBX860T - -
1239 Orphan powerpc mpc8xx - - nx823 NX823 - - 1240 Orphan powerpc mpc8xx - - nx823 NX823 - -
1240 1241
1241 1242
include/configs/B4860QDS.h
1 /* 1 /*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __CONFIG_H 7 #ifndef __CONFIG_H
8 #define __CONFIG_H 8 #define __CONFIG_H
9 9
10 /* 10 /*
11 * B4860 QDS board configuration file 11 * B4860 QDS board configuration file
12 */ 12 */
13 #define CONFIG_B4860QDS 13 #define CONFIG_B4860QDS
14 #define CONFIG_PHYS_64BIT 14 #define CONFIG_PHYS_64BIT
15 15
16 #ifdef CONFIG_RAMBOOT_PBL 16 #ifdef CONFIG_RAMBOOT_PBL
17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
19 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg 19 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
20 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg 20 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
21 #endif 21 #endif
22 22
23 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 23 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
24 /* Set 1M boot space */ 24 /* Set 1M boot space */
25 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 25 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
26 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 26 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
27 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 27 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
28 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 28 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
29 #define CONFIG_SYS_NO_FLASH 29 #define CONFIG_SYS_NO_FLASH
30 #endif 30 #endif
31 31
32 /* High Level Configuration Options */ 32 /* High Level Configuration Options */
33 #define CONFIG_BOOKE 33 #define CONFIG_BOOKE
34 #define CONFIG_E500 /* BOOKE e500 family */ 34 #define CONFIG_E500 /* BOOKE e500 family */
35 #define CONFIG_E500MC /* BOOKE e500mc family */ 35 #define CONFIG_E500MC /* BOOKE e500mc family */
36 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 36 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
37 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 37 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
38 #define CONFIG_MP /* support multiple processors */ 38 #define CONFIG_MP /* support multiple processors */
39 39
40 #ifndef CONFIG_SYS_TEXT_BASE 40 #ifndef CONFIG_SYS_TEXT_BASE
41 #define CONFIG_SYS_TEXT_BASE 0xeff80000 41 #define CONFIG_SYS_TEXT_BASE 0xeff80000
42 #endif 42 #endif
43 43
44 #ifndef CONFIG_RESET_VECTOR_ADDRESS 44 #ifndef CONFIG_RESET_VECTOR_ADDRESS
45 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 45 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
46 #endif 46 #endif
47 47
48 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 48 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
49 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 49 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
50 #define CONFIG_FSL_IFC /* Enable IFC Support */ 50 #define CONFIG_FSL_IFC /* Enable IFC Support */
51 #define CONFIG_PCI /* Enable PCI/PCIE */ 51 #define CONFIG_PCI /* Enable PCI/PCIE */
52 #define CONFIG_PCIE1 /* PCIE controler 1 */ 52 #define CONFIG_PCIE1 /* PCIE controler 1 */
53 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 53 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
54 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 54 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
55 55
56 #ifndef CONFIG_PPC_B4420 56 #ifndef CONFIG_PPC_B4420
57 #define CONFIG_SYS_SRIO 57 #define CONFIG_SYS_SRIO
58 #define CONFIG_SRIO1 /* SRIO port 1 */ 58 #define CONFIG_SRIO1 /* SRIO port 1 */
59 #define CONFIG_SRIO2 /* SRIO port 2 */ 59 #define CONFIG_SRIO2 /* SRIO port 2 */
60 #define CONFIG_SRIO_PCIE_BOOT_MASTER 60 #define CONFIG_SRIO_PCIE_BOOT_MASTER
61 #endif 61 #endif
62 62
63 #define CONFIG_FSL_LAW /* Use common FSL init code */ 63 #define CONFIG_FSL_LAW /* Use common FSL init code */
64 64
65 /* I2C bus multiplexer */ 65 /* I2C bus multiplexer */
66 #define I2C_MUX_PCA_ADDR 0x77 66 #define I2C_MUX_PCA_ADDR 0x77
67 67
68 /* VSC Crossbar switches */ 68 /* VSC Crossbar switches */
69 #define CONFIG_VSC_CROSSBAR 69 #define CONFIG_VSC_CROSSBAR
70 #define I2C_CH_DEFAULT 0x8 70 #define I2C_CH_DEFAULT 0x8
71 #define I2C_CH_VSC3316 0xc 71 #define I2C_CH_VSC3316 0xc
72 #define I2C_CH_VSC3308 0xd 72 #define I2C_CH_VSC3308 0xd
73 73
74 #define VSC3316_TX_ADDRESS 0x70 74 #define VSC3316_TX_ADDRESS 0x70
75 #define VSC3316_RX_ADDRESS 0x71 75 #define VSC3316_RX_ADDRESS 0x71
76 #define VSC3308_TX_ADDRESS 0x02 76 #define VSC3308_TX_ADDRESS 0x02
77 #define VSC3308_RX_ADDRESS 0x03 77 #define VSC3308_RX_ADDRESS 0x03
78 78
79 /* IDT clock synthesizers */ 79 /* IDT clock synthesizers */
80 #define CONFIG_IDT8T49N222A 80 #define CONFIG_IDT8T49N222A
81 #define I2C_CH_IDT 0x9 81 #define I2C_CH_IDT 0x9
82 82
83 #define IDT_SERDES1_ADDRESS 0x6E 83 #define IDT_SERDES1_ADDRESS 0x6E
84 #define IDT_SERDES2_ADDRESS 0x6C 84 #define IDT_SERDES2_ADDRESS 0x6C
85 85
86 #define CONFIG_ENV_OVERWRITE 86 #define CONFIG_ENV_OVERWRITE
87 87
88 #ifdef CONFIG_SYS_NO_FLASH 88 #ifdef CONFIG_SYS_NO_FLASH
89 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 89 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
90 #define CONFIG_ENV_IS_NOWHERE 90 #define CONFIG_ENV_IS_NOWHERE
91 #endif 91 #endif
92 #else 92 #else
93 #define CONFIG_FLASH_CFI_DRIVER 93 #define CONFIG_FLASH_CFI_DRIVER
94 #define CONFIG_SYS_FLASH_CFI 94 #define CONFIG_SYS_FLASH_CFI
95 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 95 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
96 #endif 96 #endif
97 97
98 #if defined(CONFIG_SPIFLASH) 98 #if defined(CONFIG_SPIFLASH)
99 #define CONFIG_SYS_EXTRA_ENV_RELOC 99 #define CONFIG_SYS_EXTRA_ENV_RELOC
100 #define CONFIG_ENV_IS_IN_SPI_FLASH 100 #define CONFIG_ENV_IS_IN_SPI_FLASH
101 #define CONFIG_ENV_SPI_BUS 0 101 #define CONFIG_ENV_SPI_BUS 0
102 #define CONFIG_ENV_SPI_CS 0 102 #define CONFIG_ENV_SPI_CS 0
103 #define CONFIG_ENV_SPI_MAX_HZ 10000000 103 #define CONFIG_ENV_SPI_MAX_HZ 10000000
104 #define CONFIG_ENV_SPI_MODE 0 104 #define CONFIG_ENV_SPI_MODE 0
105 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 105 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
106 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 106 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
107 #define CONFIG_ENV_SECT_SIZE 0x10000 107 #define CONFIG_ENV_SECT_SIZE 0x10000
108 #elif defined(CONFIG_SDCARD) 108 #elif defined(CONFIG_SDCARD)
109 #define CONFIG_SYS_EXTRA_ENV_RELOC 109 #define CONFIG_SYS_EXTRA_ENV_RELOC
110 #define CONFIG_ENV_IS_IN_MMC 110 #define CONFIG_ENV_IS_IN_MMC
111 #define CONFIG_SYS_MMC_ENV_DEV 0 111 #define CONFIG_SYS_MMC_ENV_DEV 0
112 #define CONFIG_ENV_SIZE 0x2000 112 #define CONFIG_ENV_SIZE 0x2000
113 #define CONFIG_ENV_OFFSET (512 * 1097) 113 #define CONFIG_ENV_OFFSET (512 * 1097)
114 #elif defined(CONFIG_NAND) 114 #elif defined(CONFIG_NAND)
115 #define CONFIG_SYS_EXTRA_ENV_RELOC 115 #define CONFIG_SYS_EXTRA_ENV_RELOC
116 #define CONFIG_ENV_IS_IN_NAND 116 #define CONFIG_ENV_IS_IN_NAND
117 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 117 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
118 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 118 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
119 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 119 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
120 #define CONFIG_ENV_IS_IN_REMOTE 120 #define CONFIG_ENV_IS_IN_REMOTE
121 #define CONFIG_ENV_ADDR 0xffe20000 121 #define CONFIG_ENV_ADDR 0xffe20000
122 #define CONFIG_ENV_SIZE 0x2000 122 #define CONFIG_ENV_SIZE 0x2000
123 #elif defined(CONFIG_ENV_IS_NOWHERE) 123 #elif defined(CONFIG_ENV_IS_NOWHERE)
124 #define CONFIG_ENV_SIZE 0x2000 124 #define CONFIG_ENV_SIZE 0x2000
125 #else 125 #else
126 #define CONFIG_ENV_IS_IN_FLASH 126 #define CONFIG_ENV_IS_IN_FLASH
127 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 127 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
128 #define CONFIG_ENV_SIZE 0x2000 128 #define CONFIG_ENV_SIZE 0x2000
129 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 129 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
130 #endif 130 #endif
131 131
132 #ifndef __ASSEMBLY__ 132 #ifndef __ASSEMBLY__
133 unsigned long get_board_sys_clk(void); 133 unsigned long get_board_sys_clk(void);
134 unsigned long get_board_ddr_clk(void); 134 unsigned long get_board_ddr_clk(void);
135 #endif 135 #endif
136 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 136 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
137 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 137 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
138 138
139 /* 139 /*
140 * These can be toggled for performance analysis, otherwise use default. 140 * These can be toggled for performance analysis, otherwise use default.
141 */ 141 */
142 #define CONFIG_SYS_CACHE_STASHING 142 #define CONFIG_SYS_CACHE_STASHING
143 #define CONFIG_BTB /* toggle branch predition */ 143 #define CONFIG_BTB /* toggle branch predition */
144 #define CONFIG_DDR_ECC 144 #define CONFIG_DDR_ECC
145 #ifdef CONFIG_DDR_ECC 145 #ifdef CONFIG_DDR_ECC
146 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 146 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
147 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 147 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
148 #endif 148 #endif
149 149
150 #define CONFIG_ENABLE_36BIT_PHYS 150 #define CONFIG_ENABLE_36BIT_PHYS
151 151
152 #ifdef CONFIG_PHYS_64BIT 152 #ifdef CONFIG_PHYS_64BIT
153 #define CONFIG_ADDR_MAP 153 #define CONFIG_ADDR_MAP
154 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 154 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
155 #endif 155 #endif
156 156
157 #if 0 157 #if 0
158 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 158 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
159 #endif 159 #endif
160 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 160 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
161 #define CONFIG_SYS_MEMTEST_END 0x00400000 161 #define CONFIG_SYS_MEMTEST_END 0x00400000
162 #define CONFIG_SYS_ALT_MEMTEST 162 #define CONFIG_SYS_ALT_MEMTEST
163 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 163 #define CONFIG_PANIC_HANG /* do not reset board on panic */
164 164
165 /* 165 /*
166 * Config the L3 Cache as L3 SRAM 166 * Config the L3 Cache as L3 SRAM
167 */ 167 */
168 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 168 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
169 169
170 #ifdef CONFIG_PHYS_64BIT 170 #ifdef CONFIG_PHYS_64BIT
171 #define CONFIG_SYS_DCSRBAR 0xf0000000 171 #define CONFIG_SYS_DCSRBAR 0xf0000000
172 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 172 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
173 #endif 173 #endif
174 174
175 /* EEPROM */ 175 /* EEPROM */
176 #define CONFIG_SYS_I2C_EEPROM_NXID 176 #define CONFIG_SYS_I2C_EEPROM_NXID
177 #define CONFIG_SYS_EEPROM_BUS_NUM 0 177 #define CONFIG_SYS_EEPROM_BUS_NUM 0
178 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 178 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
179 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 179 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
180 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 180 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
181 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 181 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
182 182
183 /* 183 /*
184 * DDR Setup 184 * DDR Setup
185 */ 185 */
186 #define CONFIG_VERY_BIG_RAM 186 #define CONFIG_VERY_BIG_RAM
187 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 187 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
188 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 188 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
189 189
190 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 190 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
191 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 191 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
192 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 192 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
193 193
194 #define CONFIG_DDR_SPD 194 #define CONFIG_DDR_SPD
195 #define CONFIG_SYS_DDR_RAW_TIMING 195 #define CONFIG_SYS_DDR_RAW_TIMING
196 #define CONFIG_SYS_FSL_DDR3 196 #define CONFIG_SYS_FSL_DDR3
197 #define CONFIG_FSL_DDR_INTERACTIVE 197 #define CONFIG_FSL_DDR_INTERACTIVE
198 198
199 #define CONFIG_SYS_SPD_BUS_NUM 0 199 #define CONFIG_SYS_SPD_BUS_NUM 0
200 #define SPD_EEPROM_ADDRESS1 0x51 200 #define SPD_EEPROM_ADDRESS1 0x51
201 #define SPD_EEPROM_ADDRESS2 0x53 201 #define SPD_EEPROM_ADDRESS2 0x53
202 202
203 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 203 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
204 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 204 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
205 205
206 /* 206 /*
207 * IFC Definitions 207 * IFC Definitions
208 */ 208 */
209 #define CONFIG_SYS_FLASH_BASE 0xe0000000 209 #define CONFIG_SYS_FLASH_BASE 0xe0000000
210 #ifdef CONFIG_PHYS_64BIT 210 #ifdef CONFIG_PHYS_64BIT
211 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 211 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
212 #else 212 #else
213 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 213 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
214 #endif 214 #endif
215 215
216 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 216 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
217 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 217 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
218 + 0x8000000) | \ 218 + 0x8000000) | \
219 CSPR_PORT_SIZE_16 | \ 219 CSPR_PORT_SIZE_16 | \
220 CSPR_MSEL_NOR | \ 220 CSPR_MSEL_NOR | \
221 CSPR_V) 221 CSPR_V)
222 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 222 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
223 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 223 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
224 CSPR_PORT_SIZE_16 | \ 224 CSPR_PORT_SIZE_16 | \
225 CSPR_MSEL_NOR | \ 225 CSPR_MSEL_NOR | \
226 CSPR_V) 226 CSPR_V)
227 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 227 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
228 /* NOR Flash Timing Params */ 228 /* NOR Flash Timing Params */
229 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 229 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
230 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 230 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
231 FTIM0_NOR_TEADC(0x04) | \ 231 FTIM0_NOR_TEADC(0x04) | \
232 FTIM0_NOR_TEAHC(0x20)) 232 FTIM0_NOR_TEAHC(0x20))
233 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 233 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
234 FTIM1_NOR_TRAD_NOR(0x1A) |\ 234 FTIM1_NOR_TRAD_NOR(0x1A) |\
235 FTIM1_NOR_TSEQRAD_NOR(0x13)) 235 FTIM1_NOR_TSEQRAD_NOR(0x13))
236 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 236 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
237 FTIM2_NOR_TCH(0x0E) | \ 237 FTIM2_NOR_TCH(0x0E) | \
238 FTIM2_NOR_TWPH(0x0E) | \ 238 FTIM2_NOR_TWPH(0x0E) | \
239 FTIM2_NOR_TWP(0x1c)) 239 FTIM2_NOR_TWP(0x1c))
240 #define CONFIG_SYS_NOR_FTIM3 0x0 240 #define CONFIG_SYS_NOR_FTIM3 0x0
241 241
242 #define CONFIG_SYS_FLASH_QUIET_TEST 242 #define CONFIG_SYS_FLASH_QUIET_TEST
243 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 243 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
244 244
245 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 245 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
246 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 246 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
247 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 247 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
248 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 248 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
249 249
250 #define CONFIG_SYS_FLASH_EMPTY_INFO 250 #define CONFIG_SYS_FLASH_EMPTY_INFO
251 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 251 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
252 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 252 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
253 253
254 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 254 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
255 #define CONFIG_FSL_QIXIS_V2 255 #define CONFIG_FSL_QIXIS_V2
256 #define QIXIS_BASE 0xffdf0000 256 #define QIXIS_BASE 0xffdf0000
257 #ifdef CONFIG_PHYS_64BIT 257 #ifdef CONFIG_PHYS_64BIT
258 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 258 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
259 #else 259 #else
260 #define QIXIS_BASE_PHYS QIXIS_BASE 260 #define QIXIS_BASE_PHYS QIXIS_BASE
261 #endif 261 #endif
262 #define QIXIS_LBMAP_SWITCH 0x01 262 #define QIXIS_LBMAP_SWITCH 0x01
263 #define QIXIS_LBMAP_MASK 0x0f 263 #define QIXIS_LBMAP_MASK 0x0f
264 #define QIXIS_LBMAP_SHIFT 0 264 #define QIXIS_LBMAP_SHIFT 0
265 #define QIXIS_LBMAP_DFLTBANK 0x00 265 #define QIXIS_LBMAP_DFLTBANK 0x00
266 #define QIXIS_LBMAP_ALTBANK 0x02 266 #define QIXIS_LBMAP_ALTBANK 0x02
267 #define QIXIS_RST_CTL_RESET 0x31 267 #define QIXIS_RST_CTL_RESET 0x31
268 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 268 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
269 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 269 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
270 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 270 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
271 271
272 #define CONFIG_SYS_CSPR3_EXT (0xf) 272 #define CONFIG_SYS_CSPR3_EXT (0xf)
273 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 273 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
274 | CSPR_PORT_SIZE_8 \ 274 | CSPR_PORT_SIZE_8 \
275 | CSPR_MSEL_GPCM \ 275 | CSPR_MSEL_GPCM \
276 | CSPR_V) 276 | CSPR_V)
277 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 277 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
278 #define CONFIG_SYS_CSOR3 0x0 278 #define CONFIG_SYS_CSOR3 0x0
279 /* QIXIS Timing parameters for IFC CS3 */ 279 /* QIXIS Timing parameters for IFC CS3 */
280 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 280 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
281 FTIM0_GPCM_TEADC(0x0e) | \ 281 FTIM0_GPCM_TEADC(0x0e) | \
282 FTIM0_GPCM_TEAHC(0x0e)) 282 FTIM0_GPCM_TEAHC(0x0e))
283 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 283 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
284 FTIM1_GPCM_TRAD(0x1f)) 284 FTIM1_GPCM_TRAD(0x1f))
285 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 285 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
286 FTIM2_GPCM_TCH(0x0) | \ 286 FTIM2_GPCM_TCH(0x0) | \
287 FTIM2_GPCM_TWP(0x1f)) 287 FTIM2_GPCM_TWP(0x1f))
288 #define CONFIG_SYS_CS3_FTIM3 0x0 288 #define CONFIG_SYS_CS3_FTIM3 0x0
289 289
290 /* NAND Flash on IFC */ 290 /* NAND Flash on IFC */
291 #define CONFIG_NAND_FSL_IFC 291 #define CONFIG_NAND_FSL_IFC
292 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
293 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
292 #define CONFIG_SYS_NAND_BASE 0xff800000 294 #define CONFIG_SYS_NAND_BASE 0xff800000
293 #ifdef CONFIG_PHYS_64BIT 295 #ifdef CONFIG_PHYS_64BIT
294 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 296 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
295 #else 297 #else
296 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 298 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
297 #endif 299 #endif
298 300
299 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 301 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
300 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 302 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
301 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 303 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
302 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 304 | CSPR_MSEL_NAND /* MSEL = NAND */ \
303 | CSPR_V) 305 | CSPR_V)
304 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 306 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
305 307
306 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 308 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
307 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 309 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
308 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 310 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
309 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 311 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
310 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 312 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
311 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 313 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
312 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 314 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
313 315
314 #define CONFIG_SYS_NAND_ONFI_DETECTION 316 #define CONFIG_SYS_NAND_ONFI_DETECTION
315 317
316 /* ONFI NAND Flash mode0 Timing Params */ 318 /* ONFI NAND Flash mode0 Timing Params */
317 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 319 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
318 FTIM0_NAND_TWP(0x18) | \ 320 FTIM0_NAND_TWP(0x18) | \
319 FTIM0_NAND_TWCHT(0x07) | \ 321 FTIM0_NAND_TWCHT(0x07) | \
320 FTIM0_NAND_TWH(0x0a)) 322 FTIM0_NAND_TWH(0x0a))
321 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 323 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
322 FTIM1_NAND_TWBE(0x39) | \ 324 FTIM1_NAND_TWBE(0x39) | \
323 FTIM1_NAND_TRR(0x0e) | \ 325 FTIM1_NAND_TRR(0x0e) | \
324 FTIM1_NAND_TRP(0x18)) 326 FTIM1_NAND_TRP(0x18))
325 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 327 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
326 FTIM2_NAND_TREH(0x0a) | \ 328 FTIM2_NAND_TREH(0x0a) | \
327 FTIM2_NAND_TWHRE(0x1e)) 329 FTIM2_NAND_TWHRE(0x1e))
328 #define CONFIG_SYS_NAND_FTIM3 0x0 330 #define CONFIG_SYS_NAND_FTIM3 0x0
329 331
330 #define CONFIG_SYS_NAND_DDR_LAW 11 332 #define CONFIG_SYS_NAND_DDR_LAW 11
331 333
332 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 334 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
333 #define CONFIG_SYS_MAX_NAND_DEVICE 1 335 #define CONFIG_SYS_MAX_NAND_DEVICE 1
334 #define CONFIG_MTD_NAND_VERIFY_WRITE 336 #define CONFIG_MTD_NAND_VERIFY_WRITE
335 #define CONFIG_CMD_NAND 337 #define CONFIG_CMD_NAND
336 338
337 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 339 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
338 340
339 #if defined(CONFIG_NAND) 341 #if defined(CONFIG_NAND)
340 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 342 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
341 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 343 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
342 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 344 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
343 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 345 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
344 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 346 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
345 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 347 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
346 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 348 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
347 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 349 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
348 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 350 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
349 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 351 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
350 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 352 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
351 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 353 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
352 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 354 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
353 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 355 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
354 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 356 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
355 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 357 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
356 #else 358 #else
357 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 359 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
358 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 360 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
359 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 361 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
360 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 362 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
361 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 363 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
362 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 364 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
363 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 365 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
364 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 366 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
365 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 367 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
366 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 368 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
367 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 369 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
368 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 370 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
369 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 371 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
370 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 372 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
371 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 373 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
372 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 374 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
373 #endif 375 #endif
374 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 376 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
375 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 377 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
376 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 378 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
377 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 379 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
378 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 380 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
379 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 381 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
380 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 382 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
381 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 383 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
382 384
383 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 385 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
384 386
385 #if defined(CONFIG_RAMBOOT_PBL) 387 #if defined(CONFIG_RAMBOOT_PBL)
386 #define CONFIG_SYS_RAMBOOT 388 #define CONFIG_SYS_RAMBOOT
387 #endif 389 #endif
388 390
389 #define CONFIG_BOARD_EARLY_INIT_R 391 #define CONFIG_BOARD_EARLY_INIT_R
390 #define CONFIG_MISC_INIT_R 392 #define CONFIG_MISC_INIT_R
391 393
392 #define CONFIG_HWCONFIG 394 #define CONFIG_HWCONFIG
393 395
394 /* define to use L1 as initial stack */ 396 /* define to use L1 as initial stack */
395 #define CONFIG_L1_INIT_RAM 397 #define CONFIG_L1_INIT_RAM
396 #define CONFIG_SYS_INIT_RAM_LOCK 398 #define CONFIG_SYS_INIT_RAM_LOCK
397 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 399 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
398 #ifdef CONFIG_PHYS_64BIT 400 #ifdef CONFIG_PHYS_64BIT
399 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 401 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
400 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 402 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
401 /* The assembler doesn't like typecast */ 403 /* The assembler doesn't like typecast */
402 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 404 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
403 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 405 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
404 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 406 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
405 #else 407 #else
406 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ 408 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */
407 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 409 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
408 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 410 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
409 #endif 411 #endif
410 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 412 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
411 413
412 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 414 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
413 GENERATED_GBL_DATA_SIZE) 415 GENERATED_GBL_DATA_SIZE)
414 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 416 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
415 417
416 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 418 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
417 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 419 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
418 420
419 /* Serial Port - controlled on board with jumper J8 421 /* Serial Port - controlled on board with jumper J8
420 * open - index 2 422 * open - index 2
421 * shorted - index 1 423 * shorted - index 1
422 */ 424 */
423 #define CONFIG_CONS_INDEX 1 425 #define CONFIG_CONS_INDEX 1
424 #define CONFIG_SYS_NS16550 426 #define CONFIG_SYS_NS16550
425 #define CONFIG_SYS_NS16550_SERIAL 427 #define CONFIG_SYS_NS16550_SERIAL
426 #define CONFIG_SYS_NS16550_REG_SIZE 1 428 #define CONFIG_SYS_NS16550_REG_SIZE 1
427 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 429 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
428 430
429 #define CONFIG_SYS_BAUDRATE_TABLE \ 431 #define CONFIG_SYS_BAUDRATE_TABLE \
430 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 432 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
431 433
432 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 434 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
433 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 435 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
434 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 436 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
435 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 437 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
436 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 438 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */
437 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 439 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
438 440
439 441
440 /* Use the HUSH parser */ 442 /* Use the HUSH parser */
441 #define CONFIG_SYS_HUSH_PARSER 443 #define CONFIG_SYS_HUSH_PARSER
442 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 444 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
443 445
444 /* pass open firmware flat tree */ 446 /* pass open firmware flat tree */
445 #define CONFIG_OF_LIBFDT 447 #define CONFIG_OF_LIBFDT
446 #define CONFIG_OF_BOARD_SETUP 448 #define CONFIG_OF_BOARD_SETUP
447 #define CONFIG_OF_STDOUT_VIA_ALIAS 449 #define CONFIG_OF_STDOUT_VIA_ALIAS
448 450
449 /* new uImage format support */ 451 /* new uImage format support */
450 #define CONFIG_FIT 452 #define CONFIG_FIT
451 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 453 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
452 454
453 /* I2C */ 455 /* I2C */
454 #define CONFIG_SYS_I2C 456 #define CONFIG_SYS_I2C
455 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 457 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
456 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 458 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
457 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 459 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
458 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 460 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
459 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 461 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
460 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 462 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
461 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 463 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
462 464
463 /* 465 /*
464 * RTC configuration 466 * RTC configuration
465 */ 467 */
466 #define RTC 468 #define RTC
467 #define CONFIG_RTC_DS3231 1 469 #define CONFIG_RTC_DS3231 1
468 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 470 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
469 471
470 /* 472 /*
471 * RapidIO 473 * RapidIO
472 */ 474 */
473 #ifdef CONFIG_SYS_SRIO 475 #ifdef CONFIG_SYS_SRIO
474 #ifdef CONFIG_SRIO1 476 #ifdef CONFIG_SRIO1
475 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 477 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
476 #ifdef CONFIG_PHYS_64BIT 478 #ifdef CONFIG_PHYS_64BIT
477 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 479 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
478 #else 480 #else
479 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 481 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
480 #endif 482 #endif
481 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 483 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
482 #endif 484 #endif
483 485
484 #ifdef CONFIG_SRIO2 486 #ifdef CONFIG_SRIO2
485 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 487 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
486 #ifdef CONFIG_PHYS_64BIT 488 #ifdef CONFIG_PHYS_64BIT
487 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 489 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
488 #else 490 #else
489 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 491 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
490 #endif 492 #endif
491 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 493 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
492 #endif 494 #endif
493 #endif 495 #endif
494 496
495 /* 497 /*
496 * for slave u-boot IMAGE instored in master memory space, 498 * for slave u-boot IMAGE instored in master memory space,
497 * PHYS must be aligned based on the SIZE 499 * PHYS must be aligned based on the SIZE
498 */ 500 */
499 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 501 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
500 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 502 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
501 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 503 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
502 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 504 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
503 /* 505 /*
504 * for slave UCODE and ENV instored in master memory space, 506 * for slave UCODE and ENV instored in master memory space,
505 * PHYS must be aligned based on the SIZE 507 * PHYS must be aligned based on the SIZE
506 */ 508 */
507 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 509 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
508 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 510 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
509 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 511 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
510 512
511 /* slave core release by master*/ 513 /* slave core release by master*/
512 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 514 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
513 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 515 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
514 516
515 /* 517 /*
516 * SRIO_PCIE_BOOT - SLAVE 518 * SRIO_PCIE_BOOT - SLAVE
517 */ 519 */
518 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 520 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
519 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 521 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
520 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 522 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
521 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 523 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
522 #endif 524 #endif
523 525
524 /* 526 /*
525 * eSPI - Enhanced SPI 527 * eSPI - Enhanced SPI
526 */ 528 */
527 #define CONFIG_FSL_ESPI 529 #define CONFIG_FSL_ESPI
528 #define CONFIG_SPI_FLASH 530 #define CONFIG_SPI_FLASH
529 #define CONFIG_SPI_FLASH_SST 531 #define CONFIG_SPI_FLASH_SST
530 #define CONFIG_CMD_SF 532 #define CONFIG_CMD_SF
531 #define CONFIG_SF_DEFAULT_SPEED 10000000 533 #define CONFIG_SF_DEFAULT_SPEED 10000000
532 #define CONFIG_SF_DEFAULT_MODE 0 534 #define CONFIG_SF_DEFAULT_MODE 0
533 535
534 /* 536 /*
535 * MAPLE 537 * MAPLE
536 */ 538 */
537 #ifdef CONFIG_PHYS_64BIT 539 #ifdef CONFIG_PHYS_64BIT
538 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 540 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
539 #else 541 #else
540 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 542 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
541 #endif 543 #endif
542 544
543 /* 545 /*
544 * General PCI 546 * General PCI
545 * Memory space is mapped 1-1, but I/O space must start from 0. 547 * Memory space is mapped 1-1, but I/O space must start from 0.
546 */ 548 */
547 549
548 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 550 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
549 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 551 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
550 #ifdef CONFIG_PHYS_64BIT 552 #ifdef CONFIG_PHYS_64BIT
551 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 553 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
552 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 554 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
553 #else 555 #else
554 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 556 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
555 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 557 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
556 #endif 558 #endif
557 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 559 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
558 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 560 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
559 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 561 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
560 #ifdef CONFIG_PHYS_64BIT 562 #ifdef CONFIG_PHYS_64BIT
561 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 563 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
562 #else 564 #else
563 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 565 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
564 #endif 566 #endif
565 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 567 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
566 568
567 /* Qman/Bman */ 569 /* Qman/Bman */
568 #ifndef CONFIG_NOBQFMAN 570 #ifndef CONFIG_NOBQFMAN
569 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 571 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
570 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 572 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
571 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 573 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
572 #ifdef CONFIG_PHYS_64BIT 574 #ifdef CONFIG_PHYS_64BIT
573 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 575 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
574 #else 576 #else
575 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 577 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
576 #endif 578 #endif
577 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 579 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
578 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 580 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
579 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 581 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
580 #ifdef CONFIG_PHYS_64BIT 582 #ifdef CONFIG_PHYS_64BIT
581 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 583 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
582 #else 584 #else
583 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 585 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
584 #endif 586 #endif
585 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 587 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
586 588
587 #define CONFIG_SYS_DPAA_FMAN 589 #define CONFIG_SYS_DPAA_FMAN
588 590
589 #define CONFIG_SYS_DPAA_RMAN 591 #define CONFIG_SYS_DPAA_RMAN
590 592
591 /* Default address of microcode for the Linux Fman driver */ 593 /* Default address of microcode for the Linux Fman driver */
592 #if defined(CONFIG_SPIFLASH) 594 #if defined(CONFIG_SPIFLASH)
593 /* 595 /*
594 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 596 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
595 * env, so we got 0x110000. 597 * env, so we got 0x110000.
596 */ 598 */
597 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 599 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
598 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 600 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
599 #elif defined(CONFIG_SDCARD) 601 #elif defined(CONFIG_SDCARD)
600 /* 602 /*
601 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 603 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
602 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 604 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
603 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 605 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
604 */ 606 */
605 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 607 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
606 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) 608 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
607 #elif defined(CONFIG_NAND) 609 #elif defined(CONFIG_NAND)
608 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 610 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
609 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 611 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
610 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 612 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
611 /* 613 /*
612 * Slave has no ucode locally, it can fetch this from remote. When implementing 614 * Slave has no ucode locally, it can fetch this from remote. When implementing
613 * in two corenet boards, slave's ucode could be stored in master's memory 615 * in two corenet boards, slave's ucode could be stored in master's memory
614 * space, the address can be mapped from slave TLB->slave LAW-> 616 * space, the address can be mapped from slave TLB->slave LAW->
615 * slave SRIO or PCIE outbound window->master inbound window-> 617 * slave SRIO or PCIE outbound window->master inbound window->
616 * master LAW->the ucode address in master's memory space. 618 * master LAW->the ucode address in master's memory space.
617 */ 619 */
618 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 620 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
619 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 621 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
620 #else 622 #else
621 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 623 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
622 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 624 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
623 #endif 625 #endif
624 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 626 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
625 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 627 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
626 #endif /* CONFIG_NOBQFMAN */ 628 #endif /* CONFIG_NOBQFMAN */
627 629
628 #ifdef CONFIG_SYS_DPAA_FMAN 630 #ifdef CONFIG_SYS_DPAA_FMAN
629 #define CONFIG_FMAN_ENET 631 #define CONFIG_FMAN_ENET
630 #define CONFIG_PHYLIB_10G 632 #define CONFIG_PHYLIB_10G
631 #define CONFIG_PHY_VITESSE 633 #define CONFIG_PHY_VITESSE
632 #define CONFIG_PHY_TERANETICS 634 #define CONFIG_PHY_TERANETICS
633 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 635 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
634 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 636 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
635 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 637 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
636 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 638 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
637 #endif 639 #endif
638 640
639 #ifdef CONFIG_PCI 641 #ifdef CONFIG_PCI
640 #define CONFIG_PCI_INDIRECT_BRIDGE 642 #define CONFIG_PCI_INDIRECT_BRIDGE
641 #define CONFIG_NET_MULTI 643 #define CONFIG_NET_MULTI
642 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 644 #define CONFIG_PCI_PNP /* do pci plug-and-play */
643 #define CONFIG_E1000 645 #define CONFIG_E1000
644 646
645 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 647 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
646 #define CONFIG_DOS_PARTITION 648 #define CONFIG_DOS_PARTITION
647 #endif /* CONFIG_PCI */ 649 #endif /* CONFIG_PCI */
648 650
649 #ifdef CONFIG_FMAN_ENET 651 #ifdef CONFIG_FMAN_ENET
650 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 652 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10
651 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 653 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11
652 654
653 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 655 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
654 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 656 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
655 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 657 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
656 658
657 659
658 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 660 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
659 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 661 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
660 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 662 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
661 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 663 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
662 664
663 #define CONFIG_MII /* MII PHY management */ 665 #define CONFIG_MII /* MII PHY management */
664 #define CONFIG_ETHPRIME "FM1@DTSEC1" 666 #define CONFIG_ETHPRIME "FM1@DTSEC1"
665 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 667 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
666 #endif 668 #endif
667 669
668 /* 670 /*
669 * Environment 671 * Environment
670 */ 672 */
671 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 673 #define CONFIG_LOADS_ECHO /* echo on for serial download */
672 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 674 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
673 675
674 /* 676 /*
675 * Command line configuration. 677 * Command line configuration.
676 */ 678 */
677 #include <config_cmd_default.h> 679 #include <config_cmd_default.h>
678 680
679 #define CONFIG_CMD_DATE 681 #define CONFIG_CMD_DATE
680 #define CONFIG_CMD_DHCP 682 #define CONFIG_CMD_DHCP
681 #define CONFIG_CMD_EEPROM 683 #define CONFIG_CMD_EEPROM
682 #define CONFIG_CMD_ELF 684 #define CONFIG_CMD_ELF
683 #define CONFIG_CMD_ERRATA 685 #define CONFIG_CMD_ERRATA
684 #define CONFIG_CMD_GREPENV 686 #define CONFIG_CMD_GREPENV
685 #define CONFIG_CMD_IRQ 687 #define CONFIG_CMD_IRQ
686 #define CONFIG_CMD_I2C 688 #define CONFIG_CMD_I2C
687 #define CONFIG_CMD_MII 689 #define CONFIG_CMD_MII
688 #define CONFIG_CMD_PING 690 #define CONFIG_CMD_PING
689 #define CONFIG_CMD_REGINFO 691 #define CONFIG_CMD_REGINFO
690 #define CONFIG_CMD_SETEXPR 692 #define CONFIG_CMD_SETEXPR
691 693
692 #ifdef CONFIG_PCI 694 #ifdef CONFIG_PCI
693 #define CONFIG_CMD_PCI 695 #define CONFIG_CMD_PCI
694 #define CONFIG_CMD_NET 696 #define CONFIG_CMD_NET
695 #endif 697 #endif
696 698
697 /* 699 /*
698 * USB 700 * USB
699 */ 701 */
700 #define CONFIG_HAS_FSL_DR_USB 702 #define CONFIG_HAS_FSL_DR_USB
701 703
702 #ifdef CONFIG_HAS_FSL_DR_USB 704 #ifdef CONFIG_HAS_FSL_DR_USB
703 #define CONFIG_USB_EHCI 705 #define CONFIG_USB_EHCI
704 706
705 #ifdef CONFIG_USB_EHCI 707 #ifdef CONFIG_USB_EHCI
706 #define CONFIG_CMD_USB 708 #define CONFIG_CMD_USB
707 #define CONFIG_USB_STORAGE 709 #define CONFIG_USB_STORAGE
708 #define CONFIG_USB_EHCI_FSL 710 #define CONFIG_USB_EHCI_FSL
709 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 711 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
710 #define CONFIG_CMD_EXT2 712 #define CONFIG_CMD_EXT2
711 #endif 713 #endif
712 #endif 714 #endif
713 715
714 /* 716 /*
715 * Miscellaneous configurable options 717 * Miscellaneous configurable options
716 */ 718 */
717 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 719 #define CONFIG_SYS_LONGHELP /* undef to save memory */
718 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 720 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
719 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 721 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
720 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 722 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
721 #ifdef CONFIG_CMD_KGDB 723 #ifdef CONFIG_CMD_KGDB
722 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 724 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
723 #else 725 #else
724 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 726 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
725 #endif 727 #endif
726 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 728 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
727 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 729 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
728 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 730 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
729 731
730 /* 732 /*
731 * For booting Linux, the board info and command line data 733 * For booting Linux, the board info and command line data
732 * have to be in the first 64 MB of memory, since this is 734 * have to be in the first 64 MB of memory, since this is
733 * the maximum mapped by the Linux kernel during initialization. 735 * the maximum mapped by the Linux kernel during initialization.
734 */ 736 */
735 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 737 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
736 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 738 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
737 739
738 #ifdef CONFIG_CMD_KGDB 740 #ifdef CONFIG_CMD_KGDB
739 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 741 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
740 #endif 742 #endif
741 743
742 /* 744 /*
743 * Environment Configuration 745 * Environment Configuration
744 */ 746 */
745 #define CONFIG_ROOTPATH "/opt/nfsroot" 747 #define CONFIG_ROOTPATH "/opt/nfsroot"
746 #define CONFIG_BOOTFILE "uImage" 748 #define CONFIG_BOOTFILE "uImage"
747 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 749 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
748 750
749 /* default location for tftp and bootm */ 751 /* default location for tftp and bootm */
750 #define CONFIG_LOADADDR 1000000 752 #define CONFIG_LOADADDR 1000000
751 753
752 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 754 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
753 755
754 #define CONFIG_BAUDRATE 115200 756 #define CONFIG_BAUDRATE 115200
755 757
756 #define __USB_PHY_TYPE ulpi 758 #define __USB_PHY_TYPE ulpi
757 759
758 #define CONFIG_EXTRA_ENV_SETTINGS \ 760 #define CONFIG_EXTRA_ENV_SETTINGS \
759 "hwconfig=fsl_ddr:ctlr_intlv=null," \ 761 "hwconfig=fsl_ddr:ctlr_intlv=null," \
760 "bank_intlv=cs0_cs1;" \ 762 "bank_intlv=cs0_cs1;" \
761 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 763 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
762 "netdev=eth0\0" \ 764 "netdev=eth0\0" \
763 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 765 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
764 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 766 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
765 "tftpflash=tftpboot $loadaddr $uboot && " \ 767 "tftpflash=tftpboot $loadaddr $uboot && " \
766 "protect off $ubootaddr +$filesize && " \ 768 "protect off $ubootaddr +$filesize && " \
767 "erase $ubootaddr +$filesize && " \ 769 "erase $ubootaddr +$filesize && " \
768 "cp.b $loadaddr $ubootaddr $filesize && " \ 770 "cp.b $loadaddr $ubootaddr $filesize && " \
769 "protect on $ubootaddr +$filesize && " \ 771 "protect on $ubootaddr +$filesize && " \
770 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 772 "cmp.b $loadaddr $ubootaddr $filesize\0" \
771 "consoledev=ttyS0\0" \ 773 "consoledev=ttyS0\0" \
772 "ramdiskaddr=2000000\0" \ 774 "ramdiskaddr=2000000\0" \
773 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 775 "ramdiskfile=b4860qds/ramdisk.uboot\0" \
774 "fdtaddr=c00000\0" \ 776 "fdtaddr=c00000\0" \
775 "fdtfile=b4860qds/b4860qds.dtb\0" \ 777 "fdtfile=b4860qds/b4860qds.dtb\0" \
776 "bdev=sda3\0" \ 778 "bdev=sda3\0" \
777 "c=ffe\0" 779 "c=ffe\0"
778 780
779 /* For emulation this causes u-boot to jump to the start of the proof point 781 /* For emulation this causes u-boot to jump to the start of the proof point
780 app code automatically */ 782 app code automatically */
781 #define CONFIG_PROOF_POINTS \ 783 #define CONFIG_PROOF_POINTS \
782 "setenv bootargs root=/dev/$bdev rw " \ 784 "setenv bootargs root=/dev/$bdev rw " \
783 "console=$consoledev,$baudrate $othbootargs;" \ 785 "console=$consoledev,$baudrate $othbootargs;" \
784 "cpu 1 release 0x29000000 - - -;" \ 786 "cpu 1 release 0x29000000 - - -;" \
785 "cpu 2 release 0x29000000 - - -;" \ 787 "cpu 2 release 0x29000000 - - -;" \
786 "cpu 3 release 0x29000000 - - -;" \ 788 "cpu 3 release 0x29000000 - - -;" \
787 "cpu 4 release 0x29000000 - - -;" \ 789 "cpu 4 release 0x29000000 - - -;" \
788 "cpu 5 release 0x29000000 - - -;" \ 790 "cpu 5 release 0x29000000 - - -;" \
789 "cpu 6 release 0x29000000 - - -;" \ 791 "cpu 6 release 0x29000000 - - -;" \
790 "cpu 7 release 0x29000000 - - -;" \ 792 "cpu 7 release 0x29000000 - - -;" \
791 "go 0x29000000" 793 "go 0x29000000"
792 794
793 #define CONFIG_HVBOOT \ 795 #define CONFIG_HVBOOT \
794 "setenv bootargs config-addr=0x60000000; " \ 796 "setenv bootargs config-addr=0x60000000; " \
795 "bootm 0x01000000 - 0x00f00000" 797 "bootm 0x01000000 - 0x00f00000"
796 798
797 #define CONFIG_ALU \ 799 #define CONFIG_ALU \
798 "setenv bootargs root=/dev/$bdev rw " \ 800 "setenv bootargs root=/dev/$bdev rw " \
799 "console=$consoledev,$baudrate $othbootargs;" \ 801 "console=$consoledev,$baudrate $othbootargs;" \
800 "cpu 1 release 0x01000000 - - -;" \ 802 "cpu 1 release 0x01000000 - - -;" \
801 "cpu 2 release 0x01000000 - - -;" \ 803 "cpu 2 release 0x01000000 - - -;" \
802 "cpu 3 release 0x01000000 - - -;" \ 804 "cpu 3 release 0x01000000 - - -;" \
803 "cpu 4 release 0x01000000 - - -;" \ 805 "cpu 4 release 0x01000000 - - -;" \
804 "cpu 5 release 0x01000000 - - -;" \ 806 "cpu 5 release 0x01000000 - - -;" \
805 "cpu 6 release 0x01000000 - - -;" \ 807 "cpu 6 release 0x01000000 - - -;" \
806 "cpu 7 release 0x01000000 - - -;" \ 808 "cpu 7 release 0x01000000 - - -;" \
807 "go 0x01000000" 809 "go 0x01000000"
808 810
809 #define CONFIG_LINUX \ 811 #define CONFIG_LINUX \
810 "setenv bootargs root=/dev/ram rw " \ 812 "setenv bootargs root=/dev/ram rw " \
811 "console=$consoledev,$baudrate $othbootargs;" \ 813 "console=$consoledev,$baudrate $othbootargs;" \
812 "setenv ramdiskaddr 0x02000000;" \ 814 "setenv ramdiskaddr 0x02000000;" \
813 "setenv fdtaddr 0x00c00000;" \ 815 "setenv fdtaddr 0x00c00000;" \
814 "setenv loadaddr 0x1000000;" \ 816 "setenv loadaddr 0x1000000;" \
815 "bootm $loadaddr $ramdiskaddr $fdtaddr" 817 "bootm $loadaddr $ramdiskaddr $fdtaddr"
816 818
817 #define CONFIG_HDBOOT \ 819 #define CONFIG_HDBOOT \
818 "setenv bootargs root=/dev/$bdev rw " \ 820 "setenv bootargs root=/dev/$bdev rw " \
819 "console=$consoledev,$baudrate $othbootargs;" \ 821 "console=$consoledev,$baudrate $othbootargs;" \
820 "tftp $loadaddr $bootfile;" \ 822 "tftp $loadaddr $bootfile;" \
821 "tftp $fdtaddr $fdtfile;" \ 823 "tftp $fdtaddr $fdtfile;" \
822 "bootm $loadaddr - $fdtaddr" 824 "bootm $loadaddr - $fdtaddr"
823 825
824 #define CONFIG_NFSBOOTCOMMAND \ 826 #define CONFIG_NFSBOOTCOMMAND \
825 "setenv bootargs root=/dev/nfs rw " \ 827 "setenv bootargs root=/dev/nfs rw " \
826 "nfsroot=$serverip:$rootpath " \ 828 "nfsroot=$serverip:$rootpath " \
827 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 829 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
828 "console=$consoledev,$baudrate $othbootargs;" \ 830 "console=$consoledev,$baudrate $othbootargs;" \
829 "tftp $loadaddr $bootfile;" \ 831 "tftp $loadaddr $bootfile;" \
830 "tftp $fdtaddr $fdtfile;" \ 832 "tftp $fdtaddr $fdtfile;" \
831 "bootm $loadaddr - $fdtaddr" 833 "bootm $loadaddr - $fdtaddr"
832 834
833 #define CONFIG_RAMBOOTCOMMAND \ 835 #define CONFIG_RAMBOOTCOMMAND \
834 "setenv bootargs root=/dev/ram rw " \ 836 "setenv bootargs root=/dev/ram rw " \
835 "console=$consoledev,$baudrate $othbootargs;" \ 837 "console=$consoledev,$baudrate $othbootargs;" \
836 "tftp $ramdiskaddr $ramdiskfile;" \ 838 "tftp $ramdiskaddr $ramdiskfile;" \
837 "tftp $loadaddr $bootfile;" \ 839 "tftp $loadaddr $bootfile;" \
838 "tftp $fdtaddr $fdtfile;" \ 840 "tftp $fdtaddr $fdtfile;" \
839 "bootm $loadaddr $ramdiskaddr $fdtaddr" 841 "bootm $loadaddr $ramdiskaddr $fdtaddr"
840 842
841 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 843 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
842 844
843 #include <asm/fsl_secure_boot.h> 845 #include <asm/fsl_secure_boot.h>
844 846
845 #endif /* __CONFIG_H */ 847 #endif /* __CONFIG_H */
846 848
include/configs/BSC9131RDB.h
1 /* 1 /*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 /* 7 /*
8 * BSC9131 RDB board configuration file 8 * BSC9131 RDB board configuration file
9 */ 9 */
10 10
11 #ifndef __CONFIG_H 11 #ifndef __CONFIG_H
12 #define __CONFIG_H 12 #define __CONFIG_H
13 13
14 #ifdef CONFIG_BSC9131RDB 14 #ifdef CONFIG_BSC9131RDB
15 #define CONFIG_BSC9131 15 #define CONFIG_BSC9131
16 #define CONFIG_NAND_FSL_IFC 16 #define CONFIG_NAND_FSL_IFC
17 #endif 17 #endif
18 18
19 #ifdef CONFIG_SPIFLASH 19 #ifdef CONFIG_SPIFLASH
20 #define CONFIG_RAMBOOT_SPIFLASH 20 #define CONFIG_RAMBOOT_SPIFLASH
21 #define CONFIG_SYS_RAMBOOT 21 #define CONFIG_SYS_RAMBOOT
22 #define CONFIG_SYS_EXTRA_ENV_RELOC 22 #define CONFIG_SYS_EXTRA_ENV_RELOC
23 #define CONFIG_SYS_TEXT_BASE 0x11000000 23 #define CONFIG_SYS_TEXT_BASE 0x11000000
24 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 24 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
25 #endif 25 #endif
26 26
27 #ifdef CONFIG_NAND 27 #ifdef CONFIG_NAND
28 #define CONFIG_SPL 28 #define CONFIG_SPL
29 #define CONFIG_SPL_INIT_MINIMAL 29 #define CONFIG_SPL_INIT_MINIMAL
30 #define CONFIG_SPL_SERIAL_SUPPORT 30 #define CONFIG_SPL_SERIAL_SUPPORT
31 #define CONFIG_SPL_NAND_SUPPORT 31 #define CONFIG_SPL_NAND_SUPPORT
32 #define CONFIG_SPL_NAND_MINIMAL 32 #define CONFIG_SPL_NAND_BOOT
33 #define CONFIG_SPL_FLUSH_IMAGE 33 #define CONFIG_SPL_FLUSH_IMAGE
34 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 34 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
35 35
36 #define CONFIG_SYS_TEXT_BASE 0x00201000 36 #define CONFIG_SYS_TEXT_BASE 0x00201000
37 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 37 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
38 #define CONFIG_SPL_MAX_SIZE 8192 38 #define CONFIG_SPL_MAX_SIZE 8192
39 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 39 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
40 #define CONFIG_SPL_RELOC_STACK 0x00100000 40 #define CONFIG_SPL_RELOC_STACK 0x00100000
41 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 41 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
42 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 42 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
43 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 43 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
44 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 44 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
45 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 45 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
46 #endif 46 #endif
47 47
48 #ifdef CONFIG_SPL_BUILD 48 #ifdef CONFIG_SPL_BUILD
49 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 49 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
50 #else 50 #else
51 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 51 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
52 #endif 52 #endif
53 53
54 54
55 /* High Level Configuration Options */ 55 /* High Level Configuration Options */
56 #define CONFIG_BOOKE /* BOOKE */ 56 #define CONFIG_BOOKE /* BOOKE */
57 #define CONFIG_E500 /* BOOKE e500 family */ 57 #define CONFIG_E500 /* BOOKE e500 family */
58 #define CONFIG_MPC85xx /* MPC8540/60/55/41/48/P1020/P2020/P1010,etc*/ 58 #define CONFIG_MPC85xx /* MPC8540/60/55/41/48/P1020/P2020/P1010,etc*/
59 #define CONFIG_FSL_IFC /* Enable IFC Support */ 59 #define CONFIG_FSL_IFC /* Enable IFC Support */
60 60
61 #define CONFIG_FSL_LAW /* Use common FSL init code */ 61 #define CONFIG_FSL_LAW /* Use common FSL init code */
62 #define CONFIG_TSEC_ENET 62 #define CONFIG_TSEC_ENET
63 #define CONFIG_ENV_OVERWRITE 63 #define CONFIG_ENV_OVERWRITE
64 64
65 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */ 65 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
66 #if defined(CONFIG_SYS_CLK_100) 66 #if defined(CONFIG_SYS_CLK_100)
67 #define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */ 67 #define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */
68 #else 68 #else
69 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */ 69 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */
70 #endif 70 #endif
71 71
72 #define CONFIG_HWCONFIG 72 #define CONFIG_HWCONFIG
73 /* 73 /*
74 * These can be toggled for performance analysis, otherwise use default. 74 * These can be toggled for performance analysis, otherwise use default.
75 */ 75 */
76 #define CONFIG_L2_CACHE /* toggle L2 cache */ 76 #define CONFIG_L2_CACHE /* toggle L2 cache */
77 #define CONFIG_BTB /* enable branch predition */ 77 #define CONFIG_BTB /* enable branch predition */
78 78
79 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 79 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
80 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 80 #define CONFIG_SYS_MEMTEST_END 0x01ffffff
81 81
82 /* DDR Setup */ 82 /* DDR Setup */
83 #define CONFIG_SYS_FSL_DDR3 83 #define CONFIG_SYS_FSL_DDR3
84 #undef CONFIG_SYS_DDR_RAW_TIMING 84 #undef CONFIG_SYS_DDR_RAW_TIMING
85 #undef CONFIG_DDR_SPD 85 #undef CONFIG_DDR_SPD
86 #define CONFIG_SYS_SPD_BUS_NUM 0 86 #define CONFIG_SYS_SPD_BUS_NUM 0
87 #define SPD_EEPROM_ADDRESS 0x52 /* I2C access */ 87 #define SPD_EEPROM_ADDRESS 0x52 /* I2C access */
88 88
89 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 89 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
90 90
91 #ifndef __ASSEMBLY__ 91 #ifndef __ASSEMBLY__
92 extern unsigned long get_sdram_size(void); 92 extern unsigned long get_sdram_size(void);
93 #endif 93 #endif
94 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 94 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
95 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 95 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
96 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 96 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
97 97
98 #define CONFIG_NUM_DDR_CONTROLLERS 1 98 #define CONFIG_NUM_DDR_CONTROLLERS 1
99 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 99 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
100 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 100 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
101 101
102 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 102 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
103 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 103 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
104 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 104 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
105 105
106 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 106 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
107 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 107 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
108 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 108 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
109 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 109 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
110 110
111 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 111 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
112 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 112 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
113 #define CONFIG_SYS_DDR_RCW_1 0x00000000 113 #define CONFIG_SYS_DDR_RCW_1 0x00000000
114 #define CONFIG_SYS_DDR_RCW_2 0x00000000 114 #define CONFIG_SYS_DDR_RCW_2 0x00000000
115 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 115 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
116 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 116 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
117 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 117 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
118 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 118 #define CONFIG_SYS_DDR_TIMING_5 0x02401400
119 119
120 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 120 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
121 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 121 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
122 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 122 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
123 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf 123 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf
124 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 124 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
125 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 125 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
126 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 126 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
127 #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 127 #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
128 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 128 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
129 129
130 /* 130 /*
131 * Base addresses -- Note these are effective addresses where the 131 * Base addresses -- Note these are effective addresses where the
132 * actual resources get mapped (not physical addresses) 132 * actual resources get mapped (not physical addresses)
133 */ 133 */
134 /* relocated CCSRBAR */ 134 /* relocated CCSRBAR */
135 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 135 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
136 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 136 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
137 137
138 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ 138 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
139 /* CONFIG_SYS_IMMR */ 139 /* CONFIG_SYS_IMMR */
140 /* DSP CCSRBAR */ 140 /* DSP CCSRBAR */
141 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 141 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
142 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 142 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
143 143
144 /* 144 /*
145 * Memory map 145 * Memory map
146 * 146 *
147 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable 147 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
148 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M 148 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
149 * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M 149 * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
150 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M 150 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
151 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K 151 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
152 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K 152 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
153 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K 153 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
154 * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M 154 * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
155 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M 155 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
156 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M 156 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
157 * 157 *
158 */ 158 */
159 159
160 /* 160 /*
161 * IFC Definitions 161 * IFC Definitions
162 */ 162 */
163 #define CONFIG_SYS_NO_FLASH 163 #define CONFIG_SYS_NO_FLASH
164 164
165 /* NAND Flash on IFC */ 165 /* NAND Flash on IFC */
166 #define CONFIG_SYS_NAND_BASE 0xff800000 166 #define CONFIG_SYS_NAND_BASE 0xff800000
167 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 167 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
168 168
169 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 169 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
170 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \ 170 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \
171 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 171 | CSPR_MSEL_NAND /* MSEL = NAND */ \
172 | CSPR_V) 172 | CSPR_V)
173 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 173 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
174 174
175 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 175 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
176 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 176 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
177 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 177 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
178 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 178 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
179 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 179 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
180 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 180 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
181 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 181 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
182 182
183 /* NAND Flash Timing Params */ 183 /* NAND Flash Timing Params */
184 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 184 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
185 | FTIM0_NAND_TWP(0x05) \ 185 | FTIM0_NAND_TWP(0x05) \
186 | FTIM0_NAND_TWCHT(0x02) \ 186 | FTIM0_NAND_TWCHT(0x02) \
187 | FTIM0_NAND_TWH(0x04)) 187 | FTIM0_NAND_TWH(0x04))
188 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \ 188 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \
189 | FTIM1_NAND_TWBE(0x1E) \ 189 | FTIM1_NAND_TWBE(0x1E) \
190 | FTIM1_NAND_TRR(0x07) \ 190 | FTIM1_NAND_TRR(0x07) \
191 | FTIM1_NAND_TRP(0x05)) 191 | FTIM1_NAND_TRP(0x05))
192 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 192 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
193 | FTIM2_NAND_TREH(0x04) \ 193 | FTIM2_NAND_TREH(0x04) \
194 | FTIM2_NAND_TWHRE(0x11)) 194 | FTIM2_NAND_TWHRE(0x11))
195 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 195 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
196 196
197 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 197 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
198 #define CONFIG_SYS_MAX_NAND_DEVICE 1 198 #define CONFIG_SYS_MAX_NAND_DEVICE 1
199 #define CONFIG_MTD_NAND_VERIFY_WRITE 199 #define CONFIG_MTD_NAND_VERIFY_WRITE
200 #define CONFIG_CMD_NAND 200 #define CONFIG_CMD_NAND
201 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 201 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
202 202
203 #define CONFIG_SYS_NAND_DDR_LAW 11 203 #define CONFIG_SYS_NAND_DDR_LAW 11
204 204
205 /* Set up IFC registers for boot location NAND */ 205 /* Set up IFC registers for boot location NAND */
206 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 206 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
207 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 207 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
208 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 208 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
209 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 209 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
210 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 210 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
211 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 211 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
212 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 212 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
213 213
214 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 214 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
215 215
216 #define CONFIG_SYS_INIT_RAM_LOCK 216 #define CONFIG_SYS_INIT_RAM_LOCK
217 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 217 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
218 #define CONFIG_SYS_INIT_RAM_END 0x00004000/* End of used area in RAM */ 218 #define CONFIG_SYS_INIT_RAM_END 0x00004000/* End of used area in RAM */
219 219
220 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 220 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
221 - GENERATED_GBL_DATA_SIZE) 221 - GENERATED_GBL_DATA_SIZE)
222 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 222 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
223 223
224 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ 224 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
225 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 225 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
226 226
227 /* Serial Port */ 227 /* Serial Port */
228 #define CONFIG_CONS_INDEX 1 228 #define CONFIG_CONS_INDEX 1
229 #undef CONFIG_SERIAL_SOFTWARE_FIFO 229 #undef CONFIG_SERIAL_SOFTWARE_FIFO
230 #define CONFIG_SYS_NS16550 230 #define CONFIG_SYS_NS16550
231 #define CONFIG_SYS_NS16550_SERIAL 231 #define CONFIG_SYS_NS16550_SERIAL
232 #define CONFIG_SYS_NS16550_REG_SIZE 1 232 #define CONFIG_SYS_NS16550_REG_SIZE 1
233 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 233 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
234 #ifdef CONFIG_SPL_BUILD 234 #ifdef CONFIG_SPL_BUILD
235 #define CONFIG_NS16550_MIN_FUNCTIONS 235 #define CONFIG_NS16550_MIN_FUNCTIONS
236 #endif 236 #endif
237 237
238 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 238 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
239 239
240 #define CONFIG_SYS_BAUDRATE_TABLE \ 240 #define CONFIG_SYS_BAUDRATE_TABLE \
241 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 241 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
242 242
243 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 243 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
244 244
245 /* Use the HUSH parser */ 245 /* Use the HUSH parser */
246 #define CONFIG_SYS_HUSH_PARSER 246 #define CONFIG_SYS_HUSH_PARSER
247 #ifdef CONFIG_SYS_HUSH_PARSER 247 #ifdef CONFIG_SYS_HUSH_PARSER
248 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 248 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
249 #endif 249 #endif
250 250
251 /* 251 /*
252 * Pass open firmware flat tree 252 * Pass open firmware flat tree
253 */ 253 */
254 #define CONFIG_OF_LIBFDT 254 #define CONFIG_OF_LIBFDT
255 #define CONFIG_OF_BOARD_SETUP 255 #define CONFIG_OF_BOARD_SETUP
256 #define CONFIG_OF_STDOUT_VIA_ALIAS 256 #define CONFIG_OF_STDOUT_VIA_ALIAS
257 257
258 /* new uImage format support */ 258 /* new uImage format support */
259 #define CONFIG_FIT 259 #define CONFIG_FIT
260 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 260 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
261 261
262 #define CONFIG_SYS_I2C 262 #define CONFIG_SYS_I2C
263 #define CONFIG_SYS_I2C_FSL 263 #define CONFIG_SYS_I2C_FSL
264 #define CONFIG_SYS_FSL_I2C_SPEED 400000 264 #define CONFIG_SYS_FSL_I2C_SPEED 400000
265 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 265 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
266 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 266 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
267 267
268 /* I2C EEPROM */ 268 /* I2C EEPROM */
269 #define CONFIG_CMD_EEPROM 269 #define CONFIG_CMD_EEPROM
270 #define CONFIG_SYS_I2C_MULTI_EEPROMS 270 #define CONFIG_SYS_I2C_MULTI_EEPROMS
271 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 271 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
272 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 272 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
273 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 273 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
274 274
275 #define CONFIG_CMD_I2C 275 #define CONFIG_CMD_I2C
276 276
277 277
278 #define CONFIG_FSL_ESPI 278 #define CONFIG_FSL_ESPI
279 /* eSPI - Enhanced SPI */ 279 /* eSPI - Enhanced SPI */
280 #ifdef CONFIG_FSL_ESPI 280 #ifdef CONFIG_FSL_ESPI
281 #define CONFIG_SPI_FLASH 281 #define CONFIG_SPI_FLASH
282 #define CONFIG_SPI_FLASH_SPANSION 282 #define CONFIG_SPI_FLASH_SPANSION
283 #define CONFIG_CMD_SF 283 #define CONFIG_CMD_SF
284 #define CONFIG_SF_DEFAULT_SPEED 10000000 284 #define CONFIG_SF_DEFAULT_SPEED 10000000
285 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 285 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
286 #endif 286 #endif
287 287
288 #if defined(CONFIG_TSEC_ENET) 288 #if defined(CONFIG_TSEC_ENET)
289 289
290 #define CONFIG_MII /* MII PHY management */ 290 #define CONFIG_MII /* MII PHY management */
291 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 291 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
292 #define CONFIG_TSEC1 1 292 #define CONFIG_TSEC1 1
293 #define CONFIG_TSEC1_NAME "eTSEC1" 293 #define CONFIG_TSEC1_NAME "eTSEC1"
294 #define CONFIG_TSEC2 1 294 #define CONFIG_TSEC2 1
295 #define CONFIG_TSEC2_NAME "eTSEC2" 295 #define CONFIG_TSEC2_NAME "eTSEC2"
296 296
297 #define TSEC1_PHY_ADDR 0 297 #define TSEC1_PHY_ADDR 0
298 #define TSEC2_PHY_ADDR 3 298 #define TSEC2_PHY_ADDR 3
299 299
300 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 300 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
301 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 301 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
302 302
303 #define TSEC1_PHYIDX 0 303 #define TSEC1_PHYIDX 0
304 304
305 #define TSEC2_PHYIDX 0 305 #define TSEC2_PHYIDX 0
306 306
307 #define CONFIG_ETHPRIME "eTSEC1" 307 #define CONFIG_ETHPRIME "eTSEC1"
308 308
309 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 309 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
310 310
311 #endif /* CONFIG_TSEC_ENET */ 311 #endif /* CONFIG_TSEC_ENET */
312 312
313 /* 313 /*
314 * Environment 314 * Environment
315 */ 315 */
316 #if defined(CONFIG_RAMBOOT_SPIFLASH) 316 #if defined(CONFIG_RAMBOOT_SPIFLASH)
317 #define CONFIG_ENV_IS_IN_SPI_FLASH 317 #define CONFIG_ENV_IS_IN_SPI_FLASH
318 #define CONFIG_ENV_SPI_BUS 0 318 #define CONFIG_ENV_SPI_BUS 0
319 #define CONFIG_ENV_SPI_CS 0 319 #define CONFIG_ENV_SPI_CS 0
320 #define CONFIG_ENV_SPI_MAX_HZ 10000000 320 #define CONFIG_ENV_SPI_MAX_HZ 10000000
321 #define CONFIG_ENV_SPI_MODE 0 321 #define CONFIG_ENV_SPI_MODE 0
322 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 322 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
323 #define CONFIG_ENV_SECT_SIZE 0x10000 323 #define CONFIG_ENV_SECT_SIZE 0x10000
324 #define CONFIG_ENV_SIZE 0x2000 324 #define CONFIG_ENV_SIZE 0x2000
325 #elif defined(CONFIG_NAND) 325 #elif defined(CONFIG_NAND)
326 #define CONFIG_ENV_IS_IN_NAND 326 #define CONFIG_ENV_IS_IN_NAND
327 #define CONFIG_SYS_EXTRA_ENV_RELOC 327 #define CONFIG_SYS_EXTRA_ENV_RELOC
328 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 328 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
329 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 329 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
330 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 330 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
331 #elif defined(CONFIG_SYS_RAMBOOT) 331 #elif defined(CONFIG_SYS_RAMBOOT)
332 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 332 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
333 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 333 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
334 #define CONFIG_ENV_SIZE 0x2000 334 #define CONFIG_ENV_SIZE 0x2000
335 #endif 335 #endif
336 336
337 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 337 #define CONFIG_LOADS_ECHO /* echo on for serial download */
338 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 338 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
339 339
340 /* 340 /*
341 * Command line configuration. 341 * Command line configuration.
342 */ 342 */
343 #include <config_cmd_default.h> 343 #include <config_cmd_default.h>
344 344
345 #define CONFIG_CMD_DHCP 345 #define CONFIG_CMD_DHCP
346 #define CONFIG_CMD_ERRATA 346 #define CONFIG_CMD_ERRATA
347 #define CONFIG_CMD_ELF 347 #define CONFIG_CMD_ELF
348 #define CONFIG_CMD_EXT2 348 #define CONFIG_CMD_EXT2
349 #define CONFIG_CMD_FAT 349 #define CONFIG_CMD_FAT
350 #define CONFIG_CMD_IRQ 350 #define CONFIG_CMD_IRQ
351 #define CONFIG_CMD_MII 351 #define CONFIG_CMD_MII
352 #define CONFIG_DOS_PARTITION 352 #define CONFIG_DOS_PARTITION
353 #define CONFIG_CMD_PING 353 #define CONFIG_CMD_PING
354 #define CONFIG_CMD_REGINFO 354 #define CONFIG_CMD_REGINFO
355 #define CONFIG_CMD_SETEXPR 355 #define CONFIG_CMD_SETEXPR
356 356
357 /* 357 /*
358 * Miscellaneous configurable options 358 * Miscellaneous configurable options
359 */ 359 */
360 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 360 #define CONFIG_SYS_LONGHELP /* undef to save memory */
361 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 361 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
362 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 362 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
363 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 363 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
364 364
365 #if defined(CONFIG_CMD_KGDB) 365 #if defined(CONFIG_CMD_KGDB)
366 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 366 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
367 #else 367 #else
368 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 368 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
369 #endif 369 #endif
370 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 370 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
371 /* Print Buffer Size */ 371 /* Print Buffer Size */
372 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 372 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
373 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 373 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
374 374
375 /* 375 /*
376 * For booting Linux, the board info and command line data 376 * For booting Linux, the board info and command line data
377 * have to be in the first 64 MB of memory, since this is 377 * have to be in the first 64 MB of memory, since this is
378 * the maximum mapped by the Linux kernel during initialization. 378 * the maximum mapped by the Linux kernel during initialization.
379 */ 379 */
380 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 380 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
381 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 381 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
382 382
383 #if defined(CONFIG_CMD_KGDB) 383 #if defined(CONFIG_CMD_KGDB)
384 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 384 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
385 #endif 385 #endif
386 386
387 #define CONFIG_USB_EHCI 387 #define CONFIG_USB_EHCI
388 388
389 #ifdef CONFIG_USB_EHCI 389 #ifdef CONFIG_USB_EHCI
390 #define CONFIG_CMD_USB 390 #define CONFIG_CMD_USB
391 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 391 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
392 #define CONFIG_USB_EHCI_FSL 392 #define CONFIG_USB_EHCI_FSL
393 #define CONFIG_USB_STORAGE 393 #define CONFIG_USB_STORAGE
394 #define CONFIG_HAS_FSL_DR_USB 394 #define CONFIG_HAS_FSL_DR_USB
395 #endif 395 #endif
396 396
397 /* 397 /*
398 * Environment Configuration 398 * Environment Configuration
399 */ 399 */
400 400
401 #if defined(CONFIG_TSEC_ENET) 401 #if defined(CONFIG_TSEC_ENET)
402 #define CONFIG_HAS_ETH0 402 #define CONFIG_HAS_ETH0
403 #endif 403 #endif
404 404
405 #define CONFIG_HOSTNAME BSC9131rdb 405 #define CONFIG_HOSTNAME BSC9131rdb
406 #define CONFIG_ROOTPATH "/opt/nfsroot" 406 #define CONFIG_ROOTPATH "/opt/nfsroot"
407 #define CONFIG_BOOTFILE "uImage" 407 #define CONFIG_BOOTFILE "uImage"
408 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 408 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
409 409
410 #define CONFIG_BAUDRATE 115200 410 #define CONFIG_BAUDRATE 115200
411 411
412 #define CONFIG_EXTRA_ENV_SETTINGS \ 412 #define CONFIG_EXTRA_ENV_SETTINGS \
413 "netdev=eth0\0" \ 413 "netdev=eth0\0" \
414 "uboot=" CONFIG_UBOOTPATH "\0" \ 414 "uboot=" CONFIG_UBOOTPATH "\0" \
415 "loadaddr=1000000\0" \ 415 "loadaddr=1000000\0" \
416 "bootfile=uImage\0" \ 416 "bootfile=uImage\0" \
417 "consoledev=ttyS0\0" \ 417 "consoledev=ttyS0\0" \
418 "ramdiskaddr=2000000\0" \ 418 "ramdiskaddr=2000000\0" \
419 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 419 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
420 "fdtaddr=c00000\0" \ 420 "fdtaddr=c00000\0" \
421 "fdtfile=bsc9131rdb.dtb\0" \ 421 "fdtfile=bsc9131rdb.dtb\0" \
422 "bdev=sda1\0" \ 422 "bdev=sda1\0" \
423 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 423 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
424 "bootm_size=0x37000000\0" \ 424 "bootm_size=0x37000000\0" \
425 "othbootargs=ramdisk_size=600000 " \ 425 "othbootargs=ramdisk_size=600000 " \
426 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \ 426 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
427 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 427 "usbext2boot=setenv bootargs root=/dev/ram rw " \
428 "console=$consoledev,$baudrate $othbootargs; " \ 428 "console=$consoledev,$baudrate $othbootargs; " \
429 "usb start;" \ 429 "usb start;" \
430 "ext2load usb 0:4 $loadaddr $bootfile;" \ 430 "ext2load usb 0:4 $loadaddr $bootfile;" \
431 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 431 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
432 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 432 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
433 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 433 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
434 434
435 #define CONFIG_RAMBOOTCOMMAND \ 435 #define CONFIG_RAMBOOTCOMMAND \
436 "setenv bootargs root=/dev/ram rw " \ 436 "setenv bootargs root=/dev/ram rw " \
437 "console=$consoledev,$baudrate $othbootargs; " \ 437 "console=$consoledev,$baudrate $othbootargs; " \
438 "tftp $ramdiskaddr $ramdiskfile;" \ 438 "tftp $ramdiskaddr $ramdiskfile;" \
439 "tftp $loadaddr $bootfile;" \ 439 "tftp $loadaddr $bootfile;" \
440 "tftp $fdtaddr $fdtfile;" \ 440 "tftp $fdtaddr $fdtfile;" \
441 "bootm $loadaddr $ramdiskaddr $fdtaddr" 441 "bootm $loadaddr $ramdiskaddr $fdtaddr"
442 442
443 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 443 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
444 444
445 #endif /* __CONFIG_H */ 445 #endif /* __CONFIG_H */
446 446
include/configs/BSC9132QDS.h
1 /* 1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc. 2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 /* 7 /*
8 * BSC9132 QDS board configuration file 8 * BSC9132 QDS board configuration file
9 */ 9 */
10 10
11 #ifndef __CONFIG_H 11 #ifndef __CONFIG_H
12 #define __CONFIG_H 12 #define __CONFIG_H
13 13
14 #ifdef CONFIG_BSC9132QDS 14 #ifdef CONFIG_BSC9132QDS
15 #define CONFIG_BSC9132 15 #define CONFIG_BSC9132
16 #endif 16 #endif
17 17
18 #define CONFIG_MISC_INIT_R 18 #define CONFIG_MISC_INIT_R
19 19
20 #ifdef CONFIG_SDCARD 20 #ifdef CONFIG_SDCARD
21 #define CONFIG_RAMBOOT_SDCARD 21 #define CONFIG_RAMBOOT_SDCARD
22 #define CONFIG_SYS_RAMBOOT 22 #define CONFIG_SYS_RAMBOOT
23 #define CONFIG_SYS_EXTRA_ENV_RELOC 23 #define CONFIG_SYS_EXTRA_ENV_RELOC
24 #define CONFIG_SYS_TEXT_BASE 0x11000000 24 #define CONFIG_SYS_TEXT_BASE 0x11000000
25 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 25 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
26 #endif 26 #endif
27 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1 27 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1
28 #ifdef CONFIG_SPIFLASH 28 #ifdef CONFIG_SPIFLASH
29 #define CONFIG_RAMBOOT_SPIFLASH 29 #define CONFIG_RAMBOOT_SPIFLASH
30 #define CONFIG_SYS_RAMBOOT 30 #define CONFIG_SYS_RAMBOOT
31 #define CONFIG_SYS_EXTRA_ENV_RELOC 31 #define CONFIG_SYS_EXTRA_ENV_RELOC
32 #define CONFIG_SYS_TEXT_BASE 0x11000000 32 #define CONFIG_SYS_TEXT_BASE 0x11000000
33 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 33 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
34 #endif 34 #endif
35 35
36 #ifdef CONFIG_NAND 36 #ifdef CONFIG_NAND
37 #define CONFIG_SPL 37 #define CONFIG_SPL
38 #define CONFIG_SPL_INIT_MINIMAL 38 #define CONFIG_SPL_INIT_MINIMAL
39 #define CONFIG_SPL_SERIAL_SUPPORT 39 #define CONFIG_SPL_SERIAL_SUPPORT
40 #define CONFIG_SPL_NAND_SUPPORT 40 #define CONFIG_SPL_NAND_SUPPORT
41 #define CONFIG_SPL_NAND_MINIMAL 41 #define CONFIG_SPL_NAND_BOOT
42 #define CONFIG_SPL_FLUSH_IMAGE 42 #define CONFIG_SPL_FLUSH_IMAGE
43 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 43 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
44 44
45 #define CONFIG_SYS_TEXT_BASE 0x00201000 45 #define CONFIG_SYS_TEXT_BASE 0x00201000
46 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 46 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
47 #define CONFIG_SPL_MAX_SIZE 8192 47 #define CONFIG_SPL_MAX_SIZE 8192
48 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 48 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
49 #define CONFIG_SPL_RELOC_STACK 0x00100000 49 #define CONFIG_SPL_RELOC_STACK 0x00100000
50 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 50 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
51 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 51 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
52 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 52 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
53 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 53 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
54 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 54 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
55 #endif 55 #endif
56 56
57 #ifndef CONFIG_SYS_TEXT_BASE 57 #ifndef CONFIG_SYS_TEXT_BASE
58 #define CONFIG_SYS_TEXT_BASE 0x8ff80000 58 #define CONFIG_SYS_TEXT_BASE 0x8ff80000
59 #endif 59 #endif
60 60
61 #ifndef CONFIG_RESET_VECTOR_ADDRESS 61 #ifndef CONFIG_RESET_VECTOR_ADDRESS
62 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc 62 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc
63 #endif 63 #endif
64 64
65 #ifdef CONFIG_SPL_BUILD 65 #ifdef CONFIG_SPL_BUILD
66 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 66 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
67 #else 67 #else
68 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 68 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
69 #endif 69 #endif
70 70
71 /* High Level Configuration Options */ 71 /* High Level Configuration Options */
72 #define CONFIG_BOOKE /* BOOKE */ 72 #define CONFIG_BOOKE /* BOOKE */
73 #define CONFIG_E500 /* BOOKE e500 family */ 73 #define CONFIG_E500 /* BOOKE e500 family */
74 #define CONFIG_MPC85xx 74 #define CONFIG_MPC85xx
75 #define CONFIG_FSL_IFC /* Enable IFC Support */ 75 #define CONFIG_FSL_IFC /* Enable IFC Support */
76 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 76 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
77 77
78 #define CONFIG_PCI /* Enable PCI/PCIE */ 78 #define CONFIG_PCI /* Enable PCI/PCIE */
79 #if defined(CONFIG_PCI) 79 #if defined(CONFIG_PCI)
80 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 80 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
81 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 81 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
82 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 82 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
83 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 83 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
84 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 84 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
85 85
86 #define CONFIG_CMD_NET 86 #define CONFIG_CMD_NET
87 #define CONFIG_CMD_PCI 87 #define CONFIG_CMD_PCI
88 88
89 #define CONFIG_E1000 /* E1000 pci Ethernet card*/ 89 #define CONFIG_E1000 /* E1000 pci Ethernet card*/
90 90
91 /* 91 /*
92 * PCI Windows 92 * PCI Windows
93 * Memory space is mapped 1-1, but I/O space must start from 0. 93 * Memory space is mapped 1-1, but I/O space must start from 0.
94 */ 94 */
95 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 95 /* controller 1, Slot 1, tgtid 1, Base address a000 */
96 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" 96 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot"
97 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 97 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
98 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 98 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
99 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 99 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
100 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 100 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
101 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 101 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000
102 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 102 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
103 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 103 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
104 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 104 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000
105 105
106 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 106 #define CONFIG_PCI_PNP /* do pci plug-and-play */
107 107
108 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 108 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
109 #define CONFIG_DOS_PARTITION 109 #define CONFIG_DOS_PARTITION
110 #endif 110 #endif
111 111
112 #define CONFIG_FSL_LAW /* Use common FSL init code */ 112 #define CONFIG_FSL_LAW /* Use common FSL init code */
113 #define CONFIG_ENV_OVERWRITE 113 #define CONFIG_ENV_OVERWRITE
114 #define CONFIG_TSEC_ENET /* ethernet */ 114 #define CONFIG_TSEC_ENET /* ethernet */
115 115
116 #if defined(CONFIG_SYS_CLK_100_DDR_100) 116 #if defined(CONFIG_SYS_CLK_100_DDR_100)
117 #define CONFIG_SYS_CLK_FREQ 100000000 117 #define CONFIG_SYS_CLK_FREQ 100000000
118 #define CONFIG_DDR_CLK_FREQ 100000000 118 #define CONFIG_DDR_CLK_FREQ 100000000
119 #elif defined(CONFIG_SYS_CLK_100_DDR_133) 119 #elif defined(CONFIG_SYS_CLK_100_DDR_133)
120 #define CONFIG_SYS_CLK_FREQ 100000000 120 #define CONFIG_SYS_CLK_FREQ 100000000
121 #define CONFIG_DDR_CLK_FREQ 133000000 121 #define CONFIG_DDR_CLK_FREQ 133000000
122 #endif 122 #endif
123 123
124 #define CONFIG_MP 124 #define CONFIG_MP
125 125
126 #define CONFIG_HWCONFIG 126 #define CONFIG_HWCONFIG
127 /* 127 /*
128 * These can be toggled for performance analysis, otherwise use default. 128 * These can be toggled for performance analysis, otherwise use default.
129 */ 129 */
130 #define CONFIG_L2_CACHE /* toggle L2 cache */ 130 #define CONFIG_L2_CACHE /* toggle L2 cache */
131 #define CONFIG_BTB /* enable branch predition */ 131 #define CONFIG_BTB /* enable branch predition */
132 132
133 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 133 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
134 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 134 #define CONFIG_SYS_MEMTEST_END 0x01ffffff
135 135
136 /* DDR Setup */ 136 /* DDR Setup */
137 #define CONFIG_SYS_FSL_DDR3 137 #define CONFIG_SYS_FSL_DDR3
138 #define CONFIG_SYS_SPD_BUS_NUM 0 138 #define CONFIG_SYS_SPD_BUS_NUM 0
139 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ 139 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
140 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ 140 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
141 #define CONFIG_FSL_DDR_INTERACTIVE 141 #define CONFIG_FSL_DDR_INTERACTIVE
142 142
143 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 143 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
144 144
145 #define CONFIG_SYS_SDRAM_SIZE (1024) 145 #define CONFIG_SYS_SDRAM_SIZE (1024)
146 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 146 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
147 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 147 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
148 148
149 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 149 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
150 150
151 /* DDR3 Controller Settings */ 151 /* DDR3 Controller Settings */
152 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 152 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
153 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 153 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
154 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 154 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302
155 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 155 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302
156 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 156 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
157 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 157 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
158 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 158 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
159 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 159 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
160 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 160 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
161 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F 161 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F
162 162
163 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 163 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
164 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 164 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
165 #define CONFIG_SYS_DDR_RCW_1 0x00000000 165 #define CONFIG_SYS_DDR_RCW_1 0x00000000
166 #define CONFIG_SYS_DDR_RCW_2 0x00000000 166 #define CONFIG_SYS_DDR_RCW_2 0x00000000
167 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 167 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000
168 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 168 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050
169 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 169 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001
170 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 170 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400
171 171
172 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 172 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008
173 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 173 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010
174 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 174 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001
175 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 175 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400
176 176
177 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 177 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
178 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 178 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
179 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 179 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846
180 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF 180 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF
181 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 181 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
182 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 182 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520
183 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 183 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
184 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 184 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000
185 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 185 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
186 186
187 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 187 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000
188 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 188 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104
189 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 189 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45
190 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 190 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114
191 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 191 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000
192 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 192 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50
193 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 193 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000
194 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 194 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513
195 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 195 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607
196 196
197 /*FIXME: the following params are constant w.r.t diff freq 197 /*FIXME: the following params are constant w.r.t diff freq
198 combinations. this should be removed later 198 combinations. this should be removed later
199 */ 199 */
200 #if CONFIG_DDR_CLK_FREQ == 100000000 200 #if CONFIG_DDR_CLK_FREQ == 100000000
201 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 201 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
202 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 202 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
203 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 203 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
204 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 204 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
205 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 205 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
206 #elif CONFIG_DDR_CLK_FREQ == 133000000 206 #elif CONFIG_DDR_CLK_FREQ == 133000000
207 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 207 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
208 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 208 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333
209 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 209 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333
210 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 210 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
211 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 211 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
212 #else 212 #else
213 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 213 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
214 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 214 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
215 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 215 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
216 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 216 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
217 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 217 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
218 #endif 218 #endif
219 219
220 220
221 /* relocated CCSRBAR */ 221 /* relocated CCSRBAR */
222 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 222 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
223 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 223 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
224 224
225 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 225 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
226 226
227 /* DSP CCSRBAR */ 227 /* DSP CCSRBAR */
228 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 228 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
229 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 229 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
230 230
231 /* 231 /*
232 * IFC Definitions 232 * IFC Definitions
233 */ 233 */
234 /* NOR Flash on IFC */ 234 /* NOR Flash on IFC */
235 235
236 #ifdef CONFIG_SPL_BUILD 236 #ifdef CONFIG_SPL_BUILD
237 #define CONFIG_SYS_NO_FLASH 237 #define CONFIG_SYS_NO_FLASH
238 #endif 238 #endif
239 #define CONFIG_SYS_FLASH_BASE 0x88000000 239 #define CONFIG_SYS_FLASH_BASE 0x88000000
240 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ 240 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */
241 241
242 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 242 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
243 243
244 #define CONFIG_SYS_NOR_CSPR 0x88000101 244 #define CONFIG_SYS_NOR_CSPR 0x88000101
245 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 245 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
246 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) 246 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5)
247 /* NOR Flash Timing Params */ 247 /* NOR Flash Timing Params */
248 248
249 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ 249 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \
250 | FTIM0_NOR_TEADC(0x03) \ 250 | FTIM0_NOR_TEADC(0x03) \
251 | FTIM0_NOR_TAVDS(0x00) \ 251 | FTIM0_NOR_TAVDS(0x00) \
252 | FTIM0_NOR_TEAHC(0x0f)) 252 | FTIM0_NOR_TEAHC(0x0f))
253 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ 253 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \
254 | FTIM1_NOR_TRAD_NOR(0x09) \ 254 | FTIM1_NOR_TRAD_NOR(0x09) \
255 | FTIM1_NOR_TSEQRAD_NOR(0x09)) 255 | FTIM1_NOR_TSEQRAD_NOR(0x09))
256 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ 256 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \
257 | FTIM2_NOR_TCH(0x4) \ 257 | FTIM2_NOR_TCH(0x4) \
258 | FTIM2_NOR_TWPH(0x7) \ 258 | FTIM2_NOR_TWPH(0x7) \
259 | FTIM2_NOR_TWP(0x1e)) 259 | FTIM2_NOR_TWP(0x1e))
260 #define CONFIG_SYS_NOR_FTIM3 0x0 260 #define CONFIG_SYS_NOR_FTIM3 0x0
261 261
262 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 262 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
263 #define CONFIG_SYS_FLASH_QUIET_TEST 263 #define CONFIG_SYS_FLASH_QUIET_TEST
264 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 264 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
265 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 265 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
266 266
267 #undef CONFIG_SYS_FLASH_CHECKSUM 267 #undef CONFIG_SYS_FLASH_CHECKSUM
268 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 268 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
269 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 269 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
270 270
271 /* CFI for NOR Flash */ 271 /* CFI for NOR Flash */
272 #define CONFIG_FLASH_CFI_DRIVER 272 #define CONFIG_FLASH_CFI_DRIVER
273 #define CONFIG_SYS_FLASH_CFI 273 #define CONFIG_SYS_FLASH_CFI
274 #define CONFIG_SYS_FLASH_EMPTY_INFO 274 #define CONFIG_SYS_FLASH_EMPTY_INFO
275 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 275 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
276 276
277 /* NAND Flash on IFC */ 277 /* NAND Flash on IFC */
278 #define CONFIG_SYS_NAND_BASE 0xff800000 278 #define CONFIG_SYS_NAND_BASE 0xff800000
279 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 279 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
280 280
281 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 281 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
282 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 282 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
283 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 283 | CSPR_MSEL_NAND /* MSEL = NAND */ \
284 | CSPR_V) 284 | CSPR_V)
285 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 285 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
286 286
287 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 287 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
288 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 288 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
289 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 289 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
290 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 290 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
291 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 291 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
292 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 292 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
293 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 293 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
294 294
295 /* NAND Flash Timing Params */ 295 /* NAND Flash Timing Params */
296 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 296 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
297 | FTIM0_NAND_TWP(0x05) \ 297 | FTIM0_NAND_TWP(0x05) \
298 | FTIM0_NAND_TWCHT(0x02) \ 298 | FTIM0_NAND_TWCHT(0x02) \
299 | FTIM0_NAND_TWH(0x04)) 299 | FTIM0_NAND_TWH(0x04))
300 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ 300 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \
301 | FTIM1_NAND_TWBE(0x1e) \ 301 | FTIM1_NAND_TWBE(0x1e) \
302 | FTIM1_NAND_TRR(0x07) \ 302 | FTIM1_NAND_TRR(0x07) \
303 | FTIM1_NAND_TRP(0x05)) 303 | FTIM1_NAND_TRP(0x05))
304 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 304 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
305 | FTIM2_NAND_TREH(0x04) \ 305 | FTIM2_NAND_TREH(0x04) \
306 | FTIM2_NAND_TWHRE(0x11)) 306 | FTIM2_NAND_TWHRE(0x11))
307 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 307 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
308 308
309 #define CONFIG_SYS_NAND_DDR_LAW 11 309 #define CONFIG_SYS_NAND_DDR_LAW 11
310 310
311 /* NAND */ 311 /* NAND */
312 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 312 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
313 #define CONFIG_SYS_MAX_NAND_DEVICE 1 313 #define CONFIG_SYS_MAX_NAND_DEVICE 1
314 #define CONFIG_MTD_NAND_VERIFY_WRITE 314 #define CONFIG_MTD_NAND_VERIFY_WRITE
315 #define CONFIG_CMD_NAND 315 #define CONFIG_CMD_NAND
316 316
317 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 317 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
318 318
319 #ifndef CONFIG_SPL_BUILD 319 #ifndef CONFIG_SPL_BUILD
320 #define CONFIG_FSL_QIXIS 320 #define CONFIG_FSL_QIXIS
321 #endif 321 #endif
322 #ifdef CONFIG_FSL_QIXIS 322 #ifdef CONFIG_FSL_QIXIS
323 #define CONFIG_SYS_FPGA_BASE 0xffb00000 323 #define CONFIG_SYS_FPGA_BASE 0xffb00000
324 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 324 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
325 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE 325 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE
326 #define QIXIS_LBMAP_SWITCH 9 326 #define QIXIS_LBMAP_SWITCH 9
327 #define QIXIS_LBMAP_MASK 0x07 327 #define QIXIS_LBMAP_MASK 0x07
328 #define QIXIS_LBMAP_SHIFT 0 328 #define QIXIS_LBMAP_SHIFT 0
329 #define QIXIS_LBMAP_DFLTBANK 0x00 329 #define QIXIS_LBMAP_DFLTBANK 0x00
330 #define QIXIS_LBMAP_ALTBANK 0x04 330 #define QIXIS_LBMAP_ALTBANK 0x04
331 #define QIXIS_RST_CTL_RESET 0x83 331 #define QIXIS_RST_CTL_RESET 0x83
332 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 332 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
333 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 333 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
334 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 334 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
335 335
336 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE 336 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE
337 337
338 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ 338 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
339 | CSPR_PORT_SIZE_8 \ 339 | CSPR_PORT_SIZE_8 \
340 | CSPR_MSEL_GPCM \ 340 | CSPR_MSEL_GPCM \
341 | CSPR_V) 341 | CSPR_V)
342 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 342 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
343 #define CONFIG_SYS_CSOR2 0x0 343 #define CONFIG_SYS_CSOR2 0x0
344 /* CPLD Timing parameters for IFC CS3 */ 344 /* CPLD Timing parameters for IFC CS3 */
345 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 345 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
346 FTIM0_GPCM_TEADC(0x0e) | \ 346 FTIM0_GPCM_TEADC(0x0e) | \
347 FTIM0_GPCM_TEAHC(0x0e)) 347 FTIM0_GPCM_TEAHC(0x0e))
348 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 348 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
349 FTIM1_GPCM_TRAD(0x1f)) 349 FTIM1_GPCM_TRAD(0x1f))
350 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 350 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
351 FTIM2_GPCM_TCH(0x0) | \ 351 FTIM2_GPCM_TCH(0x0) | \
352 FTIM2_GPCM_TWP(0x1f)) 352 FTIM2_GPCM_TWP(0x1f))
353 #define CONFIG_SYS_CS2_FTIM3 0x0 353 #define CONFIG_SYS_CS2_FTIM3 0x0
354 #endif 354 #endif
355 355
356 /* Set up IFC registers for boot location NOR/NAND */ 356 /* Set up IFC registers for boot location NOR/NAND */
357 #if defined(CONFIG_NAND) 357 #if defined(CONFIG_NAND)
358 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 358 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
359 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 359 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
360 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 360 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
361 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 361 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
362 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 362 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
363 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 363 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
364 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 364 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
365 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 365 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
366 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 366 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
367 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 367 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
368 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 368 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
369 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 369 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
370 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 370 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
371 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 371 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
372 #else 372 #else
373 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 373 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
374 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 374 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
375 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 375 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
376 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 376 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
377 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 377 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
378 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 378 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
379 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 379 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
380 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 380 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
381 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 381 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
382 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 382 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
383 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 383 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
384 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 384 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
385 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 385 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
386 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 386 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
387 #endif 387 #endif
388 388
389 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 389 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
390 #define CONFIG_BOARD_EARLY_INIT_R 390 #define CONFIG_BOARD_EARLY_INIT_R
391 391
392 #define CONFIG_SYS_INIT_RAM_LOCK 392 #define CONFIG_SYS_INIT_RAM_LOCK
393 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 393 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
394 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 394 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
395 395
396 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 396 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
397 - GENERATED_GBL_DATA_SIZE) 397 - GENERATED_GBL_DATA_SIZE)
398 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 398 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
399 399
400 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ 400 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
401 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 401 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
402 402
403 /* Serial Port */ 403 /* Serial Port */
404 #define CONFIG_CONS_INDEX 1 404 #define CONFIG_CONS_INDEX 1
405 #undef CONFIG_SERIAL_SOFTWARE_FIFO 405 #undef CONFIG_SERIAL_SOFTWARE_FIFO
406 #define CONFIG_SYS_NS16550 406 #define CONFIG_SYS_NS16550
407 #define CONFIG_SYS_NS16550_SERIAL 407 #define CONFIG_SYS_NS16550_SERIAL
408 #define CONFIG_SYS_NS16550_REG_SIZE 1 408 #define CONFIG_SYS_NS16550_REG_SIZE 1
409 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 409 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
410 #ifdef CONFIG_SPL_BUILD 410 #ifdef CONFIG_SPL_BUILD
411 #define CONFIG_NS16550_MIN_FUNCTIONS 411 #define CONFIG_NS16550_MIN_FUNCTIONS
412 #endif 412 #endif
413 413
414 #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */ 414 #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
415 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 415 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
416 416
417 #define CONFIG_SYS_BAUDRATE_TABLE \ 417 #define CONFIG_SYS_BAUDRATE_TABLE \
418 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 418 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
419 419
420 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 420 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
421 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 421 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
422 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) 422 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
423 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) 423 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
424 424
425 /* Use the HUSH parser */ 425 /* Use the HUSH parser */
426 #define CONFIG_SYS_HUSH_PARSER /* hush parser */ 426 #define CONFIG_SYS_HUSH_PARSER /* hush parser */
427 #ifdef CONFIG_SYS_HUSH_PARSER 427 #ifdef CONFIG_SYS_HUSH_PARSER
428 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 428 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
429 #endif 429 #endif
430 430
431 /* 431 /*
432 * Pass open firmware flat tree 432 * Pass open firmware flat tree
433 */ 433 */
434 #define CONFIG_OF_LIBFDT 434 #define CONFIG_OF_LIBFDT
435 #define CONFIG_OF_BOARD_SETUP 435 #define CONFIG_OF_BOARD_SETUP
436 #define CONFIG_OF_STDOUT_VIA_ALIAS 436 #define CONFIG_OF_STDOUT_VIA_ALIAS
437 437
438 /* new uImage format support */ 438 /* new uImage format support */
439 #define CONFIG_FIT 439 #define CONFIG_FIT
440 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 440 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
441 441
442 #define CONFIG_SYS_I2C 442 #define CONFIG_SYS_I2C
443 #define CONFIG_SYS_I2C_FSL 443 #define CONFIG_SYS_I2C_FSL
444 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ 444 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/
445 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 445 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
446 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ 446 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/
447 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 447 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
448 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 448 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
449 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 449 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
450 450
451 /* I2C EEPROM */ 451 /* I2C EEPROM */
452 #define CONFIG_ID_EEPROM 452 #define CONFIG_ID_EEPROM
453 #ifdef CONFIG_ID_EEPROM 453 #ifdef CONFIG_ID_EEPROM
454 #define CONFIG_SYS_I2C_EEPROM_NXID 454 #define CONFIG_SYS_I2C_EEPROM_NXID
455 #endif 455 #endif
456 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 456 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
457 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 457 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
458 #define CONFIG_SYS_EEPROM_BUS_NUM 0 458 #define CONFIG_SYS_EEPROM_BUS_NUM 0
459 459
460 /* enable read and write access to EEPROM */ 460 /* enable read and write access to EEPROM */
461 #define CONFIG_CMD_EEPROM 461 #define CONFIG_CMD_EEPROM
462 #define CONFIG_SYS_I2C_MULTI_EEPROMS 462 #define CONFIG_SYS_I2C_MULTI_EEPROMS
463 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 463 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
464 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 464 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
465 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 465 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
466 466
467 /* I2C FPGA */ 467 /* I2C FPGA */
468 #define CONFIG_I2C_FPGA 468 #define CONFIG_I2C_FPGA
469 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 469 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
470 470
471 #define CONFIG_RTC_DS3231 471 #define CONFIG_RTC_DS3231
472 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 472 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
473 473
474 /* 474 /*
475 * SPI interface will not be available in case of NAND boot SPI CS0 will be 475 * SPI interface will not be available in case of NAND boot SPI CS0 will be
476 * used for SLIC 476 * used for SLIC
477 */ 477 */
478 /* eSPI - Enhanced SPI */ 478 /* eSPI - Enhanced SPI */
479 #define CONFIG_FSL_ESPI /* SPI */ 479 #define CONFIG_FSL_ESPI /* SPI */
480 #ifdef CONFIG_FSL_ESPI 480 #ifdef CONFIG_FSL_ESPI
481 #define CONFIG_SPI_FLASH 481 #define CONFIG_SPI_FLASH
482 #define CONFIG_SPI_FLASH_SPANSION 482 #define CONFIG_SPI_FLASH_SPANSION
483 #define CONFIG_CMD_SF 483 #define CONFIG_CMD_SF
484 #define CONFIG_SF_DEFAULT_SPEED 10000000 484 #define CONFIG_SF_DEFAULT_SPEED 10000000
485 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 485 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
486 #endif 486 #endif
487 487
488 #if defined(CONFIG_TSEC_ENET) 488 #if defined(CONFIG_TSEC_ENET)
489 489
490 #define CONFIG_MII /* MII PHY management */ 490 #define CONFIG_MII /* MII PHY management */
491 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 491 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
492 #define CONFIG_TSEC1 1 492 #define CONFIG_TSEC1 1
493 #define CONFIG_TSEC1_NAME "eTSEC1" 493 #define CONFIG_TSEC1_NAME "eTSEC1"
494 #define CONFIG_TSEC2 1 494 #define CONFIG_TSEC2 1
495 #define CONFIG_TSEC2_NAME "eTSEC2" 495 #define CONFIG_TSEC2_NAME "eTSEC2"
496 496
497 #define TSEC1_PHY_ADDR 0 497 #define TSEC1_PHY_ADDR 0
498 #define TSEC2_PHY_ADDR 1 498 #define TSEC2_PHY_ADDR 1
499 499
500 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 500 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
501 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 501 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
502 502
503 #define TSEC1_PHYIDX 0 503 #define TSEC1_PHYIDX 0
504 #define TSEC2_PHYIDX 0 504 #define TSEC2_PHYIDX 0
505 505
506 #define CONFIG_ETHPRIME "eTSEC1" 506 #define CONFIG_ETHPRIME "eTSEC1"
507 507
508 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 508 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
509 509
510 /* TBI PHY configuration for SGMII mode */ 510 /* TBI PHY configuration for SGMII mode */
511 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 511 #define CONFIG_TSEC_TBICR_SETTINGS ( \
512 TBICR_PHY_RESET \ 512 TBICR_PHY_RESET \
513 | TBICR_ANEG_ENABLE \ 513 | TBICR_ANEG_ENABLE \
514 | TBICR_FULL_DUPLEX \ 514 | TBICR_FULL_DUPLEX \
515 | TBICR_SPEED1_SET \ 515 | TBICR_SPEED1_SET \
516 ) 516 )
517 517
518 #endif /* CONFIG_TSEC_ENET */ 518 #endif /* CONFIG_TSEC_ENET */
519 519
520 #define CONFIG_MMC 520 #define CONFIG_MMC
521 #ifdef CONFIG_MMC 521 #ifdef CONFIG_MMC
522 #define CONFIG_CMD_MMC 522 #define CONFIG_CMD_MMC
523 #define CONFIG_DOS_PARTITION 523 #define CONFIG_DOS_PARTITION
524 #define CONFIG_FSL_ESDHC 524 #define CONFIG_FSL_ESDHC
525 #define CONFIG_GENERIC_MMC 525 #define CONFIG_GENERIC_MMC
526 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 526 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
527 #endif 527 #endif
528 528
529 #define CONFIG_USB_EHCI /* USB */ 529 #define CONFIG_USB_EHCI /* USB */
530 #ifdef CONFIG_USB_EHCI 530 #ifdef CONFIG_USB_EHCI
531 #define CONFIG_CMD_USB 531 #define CONFIG_CMD_USB
532 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 532 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
533 #define CONFIG_USB_EHCI_FSL 533 #define CONFIG_USB_EHCI_FSL
534 #define CONFIG_USB_STORAGE 534 #define CONFIG_USB_STORAGE
535 #define CONFIG_HAS_FSL_DR_USB 535 #define CONFIG_HAS_FSL_DR_USB
536 #endif 536 #endif
537 537
538 /* 538 /*
539 * Environment 539 * Environment
540 */ 540 */
541 #if defined(CONFIG_RAMBOOT_SDCARD) 541 #if defined(CONFIG_RAMBOOT_SDCARD)
542 #define CONFIG_ENV_IS_IN_MMC 542 #define CONFIG_ENV_IS_IN_MMC
543 #define CONFIG_SYS_MMC_ENV_DEV 0 543 #define CONFIG_SYS_MMC_ENV_DEV 0
544 #define CONFIG_ENV_SIZE 0x2000 544 #define CONFIG_ENV_SIZE 0x2000
545 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 545 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
546 #define CONFIG_ENV_IS_IN_SPI_FLASH 546 #define CONFIG_ENV_IS_IN_SPI_FLASH
547 #define CONFIG_ENV_SPI_BUS 0 547 #define CONFIG_ENV_SPI_BUS 0
548 #define CONFIG_ENV_SPI_CS 0 548 #define CONFIG_ENV_SPI_CS 0
549 #define CONFIG_ENV_SPI_MAX_HZ 10000000 549 #define CONFIG_ENV_SPI_MAX_HZ 10000000
550 #define CONFIG_ENV_SPI_MODE 0 550 #define CONFIG_ENV_SPI_MODE 0
551 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 551 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
552 #define CONFIG_ENV_SECT_SIZE 0x10000 552 #define CONFIG_ENV_SECT_SIZE 0x10000
553 #define CONFIG_ENV_SIZE 0x2000 553 #define CONFIG_ENV_SIZE 0x2000
554 #elif defined(CONFIG_NAND) 554 #elif defined(CONFIG_NAND)
555 #define CONFIG_ENV_IS_IN_NAND 555 #define CONFIG_ENV_IS_IN_NAND
556 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 556 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
557 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 557 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
558 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 558 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
559 #elif defined(CONFIG_SYS_RAMBOOT) 559 #elif defined(CONFIG_SYS_RAMBOOT)
560 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 560 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
561 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 561 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
562 #define CONFIG_ENV_SIZE 0x2000 562 #define CONFIG_ENV_SIZE 0x2000
563 #else 563 #else
564 #define CONFIG_ENV_IS_IN_FLASH 564 #define CONFIG_ENV_IS_IN_FLASH
565 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 565 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
566 #define CONFIG_ENV_ADDR 0xfff80000 566 #define CONFIG_ENV_ADDR 0xfff80000
567 #else 567 #else
568 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 568 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
569 #endif 569 #endif
570 #define CONFIG_ENV_SIZE 0x2000 570 #define CONFIG_ENV_SIZE 0x2000
571 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 571 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
572 #endif 572 #endif
573 573
574 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 574 #define CONFIG_LOADS_ECHO /* echo on for serial download */
575 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 575 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
576 576
577 /* 577 /*
578 * Command line configuration. 578 * Command line configuration.
579 */ 579 */
580 #include <config_cmd_default.h> 580 #include <config_cmd_default.h>
581 581
582 #define CONFIG_CMD_DATE 582 #define CONFIG_CMD_DATE
583 #define CONFIG_CMD_DHCP 583 #define CONFIG_CMD_DHCP
584 #define CONFIG_CMD_ELF 584 #define CONFIG_CMD_ELF
585 #define CONFIG_CMD_ERRATA 585 #define CONFIG_CMD_ERRATA
586 #define CONFIG_CMD_I2C 586 #define CONFIG_CMD_I2C
587 #define CONFIG_CMD_IRQ 587 #define CONFIG_CMD_IRQ
588 #define CONFIG_CMD_MII 588 #define CONFIG_CMD_MII
589 #define CONFIG_CMD_PING 589 #define CONFIG_CMD_PING
590 #define CONFIG_CMD_SETEXPR 590 #define CONFIG_CMD_SETEXPR
591 #define CONFIG_CMD_REGINFO 591 #define CONFIG_CMD_REGINFO
592 592
593 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 593 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
594 #define CONFIG_CMD_EXT2 594 #define CONFIG_CMD_EXT2
595 #define CONFIG_CMD_FAT 595 #define CONFIG_CMD_FAT
596 #define CONFIG_DOS_PARTITION 596 #define CONFIG_DOS_PARTITION
597 #endif 597 #endif
598 598
599 /* 599 /*
600 * Miscellaneous configurable options 600 * Miscellaneous configurable options
601 */ 601 */
602 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 602 #define CONFIG_SYS_LONGHELP /* undef to save memory */
603 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 603 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
604 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 604 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
605 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 605 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
606 606
607 #if defined(CONFIG_CMD_KGDB) 607 #if defined(CONFIG_CMD_KGDB)
608 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 608 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
609 #else 609 #else
610 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 610 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
611 #endif 611 #endif
612 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 612 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
613 /* Print Buffer Size */ 613 /* Print Buffer Size */
614 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 614 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
615 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 615 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
616 616
617 617
618 /* 618 /*
619 * For booting Linux, the board info and command line data 619 * For booting Linux, the board info and command line data
620 * have to be in the first 64 MB of memory, since this is 620 * have to be in the first 64 MB of memory, since this is
621 * the maximum mapped by the Linux kernel during initialization. 621 * the maximum mapped by the Linux kernel during initialization.
622 */ 622 */
623 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 623 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
624 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 624 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
625 625
626 #if defined(CONFIG_CMD_KGDB) 626 #if defined(CONFIG_CMD_KGDB)
627 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 627 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
628 #endif 628 #endif
629 629
630 /* 630 /*
631 * Environment Configuration 631 * Environment Configuration
632 */ 632 */
633 633
634 #if defined(CONFIG_TSEC_ENET) 634 #if defined(CONFIG_TSEC_ENET)
635 #define CONFIG_HAS_ETH0 635 #define CONFIG_HAS_ETH0
636 #define CONFIG_HAS_ETH1 636 #define CONFIG_HAS_ETH1
637 #endif 637 #endif
638 638
639 #define CONFIG_HOSTNAME BSC9132qds 639 #define CONFIG_HOSTNAME BSC9132qds
640 #define CONFIG_ROOTPATH "/opt/nfsroot" 640 #define CONFIG_ROOTPATH "/opt/nfsroot"
641 #define CONFIG_BOOTFILE "uImage" 641 #define CONFIG_BOOTFILE "uImage"
642 #define CONFIG_UBOOTPATH "u-boot.bin" 642 #define CONFIG_UBOOTPATH "u-boot.bin"
643 643
644 #define CONFIG_BAUDRATE 115200 644 #define CONFIG_BAUDRATE 115200
645 645
646 #ifdef CONFIG_SDCARD 646 #ifdef CONFIG_SDCARD
647 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 647 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
648 #else 648 #else
649 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" 649 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
650 #endif 650 #endif
651 651
652 #define CONFIG_EXTRA_ENV_SETTINGS \ 652 #define CONFIG_EXTRA_ENV_SETTINGS \
653 "netdev=eth0\0" \ 653 "netdev=eth0\0" \
654 "uboot=" CONFIG_UBOOTPATH "\0" \ 654 "uboot=" CONFIG_UBOOTPATH "\0" \
655 "loadaddr=1000000\0" \ 655 "loadaddr=1000000\0" \
656 "bootfile=uImage\0" \ 656 "bootfile=uImage\0" \
657 "consoledev=ttyS0\0" \ 657 "consoledev=ttyS0\0" \
658 "ramdiskaddr=2000000\0" \ 658 "ramdiskaddr=2000000\0" \
659 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 659 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
660 "fdtaddr=c00000\0" \ 660 "fdtaddr=c00000\0" \
661 "fdtfile=bsc9132qds.dtb\0" \ 661 "fdtfile=bsc9132qds.dtb\0" \
662 "bdev=sda1\0" \ 662 "bdev=sda1\0" \
663 CONFIG_DEF_HWCONFIG\ 663 CONFIG_DEF_HWCONFIG\
664 "othbootargs=mem=880M ramdisk_size=600000 " \ 664 "othbootargs=mem=880M ramdisk_size=600000 " \
665 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ 665 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
666 "isolcpus=0\0" \ 666 "isolcpus=0\0" \
667 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 667 "usbext2boot=setenv bootargs root=/dev/ram rw " \
668 "console=$consoledev,$baudrate $othbootargs; " \ 668 "console=$consoledev,$baudrate $othbootargs; " \
669 "usb start;" \ 669 "usb start;" \
670 "ext2load usb 0:4 $loadaddr $bootfile;" \ 670 "ext2load usb 0:4 $loadaddr $bootfile;" \
671 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 671 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
672 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 672 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
673 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 673 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
674 "debug_halt_off=mw ff7e0e30 0xf0000000;" 674 "debug_halt_off=mw ff7e0e30 0xf0000000;"
675 675
676 #define CONFIG_NFSBOOTCOMMAND \ 676 #define CONFIG_NFSBOOTCOMMAND \
677 "setenv bootargs root=/dev/nfs rw " \ 677 "setenv bootargs root=/dev/nfs rw " \
678 "nfsroot=$serverip:$rootpath " \ 678 "nfsroot=$serverip:$rootpath " \
679 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 679 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
680 "console=$consoledev,$baudrate $othbootargs;" \ 680 "console=$consoledev,$baudrate $othbootargs;" \
681 "tftp $loadaddr $bootfile;" \ 681 "tftp $loadaddr $bootfile;" \
682 "tftp $fdtaddr $fdtfile;" \ 682 "tftp $fdtaddr $fdtfile;" \
683 "bootm $loadaddr - $fdtaddr" 683 "bootm $loadaddr - $fdtaddr"
684 684
685 #define CONFIG_HDBOOT \ 685 #define CONFIG_HDBOOT \
686 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 686 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
687 "console=$consoledev,$baudrate $othbootargs;" \ 687 "console=$consoledev,$baudrate $othbootargs;" \
688 "usb start;" \ 688 "usb start;" \
689 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 689 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
690 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 690 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
691 "bootm $loadaddr - $fdtaddr" 691 "bootm $loadaddr - $fdtaddr"
692 692
693 #define CONFIG_RAMBOOTCOMMAND \ 693 #define CONFIG_RAMBOOTCOMMAND \
694 "setenv bootargs root=/dev/ram rw " \ 694 "setenv bootargs root=/dev/ram rw " \
695 "console=$consoledev,$baudrate $othbootargs; " \ 695 "console=$consoledev,$baudrate $othbootargs; " \
696 "tftp $ramdiskaddr $ramdiskfile;" \ 696 "tftp $ramdiskaddr $ramdiskfile;" \
697 "tftp $loadaddr $bootfile;" \ 697 "tftp $loadaddr $bootfile;" \
698 "tftp $fdtaddr $fdtfile;" \ 698 "tftp $fdtaddr $fdtfile;" \
699 "bootm $loadaddr $ramdiskaddr $fdtaddr" 699 "bootm $loadaddr $ramdiskaddr $fdtaddr"
700 700
701 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 701 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
702 702
703 #endif /* __CONFIG_H */ 703 #endif /* __CONFIG_H */
704 704
include/configs/CMS700.h
1 /* 1 /*
2 * (C) Copyright 2005 2 * (C) Copyright 2005
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com 3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 /* 8 /*
9 * CMS700.h - configuration options, board specific 9 * CMS700.h - configuration options, board specific
10 */ 10 */
11 11
12 #ifndef __CONFIG_H 12 #ifndef __CONFIG_H
13 #define __CONFIG_H 13 #define __CONFIG_H
14 14
15 /* 15 /*
16 * High Level Configuration Options 16 * High Level Configuration Options
17 * (easy to change) 17 * (easy to change)
18 */ 18 */
19 19
20 #define CONFIG_405EP 1 /* This is a PPC405 CPU */ 20 #define CONFIG_405EP 1 /* This is a PPC405 CPU */
21 #define CONFIG_4xx 1 /* ...member of PPC4xx family */ 21 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
22 #define CONFIG_VOM405 1 /* ...on a VOM405 board */ 22 #define CONFIG_VOM405 1 /* ...on a VOM405 board */
23 23
24 #define CONFIG_SYS_TEXT_BASE 0xFFFC8000 24 #define CONFIG_SYS_TEXT_BASE 0xFFFC8000
25 25
26 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ 26 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
27 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ 27 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
28 28
29 #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ 29 #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
30 30
31 #define CONFIG_BAUDRATE 9600 31 #define CONFIG_BAUDRATE 9600
32 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ 32 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
33 33
34 #undef CONFIG_BOOTARGS 34 #undef CONFIG_BOOTARGS
35 #undef CONFIG_BOOTCOMMAND 35 #undef CONFIG_BOOTCOMMAND
36 36
37 #define CONFIG_PREBOOT /* enable preboot variable */ 37 #define CONFIG_PREBOOT /* enable preboot variable */
38 38
39 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 39 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
40 40
41 #define CONFIG_PPC4xx_EMAC 41 #define CONFIG_PPC4xx_EMAC
42 #undef CONFIG_HAS_ETH1 42 #undef CONFIG_HAS_ETH1
43 43
44 #define CONFIG_MII 1 /* MII PHY management */ 44 #define CONFIG_MII 1 /* MII PHY management */
45 #define CONFIG_PHY_ADDR 0 /* PHY address */ 45 #define CONFIG_PHY_ADDR 0 /* PHY address */
46 #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ 46 #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
47 #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ 47 #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
48 48
49 /* 49 /*
50 * BOOTP options 50 * BOOTP options
51 */ 51 */
52 #define CONFIG_BOOTP_SUBNETMASK 52 #define CONFIG_BOOTP_SUBNETMASK
53 #define CONFIG_BOOTP_GATEWAY 53 #define CONFIG_BOOTP_GATEWAY
54 #define CONFIG_BOOTP_HOSTNAME 54 #define CONFIG_BOOTP_HOSTNAME
55 #define CONFIG_BOOTP_BOOTPATH 55 #define CONFIG_BOOTP_BOOTPATH
56 #define CONFIG_BOOTP_DNS 56 #define CONFIG_BOOTP_DNS
57 #define CONFIG_BOOTP_DNS2 57 #define CONFIG_BOOTP_DNS2
58 #define CONFIG_BOOTP_SEND_HOSTNAME 58 #define CONFIG_BOOTP_SEND_HOSTNAME
59 59
60 60
61 /* 61 /*
62 * Command line configuration. 62 * Command line configuration.
63 */ 63 */
64 #include <config_cmd_default.h> 64 #include <config_cmd_default.h>
65 65
66 #define CONFIG_CMD_DHCP 66 #define CONFIG_CMD_DHCP
67 #define CONFIG_CMD_BSP 67 #define CONFIG_CMD_BSP
68 #define CONFIG_CMD_ELF 68 #define CONFIG_CMD_ELF
69 #define CONFIG_CMD_NAND 69 #define CONFIG_CMD_NAND
70 #define CONFIG_CMD_I2C 70 #define CONFIG_CMD_I2C
71 #define CONFIG_CMD_DATE 71 #define CONFIG_CMD_DATE
72 #define CONFIG_CMD_MII 72 #define CONFIG_CMD_MII
73 #define CONFIG_CMD_PING 73 #define CONFIG_CMD_PING
74 #define CONFIG_CMD_EEPROM 74 #define CONFIG_CMD_EEPROM
75 75
76 76
77 #undef CONFIG_WATCHDOG /* watchdog disabled */ 77 #undef CONFIG_WATCHDOG /* watchdog disabled */
78 78
79 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ 79 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
80 80
81 #undef CONFIG_PRAM /* no "protected RAM" */ 81 #undef CONFIG_PRAM /* no "protected RAM" */
82 82
83 /* 83 /*
84 * Miscellaneous configurable options 84 * Miscellaneous configurable options
85 */ 85 */
86 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 86 #define CONFIG_SYS_LONGHELP /* undef to save memory */
87 87
88 #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 88 #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
89 89
90 #if defined(CONFIG_CMD_KGDB) 90 #if defined(CONFIG_CMD_KGDB)
91 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 91 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
92 #else 92 #else
93 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 93 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
94 #endif 94 #endif
95 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 95 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
96 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 96 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
97 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 97 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
98 98
99 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ 99 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
100 100
101 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ 101 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
102 102
103 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 103 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
104 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 104 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
105 105
106 #define CONFIG_CONS_INDEX 2 /* Use UART1 */ 106 #define CONFIG_CONS_INDEX 2 /* Use UART1 */
107 #define CONFIG_SYS_NS16550 107 #define CONFIG_SYS_NS16550
108 #define CONFIG_SYS_NS16550_SERIAL 108 #define CONFIG_SYS_NS16550_SERIAL
109 #define CONFIG_SYS_NS16550_REG_SIZE 1 109 #define CONFIG_SYS_NS16550_REG_SIZE 1
110 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 110 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
111 111
112 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ 112 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
113 #define CONFIG_SYS_BASE_BAUD 691200 113 #define CONFIG_SYS_BASE_BAUD 691200
114 114
115 /* The following table includes the supported baudrates */ 115 /* The following table includes the supported baudrates */
116 #define CONFIG_SYS_BAUDRATE_TABLE \ 116 #define CONFIG_SYS_BAUDRATE_TABLE \
117 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 117 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
118 57600, 115200, 230400, 460800, 921600 } 118 57600, 115200, 230400, 460800, 921600 }
119 119
120 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 120 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
121 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ 121 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
122 122
123 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ 123 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
124 124
125 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ 125 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
126 126
127 #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ 127 #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
128 128
129 /*----------------------------------------------------------------------- 129 /*-----------------------------------------------------------------------
130 * RTC stuff 130 * RTC stuff
131 *----------------------------------------------------------------------- 131 *-----------------------------------------------------------------------
132 */ 132 */
133 #define CONFIG_RTC_DS1337 133 #define CONFIG_RTC_DS1337
134 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 134 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
135 135
136 /*----------------------------------------------------------------------- 136 /*-----------------------------------------------------------------------
137 * NAND-FLASH stuff 137 * NAND-FLASH stuff
138 *----------------------------------------------------------------------- 138 *-----------------------------------------------------------------------
139 */ 139 */
140 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 140 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
141 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 141 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
142 #define NAND_BIG_DELAY_US 25 142 #define NAND_BIG_DELAY_US 25
143 143
144 #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ 144 #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
145 #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ 145 #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
146 #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ 146 #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
147 #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ 147 #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
148 148
149 #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ 149 #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
150 #define CONFIG_SYS_NAND_QUIET 1 150 #define CONFIG_SYS_NAND_QUIET 1
151 151
152 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
153 #define CONFIG_SYS_NAND_MAX_ECCPOS 48
154
152 /* 155 /*
153 * For booting Linux, the board info and command line data 156 * For booting Linux, the board info and command line data
154 * have to be in the first 8 MB of memory, since this is 157 * have to be in the first 8 MB of memory, since this is
155 * the maximum mapped by the Linux kernel during initialization. 158 * the maximum mapped by the Linux kernel during initialization.
156 */ 159 */
157 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 160 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
158 /*----------------------------------------------------------------------- 161 /*-----------------------------------------------------------------------
159 * FLASH organization 162 * FLASH organization
160 */ 163 */
161 #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ 164 #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
162 165
163 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 166 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
164 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 167 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
165 168
166 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 169 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
167 #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ 170 #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
168 171
169 #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ 172 #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
170 #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ 173 #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
171 #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ 174 #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
172 /* 175 /*
173 * The following defines are added for buggy IOP480 byte interface. 176 * The following defines are added for buggy IOP480 byte interface.
174 * All other boards should use the standard values (CPCI405 etc.) 177 * All other boards should use the standard values (CPCI405 etc.)
175 */ 178 */
176 #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ 179 #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
177 #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ 180 #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
178 #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ 181 #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
179 182
180 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 183 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
181 184
182 /*----------------------------------------------------------------------- 185 /*-----------------------------------------------------------------------
183 * Start addresses for the final memory configuration 186 * Start addresses for the final memory configuration
184 * (Set up by the startup code) 187 * (Set up by the startup code)
185 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 188 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
186 */ 189 */
187 #define CONFIG_SYS_SDRAM_BASE 0x00000000 190 #define CONFIG_SYS_SDRAM_BASE 0x00000000
188 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE 191 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
189 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 192 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
190 #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) 193 #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
191 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 194 #define CONFIG_SYS_MALLOC_LEN (256 * 1024)
192 195
193 #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) 196 #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
194 # define CONFIG_SYS_RAMBOOT 1 197 # define CONFIG_SYS_RAMBOOT 1
195 #else 198 #else
196 # undef CONFIG_SYS_RAMBOOT 199 # undef CONFIG_SYS_RAMBOOT
197 #endif 200 #endif
198 201
199 /*----------------------------------------------------------------------- 202 /*-----------------------------------------------------------------------
200 * Environment Variable setup 203 * Environment Variable setup
201 */ 204 */
202 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ 205 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
203 #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ 206 #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
204 #define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ 207 #define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
205 /* total size of a CAT24WC16 is 2048 bytes */ 208 /* total size of a CAT24WC16 is 2048 bytes */
206 209
207 /*----------------------------------------------------------------------- 210 /*-----------------------------------------------------------------------
208 * I2C EEPROM (CAT24WC16) for environment 211 * I2C EEPROM (CAT24WC16) for environment
209 */ 212 */
210 #define CONFIG_SYS_I2C 213 #define CONFIG_SYS_I2C
211 #define CONFIG_SYS_I2C_PPC4XX 214 #define CONFIG_SYS_I2C_PPC4XX
212 #define CONFIG_SYS_I2C_PPC4XX_CH0 215 #define CONFIG_SYS_I2C_PPC4XX_CH0
213 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 216 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
214 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F 217 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
215 218
216 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ 219 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
217 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ 220 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
218 /* mask of address bits that overflow into the "EEPROM chip address" */ 221 /* mask of address bits that overflow into the "EEPROM chip address" */
219 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 222 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
220 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ 223 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
221 /* 16 byte page write mode using*/ 224 /* 16 byte page write mode using*/
222 /* last 4 bits of the address */ 225 /* last 4 bits of the address */
223 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 226 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
224 227
225 #define CONFIG_SYS_EEPROM_WREN 1 228 #define CONFIG_SYS_EEPROM_WREN 1
226 229
227 /*----------------------------------------------------------------------- 230 /*-----------------------------------------------------------------------
228 * External Bus Controller (EBC) Setup 231 * External Bus Controller (EBC) Setup
229 */ 232 */
230 #define CONFIG_SYS_PLD_BASE 0xf0000000 233 #define CONFIG_SYS_PLD_BASE 0xf0000000
231 #define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ 234 #define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
232 235
233 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ 236 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
234 #define CONFIG_SYS_EBC_PB0AP 0x92015480 237 #define CONFIG_SYS_EBC_PB0AP 0x92015480
235 #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ 238 #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
236 239
237 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ 240 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
238 #define CONFIG_SYS_EBC_PB1AP 0x92015480 241 #define CONFIG_SYS_EBC_PB1AP 0x92015480
239 #define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ 242 #define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
240 243
241 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ 244 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
242 #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ 245 #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
243 #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ 246 #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
244 247
245 /*----------------------------------------------------------------------- 248 /*-----------------------------------------------------------------------
246 * FPGA stuff 249 * FPGA stuff
247 */ 250 */
248 #define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000 251 #define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000
249 252
250 /* FPGA program pin configuration */ 253 /* FPGA program pin configuration */
251 #define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ 254 #define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
252 #define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ 255 #define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
253 #define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ 256 #define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
254 #define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */ 257 #define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
255 #define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ 258 #define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
256 259
257 /*----------------------------------------------------------------------- 260 /*-----------------------------------------------------------------------
258 * Definitions for initial stack pointer and data area (in data cache) 261 * Definitions for initial stack pointer and data area (in data cache)
259 */ 262 */
260 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ 263 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
261 #define CONFIG_SYS_TEMP_STACK_OCM 1 264 #define CONFIG_SYS_TEMP_STACK_OCM 1
262 265
263 /* On Chip Memory location */ 266 /* On Chip Memory location */
264 #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 267 #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
265 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 268 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
266 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ 269 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
267 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ 270 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
268 271
269 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 272 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
270 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 273 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
271 274
272 /*----------------------------------------------------------------------- 275 /*-----------------------------------------------------------------------
273 * Definitions for GPIO setup (PPC405EP specific) 276 * Definitions for GPIO setup (PPC405EP specific)
274 * 277 *
275 * GPIO0[0] - External Bus Controller BLAST output 278 * GPIO0[0] - External Bus Controller BLAST output
276 * GPIO0[1-9] - Instruction trace outputs -> GPIO 279 * GPIO0[1-9] - Instruction trace outputs -> GPIO
277 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs 280 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
278 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO 281 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
279 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs 282 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
280 * GPIO0[24-27] - UART0 control signal inputs/outputs 283 * GPIO0[24-27] - UART0 control signal inputs/outputs
281 * GPIO0[28-29] - UART1 data signal input/output 284 * GPIO0[28-29] - UART1 data signal input/output
282 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs 285 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
283 */ 286 */
284 /* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */ 287 /* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */
285 /* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ 288 /* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
286 /* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ 289 /* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
287 /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ 290 /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
288 #define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */ 291 #define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */
289 #define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */ 292 #define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */
290 #define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */ 293 #define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */
291 #define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */ 294 #define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */
292 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */ 295 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */
293 #define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */ 296 #define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */
294 #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */ 297 #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
295 298
296 #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */ 299 #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */
297 #define CONFIG_SYS_PLD_RESET (0x80000000 >> 12) /* GPIO12 */ 300 #define CONFIG_SYS_PLD_RESET (0x80000000 >> 12) /* GPIO12 */
298 301
299 /* 302 /*
300 * Default speed selection (cpu_plb_opb_ebc) in mhz. 303 * Default speed selection (cpu_plb_opb_ebc) in mhz.
301 * This value will be set if iic boot eprom is disabled. 304 * This value will be set if iic boot eprom is disabled.
302 */ 305 */
303 #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 306 #define PLLMR0_DEFAULT PLLMR0_133_66_66_33
304 #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 307 #define PLLMR1_DEFAULT PLLMR1_133_66_66_33
305 308
306 #endif /* __CONFIG_H */ 309 #endif /* __CONFIG_H */
307 310
include/configs/P1010RDB.h
1 /* 1 /*
2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 /* 7 /*
8 * P010 RDB board configuration file 8 * P010 RDB board configuration file
9 */ 9 */
10 10
11 #ifndef __CONFIG_H 11 #ifndef __CONFIG_H
12 #define __CONFIG_H 12 #define __CONFIG_H
13 13
14 #ifdef CONFIG_36BIT 14 #ifdef CONFIG_36BIT
15 #define CONFIG_PHYS_64BIT 15 #define CONFIG_PHYS_64BIT
16 #endif 16 #endif
17 17
18 #define CONFIG_P1010 18 #define CONFIG_P1010
19 #define CONFIG_E500 /* BOOKE e500 family */ 19 #define CONFIG_E500 /* BOOKE e500 family */
20 #include <asm/config_mpc85xx.h> 20 #include <asm/config_mpc85xx.h>
21 #define CONFIG_NAND_FSL_IFC 21 #define CONFIG_NAND_FSL_IFC
22 22
23 #ifdef CONFIG_SDCARD 23 #ifdef CONFIG_SDCARD
24 #define CONFIG_RAMBOOT_SDCARD 24 #define CONFIG_RAMBOOT_SDCARD
25 #define CONFIG_SYS_TEXT_BASE 0x11000000 25 #define CONFIG_SYS_TEXT_BASE 0x11000000
26 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 26 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
27 #endif 27 #endif
28 28
29 #ifdef CONFIG_SPIFLASH 29 #ifdef CONFIG_SPIFLASH
30 #define CONFIG_RAMBOOT_SPIFLASH 30 #define CONFIG_RAMBOOT_SPIFLASH
31 #define CONFIG_SYS_TEXT_BASE 0x11000000 31 #define CONFIG_SYS_TEXT_BASE 0x11000000
32 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 32 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
33 #endif 33 #endif
34 34
35 #ifdef CONFIG_NAND 35 #ifdef CONFIG_NAND
36 #define CONFIG_SPL 36 #define CONFIG_SPL
37 #define CONFIG_SPL_INIT_MINIMAL 37 #define CONFIG_SPL_INIT_MINIMAL
38 #define CONFIG_SPL_SERIAL_SUPPORT 38 #define CONFIG_SPL_SERIAL_SUPPORT
39 #define CONFIG_SPL_NAND_SUPPORT 39 #define CONFIG_SPL_NAND_SUPPORT
40 #define CONFIG_SPL_NAND_MINIMAL 40 #define CONFIG_SPL_NAND_BOOT
41 #define CONFIG_SPL_FLUSH_IMAGE 41 #define CONFIG_SPL_FLUSH_IMAGE
42 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 42 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
43 43
44 #define CONFIG_SYS_TEXT_BASE 0x00201000 44 #define CONFIG_SYS_TEXT_BASE 0x00201000
45 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 45 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
46 #define CONFIG_SPL_MAX_SIZE 8192 46 #define CONFIG_SPL_MAX_SIZE 8192
47 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 47 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
48 #define CONFIG_SPL_RELOC_STACK 0x00100000 48 #define CONFIG_SPL_RELOC_STACK 0x00100000
49 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 49 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
50 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 50 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
51 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 51 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
52 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 52 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
54 #endif 54 #endif
55 55
56 56
57 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 57 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
58 #define CONFIG_RAMBOOT_NAND 58 #define CONFIG_RAMBOOT_NAND
59 #define CONFIG_SYS_TEXT_BASE 0x11000000 59 #define CONFIG_SYS_TEXT_BASE 0x11000000
60 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 60 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
61 #endif 61 #endif
62 62
63 #ifndef CONFIG_SYS_TEXT_BASE 63 #ifndef CONFIG_SYS_TEXT_BASE
64 #define CONFIG_SYS_TEXT_BASE 0xeff80000 64 #define CONFIG_SYS_TEXT_BASE 0xeff80000
65 #endif 65 #endif
66 66
67 #ifndef CONFIG_RESET_VECTOR_ADDRESS 67 #ifndef CONFIG_RESET_VECTOR_ADDRESS
68 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 68 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
69 #endif 69 #endif
70 70
71 #ifdef CONFIG_SPL_BUILD 71 #ifdef CONFIG_SPL_BUILD
72 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 72 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
73 #else 73 #else
74 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 74 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
75 #endif 75 #endif
76 76
77 /* High Level Configuration Options */ 77 /* High Level Configuration Options */
78 #define CONFIG_BOOKE /* BOOKE */ 78 #define CONFIG_BOOKE /* BOOKE */
79 #define CONFIG_E500 /* BOOKE e500 family */ 79 #define CONFIG_E500 /* BOOKE e500 family */
80 #define CONFIG_MPC85xx 80 #define CONFIG_MPC85xx
81 #define CONFIG_FSL_IFC /* Enable IFC Support */ 81 #define CONFIG_FSL_IFC /* Enable IFC Support */
82 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 82 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
83 83
84 #define CONFIG_PCI /* Enable PCI/PCIE */ 84 #define CONFIG_PCI /* Enable PCI/PCIE */
85 #if defined(CONFIG_PCI) 85 #if defined(CONFIG_PCI)
86 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 86 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
87 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 87 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
88 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 88 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
89 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 89 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
90 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 90 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
91 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 91 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
92 92
93 #define CONFIG_CMD_NET 93 #define CONFIG_CMD_NET
94 #define CONFIG_CMD_PCI 94 #define CONFIG_CMD_PCI
95 95
96 #define CONFIG_E1000 /* E1000 pci Ethernet card*/ 96 #define CONFIG_E1000 /* E1000 pci Ethernet card*/
97 97
98 /* 98 /*
99 * PCI Windows 99 * PCI Windows
100 * Memory space is mapped 1-1, but I/O space must start from 0. 100 * Memory space is mapped 1-1, but I/O space must start from 0.
101 */ 101 */
102 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 102 /* controller 1, Slot 1, tgtid 1, Base address a000 */
103 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 103 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
104 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 104 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
105 #ifdef CONFIG_PHYS_64BIT 105 #ifdef CONFIG_PHYS_64BIT
106 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 106 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
107 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 107 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
108 #else 108 #else
109 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 109 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
110 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 110 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
111 #endif 111 #endif
112 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 112 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
113 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 113 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
114 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 114 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
115 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 115 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
116 #ifdef CONFIG_PHYS_64BIT 116 #ifdef CONFIG_PHYS_64BIT
117 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 117 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
118 #else 118 #else
119 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 119 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
120 #endif 120 #endif
121 121
122 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 122 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
123 #if defined(CONFIG_P1010RDB_PA) 123 #if defined(CONFIG_P1010RDB_PA)
124 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 124 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
125 #elif defined(CONFIG_P1010RDB_PB) 125 #elif defined(CONFIG_P1010RDB_PB)
126 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 126 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot"
127 #endif 127 #endif
128 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 128 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
129 #ifdef CONFIG_PHYS_64BIT 129 #ifdef CONFIG_PHYS_64BIT
130 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 130 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
131 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 131 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
132 #else 132 #else
133 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 133 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
134 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 134 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
135 #endif 135 #endif
136 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 136 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
137 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 137 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
138 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 138 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
139 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 139 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
140 #ifdef CONFIG_PHYS_64BIT 140 #ifdef CONFIG_PHYS_64BIT
141 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 141 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
142 #else 142 #else
143 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 143 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
144 #endif 144 #endif
145 145
146 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 146 #define CONFIG_PCI_PNP /* do pci plug-and-play */
147 147
148 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 148 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
149 #define CONFIG_DOS_PARTITION 149 #define CONFIG_DOS_PARTITION
150 #endif 150 #endif
151 151
152 #define CONFIG_FSL_LAW /* Use common FSL init code */ 152 #define CONFIG_FSL_LAW /* Use common FSL init code */
153 #define CONFIG_TSEC_ENET 153 #define CONFIG_TSEC_ENET
154 #define CONFIG_ENV_OVERWRITE 154 #define CONFIG_ENV_OVERWRITE
155 155
156 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 156 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */
157 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 157 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
158 158
159 #define CONFIG_MISC_INIT_R 159 #define CONFIG_MISC_INIT_R
160 #define CONFIG_HWCONFIG 160 #define CONFIG_HWCONFIG
161 /* 161 /*
162 * These can be toggled for performance analysis, otherwise use default. 162 * These can be toggled for performance analysis, otherwise use default.
163 */ 163 */
164 #define CONFIG_L2_CACHE /* toggle L2 cache */ 164 #define CONFIG_L2_CACHE /* toggle L2 cache */
165 #define CONFIG_BTB /* toggle branch predition */ 165 #define CONFIG_BTB /* toggle branch predition */
166 166
167 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 167 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
168 168
169 #define CONFIG_ENABLE_36BIT_PHYS 169 #define CONFIG_ENABLE_36BIT_PHYS
170 170
171 #ifdef CONFIG_PHYS_64BIT 171 #ifdef CONFIG_PHYS_64BIT
172 #define CONFIG_ADDR_MAP 1 172 #define CONFIG_ADDR_MAP 1
173 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 173 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
174 #endif 174 #endif
175 175
176 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 176 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
177 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 177 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
178 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 178 #define CONFIG_PANIC_HANG /* do not reset board on panic */
179 179
180 /* DDR Setup */ 180 /* DDR Setup */
181 #define CONFIG_SYS_FSL_DDR3 181 #define CONFIG_SYS_FSL_DDR3
182 #define CONFIG_SYS_DDR_RAW_TIMING 182 #define CONFIG_SYS_DDR_RAW_TIMING
183 #define CONFIG_DDR_SPD 183 #define CONFIG_DDR_SPD
184 #define CONFIG_SYS_SPD_BUS_NUM 1 184 #define CONFIG_SYS_SPD_BUS_NUM 1
185 #define SPD_EEPROM_ADDRESS 0x52 185 #define SPD_EEPROM_ADDRESS 0x52
186 186
187 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 187 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
188 188
189 #ifndef __ASSEMBLY__ 189 #ifndef __ASSEMBLY__
190 extern unsigned long get_sdram_size(void); 190 extern unsigned long get_sdram_size(void);
191 #endif 191 #endif
192 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 192 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
193 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 193 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
194 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 194 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
195 195
196 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 196 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
197 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 197 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
198 198
199 /* DDR3 Controller Settings */ 199 /* DDR3 Controller Settings */
200 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 200 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
201 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 201 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
202 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 202 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
203 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 203 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
204 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 204 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
205 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 205 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
206 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 206 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
207 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 207 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
208 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 208 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
209 #define CONFIG_SYS_DDR_RCW_1 0x00000000 209 #define CONFIG_SYS_DDR_RCW_1 0x00000000
210 #define CONFIG_SYS_DDR_RCW_2 0x00000000 210 #define CONFIG_SYS_DDR_RCW_2 0x00000000
211 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 211 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
212 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 212 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
213 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 213 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
214 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 214 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
215 215
216 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 216 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
217 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 217 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
218 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 218 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
219 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 219 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
220 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 220 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
221 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 221 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
222 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 222 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
223 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 223 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
224 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 224 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
225 225
226 /* settings for DDR3 at 667MT/s */ 226 /* settings for DDR3 at 667MT/s */
227 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 227 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
228 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 228 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
229 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 229 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
230 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 230 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
231 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 231 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
232 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 232 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
233 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 233 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
234 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 234 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
235 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 235 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
236 236
237 #define CONFIG_SYS_CCSRBAR 0xffe00000 237 #define CONFIG_SYS_CCSRBAR 0xffe00000
238 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 238 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
239 239
240 /* Don't relocate CCSRBAR while in NAND_SPL */ 240 /* Don't relocate CCSRBAR while in NAND_SPL */
241 #ifdef CONFIG_SPL_BUILD 241 #ifdef CONFIG_SPL_BUILD
242 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 242 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
243 #endif 243 #endif
244 244
245 /* 245 /*
246 * Memory map 246 * Memory map
247 * 247 *
248 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 248 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
249 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 249 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
250 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 250 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
251 * 251 *
252 * Localbus non-cacheable 252 * Localbus non-cacheable
253 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 253 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
254 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 254 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
255 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 255 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
256 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 256 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
257 */ 257 */
258 258
259 /* 259 /*
260 * IFC Definitions 260 * IFC Definitions
261 */ 261 */
262 /* NOR Flash on IFC */ 262 /* NOR Flash on IFC */
263 #ifdef CONFIG_SPL_BUILD 263 #ifdef CONFIG_SPL_BUILD
264 #define CONFIG_SYS_NO_FLASH 264 #define CONFIG_SYS_NO_FLASH
265 #endif 265 #endif
266 266
267 #define CONFIG_SYS_FLASH_BASE 0xee000000 267 #define CONFIG_SYS_FLASH_BASE 0xee000000
268 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 268 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
269 269
270 #ifdef CONFIG_PHYS_64BIT 270 #ifdef CONFIG_PHYS_64BIT
271 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 271 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
272 #else 272 #else
273 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 273 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
274 #endif 274 #endif
275 275
276 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 276 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
277 CSPR_PORT_SIZE_16 | \ 277 CSPR_PORT_SIZE_16 | \
278 CSPR_MSEL_NOR | \ 278 CSPR_MSEL_NOR | \
279 CSPR_V) 279 CSPR_V)
280 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 280 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
281 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 281 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
282 /* NOR Flash Timing Params */ 282 /* NOR Flash Timing Params */
283 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 283 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
284 FTIM0_NOR_TEADC(0x5) | \ 284 FTIM0_NOR_TEADC(0x5) | \
285 FTIM0_NOR_TEAHC(0x5) 285 FTIM0_NOR_TEAHC(0x5)
286 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 286 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
287 FTIM1_NOR_TRAD_NOR(0x0f) 287 FTIM1_NOR_TRAD_NOR(0x0f)
288 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 288 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
289 FTIM2_NOR_TCH(0x4) | \ 289 FTIM2_NOR_TCH(0x4) | \
290 FTIM2_NOR_TWP(0x1c) 290 FTIM2_NOR_TWP(0x1c)
291 #define CONFIG_SYS_NOR_FTIM3 0x0 291 #define CONFIG_SYS_NOR_FTIM3 0x0
292 292
293 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 293 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
294 #define CONFIG_SYS_FLASH_QUIET_TEST 294 #define CONFIG_SYS_FLASH_QUIET_TEST
295 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 295 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
296 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 296 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
297 297
298 #undef CONFIG_SYS_FLASH_CHECKSUM 298 #undef CONFIG_SYS_FLASH_CHECKSUM
299 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 299 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
300 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 300 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
301 301
302 /* CFI for NOR Flash */ 302 /* CFI for NOR Flash */
303 #define CONFIG_FLASH_CFI_DRIVER 303 #define CONFIG_FLASH_CFI_DRIVER
304 #define CONFIG_SYS_FLASH_CFI 304 #define CONFIG_SYS_FLASH_CFI
305 #define CONFIG_SYS_FLASH_EMPTY_INFO 305 #define CONFIG_SYS_FLASH_EMPTY_INFO
306 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 306 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
307 307
308 /* NAND Flash on IFC */ 308 /* NAND Flash on IFC */
309 #define CONFIG_SYS_NAND_BASE 0xff800000 309 #define CONFIG_SYS_NAND_BASE 0xff800000
310 #ifdef CONFIG_PHYS_64BIT 310 #ifdef CONFIG_PHYS_64BIT
311 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 311 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
312 #else 312 #else
313 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 313 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
314 #endif 314 #endif
315 315
316 #define CONFIG_MTD_DEVICE 316 #define CONFIG_MTD_DEVICE
317 #define CONFIG_MTD_PARTITION 317 #define CONFIG_MTD_PARTITION
318 #define CONFIG_CMD_MTDPARTS 318 #define CONFIG_CMD_MTDPARTS
319 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 319 #define MTDIDS_DEFAULT "nand0=ff800000.flash"
320 #define MTDPARTS_DEFAULT \ 320 #define MTDPARTS_DEFAULT \
321 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 321 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
322 322
323 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 323 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
324 | CSPR_PORT_SIZE_8 \ 324 | CSPR_PORT_SIZE_8 \
325 | CSPR_MSEL_NAND \ 325 | CSPR_MSEL_NAND \
326 | CSPR_V) 326 | CSPR_V)
327 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 327 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
328 328
329 #if defined(CONFIG_P1010RDB_PA) 329 #if defined(CONFIG_P1010RDB_PA)
330 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 330 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
331 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 331 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
332 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 332 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
333 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 333 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
334 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 334 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
335 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 335 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
336 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 336 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
337 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 337 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
338 338
339 #elif defined(CONFIG_P1010RDB_PB) 339 #elif defined(CONFIG_P1010RDB_PB)
340 #define CONFIG_SYS_NAND_ONFI_DETECTION 340 #define CONFIG_SYS_NAND_ONFI_DETECTION
341 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 341 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
342 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 342 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
343 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 343 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
344 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 344 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
345 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 345 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
346 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 346 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
347 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 347 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
348 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 348 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
349 #endif 349 #endif
350 350
351 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 351 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
352 #define CONFIG_SYS_MAX_NAND_DEVICE 1 352 #define CONFIG_SYS_MAX_NAND_DEVICE 1
353 #define CONFIG_MTD_NAND_VERIFY_WRITE 353 #define CONFIG_MTD_NAND_VERIFY_WRITE
354 #define CONFIG_CMD_NAND 354 #define CONFIG_CMD_NAND
355 355
356 #if defined(CONFIG_P1010RDB_PA) 356 #if defined(CONFIG_P1010RDB_PA)
357 /* NAND Flash Timing Params */ 357 /* NAND Flash Timing Params */
358 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 358 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
359 FTIM0_NAND_TWP(0x0C) | \ 359 FTIM0_NAND_TWP(0x0C) | \
360 FTIM0_NAND_TWCHT(0x04) | \ 360 FTIM0_NAND_TWCHT(0x04) | \
361 FTIM0_NAND_TWH(0x05) 361 FTIM0_NAND_TWH(0x05)
362 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 362 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
363 FTIM1_NAND_TWBE(0x1d) | \ 363 FTIM1_NAND_TWBE(0x1d) | \
364 FTIM1_NAND_TRR(0x07) | \ 364 FTIM1_NAND_TRR(0x07) | \
365 FTIM1_NAND_TRP(0x0c) 365 FTIM1_NAND_TRP(0x0c)
366 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 366 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
367 FTIM2_NAND_TREH(0x05) | \ 367 FTIM2_NAND_TREH(0x05) | \
368 FTIM2_NAND_TWHRE(0x0f) 368 FTIM2_NAND_TWHRE(0x0f)
369 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 369 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
370 370
371 #elif defined(CONFIG_P1010RDB_PB) 371 #elif defined(CONFIG_P1010RDB_PB)
372 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 372 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
373 /* ONFI NAND Flash mode0 Timing Params */ 373 /* ONFI NAND Flash mode0 Timing Params */
374 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 374 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
375 FTIM0_NAND_TWP(0x18) | \ 375 FTIM0_NAND_TWP(0x18) | \
376 FTIM0_NAND_TWCHT(0x07) | \ 376 FTIM0_NAND_TWCHT(0x07) | \
377 FTIM0_NAND_TWH(0x0a)) 377 FTIM0_NAND_TWH(0x0a))
378 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 378 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
379 FTIM1_NAND_TWBE(0x39) | \ 379 FTIM1_NAND_TWBE(0x39) | \
380 FTIM1_NAND_TRR(0x0e) | \ 380 FTIM1_NAND_TRR(0x0e) | \
381 FTIM1_NAND_TRP(0x18)) 381 FTIM1_NAND_TRP(0x18))
382 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 382 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
383 FTIM2_NAND_TREH(0x0a) | \ 383 FTIM2_NAND_TREH(0x0a) | \
384 FTIM2_NAND_TWHRE(0x1e)) 384 FTIM2_NAND_TWHRE(0x1e))
385 #define CONFIG_SYS_NAND_FTIM3 0x0 385 #define CONFIG_SYS_NAND_FTIM3 0x0
386 #endif 386 #endif
387 387
388 #define CONFIG_SYS_NAND_DDR_LAW 11 388 #define CONFIG_SYS_NAND_DDR_LAW 11
389 389
390 /* Set up IFC registers for boot location NOR/NAND */ 390 /* Set up IFC registers for boot location NOR/NAND */
391 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 391 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
392 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 392 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
393 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 393 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
394 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 394 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
395 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 395 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
396 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 396 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
397 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 397 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
398 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 398 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
399 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 399 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
400 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 400 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
401 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 401 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
402 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 402 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
403 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 403 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
404 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 404 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
405 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 405 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
406 #else 406 #else
407 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 407 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
408 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 408 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
409 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 409 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
410 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 410 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
411 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 411 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
412 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 412 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
413 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 413 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
414 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 414 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
415 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 415 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
416 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 416 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
417 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 417 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
418 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 418 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
419 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 419 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
420 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 420 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
421 #endif 421 #endif
422 422
423 /* CPLD on IFC */ 423 /* CPLD on IFC */
424 #define CONFIG_SYS_CPLD_BASE 0xffb00000 424 #define CONFIG_SYS_CPLD_BASE 0xffb00000
425 425
426 #ifdef CONFIG_PHYS_64BIT 426 #ifdef CONFIG_PHYS_64BIT
427 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 427 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
428 #else 428 #else
429 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 429 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
430 #endif 430 #endif
431 431
432 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 432 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
433 | CSPR_PORT_SIZE_8 \ 433 | CSPR_PORT_SIZE_8 \
434 | CSPR_MSEL_GPCM \ 434 | CSPR_MSEL_GPCM \
435 | CSPR_V) 435 | CSPR_V)
436 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 436 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
437 #define CONFIG_SYS_CSOR3 0x0 437 #define CONFIG_SYS_CSOR3 0x0
438 /* CPLD Timing parameters for IFC CS3 */ 438 /* CPLD Timing parameters for IFC CS3 */
439 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 439 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
440 FTIM0_GPCM_TEADC(0x0e) | \ 440 FTIM0_GPCM_TEADC(0x0e) | \
441 FTIM0_GPCM_TEAHC(0x0e)) 441 FTIM0_GPCM_TEAHC(0x0e))
442 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 442 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
443 FTIM1_GPCM_TRAD(0x1f)) 443 FTIM1_GPCM_TRAD(0x1f))
444 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 444 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
445 FTIM2_GPCM_TCH(0x0) | \ 445 FTIM2_GPCM_TCH(0x0) | \
446 FTIM2_GPCM_TWP(0x1f)) 446 FTIM2_GPCM_TWP(0x1f))
447 #define CONFIG_SYS_CS3_FTIM3 0x0 447 #define CONFIG_SYS_CS3_FTIM3 0x0
448 448
449 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 449 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
450 #define CONFIG_SYS_RAMBOOT 450 #define CONFIG_SYS_RAMBOOT
451 #define CONFIG_SYS_EXTRA_ENV_RELOC 451 #define CONFIG_SYS_EXTRA_ENV_RELOC
452 #else 452 #else
453 #undef CONFIG_SYS_RAMBOOT 453 #undef CONFIG_SYS_RAMBOOT
454 #endif 454 #endif
455 455
456 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 456 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
457 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)\ 457 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)\
458 && !defined(CONFIG_SECURE_BOOT) 458 && !defined(CONFIG_SECURE_BOOT)
459 #define CONFIG_A003399_NOR_WORKAROUND 459 #define CONFIG_A003399_NOR_WORKAROUND
460 #endif 460 #endif
461 #endif 461 #endif
462 462
463 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 463 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
464 #define CONFIG_BOARD_EARLY_INIT_R 464 #define CONFIG_BOARD_EARLY_INIT_R
465 465
466 #define CONFIG_SYS_INIT_RAM_LOCK 466 #define CONFIG_SYS_INIT_RAM_LOCK
467 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 467 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
468 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 468 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
469 469
470 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 470 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
471 - GENERATED_GBL_DATA_SIZE) 471 - GENERATED_GBL_DATA_SIZE)
472 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 472 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
473 473
474 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ 474 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
475 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 475 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
476 476
477 /* Serial Port */ 477 /* Serial Port */
478 #define CONFIG_CONS_INDEX 1 478 #define CONFIG_CONS_INDEX 1
479 #undef CONFIG_SERIAL_SOFTWARE_FIFO 479 #undef CONFIG_SERIAL_SOFTWARE_FIFO
480 #define CONFIG_SYS_NS16550 480 #define CONFIG_SYS_NS16550
481 #define CONFIG_SYS_NS16550_SERIAL 481 #define CONFIG_SYS_NS16550_SERIAL
482 #define CONFIG_SYS_NS16550_REG_SIZE 1 482 #define CONFIG_SYS_NS16550_REG_SIZE 1
483 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 483 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
484 #ifdef CONFIG_SPL_BUILD 484 #ifdef CONFIG_SPL_BUILD
485 #define CONFIG_NS16550_MIN_FUNCTIONS 485 #define CONFIG_NS16550_MIN_FUNCTIONS
486 #endif 486 #endif
487 487
488 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 488 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
489 489
490 #define CONFIG_SYS_BAUDRATE_TABLE \ 490 #define CONFIG_SYS_BAUDRATE_TABLE \
491 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 491 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
492 492
493 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 493 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
494 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 494 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
495 495
496 /* Use the HUSH parser */ 496 /* Use the HUSH parser */
497 #define CONFIG_SYS_HUSH_PARSER 497 #define CONFIG_SYS_HUSH_PARSER
498 498
499 /* 499 /*
500 * Pass open firmware flat tree 500 * Pass open firmware flat tree
501 */ 501 */
502 #define CONFIG_OF_LIBFDT 502 #define CONFIG_OF_LIBFDT
503 #define CONFIG_OF_BOARD_SETUP 503 #define CONFIG_OF_BOARD_SETUP
504 #define CONFIG_OF_STDOUT_VIA_ALIAS 504 #define CONFIG_OF_STDOUT_VIA_ALIAS
505 505
506 /* new uImage format support */ 506 /* new uImage format support */
507 #define CONFIG_FIT 507 #define CONFIG_FIT
508 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 508 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
509 509
510 /* I2C */ 510 /* I2C */
511 #define CONFIG_SYS_I2C 511 #define CONFIG_SYS_I2C
512 #define CONFIG_SYS_I2C_FSL 512 #define CONFIG_SYS_I2C_FSL
513 #define CONFIG_SYS_FSL_I2C_SPEED 400000 513 #define CONFIG_SYS_FSL_I2C_SPEED 400000
514 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 514 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
515 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 515 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
516 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 516 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
517 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 517 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
518 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 518 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
519 #define I2C_PCA9557_ADDR1 0x18 519 #define I2C_PCA9557_ADDR1 0x18
520 #define I2C_PCA9557_ADDR2 0x19 520 #define I2C_PCA9557_ADDR2 0x19
521 #define I2C_PCA9557_BUS_NUM 0 521 #define I2C_PCA9557_BUS_NUM 0
522 522
523 /* I2C EEPROM */ 523 /* I2C EEPROM */
524 #if defined(CONFIG_P1010RDB_PB) 524 #if defined(CONFIG_P1010RDB_PB)
525 #define CONFIG_ID_EEPROM 525 #define CONFIG_ID_EEPROM
526 #ifdef CONFIG_ID_EEPROM 526 #ifdef CONFIG_ID_EEPROM
527 #define CONFIG_SYS_I2C_EEPROM_NXID 527 #define CONFIG_SYS_I2C_EEPROM_NXID
528 #endif 528 #endif
529 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 529 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
530 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 530 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
531 #define CONFIG_SYS_EEPROM_BUS_NUM 0 531 #define CONFIG_SYS_EEPROM_BUS_NUM 0
532 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 532 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
533 #endif 533 #endif
534 /* enable read and write access to EEPROM */ 534 /* enable read and write access to EEPROM */
535 #define CONFIG_CMD_EEPROM 535 #define CONFIG_CMD_EEPROM
536 #define CONFIG_SYS_I2C_MULTI_EEPROMS 536 #define CONFIG_SYS_I2C_MULTI_EEPROMS
537 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 537 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
538 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 538 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
539 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 539 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
540 540
541 /* RTC */ 541 /* RTC */
542 #define CONFIG_RTC_PT7C4338 542 #define CONFIG_RTC_PT7C4338
543 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 543 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
544 544
545 #define CONFIG_CMD_I2C 545 #define CONFIG_CMD_I2C
546 546
547 /* 547 /*
548 * SPI interface will not be available in case of NAND boot SPI CS0 will be 548 * SPI interface will not be available in case of NAND boot SPI CS0 will be
549 * used for SLIC 549 * used for SLIC
550 */ 550 */
551 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 551 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
552 /* eSPI - Enhanced SPI */ 552 /* eSPI - Enhanced SPI */
553 #define CONFIG_FSL_ESPI 553 #define CONFIG_FSL_ESPI
554 #define CONFIG_SPI_FLASH 554 #define CONFIG_SPI_FLASH
555 #define CONFIG_SPI_FLASH_SPANSION 555 #define CONFIG_SPI_FLASH_SPANSION
556 #define CONFIG_CMD_SF 556 #define CONFIG_CMD_SF
557 #define CONFIG_SF_DEFAULT_SPEED 10000000 557 #define CONFIG_SF_DEFAULT_SPEED 10000000
558 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 558 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
559 #endif 559 #endif
560 560
561 #if defined(CONFIG_TSEC_ENET) 561 #if defined(CONFIG_TSEC_ENET)
562 #define CONFIG_MII /* MII PHY management */ 562 #define CONFIG_MII /* MII PHY management */
563 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 563 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
564 #define CONFIG_TSEC1 1 564 #define CONFIG_TSEC1 1
565 #define CONFIG_TSEC1_NAME "eTSEC1" 565 #define CONFIG_TSEC1_NAME "eTSEC1"
566 #define CONFIG_TSEC2 1 566 #define CONFIG_TSEC2 1
567 #define CONFIG_TSEC2_NAME "eTSEC2" 567 #define CONFIG_TSEC2_NAME "eTSEC2"
568 #define CONFIG_TSEC3 1 568 #define CONFIG_TSEC3 1
569 #define CONFIG_TSEC3_NAME "eTSEC3" 569 #define CONFIG_TSEC3_NAME "eTSEC3"
570 570
571 #define TSEC1_PHY_ADDR 1 571 #define TSEC1_PHY_ADDR 1
572 #define TSEC2_PHY_ADDR 0 572 #define TSEC2_PHY_ADDR 0
573 #define TSEC3_PHY_ADDR 2 573 #define TSEC3_PHY_ADDR 2
574 574
575 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 575 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
576 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 576 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
577 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 577 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
578 578
579 #define TSEC1_PHYIDX 0 579 #define TSEC1_PHYIDX 0
580 #define TSEC2_PHYIDX 0 580 #define TSEC2_PHYIDX 0
581 #define TSEC3_PHYIDX 0 581 #define TSEC3_PHYIDX 0
582 582
583 #define CONFIG_ETHPRIME "eTSEC1" 583 #define CONFIG_ETHPRIME "eTSEC1"
584 584
585 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 585 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
586 586
587 /* TBI PHY configuration for SGMII mode */ 587 /* TBI PHY configuration for SGMII mode */
588 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 588 #define CONFIG_TSEC_TBICR_SETTINGS ( \
589 TBICR_PHY_RESET \ 589 TBICR_PHY_RESET \
590 | TBICR_ANEG_ENABLE \ 590 | TBICR_ANEG_ENABLE \
591 | TBICR_FULL_DUPLEX \ 591 | TBICR_FULL_DUPLEX \
592 | TBICR_SPEED1_SET \ 592 | TBICR_SPEED1_SET \
593 ) 593 )
594 594
595 #endif /* CONFIG_TSEC_ENET */ 595 #endif /* CONFIG_TSEC_ENET */
596 596
597 597
598 /* SATA */ 598 /* SATA */
599 #define CONFIG_FSL_SATA 599 #define CONFIG_FSL_SATA
600 #define CONFIG_FSL_SATA_V2 600 #define CONFIG_FSL_SATA_V2
601 #define CONFIG_LIBATA 601 #define CONFIG_LIBATA
602 602
603 #ifdef CONFIG_FSL_SATA 603 #ifdef CONFIG_FSL_SATA
604 #define CONFIG_SYS_SATA_MAX_DEVICE 2 604 #define CONFIG_SYS_SATA_MAX_DEVICE 2
605 #define CONFIG_SATA1 605 #define CONFIG_SATA1
606 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 606 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
607 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 607 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
608 #define CONFIG_SATA2 608 #define CONFIG_SATA2
609 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 609 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
610 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 610 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
611 611
612 #define CONFIG_CMD_SATA 612 #define CONFIG_CMD_SATA
613 #define CONFIG_LBA48 613 #define CONFIG_LBA48
614 #endif /* #ifdef CONFIG_FSL_SATA */ 614 #endif /* #ifdef CONFIG_FSL_SATA */
615 615
616 #define CONFIG_MMC 616 #define CONFIG_MMC
617 #ifdef CONFIG_MMC 617 #ifdef CONFIG_MMC
618 #define CONFIG_CMD_MMC 618 #define CONFIG_CMD_MMC
619 #define CONFIG_DOS_PARTITION 619 #define CONFIG_DOS_PARTITION
620 #define CONFIG_FSL_ESDHC 620 #define CONFIG_FSL_ESDHC
621 #define CONFIG_GENERIC_MMC 621 #define CONFIG_GENERIC_MMC
622 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 622 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
623 #endif 623 #endif
624 624
625 #define CONFIG_HAS_FSL_DR_USB 625 #define CONFIG_HAS_FSL_DR_USB
626 626
627 #if defined(CONFIG_HAS_FSL_DR_USB) 627 #if defined(CONFIG_HAS_FSL_DR_USB)
628 #define CONFIG_USB_EHCI 628 #define CONFIG_USB_EHCI
629 629
630 #ifdef CONFIG_USB_EHCI 630 #ifdef CONFIG_USB_EHCI
631 #define CONFIG_CMD_USB 631 #define CONFIG_CMD_USB
632 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 632 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
633 #define CONFIG_USB_EHCI_FSL 633 #define CONFIG_USB_EHCI_FSL
634 #define CONFIG_USB_STORAGE 634 #define CONFIG_USB_STORAGE
635 #endif 635 #endif
636 #endif 636 #endif
637 637
638 /* 638 /*
639 * Environment 639 * Environment
640 */ 640 */
641 #if defined(CONFIG_RAMBOOT_SDCARD) 641 #if defined(CONFIG_RAMBOOT_SDCARD)
642 #define CONFIG_ENV_IS_IN_MMC 642 #define CONFIG_ENV_IS_IN_MMC
643 #define CONFIG_FSL_FIXED_MMC_LOCATION 643 #define CONFIG_FSL_FIXED_MMC_LOCATION
644 #define CONFIG_SYS_MMC_ENV_DEV 0 644 #define CONFIG_SYS_MMC_ENV_DEV 0
645 #define CONFIG_ENV_SIZE 0x2000 645 #define CONFIG_ENV_SIZE 0x2000
646 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 646 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
647 #define CONFIG_ENV_IS_IN_SPI_FLASH 647 #define CONFIG_ENV_IS_IN_SPI_FLASH
648 #define CONFIG_ENV_SPI_BUS 0 648 #define CONFIG_ENV_SPI_BUS 0
649 #define CONFIG_ENV_SPI_CS 0 649 #define CONFIG_ENV_SPI_CS 0
650 #define CONFIG_ENV_SPI_MAX_HZ 10000000 650 #define CONFIG_ENV_SPI_MAX_HZ 10000000
651 #define CONFIG_ENV_SPI_MODE 0 651 #define CONFIG_ENV_SPI_MODE 0
652 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 652 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
653 #define CONFIG_ENV_SECT_SIZE 0x10000 653 #define CONFIG_ENV_SECT_SIZE 0x10000
654 #define CONFIG_ENV_SIZE 0x2000 654 #define CONFIG_ENV_SIZE 0x2000
655 #elif defined(CONFIG_NAND) 655 #elif defined(CONFIG_NAND)
656 #define CONFIG_ENV_IS_IN_NAND 656 #define CONFIG_ENV_IS_IN_NAND
657 #if defined(CONFIG_P1010RDB_PA) 657 #if defined(CONFIG_P1010RDB_PA)
658 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 658 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
659 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 659 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
660 #elif defined(CONFIG_P1010RDB_PB) 660 #elif defined(CONFIG_P1010RDB_PB)
661 #define CONFIG_ENV_SIZE (16 * 1024) 661 #define CONFIG_ENV_SIZE (16 * 1024)
662 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 662 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
663 #endif 663 #endif
664 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 664 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
665 #elif defined(CONFIG_SYS_RAMBOOT) 665 #elif defined(CONFIG_SYS_RAMBOOT)
666 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 666 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
667 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 667 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
668 #define CONFIG_ENV_SIZE 0x2000 668 #define CONFIG_ENV_SIZE 0x2000
669 #else 669 #else
670 #define CONFIG_ENV_IS_IN_FLASH 670 #define CONFIG_ENV_IS_IN_FLASH
671 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 671 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
672 #define CONFIG_ENV_ADDR 0xfff80000 672 #define CONFIG_ENV_ADDR 0xfff80000
673 #else 673 #else
674 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 674 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
675 #endif 675 #endif
676 #define CONFIG_ENV_SIZE 0x2000 676 #define CONFIG_ENV_SIZE 0x2000
677 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 677 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
678 #endif 678 #endif
679 679
680 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 680 #define CONFIG_LOADS_ECHO /* echo on for serial download */
681 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 681 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
682 682
683 /* 683 /*
684 * Command line configuration. 684 * Command line configuration.
685 */ 685 */
686 #include <config_cmd_default.h> 686 #include <config_cmd_default.h>
687 687
688 #define CONFIG_CMD_DATE 688 #define CONFIG_CMD_DATE
689 #define CONFIG_CMD_ERRATA 689 #define CONFIG_CMD_ERRATA
690 #define CONFIG_CMD_ELF 690 #define CONFIG_CMD_ELF
691 #define CONFIG_CMD_IRQ 691 #define CONFIG_CMD_IRQ
692 #define CONFIG_CMD_MII 692 #define CONFIG_CMD_MII
693 #define CONFIG_CMD_PING 693 #define CONFIG_CMD_PING
694 #define CONFIG_CMD_SETEXPR 694 #define CONFIG_CMD_SETEXPR
695 #define CONFIG_CMD_REGINFO 695 #define CONFIG_CMD_REGINFO
696 696
697 #undef CONFIG_WATCHDOG /* watchdog disabled */ 697 #undef CONFIG_WATCHDOG /* watchdog disabled */
698 698
699 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 699 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
700 || defined(CONFIG_FSL_SATA) 700 || defined(CONFIG_FSL_SATA)
701 #define CONFIG_CMD_EXT2 701 #define CONFIG_CMD_EXT2
702 #define CONFIG_CMD_FAT 702 #define CONFIG_CMD_FAT
703 #define CONFIG_DOS_PARTITION 703 #define CONFIG_DOS_PARTITION
704 #endif 704 #endif
705 705
706 /* 706 /*
707 * Miscellaneous configurable options 707 * Miscellaneous configurable options
708 */ 708 */
709 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 709 #define CONFIG_SYS_LONGHELP /* undef to save memory */
710 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 710 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
711 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 711 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
712 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 712 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
713 713
714 #if defined(CONFIG_CMD_KGDB) 714 #if defined(CONFIG_CMD_KGDB)
715 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 715 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
716 #else 716 #else
717 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 717 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
718 #endif 718 #endif
719 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 719 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
720 /* Print Buffer Size */ 720 /* Print Buffer Size */
721 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 721 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
722 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 722 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
723 723
724 /* 724 /*
725 * Internal Definitions 725 * Internal Definitions
726 * 726 *
727 * Boot Flags 727 * Boot Flags
728 */ 728 */
729 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 729 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
730 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 730 #define BOOTFLAG_WARM 0x02 /* Software reboot */
731 731
732 /* 732 /*
733 * For booting Linux, the board info and command line data 733 * For booting Linux, the board info and command line data
734 * have to be in the first 64 MB of memory, since this is 734 * have to be in the first 64 MB of memory, since this is
735 * the maximum mapped by the Linux kernel during initialization. 735 * the maximum mapped by the Linux kernel during initialization.
736 */ 736 */
737 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 737 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
738 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 738 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
739 739
740 #if defined(CONFIG_CMD_KGDB) 740 #if defined(CONFIG_CMD_KGDB)
741 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 741 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
742 #endif 742 #endif
743 743
744 /* 744 /*
745 * Environment Configuration 745 * Environment Configuration
746 */ 746 */
747 747
748 #if defined(CONFIG_TSEC_ENET) 748 #if defined(CONFIG_TSEC_ENET)
749 #define CONFIG_HAS_ETH0 749 #define CONFIG_HAS_ETH0
750 #define CONFIG_HAS_ETH1 750 #define CONFIG_HAS_ETH1
751 #define CONFIG_HAS_ETH2 751 #define CONFIG_HAS_ETH2
752 #endif 752 #endif
753 753
754 #define CONFIG_ROOTPATH "/opt/nfsroot" 754 #define CONFIG_ROOTPATH "/opt/nfsroot"
755 #define CONFIG_BOOTFILE "uImage" 755 #define CONFIG_BOOTFILE "uImage"
756 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 756 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
757 757
758 /* default location for tftp and bootm */ 758 /* default location for tftp and bootm */
759 #define CONFIG_LOADADDR 1000000 759 #define CONFIG_LOADADDR 1000000
760 760
761 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 761 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
762 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 762 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
763 763
764 #define CONFIG_BAUDRATE 115200 764 #define CONFIG_BAUDRATE 115200
765 765
766 #define CONFIG_EXTRA_ENV_SETTINGS \ 766 #define CONFIG_EXTRA_ENV_SETTINGS \
767 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 767 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
768 "netdev=eth0\0" \ 768 "netdev=eth0\0" \
769 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 769 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
770 "loadaddr=1000000\0" \ 770 "loadaddr=1000000\0" \
771 "consoledev=ttyS0\0" \ 771 "consoledev=ttyS0\0" \
772 "ramdiskaddr=2000000\0" \ 772 "ramdiskaddr=2000000\0" \
773 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 773 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
774 "fdtaddr=c00000\0" \ 774 "fdtaddr=c00000\0" \
775 "fdtfile=p1010rdb.dtb\0" \ 775 "fdtfile=p1010rdb.dtb\0" \
776 "bdev=sda1\0" \ 776 "bdev=sda1\0" \
777 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 777 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
778 "othbootargs=ramdisk_size=600000\0" \ 778 "othbootargs=ramdisk_size=600000\0" \
779 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 779 "usbfatboot=setenv bootargs root=/dev/ram rw " \
780 "console=$consoledev,$baudrate $othbootargs; " \ 780 "console=$consoledev,$baudrate $othbootargs; " \
781 "usb start;" \ 781 "usb start;" \
782 "fatload usb 0:2 $loadaddr $bootfile;" \ 782 "fatload usb 0:2 $loadaddr $bootfile;" \
783 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 783 "fatload usb 0:2 $fdtaddr $fdtfile;" \
784 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 784 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
785 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 785 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
786 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 786 "usbext2boot=setenv bootargs root=/dev/ram rw " \
787 "console=$consoledev,$baudrate $othbootargs; " \ 787 "console=$consoledev,$baudrate $othbootargs; " \
788 "usb start;" \ 788 "usb start;" \
789 "ext2load usb 0:4 $loadaddr $bootfile;" \ 789 "ext2load usb 0:4 $loadaddr $bootfile;" \
790 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 790 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
791 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 791 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
792 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 792 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
793 CONFIG_BOOTMODE 793 CONFIG_BOOTMODE
794 794
795 #if defined(CONFIG_P1010RDB_PA) 795 #if defined(CONFIG_P1010RDB_PA)
796 #define CONFIG_BOOTMODE \ 796 #define CONFIG_BOOTMODE \
797 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 797 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
798 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 798 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
799 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 799 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
800 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 800 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
801 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 801 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
802 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 802 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
803 803
804 #elif defined(CONFIG_P1010RDB_PB) 804 #elif defined(CONFIG_P1010RDB_PB)
805 #define CONFIG_BOOTMODE \ 805 #define CONFIG_BOOTMODE \
806 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 806 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
807 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 807 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
808 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 808 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
809 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 809 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
810 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 810 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
811 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 811 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
812 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 812 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
813 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 813 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
814 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 814 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
815 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 815 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
816 #endif 816 #endif
817 817
818 #define CONFIG_RAMBOOTCOMMAND \ 818 #define CONFIG_RAMBOOTCOMMAND \
819 "setenv bootargs root=/dev/ram rw " \ 819 "setenv bootargs root=/dev/ram rw " \
820 "console=$consoledev,$baudrate $othbootargs; " \ 820 "console=$consoledev,$baudrate $othbootargs; " \
821 "tftp $ramdiskaddr $ramdiskfile;" \ 821 "tftp $ramdiskaddr $ramdiskfile;" \
822 "tftp $loadaddr $bootfile;" \ 822 "tftp $loadaddr $bootfile;" \
823 "tftp $fdtaddr $fdtfile;" \ 823 "tftp $fdtaddr $fdtfile;" \
824 "bootm $loadaddr $ramdiskaddr $fdtaddr" 824 "bootm $loadaddr $ramdiskaddr $fdtaddr"
825 825
826 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 826 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
827 827
828 #include <asm/fsl_secure_boot.h> 828 #include <asm/fsl_secure_boot.h>
829 829
830 #endif /* __CONFIG_H */ 830 #endif /* __CONFIG_H */
831 831
include/configs/P1022DS.h
1 /* 1 /*
2 * Copyright 2010-2012 Freescale Semiconductor, Inc. 2 * Copyright 2010-2012 Freescale Semiconductor, Inc.
3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com> 4 * Timur Tabi <timur@freescale.com>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #ifndef __CONFIG_H 9 #ifndef __CONFIG_H
10 #define __CONFIG_H 10 #define __CONFIG_H
11 11
12 #include "../board/freescale/common/ics307_clk.h" 12 #include "../board/freescale/common/ics307_clk.h"
13 13
14 #ifdef CONFIG_36BIT 14 #ifdef CONFIG_36BIT
15 #define CONFIG_PHYS_64BIT 15 #define CONFIG_PHYS_64BIT
16 #endif 16 #endif
17 17
18 #ifdef CONFIG_SDCARD 18 #ifdef CONFIG_SDCARD
19 #define CONFIG_SPL 19 #define CONFIG_SPL
20 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 20 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
21 #define CONFIG_SPL_ENV_SUPPORT 21 #define CONFIG_SPL_ENV_SUPPORT
22 #define CONFIG_SPL_SERIAL_SUPPORT 22 #define CONFIG_SPL_SERIAL_SUPPORT
23 #define CONFIG_SPL_MMC_SUPPORT 23 #define CONFIG_SPL_MMC_SUPPORT
24 #define CONFIG_SPL_MMC_MINIMAL 24 #define CONFIG_SPL_MMC_MINIMAL
25 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_FLUSH_IMAGE
26 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
27 #define CONFIG_SPL_LIBGENERIC_SUPPORT 27 #define CONFIG_SPL_LIBGENERIC_SUPPORT
28 #define CONFIG_SPL_LIBCOMMON_SUPPORT 28 #define CONFIG_SPL_LIBCOMMON_SUPPORT
29 #define CONFIG_SPL_I2C_SUPPORT 29 #define CONFIG_SPL_I2C_SUPPORT
30 #define CONFIG_FSL_LAW /* Use common FSL init code */ 30 #define CONFIG_FSL_LAW /* Use common FSL init code */
31 #define CONFIG_SYS_TEXT_BASE 0x11001000 31 #define CONFIG_SYS_TEXT_BASE 0x11001000
32 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 32 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
33 #define CONFIG_SPL_PAD_TO 0x18000 33 #define CONFIG_SPL_PAD_TO 0x18000
34 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 34 #define CONFIG_SPL_MAX_SIZE (96 * 1024)
35 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 35 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
36 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 36 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
37 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 37 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
38 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 38 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
40 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 40 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
41 #define CONFIG_SPL_MMC_BOOT 41 #define CONFIG_SPL_MMC_BOOT
42 #ifdef CONFIG_SPL_BUILD 42 #ifdef CONFIG_SPL_BUILD
43 #define CONFIG_SPL_COMMON_INIT_DDR 43 #define CONFIG_SPL_COMMON_INIT_DDR
44 #endif 44 #endif
45 #endif 45 #endif
46 46
47 #ifdef CONFIG_SPIFLASH 47 #ifdef CONFIG_SPIFLASH
48 #define CONFIG_SPL 48 #define CONFIG_SPL
49 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 49 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
50 #define CONFIG_SPL_ENV_SUPPORT 50 #define CONFIG_SPL_ENV_SUPPORT
51 #define CONFIG_SPL_SERIAL_SUPPORT 51 #define CONFIG_SPL_SERIAL_SUPPORT
52 #define CONFIG_SPL_SPI_SUPPORT 52 #define CONFIG_SPL_SPI_SUPPORT
53 #define CONFIG_SPL_SPI_FLASH_SUPPORT 53 #define CONFIG_SPL_SPI_FLASH_SUPPORT
54 #define CONFIG_SPL_SPI_FLASH_MINIMAL 54 #define CONFIG_SPL_SPI_FLASH_MINIMAL
55 #define CONFIG_SPL_FLUSH_IMAGE 55 #define CONFIG_SPL_FLUSH_IMAGE
56 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 56 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
57 #define CONFIG_SPL_LIBGENERIC_SUPPORT 57 #define CONFIG_SPL_LIBGENERIC_SUPPORT
58 #define CONFIG_SPL_LIBCOMMON_SUPPORT 58 #define CONFIG_SPL_LIBCOMMON_SUPPORT
59 #define CONFIG_SPL_I2C_SUPPORT 59 #define CONFIG_SPL_I2C_SUPPORT
60 #define CONFIG_FSL_LAW /* Use common FSL init code */ 60 #define CONFIG_FSL_LAW /* Use common FSL init code */
61 #define CONFIG_SYS_TEXT_BASE 0x11001000 61 #define CONFIG_SYS_TEXT_BASE 0x11001000
62 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 62 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
63 #define CONFIG_SPL_PAD_TO 0x18000 63 #define CONFIG_SPL_PAD_TO 0x18000
64 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 64 #define CONFIG_SPL_MAX_SIZE (96 * 1024)
65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
70 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 70 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
71 #define CONFIG_SPL_SPI_BOOT 71 #define CONFIG_SPL_SPI_BOOT
72 #ifdef CONFIG_SPL_BUILD 72 #ifdef CONFIG_SPL_BUILD
73 #define CONFIG_SPL_COMMON_INIT_DDR 73 #define CONFIG_SPL_COMMON_INIT_DDR
74 #endif 74 #endif
75 #endif 75 #endif
76 76
77 #define CONFIG_NAND_FSL_ELBC 77 #define CONFIG_NAND_FSL_ELBC
78 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
79 #define CONFIG_SYS_NAND_MAX_OOBFREE 5
78 80
79 #ifdef CONFIG_NAND 81 #ifdef CONFIG_NAND
80 #define CONFIG_SPL 82 #define CONFIG_SPL
81 #define CONFIG_TPL 83 #define CONFIG_TPL
82 #ifdef CONFIG_TPL_BUILD 84 #ifdef CONFIG_TPL_BUILD
83 #define CONFIG_SPL_NAND_BOOT 85 #define CONFIG_SPL_NAND_BOOT
84 #define CONFIG_SPL_FLUSH_IMAGE 86 #define CONFIG_SPL_FLUSH_IMAGE
85 #define CONFIG_SPL_ENV_SUPPORT 87 #define CONFIG_SPL_ENV_SUPPORT
86 #define CONFIG_SPL_NAND_INIT 88 #define CONFIG_SPL_NAND_INIT
87 #define CONFIG_SPL_SERIAL_SUPPORT 89 #define CONFIG_SPL_SERIAL_SUPPORT
88 #define CONFIG_SPL_LIBGENERIC_SUPPORT 90 #define CONFIG_SPL_LIBGENERIC_SUPPORT
89 #define CONFIG_SPL_LIBCOMMON_SUPPORT 91 #define CONFIG_SPL_LIBCOMMON_SUPPORT
90 #define CONFIG_SPL_I2C_SUPPORT 92 #define CONFIG_SPL_I2C_SUPPORT
91 #define CONFIG_SPL_NAND_SUPPORT 93 #define CONFIG_SPL_NAND_SUPPORT
92 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 94 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
93 #define CONFIG_SPL_COMMON_INIT_DDR 95 #define CONFIG_SPL_COMMON_INIT_DDR
94 #define CONFIG_SPL_MAX_SIZE (128 << 10) 96 #define CONFIG_SPL_MAX_SIZE (128 << 10)
95 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 97 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
96 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 98 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
97 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 99 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
98 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 100 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
99 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 101 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
100 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 102 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
101 #elif defined(CONFIG_SPL_BUILD) 103 #elif defined(CONFIG_SPL_BUILD)
102 #define CONFIG_SPL_INIT_MINIMAL 104 #define CONFIG_SPL_INIT_MINIMAL
103 #define CONFIG_SPL_SERIAL_SUPPORT 105 #define CONFIG_SPL_SERIAL_SUPPORT
104 #define CONFIG_SPL_NAND_SUPPORT 106 #define CONFIG_SPL_NAND_SUPPORT
105 #define CONFIG_SPL_FLUSH_IMAGE 107 #define CONFIG_SPL_FLUSH_IMAGE
106 #define CONFIG_SPL_TEXT_BASE 0xff800000 108 #define CONFIG_SPL_TEXT_BASE 0xff800000
107 #define CONFIG_SPL_MAX_SIZE 4096 109 #define CONFIG_SPL_MAX_SIZE 4096
108 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 110 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
109 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 111 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
110 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 112 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
111 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 113 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
112 #endif 114 #endif
113 #define CONFIG_SPL_PAD_TO 0x20000 115 #define CONFIG_SPL_PAD_TO 0x20000
114 #define CONFIG_TPL_PAD_TO 0x20000 116 #define CONFIG_TPL_PAD_TO 0x20000
115 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 117 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
116 #define CONFIG_SYS_TEXT_BASE 0x11001000 118 #define CONFIG_SYS_TEXT_BASE 0x11001000
117 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 119 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
118 #endif 120 #endif
119 121
120 /* High Level Configuration Options */ 122 /* High Level Configuration Options */
121 #define CONFIG_BOOKE /* BOOKE */ 123 #define CONFIG_BOOKE /* BOOKE */
122 #define CONFIG_E500 /* BOOKE e500 family */ 124 #define CONFIG_E500 /* BOOKE e500 family */
123 #define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ 125 #define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */
124 #define CONFIG_P1022 126 #define CONFIG_P1022
125 #define CONFIG_P1022DS 127 #define CONFIG_P1022DS
126 #define CONFIG_MP /* support multiple processors */ 128 #define CONFIG_MP /* support multiple processors */
127 129
128 #ifndef CONFIG_SYS_TEXT_BASE 130 #ifndef CONFIG_SYS_TEXT_BASE
129 #define CONFIG_SYS_TEXT_BASE 0xeff80000 131 #define CONFIG_SYS_TEXT_BASE 0xeff80000
130 #endif 132 #endif
131 133
132 #ifndef CONFIG_RESET_VECTOR_ADDRESS 134 #ifndef CONFIG_RESET_VECTOR_ADDRESS
133 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 135 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
134 #endif 136 #endif
135 137
136 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 138 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
137 #define CONFIG_PCI /* Enable PCI/PCIE */ 139 #define CONFIG_PCI /* Enable PCI/PCIE */
138 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 140 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
139 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 141 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
140 #define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */ 142 #define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
141 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 143 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
142 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 144 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
143 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 145 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
144 146
145 #define CONFIG_ENABLE_36BIT_PHYS 147 #define CONFIG_ENABLE_36BIT_PHYS
146 148
147 #ifdef CONFIG_PHYS_64BIT 149 #ifdef CONFIG_PHYS_64BIT
148 #define CONFIG_ADDR_MAP 150 #define CONFIG_ADDR_MAP
149 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 151 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
150 #endif 152 #endif
151 153
152 #define CONFIG_FSL_LAW /* Use common FSL init code */ 154 #define CONFIG_FSL_LAW /* Use common FSL init code */
153 155
154 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 156 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
155 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 157 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
156 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 158 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
157 159
158 /* 160 /*
159 * These can be toggled for performance analysis, otherwise use default. 161 * These can be toggled for performance analysis, otherwise use default.
160 */ 162 */
161 #define CONFIG_L2_CACHE 163 #define CONFIG_L2_CACHE
162 #define CONFIG_BTB 164 #define CONFIG_BTB
163 165
164 #define CONFIG_SYS_MEMTEST_START 0x00000000 166 #define CONFIG_SYS_MEMTEST_START 0x00000000
165 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 167 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
166 168
167 #define CONFIG_SYS_CCSRBAR 0xffe00000 169 #define CONFIG_SYS_CCSRBAR 0xffe00000
168 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 170 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
169 171
170 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 172 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
171 SPL code*/ 173 SPL code*/
172 #ifdef CONFIG_SPL_BUILD 174 #ifdef CONFIG_SPL_BUILD
173 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 175 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
174 #endif 176 #endif
175 177
176 178
177 /* DDR Setup */ 179 /* DDR Setup */
178 #define CONFIG_DDR_SPD 180 #define CONFIG_DDR_SPD
179 #define CONFIG_VERY_BIG_RAM 181 #define CONFIG_VERY_BIG_RAM
180 #define CONFIG_SYS_FSL_DDR3 182 #define CONFIG_SYS_FSL_DDR3
181 183
182 #ifdef CONFIG_DDR_ECC 184 #ifdef CONFIG_DDR_ECC
183 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 185 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
184 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 186 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
185 #endif 187 #endif
186 188
187 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 189 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
188 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 190 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
189 191
190 #define CONFIG_NUM_DDR_CONTROLLERS 1 192 #define CONFIG_NUM_DDR_CONTROLLERS 1
191 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 193 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
192 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 194 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
193 195
194 /* I2C addresses of SPD EEPROMs */ 196 /* I2C addresses of SPD EEPROMs */
195 #define CONFIG_SYS_SPD_BUS_NUM 1 197 #define CONFIG_SYS_SPD_BUS_NUM 1
196 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 198 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
197 199
198 /* These are used when DDR doesn't use SPD. */ 200 /* These are used when DDR doesn't use SPD. */
199 #define CONFIG_SYS_SDRAM_SIZE 2048 201 #define CONFIG_SYS_SDRAM_SIZE 2048
200 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 202 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
201 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 203 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
202 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 204 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
203 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F 205 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
204 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 206 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
205 #define CONFIG_SYS_DDR_TIMING_3 0x00010000 207 #define CONFIG_SYS_DDR_TIMING_3 0x00010000
206 #define CONFIG_SYS_DDR_TIMING_0 0x40110104 208 #define CONFIG_SYS_DDR_TIMING_0 0x40110104
207 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 209 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
208 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca 210 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
209 #define CONFIG_SYS_DDR_MODE_1 0x00441221 211 #define CONFIG_SYS_DDR_MODE_1 0x00441221
210 #define CONFIG_SYS_DDR_MODE_2 0x00000000 212 #define CONFIG_SYS_DDR_MODE_2 0x00000000
211 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 213 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100
212 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 214 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
213 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 215 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
214 #define CONFIG_SYS_DDR_CONTROL 0xc7000008 216 #define CONFIG_SYS_DDR_CONTROL 0xc7000008
215 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 217 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041
216 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 218 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
217 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 219 #define CONFIG_SYS_DDR_TIMING_5 0x02401400
218 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 220 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
219 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 221 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
220 222
221 223
222 /* 224 /*
223 * Memory map 225 * Memory map
224 * 226 *
225 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 227 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
226 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 228 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
227 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 229 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
228 * 230 *
229 * Localbus cacheable (TBD) 231 * Localbus cacheable (TBD)
230 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 232 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
231 * 233 *
232 * Localbus non-cacheable 234 * Localbus non-cacheable
233 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 235 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
234 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 236 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
235 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable 237 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
236 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 238 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
237 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 239 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
238 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 240 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
239 */ 241 */
240 242
241 /* 243 /*
242 * Local Bus Definitions 244 * Local Bus Definitions
243 */ 245 */
244 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ 246 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
245 #ifdef CONFIG_PHYS_64BIT 247 #ifdef CONFIG_PHYS_64BIT
246 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 248 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
247 #else 249 #else
248 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 250 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
249 #endif 251 #endif
250 252
251 #define CONFIG_FLASH_BR_PRELIM \ 253 #define CONFIG_FLASH_BR_PRELIM \
252 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 254 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
253 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 255 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
254 256
255 #ifdef CONFIG_NAND 257 #ifdef CONFIG_NAND
256 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 258 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
257 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 259 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
258 #else 260 #else
259 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 261 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
260 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 262 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
261 #endif 263 #endif
262 264
263 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 265 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
264 #define CONFIG_SYS_FLASH_QUIET_TEST 266 #define CONFIG_SYS_FLASH_QUIET_TEST
265 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 267 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
266 268
267 #define CONFIG_SYS_MAX_FLASH_BANKS 1 269 #define CONFIG_SYS_MAX_FLASH_BANKS 1
268 #define CONFIG_SYS_MAX_FLASH_SECT 1024 270 #define CONFIG_SYS_MAX_FLASH_SECT 1024
269 271
270 #ifndef CONFIG_SYS_MONITOR_BASE 272 #ifndef CONFIG_SYS_MONITOR_BASE
271 #ifdef CONFIG_SPL_BUILD 273 #ifdef CONFIG_SPL_BUILD
272 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 274 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
273 #else 275 #else
274 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 276 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
275 #endif 277 #endif
276 #endif 278 #endif
277 279
278 #define CONFIG_FLASH_CFI_DRIVER 280 #define CONFIG_FLASH_CFI_DRIVER
279 #define CONFIG_SYS_FLASH_CFI 281 #define CONFIG_SYS_FLASH_CFI
280 #define CONFIG_SYS_FLASH_EMPTY_INFO 282 #define CONFIG_SYS_FLASH_EMPTY_INFO
281 283
282 /* Nand Flash */ 284 /* Nand Flash */
283 #if defined(CONFIG_NAND_FSL_ELBC) 285 #if defined(CONFIG_NAND_FSL_ELBC)
284 #define CONFIG_SYS_NAND_BASE 0xff800000 286 #define CONFIG_SYS_NAND_BASE 0xff800000
285 #ifdef CONFIG_PHYS_64BIT 287 #ifdef CONFIG_PHYS_64BIT
286 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 288 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
287 #else 289 #else
288 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 290 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
289 #endif 291 #endif
290 292
291 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 293 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
292 #define CONFIG_SYS_MAX_NAND_DEVICE 1 294 #define CONFIG_SYS_MAX_NAND_DEVICE 1
293 #define CONFIG_MTD_NAND_VERIFY_WRITE 295 #define CONFIG_MTD_NAND_VERIFY_WRITE
294 #define CONFIG_CMD_NAND 1 296 #define CONFIG_CMD_NAND 1
295 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 297 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
296 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE 298 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
297 299
298 /* NAND flash config */ 300 /* NAND flash config */
299 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 301 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
300 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 302 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
301 | BR_PS_8 /* Port Size = 8 bit */ \ 303 | BR_PS_8 /* Port Size = 8 bit */ \
302 | BR_MS_FCM /* MSEL = FCM */ \ 304 | BR_MS_FCM /* MSEL = FCM */ \
303 | BR_V) /* valid */ 305 | BR_V) /* valid */
304 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ 306 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
305 | OR_FCM_PGS /* Large Page*/ \ 307 | OR_FCM_PGS /* Large Page*/ \
306 | OR_FCM_CSCT \ 308 | OR_FCM_CSCT \
307 | OR_FCM_CST \ 309 | OR_FCM_CST \
308 | OR_FCM_CHT \ 310 | OR_FCM_CHT \
309 | OR_FCM_SCY_1 \ 311 | OR_FCM_SCY_1 \
310 | OR_FCM_TRLX \ 312 | OR_FCM_TRLX \
311 | OR_FCM_EHTR) 313 | OR_FCM_EHTR)
312 #ifdef CONFIG_NAND 314 #ifdef CONFIG_NAND
313 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 315 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
314 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 316 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
315 #else 317 #else
316 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 318 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
317 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 319 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
318 #endif 320 #endif
319 321
320 #endif /* CONFIG_NAND_FSL_ELBC */ 322 #endif /* CONFIG_NAND_FSL_ELBC */
321 323
322 #define CONFIG_BOARD_EARLY_INIT_F 324 #define CONFIG_BOARD_EARLY_INIT_F
323 #define CONFIG_BOARD_EARLY_INIT_R 325 #define CONFIG_BOARD_EARLY_INIT_R
324 #define CONFIG_MISC_INIT_R 326 #define CONFIG_MISC_INIT_R
325 #define CONFIG_HWCONFIG 327 #define CONFIG_HWCONFIG
326 328
327 #define CONFIG_FSL_NGPIXIS 329 #define CONFIG_FSL_NGPIXIS
328 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 330 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
329 #ifdef CONFIG_PHYS_64BIT 331 #ifdef CONFIG_PHYS_64BIT
330 #define PIXIS_BASE_PHYS 0xfffdf0000ull 332 #define PIXIS_BASE_PHYS 0xfffdf0000ull
331 #else 333 #else
332 #define PIXIS_BASE_PHYS PIXIS_BASE 334 #define PIXIS_BASE_PHYS PIXIS_BASE
333 #endif 335 #endif
334 336
335 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 337 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
336 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 338 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
337 339
338 #define PIXIS_LBMAP_SWITCH 7 340 #define PIXIS_LBMAP_SWITCH 7
339 #define PIXIS_LBMAP_MASK 0xF0 341 #define PIXIS_LBMAP_MASK 0xF0
340 #define PIXIS_LBMAP_ALTBANK 0x20 342 #define PIXIS_LBMAP_ALTBANK 0x20
341 #define PIXIS_SPD 0x07 343 #define PIXIS_SPD 0x07
342 #define PIXIS_SPD_SYSCLK_MASK 0x07 344 #define PIXIS_SPD_SYSCLK_MASK 0x07
343 #define PIXIS_ELBC_SPI_MASK 0xc0 345 #define PIXIS_ELBC_SPI_MASK 0xc0
344 #define PIXIS_SPI 0x80 346 #define PIXIS_SPI 0x80
345 347
346 #define CONFIG_SYS_INIT_RAM_LOCK 348 #define CONFIG_SYS_INIT_RAM_LOCK
347 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 349 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
348 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 350 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
349 351
350 #define CONFIG_SYS_GBL_DATA_OFFSET \ 352 #define CONFIG_SYS_GBL_DATA_OFFSET \
351 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 353 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
352 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 354 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
353 355
354 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 356 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
355 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 357 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
356 358
357 /* 359 /*
358 * Config the L2 Cache as L2 SRAM 360 * Config the L2 Cache as L2 SRAM
359 */ 361 */
360 #if defined(CONFIG_SPL_BUILD) 362 #if defined(CONFIG_SPL_BUILD)
361 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 363 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
362 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 364 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
363 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 365 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
364 #define CONFIG_SYS_L2_SIZE (256 << 10) 366 #define CONFIG_SYS_L2_SIZE (256 << 10)
365 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 367 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
366 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 368 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
367 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 369 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
368 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 370 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
369 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 371 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
370 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 372 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
371 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 373 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
372 #elif defined(CONFIG_NAND) 374 #elif defined(CONFIG_NAND)
373 #ifdef CONFIG_TPL_BUILD 375 #ifdef CONFIG_TPL_BUILD
374 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 376 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
375 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 377 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
376 #define CONFIG_SYS_L2_SIZE (256 << 10) 378 #define CONFIG_SYS_L2_SIZE (256 << 10)
377 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 379 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
378 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 380 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
379 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 381 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
380 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 382 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
381 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 383 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
382 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 384 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
383 #else 385 #else
384 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 386 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
385 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 387 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
386 #define CONFIG_SYS_L2_SIZE (256 << 10) 388 #define CONFIG_SYS_L2_SIZE (256 << 10)
387 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 389 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
388 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 390 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
389 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 391 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
390 #endif 392 #endif
391 #endif 393 #endif
392 #endif 394 #endif
393 395
394 /* 396 /*
395 * Serial Port 397 * Serial Port
396 */ 398 */
397 #define CONFIG_CONS_INDEX 1 399 #define CONFIG_CONS_INDEX 1
398 #define CONFIG_SYS_NS16550 400 #define CONFIG_SYS_NS16550
399 #define CONFIG_SYS_NS16550_SERIAL 401 #define CONFIG_SYS_NS16550_SERIAL
400 #define CONFIG_SYS_NS16550_REG_SIZE 1 402 #define CONFIG_SYS_NS16550_REG_SIZE 1
401 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 403 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
402 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 404 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
403 #define CONFIG_NS16550_MIN_FUNCTIONS 405 #define CONFIG_NS16550_MIN_FUNCTIONS
404 #endif 406 #endif
405 407
406 #define CONFIG_SYS_BAUDRATE_TABLE \ 408 #define CONFIG_SYS_BAUDRATE_TABLE \
407 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 409 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
408 410
409 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 411 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
410 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 412 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
411 413
412 /* Use the HUSH parser */ 414 /* Use the HUSH parser */
413 #define CONFIG_SYS_HUSH_PARSER 415 #define CONFIG_SYS_HUSH_PARSER
414 416
415 /* Video */ 417 /* Video */
416 418
417 #ifdef CONFIG_FSL_DIU_FB 419 #ifdef CONFIG_FSL_DIU_FB
418 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 420 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
419 #define CONFIG_VIDEO 421 #define CONFIG_VIDEO
420 #define CONFIG_CMD_BMP 422 #define CONFIG_CMD_BMP
421 #define CONFIG_CFB_CONSOLE 423 #define CONFIG_CFB_CONSOLE
422 #define CONFIG_VIDEO_SW_CURSOR 424 #define CONFIG_VIDEO_SW_CURSOR
423 #define CONFIG_VGA_AS_SINGLE_DEVICE 425 #define CONFIG_VGA_AS_SINGLE_DEVICE
424 #define CONFIG_VIDEO_LOGO 426 #define CONFIG_VIDEO_LOGO
425 #define CONFIG_VIDEO_BMP_LOGO 427 #define CONFIG_VIDEO_BMP_LOGO
426 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 428 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
427 /* 429 /*
428 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 430 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
429 * disable empty flash sector detection, which is I/O-intensive. 431 * disable empty flash sector detection, which is I/O-intensive.
430 */ 432 */
431 #undef CONFIG_SYS_FLASH_EMPTY_INFO 433 #undef CONFIG_SYS_FLASH_EMPTY_INFO
432 #endif 434 #endif
433 435
434 #ifndef CONFIG_FSL_DIU_FB 436 #ifndef CONFIG_FSL_DIU_FB
435 #endif 437 #endif
436 438
437 #ifdef CONFIG_ATI 439 #ifdef CONFIG_ATI
438 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 440 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
439 #define CONFIG_VIDEO 441 #define CONFIG_VIDEO
440 #define CONFIG_BIOSEMU 442 #define CONFIG_BIOSEMU
441 #define CONFIG_VIDEO_SW_CURSOR 443 #define CONFIG_VIDEO_SW_CURSOR
442 #define CONFIG_ATI_RADEON_FB 444 #define CONFIG_ATI_RADEON_FB
443 #define CONFIG_VIDEO_LOGO 445 #define CONFIG_VIDEO_LOGO
444 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 446 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
445 #define CONFIG_CFB_CONSOLE 447 #define CONFIG_CFB_CONSOLE
446 #define CONFIG_VGA_AS_SINGLE_DEVICE 448 #define CONFIG_VGA_AS_SINGLE_DEVICE
447 #endif 449 #endif
448 450
449 /* 451 /*
450 * Pass open firmware flat tree 452 * Pass open firmware flat tree
451 */ 453 */
452 #define CONFIG_OF_LIBFDT 454 #define CONFIG_OF_LIBFDT
453 #define CONFIG_OF_BOARD_SETUP 455 #define CONFIG_OF_BOARD_SETUP
454 #define CONFIG_OF_STDOUT_VIA_ALIAS 456 #define CONFIG_OF_STDOUT_VIA_ALIAS
455 457
456 /* new uImage format support */ 458 /* new uImage format support */
457 #define CONFIG_FIT 459 #define CONFIG_FIT
458 #define CONFIG_FIT_VERBOSE 460 #define CONFIG_FIT_VERBOSE
459 461
460 /* I2C */ 462 /* I2C */
461 #define CONFIG_SYS_I2C 463 #define CONFIG_SYS_I2C
462 #define CONFIG_SYS_I2C_FSL 464 #define CONFIG_SYS_I2C_FSL
463 #define CONFIG_SYS_FSL_I2C_SPEED 400000 465 #define CONFIG_SYS_FSL_I2C_SPEED 400000
464 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 466 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
465 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 467 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
466 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 468 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
467 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 469 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
468 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 470 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
469 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 471 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
470 472
471 /* 473 /*
472 * I2C2 EEPROM 474 * I2C2 EEPROM
473 */ 475 */
474 #define CONFIG_ID_EEPROM 476 #define CONFIG_ID_EEPROM
475 #define CONFIG_SYS_I2C_EEPROM_NXID 477 #define CONFIG_SYS_I2C_EEPROM_NXID
476 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 478 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
477 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 479 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
478 #define CONFIG_SYS_EEPROM_BUS_NUM 1 480 #define CONFIG_SYS_EEPROM_BUS_NUM 1
479 481
480 /* 482 /*
481 * eSPI - Enhanced SPI 483 * eSPI - Enhanced SPI
482 */ 484 */
483 #define CONFIG_SPI_FLASH 485 #define CONFIG_SPI_FLASH
484 #define CONFIG_SPI_FLASH_SPANSION 486 #define CONFIG_SPI_FLASH_SPANSION
485 487
486 #define CONFIG_HARD_SPI 488 #define CONFIG_HARD_SPI
487 #define CONFIG_FSL_ESPI 489 #define CONFIG_FSL_ESPI
488 490
489 #define CONFIG_CMD_SF 491 #define CONFIG_CMD_SF
490 #define CONFIG_SF_DEFAULT_SPEED 10000000 492 #define CONFIG_SF_DEFAULT_SPEED 10000000
491 #define CONFIG_SF_DEFAULT_MODE 0 493 #define CONFIG_SF_DEFAULT_MODE 0
492 494
493 /* 495 /*
494 * General PCI 496 * General PCI
495 * Memory space is mapped 1-1, but I/O space must start from 0. 497 * Memory space is mapped 1-1, but I/O space must start from 0.
496 */ 498 */
497 499
498 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 500 /* controller 1, Slot 2, tgtid 1, Base address a000 */
499 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 501 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
500 #ifdef CONFIG_PHYS_64BIT 502 #ifdef CONFIG_PHYS_64BIT
501 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 503 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
502 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 504 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
503 #else 505 #else
504 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 506 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
505 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 507 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
506 #endif 508 #endif
507 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 509 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
508 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 510 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
509 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 511 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
510 #ifdef CONFIG_PHYS_64BIT 512 #ifdef CONFIG_PHYS_64BIT
511 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 513 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
512 #else 514 #else
513 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 515 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
514 #endif 516 #endif
515 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 517 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
516 518
517 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 519 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
518 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 520 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
519 #ifdef CONFIG_PHYS_64BIT 521 #ifdef CONFIG_PHYS_64BIT
520 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 522 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
521 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 523 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
522 #else 524 #else
523 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 525 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
524 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 526 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
525 #endif 527 #endif
526 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 528 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
527 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 529 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
528 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 530 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
529 #ifdef CONFIG_PHYS_64BIT 531 #ifdef CONFIG_PHYS_64BIT
530 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 532 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
531 #else 533 #else
532 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 534 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
533 #endif 535 #endif
534 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 536 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
535 537
536 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 538 /* controller 3, Slot 1, tgtid 3, Base address b000 */
537 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 539 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
538 #ifdef CONFIG_PHYS_64BIT 540 #ifdef CONFIG_PHYS_64BIT
539 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 541 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
540 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 542 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
541 #else 543 #else
542 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 544 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
543 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 545 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
544 #endif 546 #endif
545 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 547 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
546 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 548 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
547 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 549 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
548 #ifdef CONFIG_PHYS_64BIT 550 #ifdef CONFIG_PHYS_64BIT
549 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 551 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
550 #else 552 #else
551 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 553 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
552 #endif 554 #endif
553 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 555 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
554 556
555 #ifdef CONFIG_PCI 557 #ifdef CONFIG_PCI
556 #define CONFIG_PCI_INDIRECT_BRIDGE 558 #define CONFIG_PCI_INDIRECT_BRIDGE
557 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 559 #define CONFIG_PCI_PNP /* do pci plug-and-play */
558 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 560 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
559 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 561 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */
560 #endif 562 #endif
561 563
562 /* SATA */ 564 /* SATA */
563 #define CONFIG_LIBATA 565 #define CONFIG_LIBATA
564 #define CONFIG_FSL_SATA 566 #define CONFIG_FSL_SATA
565 #define CONFIG_FSL_SATA_V2 567 #define CONFIG_FSL_SATA_V2
566 568
567 #define CONFIG_SYS_SATA_MAX_DEVICE 2 569 #define CONFIG_SYS_SATA_MAX_DEVICE 2
568 #define CONFIG_SATA1 570 #define CONFIG_SATA1
569 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 571 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
570 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 572 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
571 #define CONFIG_SATA2 573 #define CONFIG_SATA2
572 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 574 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
573 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 575 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
574 576
575 #ifdef CONFIG_FSL_SATA 577 #ifdef CONFIG_FSL_SATA
576 #define CONFIG_LBA48 578 #define CONFIG_LBA48
577 #define CONFIG_CMD_SATA 579 #define CONFIG_CMD_SATA
578 #define CONFIG_DOS_PARTITION 580 #define CONFIG_DOS_PARTITION
579 #define CONFIG_CMD_EXT2 581 #define CONFIG_CMD_EXT2
580 #endif 582 #endif
581 583
582 #define CONFIG_MMC 584 #define CONFIG_MMC
583 #ifdef CONFIG_MMC 585 #ifdef CONFIG_MMC
584 #define CONFIG_CMD_MMC 586 #define CONFIG_CMD_MMC
585 #define CONFIG_FSL_ESDHC 587 #define CONFIG_FSL_ESDHC
586 #define CONFIG_GENERIC_MMC 588 #define CONFIG_GENERIC_MMC
587 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 589 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
588 #endif 590 #endif
589 591
590 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 592 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
591 #define CONFIG_CMD_EXT2 593 #define CONFIG_CMD_EXT2
592 #define CONFIG_CMD_FAT 594 #define CONFIG_CMD_FAT
593 #define CONFIG_DOS_PARTITION 595 #define CONFIG_DOS_PARTITION
594 #endif 596 #endif
595 597
596 #define CONFIG_TSEC_ENET 598 #define CONFIG_TSEC_ENET
597 #ifdef CONFIG_TSEC_ENET 599 #ifdef CONFIG_TSEC_ENET
598 600
599 #define CONFIG_TSECV2 601 #define CONFIG_TSECV2
600 602
601 #define CONFIG_MII /* MII PHY management */ 603 #define CONFIG_MII /* MII PHY management */
602 #define CONFIG_TSEC1 1 604 #define CONFIG_TSEC1 1
603 #define CONFIG_TSEC1_NAME "eTSEC1" 605 #define CONFIG_TSEC1_NAME "eTSEC1"
604 #define CONFIG_TSEC2 1 606 #define CONFIG_TSEC2 1
605 #define CONFIG_TSEC2_NAME "eTSEC2" 607 #define CONFIG_TSEC2_NAME "eTSEC2"
606 608
607 #define TSEC1_PHY_ADDR 1 609 #define TSEC1_PHY_ADDR 1
608 #define TSEC2_PHY_ADDR 2 610 #define TSEC2_PHY_ADDR 2
609 611
610 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 612 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
611 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 613 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
612 614
613 #define TSEC1_PHYIDX 0 615 #define TSEC1_PHYIDX 0
614 #define TSEC2_PHYIDX 0 616 #define TSEC2_PHYIDX 0
615 617
616 #define CONFIG_ETHPRIME "eTSEC1" 618 #define CONFIG_ETHPRIME "eTSEC1"
617 619
618 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 620 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
619 #endif 621 #endif
620 622
621 /* 623 /*
622 * Environment 624 * Environment
623 */ 625 */
624 #ifdef CONFIG_SPIFLASH 626 #ifdef CONFIG_SPIFLASH
625 #define CONFIG_ENV_IS_IN_SPI_FLASH 627 #define CONFIG_ENV_IS_IN_SPI_FLASH
626 #define CONFIG_ENV_SPI_BUS 0 628 #define CONFIG_ENV_SPI_BUS 0
627 #define CONFIG_ENV_SPI_CS 0 629 #define CONFIG_ENV_SPI_CS 0
628 #define CONFIG_ENV_SPI_MAX_HZ 10000000 630 #define CONFIG_ENV_SPI_MAX_HZ 10000000
629 #define CONFIG_ENV_SPI_MODE 0 631 #define CONFIG_ENV_SPI_MODE 0
630 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 632 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
631 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 633 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
632 #define CONFIG_ENV_SECT_SIZE 0x10000 634 #define CONFIG_ENV_SECT_SIZE 0x10000
633 #elif defined(CONFIG_SDCARD) 635 #elif defined(CONFIG_SDCARD)
634 #define CONFIG_ENV_IS_IN_MMC 636 #define CONFIG_ENV_IS_IN_MMC
635 #define CONFIG_FSL_FIXED_MMC_LOCATION 637 #define CONFIG_FSL_FIXED_MMC_LOCATION
636 #define CONFIG_ENV_SIZE 0x2000 638 #define CONFIG_ENV_SIZE 0x2000
637 #define CONFIG_SYS_MMC_ENV_DEV 0 639 #define CONFIG_SYS_MMC_ENV_DEV 0
638 #elif defined(CONFIG_NAND) 640 #elif defined(CONFIG_NAND)
639 #ifdef CONFIG_TPL_BUILD 641 #ifdef CONFIG_TPL_BUILD
640 #define CONFIG_ENV_SIZE 0x2000 642 #define CONFIG_ENV_SIZE 0x2000
641 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 643 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
642 #else 644 #else
643 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 645 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
644 #endif 646 #endif
645 #define CONFIG_ENV_IS_IN_NAND 647 #define CONFIG_ENV_IS_IN_NAND
646 #define CONFIG_ENV_OFFSET (1024 * 1024) 648 #define CONFIG_ENV_OFFSET (1024 * 1024)
647 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 649 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
648 #elif defined(CONFIG_SYS_RAMBOOT) 650 #elif defined(CONFIG_SYS_RAMBOOT)
649 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 651 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
650 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 652 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
651 #define CONFIG_ENV_SIZE 0x2000 653 #define CONFIG_ENV_SIZE 0x2000
652 #else 654 #else
653 #define CONFIG_ENV_IS_IN_FLASH 655 #define CONFIG_ENV_IS_IN_FLASH
654 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 656 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
655 #define CONFIG_ENV_ADDR 0xfff80000 657 #define CONFIG_ENV_ADDR 0xfff80000
656 #else 658 #else
657 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 659 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
658 #endif 660 #endif
659 #define CONFIG_ENV_SIZE 0x2000 661 #define CONFIG_ENV_SIZE 0x2000
660 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 662 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
661 #endif 663 #endif
662 664
663 #define CONFIG_LOADS_ECHO 665 #define CONFIG_LOADS_ECHO
664 #define CONFIG_SYS_LOADS_BAUD_CHANGE 666 #define CONFIG_SYS_LOADS_BAUD_CHANGE
665 667
666 /* 668 /*
667 * Command line configuration. 669 * Command line configuration.
668 */ 670 */
669 #include <config_cmd_default.h> 671 #include <config_cmd_default.h>
670 672
671 #define CONFIG_CMD_ELF 673 #define CONFIG_CMD_ELF
672 #define CONFIG_CMD_ERRATA 674 #define CONFIG_CMD_ERRATA
673 #define CONFIG_CMD_IRQ 675 #define CONFIG_CMD_IRQ
674 #define CONFIG_CMD_I2C 676 #define CONFIG_CMD_I2C
675 #define CONFIG_CMD_MII 677 #define CONFIG_CMD_MII
676 #define CONFIG_CMD_PING 678 #define CONFIG_CMD_PING
677 #define CONFIG_CMD_SETEXPR 679 #define CONFIG_CMD_SETEXPR
678 #define CONFIG_CMD_REGINFO 680 #define CONFIG_CMD_REGINFO
679 681
680 #ifdef CONFIG_PCI 682 #ifdef CONFIG_PCI
681 #define CONFIG_CMD_PCI 683 #define CONFIG_CMD_PCI
682 #define CONFIG_CMD_NET 684 #define CONFIG_CMD_NET
683 #endif 685 #endif
684 686
685 /* 687 /*
686 * USB 688 * USB
687 */ 689 */
688 #define CONFIG_HAS_FSL_DR_USB 690 #define CONFIG_HAS_FSL_DR_USB
689 #ifdef CONFIG_HAS_FSL_DR_USB 691 #ifdef CONFIG_HAS_FSL_DR_USB
690 #define CONFIG_USB_EHCI 692 #define CONFIG_USB_EHCI
691 693
692 #ifdef CONFIG_USB_EHCI 694 #ifdef CONFIG_USB_EHCI
693 #define CONFIG_CMD_USB 695 #define CONFIG_CMD_USB
694 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 696 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
695 #define CONFIG_USB_EHCI_FSL 697 #define CONFIG_USB_EHCI_FSL
696 #define CONFIG_USB_STORAGE 698 #define CONFIG_USB_STORAGE
697 #define CONFIG_CMD_FAT 699 #define CONFIG_CMD_FAT
698 #endif 700 #endif
699 #endif 701 #endif
700 702
701 /* 703 /*
702 * Miscellaneous configurable options 704 * Miscellaneous configurable options
703 */ 705 */
704 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 706 #define CONFIG_SYS_LONGHELP /* undef to save memory */
705 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 707 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
706 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 708 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
707 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 709 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
708 #ifdef CONFIG_CMD_KGDB 710 #ifdef CONFIG_CMD_KGDB
709 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 711 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
710 #else 712 #else
711 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 713 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
712 #endif 714 #endif
713 /* Print Buffer Size */ 715 /* Print Buffer Size */
714 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 716 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
715 #define CONFIG_SYS_MAXARGS 16 717 #define CONFIG_SYS_MAXARGS 16
716 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 718 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
717 719
718 /* 720 /*
719 * For booting Linux, the board info and command line data 721 * For booting Linux, the board info and command line data
720 * have to be in the first 64 MB of memory, since this is 722 * have to be in the first 64 MB of memory, since this is
721 * the maximum mapped by the Linux kernel during initialization. 723 * the maximum mapped by the Linux kernel during initialization.
722 */ 724 */
723 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 725 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
724 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 726 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
725 727
726 #ifdef CONFIG_CMD_KGDB 728 #ifdef CONFIG_CMD_KGDB
727 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 729 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
728 #endif 730 #endif
729 731
730 /* 732 /*
731 * Environment Configuration 733 * Environment Configuration
732 */ 734 */
733 735
734 #define CONFIG_HOSTNAME p1022ds 736 #define CONFIG_HOSTNAME p1022ds
735 #define CONFIG_ROOTPATH "/opt/nfsroot" 737 #define CONFIG_ROOTPATH "/opt/nfsroot"
736 #define CONFIG_BOOTFILE "uImage" 738 #define CONFIG_BOOTFILE "uImage"
737 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 739 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
738 740
739 #define CONFIG_LOADADDR 1000000 741 #define CONFIG_LOADADDR 1000000
740 742
741 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 743 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
742 744
743 #define CONFIG_BAUDRATE 115200 745 #define CONFIG_BAUDRATE 115200
744 746
745 #define CONFIG_EXTRA_ENV_SETTINGS \ 747 #define CONFIG_EXTRA_ENV_SETTINGS \
746 "netdev=eth0\0" \ 748 "netdev=eth0\0" \
747 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 749 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
748 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 750 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
749 "tftpflash=tftpboot $loadaddr $uboot && " \ 751 "tftpflash=tftpboot $loadaddr $uboot && " \
750 "protect off $ubootaddr +$filesize && " \ 752 "protect off $ubootaddr +$filesize && " \
751 "erase $ubootaddr +$filesize && " \ 753 "erase $ubootaddr +$filesize && " \
752 "cp.b $loadaddr $ubootaddr $filesize && " \ 754 "cp.b $loadaddr $ubootaddr $filesize && " \
753 "protect on $ubootaddr +$filesize && " \ 755 "protect on $ubootaddr +$filesize && " \
754 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 756 "cmp.b $loadaddr $ubootaddr $filesize\0" \
755 "consoledev=ttyS0\0" \ 757 "consoledev=ttyS0\0" \
756 "ramdiskaddr=2000000\0" \ 758 "ramdiskaddr=2000000\0" \
757 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 759 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
758 "fdtaddr=c00000\0" \ 760 "fdtaddr=c00000\0" \
759 "fdtfile=p1022ds.dtb\0" \ 761 "fdtfile=p1022ds.dtb\0" \
760 "bdev=sda3\0" \ 762 "bdev=sda3\0" \
761 "hwconfig=esdhc;audclk:12\0" 763 "hwconfig=esdhc;audclk:12\0"
762 764
763 #define CONFIG_HDBOOT \ 765 #define CONFIG_HDBOOT \
764 "setenv bootargs root=/dev/$bdev rw " \ 766 "setenv bootargs root=/dev/$bdev rw " \
765 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 767 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
766 "tftp $loadaddr $bootfile;" \ 768 "tftp $loadaddr $bootfile;" \
767 "tftp $fdtaddr $fdtfile;" \ 769 "tftp $fdtaddr $fdtfile;" \
768 "bootm $loadaddr - $fdtaddr" 770 "bootm $loadaddr - $fdtaddr"
769 771
770 #define CONFIG_NFSBOOTCOMMAND \ 772 #define CONFIG_NFSBOOTCOMMAND \
771 "setenv bootargs root=/dev/nfs rw " \ 773 "setenv bootargs root=/dev/nfs rw " \
772 "nfsroot=$serverip:$rootpath " \ 774 "nfsroot=$serverip:$rootpath " \
773 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 775 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
774 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 776 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
775 "tftp $loadaddr $bootfile;" \ 777 "tftp $loadaddr $bootfile;" \
776 "tftp $fdtaddr $fdtfile;" \ 778 "tftp $fdtaddr $fdtfile;" \
777 "bootm $loadaddr - $fdtaddr" 779 "bootm $loadaddr - $fdtaddr"
778 780
779 #define CONFIG_RAMBOOTCOMMAND \ 781 #define CONFIG_RAMBOOTCOMMAND \
780 "setenv bootargs root=/dev/ram rw " \ 782 "setenv bootargs root=/dev/ram rw " \
781 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 783 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
782 "tftp $ramdiskaddr $ramdiskfile;" \ 784 "tftp $ramdiskaddr $ramdiskfile;" \
783 "tftp $loadaddr $bootfile;" \ 785 "tftp $loadaddr $bootfile;" \
784 "tftp $fdtaddr $fdtfile;" \ 786 "tftp $fdtaddr $fdtfile;" \
785 "bootm $loadaddr $ramdiskaddr $fdtaddr" 787 "bootm $loadaddr $ramdiskaddr $fdtaddr"
786 788
787 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 789 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
788 790
789 #endif 791 #endif
790 792
include/configs/T1040QDS.h
1 /* 1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc. 2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * See file CREDITS for list of people who contributed to this 4 * See file CREDITS for list of people who contributed to this
5 * project. 5 * project.
6 * 6 *
7 * This program is free software; you can redistribute it and/or 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as 8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of 9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version. 10 * the License, or (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 * 16 *
17 * You should have received a copy of the GNU General Public License 17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA 20 * MA 02111-1307 USA
21 */ 21 */
22 22
23 #ifndef __CONFIG_H 23 #ifndef __CONFIG_H
24 #define __CONFIG_H 24 #define __CONFIG_H
25 25
26 /* 26 /*
27 * T1040 QDS board configuration file 27 * T1040 QDS board configuration file
28 */ 28 */
29 #define CONFIG_T1040QDS 29 #define CONFIG_T1040QDS
30 #define CONFIG_PHYS_64BIT 30 #define CONFIG_PHYS_64BIT
31 31
32 #ifdef CONFIG_RAMBOOT_PBL 32 #ifdef CONFIG_RAMBOOT_PBL
33 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 33 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
34 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
35 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg 35 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg
36 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg 36 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg
37 #endif 37 #endif
38 38
39 /* High Level Configuration Options */ 39 /* High Level Configuration Options */
40 #define CONFIG_BOOKE 40 #define CONFIG_BOOKE
41 #define CONFIG_E500 /* BOOKE e500 family */ 41 #define CONFIG_E500 /* BOOKE e500 family */
42 #define CONFIG_E500MC /* BOOKE e500mc family */ 42 #define CONFIG_E500MC /* BOOKE e500mc family */
43 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 43 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
44 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 44 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
45 #define CONFIG_MP /* support multiple processors */ 45 #define CONFIG_MP /* support multiple processors */
46 46
47 #ifndef CONFIG_SYS_TEXT_BASE 47 #ifndef CONFIG_SYS_TEXT_BASE
48 #define CONFIG_SYS_TEXT_BASE 0xeff80000 48 #define CONFIG_SYS_TEXT_BASE 0xeff80000
49 #endif 49 #endif
50 50
51 #ifndef CONFIG_RESET_VECTOR_ADDRESS 51 #ifndef CONFIG_RESET_VECTOR_ADDRESS
52 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 52 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
53 #endif 53 #endif
54 54
55 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 55 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
56 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 56 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
57 #define CONFIG_FSL_IFC /* Enable IFC Support */ 57 #define CONFIG_FSL_IFC /* Enable IFC Support */
58 #define CONFIG_PCI /* Enable PCI/PCIE */ 58 #define CONFIG_PCI /* Enable PCI/PCIE */
59 #define CONFIG_PCI_INDIRECT_BRIDGE 59 #define CONFIG_PCI_INDIRECT_BRIDGE
60 #define CONFIG_PCIE1 /* PCIE controler 1 */ 60 #define CONFIG_PCIE1 /* PCIE controler 1 */
61 #define CONFIG_PCIE2 /* PCIE controler 2 */ 61 #define CONFIG_PCIE2 /* PCIE controler 2 */
62 #define CONFIG_PCIE3 /* PCIE controler 3 */ 62 #define CONFIG_PCIE3 /* PCIE controler 3 */
63 #define CONFIG_PCIE4 /* PCIE controler 4 */ 63 #define CONFIG_PCIE4 /* PCIE controler 4 */
64 64
65 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 65 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
66 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 66 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
67 67
68 #define CONFIG_FSL_LAW /* Use common FSL init code */ 68 #define CONFIG_FSL_LAW /* Use common FSL init code */
69 69
70 #define CONFIG_ENV_OVERWRITE 70 #define CONFIG_ENV_OVERWRITE
71 71
72 #ifdef CONFIG_SYS_NO_FLASH 72 #ifdef CONFIG_SYS_NO_FLASH
73 #define CONFIG_ENV_IS_NOWHERE 73 #define CONFIG_ENV_IS_NOWHERE
74 #else 74 #else
75 #define CONFIG_FLASH_CFI_DRIVER 75 #define CONFIG_FLASH_CFI_DRIVER
76 #define CONFIG_SYS_FLASH_CFI 76 #define CONFIG_SYS_FLASH_CFI
77 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 77 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
78 #endif 78 #endif
79 79
80 #ifndef CONFIG_SYS_NO_FLASH 80 #ifndef CONFIG_SYS_NO_FLASH
81 #if defined(CONFIG_SPIFLASH) 81 #if defined(CONFIG_SPIFLASH)
82 #define CONFIG_SYS_EXTRA_ENV_RELOC 82 #define CONFIG_SYS_EXTRA_ENV_RELOC
83 #define CONFIG_ENV_IS_IN_SPI_FLASH 83 #define CONFIG_ENV_IS_IN_SPI_FLASH
84 #define CONFIG_ENV_SPI_BUS 0 84 #define CONFIG_ENV_SPI_BUS 0
85 #define CONFIG_ENV_SPI_CS 0 85 #define CONFIG_ENV_SPI_CS 0
86 #define CONFIG_ENV_SPI_MAX_HZ 10000000 86 #define CONFIG_ENV_SPI_MAX_HZ 10000000
87 #define CONFIG_ENV_SPI_MODE 0 87 #define CONFIG_ENV_SPI_MODE 0
88 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 88 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
89 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 89 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
90 #define CONFIG_ENV_SECT_SIZE 0x10000 90 #define CONFIG_ENV_SECT_SIZE 0x10000
91 #elif defined(CONFIG_SDCARD) 91 #elif defined(CONFIG_SDCARD)
92 #define CONFIG_SYS_EXTRA_ENV_RELOC 92 #define CONFIG_SYS_EXTRA_ENV_RELOC
93 #define CONFIG_ENV_IS_IN_MMC 93 #define CONFIG_ENV_IS_IN_MMC
94 #define CONFIG_SYS_MMC_ENV_DEV 0 94 #define CONFIG_SYS_MMC_ENV_DEV 0
95 #define CONFIG_ENV_SIZE 0x2000 95 #define CONFIG_ENV_SIZE 0x2000
96 #define CONFIG_ENV_OFFSET (512 * 1105) 96 #define CONFIG_ENV_OFFSET (512 * 1105)
97 #elif defined(CONFIG_NAND) 97 #elif defined(CONFIG_NAND)
98 #define CONFIG_SYS_EXTRA_ENV_RELOC 98 #define CONFIG_SYS_EXTRA_ENV_RELOC
99 #define CONFIG_ENV_IS_IN_NAND 99 #define CONFIG_ENV_IS_IN_NAND
100 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 100 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
101 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 101 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
102 #else 102 #else
103 #define CONFIG_ENV_IS_IN_FLASH 103 #define CONFIG_ENV_IS_IN_FLASH
104 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 104 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
105 #define CONFIG_ENV_SIZE 0x2000 105 #define CONFIG_ENV_SIZE 0x2000
106 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 106 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
107 #endif 107 #endif
108 #else /* CONFIG_SYS_NO_FLASH */ 108 #else /* CONFIG_SYS_NO_FLASH */
109 #define CONFIG_ENV_SIZE 0x2000 109 #define CONFIG_ENV_SIZE 0x2000
110 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 110 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
111 #endif 111 #endif
112 112
113 #ifndef __ASSEMBLY__ 113 #ifndef __ASSEMBLY__
114 unsigned long get_board_sys_clk(void); 114 unsigned long get_board_sys_clk(void);
115 unsigned long get_board_ddr_clk(void); 115 unsigned long get_board_ddr_clk(void);
116 #endif 116 #endif
117 117
118 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 118 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
119 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 119 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
120 120
121 /* 121 /*
122 * These can be toggled for performance analysis, otherwise use default. 122 * These can be toggled for performance analysis, otherwise use default.
123 */ 123 */
124 #define CONFIG_SYS_CACHE_STASHING 124 #define CONFIG_SYS_CACHE_STASHING
125 #define CONFIG_BACKSIDE_L2_CACHE 125 #define CONFIG_BACKSIDE_L2_CACHE
126 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 126 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
127 #define CONFIG_BTB /* toggle branch predition */ 127 #define CONFIG_BTB /* toggle branch predition */
128 #define CONFIG_DDR_ECC 128 #define CONFIG_DDR_ECC
129 #ifdef CONFIG_DDR_ECC 129 #ifdef CONFIG_DDR_ECC
130 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 130 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
131 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 131 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
132 #endif 132 #endif
133 133
134 #define CONFIG_ENABLE_36BIT_PHYS 134 #define CONFIG_ENABLE_36BIT_PHYS
135 135
136 #define CONFIG_ADDR_MAP 136 #define CONFIG_ADDR_MAP
137 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 137 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
138 138
139 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 139 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
140 #define CONFIG_SYS_MEMTEST_END 0x00400000 140 #define CONFIG_SYS_MEMTEST_END 0x00400000
141 #define CONFIG_SYS_ALT_MEMTEST 141 #define CONFIG_SYS_ALT_MEMTEST
142 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 142 #define CONFIG_PANIC_HANG /* do not reset board on panic */
143 143
144 /* 144 /*
145 * Config the L3 Cache as L3 SRAM 145 * Config the L3 Cache as L3 SRAM
146 */ 146 */
147 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 147 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
148 148
149 #define CONFIG_SYS_DCSRBAR 0xf0000000 149 #define CONFIG_SYS_DCSRBAR 0xf0000000
150 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 150 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
151 151
152 /* EEPROM */ 152 /* EEPROM */
153 #define CONFIG_ID_EEPROM 153 #define CONFIG_ID_EEPROM
154 #define CONFIG_SYS_I2C_EEPROM_NXID 154 #define CONFIG_SYS_I2C_EEPROM_NXID
155 #define CONFIG_SYS_EEPROM_BUS_NUM 0 155 #define CONFIG_SYS_EEPROM_BUS_NUM 0
156 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 156 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
157 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 157 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
158 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 158 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
159 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 159 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
160 160
161 /* 161 /*
162 * DDR Setup 162 * DDR Setup
163 */ 163 */
164 #define CONFIG_VERY_BIG_RAM 164 #define CONFIG_VERY_BIG_RAM
165 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 165 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
166 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 166 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
167 167
168 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 168 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
169 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 169 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
170 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 170 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
171 171
172 #define CONFIG_DDR_SPD 172 #define CONFIG_DDR_SPD
173 #define CONFIG_SYS_FSL_DDR3 173 #define CONFIG_SYS_FSL_DDR3
174 #define CONFIG_FSL_DDR_INTERACTIVE 174 #define CONFIG_FSL_DDR_INTERACTIVE
175 175
176 #define CONFIG_SYS_SPD_BUS_NUM 0 176 #define CONFIG_SYS_SPD_BUS_NUM 0
177 #define SPD_EEPROM_ADDRESS 0x51 177 #define SPD_EEPROM_ADDRESS 0x51
178 178
179 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 179 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
180 180
181 /* 181 /*
182 * IFC Definitions 182 * IFC Definitions
183 */ 183 */
184 #define CONFIG_SYS_FLASH_BASE 0xe0000000 184 #define CONFIG_SYS_FLASH_BASE 0xe0000000
185 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 185 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
186 186
187 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 187 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
188 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 188 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
189 + 0x8000000) | \ 189 + 0x8000000) | \
190 CSPR_PORT_SIZE_16 | \ 190 CSPR_PORT_SIZE_16 | \
191 CSPR_MSEL_NOR | \ 191 CSPR_MSEL_NOR | \
192 CSPR_V) 192 CSPR_V)
193 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 193 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
194 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 194 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
195 CSPR_PORT_SIZE_16 | \ 195 CSPR_PORT_SIZE_16 | \
196 CSPR_MSEL_NOR | \ 196 CSPR_MSEL_NOR | \
197 CSPR_V) 197 CSPR_V)
198 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 198 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
199 /* NOR Flash Timing Params */ 199 /* NOR Flash Timing Params */
200 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 200 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
201 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 201 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
202 FTIM0_NOR_TEADC(0x5) | \ 202 FTIM0_NOR_TEADC(0x5) | \
203 FTIM0_NOR_TEAHC(0x5)) 203 FTIM0_NOR_TEAHC(0x5))
204 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 204 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
205 FTIM1_NOR_TRAD_NOR(0x1A) |\ 205 FTIM1_NOR_TRAD_NOR(0x1A) |\
206 FTIM1_NOR_TSEQRAD_NOR(0x13)) 206 FTIM1_NOR_TSEQRAD_NOR(0x13))
207 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 207 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
208 FTIM2_NOR_TCH(0x4) | \ 208 FTIM2_NOR_TCH(0x4) | \
209 FTIM2_NOR_TWPH(0x0E) | \ 209 FTIM2_NOR_TWPH(0x0E) | \
210 FTIM2_NOR_TWP(0x1c)) 210 FTIM2_NOR_TWP(0x1c))
211 #define CONFIG_SYS_NOR_FTIM3 0x0 211 #define CONFIG_SYS_NOR_FTIM3 0x0
212 212
213 #define CONFIG_SYS_FLASH_QUIET_TEST 213 #define CONFIG_SYS_FLASH_QUIET_TEST
214 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 214 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
215 215
216 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 216 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
217 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 217 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
218 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 218 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
219 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 219 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
220 220
221 #define CONFIG_SYS_FLASH_EMPTY_INFO 221 #define CONFIG_SYS_FLASH_EMPTY_INFO
222 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 222 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
223 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 223 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
224 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 224 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
225 #define QIXIS_BASE 0xffdf0000 225 #define QIXIS_BASE 0xffdf0000
226 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 226 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
227 #define QIXIS_LBMAP_SWITCH 0x06 227 #define QIXIS_LBMAP_SWITCH 0x06
228 #define QIXIS_LBMAP_MASK 0x0f 228 #define QIXIS_LBMAP_MASK 0x0f
229 #define QIXIS_LBMAP_SHIFT 0 229 #define QIXIS_LBMAP_SHIFT 0
230 #define QIXIS_LBMAP_DFLTBANK 0x00 230 #define QIXIS_LBMAP_DFLTBANK 0x00
231 #define QIXIS_LBMAP_ALTBANK 0x04 231 #define QIXIS_LBMAP_ALTBANK 0x04
232 #define QIXIS_RST_CTL_RESET 0x31 232 #define QIXIS_RST_CTL_RESET 0x31
233 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 233 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
234 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 234 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
235 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 235 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
236 #define QIXIS_RST_FORCE_MEM 0x01
236 237
237 #define CONFIG_SYS_CSPR3_EXT (0xf) 238 #define CONFIG_SYS_CSPR3_EXT (0xf)
238 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 239 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
239 | CSPR_PORT_SIZE_8 \ 240 | CSPR_PORT_SIZE_8 \
240 | CSPR_MSEL_GPCM \ 241 | CSPR_MSEL_GPCM \
241 | CSPR_V) 242 | CSPR_V)
242 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 243 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
243 #define CONFIG_SYS_CSOR3 0x0 244 #define CONFIG_SYS_CSOR3 0x0
244 /* QIXIS Timing parameters for IFC CS3 */ 245 /* QIXIS Timing parameters for IFC CS3 */
245 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 246 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
246 FTIM0_GPCM_TEADC(0x0e) | \ 247 FTIM0_GPCM_TEADC(0x0e) | \
247 FTIM0_GPCM_TEAHC(0x0e)) 248 FTIM0_GPCM_TEAHC(0x0e))
248 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 249 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
249 FTIM1_GPCM_TRAD(0x3f)) 250 FTIM1_GPCM_TRAD(0x3f))
250 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 251 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
251 FTIM2_GPCM_TCH(0x0) | \ 252 FTIM2_GPCM_TCH(0x8) | \
252 FTIM2_GPCM_TWP(0x1f)) 253 FTIM2_GPCM_TWP(0x1f))
253 #define CONFIG_SYS_CS3_FTIM3 0x0 254 #define CONFIG_SYS_CS3_FTIM3 0x0
254 255
255 #define CONFIG_NAND_FSL_IFC 256 #define CONFIG_NAND_FSL_IFC
256 #define CONFIG_SYS_NAND_BASE 0xff800000 257 #define CONFIG_SYS_NAND_BASE 0xff800000
257 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 258 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
258 259
259 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 260 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
260 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 261 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
261 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 262 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
262 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 263 | CSPR_MSEL_NAND /* MSEL = NAND */ \
263 | CSPR_V) 264 | CSPR_V)
264 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 265 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
265 266
266 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 267 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
267 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 268 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
268 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 269 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
269 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 270 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
270 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 271 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
271 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 272 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
272 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 273 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
273 274
274 #define CONFIG_SYS_NAND_ONFI_DETECTION 275 #define CONFIG_SYS_NAND_ONFI_DETECTION
275 276
276 /* ONFI NAND Flash mode0 Timing Params */ 277 /* ONFI NAND Flash mode0 Timing Params */
277 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 278 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
278 FTIM0_NAND_TWP(0x18) | \ 279 FTIM0_NAND_TWP(0x18) | \
279 FTIM0_NAND_TWCHT(0x07) | \ 280 FTIM0_NAND_TWCHT(0x07) | \
280 FTIM0_NAND_TWH(0x0a)) 281 FTIM0_NAND_TWH(0x0a))
281 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 282 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
282 FTIM1_NAND_TWBE(0x39) | \ 283 FTIM1_NAND_TWBE(0x39) | \
283 FTIM1_NAND_TRR(0x0e) | \ 284 FTIM1_NAND_TRR(0x0e) | \
284 FTIM1_NAND_TRP(0x18)) 285 FTIM1_NAND_TRP(0x18))
285 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 286 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
286 FTIM2_NAND_TREH(0x0a) | \ 287 FTIM2_NAND_TREH(0x0a) | \
287 FTIM2_NAND_TWHRE(0x1e)) 288 FTIM2_NAND_TWHRE(0x1e))
288 #define CONFIG_SYS_NAND_FTIM3 0x0 289 #define CONFIG_SYS_NAND_FTIM3 0x0
289 290
290 #define CONFIG_SYS_NAND_DDR_LAW 11 291 #define CONFIG_SYS_NAND_DDR_LAW 11
291 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 292 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
292 #define CONFIG_SYS_MAX_NAND_DEVICE 1 293 #define CONFIG_SYS_MAX_NAND_DEVICE 1
293 #define CONFIG_MTD_NAND_VERIFY_WRITE 294 #define CONFIG_MTD_NAND_VERIFY_WRITE
294 #define CONFIG_CMD_NAND 295 #define CONFIG_CMD_NAND
295 296
296 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 297 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
297 298
298 #if defined(CONFIG_NAND) 299 #if defined(CONFIG_NAND)
299 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 300 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
300 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 301 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
301 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 302 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
302 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 303 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
303 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 304 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
304 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 305 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
305 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 306 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
306 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 307 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
307 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 308 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
308 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 309 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
309 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 310 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
310 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 311 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
311 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 312 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
312 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 313 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
313 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 314 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
314 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 315 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
315 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 316 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
316 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 317 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
317 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 318 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
318 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 319 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
319 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 320 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
320 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 321 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
321 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 322 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
322 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 323 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
323 #else 324 #else
324 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 325 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
325 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 326 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
326 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 327 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
327 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 328 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
328 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 329 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
329 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 330 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
330 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 331 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
331 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 332 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
332 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 333 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
333 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 334 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
334 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 335 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
335 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 336 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
336 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 337 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
337 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 338 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
338 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 339 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
339 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 340 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
340 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 341 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
341 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 342 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
342 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 343 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
343 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 344 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
344 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 345 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
345 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 346 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
346 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 347 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
347 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 348 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
348 #endif 349 #endif
349 350
350 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 351 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
351 352
352 #if defined(CONFIG_RAMBOOT_PBL) 353 #if defined(CONFIG_RAMBOOT_PBL)
353 #define CONFIG_SYS_RAMBOOT 354 #define CONFIG_SYS_RAMBOOT
354 #endif 355 #endif
355 356
356 #define CONFIG_BOARD_EARLY_INIT_R 357 #define CONFIG_BOARD_EARLY_INIT_R
357 #define CONFIG_MISC_INIT_R 358 #define CONFIG_MISC_INIT_R
358 359
359 #define CONFIG_HWCONFIG 360 #define CONFIG_HWCONFIG
360 361
361 /* define to use L1 as initial stack */ 362 /* define to use L1 as initial stack */
362 #define CONFIG_L1_INIT_RAM 363 #define CONFIG_L1_INIT_RAM
363 #define CONFIG_SYS_INIT_RAM_LOCK 364 #define CONFIG_SYS_INIT_RAM_LOCK
364 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 365 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
365 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 366 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
366 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 367 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
367 /* The assembler doesn't like typecast */ 368 /* The assembler doesn't like typecast */
368 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 369 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
369 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 370 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
370 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 371 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
371 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 372 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
372 373
373 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 374 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
374 GENERATED_GBL_DATA_SIZE) 375 GENERATED_GBL_DATA_SIZE)
375 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 376 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
376 377
377 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 378 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
378 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 379 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
379 380
380 /* Serial Port - controlled on board with jumper J8 381 /* Serial Port - controlled on board with jumper J8
381 * open - index 2 382 * open - index 2
382 * shorted - index 1 383 * shorted - index 1
383 */ 384 */
384 #define CONFIG_CONS_INDEX 1 385 #define CONFIG_CONS_INDEX 1
385 #define CONFIG_SYS_NS16550 386 #define CONFIG_SYS_NS16550
386 #define CONFIG_SYS_NS16550_SERIAL 387 #define CONFIG_SYS_NS16550_SERIAL
387 #define CONFIG_SYS_NS16550_REG_SIZE 1 388 #define CONFIG_SYS_NS16550_REG_SIZE 1
388 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 389 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
389 390
390 #define CONFIG_SYS_BAUDRATE_TABLE \ 391 #define CONFIG_SYS_BAUDRATE_TABLE \
391 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 392 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
392 393
393 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 394 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
394 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 395 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
395 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 396 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
396 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 397 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
397 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 398 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */
398 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 399 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
399 400
400 /* Use the HUSH parser */ 401 /* Use the HUSH parser */
401 #define CONFIG_SYS_HUSH_PARSER 402 #define CONFIG_SYS_HUSH_PARSER
402 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 403 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
403 404
404 /* pass open firmware flat tree */ 405 /* pass open firmware flat tree */
405 #define CONFIG_OF_LIBFDT 406 #define CONFIG_OF_LIBFDT
406 #define CONFIG_OF_BOARD_SETUP 407 #define CONFIG_OF_BOARD_SETUP
407 #define CONFIG_OF_STDOUT_VIA_ALIAS 408 #define CONFIG_OF_STDOUT_VIA_ALIAS
408 409
409 /* new uImage format support */ 410 /* new uImage format support */
410 #define CONFIG_FIT 411 #define CONFIG_FIT
411 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 412 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
412 413
413 /* I2C */ 414 /* I2C */
414 #define CONFIG_SYS_I2C 415 #define CONFIG_SYS_I2C
415 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 416 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
416 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 417 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
417 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 418 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
418 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 419 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
419 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 420 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
420 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 421 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
421 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 422 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
422 423
423 #define I2C_MUX_PCA_ADDR 0x77 424 #define I2C_MUX_PCA_ADDR 0x77
424 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 425 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
425 426
426 427
427 /* I2C bus multiplexer */ 428 /* I2C bus multiplexer */
428 #define I2C_MUX_CH_DEFAULT 0x8 429 #define I2C_MUX_CH_DEFAULT 0x8
429 430
430 /* 431 /*
431 * RTC configuration 432 * RTC configuration
432 */ 433 */
433 #define RTC 434 #define RTC
434 #define CONFIG_RTC_DS3231 1 435 #define CONFIG_RTC_DS3231 1
435 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 436 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
436 437
437 /* 438 /*
438 * eSPI - Enhanced SPI 439 * eSPI - Enhanced SPI
439 */ 440 */
440 #define CONFIG_FSL_ESPI 441 #define CONFIG_FSL_ESPI
441 #define CONFIG_SPI_FLASH 442 #define CONFIG_SPI_FLASH
442 #define CONFIG_SPI_FLASH_STMICRO 443 #define CONFIG_SPI_FLASH_STMICRO
443 #define CONFIG_SPI_FLASH_SST 444 #define CONFIG_SPI_FLASH_SST
444 #define CONFIG_SPI_FLASH_EON 445 #define CONFIG_SPI_FLASH_EON
445 #define CONFIG_CMD_SF 446 #define CONFIG_CMD_SF
446 #define CONFIG_SF_DEFAULT_SPEED 10000000 447 #define CONFIG_SF_DEFAULT_SPEED 10000000
447 #define CONFIG_SF_DEFAULT_MODE 0 448 #define CONFIG_SF_DEFAULT_MODE 0
448 449
449 /* 450 /*
450 * General PCI 451 * General PCI
451 * Memory space is mapped 1-1, but I/O space must start from 0. 452 * Memory space is mapped 1-1, but I/O space must start from 0.
452 */ 453 */
453 454
454 #ifdef CONFIG_PCI 455 #ifdef CONFIG_PCI
455 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 456 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
456 #ifdef CONFIG_PCIE1 457 #ifdef CONFIG_PCIE1
457 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 458 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
458 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 459 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
459 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 460 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
460 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 461 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
461 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 462 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
462 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 463 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
463 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 464 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
464 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 465 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
465 #endif 466 #endif
466 467
467 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 468 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
468 #ifdef CONFIG_PCIE2 469 #ifdef CONFIG_PCIE2
469 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 470 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
470 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 471 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
471 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 472 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
472 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 473 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
473 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 474 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
474 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 475 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
475 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 476 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
476 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 477 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
477 #endif 478 #endif
478 479
479 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 480 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
480 #ifdef CONFIG_PCIE3 481 #ifdef CONFIG_PCIE3
481 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 482 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
482 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 483 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
483 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 484 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
484 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 485 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
485 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 486 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
486 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 487 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
487 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 488 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
488 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 489 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
489 #endif 490 #endif
490 491
491 /* controller 4, Base address 203000 */ 492 /* controller 4, Base address 203000 */
492 #ifdef CONFIG_PCIE4 493 #ifdef CONFIG_PCIE4
493 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 494 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
494 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 495 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
495 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 496 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
496 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 497 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
497 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 498 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
498 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 499 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
499 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 500 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
500 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 501 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
501 #endif 502 #endif
502 503
503 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 504 #define CONFIG_PCI_PNP /* do pci plug-and-play */
504 #define CONFIG_E1000 505 #define CONFIG_E1000
505 506
506 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 507 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
507 #define CONFIG_DOS_PARTITION 508 #define CONFIG_DOS_PARTITION
508 #endif /* CONFIG_PCI */ 509 #endif /* CONFIG_PCI */
509 510
510 /* SATA */ 511 /* SATA */
511 #define CONFIG_FSL_SATA_V2 512 #define CONFIG_FSL_SATA_V2
512 #ifdef CONFIG_FSL_SATA_V2 513 #ifdef CONFIG_FSL_SATA_V2
513 #define CONFIG_LIBATA 514 #define CONFIG_LIBATA
514 #define CONFIG_FSL_SATA 515 #define CONFIG_FSL_SATA
515 516
516 #define CONFIG_SYS_SATA_MAX_DEVICE 2 517 #define CONFIG_SYS_SATA_MAX_DEVICE 2
517 #define CONFIG_SATA1 518 #define CONFIG_SATA1
518 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 519 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
519 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 520 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
520 #define CONFIG_SATA2 521 #define CONFIG_SATA2
521 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 522 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
522 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 523 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
523 524
524 #define CONFIG_LBA48 525 #define CONFIG_LBA48
525 #define CONFIG_CMD_SATA 526 #define CONFIG_CMD_SATA
526 #define CONFIG_DOS_PARTITION 527 #define CONFIG_DOS_PARTITION
527 #define CONFIG_CMD_EXT2 528 #define CONFIG_CMD_EXT2
528 #endif 529 #endif
529 530
530 /* 531 /*
531 * USB 532 * USB
532 */ 533 */
533 #define CONFIG_HAS_FSL_DR_USB 534 #define CONFIG_HAS_FSL_DR_USB
534 535
535 #ifdef CONFIG_HAS_FSL_DR_USB 536 #ifdef CONFIG_HAS_FSL_DR_USB
536 #define CONFIG_USB_EHCI 537 #define CONFIG_USB_EHCI
537 538
538 #ifdef CONFIG_USB_EHCI 539 #ifdef CONFIG_USB_EHCI
539 #define CONFIG_CMD_USB 540 #define CONFIG_CMD_USB
540 #define CONFIG_USB_STORAGE 541 #define CONFIG_USB_STORAGE
541 #define CONFIG_USB_EHCI_FSL 542 #define CONFIG_USB_EHCI_FSL
542 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 543 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
543 #define CONFIG_CMD_EXT2 544 #define CONFIG_CMD_EXT2
544 #endif 545 #endif
545 #endif 546 #endif
546 547
547 #define CONFIG_MMC 548 #define CONFIG_MMC
548 549
549 #ifdef CONFIG_MMC 550 #ifdef CONFIG_MMC
550 #define CONFIG_FSL_ESDHC 551 #define CONFIG_FSL_ESDHC
551 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 552 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
552 #define CONFIG_CMD_MMC 553 #define CONFIG_CMD_MMC
553 #define CONFIG_GENERIC_MMC 554 #define CONFIG_GENERIC_MMC
554 #define CONFIG_CMD_EXT2 555 #define CONFIG_CMD_EXT2
555 #define CONFIG_CMD_FAT 556 #define CONFIG_CMD_FAT
556 #define CONFIG_DOS_PARTITION 557 #define CONFIG_DOS_PARTITION
557 #endif 558 #endif
558 559
559 /* Qman/Bman */ 560 /* Qman/Bman */
560 #ifndef CONFIG_NOBQFMAN 561 #ifndef CONFIG_NOBQFMAN
561 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 562 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
562 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 563 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
563 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 564 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
564 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 565 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
565 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 566 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
566 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 567 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
567 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 568 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
568 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 569 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
569 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 570 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
570 571
571 #define CONFIG_SYS_DPAA_FMAN 572 #define CONFIG_SYS_DPAA_FMAN
572 #define CONFIG_SYS_DPAA_PME 573 #define CONFIG_SYS_DPAA_PME
573 574
574 /* Default address of microcode for the Linux Fman driver */ 575 /* Default address of microcode for the Linux Fman driver */
575 #if defined(CONFIG_SPIFLASH) 576 #if defined(CONFIG_SPIFLASH)
576 /* 577 /*
577 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 578 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
578 * env, so we got 0x110000. 579 * env, so we got 0x110000.
579 */ 580 */
580 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 581 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
581 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 582 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
582 #elif defined(CONFIG_SDCARD) 583 #elif defined(CONFIG_SDCARD)
583 /* 584 /*
584 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 585 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
585 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 586 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
586 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 587 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
587 */ 588 */
588 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 589 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
589 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) 590 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
590 #elif defined(CONFIG_NAND) 591 #elif defined(CONFIG_NAND)
591 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 592 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
592 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 593 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
593 #else 594 #else
594 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 595 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
595 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 596 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
596 #endif 597 #endif
597 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 598 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
598 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 599 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
599 #endif /* CONFIG_NOBQFMAN */ 600 #endif /* CONFIG_NOBQFMAN */
600 601
601 #ifdef CONFIG_SYS_DPAA_FMAN 602 #ifdef CONFIG_SYS_DPAA_FMAN
602 #define CONFIG_FMAN_ENET 603 #define CONFIG_FMAN_ENET
603 #define CONFIG_PHYLIB_10G 604 #define CONFIG_PHYLIB_10G
604 #define CONFIG_PHY_VITESSE 605 #define CONFIG_PHY_VITESSE
605 #define CONFIG_PHY_REALTEK 606 #define CONFIG_PHY_REALTEK
606 #define CONFIG_PHY_TERANETICS 607 #define CONFIG_PHY_TERANETICS
607 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 608 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
608 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 609 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
609 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 610 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
610 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 611 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
611 #endif 612 #endif
612 613
613 #ifdef CONFIG_FMAN_ENET 614 #ifdef CONFIG_FMAN_ENET
614 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 615 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10
615 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 616 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11
616 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 617 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
617 618
618 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 619 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
619 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 620 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
620 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 621 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
621 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 622 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
622 623
623 #define CONFIG_MII /* MII PHY management */ 624 #define CONFIG_MII /* MII PHY management */
624 #define CONFIG_ETHPRIME "FM1@DTSEC1" 625 #define CONFIG_ETHPRIME "FM1@DTSEC1"
625 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 626 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
626 #endif 627 #endif
627 628
628 /* 629 /*
629 * Environment 630 * Environment
630 */ 631 */
631 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 632 #define CONFIG_LOADS_ECHO /* echo on for serial download */
632 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 633 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
633 634
634 /* 635 /*
635 * Command line configuration. 636 * Command line configuration.
636 */ 637 */
637 #include <config_cmd_default.h> 638 #include <config_cmd_default.h>
638 639
639 #define CONFIG_CMD_DATE 640 #define CONFIG_CMD_DATE
640 #define CONFIG_CMD_DHCP 641 #define CONFIG_CMD_DHCP
641 #define CONFIG_CMD_EEPROM 642 #define CONFIG_CMD_EEPROM
642 #define CONFIG_CMD_ELF 643 #define CONFIG_CMD_ELF
643 #define CONFIG_CMD_ERRATA 644 #define CONFIG_CMD_ERRATA
644 #define CONFIG_CMD_GREPENV 645 #define CONFIG_CMD_GREPENV
645 #define CONFIG_CMD_IRQ 646 #define CONFIG_CMD_IRQ
646 #define CONFIG_CMD_I2C 647 #define CONFIG_CMD_I2C
647 #define CONFIG_CMD_MII 648 #define CONFIG_CMD_MII
648 #define CONFIG_CMD_PING 649 #define CONFIG_CMD_PING
649 #define CONFIG_CMD_REGINFO 650 #define CONFIG_CMD_REGINFO
650 #define CONFIG_CMD_SETEXPR 651 #define CONFIG_CMD_SETEXPR
651 652
652 #ifdef CONFIG_PCI 653 #ifdef CONFIG_PCI
653 #define CONFIG_CMD_PCI 654 #define CONFIG_CMD_PCI
654 #define CONFIG_CMD_NET 655 #define CONFIG_CMD_NET
655 #endif 656 #endif
656 657
657 /* 658 /*
658 * Miscellaneous configurable options 659 * Miscellaneous configurable options
659 */ 660 */
660 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 661 #define CONFIG_SYS_LONGHELP /* undef to save memory */
661 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 662 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
662 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 663 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
663 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 664 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
664 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 665 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
665 #ifdef CONFIG_CMD_KGDB 666 #ifdef CONFIG_CMD_KGDB
666 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 667 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
667 #else 668 #else
668 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 669 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
669 #endif 670 #endif
670 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 671 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
671 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 672 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
672 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 673 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
673 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ 674 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
674 675
675 /* 676 /*
676 * For booting Linux, the board info and command line data 677 * For booting Linux, the board info and command line data
677 * have to be in the first 64 MB of memory, since this is 678 * have to be in the first 64 MB of memory, since this is
678 * the maximum mapped by the Linux kernel during initialization. 679 * the maximum mapped by the Linux kernel during initialization.
679 */ 680 */
680 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 681 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
681 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 682 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
682 683
683 #ifdef CONFIG_CMD_KGDB 684 #ifdef CONFIG_CMD_KGDB
684 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 685 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
685 #endif 686 #endif
686 687
687 /* 688 /*
688 * Environment Configuration 689 * Environment Configuration
689 */ 690 */
690 #define CONFIG_ROOTPATH "/opt/nfsroot" 691 #define CONFIG_ROOTPATH "/opt/nfsroot"
691 #define CONFIG_BOOTFILE "uImage" 692 #define CONFIG_BOOTFILE "uImage"
692 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 693 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
693 694
694 /* default location for tftp and bootm */ 695 /* default location for tftp and bootm */
695 #define CONFIG_LOADADDR 1000000 696 #define CONFIG_LOADADDR 1000000
696 697
697 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 698 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
698 699
699 #define CONFIG_BAUDRATE 115200 700 #define CONFIG_BAUDRATE 115200
700 701
701 #define __USB_PHY_TYPE utmi 702 #define __USB_PHY_TYPE utmi
702 703
703 #define CONFIG_EXTRA_ENV_SETTINGS \ 704 #define CONFIG_EXTRA_ENV_SETTINGS \
704 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 705 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
705 "bank_intlv=cs0_cs1;" \ 706 "bank_intlv=cs0_cs1;" \
706 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 707 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
707 "netdev=eth0\0" \ 708 "netdev=eth0\0" \
708 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 709 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
709 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 710 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
710 "tftpflash=tftpboot $loadaddr $uboot && " \ 711 "tftpflash=tftpboot $loadaddr $uboot && " \
711 "protect off $ubootaddr +$filesize && " \ 712 "protect off $ubootaddr +$filesize && " \
712 "erase $ubootaddr +$filesize && " \ 713 "erase $ubootaddr +$filesize && " \
713 "cp.b $loadaddr $ubootaddr $filesize && " \ 714 "cp.b $loadaddr $ubootaddr $filesize && " \
714 "protect on $ubootaddr +$filesize && " \ 715 "protect on $ubootaddr +$filesize && " \
715 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 716 "cmp.b $loadaddr $ubootaddr $filesize\0" \
716 "consoledev=ttyS0\0" \ 717 "consoledev=ttyS0\0" \
717 "ramdiskaddr=2000000\0" \ 718 "ramdiskaddr=2000000\0" \
718 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 719 "ramdiskfile=t1040qds/ramdisk.uboot\0" \
719 "fdtaddr=c00000\0" \ 720 "fdtaddr=c00000\0" \
720 "fdtfile=t1040qds/t1040qds.dtb\0" \ 721 "fdtfile=t1040qds/t1040qds.dtb\0" \
721 "bdev=sda3\0" \ 722 "bdev=sda3\0" \
722 "c=ffe\0" 723 "c=ffe\0"
723 724
724 #define CONFIG_LINUX \ 725 #define CONFIG_LINUX \
725 "setenv bootargs root=/dev/ram rw " \ 726 "setenv bootargs root=/dev/ram rw " \
726 "console=$consoledev,$baudrate $othbootargs;" \ 727 "console=$consoledev,$baudrate $othbootargs;" \
727 "setenv ramdiskaddr 0x02000000;" \ 728 "setenv ramdiskaddr 0x02000000;" \
728 "setenv fdtaddr 0x00c00000;" \ 729 "setenv fdtaddr 0x00c00000;" \
729 "setenv loadaddr 0x1000000;" \ 730 "setenv loadaddr 0x1000000;" \
730 "bootm $loadaddr $ramdiskaddr $fdtaddr" 731 "bootm $loadaddr $ramdiskaddr $fdtaddr"
731 732
732 #define CONFIG_HDBOOT \ 733 #define CONFIG_HDBOOT \
733 "setenv bootargs root=/dev/$bdev rw " \ 734 "setenv bootargs root=/dev/$bdev rw " \
734 "console=$consoledev,$baudrate $othbootargs;" \ 735 "console=$consoledev,$baudrate $othbootargs;" \
735 "tftp $loadaddr $bootfile;" \ 736 "tftp $loadaddr $bootfile;" \
736 "tftp $fdtaddr $fdtfile;" \ 737 "tftp $fdtaddr $fdtfile;" \
737 "bootm $loadaddr - $fdtaddr" 738 "bootm $loadaddr - $fdtaddr"
738 739
739 #define CONFIG_NFSBOOTCOMMAND \ 740 #define CONFIG_NFSBOOTCOMMAND \
740 "setenv bootargs root=/dev/nfs rw " \ 741 "setenv bootargs root=/dev/nfs rw " \
741 "nfsroot=$serverip:$rootpath " \ 742 "nfsroot=$serverip:$rootpath " \
742 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 743 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
743 "console=$consoledev,$baudrate $othbootargs;" \ 744 "console=$consoledev,$baudrate $othbootargs;" \
744 "tftp $loadaddr $bootfile;" \ 745 "tftp $loadaddr $bootfile;" \
745 "tftp $fdtaddr $fdtfile;" \ 746 "tftp $fdtaddr $fdtfile;" \
746 "bootm $loadaddr - $fdtaddr" 747 "bootm $loadaddr - $fdtaddr"
747 748
748 #define CONFIG_RAMBOOTCOMMAND \ 749 #define CONFIG_RAMBOOTCOMMAND \
749 "setenv bootargs root=/dev/ram rw " \ 750 "setenv bootargs root=/dev/ram rw " \
750 "console=$consoledev,$baudrate $othbootargs;" \ 751 "console=$consoledev,$baudrate $othbootargs;" \
751 "tftp $ramdiskaddr $ramdiskfile;" \ 752 "tftp $ramdiskaddr $ramdiskfile;" \
752 "tftp $loadaddr $bootfile;" \ 753 "tftp $loadaddr $bootfile;" \
753 "tftp $fdtaddr $fdtfile;" \ 754 "tftp $fdtaddr $fdtfile;" \
754 "bootm $loadaddr $ramdiskaddr $fdtaddr" 755 "bootm $loadaddr $ramdiskaddr $fdtaddr"
755 756
756 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 757 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
757 758
758 #ifdef CONFIG_SECURE_BOOT 759 #ifdef CONFIG_SECURE_BOOT
759 #include <asm/fsl_secure_boot.h> 760 #include <asm/fsl_secure_boot.h>
760 #endif 761 #endif
761 762
762 #endif /* __CONFIG_H */ 763 #endif /* __CONFIG_H */
763 764