Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit e7be18225fbea76d1f0034b224f0d1e60f07cfcf

Authored by Tom Rini
2 parents 895ec893a9 8c618dd66a
Exists in master and in 50 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

Showing 18 changed files Side-by-side Diff

... ... @@ -423,6 +423,11 @@
423 423 CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
424 424 This value denotes start offset of DSP CCSR space.
425 425  
  426 + CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  427 + Single Source Clock is clocking mode present in some of FSL SoC's.
  428 + In this mode, a single differential clock is used to supply
  429 + clocks to the sysclock, ddrclock and usbclock.
  430 +
426 431 - Generic CPU options:
427 432 CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
428 433  
... ... @@ -3266,6 +3271,9 @@
3266 3271 CONFIG_SYS_NAND_ECCBYTES
3267 3272 Defines the size and behavior of the NAND that SPL uses
3268 3273 to read U-Boot
  3274 +
  3275 + CONFIG_SPL_NAND_BOOT
  3276 + Add support NAND boot
3269 3277  
3270 3278 CONFIG_SYS_NAND_U_BOOT_OFFS
3271 3279 Location in NAND to read U-Boot from
arch/powerpc/cpu/mpc85xx/speed.c
Diff comments   View file @ e7be182
... ... @@ -74,12 +74,33 @@
74 74 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
75 75 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
76 76 uint mem_pll_rat;
  77 +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  78 + uint single_src;
  79 +#endif
77 80  
78 81 sys_info->freq_systembus = sysclk;
  82 +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  83 + /*
  84 + * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
  85 + * are driven by separate DDR Refclock or single source
  86 + * differential clock.
  87 + */
  88 + single_src = (in_be32(&gur->rcwsr[5]) >>
  89 + FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
  90 + FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
  91 + /*
  92 + * For single source clocking, both ddrclock and syclock
  93 + * are driven by differential sysclock.
  94 + */
  95 + if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) {
  96 + printf("Single Source Clock Configuration\n");
  97 + sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
  98 + } else
  99 +#endif
79 100 #ifdef CONFIG_DDR_CLK_FREQ
80   - sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
  101 + sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
81 102 #else
82   - sys_info->freq_ddrbus = sysclk;
  103 + sys_info->freq_ddrbus = sysclk;
83 104 #endif
84 105  
85 106 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
arch/powerpc/include/asm/config_mpc85xx.h
Diff comments   View file @ e7be182
... ... @@ -711,6 +711,7 @@
711 711 #define CONFIG_FM_PLAT_CLK_DIV 1
712 712 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
713 713 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
  714 +#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
714 715 #define CONFIG_SYS_FSL_TBCLK_DIV 16
715 716 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
716 717 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
... ... @@ -745,7 +746,7 @@
745 746 #define CONFIG_SYS_NUM_FM1_DTSEC 6
746 747 #define CONFIG_SYS_NUM_FM1_10GEC 2
747 748 #endif
748   -#define CONFIG_SYS_FSL_NUM_USB_CTRLS 2
  749 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
749 750 #define CONFIG_NUM_DDR_CONTROLLERS 1
750 751 #define CONFIG_PME_PLAT_CLK_DIV 1
751 752 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
arch/powerpc/include/asm/immap_85xx.h
Diff comments   View file @ e7be182
... ... @@ -1774,6 +1774,9 @@
1774 1774 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000
1775 1775 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000
1776 1776 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000
  1777 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
  1778 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011
  1779 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1
1777 1780  
1778 1781 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
1779 1782 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17
board/freescale/b4860qds/b4_rcw.cfg
Diff comments   View file @ e7be182
... ... @@ -2,7 +2,7 @@
2 2 aa55aa55 010e0100
3 3 # serdes protocol 0x2A_0x98
4 4 140e0018 0f001218 00000000 00000000
5   -54980000 9000a000 f8025000 a9000000
  5 +54980000 9000a000 e8104000 a9000000
6 6 01000000 00000000 00000000 0001b1f8
7 7 00000000 14000020 00000000 00000011
board/freescale/bsc9131rdb/tlb.c
Diff comments   View file @ e7be182
... ... @@ -30,7 +30,7 @@
30 30 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
31 31 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
32 32 0, 0, BOOKE_PAGESZ_4K, 1),
33   -#ifdef CONFIG_SPL_NAND_MINIMAL
  33 +#ifdef CONFIG_SPL_NAND_BOOT
34 34 SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
35 35 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
36 36 0, 10, BOOKE_PAGESZ_4K, 1),
board/freescale/bsc9132qds/tlb.c
Diff comments   View file @ e7be182
... ... @@ -30,7 +30,7 @@
30 30 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
31 31 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
32 32 0, 0, BOOKE_PAGESZ_4K, 1),
33   -#ifdef CONFIG_SPL_NAND_MINIMAL
  33 +#ifdef CONFIG_SPL_NAND_BOOT
34 34 SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
35 35 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
36 36 0, 10, BOOKE_PAGESZ_4K, 1),
board/freescale/p1010rdb/tlb.c
Diff comments   View file @ e7be182
... ... @@ -30,7 +30,7 @@
30 30 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
31 31 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
32 32 0, 0, BOOKE_PAGESZ_4K, 1),
33   -#ifdef CONFIG_SPL_NAND_MINIMAL
  33 +#ifdef CONFIG_SPL_NAND_BOOT
34 34 SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
35 35 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
36 36 0, 10, BOOKE_PAGESZ_4K, 1),
board/freescale/t1040qds/t1040_pbi.cfg
Diff comments   View file @ e7be182
... ... @@ -3,7 +3,7 @@
3 3 09010000 00200400
4 4 09138000 00000000
5 5 091380c0 00000100
6   -#Configure CPC1 as 512KB SRAM
  6 +#Configure CPC1 as 256KB SRAM
7 7 09010100 00000000
8 8 09010104 fffc0007
9 9 09010f00 08000000
board/freescale/t1040qds/t1040qds.c
Diff comments   View file @ e7be182
... ... @@ -239,4 +239,9 @@
239 239 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
240 240 }
241 241 }
  242 +
  243 +int board_need_mem_reset(void)
  244 +{
  245 + return 1;
  246 +}
... ... @@ -965,6 +965,7 @@
965 965 Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
966 966 Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun <yorksun@freescale.com>
967 967 Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 -
  968 +Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
968 969 Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
969 970 Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
970 971 Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
include/configs/B4860QDS.h
Diff comments   View file @ e7be182
... ... @@ -289,6 +289,8 @@
289 289  
290 290 /* NAND Flash on IFC */
291 291 #define CONFIG_NAND_FSL_IFC
  292 +#define CONFIG_SYS_NAND_MAX_ECCPOS 256
  293 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2
292 294 #define CONFIG_SYS_NAND_BASE 0xff800000
293 295 #ifdef CONFIG_PHYS_64BIT
294 296 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
include/configs/BSC9131RDB.h
Diff comments   View file @ e7be182
... ... @@ -29,7 +29,7 @@
29 29 #define CONFIG_SPL_INIT_MINIMAL
30 30 #define CONFIG_SPL_SERIAL_SUPPORT
31 31 #define CONFIG_SPL_NAND_SUPPORT
32   -#define CONFIG_SPL_NAND_MINIMAL
  32 +#define CONFIG_SPL_NAND_BOOT
33 33 #define CONFIG_SPL_FLUSH_IMAGE
34 34 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
35 35  
include/configs/BSC9132QDS.h
Diff comments   View file @ e7be182
... ... @@ -38,7 +38,7 @@
38 38 #define CONFIG_SPL_INIT_MINIMAL
39 39 #define CONFIG_SPL_SERIAL_SUPPORT
40 40 #define CONFIG_SPL_NAND_SUPPORT
41   -#define CONFIG_SPL_NAND_MINIMAL
  41 +#define CONFIG_SPL_NAND_BOOT
42 42 #define CONFIG_SPL_FLUSH_IMAGE
43 43 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
44 44  
include/configs/CMS700.h
Diff comments   View file @ e7be182
... ... @@ -149,6 +149,9 @@
149 149 #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
150 150 #define CONFIG_SYS_NAND_QUIET 1
151 151  
  152 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2
  153 +#define CONFIG_SYS_NAND_MAX_ECCPOS 48
  154 +
152 155 /*
153 156 * For booting Linux, the board info and command line data
154 157 * have to be in the first 8 MB of memory, since this is
include/configs/P1010RDB.h
Diff comments   View file @ e7be182
... ... @@ -37,7 +37,7 @@
37 37 #define CONFIG_SPL_INIT_MINIMAL
38 38 #define CONFIG_SPL_SERIAL_SUPPORT
39 39 #define CONFIG_SPL_NAND_SUPPORT
40   -#define CONFIG_SPL_NAND_MINIMAL
  40 +#define CONFIG_SPL_NAND_BOOT
41 41 #define CONFIG_SPL_FLUSH_IMAGE
42 42 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
43 43  
include/configs/P1022DS.h
Diff comments   View file @ e7be182
... ... @@ -75,6 +75,8 @@
75 75 #endif
76 76  
77 77 #define CONFIG_NAND_FSL_ELBC
  78 +#define CONFIG_SYS_NAND_MAX_ECCPOS 56
  79 +#define CONFIG_SYS_NAND_MAX_OOBFREE 5
78 80  
79 81 #ifdef CONFIG_NAND
80 82 #define CONFIG_SPL
include/configs/T1040QDS.h
Diff comments   View file @ e7be182
... ... @@ -233,6 +233,7 @@
233 233 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
234 234 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
235 235 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  236 +#define QIXIS_RST_FORCE_MEM 0x01
236 237  
237 238 #define CONFIG_SYS_CSPR3_EXT (0xf)
238 239 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
... ... @@ -248,7 +249,7 @@
248 249 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
249 250 FTIM1_GPCM_TRAD(0x3f))
250 251 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
251   - FTIM2_GPCM_TCH(0x0) | \
  252 + FTIM2_GPCM_TCH(0x8) | \
252 253 FTIM2_GPCM_TWP(0x1f))
253 254 #define CONFIG_SYS_CS3_FTIM3 0x0
254 255