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Commit e7ee23ec1788d8cf269a4cf6b9cd3722cbc7d592

Authored by Peter Tyser
Committed by Kumar Gala
1 parent f6155c6fbb
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

86xx: Rename ccsr_ddr's sdram_mode_1, sdram_cfg_1 fields 

Rename sdram_mode_1 to sdram_mode and sdram_cfg_1 to sdram_cfg to match
the 86xx user's manual and other Freescale architectures

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Showing 5 changed files with 15 additions and 15 deletions Side-by-side Diff

board/freescale/mpc8610hpcd/mpc8610hpcd.c
Diff comments   View file @ e7ee23e
... ... @@ -154,7 +154,7 @@
154 154 ddr->timing_cfg_0 = 0x00260802;
155 155 ddr->timing_cfg_1 = 0x3935d322;
156 156 ddr->timing_cfg_2 = 0x14904cc8;
157   - ddr->sdram_mode_1 = 0x00480432;
  157 + ddr->sdram_mode = 0x00480432;
158 158 ddr->sdram_mode_2 = 0x00000000;
159 159 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
160 160 ddr->sdram_data_init = 0xDEADBEEF;
... ... @@ -170,7 +170,7 @@
170 170  
171 171 udelay(500);
172 172  
173   - ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/
  173 + ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
174 174  
175 175  
176 176 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
board/freescale/mpc8641hpcn/mpc8641hpcn.c
Diff comments   View file @ e7ee23e
... ... @@ -101,7 +101,7 @@
101 101 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
102 102 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
103 103 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
104   - ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
  104 + ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
105 105 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
106 106 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
107 107 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
108 108  
... ... @@ -119,9 +119,9 @@
119 119  
120 120 #if defined (CONFIG_DDR_ECC)
121 121 /* Enable ECC checking */
122   - ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
  122 + ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
123 123 #else
124   - ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL;
  124 + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
125 125 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
126 126 #endif
127 127 asm("sync; isync");
board/sbc8641d/sbc8641d.c
Diff comments   View file @ e7ee23e
... ... @@ -127,9 +127,9 @@
127 127 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
128 128 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
129 129 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
130   - ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1A;
  130 + ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
131 131 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
132   - ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
  132 + ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
133 133 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
134 134 ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
135 135 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
... ... @@ -140,7 +140,7 @@
140 140  
141 141 udelay (500);
142 142  
143   - ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1B;
  143 + ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
144 144 asm ("sync; isync");
145 145  
146 146 udelay (500);
147 147  
... ... @@ -158,9 +158,9 @@
158 158 ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
159 159 ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
160 160 ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
161   - ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1A;
  161 + ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
162 162 ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
163   - ddr->sdram_mode_1 = CONFIG_SYS_DDR2_MODE_1;
  163 + ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
164 164 ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
165 165 ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
166 166 ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
... ... @@ -171,7 +171,7 @@
171 171  
172 172 udelay (500);
173 173  
174   - ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1B;
  174 + ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
175 175 asm ("sync; isync");
176 176  
177 177 udelay (500);
cpu/mpc86xx/ddr-8641.c
Diff comments   View file @ e7ee23e
... ... @@ -56,7 +56,7 @@
56 56 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
57 57 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
58 58 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
59   - out_be32(&ddr->sdram_mode_1, regs->ddr_sdram_mode);
  59 + out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
60 60 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
61 61 out_be32(&ddr->sdram_mode_cntl, regs->ddr_sdram_md_cntl);
62 62 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
... ... @@ -74,7 +74,7 @@
74 74 udelay(200);
75 75 asm volatile("sync;isync");
76 76  
77   - out_be32(&ddr->sdram_cfg_1, regs->ddr_sdram_cfg);
  77 + out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
78 78  
79 79 /*
80 80 * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done
include/asm-ppc/immap_86xx.h
Diff comments   View file @ e7ee23e
... ... @@ -114,9 +114,9 @@
114 114 uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
115 115 uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
116 116 uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
117   - uint sdram_cfg_1; /* 0x2110 - DDR SDRAM Control Configuration 1 */
  117 + uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration 1 */
118 118 uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
119   - uint sdram_mode_1; /* 0x2118 - DDR SDRAM Mode Configuration 1 */
  119 + uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration 1 */
120 120 uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */
121 121 uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */
122 122 uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */