Eric Lee / smarc-uboot

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Commit e801931b5f6f5e720eb403af8a226d0c472e253b

Authored by Ye Li
1 parent 1061ac589c
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

MLK-23574-54 mx6ull_val: Add iMX6ULL DDR3 validation boards support 

Porting the iMX6ULL DDR3 validation board support from v2019.04 u-boot.

Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 22 changed files with 3219 additions and 0 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ e801931
... ... @@ -706,6 +706,11 @@
706 706 imx6ul-pico-pi.dtb
707 707  
708 708 dtb-$(CONFIG_MX6ULL) += \
  709 + imx6ull-14x14-ddr3-val.dtb \
  710 + imx6ull-14x14-ddr3-val-epdc.dtb \
  711 + imx6ull-14x14-ddr3-val-emmc.dtb \
  712 + imx6ull-14x14-ddr3-val-gpmi-weim.dtb \
  713 + imx6ull-14x14-ddr3-val-tsc.dtb \
709 714 imx6ull-14x14-evk.dtb \
710 715 imx6ull-14x14-evk-emmc.dtb \
711 716 imx6ull-14x14-evk-gpmi-weim.dtb \
arch/arm/dts/imx6ull-14x14-ddr3-val-emmc.dts
Diff comments   View file @ e801931
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify
  5 + * it under the terms of the GNU General Public License version 2 as
  6 + * published by the Free Software Foundation.
  7 + */
  8 +
  9 +#include "imx6ull-14x14-ddr3-val.dts"
  10 +
  11 +&usdhc1 {
  12 + pinctrl-0 = <&pinctrl_usdhc1>;
  13 + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
  14 + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
  15 + cd-gpios = <>;
  16 + wp-gpios = <>;
  17 + vmmc-supply = <>;
  18 + non-removable;
  19 + status = "okay";
  20 +};
arch/arm/dts/imx6ull-14x14-ddr3-val-epdc.dts
Diff comments   View file @ e801931
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify
  5 + * it under the terms of the GNU General Public License version 2 as
  6 + * published by the Free Software Foundation.
  7 + */
  8 +
  9 +#include "imx6ull-14x14-ddr3-val.dts"
  10 +
  11 +&epdc {
  12 + status = "okay";
  13 +};
  14 +
  15 +&fec2 {
  16 + status = "disabled";
  17 +};
  18 +
  19 +&lcdif {
  20 + status = "disabled";
  21 +};
  22 +
  23 +&max17135 {
  24 + status = "okay";
  25 +};
arch/arm/dts/imx6ull-14x14-ddr3-val-gpmi-weim.dts
Diff comments   View file @ e801931
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify
  5 + * it under the terms of the GNU General Public License version 2 as
  6 + * published by the Free Software Foundation.
  7 + */
  8 +
  9 +#include "imx6ull-14x14-ddr3-val.dts"
  10 +
  11 +&gpmi {
  12 + status ="okay";
  13 +};
  14 +
  15 +&qspi {
  16 + status ="disabled";
  17 +};
  18 +
  19 +&usdhc2{
  20 + status ="disabled";
  21 +};
arch/arm/dts/imx6ull-14x14-ddr3-val-lcdif.dts
Diff comments   View file @ e801931
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify
  5 + * it under the terms of the GNU General Public License version 2 as
  6 + * published by the Free Software Foundation.
  7 + */
  8 +
  9 +/* DTS file for LCDIF at imx6ull ddr3 val board */
  10 +
  11 +#include "imx6ull-14x14-ddr3-val.dts"
  12 +
  13 +/ {
  14 + backlight {
  15 + status = "okay";
  16 + };
  17 +};
  18 +
  19 +&fec1 {
  20 + status = "disabled";
  21 +};
  22 +
  23 +&lcdif {
  24 + status = "okay";
  25 +};
  26 +
  27 +&pwm1 {
  28 + status = "okay";
  29 +};
arch/arm/dts/imx6ull-14x14-ddr3-val-tsc.dts
Diff comments   View file @ e801931
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify
  5 + * it under the terms of the GNU General Public License version 2 as
  6 + * published by the Free Software Foundation.
  7 + */
  8 +
  9 +#include "imx6ull-14x14-ddr3-val-lcdif.dts"
  10 +
  11 +&i2c1 {
  12 + status = "disabled";
  13 +};
  14 +
  15 +&reg_usb_otg1_vbus {
  16 + pinctrl-0 = < >;
  17 + gpio = < >;
  18 +};
  19 +
  20 +&usbotg1 {
  21 + status = "disabled";
  22 +};
  23 +
  24 +&tsc {
  25 + pinctrl-names = "default";
  26 + pinctrl-0 = <&pinctrl_tsc>;
  27 + status = "okay";
  28 + xnur-gpio = <&gpio1 3 0>;
  29 + measure_delay_time = <0xfff>;
  30 + pre_charge_time = <0xffff>;
  31 +};
arch/arm/dts/imx6ull-14x14-ddr3-val.dts
Diff comments   View file @ e801931
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify
  5 + * it under the terms of the GNU General Public License version 2 as
  6 + * published by the Free Software Foundation.
  7 + */
  8 +
  9 +/dts-v1/;
  10 +
  11 +#include <dt-bindings/input/input.h>
  12 +#include "imx6ull.dtsi"
  13 +
  14 +/ {
  15 + model = "i.MX6 ULL DDR3 VAL Board";
  16 + compatible = "fsl,imx6ull-ddr3-val", "fsl,imx6ull";
  17 +
  18 + chosen {
  19 + stdout-path = &uart1;
  20 + };
  21 +
  22 + memory {
  23 + reg = <0x80000000 0x40000000>;
  24 + };
  25 +
  26 + backlight {
  27 + compatible = "pwm-backlight";
  28 + pwms = <&pwm1 0 5000000>;
  29 + brightness-levels = <0 4 8 16 32 64 128 255>;
  30 + default-brightness-level = <6>;
  31 + status = "disabled";
  32 + };
  33 +
  34 + regulators {
  35 + compatible = "simple-bus";
  36 + #address-cells = <1>;
  37 + #size-cells = <0>;
  38 +
  39 + reg_sd1_vmmc: sd1_vmmc {
  40 + compatible = "regulator-fixed";
  41 + regulator-name = "SD1_SPWR";
  42 + regulator-min-microvolt = <3000000>;
  43 + regulator-max-microvolt = <3000000>;
  44 + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  45 + u-boot,off-on-delay-us = <20000>;
  46 + enable-active-high;
  47 + };
  48 +
  49 + reg_sd2_vmmc: sd2_vmmc {
  50 + compatible = "regulator-fixed";
  51 + regulator-name = "SD2_SPWR";
  52 + regulator-min-microvolt = <3000000>;
  53 + regulator-max-microvolt = <3000000>;
  54 + gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
  55 + off-on-delay-us = <20000>;
  56 + enable-active-high;
  57 + };
  58 +
  59 + reg_can2_3v3: regulator@0 {
  60 + compatible = "regulator-fixed";
  61 + reg = <0>;
  62 + regulator-name = "can2-3v3";
  63 + regulator-min-microvolt = <3300000>;
  64 + regulator-max-microvolt = <3300000>;
  65 + gpio = <&gpio1 15 GPIO_ACTIVE_LOW>;
  66 + };
  67 +
  68 + reg_vref_3v3: regulator@1 {
  69 + compatible = "regulator-fixed";
  70 + regulator-name = "vref-3v3";
  71 + regulator-min-microvolt = <3300000>;
  72 + regulator-max-microvolt = <3300000>;
  73 + };
  74 +
  75 + reg_usb_otg1_vbus: regulator@2 {
  76 + compatible = "regulator-fixed";
  77 + reg = <2>;
  78 + pinctrl-names = "default";
  79 + pinctrl-0 = <&pinctrl_usb_otg1>;
  80 + regulator-name = "usb_otg1_vbus";
  81 + regulator-min-microvolt = <5000000>;
  82 + regulator-max-microvolt = <5000000>;
  83 + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
  84 + enable-active-high;
  85 + };
  86 + };
  87 +};
  88 +
  89 +&clks {
  90 + /* For bringup, comments this.
  91 + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
  92 + assigned-clock-rates = <786432000>;
  93 + */
  94 +};
  95 +
  96 +&cpu0 {
  97 + /*
  98 + * on i.MX6ULL, no seperated VDD_ARM_IN and VDD_SOC_IN,
  99 + * to align with other platform and use the same cpufreq
  100 + * driver, still use the seperated OPP define for arm
  101 + * and soc.
  102 + */
  103 + operating-points = <
  104 + /* kHz uV */
  105 + 528000 1175000
  106 + 396000 1175000
  107 + 198000 1175000
  108 + >;
  109 + fsl,soc-operating-points = <
  110 + /* KHz uV */
  111 + 528000 1175000
  112 + 396000 1175000
  113 + 198000 1175000
  114 + >;
  115 + fsl,arm-soc-shared = <1>;
  116 +};
  117 +
  118 +&reg_arm {
  119 + vin-supply = <&sw1a_reg>;
  120 + regulator-allow-bypass;
  121 +};
  122 +
  123 +&reg_soc {
  124 + vin-supply = <&sw1a_reg>;
  125 + regulator-allow-bypass;
  126 +};
  127 +
  128 +&ecspi1 {
  129 + fsl,spi-num-chipselects = <1>;
  130 + cs-gpios = <&gpio4 26 0>;
  131 + pinctrl-names = "default";
  132 + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>;
  133 + status = "disabled";
  134 +
  135 + flash: n25q032@0 {
  136 + #address-cells = <1>;
  137 + #size-cells = <1>;
  138 + compatible = "st,n25q032", "jedec,spi-nor";
  139 + spi-max-frequency = <20000000>;
  140 + reg = <0>;
  141 + };
  142 +};
  143 +
  144 +&epdc {
  145 + pinctrl-names = "default";
  146 + pinctrl-0 = <&pinctrl_epdc0>;
  147 + V3P3-supply = <&V3P3_reg>;
  148 + VCOM-supply = <&VCOM_reg>;
  149 + DISPLAY-supply = <&DISPLAY_reg>;
  150 + status = "disabled";
  151 +};
  152 +
  153 +&fec1 {
  154 + pinctrl-names = "default";
  155 + pinctrl-0 = <&pinctrl_enet1>;
  156 + phy-mode = "rmii";
  157 + phy-handle = <&ethphy0>;
  158 + status = "okay";
  159 +};
  160 +
  161 +&fec2 {
  162 + pinctrl-names = "default";
  163 + pinctrl-0 = <&pinctrl_enet2>;
  164 + phy-mode = "mii";
  165 + phy-handle = <&ethphy1>;
  166 + status = "okay";
  167 +
  168 + mdio {
  169 + #address-cells = <1>;
  170 + #size-cells = <0>;
  171 +
  172 + ethphy0: ethernet-phy@1 {
  173 + compatible = "ethernet-phy-ieee802.3-c22";
  174 + reg = <1>;
  175 + };
  176 +
  177 + ethphy1: ethernet-phy@2 {
  178 + compatible = "ethernet-phy-ieee802.3-c22";
  179 + reg = <2>;
  180 + };
  181 + };
  182 +};
  183 +
  184 +&can2 {
  185 + pinctrl-names = "default";
  186 + pinctrl-0 = <&pinctrl_flexcan2>;
  187 + xceiver-supply = <&reg_can2_3v3>;
  188 + status = "disabled";
  189 +};
  190 +
  191 +&gpc {
  192 + fsl,cpu_pupscr_sw2iso = <0xf>;
  193 + fsl,cpu_pupscr_sw = <0x0>;
  194 + fsl,cpu_pdnscr_iso2sw = <0x1>;
  195 + fsl,cpu_pdnscr_iso = <0x1>;
  196 + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
  197 +};
  198 +
  199 +&gpmi {
  200 + pinctrl-names = "default";
  201 + pinctrl-0 = <&pinctrl_gpmi_nand_1>;
  202 + status = "disabled";
  203 + nand-on-flash-bbt;
  204 +};
  205 +
  206 +&i2c1 {
  207 + clock-frequency = <100000>;
  208 + pinctrl-names = "default", "gpio";
  209 + pinctrl-0 = <&pinctrl_i2c1>;
  210 + pinctrl-1 = <&pinctrl_i2c1_gpio>;
  211 + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
  212 + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
  213 + status = "okay";
  214 +
  215 + pmic: pfuze100@8 {
  216 + compatible = "fsl,pfuze200";
  217 + reg = <0x08>;
  218 +
  219 + regulators {
  220 + sw1a_reg: sw1ab {
  221 + regulator-min-microvolt = <300000>;
  222 + regulator-max-microvolt = <1875000>;
  223 + regulator-always-on;
  224 + regulator-ramp-delay = <6250>;
  225 + };
  226 +
  227 + sw2_reg: sw2 {
  228 + regulator-min-microvolt = <800000>;
  229 + regulator-max-microvolt = <3300000>;
  230 + regulator-always-on;
  231 + };
  232 +
  233 + sw3a_reg: sw3a {
  234 + regulator-min-microvolt = <400000>;
  235 + regulator-max-microvolt = <1975000>;
  236 + regulator-always-on;
  237 + };
  238 +
  239 + sw3b_reg: sw3b {
  240 + regulator-min-microvolt = <800000>;
  241 + regulator-max-microvolt = <3300000>;
  242 + regulator-always-on;
  243 + };
  244 +
  245 + swbst_reg: swbst {
  246 + regulator-min-microvolt = <5000000>;
  247 + regulator-max-microvolt = <5150000>;
  248 + };
  249 +
  250 + snvs_reg: vsnvs {
  251 + regulator-min-microvolt = <1000000>;
  252 + regulator-max-microvolt = <3000000>;
  253 + regulator-always-on;
  254 + };
  255 +
  256 + vref_reg: vrefddr {
  257 + regulator-always-on;
  258 + };
  259 +
  260 + vgen1_reg: vgen1 {
  261 + regulator-min-microvolt = <800000>;
  262 + regulator-max-microvolt = <1550000>;
  263 + };
  264 +
  265 + vgen2_reg: vgen2 {
  266 + regulator-min-microvolt = <800000>;
  267 + regulator-max-microvolt = <1550000>;
  268 + };
  269 +
  270 + vgen3_reg: vgen3 {
  271 + regulator-min-microvolt = <1800000>;
  272 + regulator-max-microvolt = <3300000>;
  273 + };
  274 +
  275 + vgen4_reg: vgen4 {
  276 + regulator-min-microvolt = <1800000>;
  277 + regulator-max-microvolt = <3300000>;
  278 + regulator-always-on;
  279 + };
  280 +
  281 + vgen5_reg: vgen5 {
  282 + regulator-min-microvolt = <1800000>;
  283 + regulator-max-microvolt = <3300000>;
  284 + regulator-always-on;
  285 + };
  286 +
  287 + vgen6_reg: vgen6 {
  288 + regulator-min-microvolt = <1800000>;
  289 + regulator-max-microvolt = <3300000>;
  290 + regulator-always-on;
  291 + };
  292 + };
  293 + };
  294 +};
  295 +
  296 +&i2c4 {
  297 + clock-frequency = <100000>;
  298 + pinctrl-names = "default", "gpio";
  299 + pinctrl-0 = <&pinctrl_i2c4>;
  300 + pinctrl-1 = <&pinctrl_i2c4_gpio>;
  301 + scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
  302 + sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
  303 + status = "okay";
  304 +
  305 + max17135: max17135@48 {
  306 + pinctrl-names = "default";
  307 + pinctrl-0 = <&pinctrl_max17135>;
  308 + compatible = "maxim,max17135";
  309 + reg = <0x48>;
  310 + status = "disabled";
  311 +
  312 + vneg_pwrup = <1>;
  313 + gvee_pwrup = <2>;
  314 + vpos_pwrup = <10>;
  315 + gvdd_pwrup = <12>;
  316 + gvdd_pwrdn = <1>;
  317 + vpos_pwrdn = <2>;
  318 + gvee_pwrdn = <8>;
  319 + vneg_pwrdn = <10>;
  320 + gpio_pmic_pwrgood = <&gpio3 16 0>;
  321 + gpio_pmic_vcom_ctrl = <&gpio3 24 0>;
  322 + gpio_pmic_wakeup = <&gpio3 14 0>;
  323 + gpio_pmic_v3p3 = <&gpio3 17 0>;
  324 + gpio_pmic_intr = <&gpio3 13 0>;
  325 +
  326 + regulators {
  327 + DISPLAY_reg: DISPLAY {
  328 + regulator-name = "DISPLAY";
  329 + };
  330 +
  331 + GVDD_reg: GVDD {
  332 + /* 20v */
  333 + regulator-name = "GVDD";
  334 + };
  335 +
  336 + GVEE_reg: GVEE {
  337 + /* -22v */
  338 + regulator-name = "GVEE";
  339 + };
  340 +
  341 + HVINN_reg: HVINN {
  342 + /* -22v */
  343 + regulator-name = "HVINN";
  344 + };
  345 +
  346 + HVINP_reg: HVINP {
  347 + /* 20v */
  348 + regulator-name = "HVINP";
  349 + };
  350 +
  351 + VCOM_reg: VCOM {
  352 + regulator-name = "VCOM";
  353 + /* Real max: -500000 */
  354 + regulator-max-microvolt = <4325000>;
  355 + /* Real min: -4325000 */
  356 + regulator-min-microvolt = <500000>;
  357 + };
  358 +
  359 + VNEG_reg: VNEG {
  360 + /* -15v */
  361 + regulator-name = "VNEG";
  362 + };
  363 +
  364 + VPOS_reg: VPOS {
  365 + /* 15v */
  366 + regulator-name = "VPOS";
  367 + };
  368 +
  369 + V3P3_reg: V3P3 {
  370 + regulator-name = "V3P3";
  371 + };
  372 + };
  373 + };
  374 +};
  375 +
  376 +&iomuxc {
  377 + imx6ull-ddr3-val {
  378 + pinctrl_adc1: adc1grp {
  379 + fsl,pins = <
  380 + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0
  381 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
  382 + >;
  383 + };
  384 +
  385 +
  386 + pinctrl_csi1: csi1grp {
  387 + fsl,pins = <
  388 + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
  389 + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
  390 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
  391 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
  392 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
  393 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
  394 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
  395 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
  396 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
  397 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
  398 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
  399 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
  400 + >;
  401 + };
  402 +
  403 + pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 {
  404 + fsl,pins = <
  405 + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0
  406 + >;
  407 + };
  408 +
  409 + pinctrl_ecspi1_1: ecspi1grp-1 {
  410 + fsl,pins = <
  411 + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x10b0
  412 + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x10b0
  413 + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x10b0
  414 + >;
  415 + };
  416 +
  417 + pinctrl_enet1: enet1grp {
  418 + fsl,pins = <
  419 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
  420 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
  421 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
  422 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
  423 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
  424 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
  425 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
  426 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a0
  427 + >;
  428 + };
  429 +
  430 + pinctrl_enet2: enet2grp {
  431 + fsl,pins = <
  432 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b098
  433 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
  434 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0
  435 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0
  436 + MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x1b0a0
  437 + MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x1b0a0
  438 + MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x4001b0a8
  439 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
  440 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
  441 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
  442 + MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x1b0b0
  443 + MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x1b0b0
  444 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
  445 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
  446 + MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x4001b0a8
  447 + MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x1b0b0
  448 + MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x1b0b0
  449 + >;
  450 + };
  451 +
  452 + pinctrl_epdc0: epdcgrp0 {
  453 + fsl,pins = <
  454 + MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x10b1
  455 + MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x10b1
  456 + MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x10b1
  457 + MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x10b1
  458 + MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x10b1
  459 + MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x10b1
  460 + MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x10b1
  461 + MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x10b1
  462 + MX6ULL_PAD_LCD_CLK__EPDC_SDCLK 0x10b1
  463 + MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE 0x10b1
  464 + MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE 0x10b1
  465 + MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0 0x10b1
  466 + MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00 0x10b1
  467 + MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01 0x10b1
  468 + MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02 0x10b1
  469 + MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03 0x10b1
  470 + MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04 0x10b1
  471 + MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05 0x10b1
  472 + MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06 0x10b1
  473 + MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07 0x10b1
  474 + MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR 0x10b1
  475 + MX6ULL_PAD_LCD_DATA15__EPDC_GDRL 0x10b1
  476 + MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x10b1
  477 + MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x10b1
  478 + MX6ULL_PAD_LCD_RESET__EPDC_GDOE 0x10b1
  479 + >;
  480 + };
  481 +
  482 + pinctrl_esai: esaigrp {
  483 + fsl,pins = <
  484 + MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x1b0b0
  485 + MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x1b0b0
  486 + MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x1b0b0
  487 + MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x1b0b0
  488 + MX6ULL_PAD_CSI_DATA07__ESAI_T0 0x1b0b0
  489 + MX6ULL_PAD_CSI_HSYNC__ESAI_TX1 0x1b0b0
  490 + MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x1b0b0
  491 + MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x1b0b0
  492 + MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x1b0b0
  493 + MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x1b0b0
  494 + MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x1b0b0
  495 + MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x1b0b0
  496 + >;
  497 + };
  498 +
  499 + pinctrl_flexcan2: flexcan2grp{
  500 + fsl,pins = <
  501 + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
  502 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
  503 + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* STBY */
  504 + >;
  505 + };
  506 +
  507 + pinctrl_gpmi_nand_1: gpmi-nand-1 {
  508 + fsl,pins = <
  509 + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
  510 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
  511 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
  512 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
  513 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
  514 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
  515 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
  516 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
  517 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
  518 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
  519 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
  520 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
  521 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
  522 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
  523 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
  524 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
  525 + >;
  526 + };
  527 +
  528 + pinctrl_i2c1: i2c1grp {
  529 + fsl,pins = <
  530 + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b1
  531 + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b1
  532 + >;
  533 + };
  534 +
  535 + pinctrl_i2c1_gpio: i2c1grp_gpio {
  536 + fsl,pins = <
  537 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x1b8b1
  538 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b8b1
  539 + >;
  540 + };
  541 +
  542 + pinctrl_i2c4: i2c4grp {
  543 + fsl,pins = <
  544 + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0
  545 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0
  546 + >;
  547 + };
  548 +
  549 + pinctrl_i2c4_gpio: i2c4grp_gpio {
  550 + fsl,pins = <
  551 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x1b8b0
  552 + MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x1b8b0
  553 + >;
  554 + };
  555 +
  556 + pinctrl_lcdif_dat: lcdifdatgrp {
  557 + fsl,pins = <
  558 + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
  559 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
  560 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
  561 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
  562 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
  563 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
  564 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
  565 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
  566 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
  567 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
  568 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
  569 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
  570 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
  571 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
  572 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
  573 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
  574 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
  575 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
  576 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
  577 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
  578 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
  579 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
  580 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
  581 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
  582 + >;
  583 + };
  584 +
  585 + pinctrl_lcdif_ctrl: lcdifctrlgrp {
  586 + fsl,pins = <
  587 + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
  588 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
  589 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
  590 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
  591 + MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79
  592 + >;
  593 + };
  594 +
  595 + pinctrl_max17135: max17135grp-1 {
  596 + fsl,pins = <
  597 + MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x80000000 /* pwrgood */
  598 + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x80000000 /* vcom_ctrl */
  599 + MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x80000000 /* wakeup */
  600 + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x80000000 /* v3p3 */
  601 + MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x80000000 /* pwr int */
  602 + >;
  603 + };
  604 +
  605 + pinctrl_mqs: mqsgrp {
  606 + fsl,pins = <
  607 + MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x11088
  608 + MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x11088
  609 + >;
  610 + };
  611 +
  612 + pinctrl_pwm1: pmw1grp {
  613 + fsl,pins = <
  614 + MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x110b0
  615 + >;
  616 + };
  617 +
  618 + pinctrl_qspi: qspigrp {
  619 + fsl,pins = <
  620 + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
  621 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
  622 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
  623 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
  624 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
  625 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
  626 +#ifdef REWORKED_ENABLE_ALL_QSPI
  627 + MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x70a1
  628 + MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x70a1
  629 + MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x70a1
  630 + MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x70a1
  631 + MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x70a1
  632 + MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x70a1
  633 + MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x70a1
  634 + MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x70a1
  635 +#endif
  636 + >;
  637 + };
  638 +
  639 + pinctrl_sai2: sai2grp {
  640 + fsl,pins = <
  641 + MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x1b0b0
  642 + MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x1b0b0
  643 + MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x110b0
  644 + MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x110b0
  645 + MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x1b0b0
  646 + >;
  647 + };
  648 +
  649 + pinctrl_spdif: spdifgrp {
  650 + fsl,pins = <
  651 + MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x1b0b0
  652 + MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x1b0b0
  653 + >;
  654 + };
  655 +
  656 + pinctrl_tsc: tscgrp {
  657 + fsl,pins = <
  658 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
  659 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
  660 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
  661 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
  662 + >;
  663 + };
  664 +
  665 + pinctrl_uart1: uart1grp {
  666 + fsl,pins = <
  667 + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
  668 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
  669 + >;
  670 + };
  671 +
  672 + pinctrl_uart2: uart2grp {
  673 + fsl,pins = <
  674 + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
  675 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
  676 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
  677 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
  678 + >;
  679 + };
  680 +
  681 + pinctrl_uart2dte: uart2dtegrp {
  682 + fsl,pins = <
  683 + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
  684 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
  685 + MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1
  686 + MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1
  687 + >;
  688 + };
  689 +
  690 + pinctrl_usb_otg1_id: usbotg1idgrp {
  691 + fsl,pins = <
  692 + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
  693 + >;
  694 + };
  695 +
  696 + pinctrl_usb_otg1: usbotg1grp {
  697 + fsl,pins = <
  698 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0
  699 + >;
  700 + };
  701 +
  702 + pinctrl_usdhc1: usdhc1grp {
  703 + fsl,pins = <
  704 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
  705 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
  706 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
  707 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
  708 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
  709 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
  710 + >;
  711 + };
  712 +
  713 + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
  714 + fsl,pins = <
  715 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
  716 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
  717 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
  718 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
  719 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
  720 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
  721 + >;
  722 + };
  723 +
  724 + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
  725 + fsl,pins = <
  726 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
  727 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
  728 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
  729 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
  730 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
  731 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
  732 + >;
  733 + };
  734 +
  735 + pinctrl_usdhc1_8bit: usdhc1_8bit_grp {
  736 + fsl,pins = <
  737 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
  738 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
  739 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
  740 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
  741 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
  742 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
  743 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
  744 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
  745 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
  746 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
  747 + >;
  748 + };
  749 +
  750 + pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp {
  751 + fsl,pins = <
  752 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
  753 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
  754 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
  755 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
  756 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
  757 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
  758 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9
  759 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9
  760 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9
  761 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9
  762 + >;
  763 + };
  764 +
  765 + pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp {
  766 + fsl,pins = <
  767 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
  768 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
  769 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
  770 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
  771 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
  772 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
  773 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9
  774 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9
  775 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9
  776 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9
  777 + >;
  778 + };
  779 +
  780 + pinctrl_usdhc1_cd_wp: usdhc1_cd_wp_grp {
  781 + fsl,pins = <
  782 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
  783 + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 /* SD1 WP */
  784 + >;
  785 + };
  786 +
  787 + pinctrl_usdhc1_rst: usdhc1_rst_grp {
  788 + fsl,pins = <
  789 + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
  790 + >;
  791 + };
  792 +
  793 + pinctrl_usdhc1_vselect: usdhc1_vselect_grp {
  794 + fsl,pins = <
  795 + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
  796 + >;
  797 + };
  798 +
  799 + pinctrl_usdhc2: usdhc2grp {
  800 + fsl,pins = <
  801 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
  802 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
  803 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
  804 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
  805 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
  806 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
  807 + >;
  808 + };
  809 +
  810 + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
  811 + fsl,pins = <
  812 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
  813 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100a9
  814 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170a9
  815 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170a9
  816 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170a9
  817 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170a9
  818 + >;
  819 + };
  820 +
  821 + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
  822 + fsl,pins = <
  823 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
  824 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
  825 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
  826 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
  827 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
  828 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
  829 + >;
  830 + };
  831 +
  832 + pinctrl_usdhc2_rst: usdhc2_rst_grp {
  833 + fsl,pins = <
  834 + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x17059 /* SD2 RESET */
  835 + >;
  836 + };
  837 +
  838 + pinctrl_wdog: wdoggrp {
  839 + fsl,pins = <
  840 + MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x30b0
  841 + >;
  842 + };
  843 + };
  844 +};
  845 +
  846 +&iomuxc_snvs {
  847 + imx6ull-ddr3-val {
  848 + pinctrl_bt: btgrp {
  849 + fsl,pins = <
  850 + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x80000000
  851 + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x80000000
  852 + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x80000000
  853 + >;
  854 + };
  855 +
  856 + pinctrl_sai2_hp_det_b: sai2_hp_det_grp {
  857 + fsl,pins = <
  858 + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059
  859 + >;
  860 + };
  861 + };
  862 +};
  863 +
  864 +&lcdif {
  865 + pinctrl-names = "default";
  866 + pinctrl-0 = <&pinctrl_lcdif_dat
  867 + &pinctrl_lcdif_ctrl>;
  868 + display = <&display0>;
  869 + status = "disabled";
  870 +
  871 + display0: display {
  872 + bits-per-pixel = <16>;
  873 + bus-width = <24>;
  874 +
  875 + display-timings {
  876 + native-mode = <&timing0>;
  877 + timing0: timing0 {
  878 + clock-frequency = <33500000>;
  879 + hactive = <800>;
  880 + vactive = <480>;
  881 + hback-porch = <89>;
  882 + hfront-porch = <164>;
  883 + vback-porch = <23>;
  884 + vfront-porch = <10>;
  885 + hsync-len = <10>;
  886 + vsync-len = <10>;
  887 + hsync-active = <0>;
  888 + vsync-active = <0>;
  889 + de-active = <1>;
  890 + pixelclk-active = <0>;
  891 + };
  892 + };
  893 + };
  894 +};
  895 +
  896 +&pwm1 {
  897 + pinctrl-names = "default";
  898 + pinctrl-0 = <&pinctrl_pwm1>;
  899 + status = "disabled";
  900 +};
  901 +
  902 +&qspi {
  903 + pinctrl-names = "default";
  904 + pinctrl-0 = <&pinctrl_qspi>;
  905 + status = "okay";
  906 +#ifdef REWORKED_ENABLE_ALL_QSPI
  907 + fsl,qspi-has-second-chip = <1>;
  908 +#endif
  909 + ddrsmp=<0>;
  910 +
  911 + flash0: n25q256a@0 {
  912 + #address-cells = <1>;
  913 + #size-cells = <1>;
  914 + compatible = "micron,n25q256a", "jedec,spi-nor";
  915 + spi-max-frequency = <29000000>;
  916 + spi-nor,ddr-quad-read-dummy = <6>;
  917 + reg = <0>;
  918 + };
  919 +
  920 +#ifdef REWORKED_ENABLE_ALL_QSPI
  921 +
  922 + flash1: n25q256a@1 {
  923 + #address-cells = <1>;
  924 + #size-cells = <1>;
  925 + compatible = "micron,n25q256a", "jedec,spi-nor";
  926 + spi-max-frequency = <29000000>;
  927 + spi-nor,ddr-quad-read-dummy = <6>;
  928 + reg = <1>;
  929 + };
  930 +
  931 + flash2: n25q256a@2 {
  932 + #address-cells = <1>;
  933 + #size-cells = <1>;
  934 + compatible = "micron,n25q256a", "jedec,spi-nor";
  935 + spi-max-frequency = <29000000>;
  936 + spi-nor,ddr-quad-read-dummy = <6>;
  937 + reg = <2>;
  938 + };
  939 +
  940 + flash3: n25q256a@3 {
  941 + #address-cells = <1>;
  942 + #size-cells = <1>;
  943 + compatible = "micron,n25q256a", "jedec,spi-nor";
  944 + spi-max-frequency = <29000000>;
  945 + spi-nor,ddr-quad-read-dummy = <6>;
  946 + reg = <3>;
  947 + };
  948 +#endif
  949 +};
  950 +
  951 +&uart1 {
  952 + pinctrl-names = "default";
  953 + pinctrl-0 = <&pinctrl_uart1>;
  954 + status = "okay";
  955 +};
  956 +
  957 +&uart2 {
  958 + pinctrl-names = "default";
  959 + pinctrl-0 = <&pinctrl_uart2
  960 + &pinctrl_bt>;
  961 + fsl,uart-has-rtscts;
  962 + /* for DTE mode, add below change */
  963 + /* fsl,dte-mode; */
  964 + /* pinctrl-0 = <&pinctrl_uart2dte>; */
  965 + status = "disabled";
  966 +};
  967 +
  968 +&usbotg1 {
  969 + vbus-supply = <&reg_usb_otg1_vbus>;
  970 + pinctrl-names = "default";
  971 + pinctrl-0 = <&pinctrl_usb_otg1_id>;
  972 + srp-disable;
  973 + hnp-disable;
  974 + adp-disable;
  975 + status = "okay";
  976 +};
  977 +
  978 +&usdhc1 {
  979 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
  980 + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>;
  981 + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>;
  982 + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>;
  983 + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
  984 + wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
  985 + keep-power-in-suspend;
  986 + enable-sdio-wakeup;
  987 + vmmc-supply = <&reg_sd1_vmmc>;
  988 + status = "okay";
  989 +};
  990 +
  991 +&usdhc2 {
  992 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
  993 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_rst>;
  994 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_rst>;
  995 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_rst>;
  996 + non-removable;
  997 + no-1-8-v; /* VSELECT not connected by default */
  998 + keep-power-in-suspend;
  999 + enable-sdio-wakeup;
  1000 + vmmc-supply = <&reg_sd2_vmmc>;
  1001 + status = "okay";
  1002 +};
  1003 +
  1004 +&wdog1 {
  1005 + pinctrl-names = "default";
  1006 + pinctrl-0 = <&pinctrl_wdog>;
  1007 + fsl,ext-reset-output;
  1008 +};
arch/arm/mach-imx/mx6/Kconfig
Diff comments   View file @ e801931
... ... @@ -586,6 +586,14 @@
586 586 select SUPPORT_SPL
587 587 imply CMD_DM
588 588  
  589 +config TARGET_MX6ULL_DDR3_VAL
  590 + bool "Support mx6ull_ddr3_val"
  591 + select BOARD_LATE_INIT
  592 + select MX6ULL
  593 + select DM
  594 + select DM_THERMAL
  595 + imply CMD_DM
  596 +
589 597 config TARGET_MX6ULL_9X9_EVK
590 598 bool "Support mx6ull_9x9_evk"
591 599 select BOARD_LATE_INIT
... ... @@ -849,6 +857,7 @@
849 857 source "board/freescale/mx6ul_14x14_ddr3_val/Kconfig"
850 858 source "board/freescale/mx6ul_14x14_lpddr2_val/Kconfig"
851 859 source "board/freescale/mx6ullevk/Kconfig"
  860 +source "board/freescale/mx6ull_ddr3_val/Kconfig"
852 861 source "board/grinn/liteboard/Kconfig"
853 862 source "board/phytec/pcm058/Kconfig"
854 863 source "board/phytec/pfla02/Kconfig"
board/freescale/mx6ull_ddr3_val/Kconfig
Diff comments   View file @ e801931
  1 +if TARGET_MX6ULL_DDR3_VAL
  2 +
  3 +config SYS_BOARD
  4 + default "mx6ull_ddr3_val"
  5 +
  6 +config SYS_VENDOR
  7 + default "freescale"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "mx6ull_ddr3_val"
  11 +
  12 +config MX6ULL_DDR3_VAL_EMMC_REWORK
  13 + bool "Select this for the board with eMMC rework"
  14 +
  15 +config SYS_TEXT_BASE
  16 + default 0x87800000
  17 +
  18 +config MX6ULL_DDR3_VAL_TSC_REWORK
  19 + bool "Select this for the board with screen touch rework"
  20 +
  21 +config MX6ULL_DDR3_VAL_QSPIB_REWORK
  22 + bool "Select this for the board with flash on QSPI-B port rework"
  23 +
  24 +endif
board/freescale/mx6ull_ddr3_val/Makefile
Diff comments   View file @ e801931
  1 +# (C) Copyright 2016 Freescale Semiconductor, Inc.
  2 +#
  3 +# SPDX-License-Identifier: GPL-2.0+
  4 +#
  5 +
  6 +obj-y := mx6ull_ddr3_val.o
board/freescale/mx6ull_ddr3_val/imximage.cfg
Diff comments   View file @ e801931
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +#ifdef CONFIG_QSPI_BOOT
  25 +BOOT_FROM qspi
  26 +#elif defined(CONFIG_NOR_BOOT)
  27 +BOOT_FROM nor
  28 +#else
  29 +BOOT_FROM sd
  30 +#endif
  31 +
  32 +#ifdef CONFIG_USE_IMXIMG_PLUGIN
  33 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  34 +PLUGIN board/freescale/mx6ull_ddr3_val/plugin.bin 0x00907000
  35 +#else
  36 +
  37 +#ifdef CONFIG_IMX_HAB
  38 +CSF CONFIG_CSF_SIZE
  39 +#endif
  40 +
  41 +/*
  42 + * Device Configuration Data (DCD)
  43 + *
  44 + * Each entry must have the format:
  45 + * Addr-type Address Value
  46 + *
  47 + * where:
  48 + * Addr-type register length (1,2 or 4 bytes)
  49 + * Address absolute address of the register
  50 + * value value to be stored in the register
  51 + */
  52 +
  53 +DATA 4 0x020c4068 0xffffffff
  54 +DATA 4 0x020c406c 0xffffffff
  55 +DATA 4 0x020c4070 0xffffffff
  56 +DATA 4 0x020c4074 0xffffffff
  57 +DATA 4 0x020c4078 0xffffffff
  58 +DATA 4 0x020c407c 0xffffffff
  59 +DATA 4 0x020c4080 0xffffffff
  60 +
  61 +DATA 4 0x020E04B4 0x000C0000
  62 +DATA 4 0x020E04AC 0x00000000
  63 +DATA 4 0x020E027C 0x00000030
  64 +DATA 4 0x020E0250 0x00000030
  65 +DATA 4 0x020E024C 0x00000030
  66 +DATA 4 0x020E0490 0x00000030
  67 +DATA 4 0x020E0288 0x000C0030
  68 +DATA 4 0x020E0270 0x00000000
  69 +DATA 4 0x020E0260 0x00000030
  70 +DATA 4 0x020E0264 0x00000030
  71 +DATA 4 0x020E04A0 0x00000030
  72 +DATA 4 0x020E0494 0x00020000
  73 +DATA 4 0x020E0280 0x00000030
  74 +DATA 4 0x020E0284 0x00000030
  75 +DATA 4 0x020E04B0 0x00020000
  76 +DATA 4 0x020E0498 0x00000030
  77 +DATA 4 0x020E04A4 0x00000030
  78 +DATA 4 0x020E0244 0x00000030
  79 +DATA 4 0x020E0248 0x00000030
  80 +DATA 4 0x021B001C 0x00008000
  81 +DATA 4 0x021B0800 0xA1390003
  82 +DATA 4 0x021B080C 0x00150019
  83 +DATA 4 0x021B083C 0x41550153
  84 +DATA 4 0x021B0848 0x40403A3E
  85 +DATA 4 0x021B0850 0x40402F2A
  86 +DATA 4 0x021B081C 0x33333333
  87 +DATA 4 0x021B0820 0x33333333
  88 +DATA 4 0x021B082C 0xf3333333
  89 +DATA 4 0x021B0830 0xf3333333
  90 +DATA 4 0x021B08C0 0x00944009
  91 +DATA 4 0x021B08b8 0x00000800
  92 +DATA 4 0x021B0004 0x0002002D
  93 +DATA 4 0x021B0008 0x1B333030
  94 +DATA 4 0x021B000C 0x676B52F3
  95 +DATA 4 0x021B0010 0xB66D0B63
  96 +DATA 4 0x021B0014 0x01FF00DB
  97 +DATA 4 0x021B0018 0x00211740
  98 +DATA 4 0x021B001C 0x00008000
  99 +DATA 4 0x021B002C 0x000026D2
  100 +DATA 4 0x021B0030 0x006B1023
  101 +DATA 4 0x021B0040 0x0000005F
  102 +DATA 4 0x021B0000 0x85180000
  103 +DATA 4 0x021B0890 0x00400000
  104 +DATA 4 0x021B001C 0x02008032
  105 +DATA 4 0x021B001C 0x00008033
  106 +DATA 4 0x021B001C 0x00048031
  107 +DATA 4 0x021B001C 0x15208030
  108 +DATA 4 0x021B001C 0x04008040
  109 +DATA 4 0x021B0020 0x00000800
  110 +DATA 4 0x021B0818 0x00000227
  111 +DATA 4 0x021B0004 0x0002552D
  112 +DATA 4 0x021B0404 0x00011006
  113 +DATA 4 0x021B001C 0x00000000
  114 +#endif
board/freescale/mx6ull_ddr3_val/mx6ull_ddr3_val.c
Diff comments   View file @ e801931
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <asm/arch/clock.h>
  8 +#include <asm/arch/crm_regs.h>
  9 +#include <asm/arch/iomux.h>
  10 +#include <asm/arch/imx-regs.h>
  11 +#include <asm/arch/mx6-pins.h>
  12 +#include <asm/arch/sys_proto.h>
  13 +#include <asm/gpio.h>
  14 +#include <asm/mach-imx/iomux-v3.h>
  15 +#include <asm/mach-imx/boot_mode.h>
  16 +#include <asm/mach-imx/mxc_i2c.h>
  17 +#include <asm/io.h>
  18 +#include <common.h>
  19 +#include <fsl_esdhc_imx.h>
  20 +#include <i2c.h>
  21 +#include <linux/sizes.h>
  22 +#include <linux/fb.h>
  23 +#include <miiphy.h>
  24 +#include <mmc.h>
  25 +#include <mxsfb.h>
  26 +#include <netdev.h>
  27 +#include <power/pmic.h>
  28 +#include <power/pfuze100_pmic.h>
  29 +#include "../common/pfuze.h"
  30 +#include <usb.h>
  31 +#include <usb/ehci-ci.h>
  32 +#if defined(CONFIG_MXC_EPDC)
  33 +#include <lcd.h>
  34 +#include <mxc_epdc_fb.h>
  35 +#endif
  36 +#include <asm/mach-imx/video.h>
  37 +
  38 +DECLARE_GLOBAL_DATA_PTR;
  39 +
  40 +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  41 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  42 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  43 +
  44 +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  45 + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
  46 + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  47 +
  48 +#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE | \
  49 + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
  50 + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  51 +
  52 +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  53 + PAD_CTL_SPEED_HIGH | \
  54 + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  55 +
  56 +#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  57 + PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  58 +
  59 +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  60 + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
  61 +
  62 +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  63 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  64 + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  65 + PAD_CTL_ODE)
  66 +
  67 +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  68 + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  69 +
  70 +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  71 +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  72 + PAD_CTL_SRE_FAST)
  73 +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  74 +
  75 +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  76 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  77 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  78 +
  79 +#define SPI_PAD_CTRL (PAD_CTL_HYS | \
  80 + PAD_CTL_SPEED_MED | \
  81 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  82 +
  83 +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  84 + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  85 + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  86 +
  87 +#define EPDC_PAD_CTRL 0x010b1
  88 +
  89 +#ifdef CONFIG_SYS_I2C
  90 +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  91 +/* I2C1 for PMIC and EEPROM */
  92 +struct i2c_pads_info i2c_pad_info1 = {
  93 + .scl = {
  94 + /* conflict with usb_otg2_pwr */
  95 + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
  96 + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
  97 + .gp = IMX_GPIO_NR(1, 2),
  98 + },
  99 + .sda = {
  100 + /* conflict with usb_otg2_oc */
  101 + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
  102 + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
  103 + .gp = IMX_GPIO_NR(1, 3),
  104 + },
  105 +};
  106 +#endif
  107 +
  108 +int dram_init(void)
  109 +{
  110 + gd->ram_size = PHYS_SDRAM_SIZE;
  111 +
  112 + return 0;
  113 +}
  114 +
  115 +static iomux_v3_cfg_t const uart1_pads[] = {
  116 + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  117 + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  118 +};
  119 +
  120 +#ifdef CONFIG_MX6ULL_DDR3_VAL_EMMC_REWORK
  121 +static iomux_v3_cfg_t const usdhc1_emmc_pads[] = {
  122 + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  123 + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  124 + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  125 + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  126 + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  127 + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  128 + /*
  129 + * The following 4 pins conflicts with qspi and nand flash.
  130 + * You can comment out the following 4 pins and change
  131 + * {USDHC1_BASE_ADDR, 0, 8} -> {USDHC1_BASE_ADDR, 0, 4}
  132 + * to make emmc and qspi coexists.
  133 + */
  134 + MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  135 + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  136 + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  137 + MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  138 +
  139 + /* Default NO WP for emmc, since we use pull down */
  140 + MX6_PAD_UART1_CTS_B__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL_WP),
  141 + /* RST_B */
  142 + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
  143 +};
  144 +#else
  145 +static iomux_v3_cfg_t const usdhc1_pads[] = {
  146 + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  147 + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  148 + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  149 + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  150 + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  151 + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  152 + MX6_PAD_UART1_CTS_B__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  153 +
  154 + /* VSELECT */
  155 + MX6_PAD_GPIO1_IO05__GPIO1_IO05 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  156 + /* CD */
  157 + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
  158 + /* RST_B */
  159 + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
  160 +};
  161 +#endif
  162 +
  163 +#if !defined(CONFIG_NAND_MXS) && !defined(CONFIG_MX6ULL_DDR3_VAL_QSPIB_REWORK)
  164 +static iomux_v3_cfg_t const usdhc2_pads[] = {
  165 + /* usdhc2_clk, nand_re_b, qspi1b_clk */
  166 + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  167 + /* usdhc2_cmd, nand_we_b, qspi1b_cs0_b */
  168 + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  169 + /* usdhc2_data0, nand_data0, qspi1b_cs1_b */
  170 + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  171 + /* usdhc2_data1, nand_data1 */
  172 + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  173 + /* usdhc2_data2, nand_data2, qspi1b_dat0 */
  174 + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  175 + /* usdhc2_data3, nand_data3, qspi1b_dat1 */
  176 + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  177 +
  178 + /*
  179 + * VSELECT
  180 + * Conflicts with WDOG1, so default disabled.
  181 + * MX6_PAD_GPIO1_IO08__USDHC2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  182 + */
  183 + /*
  184 + * CD
  185 + * Share with sdhc1
  186 + * MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
  187 + */
  188 + /*
  189 + * RST_B
  190 + * Pin conflicts with NAND ALE, if want to test nand,
  191 + * Connect R169(B), disconnect R169(A).
  192 + */
  193 + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  194 +};
  195 +#endif
  196 +
  197 +#ifdef CONFIG_NAND_MXS
  198 +static iomux_v3_cfg_t const nand_pads[] = {
  199 + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  200 + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  201 + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  202 + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  203 + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  204 + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  205 + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  206 + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  207 + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  208 + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  209 + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  210 + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  211 + MX6_PAD_CSI_MCLK__RAWNAND_CE2_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  212 + MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  213 + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  214 + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  215 + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  216 + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  217 + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  218 +};
  219 +
  220 +static void setup_gpmi_nand(void)
  221 +{
  222 + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  223 +
  224 + /* config gpmi nand iomux */
  225 + SETUP_IOMUX_PADS(nand_pads);
  226 +
  227 + setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  228 + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  229 + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
  230 +
  231 + /* enable apbh clock gating */
  232 + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  233 +}
  234 +#endif
  235 +
  236 +#ifdef CONFIG_MXC_SPI
  237 +#ifndef CONFIG_DM_SPI
  238 +static iomux_v3_cfg_t const ecspi1_pads[] = {
  239 + MX6_PAD_CSI_DATA06__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  240 + MX6_PAD_CSI_DATA04__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  241 + MX6_PAD_CSI_DATA07__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  242 +
  243 + /* CS Pin */
  244 + MX6_PAD_CSI_DATA05__GPIO4_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL),
  245 +};
  246 +
  247 +static void setup_spinor(void)
  248 +{
  249 + SETUP_IOMUX_PADS(ecspi1_pads);
  250 + gpio_request(IMX_GPIO_NR(4, 26), "escpi cs");
  251 + gpio_direction_output(IMX_GPIO_NR(4, 26), 0);
  252 +}
  253 +
  254 +int board_spi_cs_gpio(unsigned bus, unsigned cs)
  255 +{
  256 + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 26)) : -1;
  257 +}
  258 +#endif
  259 +#endif
  260 +
  261 +#ifdef CONFIG_FEC_MXC
  262 +/*
  263 + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
  264 + * be used for ENET1 or ENET2, cannot be used for both.
  265 + */
  266 +static iomux_v3_cfg_t const fec1_pads[] = {
  267 + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  268 + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  269 + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  270 + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  271 + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  272 + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  273 + /* Pin conflicts with LCD PWM1 */
  274 + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  275 + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  276 + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
  277 + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  278 +};
  279 +
  280 +static iomux_v3_cfg_t const fec1_phy_rst[] = {
  281 + /*
  282 + * ALT5 mode is only valid when TAMPER pin is used for GPIO.
  283 + * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0].
  284 + *
  285 + * ENET1_RST
  286 + */
  287 + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  288 +};
  289 +
  290 +static iomux_v3_cfg_t const fec2_pads[] = {
  291 + MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  292 + MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  293 +
  294 + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  295 + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  296 + MX6_PAD_UART3_TX_DATA__ENET2_RDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  297 + MX6_PAD_UART3_RX_DATA__ENET2_RDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  298 + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  299 + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
  300 + MX6_PAD_UART3_CTS_B__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  301 +
  302 + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  303 + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  304 + MX6_PAD_UART4_TX_DATA__ENET2_TDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  305 + MX6_PAD_UART4_RX_DATA__ENET2_TDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  306 + MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  307 + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  308 +
  309 + MX6_PAD_UART5_RX_DATA__ENET2_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  310 + MX6_PAD_UART5_TX_DATA__ENET2_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
  311 +};
  312 +
  313 +static iomux_v3_cfg_t const fec2_phy_rst[] = {
  314 + /*
  315 + * ENET2_RST
  316 + *
  317 + * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0]
  318 + */
  319 + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  320 +};
  321 +
  322 +static void setup_iomux_fec(int fec_id)
  323 +{
  324 + if (fec_id == 0) {
  325 + SETUP_IOMUX_PADS(fec1_pads);
  326 + } else {
  327 + SETUP_IOMUX_PADS(fec2_pads);
  328 + }
  329 +}
  330 +#endif
  331 +
  332 +static void setup_iomux_uart(void)
  333 +{
  334 + SETUP_IOMUX_PADS(uart1_pads);
  335 +}
  336 +
  337 +#ifdef CONFIG_FSL_QSPI
  338 +
  339 +#ifndef CONFIG_DM_SPI
  340 +#define QSPI_PAD_CTRL1 \
  341 + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
  342 + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
  343 +
  344 +static iomux_v3_cfg_t const quadspi_pads[] = {
  345 + MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  346 + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  347 + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  348 + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  349 + MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  350 + MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  351 + MX6_PAD_NAND_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  352 +
  353 +#ifdef CONFIG_MX6ULL_DDR3_VAL_QSPIB_REWORK
  354 + MX6_PAD_NAND_RE_B__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  355 + MX6_PAD_NAND_WE_B__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  356 + MX6_PAD_NAND_DATA00__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  357 + MX6_PAD_NAND_DATA02__QSPI_B_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  358 + MX6_PAD_NAND_DATA03__QSPI_B_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  359 + MX6_PAD_NAND_DATA04__QSPI_B_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  360 + MX6_PAD_NAND_DATA05__QSPI_B_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  361 +#endif
  362 +};
  363 +#endif
  364 +
  365 +int board_qspi_init(void)
  366 +{
  367 +#ifndef CONFIG_DM_SPI
  368 + /* Set the iomux */
  369 + SETUP_IOMUX_PADS(quadspi_pads);
  370 +#endif
  371 + /* Set the clock */
  372 + enable_qspi_clk(0);
  373 +
  374 + return 0;
  375 +}
  376 +#endif
  377 +
  378 +#ifdef CONFIG_FSL_ESDHC
  379 +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  380 +#ifdef CONFIG_MX6ULL_DDR3_VAL_EMMC_REWORK
  381 + /* If want to use qspi, should change to 4 bit width */
  382 + {USDHC1_BASE_ADDR, 0, 8},
  383 +#else
  384 + {USDHC1_BASE_ADDR, 0, 4},
  385 +#endif
  386 +#if !defined(CONFIG_NAND_MXS) && !defined(CONFIG_MX6ULL_DDR3_VAL_QSPIB_REWORK)
  387 + {USDHC2_BASE_ADDR, 0, 4},
  388 +#endif
  389 +};
  390 +
  391 +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
  392 +#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
  393 +#define USDHC1_VSELECT IMX_GPIO_NR(1, 5)
  394 +#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
  395 +
  396 +int board_mmc_getcd(struct mmc *mmc)
  397 +{
  398 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  399 + int ret = 0;
  400 +
  401 + switch (cfg->esdhc_base) {
  402 + case USDHC1_BASE_ADDR:
  403 +#ifdef CONFIG_MX6ULL_DDR3_VAL_EMMC_REWORK
  404 + ret = 1;
  405 +#else
  406 + ret = !gpio_get_value(USDHC1_CD_GPIO);
  407 +#endif
  408 + break;
  409 +#if !defined(CONFIG_NAND_MXS) && !defined(CONFIG_MX6ULL_DDR3_VAL_QSPIB_REWORK)
  410 + case USDHC2_BASE_ADDR:
  411 + ret = 1;
  412 + break;
  413 +#endif
  414 + }
  415 +
  416 + return ret;
  417 +}
  418 +
  419 +int board_mmc_init(bd_t *bis)
  420 +{
  421 + int i;
  422 +
  423 + /*
  424 + * According to the board_mmc_init() the following map is done:
  425 + * (U-boot device node) (Physical Port)
  426 + * mmc0 USDHC1
  427 + * mmc1 USDHC2
  428 + */
  429 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  430 + switch (i) {
  431 + case 0:
  432 +#ifdef CONFIG_MX6ULL_DDR3_VAL_EMMC_REWORK
  433 + SETUP_IOMUX_PADS(usdhc1_emmc_pads);
  434 +#else
  435 + SETUP_IOMUX_PADS(usdhc1_pads);
  436 + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
  437 + gpio_direction_input(USDHC1_CD_GPIO);
  438 +#endif
  439 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  440 + /* 3.3V */
  441 + gpio_request(USDHC1_VSELECT, "usdhc1 vsel");
  442 + gpio_request(USDHC1_PWR_GPIO, "usdhc1 pwr");
  443 + gpio_direction_output(USDHC1_VSELECT, 0);
  444 + gpio_direction_output(USDHC1_PWR_GPIO, 1);
  445 + break;
  446 +#if !defined(CONFIG_NAND_MXS) && !defined(CONFIG_MX6ULL_DDR3_VAL_QSPIB_REWORK)
  447 + case 1:
  448 + SETUP_IOMUX_PADS(usdhc2_pads);
  449 + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr");
  450 + gpio_direction_output(USDHC2_PWR_GPIO, 1);
  451 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  452 + break;
  453 +#endif
  454 + default:
  455 + printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
  456 + return 0;
  457 + }
  458 +
  459 + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
  460 + printf("Warning: failed to initialize mmc dev %d\n", i);
  461 + }
  462 +
  463 + return 0;
  464 +}
  465 +#endif
  466 +
  467 +#ifdef CONFIG_VIDEO_MXS
  468 +static iomux_v3_cfg_t const lcd_pads[] = {
  469 + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
  470 + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
  471 + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  472 + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  473 + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  474 + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  475 + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  476 + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  477 + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  478 + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  479 + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  480 + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  481 + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  482 + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  483 + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  484 + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  485 + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  486 + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  487 + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  488 + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  489 + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  490 + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  491 + MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  492 + MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  493 + MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  494 + MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  495 + MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  496 + MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  497 + MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  498 +
  499 + /*
  500 + * PWM1, pin conflicts with ENET1_RX_DATA0
  501 + * Use GPIO for Brightness adjustment, duty cycle = period.
  502 + */
  503 + /* MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),*/
  504 +};
  505 +
  506 +struct lcd_panel_info_t {
  507 + unsigned int lcdif_base_addr;
  508 + int depth;
  509 + void (*enable)(struct lcd_panel_info_t const *dev);
  510 + struct fb_videomode mode;
  511 +};
  512 +
  513 +void do_enable_parallel_lcd(struct display_info_t const *dev)
  514 +{
  515 + enable_lcdif_clock(dev->bus, 1);
  516 +
  517 + SETUP_IOMUX_PADS(lcd_pads);
  518 +
  519 + /* Power up the LCD */
  520 + gpio_request(IMX_GPIO_NR(3, 4), "lcd power");
  521 + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
  522 +
  523 + /* Set Brightness to high */
  524 + /* gpio_direction_output(IMX_GPIO_NR(2, 0) , 1); */
  525 +}
  526 +
  527 +struct display_info_t const displays[] = {{
  528 + .bus = MX6ULL_LCDIF1_BASE_ADDR,
  529 + .addr = 0,
  530 + .pixfmt = 24,
  531 + .detect = NULL,
  532 + .enable = do_enable_parallel_lcd,
  533 + .mode = {
  534 + .name = "MCIMX28LCD",
  535 + .xres = 800,
  536 + .yres = 480,
  537 + .pixclock = 29850,
  538 + .left_margin = 89,
  539 + .right_margin = 164,
  540 + .upper_margin = 23,
  541 + .lower_margin = 10,
  542 + .hsync_len = 10,
  543 + .vsync_len = 10,
  544 + .sync = 0,
  545 + .vmode = FB_VMODE_NONINTERLACED
  546 +} } };
  547 +size_t display_count = ARRAY_SIZE(displays);
  548 +#endif
  549 +
  550 +#ifdef CONFIG_MXC_EPDC
  551 +static iomux_v3_cfg_t const epdc_enable_pads[] = {
  552 + MX6_PAD_ENET2_RX_DATA0__EPDC_SDDO08 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  553 + MX6_PAD_ENET2_RX_DATA1__EPDC_SDDO09 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  554 + MX6_PAD_ENET2_RX_EN__EPDC_SDDO10 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  555 + MX6_PAD_ENET2_TX_DATA0__EPDC_SDDO11 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  556 + MX6_PAD_ENET2_TX_DATA1__EPDC_SDDO12 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  557 + MX6_PAD_ENET2_TX_EN__EPDC_SDDO13 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  558 + MX6_PAD_ENET2_TX_CLK__EPDC_SDDO14 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  559 + MX6_PAD_ENET2_RX_ER__EPDC_SDDO15 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  560 + MX6_PAD_LCD_CLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  561 + MX6_PAD_LCD_ENABLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  562 + MX6_PAD_LCD_HSYNC__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  563 + MX6_PAD_LCD_VSYNC__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  564 + MX6_PAD_LCD_DATA00__EPDC_SDDO00 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  565 + MX6_PAD_LCD_DATA01__EPDC_SDDO01 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  566 + MX6_PAD_LCD_DATA02__EPDC_SDDO02 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  567 + MX6_PAD_LCD_DATA03__EPDC_SDDO03 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  568 + MX6_PAD_LCD_DATA04__EPDC_SDDO04 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  569 + MX6_PAD_LCD_DATA05__EPDC_SDDO05 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  570 + MX6_PAD_LCD_DATA06__EPDC_SDDO06 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  571 + MX6_PAD_LCD_DATA07__EPDC_SDDO07 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  572 + MX6_PAD_LCD_DATA14__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  573 + MX6_PAD_LCD_DATA15__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  574 + MX6_PAD_LCD_DATA16__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  575 + MX6_PAD_LCD_DATA17__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  576 + MX6_PAD_LCD_RESET__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  577 +};
  578 +
  579 +static iomux_v3_cfg_t const epdc_disable_pads[] = {
  580 + MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08,
  581 + MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09,
  582 + MX6_PAD_ENET2_RX_EN__GPIO2_IO10,
  583 + MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11,
  584 + MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12,
  585 + MX6_PAD_ENET2_TX_EN__GPIO2_IO13,
  586 + MX6_PAD_ENET2_TX_CLK__GPIO2_IO14,
  587 + MX6_PAD_ENET2_RX_ER__GPIO2_IO15,
  588 + MX6_PAD_LCD_CLK__GPIO3_IO00,
  589 + MX6_PAD_LCD_ENABLE__GPIO3_IO01,
  590 + MX6_PAD_LCD_HSYNC__GPIO3_IO02,
  591 + MX6_PAD_LCD_VSYNC__GPIO3_IO03,
  592 + MX6_PAD_LCD_DATA00__GPIO3_IO05,
  593 + MX6_PAD_LCD_DATA01__GPIO3_IO06,
  594 + MX6_PAD_LCD_DATA02__GPIO3_IO07,
  595 + MX6_PAD_LCD_DATA03__GPIO3_IO08,
  596 + MX6_PAD_LCD_DATA04__GPIO3_IO09,
  597 + MX6_PAD_LCD_DATA05__GPIO3_IO10,
  598 + MX6_PAD_LCD_DATA06__GPIO3_IO11,
  599 + MX6_PAD_LCD_DATA07__GPIO3_IO12,
  600 + MX6_PAD_LCD_DATA14__GPIO3_IO19,
  601 + MX6_PAD_LCD_DATA15__GPIO3_IO20,
  602 + MX6_PAD_LCD_DATA16__GPIO3_IO21,
  603 + MX6_PAD_LCD_DATA17__GPIO3_IO22,
  604 + MX6_PAD_LCD_RESET__GPIO3_IO04,
  605 +};
  606 +
  607 +vidinfo_t panel_info = {
  608 + .vl_refresh = 85,
  609 + .vl_col = 1024,
  610 + .vl_row = 758,
  611 + .vl_pixclock = 40000000,
  612 + .vl_left_margin = 12,
  613 + .vl_right_margin = 76,
  614 + .vl_upper_margin = 4,
  615 + .vl_lower_margin = 5,
  616 + .vl_hsync = 12,
  617 + .vl_vsync = 2,
  618 + .vl_sync = 0,
  619 + .vl_mode = 0,
  620 + .vl_flag = 0,
  621 + .vl_bpix = 3,
  622 + .cmap = 0,
  623 +};
  624 +
  625 +struct epdc_timing_params panel_timings = {
  626 + .vscan_holdoff = 4,
  627 + .sdoed_width = 10,
  628 + .sdoed_delay = 20,
  629 + .sdoez_width = 10,
  630 + .sdoez_delay = 20,
  631 + .gdclk_hp_offs = 524,
  632 + .gdsp_offs = 327,
  633 + .gdoe_offs = 0,
  634 + .gdclk_offs = 19,
  635 + .num_ce = 1,
  636 +};
  637 +
  638 +static iomux_v3_cfg_t const epdc_pwr_ctrl_pads[] = {
  639 + IOMUX_PADS(PAD_LCD_DATA11__GPIO3_IO16 | MUX_PAD_CTRL(EPDC_PAD_CTRL)),
  640 + IOMUX_PADS(PAD_LCD_DATA19__GPIO3_IO24 | MUX_PAD_CTRL(EPDC_PAD_CTRL)),
  641 + IOMUX_PADS(PAD_LCD_DATA09__GPIO3_IO14 | MUX_PAD_CTRL(EPDC_PAD_CTRL)),
  642 + IOMUX_PADS(PAD_LCD_DATA12__GPIO3_IO17 | MUX_PAD_CTRL(EPDC_PAD_CTRL)),
  643 +};
  644 +
  645 +static void setup_epdc_power(void)
  646 +{
  647 + SETUP_IOMUX_PADS(epdc_pwr_ctrl_pads);
  648 +
  649 + /* Setup epdc voltage */
  650 +
  651 + /* EPDC_PWRSTAT - GPIO3[16] for PWR_GOOD status */
  652 + gpio_request(IMX_GPIO_NR(3, 16), "EPDC_PWRSTAT");
  653 + gpio_direction_input(IMX_GPIO_NR(3, 16));
  654 +
  655 + /* EPDC_VCOM0 - GPIO3[24] for VCOM control */
  656 + /* Set as output */
  657 + gpio_request(IMX_GPIO_NR(3, 24), "EPDC_VCOM0");
  658 + gpio_direction_output(IMX_GPIO_NR(3, 24), 1);
  659 +
  660 + /* EPDC_PWRWAKEUP - GPIO3[14] for EPD PMIC WAKEUP */
  661 + /* Set as output */
  662 + gpio_request(IMX_GPIO_NR(3, 14), "EPDC_PWRWAKEUP");
  663 + gpio_direction_output(IMX_GPIO_NR(3, 14), 1);
  664 +
  665 + /* EPDC_PWRCTRL0 - GPIO3[17] for EPD PWR CTL0 */
  666 + /* Set as output */
  667 + gpio_request(IMX_GPIO_NR(3, 17), "EPDC_PWRCTRL0");
  668 + gpio_direction_output(IMX_GPIO_NR(3, 17), 1);
  669 +}
  670 +
  671 +static void epdc_enable_pins(void)
  672 +{
  673 + /* epdc iomux settings */
  674 + SETUP_IOMUX_PADS(epdc_enable_pads);
  675 +}
  676 +
  677 +static void epdc_disable_pins(void)
  678 +{
  679 + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */
  680 + SETUP_IOMUX_PADS(epdc_disable_pads);
  681 +}
  682 +
  683 +static void setup_epdc(void)
  684 +{
  685 + /* Set pixel clock rates for EPDC in clock.c */
  686 +
  687 + panel_info.epdc_data.wv_modes.mode_init = 0;
  688 + panel_info.epdc_data.wv_modes.mode_du = 1;
  689 + panel_info.epdc_data.wv_modes.mode_gc4 = 3;
  690 + panel_info.epdc_data.wv_modes.mode_gc8 = 2;
  691 + panel_info.epdc_data.wv_modes.mode_gc16 = 2;
  692 + panel_info.epdc_data.wv_modes.mode_gc32 = 2;
  693 +
  694 + panel_info.epdc_data.epdc_timings = panel_timings;
  695 +
  696 + setup_epdc_power();
  697 +}
  698 +
  699 +void epdc_power_on(void)
  700 +{
  701 + unsigned int reg;
  702 + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO3_BASE_ADDR;
  703 +
  704 + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
  705 + gpio_set_value(IMX_GPIO_NR(3, 17), 1);
  706 + udelay(1000);
  707 +
  708 + /* Enable epdc signal pin */
  709 + epdc_enable_pins();
  710 +
  711 + /* Set PMIC Wakeup to high - enable Display power */
  712 + gpio_set_value(IMX_GPIO_NR(3, 14), 1);
  713 +
  714 + /* Wait for PWRGOOD == 1 */
  715 + while (1) {
  716 + reg = readl(&gpio_regs->gpio_psr);
  717 + if (!(reg & (1 << 16)))
  718 + break;
  719 +
  720 + udelay(100);
  721 + }
  722 +
  723 + /* Enable VCOM */
  724 + gpio_set_value(IMX_GPIO_NR(3, 24), 1);
  725 +
  726 + udelay(500);
  727 +}
  728 +
  729 +void epdc_power_off(void)
  730 +{
  731 + /* Set PMIC Wakeup to low - disable Display power */
  732 + gpio_set_value(IMX_GPIO_NR(3, 14), 0);
  733 +
  734 + /* Disable VCOM */
  735 + gpio_set_value(IMX_GPIO_NR(3, 24), 0);
  736 +
  737 + epdc_disable_pins();
  738 +
  739 + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
  740 + gpio_set_value(IMX_GPIO_NR(3, 17), 0);
  741 +}
  742 +#endif
  743 +
  744 +#ifdef CONFIG_FEC_MXC
  745 +int board_eth_init(bd_t *bis)
  746 +{
  747 + int ret;
  748 +
  749 + setup_iomux_fec(CONFIG_FEC_ENET_DEV);
  750 +
  751 + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
  752 + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
  753 + if (ret)
  754 + printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__);
  755 +
  756 + return 0;
  757 +}
  758 +
  759 +static int setup_fec(int fec_id)
  760 +{
  761 + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  762 + = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  763 + int ret;
  764 +
  765 + if (0 == fec_id) {
  766 + if (check_module_fused(MX6_MODULE_ENET1))
  767 + return -1;
  768 + /*
  769 + * Use 50M anatop loopback REF_CLK1 for ENET1,
  770 + * clear gpr1[13], set gpr1[17]
  771 + */
  772 + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  773 + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
  774 + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
  775 + if (ret)
  776 + return ret;
  777 +
  778 + SETUP_IOMUX_PADS(fec1_phy_rst);
  779 + gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset");
  780 + gpio_direction_output(IMX_GPIO_NR(5, 2), 0);
  781 + udelay(50);
  782 + gpio_direction_output(IMX_GPIO_NR(5, 2), 1);
  783 +
  784 + } else {
  785 + if (check_module_fused(MX6_MODULE_ENET2))
  786 + return -1;
  787 +
  788 + /* clk from phy, set gpr1[14], clear gpr1[18]*/
  789 + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
  790 + IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK);
  791 +
  792 + SETUP_IOMUX_PADS(fec2_phy_rst);
  793 + gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset");
  794 + gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
  795 + udelay(50);
  796 + gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
  797 + }
  798 +
  799 + enable_enet_clk(1);
  800 +
  801 + return 0;
  802 +}
  803 +
  804 +int board_phy_config(struct phy_device *phydev)
  805 +{
  806 + if (CONFIG_FEC_ENET_DEV == 0) {
  807 + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x202);
  808 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
  809 + } else if (CONFIG_FEC_ENET_DEV == 1) {
  810 + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x201);
  811 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8110);
  812 + }
  813 +
  814 + if (phydev->drv->config)
  815 + phydev->drv->config(phydev);
  816 +
  817 + return 0;
  818 +}
  819 +#endif
  820 +
  821 +#ifdef CONFIG_POWER
  822 +#define I2C_PMIC 0
  823 +static struct pmic *pfuze;
  824 +int power_init_board(void)
  825 +{
  826 + int ret;
  827 + u32 rev_id, value;
  828 +
  829 + ret = power_pfuze100_init(I2C_PMIC);
  830 + if (ret)
  831 + return ret;
  832 +
  833 + pfuze = pmic_get("PFUZE100");
  834 + if (!pfuze)
  835 + return -ENODEV;
  836 +
  837 + ret = pmic_probe(pfuze);
  838 + if (ret)
  839 + return ret;
  840 +
  841 + ret = pfuze_mode_init(pfuze, APS_PFM);
  842 + if (ret < 0)
  843 + return ret;
  844 +
  845 + pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value);
  846 + pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id);
  847 + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id);
  848 +
  849 + /*
  850 + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP
  851 + * Configuration is F0.
  852 + * Default VOLT:
  853 + * VSNVS_VOLT | 3.0V
  854 + * SW1AB | 1.375V
  855 + * SW2 | 3.3V
  856 + * SW3A | 1.5V
  857 + * SW3B | 1.5V
  858 + * VGEN1 | 1.5V
  859 + * VGEN2 | 1.5V
  860 + * VGEN3 | 2.5V
  861 + * VGEN4 | 1.8V
  862 + * VGEN5 | 2.8V
  863 + * VGEN6 | 3.3V
  864 + *
  865 + * According to schematic, we need SW3A 1.35V, SW3B 3.3V,
  866 + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V,
  867 + * VGEN5 3.3V, VGEN6 3.0V.
  868 + *
  869 + * Here we just use the default VOLT, but not configure
  870 + * them, when needed, configure them to our requested voltage.
  871 + */
  872 +
  873 + /* set SW1AB standby volatage 0.975V */
  874 + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value);
  875 + value &= ~0x3f;
  876 + value |= PFUZE100_SW1ABC_SETP(9750);
  877 + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value);
  878 +
  879 + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
  880 + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value);
  881 + value &= ~0xc0;
  882 + value |= 0x40;
  883 + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value);
  884 +
  885 + /* Enable power of VGEN5 3V3 */
  886 + pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &value);
  887 + value &= ~0x1F;
  888 + value |= 0x1F;
  889 + pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, value);
  890 +
  891 + return 0;
  892 +}
  893 +
  894 +#ifdef CONFIG_LDO_BYPASS_CHECK
  895 +void ldo_mode_set(int ldo_bypass)
  896 +{
  897 + unsigned int value;
  898 + int is_400M;
  899 + u32 vddarm;
  900 +
  901 + struct pmic *p = pfuze;
  902 +
  903 + if (!p) {
  904 + printf("No PMIC found!\n");
  905 + return;
  906 + }
  907 +
  908 + /* switch to ldo_bypass mode */
  909 + if (ldo_bypass) {
  910 + prep_anatop_bypass();
  911 + /* decrease VDDARM to 1.275V */
  912 + pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value);
  913 + value &= ~0x3f;
  914 + value |= PFUZE100_SW1ABC_SETP(12750);
  915 + pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value);
  916 +
  917 + is_400M = set_anatop_bypass(1);
  918 + if (is_400M)
  919 + vddarm = PFUZE100_SW1ABC_SETP(10750);
  920 + else
  921 + vddarm = PFUZE100_SW1ABC_SETP(11750);
  922 +
  923 + pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value);
  924 + value &= ~0x3f;
  925 + value |= vddarm;
  926 + pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value);
  927 +
  928 + finish_anatop_bypass();
  929 +
  930 + printf("switch to ldo_bypass mode!\n");
  931 + }
  932 +}
  933 +#endif
  934 +
  935 +#elif defined(CONFIG_DM_PMIC_PFUZE100)
  936 +int power_init_board(void)
  937 +{
  938 + struct udevice *dev;
  939 + int ret;
  940 + unsigned int reg, dev_id, rev_id;
  941 +
  942 + ret = pmic_get("pfuze100@8", &dev);
  943 + if (ret == -ENODEV)
  944 + return ret;
  945 +
  946 + ret = pfuze_mode_init(dev, APS_PFM);
  947 + if (ret < 0)
  948 + return ret;
  949 +
  950 + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
  951 + rev_id = pmic_reg_read(dev, PFUZE100_REVID);
  952 + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
  953 +
  954 + /*
  955 + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP
  956 + * Configuration is F0.
  957 + * Default VOLT:
  958 + * VSNVS_VOLT | 3.0V
  959 + * SW1AB | 1.375V
  960 + * SW2 | 3.3V
  961 + * SW3A | 1.5V
  962 + * SW3B | 1.5V
  963 + * VGEN1 | 1.5V
  964 + * VGEN2 | 1.5V
  965 + * VGEN3 | 2.5V
  966 + * VGEN4 | 1.8V
  967 + * VGEN5 | 2.8V
  968 + * VGEN6 | 3.3V
  969 + *
  970 + * According to schematic, we need SW3A 1.35V, SW3B 3.3V,
  971 + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V,
  972 + * VGEN5 3.3V, VGEN6 3.0V.
  973 + *
  974 + * Here we just use the default VOLT, but not configure
  975 + * them, when needed, configure them to our requested voltage.
  976 + */
  977 +
  978 + /* Set SW1AB stanby volage to 0.975V */
  979 + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
  980 + reg &= ~SW1x_STBY_MASK;
  981 + reg |= SW1x_0_975V;
  982 + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
  983 +
  984 + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
  985 + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
  986 + reg &= ~SW1xCONF_DVSSPEED_MASK;
  987 + reg |= SW1xCONF_DVSSPEED_4US;
  988 + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
  989 +
  990 + /* Enable power of VGEN5 3V3 */
  991 + reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
  992 + reg &= ~0x1F;
  993 + reg |= 0x1F;
  994 + pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
  995 +
  996 + return 0;
  997 +}
  998 +
  999 +#ifdef CONFIG_LDO_BYPASS_CHECK
  1000 +void ldo_mode_set(int ldo_bypass)
  1001 +{
  1002 + struct udevice *dev;
  1003 + int ret;
  1004 + int is_400M;
  1005 + u32 vddarm;
  1006 +
  1007 + ret = pmic_get("pfuze100", &dev);
  1008 + if (ret == -ENODEV) {
  1009 + printf("No PMIC found!\n");
  1010 + return;
  1011 + }
  1012 +
  1013 + /* switch to ldo_bypass mode */
  1014 + if (ldo_bypass) {
  1015 + /* decrease VDDARM to 1.275V */
  1016 + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750));
  1017 +
  1018 + is_400M = set_anatop_bypass(1);
  1019 + if (is_400M)
  1020 + vddarm = PFUZE100_SW1ABC_SETP(10750);
  1021 + else
  1022 + vddarm = PFUZE100_SW1ABC_SETP(11750);
  1023 +
  1024 + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);
  1025 +
  1026 + set_anatop_bypass(1);
  1027 +
  1028 + printf("switch to ldo_bypass mode!\n");
  1029 + }
  1030 +}
  1031 +#endif
  1032 +
  1033 +#endif
  1034 +
  1035 +int board_early_init_f(void)
  1036 +{
  1037 + setup_iomux_uart();
  1038 +
  1039 + return 0;
  1040 +}
  1041 +
  1042 +int board_init(void)
  1043 +{
  1044 + /* Address of boot parameters */
  1045 + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  1046 +
  1047 +#ifdef CONFIG_SYS_I2C
  1048 + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  1049 +#endif
  1050 +
  1051 +#ifdef CONFIG_FEC_MXC
  1052 + setup_fec(CONFIG_FEC_ENET_DEV);
  1053 +#endif
  1054 +
  1055 +#ifdef CONFIG_MXC_SPI
  1056 +#ifndef CONFIG_DM_SPI
  1057 + setup_spinor();
  1058 +#endif
  1059 +#endif
  1060 +
  1061 +#ifdef CONFIG_NAND_MXS
  1062 + setup_gpmi_nand();
  1063 +#endif
  1064 +
  1065 +#ifdef CONFIG_FSL_QSPI
  1066 + board_qspi_init();
  1067 +#endif
  1068 +
  1069 +#ifdef CONFIG_MXC_EPDC
  1070 + enable_epdc_clock();
  1071 + setup_epdc();
  1072 +#endif
  1073 +
  1074 + return 0;
  1075 +}
  1076 +
  1077 +#ifdef CONFIG_CMD_BMODE
  1078 +static const struct boot_mode board_boot_modes[] = {
  1079 + /* 4 bit bus width */
  1080 + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
  1081 + {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
  1082 + {NULL, 0},
  1083 +};
  1084 +#endif
  1085 +
  1086 +int board_late_init(void)
  1087 +{
  1088 +#ifdef CONFIG_CMD_BMODE
  1089 + add_board_boot_modes(board_boot_modes);
  1090 +#endif
  1091 +
  1092 +#ifdef CONFIG_ENV_IS_IN_MMC
  1093 + board_late_mmc_env_init();
  1094 +#endif
  1095 +
  1096 + return 0;
  1097 +}
  1098 +
  1099 +u32 get_board_rev(void)
  1100 +{
  1101 + return get_cpu_rev();
  1102 +}
  1103 +
  1104 +int checkboard(void)
  1105 +{
  1106 + puts("Board: MX6ULL 14X14 DDR3 Validation\n");
  1107 +
  1108 + return 0;
  1109 +}
  1110 +
  1111 +#ifdef CONFIG_USB_EHCI_MX6
  1112 +#ifndef CONFIG_DM_USB
  1113 +
  1114 +#define USB_OTHERREGS_OFFSET 0x800
  1115 +#define UCTRL_PWR_POL (1 << 9)
  1116 +iomux_v3_cfg_t const usb_otg1_pads[] = {
  1117 + MX6_PAD_GPIO1_IO04__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  1118 + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
  1119 +};
  1120 +
  1121 +/*
  1122 + * Leave it here, but default configuration only supports 1 port now,
  1123 + * because we need sd1 and i2c1
  1124 + */
  1125 +iomux_v3_cfg_t const usb_otg2_pads[] = {
  1126 + /* conflict with i2c1_scl */
  1127 + MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  1128 + /* conflict with sd1_vselect */
  1129 + MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
  1130 +};
  1131 +
  1132 +int board_usb_phy_mode(int port)
  1133 +{
  1134 + return usb_phy_mode(port);
  1135 +}
  1136 +
  1137 +int board_ehci_hcd_init(int port)
  1138 +{
  1139 + u32 *usbnc_usb_ctrl;
  1140 +
  1141 + if (port > 1)
  1142 + return -EINVAL;
  1143 +
  1144 + switch (port) {
  1145 + case 0:
  1146 + SETUP_IOMUX_PADS(usb_otg1_pads);
  1147 + break;
  1148 + case 1:
  1149 + SETUP_IOMUX_PADS(usb_otg2_pads);
  1150 + break;
  1151 + default:
  1152 + printf("MXC USB port %d not yet supported\n", port);
  1153 + return 1;
  1154 + }
  1155 +
  1156 + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
  1157 + port * 4);
  1158 +
  1159 + /* Set Power polarity */
  1160 + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
  1161 +
  1162 + return 0;
  1163 +}
  1164 +#endif
  1165 +#endif
board/freescale/mx6ull_ddr3_val/plugin.S
Diff comments   View file @ e801931
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <config.h>
  8 +
  9 +/* DDR script */
  10 +.macro imx6ull_ddr3_val_setting
  11 + ldr r0, =IOMUXC_BASE_ADDR
  12 + ldr r1, =0x000C0000
  13 + str r1, [r0, #0x4B4]
  14 + ldr r1, =0x00000000
  15 + str r1, [r0, #0x4AC]
  16 + ldr r1, =0x00000030
  17 + str r1, [r0, #0x27C]
  18 + str r1, [r0, #0x250]
  19 + str r1, [r0, #0x24C]
  20 + str r1, [r0, #0x490]
  21 + ldr r1, =0x000C0030
  22 + str r1, [r0, #0x288]
  23 +
  24 + ldr r1, =0x00000000
  25 + str r1, [r0, #0x270]
  26 +
  27 + ldr r1, =0x00000030
  28 + str r1, [r0, #0x260]
  29 + str r1, [r0, #0x264]
  30 + str r1, [r0, #0x4A0]
  31 +
  32 + ldr r1, =0x00020000
  33 + str r1, [r0, #0x494]
  34 +
  35 + ldr r1, =0x00000030
  36 + str r1, [r0, #0x280]
  37 + str r1, [r0, #0x284]
  38 +
  39 + ldr r1, =0x00020000
  40 + str r1, [r0, #0x4B0]
  41 +
  42 + ldr r1, =0x00000030
  43 + str r1, [r0, #0x498]
  44 + str r1, [r0, #0x4A4]
  45 + str r1, [r0, #0x244]
  46 + str r1, [r0, #0x248]
  47 +
  48 + ldr r0, =MMDC_P0_BASE_ADDR
  49 + ldr r1, =0x00008000
  50 + str r1, [r0, #0x1C]
  51 + ldr r1, =0xA1390003
  52 + str r1, [r0, #0x800]
  53 + ldr r1, =0x00150019
  54 + str r1, [r0, #0x80C]
  55 + ldr r1, =0x41550153
  56 + str r1, [r0, #0x83C]
  57 + ldr r1, =0x40403A3E
  58 + str r1, [r0, #0x848]
  59 + ldr r1, =0x40402F2A
  60 + str r1, [r0, #0x850]
  61 + ldr r1, =0x33333333
  62 + str r1, [r0, #0x81C]
  63 + str r1, [r0, #0x820]
  64 + ldr r1, =0xF3333333
  65 + str r1, [r0, #0x82C]
  66 + str r1, [r0, #0x830]
  67 + ldr r1, =0x00944009
  68 + str r1, [r0, #0x8C0]
  69 + ldr r1, =0x00000800
  70 + str r1, [r0, #0x8B8]
  71 + ldr r1, =0x0002002D
  72 + str r1, [r0, #0x004]
  73 + ldr r1, =0x1B333030
  74 + str r1, [r0, #0x008]
  75 + ldr r1, =0x676B52F3
  76 + str r1, [r0, #0x00C]
  77 + ldr r1, =0xB66D0B63
  78 + str r1, [r0, #0x010]
  79 + ldr r1, =0x01FF00DB
  80 + str r1, [r0, #0x014]
  81 + ldr r1, =0x00211740
  82 + str r1, [r0, #0x018]
  83 + ldr r1, =0x00008000
  84 + str r1, [r0, #0x01C]
  85 + ldr r1, =0x000026D2
  86 + str r1, [r0, #0x02C]
  87 + ldr r1, =0x006B1023
  88 + str r1, [r0, #0x030]
  89 + ldr r1, =0x0000005F
  90 + str r1, [r0, #0x040]
  91 + ldr r1, =0x85180000
  92 + str r1, [r0, #0x000]
  93 + ldr r1, =0x00400000
  94 + str r1, [r0, #0x890]
  95 + ldr r1, =0x02008032
  96 + str r1, [r0, #0x01C]
  97 + ldr r1, =0x00008033
  98 + str r1, [r0, #0x01C]
  99 + ldr r1, =0x00048031
  100 + str r1, [r0, #0x01C]
  101 + ldr r1, =0x15208030
  102 + str r1, [r0, #0x01C]
  103 + ldr r1, =0x04008040
  104 + str r1, [r0, #0x01C]
  105 + ldr r1, =0x00000800
  106 + str r1, [r0, #0x020]
  107 + ldr r1, =0x00000227
  108 + str r1, [r0, #0x818]
  109 + ldr r1, =0x0002552D
  110 + str r1, [r0, #0x004]
  111 + ldr r1, =0x00011006
  112 + str r1, [r0, #0x404]
  113 + ldr r1, =0x00000000
  114 + str r1, [r0, #0x01C]
  115 +.endm
  116 +
  117 +.macro imx6_clock_gating
  118 + ldr r0, =CCM_BASE_ADDR
  119 + ldr r1, =0xFFFFFFFF
  120 + str r1, [r0, #0x68]
  121 + str r1, [r0, #0x6C]
  122 + str r1, [r0, #0x70]
  123 + str r1, [r0, #0x74]
  124 + str r1, [r0, #0x78]
  125 + str r1, [r0, #0x7C]
  126 + str r1, [r0, #0x80]
  127 +.endm
  128 +
  129 +.macro imx6_qos_setting
  130 +.endm
  131 +
  132 +.macro imx6_ddr_setting
  133 + imx6ull_ddr3_val_setting
  134 +.endm
  135 +
  136 +/* include the common plugin code here */
  137 +#include <asm/arch/mx6_plugin.S>
configs/mx6ull_14x14_ddr3_val_defconfig
Diff comments   View file @ e801931
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_val/imximage.cfg"
  2 +CONFIG_ARM=y
  3 +CONFIG_ARCH_MX6=y
  4 +CONFIG_TARGET_MX6ULL_DDR3_VAL=y
  5 +CONFIG_ENV_SIZE=0x2000
  6 +CONFIG_ENV_OFFSET=0xE0000
  7 +CONFIG_DM_GPIO=y
  8 +CONFIG_NR_DRAM_BANKS=1
  9 +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val"
  10 +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb"
  11 +CONFIG_BOOTDELAY=3
  12 +# CONFIG_CONSOLE_MUX is not set
  13 +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
  14 +CONFIG_SUPPORT_RAW_INITRD=y
  15 +CONFIG_BOUNCE_BUFFER=y
  16 +CONFIG_BOARD_EARLY_INIT_F=y
  17 +CONFIG_HUSH_PARSER=y
  18 +CONFIG_CMD_BOOTZ=y
  19 +# CONFIG_CMD_IMLS is not set
  20 +CONFIG_CMD_MEMTEST=y
  21 +CONFIG_CMD_GPIO=y
  22 +CONFIG_CMD_I2C=y
  23 +CONFIG_CMD_MMC=y
  24 +CONFIG_CMD_SF=y
  25 +CONFIG_CMD_USB=y
  26 +CONFIG_CMD_DHCP=y
  27 +CONFIG_CMD_PING=y
  28 +CONFIG_CMD_BMP=y
  29 +CONFIG_CMD_CACHE=y
  30 +CONFIG_CMD_NET=y
  31 +CONFIG_CMD_EXT2=y
  32 +CONFIG_CMD_EXT4=y
  33 +CONFIG_CMD_EXT4_WRITE=y
  34 +CONFIG_CMD_FAT=y
  35 +CONFIG_CMD_FS_GENERIC=y
  36 +CONFIG_OF_CONTROL=y
  37 +CONFIG_ENV_IS_IN_MMC=y
  38 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  39 +CONFIG_DM_I2C=y
  40 +CONFIG_DM_MMC=y
  41 +CONFIG_FSL_USDHC=y
  42 +CONFIG_MTD=y
  43 +CONFIG_DM_SPI_FLASH=y
  44 +CONFIG_SPI_FLASH=y
  45 +CONFIG_SF_DEFAULT_MODE=0
  46 +CONFIG_SF_DEFAULT_SPEED=40000000
  47 +CONFIG_SPI_FLASH_STMICRO=y
  48 +CONFIG_PHYLIB=y
  49 +CONFIG_PHY_MICREL=y
  50 +CONFIG_DM_ETH=y
  51 +CONFIG_MII=y
  52 +CONFIG_PINCTRL=y
  53 +CONFIG_PINCTRL_IMX6=y
  54 +CONFIG_DM_PMIC=y
  55 +CONFIG_DM_PMIC_PFUZE100=y
  56 +CONFIG_DM_REGULATOR=y
  57 +CONFIG_DM_REGULATOR_PFUZE100=y
  58 +CONFIG_DM_REGULATOR_FIXED=y
  59 +CONFIG_DM_REGULATOR_GPIO=y
  60 +CONFIG_SPI=y
  61 +CONFIG_DM_SPI=y
  62 +CONFIG_FSL_QSPI=y
  63 +CONFIG_USB=y
  64 +CONFIG_DM_USB=y
  65 +CONFIG_USB_STORAGE=y
  66 +CONFIG_USB_HOST_ETHER=y
  67 +CONFIG_USB_ETHER_ASIX=y
  68 +CONFIG_VIDEO=y
configs/mx6ull_14x14_ddr3_val_emmc_defconfig
Diff comments   View file @ e801931
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_val/imximage.cfg"
  2 +CONFIG_ARM=y
  3 +CONFIG_ARCH_MX6=y
  4 +CONFIG_TARGET_MX6ULL_DDR3_VAL=y
  5 +CONFIG_ENV_SIZE=0x2000
  6 +CONFIG_ENV_OFFSET=0xE0000
  7 +CONFIG_DM_GPIO=y
  8 +CONFIG_NR_DRAM_BANKS=1
  9 +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val-emmc"
  10 +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb"
  11 +CONFIG_MX6ULL_DDR3_VAL_EMMC_REWORK=y
  12 +CONFIG_BOOTDELAY=3
  13 +# CONFIG_CONSOLE_MUX is not set
  14 +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
  15 +CONFIG_SUPPORT_RAW_INITRD=y
  16 +CONFIG_BOUNCE_BUFFER=y
  17 +CONFIG_BOARD_EARLY_INIT_F=y
  18 +CONFIG_HUSH_PARSER=y
  19 +CONFIG_CMD_BOOTZ=y
  20 +# CONFIG_CMD_IMLS is not set
  21 +CONFIG_CMD_MEMTEST=y
  22 +CONFIG_CMD_GPIO=y
  23 +CONFIG_CMD_I2C=y
  24 +CONFIG_CMD_MMC=y
  25 +CONFIG_CMD_USB=y
  26 +CONFIG_CMD_DHCP=y
  27 +CONFIG_CMD_PING=y
  28 +CONFIG_CMD_BMP=y
  29 +CONFIG_CMD_CACHE=y
  30 +CONFIG_CMD_NET=y
  31 +CONFIG_CMD_EXT2=y
  32 +CONFIG_CMD_EXT4=y
  33 +CONFIG_CMD_EXT4_WRITE=y
  34 +CONFIG_CMD_FAT=y
  35 +CONFIG_CMD_FS_GENERIC=y
  36 +CONFIG_OF_CONTROL=y
  37 +CONFIG_ENV_IS_IN_MMC=y
  38 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  39 +CONFIG_DM_I2C=y
  40 +CONFIG_DM_MMC=y
  41 +CONFIG_FSL_USDHC=y
  42 +CONFIG_MTD=y
  43 +CONFIG_PHYLIB=y
  44 +CONFIG_PHY_MICREL=y
  45 +CONFIG_DM_ETH=y
  46 +CONFIG_MII=y
  47 +CONFIG_PINCTRL=y
  48 +CONFIG_PINCTRL_IMX6=y
  49 +CONFIG_DM_PMIC=y
  50 +CONFIG_DM_PMIC_PFUZE100=y
  51 +CONFIG_DM_REGULATOR=y
  52 +CONFIG_DM_REGULATOR_PFUZE100=y
  53 +CONFIG_DM_REGULATOR_FIXED=y
  54 +CONFIG_DM_REGULATOR_GPIO=y
  55 +CONFIG_USB=y
  56 +CONFIG_DM_USB=y
  57 +CONFIG_USB_STORAGE=y
  58 +CONFIG_USB_HOST_ETHER=y
  59 +CONFIG_USB_ETHER_ASIX=y
  60 +CONFIG_VIDEO=y
configs/mx6ull_14x14_ddr3_val_epdc_defconfig
Diff comments   View file @ e801931
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_val/imximage.cfg"
  2 +CONFIG_ARM=y
  3 +CONFIG_ARCH_MX6=y
  4 +CONFIG_TARGET_MX6ULL_DDR3_VAL=y
  5 +CONFIG_ENV_SIZE=0x2000
  6 +CONFIG_ENV_OFFSET=0xE0000
  7 +CONFIG_DM_GPIO=y
  8 +CONFIG_VIDEO=y
  9 +CONFIG_LCD=y
  10 +CONFIG_MXC_EPDC=y
  11 +CONFIG_NR_DRAM_BANKS=1
  12 +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val-epdc"
  13 +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb"
  14 +CONFIG_BOOTDELAY=3
  15 +# CONFIG_CONSOLE_MUX is not set
  16 +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
  17 +CONFIG_SUPPORT_RAW_INITRD=y
  18 +CONFIG_BOUNCE_BUFFER=y
  19 +CONFIG_BOARD_EARLY_INIT_F=y
  20 +CONFIG_HUSH_PARSER=y
  21 +CONFIG_CMD_BOOTZ=y
  22 +# CONFIG_CMD_IMLS is not set
  23 +CONFIG_CMD_MEMTEST=y
  24 +CONFIG_CMD_GPIO=y
  25 +CONFIG_CMD_I2C=y
  26 +CONFIG_CMD_MMC=y
  27 +CONFIG_CMD_SF=y
  28 +CONFIG_CMD_USB=y
  29 +CONFIG_CMD_DHCP=y
  30 +CONFIG_CMD_PING=y
  31 +CONFIG_CMD_BMP=y
  32 +CONFIG_CMD_CACHE=y
  33 +CONFIG_CMD_NET=y
  34 +CONFIG_CMD_EXT2=y
  35 +CONFIG_CMD_EXT4=y
  36 +CONFIG_CMD_EXT4_WRITE=y
  37 +CONFIG_CMD_FAT=y
  38 +CONFIG_CMD_FS_GENERIC=y
  39 +CONFIG_OF_CONTROL=y
  40 +CONFIG_ENV_IS_IN_MMC=y
  41 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  42 +CONFIG_DM_I2C=y
  43 +CONFIG_DM_MMC=y
  44 +CONFIG_FSL_USDHC=y
  45 +CONFIG_MTD=y
  46 +CONFIG_DM_SPI_FLASH=y
  47 +CONFIG_SPI_FLASH=y
  48 +CONFIG_SF_DEFAULT_MODE=0
  49 +CONFIG_SF_DEFAULT_SPEED=40000000
  50 +CONFIG_SPI_FLASH_STMICRO=y
  51 +CONFIG_PHYLIB=y
  52 +CONFIG_PHY_MICREL=y
  53 +CONFIG_DM_ETH=y
  54 +CONFIG_MII=y
  55 +CONFIG_PINCTRL=y
  56 +CONFIG_PINCTRL_IMX6=y
  57 +CONFIG_DM_PMIC=y
  58 +CONFIG_DM_PMIC_PFUZE100=y
  59 +CONFIG_DM_REGULATOR=y
  60 +CONFIG_DM_REGULATOR_PFUZE100=y
  61 +CONFIG_DM_REGULATOR_FIXED=y
  62 +CONFIG_DM_REGULATOR_GPIO=y
  63 +CONFIG_SPI=y
  64 +CONFIG_DM_SPI=y
  65 +CONFIG_FSL_QSPI=y
  66 +CONFIG_USB=y
  67 +CONFIG_DM_USB=y
  68 +CONFIG_USB_STORAGE=y
  69 +CONFIG_USB_HOST_ETHER=y
  70 +CONFIG_USB_ETHER_ASIX=y
configs/mx6ull_14x14_ddr3_val_nand_defconfig
Diff comments   View file @ e801931
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_val/imximage.cfg"
  2 +CONFIG_ARM=y
  3 +CONFIG_ARCH_MX6=y
  4 +CONFIG_TARGET_MX6ULL_DDR3_VAL=y
  5 +CONFIG_ENV_SIZE=0x20000
  6 +CONFIG_ENV_OFFSET=0x3c00000
  7 +CONFIG_DM_GPIO=y
  8 +CONFIG_NR_DRAM_BANKS=1
  9 +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val-gpmi-weim"
  10 +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb"
  11 +CONFIG_NAND_BOOT=y
  12 +CONFIG_CMD_NAND=y
  13 +CONFIG_CMD_NAND_TRIMFFS=y
  14 +CONFIG_CMD_UBI=y
  15 +CONFIG_MTD=y
  16 +CONFIG_DM_MTD=y
  17 +CONFIG_MTD_RAW_NAND=y
  18 +CONFIG_NAND=y
  19 +CONFIG_NAND_MXS=y
  20 +CONFIG_NAND_MXS_DT=y
  21 +CONFIG_ENV_IS_IN_NAND=y
  22 +CONFIG_BOOTDELAY=3
  23 +# CONFIG_CONSOLE_MUX is not set
  24 +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
  25 +CONFIG_SUPPORT_RAW_INITRD=y
  26 +CONFIG_BOUNCE_BUFFER=y
  27 +CONFIG_BOARD_EARLY_INIT_F=y
  28 +CONFIG_HUSH_PARSER=y
  29 +CONFIG_CMD_BOOTZ=y
  30 +# CONFIG_CMD_IMLS is not set
  31 +CONFIG_CMD_MEMTEST=y
  32 +CONFIG_CMD_GPIO=y
  33 +CONFIG_CMD_I2C=y
  34 +CONFIG_CMD_MMC=y
  35 +CONFIG_CMD_USB=y
  36 +CONFIG_CMD_DHCP=y
  37 +CONFIG_CMD_PING=y
  38 +CONFIG_CMD_BMP=y
  39 +CONFIG_CMD_CACHE=y
  40 +CONFIG_CMD_NET=y
  41 +CONFIG_CMD_EXT2=y
  42 +CONFIG_CMD_EXT4=y
  43 +CONFIG_CMD_EXT4_WRITE=y
  44 +CONFIG_CMD_FAT=y
  45 +CONFIG_CMD_FS_GENERIC=y
  46 +CONFIG_OF_CONTROL=y
  47 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  48 +CONFIG_DM_I2C=y
  49 +CONFIG_DM_MMC=y
  50 +CONFIG_FSL_USDHC=y
  51 +CONFIG_PHYLIB=y
  52 +CONFIG_PHY_MICREL=y
  53 +CONFIG_DM_ETH=y
  54 +CONFIG_MII=y
  55 +CONFIG_PINCTRL=y
  56 +CONFIG_PINCTRL_IMX6=y
  57 +CONFIG_DM_PMIC=y
  58 +CONFIG_DM_PMIC_PFUZE100=y
  59 +CONFIG_DM_REGULATOR=y
  60 +CONFIG_DM_REGULATOR_PFUZE100=y
  61 +CONFIG_DM_REGULATOR_FIXED=y
  62 +CONFIG_DM_REGULATOR_GPIO=y
  63 +CONFIG_USB=y
  64 +CONFIG_DM_USB=y
  65 +CONFIG_USB_STORAGE=y
  66 +CONFIG_USB_HOST_ETHER=y
  67 +CONFIG_USB_ETHER_ASIX=y
  68 +CONFIG_VIDEO=y
configs/mx6ull_14x14_ddr3_val_plugin_defconfig
Diff comments   View file @ e801931
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_val/imximage.cfg"
  2 +CONFIG_ARM=y
  3 +CONFIG_ARCH_MX6=y
  4 +CONFIG_TARGET_MX6ULL_DDR3_VAL=y
  5 +CONFIG_ENV_SIZE=0x2000
  6 +CONFIG_ENV_OFFSET=0xE0000
  7 +CONFIG_DM_GPIO=y
  8 +CONFIG_NR_DRAM_BANKS=1
  9 +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val"
  10 +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb"
  11 +CONFIG_USE_IMXIMG_PLUGIN=y
  12 +CONFIG_BOOTDELAY=3
  13 +# CONFIG_CONSOLE_MUX is not set
  14 +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
  15 +CONFIG_SUPPORT_RAW_INITRD=y
  16 +CONFIG_BOUNCE_BUFFER=y
  17 +CONFIG_BOARD_EARLY_INIT_F=y
  18 +CONFIG_HUSH_PARSER=y
  19 +CONFIG_CMD_BOOTZ=y
  20 +# CONFIG_CMD_IMLS is not set
  21 +CONFIG_CMD_MEMTEST=y
  22 +CONFIG_CMD_GPIO=y
  23 +CONFIG_CMD_I2C=y
  24 +CONFIG_CMD_MMC=y
  25 +CONFIG_CMD_SF=y
  26 +CONFIG_CMD_USB=y
  27 +CONFIG_CMD_DHCP=y
  28 +CONFIG_CMD_PING=y
  29 +CONFIG_CMD_BMP=y
  30 +CONFIG_CMD_CACHE=y
  31 +CONFIG_CMD_NET=y
  32 +CONFIG_CMD_EXT2=y
  33 +CONFIG_CMD_EXT4=y
  34 +CONFIG_CMD_EXT4_WRITE=y
  35 +CONFIG_CMD_FAT=y
  36 +CONFIG_CMD_FS_GENERIC=y
  37 +CONFIG_OF_CONTROL=y
  38 +CONFIG_ENV_IS_IN_MMC=y
  39 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  40 +CONFIG_DM_I2C=y
  41 +CONFIG_DM_MMC=y
  42 +CONFIG_FSL_USDHC=y
  43 +CONFIG_MTD=y
  44 +CONFIG_DM_SPI_FLASH=y
  45 +CONFIG_SPI_FLASH=y
  46 +CONFIG_SF_DEFAULT_MODE=0
  47 +CONFIG_SF_DEFAULT_SPEED=40000000
  48 +CONFIG_SPI_FLASH_STMICRO=y
  49 +CONFIG_PHYLIB=y
  50 +CONFIG_PHY_MICREL=y
  51 +CONFIG_DM_ETH=y
  52 +CONFIG_MII=y
  53 +CONFIG_PINCTRL=y
  54 +CONFIG_PINCTRL_IMX6=y
  55 +CONFIG_DM_PMIC=y
  56 +CONFIG_DM_PMIC_PFUZE100=y
  57 +CONFIG_DM_REGULATOR=y
  58 +CONFIG_DM_REGULATOR_PFUZE100=y
  59 +CONFIG_DM_REGULATOR_FIXED=y
  60 +CONFIG_DM_REGULATOR_GPIO=y
  61 +CONFIG_SPI=y
  62 +CONFIG_DM_SPI=y
  63 +CONFIG_FSL_QSPI=y
  64 +CONFIG_USB=y
  65 +CONFIG_DM_USB=y
  66 +CONFIG_USB_STORAGE=y
  67 +CONFIG_USB_HOST_ETHER=y
  68 +CONFIG_USB_ETHER_ASIX=y
  69 +CONFIG_VIDEO=y
configs/mx6ull_14x14_ddr3_val_qspi1_defconfig
Diff comments   View file @ e801931
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_val/imximage.cfg"
  2 +CONFIG_ARM=y
  3 +CONFIG_ARCH_MX6=y
  4 +CONFIG_TARGET_MX6ULL_DDR3_VAL=y
  5 +CONFIG_ENV_SIZE=0x2000
  6 +CONFIG_ENV_OFFSET=0xE0000
  7 +CONFIG_ENV_SECT_SIZE=0x10000
  8 +CONFIG_DM_GPIO=y
  9 +CONFIG_NR_DRAM_BANKS=1
  10 +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val"
  11 +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb"
  12 +CONFIG_QSPI_BOOT=y
  13 +CONFIG_ENV_IS_IN_SPI_FLASH=y
  14 +CONFIG_BOOTDELAY=3
  15 +# CONFIG_CONSOLE_MUX is not set
  16 +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
  17 +CONFIG_SUPPORT_RAW_INITRD=y
  18 +CONFIG_BOUNCE_BUFFER=y
  19 +CONFIG_BOARD_EARLY_INIT_F=y
  20 +CONFIG_HUSH_PARSER=y
  21 +CONFIG_CMD_BOOTZ=y
  22 +# CONFIG_CMD_IMLS is not set
  23 +CONFIG_CMD_MEMTEST=y
  24 +CONFIG_CMD_GPIO=y
  25 +CONFIG_CMD_I2C=y
  26 +CONFIG_CMD_MMC=y
  27 +CONFIG_CMD_SF=y
  28 +CONFIG_CMD_USB=y
  29 +CONFIG_CMD_DHCP=y
  30 +CONFIG_CMD_PING=y
  31 +CONFIG_CMD_BMP=y
  32 +CONFIG_CMD_CACHE=y
  33 +CONFIG_CMD_NET=y
  34 +CONFIG_CMD_EXT2=y
  35 +CONFIG_CMD_EXT4=y
  36 +CONFIG_CMD_EXT4_WRITE=y
  37 +CONFIG_CMD_FAT=y
  38 +CONFIG_CMD_FS_GENERIC=y
  39 +CONFIG_OF_CONTROL=y
  40 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  41 +CONFIG_DM_I2C=y
  42 +CONFIG_DM_MMC=y
  43 +CONFIG_FSL_USDHC=y
  44 +CONFIG_MTD=y
  45 +CONFIG_DM_SPI_FLASH=y
  46 +CONFIG_SPI_FLASH=y
  47 +CONFIG_SF_DEFAULT_MODE=0
  48 +CONFIG_SF_DEFAULT_SPEED=40000000
  49 +CONFIG_SPI_FLASH_STMICRO=y
  50 +CONFIG_PHYLIB=y
  51 +CONFIG_PHY_MICREL=y
  52 +CONFIG_DM_ETH=y
  53 +CONFIG_MII=y
  54 +CONFIG_PINCTRL=y
  55 +CONFIG_PINCTRL_IMX6=y
  56 +CONFIG_DM_PMIC=y
  57 +CONFIG_DM_PMIC_PFUZE100=y
  58 +CONFIG_DM_REGULATOR=y
  59 +CONFIG_DM_REGULATOR_PFUZE100=y
  60 +CONFIG_DM_REGULATOR_FIXED=y
  61 +CONFIG_DM_REGULATOR_GPIO=y
  62 +CONFIG_SPI=y
  63 +CONFIG_DM_SPI=y
  64 +CONFIG_FSL_QSPI=y
  65 +CONFIG_USB=y
  66 +CONFIG_DM_USB=y
  67 +CONFIG_USB_STORAGE=y
  68 +CONFIG_USB_HOST_ETHER=y
  69 +CONFIG_USB_ETHER_ASIX=y
  70 +CONFIG_VIDEO=y
configs/mx6ull_14x14_ddr3_val_spinor_defconfig
Diff comments   View file @ e801931
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_val/imximage.cfg"
  2 +CONFIG_ARM=y
  3 +CONFIG_ARCH_MX6=y
  4 +CONFIG_TARGET_MX6ULL_DDR3_VAL=y
  5 +CONFIG_ENV_SIZE=0x2000
  6 +CONFIG_ENV_OFFSET=0xE0000
  7 +CONFIG_ENV_SECT_SIZE=0x10000
  8 +CONFIG_DM_GPIO=y
  9 +CONFIG_NR_DRAM_BANKS=1
  10 +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val"
  11 +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb"
  12 +CONFIG_SPI_BOOT=y
  13 +CONFIG_MXC_SPI=y
  14 +CONFIG_ENV_IS_IN_SPI_FLASH=y
  15 +CONFIG_BOOTDELAY=3
  16 +# CONFIG_CONSOLE_MUX is not set
  17 +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
  18 +CONFIG_SUPPORT_RAW_INITRD=y
  19 +CONFIG_BOUNCE_BUFFER=y
  20 +CONFIG_BOARD_EARLY_INIT_F=y
  21 +CONFIG_HUSH_PARSER=y
  22 +CONFIG_CMD_BOOTZ=y
  23 +# CONFIG_CMD_IMLS is not set
  24 +CONFIG_CMD_MEMTEST=y
  25 +CONFIG_CMD_GPIO=y
  26 +CONFIG_CMD_I2C=y
  27 +CONFIG_CMD_MMC=y
  28 +CONFIG_CMD_SF=y
  29 +CONFIG_CMD_USB=y
  30 +CONFIG_CMD_DHCP=y
  31 +CONFIG_CMD_PING=y
  32 +CONFIG_CMD_BMP=y
  33 +CONFIG_CMD_CACHE=y
  34 +CONFIG_CMD_NET=y
  35 +CONFIG_CMD_EXT2=y
  36 +CONFIG_CMD_EXT4=y
  37 +CONFIG_CMD_EXT4_WRITE=y
  38 +CONFIG_CMD_FAT=y
  39 +CONFIG_CMD_FS_GENERIC=y
  40 +CONFIG_OF_CONTROL=y
  41 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  42 +CONFIG_DM_I2C=y
  43 +CONFIG_DM_MMC=y
  44 +CONFIG_FSL_USDHC=y
  45 +CONFIG_MTD=y
  46 +CONFIG_DM_SPI_FLASH=y
  47 +CONFIG_SPI_FLASH=y
  48 +CONFIG_SF_DEFAULT_BUS=1
  49 +CONFIG_SF_DEFAULT_MODE=0
  50 +CONFIG_SF_DEFAULT_SPEED=20000000
  51 +CONFIG_SPI_FLASH_STMICRO=y
  52 +CONFIG_PHYLIB=y
  53 +CONFIG_PHY_MICREL=y
  54 +CONFIG_DM_ETH=y
  55 +CONFIG_MII=y
  56 +CONFIG_PINCTRL=y
  57 +CONFIG_PINCTRL_IMX6=y
  58 +CONFIG_DM_PMIC=y
  59 +CONFIG_DM_PMIC_PFUZE100=y
  60 +CONFIG_DM_REGULATOR=y
  61 +CONFIG_DM_REGULATOR_PFUZE100=y
  62 +CONFIG_DM_REGULATOR_FIXED=y
  63 +CONFIG_DM_REGULATOR_GPIO=y
  64 +CONFIG_SPI=y
  65 +CONFIG_DM_SPI=y
  66 +CONFIG_USB=y
  67 +CONFIG_DM_USB=y
  68 +CONFIG_USB_STORAGE=y
  69 +CONFIG_USB_HOST_ETHER=y
  70 +CONFIG_USB_ETHER_ASIX=y
  71 +CONFIG_VIDEO=y
configs/mx6ull_14x14_ddr3_val_tsc_defconfig
Diff comments   View file @ e801931
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_val/imximage.cfg"
  2 +CONFIG_ARM=y
  3 +CONFIG_ARCH_MX6=y
  4 +CONFIG_TARGET_MX6ULL_DDR3_VAL=y
  5 +CONFIG_ENV_SIZE=0x2000
  6 +CONFIG_ENV_OFFSET=0xE0000
  7 +CONFIG_DM_GPIO=y
  8 +CONFIG_NR_DRAM_BANKS=1
  9 +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val-tsc"
  10 +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb"
  11 +CONFIG_MX6ULL_DDR3_VAL_TSC_REWORK=y
  12 +CONFIG_BOOTDELAY=3
  13 +# CONFIG_CONSOLE_MUX is not set
  14 +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
  15 +CONFIG_SUPPORT_RAW_INITRD=y
  16 +CONFIG_BOUNCE_BUFFER=y
  17 +CONFIG_BOARD_EARLY_INIT_F=y
  18 +CONFIG_HUSH_PARSER=y
  19 +CONFIG_CMD_BOOTZ=y
  20 +# CONFIG_CMD_IMLS is not set
  21 +CONFIG_CMD_MEMTEST=y
  22 +CONFIG_CMD_GPIO=y
  23 +CONFIG_CMD_I2C=y
  24 +CONFIG_CMD_MMC=y
  25 +CONFIG_CMD_SF=y
  26 +CONFIG_CMD_USB=y
  27 +CONFIG_CMD_DHCP=y
  28 +CONFIG_CMD_PING=y
  29 +CONFIG_CMD_BMP=y
  30 +CONFIG_CMD_CACHE=y
  31 +CONFIG_CMD_NET=y
  32 +CONFIG_CMD_EXT2=y
  33 +CONFIG_CMD_EXT4=y
  34 +CONFIG_CMD_EXT4_WRITE=y
  35 +CONFIG_CMD_FAT=y
  36 +CONFIG_CMD_FS_GENERIC=y
  37 +CONFIG_OF_CONTROL=y
  38 +CONFIG_ENV_IS_IN_MMC=y
  39 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  40 +CONFIG_DM_I2C=y
  41 +CONFIG_DM_MMC=y
  42 +CONFIG_FSL_USDHC=y
  43 +CONFIG_MTD=y
  44 +CONFIG_DM_SPI_FLASH=y
  45 +CONFIG_SPI_FLASH=y
  46 +CONFIG_SF_DEFAULT_MODE=0
  47 +CONFIG_SF_DEFAULT_SPEED=40000000
  48 +CONFIG_SPI_FLASH_STMICRO=y
  49 +CONFIG_PHYLIB=y
  50 +CONFIG_PHY_MICREL=y
  51 +CONFIG_DM_ETH=y
  52 +CONFIG_MII=y
  53 +CONFIG_PINCTRL=y
  54 +CONFIG_PINCTRL_IMX6=y
  55 +CONFIG_DM_PMIC=y
  56 +CONFIG_DM_PMIC_PFUZE100=y
  57 +CONFIG_DM_REGULATOR=y
  58 +CONFIG_DM_REGULATOR_PFUZE100=y
  59 +CONFIG_DM_REGULATOR_FIXED=y
  60 +CONFIG_DM_REGULATOR_GPIO=y
  61 +CONFIG_SPI=y
  62 +CONFIG_DM_SPI=y
  63 +CONFIG_FSL_QSPI=y
  64 +CONFIG_USB=y
  65 +CONFIG_DM_USB=y
  66 +CONFIG_USB_STORAGE=y
  67 +CONFIG_USB_HOST_ETHER=y
  68 +CONFIG_USB_ETHER_ASIX=y
  69 +CONFIG_VIDEO=y
include/configs/mx6ull_ddr3_val.h
Diff comments   View file @ e801931
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * Configuration settings for the Freescale i.MX6UL 14x14 DDR3 ARM2.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +#ifndef __MX6ULL_DDR3_VAL_CONFIG_H
  9 +#define __MX6ULL_DDR3_VAL_CONFIG_H
  10 +
  11 +
  12 +#define BOOTARGS_CMA_SIZE ""
  13 +
  14 +#include "mx6ul_val.h"
  15 +
  16 +#define CONFIG_IOMUX_LPSR
  17 +
  18 +#define PHYS_SDRAM_SIZE SZ_1G
  19 +
  20 +/*
  21 + * TSC pins conflict with I2C1 bus, so after TSC
  22 + * hardware rework, need to disable i2c1 bus, also
  23 + * need to disable PMIC and ldo bypass check.
  24 + */
  25 +#ifdef CONFIG_MX6ULL_DDR3_VAL_TSC_REWORK
  26 +#undef CONFIG_LDO_BYPASS_CHECK
  27 +#undef CONFIG_SYS_I2C_MXC
  28 +#undef CONFIG_SYS_I2C
  29 +#undef CONFIG_CMD_I2C
  30 +#undef CONFIG_POWER_PFUZE100_I2C_ADDR
  31 +#undef CONFIG_POWER_PFUZE100
  32 +#undef CONFIG_POWER_I2C
  33 +#undef CONFIG_POWER
  34 +#endif
  35 +
  36 +#ifdef CONFIG_DM_ETH
  37 +#define CONFIG_CMD_MII
  38 +#define CONFIG_FEC_MXC
  39 +#define CONFIG_FEC_ENET_DEV 1
  40 +
  41 +#if (CONFIG_FEC_ENET_DEV == 0)
  42 +#define IMX_FEC_BASE ENET_BASE_ADDR
  43 +#define CONFIG_FEC_MXC_PHYADDR 0x1
  44 +#define CONFIG_FEC_XCV_TYPE RMII
  45 +#define CONFIG_ETHPRIME "eth0"
  46 +#elif (CONFIG_FEC_ENET_DEV == 1)
  47 +#define IMX_FEC_BASE ENET2_BASE_ADDR
  48 +#define CONFIG_FEC_MXC_PHYADDR 0x2
  49 +#define CONFIG_FEC_XCV_TYPE MII100
  50 +#define CONFIG_ETHPRIME "eth1"
  51 +#endif
  52 +
  53 +#define CONFIG_FEC_MXC_MDIO_BASE ENET2_BASE_ADDR
  54 +#endif
  55 +
  56 +
  57 +/* #define CONFIG_SPLASH_SCREEN*/
  58 +/* #define CONFIG_MXC_EPDC*/
  59 +
  60 +/*
  61 + * SPLASH SCREEN Configs
  62 + */
  63 +#if defined(CONFIG_MXC_EPDC)
  64 +/*
  65 + * Framebuffer and LCD
  66 + */
  67 +#define CONFIG_SPLASH_SCREEN
  68 +
  69 +#undef LCD_TEST_PATTERN
  70 +/* #define CONFIG_SPLASH_IS_IN_MMC 1 */
  71 +#define LCD_BPP LCD_MONOCHROME
  72 +/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */
  73 +
  74 +#define CONFIG_WAVEFORM_BUF_SIZE 0x400000
  75 +#endif
  76 +
  77 +#define CONFIG_MODULE_FUSE
  78 +#define CONFIG_OF_SYSTEM_SETUP
  79 +
  80 +#endif