ARM: dts: dra72: add rev C evm support

Add DTS support for dra72 evm Rev C which has the following changes * Two ethernet ports now instead of the single one in rev B. * DP83867 ethernet phy instead of DP838865. Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>

ARM: dts: dra72: add rev C evm support
Add DTS support for dra72 evm Rev C which has the following changes * Two ethernet ports now instead of the single one in rev B. * DP83867 ethernet phy instead of DP838865. Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Mugunthan V N · Tom Rini
1 parent 692fcdd800
Showing 6 changed files with 601 additions and 667 deletions Side-by-side Diff
arch/arm/dts/Makefile
arch/arm/dts/dra72-evm-common.dtsi
arch/arm/dts/dra72-evm-revc.dts
arch/arm/dts/dra72-evm.dts
board/ti/dra7xx/evm.c
configs/dra7xx_evm_defconfig
@@ -133,7 +133,8 @@
 	socfpga_cyclone5_sr1500.dtb			\
 	socfpga_cyclone5_vining_fpga.dtb
  
-dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
+dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb	\
+	dra72-evm-revc.dtb
 dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
 	am572x-idk.dtb
 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "dra72x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
+
+	chosen {
+		stdout-path = &uart1;
+		tick-timer = &timer2;
+	};
+
+	aliases {
+		display0 = &hdmi0;
+	};
+
+	evm_3v3: fixedregulator-evm_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "evm_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	extcon_usb1: extcon_usb1 {
+		compatible = "linux,extcon-usb-gpio";
+		id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
+	};
+
+	extcon_usb2: extcon_usb2 {
+		compatible = "linux,extcon-usb-gpio";
+		id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
+	};
+
+	hdmi0: connector {
+		compatible = "hdmi-connector";
+		label = "hdmi";
+
+		type = "a";
+
+		port {
+			hdmi_connector_in: endpoint {
+				remote-endpoint = <&tpd12s015_out>;
+			};
+		};
+	};
+
+	tpd12s015: encoder {
+		compatible = "ti,tpd12s015";
+
+		gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>,	/* P4, CT CP HPD */
+			<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>,	/* P5, LS OE */
+			<&gpio7 12 GPIO_ACTIVE_HIGH>;	/* gpio7_12/sp1_cs2, HPD */
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				tpd12s015_in: endpoint {
+					remote-endpoint = <&hdmi_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				tpd12s015_out: endpoint {
+					remote-endpoint = <&hdmi_connector_in>;
+				};
+			};
+		};
+	};
+};
+
+&dra7_pmx_core {
+	mmc1_pins_default: mmc1_pins_default {
+		pinctrl-single,pins = <
+			0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+			0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+			0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+			0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+			0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+			0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+		>;
+	};
+
+	mmc2_pins_default: mmc2_pins_default {
+		pinctrl-single,pins = <
+			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+		>;
+	};
+
+	dcan1_pins_default: dcan1_pins_default {
+		pinctrl-single,pins = <
+			0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
+			0x418   (PULL_UP | MUX_MODE1)	/* wakeup0.dcan1_rx */
+		>;
+	};
+
+	dcan1_pins_sleep: dcan1_pins_sleep {
+		pinctrl-single,pins = <
+			0x3d0   (MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
+			0x418   (MUX_MODE15 | PULL_UP)	/* wakeup0.off */
+		>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	tps65917: tps65917@58 {
+		compatible = "ti,tps65917";
+		reg = <0x58>;
+
+		interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		ti,system-power-controller;
+
+		tps65917_pmic {
+			compatible = "ti,tps65917-pmic";
+
+			tps65917_regulators: regulators {
+				smps1_reg: smps1 {
+					/* VDD_MPU */
+					regulator-name = "smps1";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1250000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				smps2_reg: smps2 {
+					/* VDD_CORE */
+					regulator-name = "smps2";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1060000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				smps3_reg: smps3 {
+					/* VDD_GPU IVA DSPEVE */
+					regulator-name = "smps3";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1250000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				smps4_reg: smps4 {
+					/* VDDS1V8 */
+					regulator-name = "smps4";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				smps5_reg: smps5 {
+					/* VDD_DDR */
+					regulator-name = "smps5";
+					regulator-min-microvolt = <1350000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				ldo1_reg: ldo1 {
+					/* LDO1_OUT --> SDIO  */
+					regulator-name = "ldo1";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-allow-bypass;
+				};
+
+				ldo3_reg: ldo3 {
+					/* VDDA_1V8_PHY */
+					regulator-name = "ldo3";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				ldo5_reg: ldo5 {
+					/* VDDA_1V8_PLL */
+					regulator-name = "ldo5";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldo4_reg: ldo4 {
+					/* VDDA_3V_USB: VDDA_USBHS33 */
+					regulator-name = "ldo4";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-boot-on;
+				};
+			};
+		};
+
+		tps65917_power_button {
+			compatible = "ti,palmas-pwrbutton";
+			interrupt-parent = <&tps65917>;
+			interrupts = <1 IRQ_TYPE_NONE>;
+			wakeup-source;
+			ti,palmas-long-press-seconds = <6>;
+		};
+	};
+
+	pcf_gpio_21: gpio@21 {
+		compatible = "ti,pcf8575";
+		u-boot,i2c-offset-len = <0>;
+		reg = <0x21>;
+		lines-initial-states = <0x1408>;
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&i2c5 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	pcf_hdmi: pcf8575@26 {
+		compatible = "nxp,pcf8575";
+		u-boot,i2c-offset-len = <0>;
+		reg = <0x26>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		/*
+		 * initial state is used here to keep the mdio interface
+		 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
+		 * VIN2_S0 driven high otherwise Ethernet stops working
+		 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
+		 */
+		lines-initial-states = <0x0f2b>;
+
+		p1 {
+			/* vin6_sel_s0: high: VIN6, low: audio */
+			gpio-hog;
+			gpios = <1 GPIO_ACTIVE_HIGH>;
+			output-low;
+			line-name = "vin6_sel_s0";
+		};
+	};
+};
+
+&uart1 {
+	status = "okay";
+	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+			      <&dra7_pmx_core 0x3e0>;
+};
+
+&elm {
+	status = "okay";
+};
+
+&gpmc {
+	/*
+	 * For the existing IOdelay configuration via U-Boot we don't
+	 * support NAND on dra72-evm. Keep it disabled. Enabling it
+	 * requires a different configuration by U-Boot.
+	 */
+	status = "disabled";
+	ranges = <0 0 0x08000000 0x01000000>;	/* minimum GPMC partition = 16MB */
+	nand@0,0 {
+		/* To use NAND, DIP switch SW5 must be set like so:
+		 * SW5.1 (NAND_SELn) = ON (LOW)
+		 * SW5.9 (GPMC_WPN) = OFF (HIGH)
+		 */
+		compatible = "ti,omap2-nand";
+		reg = <0 0 4>;          /* device IO registers */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>; /* termcount */
+		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */	/* device IO registers */
+		ti,nand-ecc-opt = "bch8";
+		ti,elm-id = <&elm>;
+		nand-bus-width = <16>;
+		gpmc,device-width = <2>;
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <80>;
+		gpmc,cs-wr-off-ns = <80>;
+		gpmc,adv-on-ns = <0>;
+		gpmc,adv-rd-off-ns = <60>;
+		gpmc,adv-wr-off-ns = <60>;
+		gpmc,we-on-ns = <10>;
+		gpmc,we-off-ns = <50>;
+		gpmc,oe-on-ns = <4>;
+		gpmc,oe-off-ns = <40>;
+		gpmc,access-ns = <40>;
+		gpmc,wr-access-ns = <80>;
+		gpmc,rd-cycle-ns = <80>;
+		gpmc,wr-cycle-ns = <80>;
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wait-monitoring-ns = <0>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+		/* MTD partition table */
+		/* All SPL-* partitions are sized to minimal length
+		 * which can be independently programmable. For
+		 * NAND flash this is equal to size of erase-block */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition@0 {
+			label = "NAND.SPL";
+			reg = <0x00000000 0x000020000>;
+		};
+		partition@1 {
+			label = "NAND.SPL.backup1";
+			reg = <0x00020000 0x00020000>;
+		};
+		partition@2 {
+			label = "NAND.SPL.backup2";
+			reg = <0x00040000 0x00020000>;
+		};
+		partition@3 {
+			label = "NAND.SPL.backup3";
+			reg = <0x00060000 0x00020000>;
+		};
+		partition@4 {
+			label = "NAND.u-boot-spl-os";
+			reg = <0x00080000 0x00040000>;
+		};
+		partition@5 {
+			label = "NAND.u-boot";
+			reg = <0x000c0000 0x00100000>;
+		};
+		partition@6 {
+			label = "NAND.u-boot-env";
+			reg = <0x001c0000 0x00020000>;
+		};
+		partition@7 {
+			label = "NAND.u-boot-env.backup1";
+			reg = <0x001e0000 0x00020000>;
+		};
+		partition@8 {
+			label = "NAND.kernel";
+			reg = <0x00200000 0x00800000>;
+		};
+		partition@9 {
+			label = "NAND.file-system";
+			reg = <0x00a00000 0x0f600000>;
+		};
+	};
+};
+
+&usb2_phy1 {
+	phy-supply = <&ldo4_reg>;
+};
+
+&usb2_phy2 {
+	phy-supply = <&ldo4_reg>;
+};
+
+&omap_dwc3_1 {
+	extcon = <&extcon_usb1>;
+};
+
+&omap_dwc3_2 {
+	extcon = <&extcon_usb2>;
+};
+
+&usb1 {
+	dr_mode = "otg";
+};
+
+&usb2 {
+	dr_mode = "host";
+};
+
+&mmc1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins_default>;
+	vmmc_aux-supply = <&ldo1_reg>;
+	bus-width = <4>;
+	/*
+	 * SDCD signal is not being used here - using the fact that GPIO mode
+	 * is a viable alternative
+	 */
+	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
+	max-frequency = <192000000>;
+};
+
+&mmc2 {
+	/* SW5-3 in ON position */
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins_default>;
+
+	vmmc-supply = <&evm_3v3>;
+	bus-width = <8>;
+	ti,non-removable;
+	max-frequency = <192000000>;
+};
+
+&mac {
+	status = "okay";
+};
+
+&dcan1 {
+	status = "ok";
+};
+
+&qspi {
+	status = "okay";
+
+	spi-max-frequency = <76800000>;
+	m25p80@0 {
+		compatible = "s25fl256s1", "spi-flash";
+		spi-max-frequency = <64000000>;
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* MTD partition table.
+		 * The ROM checks the first four physical blocks
+		 * for a valid file to boot and the flash here is
+		 * 64KiB block size.
+		 */
+		partition@0 {
+			label = "QSPI.SPL";
+			reg = <0x00000000 0x000010000>;
+		};
+		partition@1 {
+			label = "QSPI.SPL.backup1";
+			reg = <0x00010000 0x00010000>;
+		};
+		partition@2 {
+			label = "QSPI.SPL.backup2";
+			reg = <0x00020000 0x00010000>;
+		};
+		partition@3 {
+			label = "QSPI.SPL.backup3";
+			reg = <0x00030000 0x00010000>;
+		};
+		partition@4 {
+			label = "QSPI.u-boot";
+			reg = <0x00040000 0x00100000>;
+		};
+		partition@5 {
+			label = "QSPI.u-boot-spl-os";
+			reg = <0x00140000 0x00080000>;
+		};
+		partition@6 {
+			label = "QSPI.u-boot-env";
+			reg = <0x001c0000 0x00010000>;
+		};
+		partition@7 {
+			label = "QSPI.u-boot-env.backup1";
+			reg = <0x001d0000 0x0010000>;
+		};
+		partition@8 {
+			label = "QSPI.kernel";
+			reg = <0x001e0000 0x0800000>;
+		};
+		partition@9 {
+			label = "QSPI.file-system";
+			reg = <0x009e0000 0x01620000>;
+		};
+	};
+};
+
+&dss {
+	status = "ok";
+
+	vdda_video-supply = <&ldo5_reg>;
+};
+
+&hdmi {
+	status = "ok";
+
+	port {
+		hdmi_out: endpoint {
+			remote-endpoint = <&tpd12s015_in>;
+		};
+	};
+};
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "dra72-evm-common.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+	model = "TI DRA722 Rev C EVM";
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
+	};
+};
+
+&tps65917_regulators {
+	ldo2_reg: ldo2 {
+		/* LDO2_OUT --> VDDA_1V8_PHY2 */
+		regulator-name = "ldo2";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&hdmi {
+	vdda_video-supply = <&ldo2_reg>;
+};
+
+&mac {
+	mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
+		     <&pcf_hdmi 9 GPIO_ACTIVE_LOW>,	/* P11 */
+		     <&pcf_hdmi 10 GPIO_ACTIVE_LOW>;	/* P12 */
+	dual_emac;
+};
+
+&cpsw_emac0 {
+	phy-handle = <&dp83867_0>;
+	phy-mode = "rgmii-id";
+	dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+	phy-handle = <&dp83867_1>;
+	phy-mode = "rgmii-id";
+	dual_emac_res_vlan = <2>;
+};
+
+&davinci_mdio {
+	dp83867_0: ethernet-phy@2 {
+		reg = <2>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+		ti,min-output-imepdance;
+	};
+
+	dp83867_1: ethernet-phy@3 {
+		reg = <3>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+		ti,min-output-imepdance;
+	};
+};
@@ -5,674 +5,24 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-/dts-v1/;
+#include <dra72-evm-common.dtsi>
  
-#include "dra72x.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
 / {
 	model = "TI DRA722";
 	compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
  
-	chosen {
-		stdout-path = &uart1;
-		tick-timer = &timer2;
-	};
-
 	memory {
 		device_type = "memory";
 		reg = <0x80000000 0x40000000>; /* 1024 MB */
 	};
-
-	aliases {
-		display0 = &hdmi0;
-	};
-
-	evm_3v3: fixedregulator-evm_3v3 {
-		compatible = "regulator-fixed";
-		regulator-name = "evm_3v3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-	};
-
-	evm_3v3_sd: fixedregulator-sd {
-		compatible = "regulator-fixed";
-		regulator-name = "evm_3v3_sd";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		enable-active-high;
-		gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
-	};
-
-	extcon_usb1: extcon_usb1 {
-		compatible = "linux,extcon-usb-gpio";
-		id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
-	};
-
-	extcon_usb2: extcon_usb2 {
-		compatible = "linux,extcon-usb-gpio";
-		id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
-	};
-
-	hdmi0: connector {
-		compatible = "hdmi-connector";
-		label = "hdmi";
-
-		type = "a";
-
-		port {
-			hdmi_connector_in: endpoint {
-				remote-endpoint = <&tpd12s015_out>;
-			};
-		};
-	};
-
-	tpd12s015: encoder {
-		compatible = "ti,tpd12s015";
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&tpd12s015_pins>;
-
-		gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>,	/* P4, CT CP HPD */
-			<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>,	/* P5, LS OE */
-			<&gpio7 12 GPIO_ACTIVE_HIGH>;	/* gpio7_12/sp1_cs2, HPD */
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-
-				tpd12s015_in: endpoint {
-					remote-endpoint = <&hdmi_out>;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-
-				tpd12s015_out: endpoint {
-					remote-endpoint = <&hdmi_connector_in>;
-				};
-			};
-		};
-	};
 };
  
-&dra7_pmx_core {
-	i2c1_pins: pinmux_i2c1_pins {
-		pinctrl-single,pins = <
-			0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
-			0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
-		>;
-	};
  
-	i2c5_pins: pinmux_i2c5_pins {
-		pinctrl-single,pins = <
-			0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
-			0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
-		>;
-	};
-
-	nand_default: nand_default {
-		pinctrl-single,pins = <
-			0x0	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad0 */
-			0x4	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad1 */
-			0x8	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad2 */
-			0xc	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad3 */
-			0x10	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad4 */
-			0x14	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad5 */
-			0x18	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad6 */
-			0x1c	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad7 */
-			0x20	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad8 */
-			0x24	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad9 */
-			0x28	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad10 */
-			0x2c	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad11 */
-			0x30	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad12 */
-			0x34	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad13 */
-			0x38	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad14 */
-			0x3c	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad15 */
-			0xb4	(PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
-			0xc4	(PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
-			0xcc	(PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
-			0xc8	(PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
-			0xd0	(PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
-			0xd8	(PIN_INPUT  | MUX_MODE0) /* gpmc_wait0 */
-		>;
-	};
-
-	usb1_pins: pinmux_usb1_pins {
-		pinctrl-single,pins = <
-			0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
-		>;
-	};
-
-	usb2_pins: pinmux_usb2_pins {
-		pinctrl-single,pins = <
-			0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
-		>;
-	};
-
-	tps65917_pins_default: tps65917_pins_default {
-		pinctrl-single,pins = <
-			0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
-		>;
-	};
-
-	mmc1_pins_default: mmc1_pins_default {
-		pinctrl-single,pins = <
-			0x36c (PIN_INPUT | MUX_MODE14)	/* mmc1sdcd.gpio219 */
-			0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
-			0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
-			0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
-			0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
-			0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
-			0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
-		>;
-	};
-
-	mmc2_pins_default: mmc2_pins_default {
-		pinctrl-single,pins = <
-			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
-			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
-			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
-			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
-			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
-			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
-			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
-			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
-			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
-			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
-		>;
-	};
-
-	dcan1_pins_default: dcan1_pins_default {
-		pinctrl-single,pins = <
-			0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
-			0x418   (PULL_UP | MUX_MODE1)	/* wakeup0.dcan1_rx */
-		>;
-	};
-
-	dcan1_pins_sleep: dcan1_pins_sleep {
-		pinctrl-single,pins = <
-			0x3d0   (MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
-			0x418   (MUX_MODE15 | PULL_UP)	/* wakeup0.off */
-		>;
-	};
-
-	qspi1_pins: pinmux_qspi1_pins {
-		pinctrl-single,pins = <
-			0x74 (PIN_OUTPUT | MUX_MODE1)	/* gpmc_a13.qspi1_rtclk */
-			0x78 (PIN_INPUT | MUX_MODE1)	/* gpmc_a14.qspi1_d3 */
-			0x7c (PIN_INPUT | MUX_MODE1)	/* gpmc_a15.qspi1_d2 */
-			0x80 (PIN_INPUT | MUX_MODE1)	/* gpmc_a16.qspi1_d1 */
-			0x84 (PIN_INPUT | MUX_MODE1)	/* gpmc_a17.qspi1_d0 */
-			0x88 (PIN_OUTPUT | MUX_MODE1)	/* qpmc_a18.qspi1_sclk */
-			0xb8 (PIN_OUTPUT | MUX_MODE1)	/* gpmc_cs2.qspi1_cs0 */
-		>;
-	};
-
-	hdmi_pins: pinmux_hdmi_pins {
-		pinctrl-single,pins = <
-			0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
-			0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
-		>;
-	};
-
-	tpd12s015_pins: pinmux_tpd12s015_pins {
-		pinctrl-single,pins = <
-			0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
-		>;
-	};
-};
-
-&i2c1 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins>;
-	clock-frequency = <400000>;
-
-	tps65917: tps65917@58 {
-		compatible = "ti,tps65917";
-		reg = <0x58>;
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&tps65917_pins_default>;
-
-		interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
-		interrupt-controller;
-		#interrupt-cells = <2>;
-
-		ti,system-power-controller;
-
-		tps65917_pmic {
-			compatible = "ti,tps65917-pmic";
-
-			regulators {
-				smps1_reg: smps1 {
-					/* VDD_MPU */
-					regulator-name = "smps1";
-					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <1250000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				smps2_reg: smps2 {
-					/* VDD_CORE */
-					regulator-name = "smps2";
-					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <1060000>;
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				smps3_reg: smps3 {
-					/* VDD_GPU IVA DSPEVE */
-					regulator-name = "smps3";
-					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <1250000>;
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				smps4_reg: smps4 {
-					/* VDDS1V8 */
-					regulator-name = "smps4";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				smps5_reg: smps5 {
-					/* VDD_DDR */
-					regulator-name = "smps5";
-					regulator-min-microvolt = <1350000>;
-					regulator-max-microvolt = <1350000>;
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				ldo1_reg: ldo1 {
-					/* LDO1_OUT --> SDIO  */
-					regulator-name = "ldo1";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <3300000>;
-					regulator-boot-on;
-				};
-
-				ldo2_reg: ldo2 {
-					/* LDO2_OUT --> TP1017 (UNUSED)  */
-					regulator-name = "ldo2";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <3300000>;
-				};
-
-				ldo3_reg: ldo3 {
-					/* VDDA_1V8_PHY */
-					regulator-name = "ldo3";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				ldo5_reg: ldo5 {
-					/* VDDA_1V8_PLL */
-					regulator-name = "ldo5";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				ldo4_reg: ldo4 {
-					/* VDDA_3V_USB: VDDA_USBHS33 */
-					regulator-name = "ldo4";
-					regulator-min-microvolt = <3300000>;
-					regulator-max-microvolt = <3300000>;
-					regulator-boot-on;
-				};
-			};
-		};
-
-		tps65917_power_button {
-			compatible = "ti,palmas-pwrbutton";
-			interrupt-parent = <&tps65917>;
-			interrupts = <1 IRQ_TYPE_NONE>;
-			wakeup-source;
-			ti,palmas-long-press-seconds = <6>;
-		};
-	};
-
-	pcf_gpio_21: gpio@21 {
-		compatible = "ti,pcf8575";
-		reg = <0x21>;
-		lines-initial-states = <0x1408>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-parent = <&gpio6>;
-		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		u-boot,i2c-offset-len = <0>;
-	};
-};
-
-&i2c5 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c5_pins>;
-	clock-frequency = <400000>;
-
-	pcf_hdmi: pcf8575@26 {
-		compatible = "nxp,pcf8575";
-		reg = <0x26>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		/*
-		 * initial state is used here to keep the mdio interface
-		 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
-		 * VIN2_S0 driven high otherwise Ethernet stops working
-		 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
-		 */
-		lines-initial-states = <0x0f2b>;
-		u-boot,i2c-offset-len = <0>;
-	};
-};
-
-&uart1 {
-	status = "okay";
-};
-
-&elm {
-	status = "okay";
-};
-
-&gpmc {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&nand_default>;
-	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */
-	nand@0,0 {
-		/* To use NAND, DIP switch SW5 must be set like so:
-		 * SW5.1 (NAND_SELn) = ON (LOW)
-		 * SW5.9 (GPMC_WPN) = OFF (HIGH)
-		 */
-		reg = <0 0 4>;		/* device IO registers */
-		ti,nand-ecc-opt = "bch8";
-		ti,elm-id = <&elm>;
-		nand-bus-width = <16>;
-		gpmc,device-width = <2>;
-		gpmc,sync-clk-ps = <0>;
-		gpmc,cs-on-ns = <0>;
-		gpmc,cs-rd-off-ns = <80>;
-		gpmc,cs-wr-off-ns = <80>;
-		gpmc,adv-on-ns = <0>;
-		gpmc,adv-rd-off-ns = <60>;
-		gpmc,adv-wr-off-ns = <60>;
-		gpmc,we-on-ns = <10>;
-		gpmc,we-off-ns = <50>;
-		gpmc,oe-on-ns = <4>;
-		gpmc,oe-off-ns = <40>;
-		gpmc,access-ns = <40>;
-		gpmc,wr-access-ns = <80>;
-		gpmc,rd-cycle-ns = <80>;
-		gpmc,wr-cycle-ns = <80>;
-		gpmc,bus-turnaround-ns = <0>;
-		gpmc,cycle2cycle-delay-ns = <0>;
-		gpmc,clk-activation-ns = <0>;
-		gpmc,wait-monitoring-ns = <0>;
-		gpmc,wr-data-mux-bus-ns = <0>;
-		/* MTD partition table */
-		/* All SPL-* partitions are sized to minimal length
-		 * which can be independently programmable. For
-		 * NAND flash this is equal to size of erase-block */
-		#address-cells = <1>;
-		#size-cells = <1>;
-		partition@0 {
-			label = "NAND.SPL";
-			reg = <0x00000000 0x000020000>;
-		};
-		partition@1 {
-			label = "NAND.SPL.backup1";
-			reg = <0x00020000 0x00020000>;
-		};
-		partition@2 {
-			label = "NAND.SPL.backup2";
-			reg = <0x00040000 0x00020000>;
-		};
-		partition@3 {
-			label = "NAND.SPL.backup3";
-			reg = <0x00060000 0x00020000>;
-		};
-		partition@4 {
-			label = "NAND.u-boot-spl-os";
-			reg = <0x00080000 0x00040000>;
-		};
-		partition@5 {
-			label = "NAND.u-boot";
-			reg = <0x000c0000 0x00100000>;
-		};
-		partition@6 {
-			label = "NAND.u-boot-env";
-			reg = <0x001c0000 0x00020000>;
-		};
-		partition@7 {
-			label = "NAND.u-boot-env.backup1";
-			reg = <0x001e0000 0x00020000>;
-		};
-		partition@8 {
-			label = "NAND.kernel";
-			reg = <0x00200000 0x00800000>;
-		};
-		partition@9 {
-			label = "NAND.file-system";
-			reg = <0x00a00000 0x0f600000>;
-		};
-	};
-};
-
-&usb2_phy1 {
-	phy-supply = <&ldo4_reg>;
-};
-
-&usb2_phy2 {
-	phy-supply = <&ldo4_reg>;
-};
-
-&omap_dwc3_1 {
-	extcon = <&extcon_usb1>;
-};
-
-&omap_dwc3_2 {
-	extcon = <&extcon_usb2>;
-};
-
-&usb1 {
-	dr_mode = "peripheral";
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb1_pins>;
-};
-
-&usb2 {
-	dr_mode = "host";
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb2_pins>;
-};
-
-&mmc1 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc1_pins_default>;
-
-	vmmc_aux-supply = <&ldo1_reg>;
-	vmmc-supply = <&evm_3v3_sd>;
-	bus-width = <4>;
-	/*
-	 * SDCD signal is not being used here - using the fact that GPIO mode
-	 * is a viable alternative
-	 */
-	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
-};
-
-&mmc2 {
-	/* SW5-3 in ON position */
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc2_pins_default>;
-
-	vmmc-supply = <&evm_3v3>;
-	bus-width = <8>;
-	ti,non-removable;
-};
-
-&dra7_pmx_core {
-	cpsw_default: cpsw_default {
-		pinctrl-single,pins = <
-			/* Slave 2 */
-			0x198 (PIN_OUTPUT | MUX_MODE3)	/* vin2a_d12.rgmii1_txc */
-			0x19c (PIN_OUTPUT | MUX_MODE3)	/* vin2a_d13.rgmii1_tctl */
-			0x1a0 (PIN_OUTPUT | MUX_MODE3)	/* vin2a_d14.rgmii1_td3 */
-			0x1a4 (PIN_OUTPUT | MUX_MODE3)	/* vin2a_d15.rgmii1_td2 */
-			0x1a8 (PIN_OUTPUT | MUX_MODE3)	/* vin2a_d16.rgmii1_td1 */
-			0x1ac (PIN_OUTPUT | MUX_MODE3)	/* vin2a_d17.rgmii1_td0 */
-			0x1b0 (PIN_INPUT | MUX_MODE3)	/* vin2a_d18.rgmii1_rclk */
-			0x1b4 (PIN_INPUT | MUX_MODE3)	/* vin2a_d19.rgmii1_rctl */
-			0x1b8 (PIN_INPUT | MUX_MODE3)	/* vin2a_d20.rgmii1_rd3 */
-			0x1bc (PIN_INPUT | MUX_MODE3)	/* vin2a_d21.rgmii1_rd2 */
-			0x1c0 (PIN_INPUT | MUX_MODE3)	/* vin2a_d22.rgmii1_rd1 */
-			0x1c4 (PIN_INPUT | MUX_MODE3)	/* vin2a_d23.rgmii1_rd0 */
-		>;
-
-	};
-
-	cpsw_sleep: cpsw_sleep {
-		pinctrl-single,pins = <
-			/* Slave 2 */
-			0x198 (MUX_MODE15)
-			0x19c (MUX_MODE15)
-			0x1a0 (MUX_MODE15)
-			0x1a4 (MUX_MODE15)
-			0x1a8 (MUX_MODE15)
-			0x1ac (MUX_MODE15)
-			0x1b0 (MUX_MODE15)
-			0x1b4 (MUX_MODE15)
-			0x1b8 (MUX_MODE15)
-			0x1bc (MUX_MODE15)
-			0x1c0 (MUX_MODE15)
-			0x1c4 (MUX_MODE15)
-		>;
-	};
-
-	davinci_mdio_default: davinci_mdio_default {
-		pinctrl-single,pins = <
-			/* MDIO */
-			0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* mdio_d.mdio_d */
-			0x240 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mdio_clk.mdio_clk */
-		>;
-	};
-
-	davinci_mdio_sleep: davinci_mdio_sleep {
-		pinctrl-single,pins = <
-			0x23c (MUX_MODE15)
-			0x240 (MUX_MODE15)
-		>;
-	};
-};
-
-&mac {
-	status = "okay";
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&cpsw_default>;
-	pinctrl-1 = <&cpsw_sleep>;
-	mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
-};
-
 &cpsw_emac0 {
 	phy_id = <&davinci_mdio>, <3>;
 	phy-mode = "rgmii";
 };
  
-&davinci_mdio {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&davinci_mdio_default>;
-	pinctrl-1 = <&davinci_mdio_sleep>;
-};
-
-&dcan1 {
-	status = "ok";
-	pinctrl-names = "default", "sleep", "active";
-	pinctrl-0 = <&dcan1_pins_sleep>;
-	pinctrl-1 = <&dcan1_pins_sleep>;
-	pinctrl-2 = <&dcan1_pins_default>;
-};
-
-&qspi {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&qspi1_pins>;
-
-	spi-max-frequency = <76800000>;
-	m25p80@0 {
-		compatible = "s25fl256s1","spi-flash";
-		spi-max-frequency = <64000000>;
-		reg = <0>;
-		spi-tx-bus-width = <1>;
-		spi-rx-bus-width = <4>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		/* MTD partition table.
-		 * The ROM checks the first four physical blocks
-		 * for a valid file to boot and the flash here is
-		 * 64KiB block size.
-		 */
-		partition@0 {
-			label = "QSPI.SPL";
-			reg = <0x00000000 0x000010000>;
-		};
-		partition@1 {
-			label = "QSPI.SPL.backup1";
-			reg = <0x00010000 0x00010000>;
-		};
-		partition@2 {
-			label = "QSPI.SPL.backup2";
-			reg = <0x00020000 0x00010000>;
-		};
-		partition@3 {
-			label = "QSPI.SPL.backup3";
-			reg = <0x00030000 0x00010000>;
-		};
-		partition@4 {
-			label = "QSPI.u-boot";
-			reg = <0x00040000 0x00100000>;
-		};
-		partition@5 {
-			label = "QSPI.u-boot-spl-os";
-			reg = <0x00140000 0x00080000>;
-		};
-		partition@6 {
-			label = "QSPI.u-boot-env";
-			reg = <0x001c0000 0x00010000>;
-		};
-		partition@7 {
-			label = "QSPI.u-boot-env.backup1";
-			reg = <0x001d0000 0x0010000>;
-		};
-		partition@8 {
-			label = "QSPI.kernel";
-			reg = <0x001e0000 0x0800000>;
-		};
-		partition@9 {
-			label = "QSPI.file-system";
-			reg = <0x009e0000 0x01620000>;
-		};
-	};
-};
-
 &dss {
 	status = "ok";
  
  
  
@@ -680,16 +30,10 @@
 };
  
 &hdmi {
-	status = "ok";
 	vdda-supply = <&ldo3_reg>;
+};
  
-	pinctrl-names = "default";
-	pinctrl-0 = <&hdmi_pins>;
-
-	port {
-		hdmi_out: endpoint {
-			remote-endpoint = <&tpd12s015_in>;
-		};
-	};
+&mac {
+	 mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
 };
@@ -828,12 +828,18 @@
 #ifdef CONFIG_SPL_LOAD_FIT
 int board_fit_config_name_match(const char *name)
 {
-	if (is_dra72x() && !strcmp(name, "dra72-evm"))
+	if (is_dra72x()) {
+		if (board_is_dra72x_revc_or_later()) {
+			if (!strcmp(name, "dra72-evm-revc"))
+				return 0;
+		} else if (!strcmp(name, "dra72-evm")) {
+			return 0;
+		}
+	} else if (!is_dra72x() && !strcmp(name, "dra7-evm")) {
 		return 0;
-	else if (!is_dra72x() && !strcmp(name, "dra7-evm"))
-		return 0;
-	else
-		return -1;
+	}
+
+	return -1;
 }
 #endif
  
@@ -45,7 +45,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="dra7-evm dra72-evm"
+CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc"
 CONFIG_DM=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
...	...	@@ -133,7 +133,8 @@
133	133	socfpga_cyclone5_sr1500.dtb \
134	134	socfpga_cyclone5_vining_fpga.dtb
135	135
136		-dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
	136	+dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
	137	+ dra72-evm-revc.dtb
137	138	dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
138	139	am572x-idk.dtb
139	140	dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
	1	+/*
	2	+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or modify
	5	+ * it under the terms of the GNU General Public License version 2 as
	6	+ * published by the Free Software Foundation.
	7	+ */
	8	+/dts-v1/;
	9	+
	10	+#include "dra72x.dtsi"
	11	+#include <dt-bindings/gpio/gpio.h>
	12	+
	13	+/ {
	14	+ compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
	15	+
	16	+ chosen {
	17	+ stdout-path = &uart1;
	18	+ tick-timer = &timer2;
	19	+ };
	20	+
	21	+ aliases {
	22	+ display0 = &hdmi0;
	23	+ };
	24	+
	25	+ evm_3v3: fixedregulator-evm_3v3 {
	26	+ compatible = "regulator-fixed";
	27	+ regulator-name = "evm_3v3";
	28	+ regulator-min-microvolt = <3300000>;
	29	+ regulator-max-microvolt = <3300000>;
	30	+ };
	31	+
	32	+ extcon_usb1: extcon_usb1 {
	33	+ compatible = "linux,extcon-usb-gpio";
	34	+ id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
	35	+ };
	36	+
	37	+ extcon_usb2: extcon_usb2 {
	38	+ compatible = "linux,extcon-usb-gpio";
	39	+ id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
	40	+ };
	41	+
	42	+ hdmi0: connector {
	43	+ compatible = "hdmi-connector";
	44	+ label = "hdmi";
	45	+
	46	+ type = "a";
	47	+
	48	+ port {
	49	+ hdmi_connector_in: endpoint {
	50	+ remote-endpoint = <&tpd12s015_out>;
	51	+ };
	52	+ };
	53	+ };
	54	+
	55	+ tpd12s015: encoder {
	56	+ compatible = "ti,tpd12s015";
	57	+
	58	+ gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
	59	+ <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
	60	+ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
	61	+
	62	+ ports {
	63	+ #address-cells = <1>;
	64	+ #size-cells = <0>;
	65	+
	66	+ port@0 {
	67	+ reg = <0>;
	68	+
	69	+ tpd12s015_in: endpoint {
	70	+ remote-endpoint = <&hdmi_out>;
	71	+ };
	72	+ };
	73	+
	74	+ port@1 {
	75	+ reg = <1>;
	76	+
	77	+ tpd12s015_out: endpoint {
	78	+ remote-endpoint = <&hdmi_connector_in>;
	79	+ };
	80	+ };
	81	+ };
	82	+ };
	83	+};
	84	+
	85	+&dra7_pmx_core {
	86	+ mmc1_pins_default: mmc1_pins_default {
	87	+ pinctrl-single,pins = <
	88	+ 0x354 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_clk.clk */
	89	+ 0x358 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_cmd.cmd */
	90	+ 0x35c (PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat0.dat0 */
	91	+ 0x360 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat1.dat1 */
	92	+ 0x364 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat2.dat2 */
	93	+ 0x368 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat3.dat3 */
	94	+ >;
	95	+ };
	96	+
	97	+ mmc2_pins_default: mmc2_pins_default {
	98	+ pinctrl-single,pins = <
	99	+ 0x9c (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a23.mmc2_clk */
	100	+ 0xb0 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
	101	+ 0xa0 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
	102	+ 0xa4 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
	103	+ 0xa8 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
	104	+ 0xac (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
	105	+ 0x8c (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
	106	+ 0x90 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
	107	+ 0x94 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
	108	+ 0x98 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
	109	+ >;
	110	+ };
	111	+
	112	+ dcan1_pins_default: dcan1_pins_default {
	113	+ pinctrl-single,pins = <
	114	+ 0x3d0 (PIN_OUTPUT_PULLUP \| MUX_MODE0) /* dcan1_tx */
	115	+ 0x418 (PULL_UP \| MUX_MODE1) /* wakeup0.dcan1_rx */
	116	+ >;
	117	+ };
	118	+
	119	+ dcan1_pins_sleep: dcan1_pins_sleep {
	120	+ pinctrl-single,pins = <
	121	+ 0x3d0 (MUX_MODE15 \| PULL_UP) /* dcan1_tx.off */
	122	+ 0x418 (MUX_MODE15 \| PULL_UP) /* wakeup0.off */
	123	+ >;
	124	+ };
	125	+};
	126	+
	127	+&i2c1 {
	128	+ status = "okay";
	129	+ clock-frequency = <400000>;
	130	+
	131	+ tps65917: tps65917@58 {
	132	+ compatible = "ti,tps65917";
	133	+ reg = <0x58>;
	134	+
	135	+ interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
	136	+ interrupt-controller;
	137	+ #interrupt-cells = <2>;
	138	+
	139	+ ti,system-power-controller;
	140	+
	141	+ tps65917_pmic {
	142	+ compatible = "ti,tps65917-pmic";
	143	+
	144	+ tps65917_regulators: regulators {
	145	+ smps1_reg: smps1 {
	146	+ /* VDD_MPU */
	147	+ regulator-name = "smps1";
	148	+ regulator-min-microvolt = <850000>;
	149	+ regulator-max-microvolt = <1250000>;
	150	+ regulator-always-on;
	151	+ regulator-boot-on;
	152	+ };
	153	+
	154	+ smps2_reg: smps2 {
	155	+ /* VDD_CORE */
	156	+ regulator-name = "smps2";
	157	+ regulator-min-microvolt = <850000>;
	158	+ regulator-max-microvolt = <1060000>;
	159	+ regulator-boot-on;
	160	+ regulator-always-on;
	161	+ };
	162	+
	163	+ smps3_reg: smps3 {
	164	+ /* VDD_GPU IVA DSPEVE */
	165	+ regulator-name = "smps3";
	166	+ regulator-min-microvolt = <850000>;
	167	+ regulator-max-microvolt = <1250000>;
	168	+ regulator-boot-on;
	169	+ regulator-always-on;
	170	+ };
	171	+
	172	+ smps4_reg: smps4 {
	173	+ /* VDDS1V8 */
	174	+ regulator-name = "smps4";
	175	+ regulator-min-microvolt = <1800000>;
	176	+ regulator-max-microvolt = <1800000>;
	177	+ regulator-always-on;
	178	+ regulator-boot-on;
	179	+ };
	180	+
	181	+ smps5_reg: smps5 {
	182	+ /* VDD_DDR */
	183	+ regulator-name = "smps5";
	184	+ regulator-min-microvolt = <1350000>;
	185	+ regulator-max-microvolt = <1350000>;
	186	+ regulator-boot-on;
	187	+ regulator-always-on;
	188	+ };
	189	+
	190	+ ldo1_reg: ldo1 {
	191	+ /* LDO1_OUT --> SDIO */
	192	+ regulator-name = "ldo1";
	193	+ regulator-min-microvolt = <1800000>;
	194	+ regulator-max-microvolt = <3300000>;
	195	+ regulator-always-on;
	196	+ regulator-boot-on;
	197	+ regulator-allow-bypass;
	198	+ };
	199	+
	200	+ ldo3_reg: ldo3 {
	201	+ /* VDDA_1V8_PHY */
	202	+ regulator-name = "ldo3";
	203	+ regulator-min-microvolt = <1800000>;
	204	+ regulator-max-microvolt = <1800000>;
	205	+ regulator-boot-on;
	206	+ regulator-always-on;
	207	+ };
	208	+
	209	+ ldo5_reg: ldo5 {
	210	+ /* VDDA_1V8_PLL */
	211	+ regulator-name = "ldo5";
	212	+ regulator-min-microvolt = <1800000>;
	213	+ regulator-max-microvolt = <1800000>;
	214	+ regulator-always-on;
	215	+ regulator-boot-on;
	216	+ };
	217	+
	218	+ ldo4_reg: ldo4 {
	219	+ /* VDDA_3V_USB: VDDA_USBHS33 */
	220	+ regulator-name = "ldo4";
	221	+ regulator-min-microvolt = <3300000>;
	222	+ regulator-max-microvolt = <3300000>;
	223	+ regulator-boot-on;
	224	+ };
	225	+ };
	226	+ };
	227	+
	228	+ tps65917_power_button {
	229	+ compatible = "ti,palmas-pwrbutton";
	230	+ interrupt-parent = <&tps65917>;
	231	+ interrupts = <1 IRQ_TYPE_NONE>;
	232	+ wakeup-source;
	233	+ ti,palmas-long-press-seconds = <6>;
	234	+ };
	235	+ };
	236	+
	237	+ pcf_gpio_21: gpio@21 {
	238	+ compatible = "ti,pcf8575";
	239	+ u-boot,i2c-offset-len = <0>;
	240	+ reg = <0x21>;
	241	+ lines-initial-states = <0x1408>;
	242	+ gpio-controller;
	243	+ #gpio-cells = <2>;
	244	+
	245	+ interrupt-controller;
	246	+ #interrupt-cells = <2>;
	247	+ };
	248	+};
	249	+
	250	+&i2c5 {
	251	+ status = "okay";
	252	+ clock-frequency = <400000>;
	253	+
	254	+ pcf_hdmi: pcf8575@26 {
	255	+ compatible = "nxp,pcf8575";
	256	+ u-boot,i2c-offset-len = <0>;
	257	+ reg = <0x26>;
	258	+ gpio-controller;
	259	+ #gpio-cells = <2>;
	260	+ /*
	261	+ * initial state is used here to keep the mdio interface
	262	+ * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
	263	+ * VIN2_S0 driven high otherwise Ethernet stops working
	264	+ * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
	265	+ */
	266	+ lines-initial-states = <0x0f2b>;
	267	+
	268	+ p1 {
	269	+ /* vin6_sel_s0: high: VIN6, low: audio */
	270	+ gpio-hog;
	271	+ gpios = <1 GPIO_ACTIVE_HIGH>;
	272	+ output-low;
	273	+ line-name = "vin6_sel_s0";
	274	+ };
	275	+ };
	276	+};
	277	+
	278	+&uart1 {
	279	+ status = "okay";
	280	+ interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	281	+ <&dra7_pmx_core 0x3e0>;
	282	+};
	283	+
	284	+&elm {
	285	+ status = "okay";
	286	+};
	287	+
	288	+&gpmc {
	289	+ /*
	290	+ * For the existing IOdelay configuration via U-Boot we don't
	291	+ * support NAND on dra72-evm. Keep it disabled. Enabling it
	292	+ * requires a different configuration by U-Boot.
	293	+ */
	294	+ status = "disabled";
	295	+ ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
	296	+ nand@0,0 {
	297	+ /* To use NAND, DIP switch SW5 must be set like so:
	298	+ * SW5.1 (NAND_SELn) = ON (LOW)
	299	+ * SW5.9 (GPMC_WPN) = OFF (HIGH)
	300	+ */
	301	+ compatible = "ti,omap2-nand";
	302	+ reg = <0 0 4>; /* device IO registers */
	303	+ interrupt-parent = <&gpmc>;
	304	+ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
	305	+ <1 IRQ_TYPE_NONE>; /* termcount */
	306	+ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin / / device IO registers */
	307	+ ti,nand-ecc-opt = "bch8";
	308	+ ti,elm-id = <&elm>;
	309	+ nand-bus-width = <16>;
	310	+ gpmc,device-width = <2>;
	311	+ gpmc,sync-clk-ps = <0>;
	312	+ gpmc,cs-on-ns = <0>;
	313	+ gpmc,cs-rd-off-ns = <80>;
	314	+ gpmc,cs-wr-off-ns = <80>;
	315	+ gpmc,adv-on-ns = <0>;
	316	+ gpmc,adv-rd-off-ns = <60>;
	317	+ gpmc,adv-wr-off-ns = <60>;
	318	+ gpmc,we-on-ns = <10>;
	319	+ gpmc,we-off-ns = <50>;
	320	+ gpmc,oe-on-ns = <4>;
	321	+ gpmc,oe-off-ns = <40>;
	322	+ gpmc,access-ns = <40>;
	323	+ gpmc,wr-access-ns = <80>;
	324	+ gpmc,rd-cycle-ns = <80>;
	325	+ gpmc,wr-cycle-ns = <80>;
	326	+ gpmc,bus-turnaround-ns = <0>;
	327	+ gpmc,cycle2cycle-delay-ns = <0>;
	328	+ gpmc,clk-activation-ns = <0>;
	329	+ gpmc,wait-monitoring-ns = <0>;
	330	+ gpmc,wr-data-mux-bus-ns = <0>;
	331	+ /* MTD partition table */
	332	+ /* All SPL-* partitions are sized to minimal length
	333	+ * which can be independently programmable. For
	334	+ * NAND flash this is equal to size of erase-block */
	335	+ #address-cells = <1>;
	336	+ #size-cells = <1>;
	337	+ partition@0 {
	338	+ label = "NAND.SPL";
	339	+ reg = <0x00000000 0x000020000>;
	340	+ };
	341	+ partition@1 {
	342	+ label = "NAND.SPL.backup1";
	343	+ reg = <0x00020000 0x00020000>;
	344	+ };
	345	+ partition@2 {
	346	+ label = "NAND.SPL.backup2";
	347	+ reg = <0x00040000 0x00020000>;
	348	+ };
	349	+ partition@3 {
	350	+ label = "NAND.SPL.backup3";
	351	+ reg = <0x00060000 0x00020000>;
	352	+ };
	353	+ partition@4 {
	354	+ label = "NAND.u-boot-spl-os";
	355	+ reg = <0x00080000 0x00040000>;
	356	+ };
	357	+ partition@5 {
	358	+ label = "NAND.u-boot";
	359	+ reg = <0x000c0000 0x00100000>;
	360	+ };
	361	+ partition@6 {
	362	+ label = "NAND.u-boot-env";
	363	+ reg = <0x001c0000 0x00020000>;
	364	+ };
	365	+ partition@7 {
	366	+ label = "NAND.u-boot-env.backup1";
	367	+ reg = <0x001e0000 0x00020000>;
	368	+ };
	369	+ partition@8 {
	370	+ label = "NAND.kernel";
	371	+ reg = <0x00200000 0x00800000>;
	372	+ };
	373	+ partition@9 {
	374	+ label = "NAND.file-system";
	375	+ reg = <0x00a00000 0x0f600000>;
	376	+ };
	377	+ };
	378	+};
	379	+
	380	+&usb2_phy1 {
	381	+ phy-supply = <&ldo4_reg>;
	382	+};
	383	+
	384	+&usb2_phy2 {
	385	+ phy-supply = <&ldo4_reg>;
	386	+};
	387	+
	388	+&omap_dwc3_1 {
	389	+ extcon = <&extcon_usb1>;
	390	+};
	391	+
	392	+&omap_dwc3_2 {
	393	+ extcon = <&extcon_usb2>;
	394	+};
	395	+
	396	+&usb1 {
	397	+ dr_mode = "otg";
	398	+};
	399	+
	400	+&usb2 {
	401	+ dr_mode = "host";
	402	+};
	403	+
	404	+&mmc1 {
	405	+ status = "okay";
	406	+ pinctrl-names = "default";
	407	+ pinctrl-0 = <&mmc1_pins_default>;
	408	+ vmmc_aux-supply = <&ldo1_reg>;
	409	+ bus-width = <4>;
	410	+ /*
	411	+ * SDCD signal is not being used here - using the fact that GPIO mode
	412	+ * is a viable alternative
	413	+ */
	414	+ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
	415	+ max-frequency = <192000000>;
	416	+};
	417	+
	418	+&mmc2 {
	419	+ /* SW5-3 in ON position */
	420	+ status = "okay";
	421	+ pinctrl-names = "default";
	422	+ pinctrl-0 = <&mmc2_pins_default>;
	423	+
	424	+ vmmc-supply = <&evm_3v3>;
	425	+ bus-width = <8>;
	426	+ ti,non-removable;
	427	+ max-frequency = <192000000>;
	428	+};
	429	+
	430	+&mac {
	431	+ status = "okay";
	432	+};
	433	+
	434	+&dcan1 {
	435	+ status = "ok";
	436	+};
	437	+
	438	+&qspi {
	439	+ status = "okay";
	440	+
	441	+ spi-max-frequency = <76800000>;
	442	+ m25p80@0 {
	443	+ compatible = "s25fl256s1", "spi-flash";
	444	+ spi-max-frequency = <64000000>;
	445	+ reg = <0>;
	446	+ spi-tx-bus-width = <1>;
	447	+ spi-rx-bus-width = <4>;
	448	+ #address-cells = <1>;
	449	+ #size-cells = <1>;
	450	+
	451	+ /* MTD partition table.
	452	+ * The ROM checks the first four physical blocks
	453	+ * for a valid file to boot and the flash here is
	454	+ * 64KiB block size.
	455	+ */
	456	+ partition@0 {
	457	+ label = "QSPI.SPL";
	458	+ reg = <0x00000000 0x000010000>;
	459	+ };
	460	+ partition@1 {
	461	+ label = "QSPI.SPL.backup1";
	462	+ reg = <0x00010000 0x00010000>;
	463	+ };
	464	+ partition@2 {
	465	+ label = "QSPI.SPL.backup2";
	466	+ reg = <0x00020000 0x00010000>;
	467	+ };
	468	+ partition@3 {
	469	+ label = "QSPI.SPL.backup3";
	470	+ reg = <0x00030000 0x00010000>;
	471	+ };
	472	+ partition@4 {
	473	+ label = "QSPI.u-boot";
	474	+ reg = <0x00040000 0x00100000>;
	475	+ };
	476	+ partition@5 {
	477	+ label = "QSPI.u-boot-spl-os";
	478	+ reg = <0x00140000 0x00080000>;
	479	+ };
	480	+ partition@6 {
	481	+ label = "QSPI.u-boot-env";
	482	+ reg = <0x001c0000 0x00010000>;
	483	+ };
	484	+ partition@7 {
	485	+ label = "QSPI.u-boot-env.backup1";
	486	+ reg = <0x001d0000 0x0010000>;
	487	+ };
	488	+ partition@8 {
	489	+ label = "QSPI.kernel";
	490	+ reg = <0x001e0000 0x0800000>;
	491	+ };
	492	+ partition@9 {
	493	+ label = "QSPI.file-system";
	494	+ reg = <0x009e0000 0x01620000>;
	495	+ };
	496	+ };
	497	+};
	498	+
	499	+&dss {
	500	+ status = "ok";
	501	+
	502	+ vdda_video-supply = <&ldo5_reg>;
	503	+};
	504	+
	505	+&hdmi {
	506	+ status = "ok";
	507	+
	508	+ port {
	509	+ hdmi_out: endpoint {
	510	+ remote-endpoint = <&tpd12s015_in>;
	511	+ };
	512	+ };
	513	+};
...	...	@@ -5,674 +5,24 @@
5	5	* it under the terms of the GNU General Public License version 2 as
6	6	* published by the Free Software Foundation.
7	7	*/
8		-/dts-v1/;
	8	+#include <dra72-evm-common.dtsi>
9	9
10		-#include "dra72x.dtsi"
11		-#include <dt-bindings/gpio/gpio.h>
12		-
13	10	/ {
14	11	model = "TI DRA722";
15	12	compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
16	13
17		- chosen {
18		- stdout-path = &uart1;
19		- tick-timer = &timer2;
20		- };
21		-
22	14	memory {
23	15	device_type = "memory";
24	16	reg = <0x80000000 0x40000000>; /* 1024 MB */
25	17	};
26		-
27		- aliases {
28		- display0 = &hdmi0;
29		- };
30		-
31		- evm_3v3: fixedregulator-evm_3v3 {
32		- compatible = "regulator-fixed";
33		- regulator-name = "evm_3v3";
34		- regulator-min-microvolt = <3300000>;
35		- regulator-max-microvolt = <3300000>;
36		- };
37		-
38		- evm_3v3_sd: fixedregulator-sd {
39		- compatible = "regulator-fixed";
40		- regulator-name = "evm_3v3_sd";
41		- regulator-min-microvolt = <3300000>;
42		- regulator-max-microvolt = <3300000>;
43		- enable-active-high;
44		- gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
45		- };
46		-
47		- extcon_usb1: extcon_usb1 {
48		- compatible = "linux,extcon-usb-gpio";
49		- id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
50		- };
51		-
52		- extcon_usb2: extcon_usb2 {
53		- compatible = "linux,extcon-usb-gpio";
54		- id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
55		- };
56		-
57		- hdmi0: connector {
58		- compatible = "hdmi-connector";
59		- label = "hdmi";
60		-
61		- type = "a";
62		-
63		- port {
64		- hdmi_connector_in: endpoint {
65		- remote-endpoint = <&tpd12s015_out>;
66		- };
67		- };
68		- };
69		-
70		- tpd12s015: encoder {
71		- compatible = "ti,tpd12s015";
72		-
73		- pinctrl-names = "default";
74		- pinctrl-0 = <&tpd12s015_pins>;
75		-
76		- gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
77		- <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
78		- <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
79		-
80		- ports {
81		- #address-cells = <1>;
82		- #size-cells = <0>;
83		-
84		- port@0 {
85		- reg = <0>;
86		-
87		- tpd12s015_in: endpoint {
88		- remote-endpoint = <&hdmi_out>;
89		- };
90		- };
91		-
92		- port@1 {
93		- reg = <1>;
94		-
95		- tpd12s015_out: endpoint {
96		- remote-endpoint = <&hdmi_connector_in>;
97		- };
98		- };
99		- };
100		- };
101	18	};
102	19
103		-&dra7_pmx_core {
104		- i2c1_pins: pinmux_i2c1_pins {
105		- pinctrl-single,pins = <
106		- 0x400 (PIN_INPUT \| MUX_MODE0) /* i2c1_sda.i2c1_sda */
107		- 0x404 (PIN_INPUT \| MUX_MODE0) /* i2c1_scl.i2c1_scl */
108		- >;
109		- };
110	20
111		- i2c5_pins: pinmux_i2c5_pins {
112		- pinctrl-single,pins = <
113		- 0x2b4 (PIN_INPUT \| MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
114		- 0x2b8 (PIN_INPUT \| MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
115		- >;
116		- };
117		-
118		- nand_default: nand_default {
119		- pinctrl-single,pins = <
120		- 0x0 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad0 */
121		- 0x4 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad1 */
122		- 0x8 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad2 */
123		- 0xc (PIN_INPUT \| MUX_MODE0) /* gpmc_ad3 */
124		- 0x10 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad4 */
125		- 0x14 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad5 */
126		- 0x18 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad6 */
127		- 0x1c (PIN_INPUT \| MUX_MODE0) /* gpmc_ad7 */
128		- 0x20 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad8 */
129		- 0x24 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad9 */
130		- 0x28 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad10 */
131		- 0x2c (PIN_INPUT \| MUX_MODE0) /* gpmc_ad11 */
132		- 0x30 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad12 */
133		- 0x34 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad13 */
134		- 0x38 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad14 */
135		- 0x3c (PIN_INPUT \| MUX_MODE0) /* gpmc_ad15 */
136		- 0xb4 (PIN_OUTPUT \| MUX_MODE0) /* gpmc_cs0 */
137		- 0xc4 (PIN_OUTPUT \| MUX_MODE0) /* gpmc_advn_ale */
138		- 0xcc (PIN_OUTPUT \| MUX_MODE0) /* gpmc_wen */
139		- 0xc8 (PIN_OUTPUT \| MUX_MODE0) /* gpmc_oen_ren */
140		- 0xd0 (PIN_OUTPUT \| MUX_MODE0) /* gpmc_ben0 */
141		- 0xd8 (PIN_INPUT \| MUX_MODE0) /* gpmc_wait0 */
142		- >;
143		- };
144		-
145		- usb1_pins: pinmux_usb1_pins {
146		- pinctrl-single,pins = <
147		- 0x280 (PIN_INPUT_SLEW \| MUX_MODE0) /* usb1_drvvbus */
148		- >;
149		- };
150		-
151		- usb2_pins: pinmux_usb2_pins {
152		- pinctrl-single,pins = <
153		- 0x284 (PIN_INPUT_SLEW \| MUX_MODE0) /* usb2_drvvbus */
154		- >;
155		- };
156		-
157		- tps65917_pins_default: tps65917_pins_default {
158		- pinctrl-single,pins = <
159		- 0x424 (PIN_INPUT_PULLUP \| MUX_MODE1) /* wakeup3.sys_nirq1 */
160		- >;
161		- };
162		-
163		- mmc1_pins_default: mmc1_pins_default {
164		- pinctrl-single,pins = <
165		- 0x36c (PIN_INPUT \| MUX_MODE14) /* mmc1sdcd.gpio219 */
166		- 0x354 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_clk.clk */
167		- 0x358 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_cmd.cmd */
168		- 0x35c (PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat0.dat0 */
169		- 0x360 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat1.dat1 */
170		- 0x364 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat2.dat2 */
171		- 0x368 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat3.dat3 */
172		- >;
173		- };
174		-
175		- mmc2_pins_default: mmc2_pins_default {
176		- pinctrl-single,pins = <
177		- 0x9c (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a23.mmc2_clk */
178		- 0xb0 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
179		- 0xa0 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
180		- 0xa4 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
181		- 0xa8 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
182		- 0xac (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
183		- 0x8c (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
184		- 0x90 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
185		- 0x94 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
186		- 0x98 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
187		- >;
188		- };
189		-
190		- dcan1_pins_default: dcan1_pins_default {
191		- pinctrl-single,pins = <
192		- 0x3d0 (PIN_OUTPUT_PULLUP \| MUX_MODE0) /* dcan1_tx */
193		- 0x418 (PULL_UP \| MUX_MODE1) /* wakeup0.dcan1_rx */
194		- >;
195		- };
196		-
197		- dcan1_pins_sleep: dcan1_pins_sleep {
198		- pinctrl-single,pins = <
199		- 0x3d0 (MUX_MODE15 \| PULL_UP) /* dcan1_tx.off */
200		- 0x418 (MUX_MODE15 \| PULL_UP) /* wakeup0.off */
201		- >;
202		- };
203		-
204		- qspi1_pins: pinmux_qspi1_pins {
205		- pinctrl-single,pins = <
206		- 0x74 (PIN_OUTPUT \| MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
207		- 0x78 (PIN_INPUT \| MUX_MODE1) /* gpmc_a14.qspi1_d3 */
208		- 0x7c (PIN_INPUT \| MUX_MODE1) /* gpmc_a15.qspi1_d2 */
209		- 0x80 (PIN_INPUT \| MUX_MODE1) /* gpmc_a16.qspi1_d1 */
210		- 0x84 (PIN_INPUT \| MUX_MODE1) /* gpmc_a17.qspi1_d0 */
211		- 0x88 (PIN_OUTPUT \| MUX_MODE1) /* qpmc_a18.qspi1_sclk */
212		- 0xb8 (PIN_OUTPUT \| MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
213		- >;
214		- };
215		-
216		- hdmi_pins: pinmux_hdmi_pins {
217		- pinctrl-single,pins = <
218		- 0x408 (PIN_INPUT \| MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
219		- 0x40c (PIN_INPUT \| MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
220		- >;
221		- };
222		-
223		- tpd12s015_pins: pinmux_tpd12s015_pins {
224		- pinctrl-single,pins = <
225		- 0x3b8 (PIN_INPUT_PULLDOWN \| MUX_MODE14) /* gpio7_12 HPD */
226		- >;
227		- };
228		-};
229		-
230		-&i2c1 {
231		- status = "okay";
232		- pinctrl-names = "default";
233		- pinctrl-0 = <&i2c1_pins>;
234		- clock-frequency = <400000>;
235		-
236		- tps65917: tps65917@58 {
237		- compatible = "ti,tps65917";
238		- reg = <0x58>;
239		-
240		- pinctrl-names = "default";
241		- pinctrl-0 = <&tps65917_pins_default>;
242		-
243		- interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
244		- interrupt-controller;
245		- #interrupt-cells = <2>;
246		-
247		- ti,system-power-controller;
248		-
249		- tps65917_pmic {
250		- compatible = "ti,tps65917-pmic";
251		-
252		- regulators {
253		- smps1_reg: smps1 {
254		- /* VDD_MPU */
255		- regulator-name = "smps1";
256		- regulator-min-microvolt = <850000>;
257		- regulator-max-microvolt = <1250000>;
258		- regulator-always-on;
259		- regulator-boot-on;
260		- };
261		-
262		- smps2_reg: smps2 {
263		- /* VDD_CORE */
264		- regulator-name = "smps2";
265		- regulator-min-microvolt = <850000>;
266		- regulator-max-microvolt = <1060000>;
267		- regulator-boot-on;
268		- regulator-always-on;
269		- };
270		-
271		- smps3_reg: smps3 {
272		- /* VDD_GPU IVA DSPEVE */
273		- regulator-name = "smps3";
274		- regulator-min-microvolt = <850000>;
275		- regulator-max-microvolt = <1250000>;
276		- regulator-boot-on;
277		- regulator-always-on;
278		- };
279		-
280		- smps4_reg: smps4 {
281		- /* VDDS1V8 */
282		- regulator-name = "smps4";
283		- regulator-min-microvolt = <1800000>;
284		- regulator-max-microvolt = <1800000>;
285		- regulator-always-on;
286		- regulator-boot-on;
287		- };
288		-
289		- smps5_reg: smps5 {
290		- /* VDD_DDR */
291		- regulator-name = "smps5";
292		- regulator-min-microvolt = <1350000>;
293		- regulator-max-microvolt = <1350000>;
294		- regulator-boot-on;
295		- regulator-always-on;
296		- };
297		-
298		- ldo1_reg: ldo1 {
299		- /* LDO1_OUT --> SDIO */
300		- regulator-name = "ldo1";
301		- regulator-min-microvolt = <1800000>;
302		- regulator-max-microvolt = <3300000>;
303		- regulator-boot-on;
304		- };
305		-
306		- ldo2_reg: ldo2 {
307		- /* LDO2_OUT --> TP1017 (UNUSED) */
308		- regulator-name = "ldo2";
309		- regulator-min-microvolt = <1800000>;
310		- regulator-max-microvolt = <3300000>;
311		- };
312		-
313		- ldo3_reg: ldo3 {
314		- /* VDDA_1V8_PHY */
315		- regulator-name = "ldo3";
316		- regulator-min-microvolt = <1800000>;
317		- regulator-max-microvolt = <1800000>;
318		- regulator-boot-on;
319		- regulator-always-on;
320		- };
321		-
322		- ldo5_reg: ldo5 {
323		- /* VDDA_1V8_PLL */
324		- regulator-name = "ldo5";
325		- regulator-min-microvolt = <1800000>;
326		- regulator-max-microvolt = <1800000>;
327		- regulator-always-on;
328		- regulator-boot-on;
329		- };
330		-
331		- ldo4_reg: ldo4 {
332		- /* VDDA_3V_USB: VDDA_USBHS33 */
333		- regulator-name = "ldo4";
334		- regulator-min-microvolt = <3300000>;
335		- regulator-max-microvolt = <3300000>;
336		- regulator-boot-on;
337		- };
338		- };
339		- };
340		-
341		- tps65917_power_button {
342		- compatible = "ti,palmas-pwrbutton";
343		- interrupt-parent = <&tps65917>;
344		- interrupts = <1 IRQ_TYPE_NONE>;
345		- wakeup-source;
346		- ti,palmas-long-press-seconds = <6>;
347		- };
348		- };
349		-
350		- pcf_gpio_21: gpio@21 {
351		- compatible = "ti,pcf8575";
352		- reg = <0x21>;
353		- lines-initial-states = <0x1408>;
354		- gpio-controller;
355		- #gpio-cells = <2>;
356		- interrupt-parent = <&gpio6>;
357		- interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
358		- interrupt-controller;
359		- #interrupt-cells = <2>;
360		- u-boot,i2c-offset-len = <0>;
361		- };
362		-};
363		-
364		-&i2c5 {
365		- status = "okay";
366		- pinctrl-names = "default";
367		- pinctrl-0 = <&i2c5_pins>;
368		- clock-frequency = <400000>;
369		-
370		- pcf_hdmi: pcf8575@26 {
371		- compatible = "nxp,pcf8575";
372		- reg = <0x26>;
373		- gpio-controller;
374		- #gpio-cells = <2>;
375		- /*
376		- * initial state is used here to keep the mdio interface
377		- * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
378		- * VIN2_S0 driven high otherwise Ethernet stops working
379		- * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
380		- */
381		- lines-initial-states = <0x0f2b>;
382		- u-boot,i2c-offset-len = <0>;
383		- };
384		-};
385		-
386		-&uart1 {
387		- status = "okay";
388		-};
389		-
390		-&elm {
391		- status = "okay";
392		-};
393		-
394		-&gpmc {
395		- status = "okay";
396		- pinctrl-names = "default";
397		- pinctrl-0 = <&nand_default>;
398		- ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
399		- nand@0,0 {
400		- /* To use NAND, DIP switch SW5 must be set like so:
401		- * SW5.1 (NAND_SELn) = ON (LOW)
402		- * SW5.9 (GPMC_WPN) = OFF (HIGH)
403		- */
404		- reg = <0 0 4>; /* device IO registers */
405		- ti,nand-ecc-opt = "bch8";
406		- ti,elm-id = <&elm>;
407		- nand-bus-width = <16>;
408		- gpmc,device-width = <2>;
409		- gpmc,sync-clk-ps = <0>;
410		- gpmc,cs-on-ns = <0>;
411		- gpmc,cs-rd-off-ns = <80>;
412		- gpmc,cs-wr-off-ns = <80>;
413		- gpmc,adv-on-ns = <0>;
414		- gpmc,adv-rd-off-ns = <60>;
415		- gpmc,adv-wr-off-ns = <60>;
416		- gpmc,we-on-ns = <10>;
417		- gpmc,we-off-ns = <50>;
418		- gpmc,oe-on-ns = <4>;
419		- gpmc,oe-off-ns = <40>;
420		- gpmc,access-ns = <40>;
421		- gpmc,wr-access-ns = <80>;
422		- gpmc,rd-cycle-ns = <80>;
423		- gpmc,wr-cycle-ns = <80>;
424		- gpmc,bus-turnaround-ns = <0>;
425		- gpmc,cycle2cycle-delay-ns = <0>;
426		- gpmc,clk-activation-ns = <0>;
427		- gpmc,wait-monitoring-ns = <0>;
428		- gpmc,wr-data-mux-bus-ns = <0>;
429		- /* MTD partition table */
430		- /* All SPL-* partitions are sized to minimal length
431		- * which can be independently programmable. For
432		- * NAND flash this is equal to size of erase-block */
433		- #address-cells = <1>;
434		- #size-cells = <1>;
435		- partition@0 {
436		- label = "NAND.SPL";
437		- reg = <0x00000000 0x000020000>;
438		- };
439		- partition@1 {
440		- label = "NAND.SPL.backup1";
441		- reg = <0x00020000 0x00020000>;
442		- };
443		- partition@2 {
444		- label = "NAND.SPL.backup2";
445		- reg = <0x00040000 0x00020000>;
446		- };
447		- partition@3 {
448		- label = "NAND.SPL.backup3";
449		- reg = <0x00060000 0x00020000>;
450		- };
451		- partition@4 {
452		- label = "NAND.u-boot-spl-os";
453		- reg = <0x00080000 0x00040000>;
454		- };
455		- partition@5 {
456		- label = "NAND.u-boot";
457		- reg = <0x000c0000 0x00100000>;
458		- };
459		- partition@6 {
460		- label = "NAND.u-boot-env";
461		- reg = <0x001c0000 0x00020000>;
462		- };
463		- partition@7 {
464		- label = "NAND.u-boot-env.backup1";
465		- reg = <0x001e0000 0x00020000>;
466		- };
467		- partition@8 {
468		- label = "NAND.kernel";
469		- reg = <0x00200000 0x00800000>;
470		- };
471		- partition@9 {
472		- label = "NAND.file-system";
473		- reg = <0x00a00000 0x0f600000>;
474		- };
475		- };
476		-};
477		-
478		-&usb2_phy1 {
479		- phy-supply = <&ldo4_reg>;
480		-};
481		-
482		-&usb2_phy2 {
483		- phy-supply = <&ldo4_reg>;
484		-};
485		-
486		-&omap_dwc3_1 {
487		- extcon = <&extcon_usb1>;
488		-};
489		-
490		-&omap_dwc3_2 {
491		- extcon = <&extcon_usb2>;
492		-};
493		-
494		-&usb1 {
495		- dr_mode = "peripheral";
496		- pinctrl-names = "default";
497		- pinctrl-0 = <&usb1_pins>;
498		-};
499		-
500		-&usb2 {
501		- dr_mode = "host";
502		- pinctrl-names = "default";
503		- pinctrl-0 = <&usb2_pins>;
504		-};
505		-
506		-&mmc1 {
507		- status = "okay";
508		- pinctrl-names = "default";
509		- pinctrl-0 = <&mmc1_pins_default>;
510		-
511		- vmmc_aux-supply = <&ldo1_reg>;
512		- vmmc-supply = <&evm_3v3_sd>;
513		- bus-width = <4>;
514		- /*
515		- * SDCD signal is not being used here - using the fact that GPIO mode
516		- * is a viable alternative
517		- */
518		- cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
519		-};
520		-
521		-&mmc2 {
522		- /* SW5-3 in ON position */
523		- status = "okay";
524		- pinctrl-names = "default";
525		- pinctrl-0 = <&mmc2_pins_default>;
526		-
527		- vmmc-supply = <&evm_3v3>;
528		- bus-width = <8>;
529		- ti,non-removable;
530		-};
531		-
532		-&dra7_pmx_core {
533		- cpsw_default: cpsw_default {
534		- pinctrl-single,pins = <
535		- /* Slave 2 */
536		- 0x198 (PIN_OUTPUT \| MUX_MODE3) /* vin2a_d12.rgmii1_txc */
537		- 0x19c (PIN_OUTPUT \| MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
538		- 0x1a0 (PIN_OUTPUT \| MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
539		- 0x1a4 (PIN_OUTPUT \| MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
540		- 0x1a8 (PIN_OUTPUT \| MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
541		- 0x1ac (PIN_OUTPUT \| MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
542		- 0x1b0 (PIN_INPUT \| MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
543		- 0x1b4 (PIN_INPUT \| MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
544		- 0x1b8 (PIN_INPUT \| MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
545		- 0x1bc (PIN_INPUT \| MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
546		- 0x1c0 (PIN_INPUT \| MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
547		- 0x1c4 (PIN_INPUT \| MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
548		- >;
549		-
550		- };
551		-
552		- cpsw_sleep: cpsw_sleep {
553		- pinctrl-single,pins = <
554		- /* Slave 2 */
555		- 0x198 (MUX_MODE15)
556		- 0x19c (MUX_MODE15)
557		- 0x1a0 (MUX_MODE15)
558		- 0x1a4 (MUX_MODE15)
559		- 0x1a8 (MUX_MODE15)
560		- 0x1ac (MUX_MODE15)
561		- 0x1b0 (MUX_MODE15)
562		- 0x1b4 (MUX_MODE15)
563		- 0x1b8 (MUX_MODE15)
564		- 0x1bc (MUX_MODE15)
565		- 0x1c0 (MUX_MODE15)
566		- 0x1c4 (MUX_MODE15)
567		- >;
568		- };
569		-
570		- davinci_mdio_default: davinci_mdio_default {
571		- pinctrl-single,pins = <
572		- /* MDIO */
573		- 0x23c (PIN_OUTPUT_PULLUP \| MUX_MODE0) /* mdio_d.mdio_d */
574		- 0x240 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mdio_clk.mdio_clk */
575		- >;
576		- };
577		-
578		- davinci_mdio_sleep: davinci_mdio_sleep {
579		- pinctrl-single,pins = <
580		- 0x23c (MUX_MODE15)
581		- 0x240 (MUX_MODE15)
582		- >;
583		- };
584		-};
585		-
586		-&mac {
587		- status = "okay";
588		- pinctrl-names = "default", "sleep";
589		- pinctrl-0 = <&cpsw_default>;
590		- pinctrl-1 = <&cpsw_sleep>;
591		- mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
592		-};
593		-
594	21	&cpsw_emac0 {
595	22	phy_id = <&davinci_mdio>, <3>;
596	23	phy-mode = "rgmii";
597	24	};
598	25
599		-&davinci_mdio {
600		- pinctrl-names = "default", "sleep";
601		- pinctrl-0 = <&davinci_mdio_default>;
602		- pinctrl-1 = <&davinci_mdio_sleep>;
603		-};
604		-
605		-&dcan1 {
606		- status = "ok";
607		- pinctrl-names = "default", "sleep", "active";
608		- pinctrl-0 = <&dcan1_pins_sleep>;
609		- pinctrl-1 = <&dcan1_pins_sleep>;
610		- pinctrl-2 = <&dcan1_pins_default>;
611		-};
612		-
613		-&qspi {
614		- status = "okay";
615		- pinctrl-names = "default";
616		- pinctrl-0 = <&qspi1_pins>;
617		-
618		- spi-max-frequency = <76800000>;
619		- m25p80@0 {
620		- compatible = "s25fl256s1","spi-flash";
621		- spi-max-frequency = <64000000>;
622		- reg = <0>;
623		- spi-tx-bus-width = <1>;
624		- spi-rx-bus-width = <4>;
625		- #address-cells = <1>;
626		- #size-cells = <1>;
627		-
628		- /* MTD partition table.
629		- * The ROM checks the first four physical blocks
630		- * for a valid file to boot and the flash here is
631		- * 64KiB block size.
632		- */
633		- partition@0 {
634		- label = "QSPI.SPL";
635		- reg = <0x00000000 0x000010000>;
636		- };
637		- partition@1 {
638		- label = "QSPI.SPL.backup1";
639		- reg = <0x00010000 0x00010000>;
640		- };
641		- partition@2 {
642		- label = "QSPI.SPL.backup2";
643		- reg = <0x00020000 0x00010000>;
644		- };
645		- partition@3 {
646		- label = "QSPI.SPL.backup3";
647		- reg = <0x00030000 0x00010000>;
648		- };
649		- partition@4 {
650		- label = "QSPI.u-boot";
651		- reg = <0x00040000 0x00100000>;
652		- };
653		- partition@5 {
654		- label = "QSPI.u-boot-spl-os";
655		- reg = <0x00140000 0x00080000>;
656		- };
657		- partition@6 {
658		- label = "QSPI.u-boot-env";
659		- reg = <0x001c0000 0x00010000>;
660		- };
661		- partition@7 {
662		- label = "QSPI.u-boot-env.backup1";
663		- reg = <0x001d0000 0x0010000>;
664		- };
665		- partition@8 {
666		- label = "QSPI.kernel";
667		- reg = <0x001e0000 0x0800000>;
668		- };
669		- partition@9 {
670		- label = "QSPI.file-system";
671		- reg = <0x009e0000 0x01620000>;
672		- };
673		- };
674		-};
675		-
676	26	&dss {
677	27	status = "ok";
678	28
679	29
680	30
...	...	@@ -680,16 +30,10 @@
680	30	};
681	31
682	32	&hdmi {
683		- status = "ok";
684	33	vdda-supply = <&ldo3_reg>;
	34	+};
685	35
686		- pinctrl-names = "default";
687		- pinctrl-0 = <&hdmi_pins>;
688		-
689		- port {
690		- hdmi_out: endpoint {
691		- remote-endpoint = <&tpd12s015_in>;
692		- };
693		- };
	36	+&mac {
	37	+ mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
694	38	};
...	...	@@ -828,12 +828,18 @@
828	828	#ifdef CONFIG_SPL_LOAD_FIT
829	829	int board_fit_config_name_match(const char *name)
830	830	{
831		- if (is_dra72x() && !strcmp(name, "dra72-evm"))
	831	+ if (is_dra72x()) {
	832	+ if (board_is_dra72x_revc_or_later()) {
	833	+ if (!strcmp(name, "dra72-evm-revc"))
	834	+ return 0;
	835	+ } else if (!strcmp(name, "dra72-evm")) {
	836	+ return 0;
	837	+ }
	838	+ } else if (!is_dra72x() && !strcmp(name, "dra7-evm")) {
832	839	return 0;
833		- else if (!is_dra72x() && !strcmp(name, "dra7-evm"))
834		- return 0;
835		- else
836		- return -1;
	840	+ }
	841	+
	842	+ return -1;
837	843	}
838	844	#endif
839	845
...	...	@@ -45,7 +45,7 @@
45	45	CONFIG_CMD_FAT=y
46	46	CONFIG_CMD_FS_GENERIC=y
47	47	CONFIG_OF_CONTROL=y
48		-CONFIG_OF_LIST="dra7-evm dra72-evm"
	48	+CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc"
49	49	CONFIG_DM=y
50	50	CONFIG_DFU_MMC=y
51	51	CONFIG_DFU_RAM=y