Commit e81f63f0d2acb130df68da52e711f9178592a012
Committed by
Tom Rini
Tom Rini
1 parent
02c41535b6
Exists in
master
and in
49 other branches
ARM: OMAP4/5: Remove dead code against CONFIG_SYS_ENABLE_PADS_ALL
The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Showing 9 changed files with 0 additions and 688 deletions Side-by-side Diff
- arch/arm/cpu/armv7/omap-common/hwinit-common.c
- arch/arm/include/asm/arch-omap4/sys_proto.h
- arch/arm/include/asm/arch-omap5/sys_proto.h
- board/ti/omap5_uevm/evm.c
- board/ti/omap5_uevm/mux_data.h
- board/ti/panda/panda.c
- board/ti/panda/panda_mux_data.h
- board/ti/sdp4430/sdp.c
- board/ti/sdp4430/sdp4430_mux_data.h
arch/arm/cpu/armv7/omap-common/hwinit-common.c
| ... | ... | @@ -43,16 +43,10 @@ |
| 43 | 43 | set_muxconf_regs_essential(); |
| 44 | 44 | break; |
| 45 | 45 | case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL: |
| 46 | -#ifdef CONFIG_SYS_ENABLE_PADS_ALL | |
| 47 | - set_muxconf_regs_non_essential(); | |
| 48 | -#endif | |
| 49 | 46 | break; |
| 50 | 47 | case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: |
| 51 | 48 | case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: |
| 52 | 49 | set_muxconf_regs_essential(); |
| 53 | -#ifdef CONFIG_SYS_ENABLE_PADS_ALL | |
| 54 | - set_muxconf_regs_non_essential(); | |
| 55 | -#endif | |
| 56 | 50 | break; |
| 57 | 51 | } |
| 58 | 52 | } |
arch/arm/include/asm/arch-omap4/sys_proto.h
| ... | ... | @@ -30,7 +30,6 @@ |
| 30 | 30 | u32 get_device_type(void); |
| 31 | 31 | void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); |
| 32 | 32 | void set_muxconf_regs_essential(void); |
| 33 | -void set_muxconf_regs_non_essential(void); | |
| 34 | 33 | void sr32(void *, u32, u32, u32); |
| 35 | 34 | u32 wait_on_value(u32, u32, void *, u32); |
| 36 | 35 | void sdelay(unsigned long); |
arch/arm/include/asm/arch-omap5/sys_proto.h
| ... | ... | @@ -31,7 +31,6 @@ |
| 31 | 31 | u32 get_device_type(void); |
| 32 | 32 | void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); |
| 33 | 33 | void set_muxconf_regs_essential(void); |
| 34 | -void set_muxconf_regs_non_essential(void); | |
| 35 | 34 | void sr32(void *, u32, u32, u32); |
| 36 | 35 | u32 wait_on_value(u32, u32, void *, u32); |
| 37 | 36 | void sdelay(unsigned long); |
board/ti/omap5_uevm/evm.c
| ... | ... | @@ -157,19 +157,6 @@ |
| 157 | 157 | sizeof(struct pad_conf_entry)); |
| 158 | 158 | } |
| 159 | 159 | |
| 160 | -void set_muxconf_regs_non_essential(void) | |
| 161 | -{ | |
| 162 | - do_set_mux((*ctrl)->control_padconf_core_base, | |
| 163 | - core_padconf_array_non_essential, | |
| 164 | - sizeof(core_padconf_array_non_essential) / | |
| 165 | - sizeof(struct pad_conf_entry)); | |
| 166 | - | |
| 167 | - do_set_mux((*ctrl)->control_padconf_wkup_base, | |
| 168 | - wkup_padconf_array_non_essential, | |
| 169 | - sizeof(wkup_padconf_array_non_essential) / | |
| 170 | - sizeof(struct pad_conf_entry)); | |
| 171 | -} | |
| 172 | - | |
| 173 | 160 | #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) |
| 174 | 161 | int board_mmc_init(bd_t *bis) |
| 175 | 162 | { |
board/ti/omap5_uevm/mux_data.h
| ... | ... | @@ -55,239 +55,5 @@ |
| 55 | 55 | |
| 56 | 56 | }; |
| 57 | 57 | |
| 58 | -const struct pad_conf_entry core_padconf_array_non_essential[] = { | |
| 59 | - | |
| 60 | - {C2C_DATAIN0, (IEN | M0)}, /* C2C_DATAIN0 */ | |
| 61 | - {C2C_DATAIN1, (IEN | M0)}, /* C2C_DATAIN1 */ | |
| 62 | - {C2C_DATAIN2, (IEN | M0)}, /* C2C_DATAIN2 */ | |
| 63 | - {C2C_DATAIN3, (IEN | M0)}, /* C2C_DATAIN3 */ | |
| 64 | - {C2C_DATAIN4, (IEN | M0)}, /* C2C_DATAIN4 */ | |
| 65 | - {C2C_DATAIN5, (IEN | M0)}, /* C2C_DATAIN5 */ | |
| 66 | - {C2C_DATAIN6, (IEN | M0)}, /* C2C_DATAIN6 */ | |
| 67 | - {C2C_DATAIN7, (IEN | M0)}, /* C2C_DATAIN7 */ | |
| 68 | - {C2C_CLKIN1, (IEN | M0)}, /* C2C_CLKIN1 */ | |
| 69 | - {C2C_CLKIN0, (IEN | M0)}, /* C2C_CLKIN0 */ | |
| 70 | - {C2C_CLKOUT0, (M0)}, /* C2C_CLKOUT0 */ | |
| 71 | - {C2C_CLKOUT1, (M0)}, /* C2C_CLKOUT1 */ | |
| 72 | - {C2C_DATAOUT0, (M0)}, /* C2C_DATAOUT0 */ | |
| 73 | - {C2C_DATAOUT1, (M0)}, /* C2C_DATAOUT1 */ | |
| 74 | - {C2C_DATAOUT2, (M0)}, /* C2C_DATAOUT2 */ | |
| 75 | - {C2C_DATAOUT3, (M0)}, /* C2C_DATAOUT3 */ | |
| 76 | - {C2C_DATAOUT4, (M0)}, /* C2C_DATAOUT4 */ | |
| 77 | - {C2C_DATAOUT5, (M0)}, /* C2C_DATAOUT5 */ | |
| 78 | - {C2C_DATAOUT6, (M0)}, /* C2C_DATAOUT6 */ | |
| 79 | - {C2C_DATAOUT7, (M0)}, /* C2C_DATAOUT7 */ | |
| 80 | - {C2C_DATA8, (IEN | M0)}, /* C2C_DATA8 */ | |
| 81 | - {C2C_DATA9, (IEN | M0)}, /* C2C_DATA9 */ | |
| 82 | - {C2C_DATA10, (IEN | M0)}, /* C2C_DATA10 */ | |
| 83 | - {C2C_DATA11, (IEN | M0)}, /* C2C_DATA11 */ | |
| 84 | - {C2C_DATA12, (IEN | M0)}, /* C2C_DATA12 */ | |
| 85 | - {C2C_DATA13, (IEN | M0)}, /* C2C_DATA13 */ | |
| 86 | - {C2C_DATA14, (IEN | M0)}, /* C2C_DATA14 */ | |
| 87 | - {C2C_DATA15, (IEN | M0)}, /* C2C_DATA15 */ | |
| 88 | - {LLIB_WAKEREQOUT, (PTU | IEN | M6)}, /* GPIO2_32 */ | |
| 89 | - {LLIA_WAKEREQOUT, (M1)}, /* C2C_WAKEREQOUT */ | |
| 90 | - {HSI1_ACREADY, (PTD | M6)}, /* GPIO3_64 */ | |
| 91 | - {HSI1_CAREADY, (PTD | M6)}, /* GPIO3_65 */ | |
| 92 | - {HSI1_ACWAKE, (PTD | IEN | M6)}, /* GPIO3_66 */ | |
| 93 | - {HSI1_CAWAKE, (PTU | IEN | M6)}, /* GPIO3_67 */ | |
| 94 | - {HSI1_ACFLAG, (PTD | IEN | M6)}, /* GPIO3_68 */ | |
| 95 | - {HSI1_ACDATA, (PTD | M6)}, /* GPIO3_69 */ | |
| 96 | - {HSI1_CAFLAG, (M6)}, /* GPIO3_70 */ | |
| 97 | - {HSI1_CADATA, (M6)}, /* GPIO3_71 */ | |
| 98 | - {UART1_TX, (M0)}, /* UART1_TX */ | |
| 99 | - {UART1_CTS, (PTU | IEN | M0)}, /* UART1_CTS */ | |
| 100 | - {UART1_RX, (PTU | IEN | M0)}, /* UART1_RX */ | |
| 101 | - {UART1_RTS, (M0)}, /* UART1_RTS */ | |
| 102 | - {HSI2_CAREADY, (IEN | M0)}, /* HSI2_CAREADY */ | |
| 103 | - {HSI2_ACREADY, (OFF_EN | M0)}, /* HSI2_ACREADY */ | |
| 104 | - {HSI2_CAWAKE, (IEN | PTD | M0)}, /* HSI2_CAWAKE */ | |
| 105 | - {HSI2_ACWAKE, (M0)}, /* HSI2_ACWAKE */ | |
| 106 | - {HSI2_CAFLAG, (IEN | PTD | M0)}, /* HSI2_CAFLAG */ | |
| 107 | - {HSI2_CADATA, (IEN | PTD | M0)}, /* HSI2_CADATA */ | |
| 108 | - {HSI2_ACFLAG, (M0)}, /* HSI2_ACFLAG */ | |
| 109 | - {HSI2_ACDATA, (M0)}, /* HSI2_ACDATA */ | |
| 110 | - {UART2_RTS, (IEN | M1)}, /* MCSPI3_SOMI */ | |
| 111 | - {UART2_CTS, (IEN | M1)}, /* MCSPI3_CS0 */ | |
| 112 | - {UART2_RX, (IEN | M1)}, /* MCSPI3_SIMO */ | |
| 113 | - {UART2_TX, (IEN | M1)}, /* MCSPI3_CLK */ | |
| 114 | - {TIMER10_PWM_EVT, (IEN | M0)}, /* TIMER10_PWM_EVT */ | |
| 115 | - {DSIPORTA_TE0, (IEN | M0)}, /* DSIPORTA_TE0 */ | |
| 116 | - {DSIPORTA_LANE0X, (IEN | M0)}, /* DSIPORTA_LANE0X */ | |
| 117 | - {DSIPORTA_LANE0Y, (IEN | M0)}, /* DSIPORTA_LANE0Y */ | |
| 118 | - {DSIPORTA_LANE1X, (IEN | M0)}, /* DSIPORTA_LANE1X */ | |
| 119 | - {DSIPORTA_LANE1Y, (IEN | M0)}, /* DSIPORTA_LANE1Y */ | |
| 120 | - {DSIPORTA_LANE2X, (IEN | M0)}, /* DSIPORTA_LANE2X */ | |
| 121 | - {DSIPORTA_LANE2Y, (IEN | M0)}, /* DSIPORTA_LANE2Y */ | |
| 122 | - {DSIPORTA_LANE3X, (IEN | M0)}, /* DSIPORTA_LANE3X */ | |
| 123 | - {DSIPORTA_LANE3Y, (IEN | M0)}, /* DSIPORTA_LANE3Y */ | |
| 124 | - {DSIPORTA_LANE4X, (IEN | M0)}, /* DSIPORTA_LANE4X */ | |
| 125 | - {DSIPORTA_LANE4Y, (IEN | M0)}, /* DSIPORTA_LANE4Y */ | |
| 126 | - {TIMER9_PWM_EVT, (IEN | M0)}, /* TIMER9_PWM_EVT */ | |
| 127 | - {DSIPORTC_TE0, (IEN | M0)}, /* DSIPORTC_TE0 */ | |
| 128 | - {DSIPORTC_LANE0X, (IEN | M0)}, /* DSIPORTC_LANE0X */ | |
| 129 | - {DSIPORTC_LANE0Y, (IEN | M0)}, /* DSIPORTC_LANE0Y */ | |
| 130 | - {DSIPORTC_LANE1X, (IEN | M0)}, /* DSIPORTC_LANE1X */ | |
| 131 | - {DSIPORTC_LANE1Y, (IEN | M0)}, /* DSIPORTC_LANE1Y */ | |
| 132 | - {DSIPORTC_LANE2X, (IEN | M0)}, /* DSIPORTC_LANE2X */ | |
| 133 | - {DSIPORTC_LANE2Y, (IEN | M0)}, /* DSIPORTC_LANE2Y */ | |
| 134 | - {DSIPORTC_LANE3X, (IEN | M0)}, /* DSIPORTC_LANE3X */ | |
| 135 | - {DSIPORTC_LANE3Y, (IEN | M0)}, /* DSIPORTC_LANE3Y */ | |
| 136 | - {DSIPORTC_LANE4X, (IEN | M0)}, /* DSIPORTC_LANE4X */ | |
| 137 | - {DSIPORTC_LANE4Y, (IEN | M0)}, /* DSIPORTC_LANE4Y */ | |
| 138 | - {RFBI_HSYNC0, (M4)}, /* KBD_COL5 */ | |
| 139 | - {RFBI_TE_VSYNC0, (PTD | M6)}, /* GPIO6_161 */ | |
| 140 | - {RFBI_RE, (M4)}, /* KBD_COL4 */ | |
| 141 | - {RFBI_A0, (PTD | IEN | M6)}, /* GPIO6_165 */ | |
| 142 | - {RFBI_DATA8, (M4)}, /* KBD_COL3 */ | |
| 143 | - {RFBI_DATA9, (PTD | M6)}, /* GPIO6_175 */ | |
| 144 | - {RFBI_DATA10, (PTD | M6)}, /* GPIO6_176 */ | |
| 145 | - {RFBI_DATA11, (PTD | M6)}, /* GPIO6_177 */ | |
| 146 | - {RFBI_DATA12, (PTD | M6)}, /* GPIO6_178 */ | |
| 147 | - {RFBI_DATA13, (PTU | IEN | M6)}, /* GPIO6_179 */ | |
| 148 | - {RFBI_DATA14, (M4)}, /* KBD_COL7 */ | |
| 149 | - {RFBI_DATA15, (M4)}, /* KBD_COL6 */ | |
| 150 | - {GPIO6_182, (M6)}, /* GPIO6_182 */ | |
| 151 | - {GPIO6_183, (PTD | M6)}, /* GPIO6_183 */ | |
| 152 | - {GPIO6_184, (M4)}, /* KBD_COL2 */ | |
| 153 | - {GPIO6_185, (PTD | IEN | M6)}, /* GPIO6_185 */ | |
| 154 | - {GPIO6_186, (PTD | M6)}, /* GPIO6_186 */ | |
| 155 | - {GPIO6_187, (PTU | IEN | M4)}, /* KBD_ROW2 */ | |
| 156 | - {RFBI_DATA0, (PTD | M6)}, /* GPIO6_166 */ | |
| 157 | - {RFBI_DATA1, (PTD | M6)}, /* GPIO6_167 */ | |
| 158 | - {RFBI_DATA2, (PTD | M6)}, /* GPIO6_168 */ | |
| 159 | - {RFBI_DATA3, (PTD | IEN | M6)}, /* GPIO6_169 */ | |
| 160 | - {RFBI_DATA4, (IEN | M6)}, /* GPIO6_170 */ | |
| 161 | - {RFBI_DATA5, (IEN | M6)}, /* GPIO6_171 */ | |
| 162 | - {RFBI_DATA6, (PTD | M6)}, /* GPIO6_172 */ | |
| 163 | - {RFBI_DATA7, (PTD | M6)}, /* GPIO6_173 */ | |
| 164 | - {RFBI_CS0, (PTD | IEN | M6)}, /* GPIO6_163 */ | |
| 165 | - {RFBI_WE, (PTD | M6)}, /* GPIO6_162 */ | |
| 166 | - {MCSPI2_CS0, (M0)}, /* MCSPI2_CS0 */ | |
| 167 | - {MCSPI2_CLK, (IEN | M0)}, /* MCSPI2_CLK */ | |
| 168 | - {MCSPI2_SIMO, (IEN | M0)}, /* MCSPI2_SIMO*/ | |
| 169 | - {MCSPI2_SOMI, (PTU | IEN | M0)}, /* MCSPI2_SOMI*/ | |
| 170 | - {I2C4_SCL, (IEN | M0)}, /* I2C4_SCL */ | |
| 171 | - {I2C4_SDA, (IEN | M0)}, /* I2C4_SDA */ | |
| 172 | - {HDMI_CEC, (IEN | M0)}, /* HDMI_CEC */ | |
| 173 | - {HDMI_HPD, (PTD | IEN | M0)}, /* HDMI_HPD */ | |
| 174 | - {HDMI_DDC_SCL, (IEN | M0)}, /* HDMI_DDC_SCL */ | |
| 175 | - {HDMI_DDC_SDA, (IEN | M0)}, /* HDMI_DDC_SDA */ | |
| 176 | - {CSIPORTA_LANE0X, (IEN | M0)}, /* CSIPORTA_LANE0X */ | |
| 177 | - {CSIPORTA_LANE0Y, (IEN | M0)}, /* CSIPORTA_LANE0Y */ | |
| 178 | - {CSIPORTA_LANE1Y, (IEN | M0)}, /* CSIPORTA_LANE1Y */ | |
| 179 | - {CSIPORTA_LANE1X, (IEN | M0)}, /* CSIPORTA_LANE1X */ | |
| 180 | - {CSIPORTA_LANE2Y, (IEN | M0)}, /* CSIPORTA_LANE2Y */ | |
| 181 | - {CSIPORTA_LANE2X, (IEN | M0)}, /* CSIPORTA_LANE2X */ | |
| 182 | - {CSIPORTA_LANE3X, (IEN | M0)}, /* CSIPORTA_LANE3X */ | |
| 183 | - {CSIPORTA_LANE3Y, (IEN | M0)}, /* CSIPORTA_LANE3Y */ | |
| 184 | - {CSIPORTA_LANE4X, (IEN | M0)}, /* CSIPORTA_LANE4X */ | |
| 185 | - {CSIPORTA_LANE4Y, (IEN | M0)}, /* CSIPORTA_LANE4Y */ | |
| 186 | - {CSIPORTB_LANE0X, (IEN | M0)}, /* CSIPORTB_LANE0X */ | |
| 187 | - {CSIPORTB_LANE0Y, (IEN | M0)}, /* CSIPORTB_LANE0Y */ | |
| 188 | - {CSIPORTB_LANE1Y, (IEN | M0)}, /* CSIPORTB_LANE1Y */ | |
| 189 | - {CSIPORTB_LANE1X, (IEN | M0)}, /* CSIPORTB_LANE1X */ | |
| 190 | - {CSIPORTB_LANE2Y, (IEN | M0)}, /* CSIPORTB_LANE2Y */ | |
| 191 | - {CSIPORTB_LANE2X, (IEN | M0)}, /* CSIPORTB_LANE2X */ | |
| 192 | - {CSIPORTC_LANE0Y, (IEN | M0)}, /* CSIPORTC_LANE0Y */ | |
| 193 | - {CSIPORTC_LANE0X, (IEN | M0)}, /* CSIPORTC_LANE0X */ | |
| 194 | - {CSIPORTC_LANE1Y, (IEN | M0)}, /* CSIPORTC_LANE1Y */ | |
| 195 | - {CSIPORTC_LANE1X, (IEN | M0)}, /* CSIPORTC_LANE1X */ | |
| 196 | - {CAM_SHUTTER, (M0)}, /* CAM_SHUTTER */ | |
| 197 | - {CAM_STROBE, (M0)}, /* CAM_STROBE */ | |
| 198 | - {CAM_GLOBALRESET, (IEN | M0)}, /* CAM_GLOBALRESET */ | |
| 199 | - {TIMER11_PWM_EVT, (PTD | M6)}, /* GPIO8_227 */ | |
| 200 | - {TIMER5_PWM_EVT, (PTD | M6)}, /* GPIO8_228 */ | |
| 201 | - {TIMER6_PWM_EVT, (PTD | M6)}, /* GPIO8_229 */ | |
| 202 | - {TIMER8_PWM_EVT, (PTU | M6)}, /* GPIO8_230 */ | |
| 203 | - {I2C3_SCL, (IEN | M0)}, /* I2C3_SCL */ | |
| 204 | - {I2C3_SDA, (IEN | M0)}, /* I2C3_SDA */ | |
| 205 | - {GPIO8_233, (IEN | M2)}, /* TIMER8_PWM_EVT */ | |
| 206 | - {ABE_CLKS, (IEN | M0)}, /* ABE_CLKS */ | |
| 207 | - {ABEDMIC_DIN1, (IEN | M0)}, /* ABEDMIC_DIN1 */ | |
| 208 | - {ABEDMIC_DIN2, (IEN | M0)}, /* ABEDMIC_DIN2 */ | |
| 209 | - {ABEDMIC_DIN3, (IEN | M0)}, /* ABEDMIC_DIN3 */ | |
| 210 | - {ABEDMIC_CLK1, (M0)}, /* ABEDMIC_CLK1 */ | |
| 211 | - {ABEDMIC_CLK2, (IEN | M1)}, /* ABEMCBSP1_FSX */ | |
| 212 | - {ABEDMIC_CLK3, (M1)}, /* ABEMCBSP1_DX */ | |
| 213 | - {ABESLIMBUS1_CLOCK, (IEN | M1)}, /* ABEMCBSP1_CLKX */ | |
| 214 | - {ABESLIMBUS1_DATA, (IEN | M1)}, /* ABEMCBSP1_DR */ | |
| 215 | - {ABEMCBSP2_DR, (IEN | M0)}, /* ABEMCBSP2_DR */ | |
| 216 | - {ABEMCBSP2_DX, (M0)}, /* ABEMCBSP2_DX */ | |
| 217 | - {ABEMCBSP2_FSX, (IEN | M0)}, /* ABEMCBSP2_FSX */ | |
| 218 | - {ABEMCBSP2_CLKX, (IEN | M0)}, /* ABEMCBSP2_CLKX */ | |
| 219 | - {ABEMCPDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_UL_DATA */ | |
| 220 | - {ABEMCPDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_DL_DATA */ | |
| 221 | - {ABEMCPDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_FRAME */ | |
| 222 | - {ABEMCPDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_LB_CLK */ | |
| 223 | - {WLSDIO_CLK, (PTU | IEN | M0)}, /* WLSDIO_CLK */ | |
| 224 | - {WLSDIO_CMD, (PTU | IEN | M0)}, /* WLSDIO_CMD */ | |
| 225 | - {WLSDIO_DATA0, (PTU | IEN | M0)}, /* WLSDIO_DATA0*/ | |
| 226 | - {WLSDIO_DATA1, (PTU | IEN | M0)}, /* WLSDIO_DATA1*/ | |
| 227 | - {WLSDIO_DATA2, (PTU | IEN | M0)}, /* WLSDIO_DATA2*/ | |
| 228 | - {WLSDIO_DATA3, (PTU | IEN | M0)}, /* WLSDIO_DATA3*/ | |
| 229 | - {UART5_RX, (PTU | IEN | M0)}, /* UART5_RX */ | |
| 230 | - {UART5_TX, (M0)}, /* UART5_TX */ | |
| 231 | - {UART5_CTS, (PTU | IEN | M0)}, /* UART5_CTS */ | |
| 232 | - {UART5_RTS, (M0)}, /* UART5_RTS */ | |
| 233 | - {I2C2_SCL, (IEN | M0)}, /* I2C2_SCL */ | |
| 234 | - {I2C2_SDA, (IEN | M0)}, /* I2C2_SDA */ | |
| 235 | - {MCSPI1_CLK, (M6)}, /* GPIO5_140 */ | |
| 236 | - {MCSPI1_SOMI, (IEN | M6)}, /* GPIO5_141 */ | |
| 237 | - {MCSPI1_SIMO, (PTD | M6)}, /* GPIO5_142 */ | |
| 238 | - {MCSPI1_CS0, (PTD | M6)}, /* GPIO5_143 */ | |
| 239 | - {MCSPI1_CS1, (PTD | IEN | M6)}, /* GPIO5_144 */ | |
| 240 | - {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */ | |
| 241 | - {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */ | |
| 242 | - {PERSLIMBUS2_CLOCK, (PTD | M6)}, /* GPIO5_145 */ | |
| 243 | - {PERSLIMBUS2_DATA, (PTD | IEN | M6)}, /* GPIO5_146 */ | |
| 244 | - {UART6_TX, (PTU | IEN | M6)}, /* GPIO5_149 */ | |
| 245 | - {UART6_RX, (PTU | IEN | M6)}, /* GPIO5_150 */ | |
| 246 | - {UART6_CTS, (PTU | IEN | M6)}, /* GPIO5_151 */ | |
| 247 | - {UART6_RTS, (PTU | M0)}, /* UART6_RTS */ | |
| 248 | - {UART3_CTS_RCTX, (PTU | IEN | M6)}, /* GPIO5_153 */ | |
| 249 | - {UART3_RTS_IRSD, (PTU | IEN | M1)}, /* HDQ_SIO */ | |
| 250 | - {I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */ | |
| 251 | - {I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */ | |
| 252 | - | |
| 253 | -}; | |
| 254 | - | |
| 255 | -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { | |
| 256 | - | |
| 257 | -/* | |
| 258 | - * This pad keeps C2C Module always enabled. | |
| 259 | - * Putting this in safe mode do not cause the issue. | |
| 260 | - * C2C driver could enable this mux setting if needed. | |
| 261 | - */ | |
| 262 | - {LLIA_WAKEREQIN, (M7)}, /* SAFE MODE */ | |
| 263 | - {LLIB_WAKEREQIN, (M7)}, /* SAFE MODE */ | |
| 264 | - {DRM_EMU0, (PTU | IEN | M0)}, /* DRM_EMU0 */ | |
| 265 | - {DRM_EMU1, (PTU | IEN | M0)}, /* DRM_EMU1 */ | |
| 266 | - {JTAG_NTRST, (IEN | M0)}, /* JTAG_NTRST */ | |
| 267 | - {JTAG_TCK, (IEN | M0)}, /* JTAG_TCK */ | |
| 268 | - {JTAG_RTCK, (M0)}, /* JTAG_RTCK */ | |
| 269 | - {JTAG_TMSC, (IEN | M0)}, /* JTAG_TMSC */ | |
| 270 | - {JTAG_TDI, (IEN | M0)}, /* JTAG_TDI */ | |
| 271 | - {JTAG_TDO, (M0)}, /* JTAG_TDO */ | |
| 272 | - {FREF_CLK_IOREQ, (IEN | M0)}, /* FREF_CLK_IOREQ */ | |
| 273 | - {FREF_CLK0_OUT, (M0)}, /* FREF_CLK0_OUT */ | |
| 274 | - {FREF_CLK1_OUT, (M0)}, /* FREF_CLK1_OUT */ | |
| 275 | - {FREF_CLK2_OUT, (M0)}, /* FREF_CLK2_OUT */ | |
| 276 | - {FREF_CLK2_REQ, (PTU | IEN | M6)}, /* GPIO1_WK9 */ | |
| 277 | - {FREF_CLK1_REQ, (PTD | IEN | M6)}, /* GPIO1_WK8 */ | |
| 278 | - {SYS_NRESPWRON, (IEN | M0)}, /* SYS_NRESPWRON */ | |
| 279 | - {SYS_NRESWARM, (PTU | IEN | M0)}, /* SYS_NRESWARM */ | |
| 280 | - {SYS_PWR_REQ, (M0)}, /* SYS_PWR_REQ */ | |
| 281 | - {SYS_NIRQ1, (PTU | IEN | M0)}, /* SYS_NIRQ1 */ | |
| 282 | - {SYS_NIRQ2, (PTU | IEN | M0)}, /* SYS_NIRQ2 */ | |
| 283 | - {SYS_BOOT0, (IEN | M0)}, /* SYS_BOOT0 */ | |
| 284 | - {SYS_BOOT1, (IEN | M0)}, /* SYS_BOOT1 */ | |
| 285 | - {SYS_BOOT2, (IEN | M0)}, /* SYS_BOOT2 */ | |
| 286 | - {SYS_BOOT3, (IEN | M0)}, /* SYS_BOOT3 */ | |
| 287 | - {SYS_BOOT4, (IEN | M0)}, /* SYS_BOOT4 */ | |
| 288 | - {SYS_BOOT5, (IEN | M0)}, /* SYS_BOOT5 */ | |
| 289 | - | |
| 290 | -}; | |
| 291 | - | |
| 292 | 58 | #endif /* _EVM4430_MUX_DATA_H */ |
board/ti/panda/panda.c
| ... | ... | @@ -284,36 +284,6 @@ |
| 284 | 284 | sizeof(struct pad_conf_entry)); |
| 285 | 285 | } |
| 286 | 286 | |
| 287 | -void set_muxconf_regs_non_essential(void) | |
| 288 | -{ | |
| 289 | - do_set_mux((*ctrl)->control_padconf_core_base, | |
| 290 | - core_padconf_array_non_essential, | |
| 291 | - sizeof(core_padconf_array_non_essential) / | |
| 292 | - sizeof(struct pad_conf_entry)); | |
| 293 | - | |
| 294 | - if (omap_revision() < OMAP4460_ES1_0) | |
| 295 | - do_set_mux((*ctrl)->control_padconf_core_base, | |
| 296 | - core_padconf_array_non_essential_4430, | |
| 297 | - sizeof(core_padconf_array_non_essential_4430) / | |
| 298 | - sizeof(struct pad_conf_entry)); | |
| 299 | - else | |
| 300 | - do_set_mux((*ctrl)->control_padconf_core_base, | |
| 301 | - core_padconf_array_non_essential_4460, | |
| 302 | - sizeof(core_padconf_array_non_essential_4460) / | |
| 303 | - sizeof(struct pad_conf_entry)); | |
| 304 | - | |
| 305 | - do_set_mux((*ctrl)->control_padconf_wkup_base, | |
| 306 | - wkup_padconf_array_non_essential, | |
| 307 | - sizeof(wkup_padconf_array_non_essential) / | |
| 308 | - sizeof(struct pad_conf_entry)); | |
| 309 | - | |
| 310 | - if (omap_revision() < OMAP4460_ES1_0) | |
| 311 | - do_set_mux((*ctrl)->control_padconf_wkup_base, | |
| 312 | - wkup_padconf_array_non_essential_4430, | |
| 313 | - sizeof(wkup_padconf_array_non_essential_4430) / | |
| 314 | - sizeof(struct pad_conf_entry)); | |
| 315 | -} | |
| 316 | - | |
| 317 | 287 | #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) |
| 318 | 288 | int board_mmc_init(bd_t *bis) |
| 319 | 289 | { |
board/ti/panda/panda_mux_data.h
| ... | ... | @@ -84,191 +84,5 @@ |
| 84 | 84 | |
| 85 | 85 | }; |
| 86 | 86 | |
| 87 | -const struct pad_conf_entry core_padconf_array_non_essential[] = { | |
| 88 | - {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ | |
| 89 | - {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ | |
| 90 | - {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ | |
| 91 | - {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ | |
| 92 | - {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ | |
| 93 | - {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ | |
| 94 | - {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ | |
| 95 | - {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ | |
| 96 | - {GPMC_A16, (M3)}, /* gpio_40 */ | |
| 97 | - {GPMC_A17, (PTD | M3)}, /* gpio_41 */ | |
| 98 | - {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ | |
| 99 | - {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ | |
| 100 | - {GPMC_A20, (IEN | M3)}, /* gpio_44 */ | |
| 101 | - {GPMC_A21, (M3)}, /* gpio_45 */ | |
| 102 | - {GPMC_A22, (M3)}, /* gpio_46 */ | |
| 103 | - {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ | |
| 104 | - {GPMC_A24, (PTD | M3)}, /* gpio_48 */ | |
| 105 | - {GPMC_A25, (PTD | M3)}, /* gpio_49 */ | |
| 106 | - {GPMC_NCS0, (M3)}, /* gpio_50 */ | |
| 107 | - {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ | |
| 108 | - {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ | |
| 109 | - {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ | |
| 110 | - {GPMC_NWP, (M3)}, /* gpio_54 */ | |
| 111 | - {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ | |
| 112 | - {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ | |
| 113 | - {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ | |
| 114 | - {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ | |
| 115 | - {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ | |
| 116 | - {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ | |
| 117 | - {C2C_DATA12, (PTU | IEN | M3)}, /* gpio_101 */ | |
| 118 | - {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ | |
| 119 | - {C2C_DATA14, (M1)}, /* dsi2_te0 */ | |
| 120 | - {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ | |
| 121 | - {HDMI_HPD, (M0)}, /* hdmi_hpd */ | |
| 122 | - {HDMI_CEC, (M0)}, /* hdmi_cec */ | |
| 123 | - {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ | |
| 124 | - {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ | |
| 125 | - {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ | |
| 126 | - {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ | |
| 127 | - {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ | |
| 128 | - {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ | |
| 129 | - {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ | |
| 130 | - {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ | |
| 131 | - {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ | |
| 132 | - {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ | |
| 133 | - {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ | |
| 134 | - {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ | |
| 135 | - {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ | |
| 136 | - {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ | |
| 137 | - {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ | |
| 138 | - {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ | |
| 139 | - {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ | |
| 140 | - {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ | |
| 141 | - {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ | |
| 142 | - {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ | |
| 143 | - {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ | |
| 144 | - {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ | |
| 145 | - {ABE_MCBSP1_CLKX, (IEN | M0)}, /* abe_mcbsp1_clkx */ | |
| 146 | - {ABE_MCBSP1_DR, (IEN | M0)}, /* abe_mcbsp1_dr */ | |
| 147 | - {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ | |
| 148 | - {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ | |
| 149 | - {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ | |
| 150 | - {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ | |
| 151 | - {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ | |
| 152 | - {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ | |
| 153 | - {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ | |
| 154 | - {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ | |
| 155 | - {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ | |
| 156 | - {ABE_DMIC_DIN2, (PTU | IEN | M3)}, /* gpio_121 */ | |
| 157 | - {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ | |
| 158 | - {UART2_CTS, (PTU | IEN | M7)}, /* uart2_cts */ | |
| 159 | - {UART2_RTS, (M7)}, /* uart2_rts */ | |
| 160 | - {UART2_RX, (PTU | IEN | M7)}, /* uart2_rx */ | |
| 161 | - {UART2_TX, (M7)}, /* uart2_tx */ | |
| 162 | - {HDQ_SIO, (M3)}, /* gpio_127 */ | |
| 163 | - {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ | |
| 164 | - {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ | |
| 165 | - {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ | |
| 166 | - {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ | |
| 167 | - {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ | |
| 168 | - {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ | |
| 169 | - {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ | |
| 170 | - {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ | |
| 171 | - {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ | |
| 172 | - {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ | |
| 173 | - {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ | |
| 174 | - {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ | |
| 175 | - {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ | |
| 176 | - {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ | |
| 177 | - {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ | |
| 178 | - {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ | |
| 179 | - {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ | |
| 180 | - {UART4_RX, (IEN | M0)}, /* uart4_rx */ | |
| 181 | - {UART4_TX, (M0)}, /* uart4_tx */ | |
| 182 | - {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ | |
| 183 | - {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ | |
| 184 | - {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ | |
| 185 | - {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ | |
| 186 | - {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ | |
| 187 | - {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ | |
| 188 | - {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ | |
| 189 | - {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ | |
| 190 | - {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ | |
| 191 | - {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ | |
| 192 | - {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ | |
| 193 | - {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ | |
| 194 | - {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ | |
| 195 | - {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ | |
| 196 | - {UNIPRO_TX0, (PTD | IEN | M3)}, /* gpio_171 */ | |
| 197 | - {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ | |
| 198 | - {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ | |
| 199 | - {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ | |
| 200 | - {UNIPRO_TX2, (PTU | IEN | M3)}, /* gpio_0 */ | |
| 201 | - {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ | |
| 202 | - {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ | |
| 203 | - {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ | |
| 204 | - {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ | |
| 205 | - {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ | |
| 206 | - {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ | |
| 207 | - {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ | |
| 208 | - {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ | |
| 209 | - {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ | |
| 210 | - {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ | |
| 211 | - {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ | |
| 212 | - {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ | |
| 213 | - {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ | |
| 214 | - {SYS_BOOT1, (M3)}, /* gpio_185 */ | |
| 215 | - {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ | |
| 216 | - {SYS_BOOT3, (M3)}, /* gpio_187 */ | |
| 217 | - {SYS_BOOT4, (M3)}, /* gpio_188 */ | |
| 218 | - {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ | |
| 219 | - {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ | |
| 220 | - {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ | |
| 221 | - {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ | |
| 222 | - {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ | |
| 223 | - {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ | |
| 224 | - {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ | |
| 225 | - {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ | |
| 226 | - {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ | |
| 227 | - {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ | |
| 228 | - {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ | |
| 229 | - {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ | |
| 230 | - {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ | |
| 231 | - {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ | |
| 232 | - {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ | |
| 233 | - {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ | |
| 234 | - {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ | |
| 235 | - {DPM_EMU16, (M3)}, /* gpio_27 */ | |
| 236 | - {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ | |
| 237 | - {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ | |
| 238 | - {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ | |
| 239 | -}; | |
| 240 | - | |
| 241 | -const struct pad_conf_entry core_padconf_array_non_essential_4430[] = { | |
| 242 | - {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ | |
| 243 | -}; | |
| 244 | - | |
| 245 | -const struct pad_conf_entry core_padconf_array_non_essential_4460[] = { | |
| 246 | - {ABE_MCBSP2_CLKX, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */ | |
| 247 | -}; | |
| 248 | - | |
| 249 | -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { | |
| 250 | - {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ | |
| 251 | - {PAD1_SIM_CLK, (M0)}, /* sim_clk */ | |
| 252 | - {PAD0_SIM_RESET, (M0)}, /* sim_reset */ | |
| 253 | - {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ | |
| 254 | - {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ | |
| 255 | - {PAD1_FREF_XTAL_IN, (M0)}, /* # */ | |
| 256 | - {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ | |
| 257 | - {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ | |
| 258 | - {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ | |
| 259 | - {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ | |
| 260 | - {PAD0_FREF_CLK4_OUT, (PTU | M3)}, /* led status_2 */ | |
| 261 | - {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ | |
| 262 | - {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ | |
| 263 | - {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ | |
| 264 | - {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ | |
| 265 | - {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ | |
| 266 | - {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ | |
| 267 | -}; | |
| 268 | - | |
| 269 | -const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = { | |
| 270 | - {PAD1_FREF_CLK4_REQ, (PTU | M3)}, /* led status_1 */ | |
| 271 | -}; | |
| 272 | - | |
| 273 | 87 | #endif /* _PANDA_MUX_DATA_H_ */ |
board/ti/sdp4430/sdp.c
| ... | ... | @@ -73,26 +73,6 @@ |
| 73 | 73 | sizeof(struct pad_conf_entry)); |
| 74 | 74 | } |
| 75 | 75 | |
| 76 | -void set_muxconf_regs_non_essential(void) | |
| 77 | -{ | |
| 78 | - do_set_mux((*ctrl)->control_padconf_core_base, | |
| 79 | - core_padconf_array_non_essential, | |
| 80 | - sizeof(core_padconf_array_non_essential) / | |
| 81 | - sizeof(struct pad_conf_entry)); | |
| 82 | - | |
| 83 | - do_set_mux((*ctrl)->control_padconf_wkup_base, | |
| 84 | - wkup_padconf_array_non_essential, | |
| 85 | - sizeof(wkup_padconf_array_non_essential) / | |
| 86 | - sizeof(struct pad_conf_entry)); | |
| 87 | - | |
| 88 | - if (omap_revision() < OMAP4460_ES1_0) { | |
| 89 | - do_set_mux((*ctrl)->control_padconf_wkup_base, | |
| 90 | - wkup_padconf_array_non_essential_4430, | |
| 91 | - sizeof(wkup_padconf_array_non_essential_4430) / | |
| 92 | - sizeof(struct pad_conf_entry)); | |
| 93 | - } | |
| 94 | -} | |
| 95 | - | |
| 96 | 76 | #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) |
| 97 | 77 | int board_mmc_init(bd_t *bis) |
| 98 | 78 | { |
board/ti/sdp4430/sdp4430_mux_data.h
| ... | ... | @@ -65,202 +65,5 @@ |
| 65 | 65 | |
| 66 | 66 | }; |
| 67 | 67 | |
| 68 | -const struct pad_conf_entry core_padconf_array_non_essential[] = { | |
| 69 | - {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ | |
| 70 | - {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ | |
| 71 | - {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ | |
| 72 | - {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ | |
| 73 | - {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ | |
| 74 | - {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ | |
| 75 | - {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ | |
| 76 | - {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ | |
| 77 | - {GPMC_A16, (M3)}, /* gpio_40 */ | |
| 78 | - {GPMC_A17, (PTD | M3)}, /* gpio_41 */ | |
| 79 | - {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ | |
| 80 | - {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ | |
| 81 | - {GPMC_A20, (IEN | M3)}, /* gpio_44 */ | |
| 82 | - {GPMC_A21, (M3)}, /* gpio_45 */ | |
| 83 | - {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ | |
| 84 | - {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ | |
| 85 | - {GPMC_A24, (PTD | M3)}, /* gpio_48 */ | |
| 86 | - {GPMC_A25, (PTD | M3)}, /* gpio_49 */ | |
| 87 | - {GPMC_NCS0, (M3)}, /* gpio_50 */ | |
| 88 | - {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ | |
| 89 | - {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ | |
| 90 | - {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ | |
| 91 | - {GPMC_NWP, (M3)}, /* gpio_54 */ | |
| 92 | - {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ | |
| 93 | - {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ | |
| 94 | - {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ | |
| 95 | - {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ | |
| 96 | - {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ | |
| 97 | - {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ | |
| 98 | - {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ | |
| 99 | - {C2C_DATA12, (M1)}, /* dsi1_te0 */ | |
| 100 | - {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ | |
| 101 | - {C2C_DATA14, (M1)}, /* dsi2_te0 */ | |
| 102 | - {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ | |
| 103 | - {HDMI_HPD, (M0)}, /* hdmi_hpd */ | |
| 104 | - {HDMI_CEC, (M0)}, /* hdmi_cec */ | |
| 105 | - {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ | |
| 106 | - {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ | |
| 107 | - {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ | |
| 108 | - {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ | |
| 109 | - {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ | |
| 110 | - {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ | |
| 111 | - {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ | |
| 112 | - {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ | |
| 113 | - {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ | |
| 114 | - {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ | |
| 115 | - {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ | |
| 116 | - {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ | |
| 117 | - {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ | |
| 118 | - {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ | |
| 119 | - {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ | |
| 120 | - {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ | |
| 121 | - {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ | |
| 122 | - {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ | |
| 123 | - {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ | |
| 124 | - {USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cawake */ | |
| 125 | - {USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cadata */ | |
| 126 | - {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caflag */ | |
| 127 | - {USBB1_ULPITLL_NXT, (OFF_EN | M1)}, /* hsi1_acready */ | |
| 128 | - {USBB1_ULPITLL_DAT0, (OFF_EN | M1)}, /* hsi1_acwake */ | |
| 129 | - {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ | |
| 130 | - {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ | |
| 131 | - {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ | |
| 132 | - {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ | |
| 133 | - {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ | |
| 134 | - {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ | |
| 135 | - {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ | |
| 136 | - {ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_clkx */ | |
| 137 | - {ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dr */ | |
| 138 | - {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ | |
| 139 | - {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ | |
| 140 | - {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ | |
| 141 | - {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ | |
| 142 | - {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ | |
| 143 | - {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ | |
| 144 | - {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ | |
| 145 | - {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ | |
| 146 | - {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ | |
| 147 | - {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ | |
| 148 | - {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ | |
| 149 | - {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ | |
| 150 | - {UART2_RTS, (M0)}, /* uart2_rts */ | |
| 151 | - {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ | |
| 152 | - {UART2_TX, (M0)}, /* uart2_tx */ | |
| 153 | - {HDQ_SIO, (M3)}, /* gpio_127 */ | |
| 154 | - {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ | |
| 155 | - {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ | |
| 156 | - {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ | |
| 157 | - {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ | |
| 158 | - {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ | |
| 159 | - {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ | |
| 160 | - {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ | |
| 161 | - {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ | |
| 162 | - {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ | |
| 163 | - {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ | |
| 164 | - {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ | |
| 165 | - {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ | |
| 166 | - {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ | |
| 167 | - {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ | |
| 168 | - {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ | |
| 169 | - {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ | |
| 170 | - {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ | |
| 171 | - {UART4_RX, (IEN | M0)}, /* uart4_rx */ | |
| 172 | - {UART4_TX, (M0)}, /* uart4_tx */ | |
| 173 | - {USBB2_ULPITLL_CLK, (PTD | IEN | M3)}, /* gpio_157 */ | |
| 174 | - {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ | |
| 175 | - {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ | |
| 176 | - {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ | |
| 177 | - {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ | |
| 178 | - {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ | |
| 179 | - {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ | |
| 180 | - {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ | |
| 181 | - {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ | |
| 182 | - {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ | |
| 183 | - {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ | |
| 184 | - {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ | |
| 185 | - {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ | |
| 186 | - {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ | |
| 187 | - {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ | |
| 188 | - {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ | |
| 189 | - {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ | |
| 190 | - {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ | |
| 191 | - {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ | |
| 192 | - {UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */ | |
| 193 | - {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ | |
| 194 | - {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ | |
| 195 | - {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ | |
| 196 | - {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ | |
| 197 | - {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ | |
| 198 | - {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ | |
| 199 | - {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ | |
| 200 | - {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ | |
| 201 | - {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ | |
| 202 | - {SYS_NIRQ2, (M7)}, /* sys_nirq2 */ | |
| 203 | - {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ | |
| 204 | - {SYS_BOOT1, (M3)}, /* gpio_185 */ | |
| 205 | - {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ | |
| 206 | - {SYS_BOOT3, (PTD | IEN | M3)}, /* gpio_187 */ | |
| 207 | - {SYS_BOOT4, (M3)}, /* gpio_188 */ | |
| 208 | - {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ | |
| 209 | - {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ | |
| 210 | - {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ | |
| 211 | - {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ | |
| 212 | - {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ | |
| 213 | - {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ | |
| 214 | - {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ | |
| 215 | - {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ | |
| 216 | - {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ | |
| 217 | - {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ | |
| 218 | - {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ | |
| 219 | - {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ | |
| 220 | - {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ | |
| 221 | - {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ | |
| 222 | - {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ | |
| 223 | - {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ | |
| 224 | - {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ | |
| 225 | - {DPM_EMU16, (M3)}, /* gpio_27 */ | |
| 226 | - {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ | |
| 227 | - {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ | |
| 228 | - {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ | |
| 229 | - {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ | |
| 230 | - {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ | |
| 231 | - {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ | |
| 232 | - {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ | |
| 233 | - {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ | |
| 234 | - {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ | |
| 235 | - {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ | |
| 236 | - {I2C4_SDA, (PTU | IEN | M0)} /* i2c4_sda */ | |
| 237 | - | |
| 238 | -}; | |
| 239 | - | |
| 240 | -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { | |
| 241 | - {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ | |
| 242 | - {PAD1_SIM_CLK, (M0)}, /* sim_clk */ | |
| 243 | - {PAD0_SIM_RESET, (M0)}, /* sim_reset */ | |
| 244 | - {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ | |
| 245 | - {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ | |
| 246 | - {PAD1_FREF_XTAL_IN, (M0)}, /* # */ | |
| 247 | - {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ | |
| 248 | - {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ | |
| 249 | - {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ | |
| 250 | - {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 - Debug led-1 */ | |
| 251 | - {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ | |
| 252 | - {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 - Debug led-3 */ | |
| 253 | - {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ | |
| 254 | - {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ | |
| 255 | - {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ | |
| 256 | - {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ | |
| 257 | - {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ | |
| 258 | - {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ | |
| 259 | -}; | |
| 260 | - | |
| 261 | -const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = { | |
| 262 | - {PAD1_FREF_CLK4_REQ, (M3)} /* gpio_wk7 - Debug led-2 */ | |
| 263 | -}; | |
| 264 | - | |
| 265 | 68 | #endif /* _SDP4430_MUX_DATA_H */ |