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Commit e84a324ba7950e88c0df4a2c656f533c723aeaae

Authored by Ashish Kumar
Committed by York Sun
1 parent 6d9b82d085
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

armv8: ls1088ardb: Add support for LS1088ARDB platform 

LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin
platform that supports the LS1088A family SoCs. This patch add basic
support of the platform.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Disabled NAND in board header file]
Reviewed-by: York Sun <york.sun@nxp.com>

WIP: disable NAND for LS1088ARDB

Showing 17 changed files with 1316 additions and 1 deletions Side-by-side Diff

... ... @@ -909,6 +909,19 @@
909 909 development platform that supports the QorIQ LS1012A
910 910 Layerscape Architecture processor.
911 911  
  912 +config TARGET_LS1088ARDB
  913 + bool "Support ls1088ardb"
  914 + select ARCH_LS1088A
  915 + select ARM64
  916 + select ARMV8_MULTIENTRY
  917 + select ARCH_MISC_INIT
  918 + select BOARD_LATE_INIT
  919 + help
  920 + Support for NXP LS1088ARDB platform.
  921 + The LS1088A Reference design board (RDB) is a high-performance
  922 + development platform that supports the QorIQ LS1088A
  923 + Layerscape Architecture processor.
  924 +
912 925 config TARGET_LS1021AQDS
913 926 bool "Support ls1021aqds"
914 927 select BOARD_LATE_INIT
... ... @@ -1192,6 +1205,7 @@
1192 1205 source "board/freescale/ls2080a/Kconfig"
1193 1206 source "board/freescale/ls2080aqds/Kconfig"
1194 1207 source "board/freescale/ls2080ardb/Kconfig"
  1208 +source "board/freescale/ls1088a/Kconfig"
1195 1209 source "board/freescale/ls1021aqds/Kconfig"
1196 1210 source "board/freescale/ls1043aqds/Kconfig"
1197 1211 source "board/freescale/ls1021atwr/Kconfig"
arch/arm/cpu/armv8/Kconfig
Diff comments   View file @ e84a324
... ... @@ -88,6 +88,7 @@
88 88 depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \
89 89 !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
90 90 !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \
  91 + !TARGET_LS1088ARDB && \
91 92 !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
92 93 !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
93 94 !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
Diff comments   View file @ e84a324
... ... @@ -208,6 +208,7 @@
208 208 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
209 209 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
210 210 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
  211 + default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
211 212 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
212 213 default 0x400000 if SYS_LS_PPA_FW_IN_MMC
213 214 default 0x400000 if SYS_LS_PPA_FW_IN_NAND
arch/arm/dts/Makefile
Diff comments   View file @ e84a324
... ... @@ -187,7 +187,8 @@
187 187 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
188 188 fsl-ls2080a-rdb.dtb \
189 189 fsl-ls2081a-rdb.dtb \
190   - fsl-ls2088a-rdb-qspi.dtb
  190 + fsl-ls2088a-rdb-qspi.dtb \
  191 + fsl-ls1088a-rdb.dtb
191 192 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
192 193 fsl-ls1043a-qds-lpuart.dtb \
193 194 fsl-ls1043a-rdb.dtb \
arch/arm/dts/fsl-ls1088a-rdb.dts
Diff comments   View file @ e84a324
  1 +/*
  2 + * NXP ls1088a RDB board device tree source
  3 + *
  4 + * Copyright 2017 NXP
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +/dts-v1/;
  10 +
  11 +#include "fsl-ls1088a.dtsi"
  12 +
  13 +/ {
  14 + model = "NXP Layerscape 1088a RDB Board";
  15 + compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
  16 + aliases {
  17 + spi0 = &qspi;
  18 + };
  19 +};
  20 +
  21 +&qspi {
  22 + bus-num = <0>;
  23 + status = "okay";
  24 +
  25 + qflash0: s25fs512s@0 {
  26 + #address-cells = <1>;
  27 + #size-cells = <1>;
  28 + compatible = "spi-flash";
  29 + spi-max-frequency = <50000000>;
  30 + reg = <0>;
  31 + };
  32 +
  33 + qflash1: s25fs512s@1 {
  34 + #address-cells = <1>;
  35 + #size-cells = <1>;
  36 + compatible = "spi-flash";
  37 + spi-max-frequency = <50000000>;
  38 + reg = <1>;
  39 + };
  40 +};
board/freescale/ls1088a/Kconfig
Diff comments   View file @ e84a324
  1 +if TARGET_LS1088ARDB
  2 +
  3 +config SYS_BOARD
  4 + default "ls1088a"
  5 +
  6 +config SYS_VENDOR
  7 + default "freescale"
  8 +
  9 +config SYS_SOC
  10 + default "fsl-layerscape"
  11 +
  12 +config SYS_CONFIG_NAME
  13 + default "ls1088ardb"
  14 +
  15 +endif
board/freescale/ls1088a/MAINTAINERS
Diff comments   View file @ e84a324
  1 +LS1088ARDB BOARD
  2 +M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
  3 +M: Ashish Kumar <Ashish.Kumar@nxp.com>
  4 +S: Maintained
  5 +F: board/freescale/ls1088a/
  6 +F: include/configs/ls1088ardb.h
  7 +F: configs/ls1088ardb_qspi_defconfig
board/freescale/ls1088a/Makefile
Diff comments   View file @ e84a324
  1 +#
  2 +# Copyright 2017 NXP
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +obj-y += ls1088a.o
  8 +obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o
  9 +obj-y += ddr.o
board/freescale/ls1088a/README
Diff comments   View file @ e84a324
  1 +Overview
  2 +--------
  3 +The LS1088A Reference Design (RDB) is a high-performance computing,
  4 +evaluation, and development platform that supports ARM SoC LS1088A and its
  5 +derivatives.
  6 +
  7 +
  8 +LS1088A SoC Overview
  9 +--------------------------------------
  10 +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
  11 +
  12 +RDB Default Switch Settings (1: ON; 0: OFF)
  13 +-------------------------------------------
  14 +
  15 +For QSPI Boot
  16 +SW1 0011 0001
  17 +SW2 x100 0000
  18 +SW3 1111 0010
  19 +SW4 1001 0011
  20 +SW5 1111 0000
  21 +
  22 +For SD Boot
  23 +SW1 0010 0000
  24 +SW2 0100 0000
  25 +SW3 1111 0010
  26 +SW4 1001 0011
  27 +SW5 1111 0000
  28 +
  29 +For eMMC Boot
  30 +SW1 0010 0000
  31 +SW2 1100 0000
  32 +SW3 1111 0010
  33 +SW4 1001 0011
  34 +SW5 1111 0000
  35 +
  36 +Alternately you can use this command to switch from QSPI to SD
  37 +
  38 +=> i2c mw 66 0x60 0x20; i2c mw 66 10 10;i2c mw 66 10 21
  39 +
  40 + LS1088ARDB board Overview
  41 + -------------------------
  42 + - SERDES Connections, 16 lanes supporting:
  43 + - PCI Express - 3.0
  44 + - SATA 3.0
  45 + - XFI
  46 + - QSGMII
  47 + - DDR Controller
  48 + - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
  49 + chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default
  50 + with FSL refernce software is 2100MT/s
  51 + - 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB
  52 + - IFC/Local Bus
  53 + - One 2 GB NAND flash with ECC support, not as boot source
  54 + - CPLD of size 2K
  55 + - USB 3.0
  56 + - Two high speed USB 3.0 ports
  57 + - First USB 3.0 port configured as Host with Type-A connector
  58 + - Second USB 3.0 port configured as OTG with micro-AB connector
  59 + - SDHC/eMMC
  60 + - SDHC slot and onboard eMMC are muxed together
  61 + - 4 I2C controllers
  62 + - Two SATA onboard connectors
  63 + - 2 UART
  64 + - JTAG support
  65 + - QSPI emulator support
  66 + - TDM riser support
board/freescale/ls1088a/ddr.c
Diff comments   View file @ e84a324
  1 +/*
  2 + * Copyright 2017 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <fsl_ddr_sdram.h>
  9 +#include <fsl_ddr_dimm_params.h>
  10 +#include <asm/arch/soc.h>
  11 +#include <asm/arch/clock.h>
  12 +#include "ddr.h"
  13 +
  14 +DECLARE_GLOBAL_DATA_PTR;
  15 +
  16 +void fsl_ddr_board_options(memctl_options_t *popts,
  17 + dimm_params_t *pdimm,
  18 + unsigned int ctrl_num)
  19 +{
  20 + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  21 + ulong ddr_freq;
  22 +
  23 + if (ctrl_num > 1) {
  24 + printf("Not supported controller number %d\n", ctrl_num);
  25 + return;
  26 + }
  27 + if (!pdimm->n_ranks)
  28 + return;
  29 +
  30 + /*
  31 + * we use identical timing for all slots. If needed, change the code
  32 + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  33 + */
  34 + pbsp = udimms[0];
  35 +
  36 + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  37 + * freqency and n_banks specified in board_specific_parameters table.
  38 + */
  39 + ddr_freq = get_ddr_freq(0) / 1000000;
  40 + while (pbsp->datarate_mhz_high) {
  41 + if (pbsp->n_ranks == pdimm->n_ranks) {
  42 + if (ddr_freq <= pbsp->datarate_mhz_high) {
  43 + popts->clk_adjust = pbsp->clk_adjust;
  44 + popts->wrlvl_start = pbsp->wrlvl_start;
  45 + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  46 + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  47 + goto found;
  48 + }
  49 + pbsp_highest = pbsp;
  50 + }
  51 + pbsp++;
  52 + }
  53 +
  54 + if (pbsp_highest) {
  55 + printf("Error: board specific timing not found for %lu MT/s\n",
  56 + ddr_freq);
  57 + printf("Trying to use the highest speed (%u) parameters\n",
  58 + pbsp_highest->datarate_mhz_high);
  59 + popts->clk_adjust = pbsp_highest->clk_adjust;
  60 + popts->wrlvl_start = pbsp_highest->wrlvl_start;
  61 + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  62 + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  63 + } else {
  64 + panic("DIMM is not supported by this board");
  65 + }
  66 +found:
  67 + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  68 + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
  69 + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  70 + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  71 + pbsp->wrlvl_ctl_3);
  72 +
  73 +
  74 +
  75 + popts->half_strength_driver_enable = 0;
  76 + /*
  77 + * Write leveling override
  78 + */
  79 + popts->wrlvl_override = 1;
  80 + popts->wrlvl_sample = 0xf;
  81 +
  82 +
  83 + /* Enable ZQ calibration */
  84 + popts->zq_en = 1;
  85 +
  86 + /* Enable DDR hashing */
  87 + popts->addr_hash = 1;
  88 +
  89 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
  90 + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
  91 + DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
  92 +}
  93 +
  94 +
  95 +int fsl_initdram(void)
  96 +{
  97 + puts("Initializing DDR....using SPD\n");
  98 +
  99 + gd->ram_size = fsl_ddr_sdram();
  100 +
  101 + return 0;
  102 +}
board/freescale/ls1088a/ddr.h
Diff comments   View file @ e84a324
  1 +/*
  2 + * Copyright 2017 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __LS1088A_DDR_H__
  8 +#define __LS1088A_DDR_H__
  9 +struct board_specific_parameters {
  10 + u32 n_ranks;
  11 + u32 datarate_mhz_high;
  12 + u32 rank_gb;
  13 + u32 clk_adjust;
  14 + u32 wrlvl_start;
  15 + u32 wrlvl_ctl_2;
  16 + u32 wrlvl_ctl_3;
  17 +};
  18 +
  19 +/*
  20 + * These tables contain all valid speeds we want to override with board
  21 + * specific parameters. datarate_mhz_high values need to be in ascending order
  22 + * for each n_ranks group.
  23 + */
  24 +
  25 +static const struct board_specific_parameters udimm0[] = {
  26 + /*
  27 + * memory controller 0
  28 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
  29 + * ranks| mhz| GB |adjst| start | ctl2 | ctl3
  30 + */
  31 +#if defined(CONFIG_TARGET_LS1088ARDB)
  32 +
  33 + {2, 1666, 0, 8, 8, 0x090A0B0E, 0x0F10110D,},
  34 + {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
  35 + {2, 2300, 0, 8, 9, 0x0A0C0E11, 0x1214160F,},
  36 + {}
  37 +
  38 +#endif
  39 +};
  40 +
  41 +static const struct board_specific_parameters *udimms[] = {
  42 + udimm0,
  43 +};
  44 +#endif
board/freescale/ls1088a/eth_ls1088ardb.c
Diff comments   View file @ e84a324
  1 +/*
  2 + * Copyright 2017 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <command.h>
  9 +#include <netdev.h>
  10 +#include <malloc.h>
  11 +#include <fsl_mdio.h>
  12 +#include <miiphy.h>
  13 +#include <phy.h>
  14 +#include <fm_eth.h>
  15 +#include <asm/io.h>
  16 +#include <exports.h>
  17 +#include <asm/arch/fsl_serdes.h>
  18 +#include <fsl-mc/ldpaa_wriop.h>
  19 +
  20 +DECLARE_GLOBAL_DATA_PTR;
  21 +
  22 +#define MC_BOOT_ENV_VAR "mcinitcmd"
  23 +int board_eth_init(bd_t *bis)
  24 +{
  25 +#if defined(CONFIG_FSL_MC_ENET)
  26 + char *mc_boot_env_var;
  27 + int i, interface;
  28 + struct memac_mdio_info mdio_info;
  29 + struct mii_dev *dev;
  30 + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  31 + struct memac_mdio_controller *reg;
  32 + u32 srds_s1, cfg;
  33 +
  34 + cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
  35 + FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  36 + cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  37 +
  38 + srds_s1 = serdes_get_number(FSL_SRDS_1, cfg);
  39 +
  40 + reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
  41 + mdio_info.regs = reg;
  42 + mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
  43 +
  44 + /* Register the EMI 1 */
  45 + fm_memac_mdio_init(bis, &mdio_info);
  46 +
  47 + reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
  48 + mdio_info.regs = reg;
  49 + mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
  50 +
  51 + /* Register the EMI 2 */
  52 + fm_memac_mdio_init(bis, &mdio_info);
  53 +
  54 + switch (srds_s1) {
  55 + case 0x1D:
  56 + /*
  57 + * XFI does not need a PHY to work, but to avoid U-boot use
  58 + * default PHY address which is zero to a MAC when it found
  59 + * a MAC has no PHY address, we give a PHY address to XFI
  60 + * MAC error.
  61 + */
  62 + wriop_set_phy_address(WRIOP1_DPMAC1, 0x0a);
  63 + wriop_set_phy_address(WRIOP1_DPMAC2, AQ_PHY_ADDR1);
  64 + wriop_set_phy_address(WRIOP1_DPMAC3, QSGMII1_PORT1_PHY_ADDR);
  65 + wriop_set_phy_address(WRIOP1_DPMAC4, QSGMII1_PORT2_PHY_ADDR);
  66 + wriop_set_phy_address(WRIOP1_DPMAC5, QSGMII1_PORT3_PHY_ADDR);
  67 + wriop_set_phy_address(WRIOP1_DPMAC6, QSGMII1_PORT4_PHY_ADDR);
  68 + wriop_set_phy_address(WRIOP1_DPMAC7, QSGMII2_PORT1_PHY_ADDR);
  69 + wriop_set_phy_address(WRIOP1_DPMAC8, QSGMII2_PORT2_PHY_ADDR);
  70 + wriop_set_phy_address(WRIOP1_DPMAC9, QSGMII2_PORT3_PHY_ADDR);
  71 + wriop_set_phy_address(WRIOP1_DPMAC10, QSGMII2_PORT4_PHY_ADDR);
  72 +
  73 + break;
  74 + default:
  75 + printf("SerDes1 protocol 0x%x is not supported on LS1088ARDB\n",
  76 + srds_s1);
  77 + break;
  78 + }
  79 +
  80 + for (i = WRIOP1_DPMAC3; i <= WRIOP1_DPMAC10; i++) {
  81 + interface = wriop_get_enet_if(i);
  82 + switch (interface) {
  83 + case PHY_INTERFACE_MODE_QSGMII:
  84 + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
  85 + wriop_set_mdio(i, dev);
  86 + break;
  87 + default:
  88 + break;
  89 + }
  90 + }
  91 +
  92 + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
  93 + wriop_set_mdio(WRIOP1_DPMAC2, dev);
  94 +
  95 + mc_boot_env_var = env_get(MC_BOOT_ENV_VAR);
  96 + if (mc_boot_env_var)
  97 + run_command_list(mc_boot_env_var, -1, 0);
  98 + cpu_eth_init(bis);
  99 +#endif /* CONFIG_FMAN_ENET */
  100 +
  101 + return pci_eth_init(bis);
  102 +}
board/freescale/ls1088a/ls1088a.c
Diff comments   View file @ e84a324
  1 +/*
  2 + * Copyright 2017 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +#include <common.h>
  7 +#include <i2c.h>
  8 +#include <malloc.h>
  9 +#include <errno.h>
  10 +#include <netdev.h>
  11 +#include <fsl_ifc.h>
  12 +#include <fsl_ddr.h>
  13 +#include <fsl_sec.h>
  14 +#include <asm/io.h>
  15 +#include <fdt_support.h>
  16 +#include <libfdt.h>
  17 +#include <fsl-mc/fsl_mc.h>
  18 +#include <environment.h>
  19 +#include <asm/arch-fsl-layerscape/soc.h>
  20 +#include <asm/arch/ppa.h>
  21 +
  22 +#include "../common/qixis.h"
  23 +#include "ls1088a_qixis.h"
  24 +
  25 +DECLARE_GLOBAL_DATA_PTR;
  26 +
  27 +unsigned long long get_qixis_addr(void)
  28 +{
  29 + unsigned long long addr;
  30 +
  31 + if (gd->flags & GD_FLG_RELOC)
  32 + addr = QIXIS_BASE_PHYS;
  33 + else
  34 + addr = QIXIS_BASE_PHYS_EARLY;
  35 +
  36 + /*
  37 + * IFC address under 256MB is mapped to 0x30000000, any address above
  38 + * is mapped to 0x5_10000000 up to 4GB.
  39 + */
  40 + addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  41 +
  42 + return addr;
  43 +}
  44 +
  45 +int checkboard(void)
  46 +{
  47 + char buf[64];
  48 + u8 sw;
  49 + static const char *const freq[] = {"100", "125", "156.25",
  50 + "100 separate SSCG"};
  51 + int clock;
  52 +
  53 +
  54 + printf("Board: LS1088A-RDB, ");
  55 +
  56 + sw = QIXIS_READ(arch);
  57 + printf("Board Arch: V%d, ", sw >> 4);
  58 +
  59 + printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
  60 +
  61 +
  62 + memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
  63 +
  64 + sw = QIXIS_READ(brdcfg[0]);
  65 + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  66 +
  67 +#ifdef CONFIG_SD_BOOT
  68 + puts("SD card\n");
  69 +#endif
  70 + switch (sw) {
  71 + case 0:
  72 +
  73 + puts("QSPI:");
  74 + sw = QIXIS_READ(brdcfg[0]);
  75 + sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
  76 + if (sw == 0 || sw == 4)
  77 + puts("0\n");
  78 + else if (sw == 1)
  79 + puts("1\n");
  80 + else
  81 + puts("EMU\n");
  82 + break;
  83 +
  84 + default:
  85 + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  86 + break;
  87 + }
  88 +
  89 +
  90 + printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
  91 +
  92 +
  93 + /*
  94 + * Display the actual SERDES reference clocks as configured by the
  95 + * dip switches on the board. Note that the SWx registers could
  96 + * technically be set to force the reference clocks to match the
  97 + * values that the SERDES expects (or vice versa). For now, however,
  98 + * we just display both values and hope the user notices when they
  99 + * don't match.
  100 + */
  101 + puts("SERDES1 Reference : ");
  102 + sw = QIXIS_READ(brdcfg[2]);
  103 + clock = (sw >> 6) & 3;
  104 + printf("Clock1 = %sMHz ", freq[clock]);
  105 + clock = (sw >> 4) & 3;
  106 + printf("Clock2 = %sMHz", freq[clock]);
  107 +
  108 + puts("\nSERDES2 Reference : ");
  109 + clock = (sw >> 2) & 3;
  110 + printf("Clock1 = %sMHz ", freq[clock]);
  111 + clock = (sw >> 0) & 3;
  112 + printf("Clock2 = %sMHz\n", freq[clock]);
  113 +
  114 + return 0;
  115 +}
  116 +
  117 +bool if_board_diff_clk(void)
  118 +{
  119 + u8 diff_conf = QIXIS_READ(dutcfg[11]);
  120 + return diff_conf & 0x80;
  121 +}
  122 +
  123 +unsigned long get_board_sys_clk(void)
  124 +{
  125 + u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  126 +
  127 + switch (sysclk_conf & 0x0f) {
  128 + case QIXIS_SYSCLK_83:
  129 + return 83333333;
  130 + case QIXIS_SYSCLK_100:
  131 + return 100000000;
  132 + case QIXIS_SYSCLK_125:
  133 + return 125000000;
  134 + case QIXIS_SYSCLK_133:
  135 + return 133333333;
  136 + case QIXIS_SYSCLK_150:
  137 + return 150000000;
  138 + case QIXIS_SYSCLK_160:
  139 + return 160000000;
  140 + case QIXIS_SYSCLK_166:
  141 + return 166666666;
  142 + }
  143 +
  144 + return 66666666;
  145 +}
  146 +
  147 +unsigned long get_board_ddr_clk(void)
  148 +{
  149 + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  150 +
  151 + if (if_board_diff_clk())
  152 + return get_board_sys_clk();
  153 + switch ((ddrclk_conf & 0x30) >> 4) {
  154 + case QIXIS_DDRCLK_100:
  155 + return 100000000;
  156 + case QIXIS_DDRCLK_125:
  157 + return 125000000;
  158 + case QIXIS_DDRCLK_133:
  159 + return 133333333;
  160 + }
  161 +
  162 + return 66666666;
  163 +}
  164 +
  165 +int select_i2c_ch_pca9547(u8 ch)
  166 +{
  167 + int ret;
  168 +
  169 + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  170 + if (ret) {
  171 + puts("PCA: failed to select proper channel\n");
  172 + return ret;
  173 + }
  174 +
  175 + return 0;
  176 +}
  177 +
  178 +void board_retimer_init(void)
  179 +{
  180 + u8 reg;
  181 +
  182 + /* Retimer is connected to I2C1_CH5 */
  183 + select_i2c_ch_pca9547(I2C_MUX_CH5);
  184 +
  185 + /* Access to Control/Shared register */
  186 + reg = 0x0;
  187 + i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  188 +
  189 + /* Read device revision and ID */
  190 + i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
  191 + debug("Retimer version id = 0x%x\n", reg);
  192 +
  193 + /* Enable Broadcast. All writes target all channel register sets */
  194 + reg = 0x0c;
  195 + i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  196 +
  197 + /* Reset Channel Registers */
  198 + i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  199 + reg |= 0x4;
  200 + i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  201 +
  202 + /* Set data rate as 10.3125 Gbps */
  203 + reg = 0x90;
  204 + i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
  205 + reg = 0xb3;
  206 + i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
  207 + reg = 0x90;
  208 + i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
  209 + reg = 0xb3;
  210 + i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
  211 + reg = 0xcd;
  212 + i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
  213 +
  214 + /* Select VCO Divider to full rate (000) */
  215 + i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
  216 + reg &= 0x0f;
  217 + reg |= 0x70;
  218 + i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
  219 +
  220 +
  221 + /*return the default channel*/
  222 + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  223 +}
  224 +
  225 +int board_init(void)
  226 +{
  227 + init_final_memctl_regs();
  228 +#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
  229 + u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
  230 +#endif
  231 +
  232 + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  233 + board_retimer_init();
  234 +
  235 +#ifdef CONFIG_ENV_IS_NOWHERE
  236 + gd->env_addr = (ulong)&default_environment[0];
  237 +#endif
  238 +
  239 +#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
  240 + /* invert AQR105 IRQ pins polarity */
  241 + out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
  242 +#endif
  243 +
  244 +#ifdef CONFIG_FSL_LS_PPA
  245 + ppa_init();
  246 +#endif
  247 + return 0;
  248 +}
  249 +
  250 +int board_early_init_f(void)
  251 +{
  252 + fsl_lsch3_early_init_f();
  253 + return 0;
  254 +}
  255 +
  256 +void detail_board_ddr_info(void)
  257 +{
  258 + puts("\nDDR ");
  259 + print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
  260 + print_ddr_info(0);
  261 +}
  262 +
  263 +#if defined(CONFIG_ARCH_MISC_INIT)
  264 +int arch_misc_init(void)
  265 +{
  266 +#ifdef CONFIG_FSL_CAAM
  267 + sec_init();
  268 +#endif
  269 + return 0;
  270 +}
  271 +#endif
  272 +
  273 +#ifdef CONFIG_FSL_MC_ENET
  274 +void fdt_fixup_board_enet(void *fdt)
  275 +{
  276 + int offset;
  277 +
  278 + offset = fdt_path_offset(fdt, "/fsl-mc");
  279 +
  280 + if (offset < 0)
  281 + offset = fdt_path_offset(fdt, "/fsl,dprc@0");
  282 +
  283 + if (offset < 0) {
  284 + printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
  285 + __func__, offset);
  286 + return;
  287 + }
  288 +
  289 + if (get_mc_boot_status() == 0)
  290 + fdt_status_okay(fdt, offset);
  291 + else
  292 + fdt_status_fail(fdt, offset);
  293 +}
  294 +#endif
  295 +
  296 +#ifdef CONFIG_OF_BOARD_SETUP
  297 +int ft_board_setup(void *blob, bd_t *bd)
  298 +{
  299 + int err, i;
  300 + u64 base[CONFIG_NR_DRAM_BANKS];
  301 + u64 size[CONFIG_NR_DRAM_BANKS];
  302 +
  303 + ft_cpu_setup(blob, bd);
  304 +
  305 + /* fixup DT for the two GPP DDR banks */
  306 + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  307 + base[i] = gd->bd->bi_dram[i].start;
  308 + size[i] = gd->bd->bi_dram[i].size;
  309 + }
  310 +
  311 +#ifdef CONFIG_RESV_RAM
  312 + /* reduce size if reserved memory is within this bank */
  313 + if (gd->arch.resv_ram >= base[0] &&
  314 + gd->arch.resv_ram < base[0] + size[0])
  315 + size[0] = gd->arch.resv_ram - base[0];
  316 + else if (gd->arch.resv_ram >= base[1] &&
  317 + gd->arch.resv_ram < base[1] + size[1])
  318 + size[1] = gd->arch.resv_ram - base[1];
  319 +#endif
  320 +
  321 + fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
  322 +
  323 +#ifdef CONFIG_FSL_MC_ENET
  324 + fdt_fixup_board_enet(blob);
  325 + err = fsl_mc_ldpaa_exit(bd);
  326 + if (err)
  327 + return err;
  328 +#endif
  329 +
  330 + return 0;
  331 +}
  332 +#endif
board/freescale/ls1088a/ls1088a_qixis.h
Diff comments   View file @ e84a324
  1 +/*
  2 + * Copyright 2017 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __LS1088AQDS_QIXIS_H__
  8 +#define __LS1088AQDS_QIXIS_H__
  9 +
  10 +/* Definitions of QIXIS Registers for LS1088AQDS */
  11 +
  12 +/* SYSCLK */
  13 +#define QIXIS_SYSCLK_66 0x0
  14 +#define QIXIS_SYSCLK_83 0x1
  15 +#define QIXIS_SYSCLK_100 0x2
  16 +#define QIXIS_SYSCLK_125 0x3
  17 +#define QIXIS_SYSCLK_133 0x4
  18 +#define QIXIS_SYSCLK_150 0x5
  19 +#define QIXIS_SYSCLK_160 0x6
  20 +#define QIXIS_SYSCLK_166 0x7
  21 +
  22 +/* DDRCLK */
  23 +#define QIXIS_DDRCLK_66 0x0
  24 +#define QIXIS_DDRCLK_100 0x1
  25 +#define QIXIS_DDRCLK_125 0x2
  26 +#define QIXIS_DDRCLK_133 0x3
  27 +
  28 +/* BRDCFG2 - SD clock*/
  29 +#define QIXIS_SDCLK1_100 0x0
  30 +#define QIXIS_SDCLK1_125 0x1
  31 +#define QIXIS_SDCLK1_165 0x2
  32 +#define QIXIS_SDCLK1_100_SP 0x3
  33 +
  34 +#endif
configs/ls1088ardb_qspi_defconfig
Diff comments   View file @ e84a324
  1 +CONFIG_ARM=y
  2 +CONFIG_TARGET_LS1088ARDB=y
  3 +# CONFIG_SYS_MALLOC_F is not set
  4 +CONFIG_DM_SPI=y
  5 +CONFIG_DM_SPI_FLASH=y
  6 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
  7 +CONFIG_FIT=y
  8 +CONFIG_FIT_VERBOSE=y
  9 +CONFIG_OF_BOARD_SETUP=y
  10 +CONFIG_OF_STDOUT_VIA_ALIAS=y
  11 +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
  12 +CONFIG_HUSH_PARSER=y
  13 +CONFIG_CMD_MMC=y
  14 +CONFIG_CMD_SF=y
  15 +CONFIG_CMD_I2C=y
  16 +# CONFIG_CMD_SETEXPR is not set
  17 +CONFIG_CMD_DHCP=y
  18 +CONFIG_CMD_PING=y
  19 +CONFIG_OF_CONTROL=y
  20 +CONFIG_NET_RANDOM_ETHADDR=y
  21 +CONFIG_DM=y
  22 +CONFIG_SPI_FLASH=y
  23 +CONFIG_NETDEVICES=y
  24 +CONFIG_E1000=y
  25 +CONFIG_SYS_NS16550=y
  26 +CONFIG_FSL_DSPI=y
  27 +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
  28 +# CONFIG_DISPLAY_BOARDINFO is not set
  29 +CONFIG_FSL_LS_PPA=y
include/configs/ls1088a_common.h
Diff comments   View file @ e84a324
  1 +/*
  2 + * Copyright 2017 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __LS1088_COMMON_H
  8 +#define __LS1088_COMMON_H
  9 +
  10 +
  11 +#define CONFIG_REMAKE_ELF
  12 +#define CONFIG_FSL_LAYERSCAPE
  13 +#define CONFIG_MP
  14 +
  15 +#include <asm/arch/stream_id_lsch3.h>
  16 +#include <asm/arch/config.h>
  17 +#include <asm/arch/soc.h>
  18 +
  19 +/* Link Definitions */
  20 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  21 +
  22 +/* Link Definitions */
  23 +#ifdef CONFIG_QSPI_BOOT
  24 +#define CONFIG_SYS_TEXT_BASE 0x20100000
  25 +#else
  26 +#define CONFIG_SYS_TEXT_BASE 0x30100000
  27 +#endif
  28 +
  29 +#define CONFIG_SUPPORT_RAW_INITRD
  30 +
  31 +
  32 +#define CONFIG_SKIP_LOWLEVEL_INIT
  33 +
  34 +#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
  35 +
  36 +#define CONFIG_VERY_BIG_RAM
  37 +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  38 +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
  39 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  40 +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
  41 +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
  42 +/*
  43 + * SMP Definitinos
  44 + */
  45 +#define CPU_RELEASE_ADDR secondary_boot_func
  46 +
  47 +/* Size of malloc() pool */
  48 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
  49 +
  50 +/* I2C */
  51 +#define CONFIG_SYS_I2C
  52 +#define CONFIG_SYS_I2C_MXC
  53 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  54 +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  55 +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
  56 +#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
  57 +
  58 +/* Serial Port */
  59 +#define CONFIG_CONS_INDEX 1
  60 +#define CONFIG_SYS_NS16550_SERIAL
  61 +#define CONFIG_SYS_NS16550_REG_SIZE 1
  62 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
  63 +
  64 +#define CONFIG_BAUDRATE 115200
  65 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  66 +
  67 +/* IFC */
  68 +#define CONFIG_FSL_IFC
  69 +
  70 +/*
  71 + * During booting, IFC is mapped at the region of 0x30000000.
  72 + * But this region is limited to 256MB. To accommodate NOR, promjet
  73 + * and FPGA. This region is divided as below:
  74 + * 0x30000000 - 0x37ffffff : 128MB : NOR flash
  75 + * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
  76 + * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
  77 + *
  78 + * To accommodate bigger NOR flash and other devices, we will map IFC
  79 + * chip selects to as below:
  80 + * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
  81 + * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
  82 + * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
  83 + * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
  84 + * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
  85 + *
  86 + * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
  87 + * CONFIG_SYS_FLASH_BASE has the final address (core view)
  88 + * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  89 + * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  90 + * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
  91 + */
  92 +
  93 +#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
  94 +#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
  95 +#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
  96 +
  97 +#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
  98 +#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
  99 +
  100 +#ifndef __ASSEMBLY__
  101 +unsigned long long get_qixis_addr(void);
  102 +#endif
  103 +
  104 +#define QIXIS_BASE get_qixis_addr()
  105 +#define QIXIS_BASE_PHYS 0x20000000
  106 +#define QIXIS_BASE_PHYS_EARLY 0xC000000
  107 +
  108 +
  109 +#define CONFIG_SYS_NAND_BASE 0x530000000ULL
  110 +#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
  111 +
  112 +
  113 +/* MC firmware */
  114 +/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
  115 +#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
  116 +#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
  117 +#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
  118 +#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
  119 +#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
  120 +#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
  121 +/*
  122 + * Carve out a DDR region which will not be used by u-boot/Linux
  123 + *
  124 + * It will be used by MC and Debug Server. The MC region must be
  125 + * 512MB aligned, so the min size to hide is 512MB.
  126 + */
  127 +
  128 +#if defined(CONFIG_FSL_MC_ENET)
  129 +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
  130 +#endif
  131 +
  132 +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
  133 +
  134 +/* Command line configuration */
  135 +#define CONFIG_CMD_GREPENV
  136 +#define CONFIG_CMD_CACHE
  137 +
  138 +/* Miscellaneous configurable options */
  139 +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
  140 +
  141 +/* Physical Memory Map */
  142 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4
  143 +
  144 +#define CONFIG_NR_DRAM_BANKS 2
  145 +
  146 +#define CONFIG_HWCONFIG
  147 +#define HWCONFIG_BUFFER_SIZE 128
  148 +
  149 +/* #define CONFIG_DISPLAY_CPUINFO */
  150 +
  151 +/* Allow to overwrite serial and ethaddr */
  152 +#define CONFIG_ENV_OVERWRITE
  153 +
  154 +/* Initial environment variables */
  155 +#define CONFIG_EXTRA_ENV_SETTINGS \
  156 + "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  157 + "loadaddr=0x80100000\0" \
  158 + "kernel_addr=0x100000\0" \
  159 + "ramdisk_addr=0x800000\0" \
  160 + "ramdisk_size=0x2000000\0" \
  161 + "fdt_high=0xa0000000\0" \
  162 + "initrd_high=0xffffffffffffffff\0" \
  163 + "kernel_start=0x581000000\0" \
  164 + "kernel_load=0xa0000000\0" \
  165 + "kernel_size=0x2800000\0" \
  166 + "console=ttyAMA0,38400n8\0" \
  167 + "mcinitcmd=fsl_mc start mc 0x580a00000" \
  168 + " 0x580e00000 \0"
  169 +
  170 +#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
  171 + "earlycon=uart8250,mmio,0x21c0500 " \
  172 + "ramdisk_size=0x3000000 default_hugepagesz=2m" \
  173 + " hugepagesz=2m hugepages=256"
  174 +#if defined(CONFIG_QSPI_BOOT)
  175 +#define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
  176 + "sf read 0x80200000 0xd00000 0x100000;"\
  177 + " fsl_mc apply dpl 0x80200000 &&" \
  178 + " sf read $kernel_load $kernel_start" \
  179 + " $kernel_size && bootm $kernel_load"
  180 +#else /* NOR BOOT*/
  181 +#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
  182 + " cp.b $kernel_start $kernel_load" \
  183 + " $kernel_size && bootm $kernel_load"
  184 +#endif
  185 +
  186 +/* Monitor Command Prompt */
  187 +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  188 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  189 + sizeof(CONFIG_SYS_PROMPT) + 16)
  190 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  191 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
  192 +#define CONFIG_SYS_LONGHELP
  193 +#define CONFIG_CMDLINE_EDITING 1
  194 +#define CONFIG_AUTO_COMPLETE
  195 +#define CONFIG_SYS_MAXARGS 64 /* max command args */
  196 +
  197 +#define CONFIG_PANIC_HANG /* do not reset board on panic */
  198 +
  199 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  200 +
  201 +#endif /* __LS1088_COMMON_H */
include/configs/ls1088ardb.h
Diff comments   View file @ e84a324
  1 +/*
  2 + * Copyright 2017 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __LS1088A_RDB_H
  8 +#define __LS1088A_RDB_H
  9 +
  10 +#include "ls1088a_common.h"
  11 +
  12 +#define CONFIG_DISPLAY_BOARDINFO_LATE
  13 +
  14 +#if defined(CONFIG_QSPI_BOOT)
  15 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  16 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  17 +#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
  18 +#define CONFIG_ENV_SECT_SIZE 0x40000
  19 +#else
  20 +#define CONFIG_ENV_IS_IN_FLASH
  21 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
  22 +#define CONFIG_ENV_SECT_SIZE 0x20000
  23 +#define CONFIG_ENV_SIZE 0x20000
  24 +#endif
  25 +
  26 +#if defined(CONFIG_QSPI_BOOT)
  27 +#define CONFIG_QIXIS_I2C_ACCESS
  28 +#define SYS_NO_FLASH
  29 +#undef CONFIG_CMD_IMLS
  30 +#endif
  31 +
  32 +#define CONFIG_SYS_CLK_FREQ 100000000
  33 +#define CONFIG_DDR_CLK_FREQ 100000000
  34 +#define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
  35 +#define COUNTER_FREQUENCY 25000000 /* 25MHz */
  36 +
  37 +#define CONFIG_DDR_SPD
  38 +#ifdef CONFIG_EMU
  39 +#define CONFIG_SYS_FSL_DDR_EMU
  40 +#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
  41 +#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
  42 +#else
  43 +#define CONFIG_DDR_ECC
  44 +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  45 +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  46 +#endif
  47 +#define SPD_EEPROM_ADDRESS 0x51
  48 +#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
  49 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1
  50 +
  51 +
  52 +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  53 +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  54 +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
  55 +#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
  56 +
  57 +#define CONFIG_SYS_NOR0_CSPR \
  58 + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  59 + CSPR_PORT_SIZE_16 | \
  60 + CSPR_MSEL_NOR | \
  61 + CSPR_V)
  62 +#define CONFIG_SYS_NOR0_CSPR_EARLY \
  63 + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
  64 + CSPR_PORT_SIZE_16 | \
  65 + CSPR_MSEL_NOR | \
  66 + CSPR_V)
  67 +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
  68 +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
  69 + FTIM0_NOR_TEADC(0x1) | \
  70 + FTIM0_NOR_TEAHC(0x1))
  71 +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
  72 + FTIM1_NOR_TRAD_NOR(0x1))
  73 +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
  74 + FTIM2_NOR_TCH(0x0) | \
  75 + FTIM2_NOR_TWP(0x1))
  76 +#define CONFIG_SYS_NOR_FTIM3 0x04000000
  77 +#define CONFIG_SYS_IFC_CCR 0x01000000
  78 +
  79 +#ifndef SYS_NO_FLASH
  80 +#define CONFIG_FLASH_CFI_DRIVER
  81 +#define CONFIG_SYS_FLASH_CFI
  82 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  83 +#define CONFIG_SYS_FLASH_QUIET_TEST
  84 +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  85 +
  86 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  87 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  88 +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  89 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  90 +
  91 +#define CONFIG_SYS_FLASH_EMPTY_INFO
  92 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  93 +#endif
  94 +#endif
  95 +#define CONFIG_SYS_NAND_MAX_ECCPOS 256
  96 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2
  97 +
  98 +#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  99 +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  100 + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  101 + | CSPR_MSEL_NAND /* MSEL = NAND */ \
  102 + | CSPR_V)
  103 +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
  104 +
  105 +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  106 + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  107 + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  108 + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  109 + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  110 + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  111 + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  112 +
  113 +#define CONFIG_SYS_NAND_ONFI_DETECTION
  114 +
  115 +/* ONFI NAND Flash mode0 Timing Params */
  116 +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  117 + FTIM0_NAND_TWP(0x18) | \
  118 + FTIM0_NAND_TWCHT(0x07) | \
  119 + FTIM0_NAND_TWH(0x0a))
  120 +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  121 + FTIM1_NAND_TWBE(0x39) | \
  122 + FTIM1_NAND_TRR(0x0e) | \
  123 + FTIM1_NAND_TRP(0x18))
  124 +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  125 + FTIM2_NAND_TREH(0x0a) | \
  126 + FTIM2_NAND_TWHRE(0x1e))
  127 +#define CONFIG_SYS_NAND_FTIM3 0x0
  128 +
  129 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  130 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  131 +#define CONFIG_MTD_NAND_VERIFY_WRITE
  132 +
  133 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  134 +
  135 +#define CONFIG_FSL_QIXIS
  136 +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  137 +#define QIXIS_LBMAP_SWITCH 2
  138 +#define QIXIS_QMAP_MASK 0xe0
  139 +#define QIXIS_QMAP_SHIFT 5
  140 +#define QIXIS_LBMAP_MASK 0x1f
  141 +#define QIXIS_LBMAP_SHIFT 5
  142 +#define QIXIS_LBMAP_DFLTBANK 0x00
  143 +#define QIXIS_LBMAP_ALTBANK 0x20
  144 +#define QIXIS_LBMAP_SD 0x00
  145 +#define QIXIS_LBMAP_SD_QSPI 0x00
  146 +#define QIXIS_LBMAP_QSPI 0x00
  147 +#define QIXIS_RCW_SRC_SD 0x40
  148 +#define QIXIS_RCW_SRC_QSPI 0x62
  149 +#define QIXIS_RST_CTL_RESET 0x31
  150 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  151 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  152 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  153 +#define QIXIS_RST_FORCE_MEM 0x01
  154 +
  155 +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
  156 +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
  157 + | CSPR_PORT_SIZE_8 \
  158 + | CSPR_MSEL_GPCM \
  159 + | CSPR_V)
  160 +#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  161 + | CSPR_PORT_SIZE_8 \
  162 + | CSPR_MSEL_GPCM \
  163 + | CSPR_V)
  164 +
  165 +#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
  166 +#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
  167 +/* QIXIS Timing parameters*/
  168 +#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  169 + FTIM0_GPCM_TEADC(0x0e) | \
  170 + FTIM0_GPCM_TEAHC(0x0e))
  171 +#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  172 + FTIM1_GPCM_TRAD(0x3f))
  173 +#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
  174 + FTIM2_GPCM_TCH(0xf) | \
  175 + FTIM2_GPCM_TWP(0x3E))
  176 +#define SYS_FPGA_CS_FTIM3 0x0
  177 +
  178 +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  179 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  180 +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  181 +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  182 +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  183 +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  184 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  185 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  186 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  187 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
  188 +#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
  189 +#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
  190 +#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
  191 +#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
  192 +#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
  193 +#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
  194 +#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
  195 +#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
  196 +#else
  197 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  198 +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
  199 +#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
  200 +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  201 +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  202 +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  203 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  204 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  205 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  206 +#endif
  207 +
  208 +
  209 +#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
  210 +
  211 +/*
  212 + * I2C bus multiplexer
  213 + */
  214 +#define I2C_MUX_PCA_ADDR_PRI 0x77
  215 +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
  216 +#define I2C_RETIMER_ADDR 0x18
  217 +#define I2C_MUX_CH_DEFAULT 0x8
  218 +#define I2C_MUX_CH5 0xD
  219 +/*
  220 +* RTC configuration
  221 +*/
  222 +#define RTC
  223 +#define CONFIG_RTC_PCF8563 1
  224 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
  225 +#define CONFIG_CMD_DATE
  226 +
  227 +/* EEPROM */
  228 +#define CONFIG_ID_EEPROM
  229 +#define CONFIG_SYS_I2C_EEPROM_NXID
  230 +#define CONFIG_SYS_EEPROM_BUS_NUM 0
  231 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  232 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  233 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  234 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  235 +
  236 +/* QSPI device */
  237 +#if defined(CONFIG_QSPI_BOOT)
  238 +#define CONFIG_FSL_QSPI
  239 +#define CONFIG_SPI_FLASH_SPANSION
  240 +#define FSL_QSPI_FLASH_SIZE (1 << 26)
  241 +#define FSL_QSPI_FLASH_NUM 2
  242 +#endif
  243 +
  244 +#define CONFIG_CMD_MEMINFO
  245 +#define CONFIG_CMD_MEMTEST
  246 +#define CONFIG_SYS_MEMTEST_START 0x80000000
  247 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff
  248 +
  249 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  250 +
  251 +#define CONFIG_FSL_MEMAC
  252 +
  253 +/* Initial environment variables */
  254 +#if defined(CONFIG_QSPI_BOOT)
  255 +#undef CONFIG_EXTRA_ENV_SETTINGS
  256 +#define CONFIG_EXTRA_ENV_SETTINGS \
  257 + "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  258 + "loadaddr=0x90100000\0" \
  259 + "kernel_addr=0x100000\0" \
  260 + "ramdisk_addr=0x800000\0" \
  261 + "ramdisk_size=0x2000000\0" \
  262 + "fdt_high=0xa0000000\0" \
  263 + "initrd_high=0xffffffffffffffff\0" \
  264 + "kernel_start=0x1000000\0" \
  265 + "kernel_load=0xa0000000\0" \
  266 + "kernel_size=0x2800000\0" \
  267 + "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
  268 + "sf read 0x80100000 0xE00000 0x100000;" \
  269 + "fsl_mc start mc 0x80000000 0x80100000\0" \
  270 + "mcmemsize=0x70000000 \0"
  271 +
  272 +#endif
  273 +
  274 +/* MAC/PHY configuration */
  275 +#ifdef CONFIG_FSL_MC_ENET
  276 +#define CONFIG_PHYLIB_10G
  277 +#define CONFIG_PHY_GIGE
  278 +#define CONFIG_PHYLIB
  279 +
  280 +#define CONFIG_PHY_VITESSE
  281 +#define CONFIG_PHY_AQUANTIA
  282 +#define AQ_PHY_ADDR1 0x00
  283 +#define AQR105_IRQ_MASK 0x00000004
  284 +
  285 +#define QSGMII1_PORT1_PHY_ADDR 0x0c
  286 +#define QSGMII1_PORT2_PHY_ADDR 0x0d
  287 +#define QSGMII1_PORT3_PHY_ADDR 0x0e
  288 +#define QSGMII1_PORT4_PHY_ADDR 0x0f
  289 +#define QSGMII2_PORT1_PHY_ADDR 0x1c
  290 +#define QSGMII2_PORT2_PHY_ADDR 0x1d
  291 +#define QSGMII2_PORT3_PHY_ADDR 0x1e
  292 +#define QSGMII2_PORT4_PHY_ADDR 0x1f
  293 +
  294 +#define CONFIG_MII
  295 +#define CONFIG_ETHPRIME "DPMAC1@xgmii"
  296 +#define CONFIG_PHY_GIGE
  297 +#endif
  298 +
  299 +/* MMC */
  300 +#ifdef CONFIG_MMC
  301 +#define CONFIG_FSL_ESDHC
  302 +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  303 +#endif
  304 +
  305 +#undef CONFIG_CMDLINE_EDITING
  306 +#include <config_distro_defaults.h>
  307 +
  308 +#define BOOT_TARGET_DEVICES(func) \
  309 + func(USB, usb, 0) \
  310 + func(MMC, mmc, 0) \
  311 + func(SCSI, scsi, 0) \
  312 + func(DHCP, dhcp, na)
  313 +#include <config_distro_bootcmd.h>
  314 +
  315 +#include <asm/fsl_secure_boot.h>
  316 +
  317 +#endif /* __LS1088A_RDB_H */