Eric Lee / smarc-uboot

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Commit e85390dc1d9c3c942c11bbf003e6c10a73e25ed6

Authored by wdenk
1 parent a6b6b68640
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Initial revision

Showing 14 changed files with 1553 additions and 0 deletions Side-by-side Diff

board/esd/adciop/Makefile
Diff comments   View file @ e85390d
  1 +#
  2 +# (C) Copyright 2000
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = lib$(BOARD).a
  27 +
  28 +OBJS = $(BOARD).o flash.o ../common/pci.o
  29 +
  30 +$(LIB): $(OBJS)
  31 + $(AR) crv $@ $^
  32 +
  33 +clean:
  34 + rm -f $(SOBJS) $(OBJS)
  35 +
  36 +distclean: clean
  37 + rm -f $(LIB) core *.bak .depend
  38 +
  39 +#########################################################################
  40 +
  41 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
  42 + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
  43 +
  44 +sinclude .depend
  45 +
  46 +#########################################################################
board/esd/dasa_sim/Makefile
Diff comments   View file @ e85390d
  1 +#
  2 +# (C) Copyright 2000
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = lib$(BOARD).a
  27 +
  28 +OBJS = $(BOARD).o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o
  29 +
  30 +$(LIB): $(OBJS)
  31 + $(AR) crv $@ $^
  32 +
  33 +clean:
  34 + rm -f $(SOBJS) $(OBJS)
  35 +
  36 +distclean: clean
  37 + rm -f $(LIB) core *.bak .depend
  38 +
  39 +#########################################################################
  40 +
  41 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
  42 + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
  43 +
  44 +sinclude .depend
  45 +
  46 +#########################################################################
board/evb64260/Makefile
Diff comments   View file @ e85390d
  1 +#
  2 +# (C) Copyright 2001
  3 +# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = lib$(BOARD).a
  27 +
  28 +SOBJS = misc.o
  29 +OBJS = $(BOARD).o flash.o serial.o memory.o pci.o \
  30 + eth.o eth_addrtbl.o mpsc.o i2c.o \
  31 + sdram_init.o zuma_pbb.o intel_flash.o zuma_pbb_mbox.o
  32 +
  33 +
  34 +$(LIB): .depend $(OBJS) $(SOBJS)
  35 + $(AR) crv $@ $^
  36 +
  37 +#########################################################################
  38 +
  39 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
  40 + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
  41 +
  42 +sinclude .depend
  43 +
  44 +#########################################################################
board/mousse/Makefile
Diff comments   View file @ e85390d
  1 +#
  2 +# (C) Copyright 2001
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = lib$(BOARD).a
  27 +
  28 +OBJS = $(BOARD).o m48t59y.o pci.o flash.o
  29 +
  30 +$(LIB): .depend $(OBJS)
  31 + $(AR) crv $@ $^
  32 +
  33 +#########################################################################
  34 +
  35 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
  36 + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
  37 +
  38 +sinclude .depend
  39 +
  40 +#########################################################################
board/musenki/Makefile
Diff comments   View file @ e85390d
  1 +#
  2 +# (C) Copyright 2001
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = lib$(BOARD).a
  27 +
  28 +OBJS = $(BOARD).o flash.o
  29 +SOBJS =
  30 +
  31 +$(LIB): .depend $(OBJS) $(SOBJS)
  32 + $(AR) crv $@ $^
  33 +
  34 +#########################################################################
  35 +
  36 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
  37 + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
  38 +
  39 +sinclude .depend
  40 +
  41 +#########################################################################
board/pcippc2/Makefile
Diff comments   View file @ e85390d
  1 +#
  2 +# (C) Copyright 2002
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = lib$(BOARD).a
  27 +
  28 +COBJS = $(BOARD).o cpc710_pci.o flash.o sconsole.o \
  29 + fpga_serial.o pcippc2_fpga.o cpc710_init_ram.o i2c.o
  30 +
  31 +AOBJS =
  32 +
  33 +OBJS = $(COBJS) $(AOBJS)
  34 +
  35 +$(LIB): .depend $(OBJS)
  36 + $(AR) crv $@ $^
  37 +
  38 +#########################################################################
  39 +
  40 +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
  41 + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
  42 +
  43 +sinclude .depend
  44 +
  45 +#########################################################################
board/pcippc2/cpc710_pci.h
Diff comments   View file @ e85390d
  1 +/*
  2 + * (C) Copyright 2002
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#ifndef _CPC710_PCI_H_
  25 +#define _CPC710_PCI_H_
  26 +
  27 +#define PCI_MEMORY_PHYS 0x00000000
  28 +#define PCI_MEMORY_BUS 0x80000000
  29 +#define PCI_MEMORY_MAXSIZE 0x20000000
  30 +
  31 +#define BRIDGE_CPCI_PHYS 0xff500000
  32 +#define BRIDGE_CPCI_MEM_SIZE 0x08000000
  33 +#define BRIDGE_CPCI_MEM_PHYS 0xf0000000
  34 +#define BRIDGE_CPCI_MEM_BUS 0x00000000
  35 +#define BRIDGE_CPCI_IO_SIZE 0x02000000
  36 +#define BRIDGE_CPCI_IO_PHYS 0xfc000000
  37 +#define BRIDGE_CPCI_IO_BUS 0x00000000
  38 +
  39 +#define BRIDGE_LOCAL_PHYS 0xff400000
  40 +#define BRIDGE_LOCAL_MEM_SIZE 0x04000000
  41 +#define BRIDGE_LOCAL_MEM_PHYS 0xf8000000
  42 +#define BRIDGE_LOCAL_MEM_BUS 0x40000000
  43 +#define BRIDGE_LOCAL_IO_SIZE 0x01000000
  44 +#define BRIDGE_LOCAL_IO_PHYS 0xfe000000
  45 +#define BRIDGE_LOCAL_IO_BUS 0x04000000
  46 +
  47 +#define BRIDGE(r, x) (BRIDGE_##r##_PHYS + HW_BRIDGE_##x)
  48 +
  49 +#define PCI_LATENCY_TIMER_VAL 0xff
  50 +
  51 +#endif
board/sandpoint/Makefile
Diff comments   View file @ e85390d
  1 +#
  2 +# (C) Copyright 2000
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = lib$(BOARD).a
  27 +
  28 +OBJS = $(BOARD).o flash.o
  29 +
  30 +$(LIB): .depend $(OBJS)
  31 + $(AR) crv $@ $^
  32 +
  33 +#########################################################################
  34 +
  35 +.depend: Makefile $(OBJS:.o=.c)
  36 + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
  37 +
  38 +sinclude .depend
  39 +
  40 +#########################################################################
cpu/mpc824x/Makefile
Diff comments   View file @ e85390d
  1 +#
  2 +# (C) Copyright 2000
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = lib$(CPU).a
  27 +
  28 +START = start.S drivers/i2c/i2c2.o
  29 +OBJS = traps.o cpu.o cpu_init.o interrupts.o speed.o \
  30 + drivers/epic/epic1.o drivers/i2c/i2c1.o pci.o
  31 +
  32 +all: .depend $(START) $(LIB)
  33 +
  34 +$(LIB): $(OBJS)
  35 + $(AR) crv $@ $(OBJS) drivers/i2c/i2c2.o
  36 +
  37 +#########################################################################
  38 +
  39 +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
  40 + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
  41 +
  42 +sinclude .depend
  43 +
  44 +#########################################################################
  1 +/*
  2 + * COM1 NS16550 support
  3 + * originally from linux source (arch/ppc/boot/ns16550.c)
  4 + * modified to use CFG_ISA_MEM and new defines
  5 + */
  6 +
  7 +#include <config.h>
  8 +
  9 +#ifdef CFG_NS16550
  10 +
  11 +#include <ns16550.h>
  12 +
  13 +#define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */
  14 +#define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */
  15 +#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs */
  16 +
  17 +void NS16550_init (NS16550_t com_port, int baud_divisor)
  18 +{
  19 + com_port->ier = 0x00;
  20 + com_port->lcr = LCR_BKSE | LCRVAL;
  21 + com_port->dll = baud_divisor & 0xff;
  22 + com_port->dlm = (baud_divisor >> 8) & 0xff;
  23 + com_port->lcr = LCRVAL;
  24 + com_port->mcr = MCRVAL;
  25 + com_port->fcr = FCRVAL;
  26 +}
  27 +
  28 +void NS16550_reinit (NS16550_t com_port, int baud_divisor)
  29 +{
  30 + com_port->ier = 0x00;
  31 + com_port->lcr = LCR_BKSE;
  32 + com_port->dll = baud_divisor & 0xff;
  33 + com_port->dlm = (baud_divisor >> 8) & 0xff;
  34 + com_port->lcr = LCRVAL;
  35 + com_port->mcr = MCRVAL;
  36 + com_port->fcr = FCRVAL;
  37 +}
  38 +
  39 +void NS16550_putc (NS16550_t com_port, char c)
  40 +{
  41 + while ((com_port->lsr & LSR_THRE) == 0);
  42 + com_port->thr = c;
  43 +}
  44 +
  45 +char NS16550_getc (NS16550_t com_port)
  46 +{
  47 + while ((com_port->lsr & LSR_DR) == 0);
  48 + return (com_port->rbr);
  49 +}
  50 +
  51 +int NS16550_tstc (NS16550_t com_port)
  52 +{
  53 + return ((com_port->lsr & LSR_DR) != 0);
  54 +}
  55 +
  56 +#endif
  1 +#ifndef _405GP_PCI_H
  2 +#define _405GP_PCI_H
  3 +
  4 +/*----------------------------------------------------------------------------+
  5 +| 405GP PCI core memory map defines.
  6 ++----------------------------------------------------------------------------*/
  7 +#define MIN_PCI_MEMADDR1 0x80000000
  8 +#define MIN_PCI_MEMADDR2 0x00000000
  9 +#define MIN_PLB_PCI_IOADDR 0xE8000000 /* PLB side of PCI I/O address space */
  10 +#define MIN_PCI_PCI_IOADDR 0x00000000 /* PCI side of PCI I/O address space */
  11 +#define MAX_PCI_DEVICES 32
  12 +
  13 +/*----------------------------------------------------------------------------+
  14 +| Defines for the 405GP PCI Config address and data registers followed by
  15 +| defines for the standard PCI device configuration header.
  16 ++----------------------------------------------------------------------------*/
  17 +#define PCICFGADR 0xEEC00000
  18 +#define PCICFGDATA 0xEEC00004
  19 +
  20 +#define PCIBUSNUM 0x40 /* 405GP specific parameters */
  21 +#define PCISUBBUSNUM 0x41
  22 +#define PCIDISCOUNT 0x42
  23 +#define PCIBRDGOPT1 0x4A
  24 +#define PCIBRDGOPT2 0x60
  25 +
  26 +/*----------------------------------------------------------------------------+
  27 +| Defines for 405GP PCI Master local configuration regs.
  28 ++----------------------------------------------------------------------------*/
  29 +#define PMM0LA 0xEF400000
  30 +#define PMM0MA 0xEF400004
  31 +#define PMM0PCILA 0xEF400008
  32 +#define PMM0PCIHA 0xEF40000C
  33 +#define PMM1LA 0xEF400010
  34 +#define PMM1MA 0xEF400014
  35 +#define PMM1PCILA 0xEF400018
  36 +#define PMM1PCIHA 0xEF40001C
  37 +#define PMM2LA 0xEF400020
  38 +#define PMM2MA 0xEF400024
  39 +#define PMM2PCILA 0xEF400028
  40 +#define PMM2PCIHA 0xEF40002C
  41 +
  42 +/*----------------------------------------------------------------------------+
  43 +| Defines for 405GP PCI Target local configuration regs.
  44 ++----------------------------------------------------------------------------*/
  45 +#define PTM1MS 0xEF400030
  46 +#define PTM1LA 0xEF400034
  47 +#define PTM2MS 0xEF400038
  48 +#define PTM2LA 0xEF40003C
  49 +
  50 +#define PCIDEVID_405GP 0x0
  51 +
  52 +#endif
  1 +/*
  2 + * (C) Copyright 2000
  3 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#ifndef _NS87308_H_
  25 +#define _NS87308_H_
  26 +
  27 +#include <asm/pci_io.h>
  28 +
  29 +/* Note: I couldn't find a full data sheet for the ns87308, but the ns87307 seems to be pretty
  30 + functionally- (and pin-) equivalent to the 87308, but the 308 has better ir support. */
  31 +
  32 +void initialise_ns87308(void);
  33 +
  34 +/*
  35 + * The following struct represents the GPIO registers on the NS87308/NS97307
  36 + */
  37 +struct GPIO
  38 +{
  39 + unsigned char dta1; /* 0 data port 1 */
  40 + unsigned char dir1; /* 1 direction port 1 */
  41 + unsigned char out1; /* 2 output type port 1 */
  42 + unsigned char puc1; /* 3 pull-up control port 1 */
  43 + unsigned char dta2; /* 4 data port 2 */
  44 + unsigned char dir2; /* 5 direction port 2 */
  45 + unsigned char out2; /* 6 output type port 2 */
  46 + unsigned char puc2; /* 7 pull-up control port 2 */
  47 +};
  48 +
  49 +/*
  50 + * The following represents the power management registers on the NS87308/NS97307
  51 + */
  52 +#define PWM_FER1 0 /* 0 function enable reg. 1 */
  53 +#define PWM_FER2 1 /* 1 function enable reg. 2 */
  54 +#define PWM_PMC1 2 /* 2 power mgmt. control 1 */
  55 +#define PWM_PMC2 3 /* 3 power mgmt. control 2 */
  56 +#define PWM_PMC3 4 /* 4 power mgmt. control 3 */
  57 +#define PWM_WDTO 5 /* 5 watchdog time-out */
  58 +#define PWM_WDCF 6 /* 6 watchdog config. */
  59 +#define PWM_WDST 7 /* 7 watchdog status */
  60 +
  61 +/*PNP config registers:
  62 + * these depend on the stated of BADDR1 and BADDR0 on startup
  63 + * so there's three versions here with the last two digits indicating
  64 + * for which configuration their valid
  65 + * the 1st of the two digits indicates the state of BADDR1
  66 + * the 2st of the two digits indicates the state of BADDR0
  67 + */
  68 +
  69 +
  70 +#define IO_INDEX_OFFSET_0x 0x0279 /* full PnP isa Mode */
  71 +#define IO_INDEX_OFFSET_10 0x015C /* PnP motherboard mode */
  72 +#define IO_INDEX_OFFSET_11 0x002E /* PnP motherboard mode */
  73 +#define IO_DATA_OFFSET_0x 0x0A79 /* full PnP isa Mode */
  74 +#define IO_DATA_OFFSET_10 0x015D /* PnP motherboard mode */
  75 +#define IO_DATA_OFFSET_11 0x002F /* PnP motherboard mode */
  76 +
  77 +#if defined(CFG_NS87308_BADDR_0x)
  78 +#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_0x)
  79 +#define IO_DATA (CFG_ISA_IO + IO_DATA_OFFSET_0x)
  80 +#elif defined(CFG_NS87308_BADDR_10)
  81 +#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_10)
  82 +#define IO_DATA (CFG_ISA_IO + IO_DATA_OFFSET_10)
  83 +#elif defined(CFG_NS87308_BADDR_11)
  84 +#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_11)
  85 +#define IO_DATA (CFG_ISA_IO + IO_DATA_OFFSET_11)
  86 +#endif
  87 +
  88 +/* PnP register definitions */
  89 +
  90 +#define SET_RD_DATA_PORT 0x00
  91 +#define SERIAL_ISOLATION 0x01
  92 +#define CONFIG_CONTROL 0x02
  93 +#define WAKE_CSN 0x03
  94 +#define RES_DATA 0x04
  95 +#define STATUS 0x05
  96 +#define SET_CSN 0x06
  97 +#define LOGICAL_DEVICE 0x07
  98 +
  99 +/*vendor defined values */
  100 +#define SID_REG 0x20
  101 +#define SUPOERIO_CONF1 0x21
  102 +#define SUPOERIO_CONF2 0x22
  103 +#define PGCS_INDEX 0x23
  104 +#define PGCS_DATA 0x24
  105 +
  106 +/* values above 30 are different for each logical device
  107 + but I can't be arsed to enter them all. the ones here
  108 + are pretty consistent between all logical devices
  109 + feel free to correct the situation if you want.. ;)
  110 + */
  111 +#define ACTIVATE 0x30
  112 +#define ACTIVATE_OFF 0x00
  113 +#define ACTIVATE_ON 0x01
  114 +
  115 +#define BASE_ADDR_HIGH 0x60
  116 +#define BASE_ADDR_LOW 0x61
  117 +#define LUN_CONFIG_REG 0xF0
  118 +#define DBASE_HIGH 0x60 /* SIO KBC data base address, 15:8 */
  119 +#define DBASE_LOW 0x61 /* SIO KBC data base address, 7:0 */
  120 +#define CBASE_HIGH 0x62 /* SIO KBC command base addr, 15:8 */
  121 +#define CBASE_LOW 0x63 /* SIO KBC command base addr, 7:0 */
  122 +
  123 +/* the logical devices*/
  124 +#define LDEV_KBC1 0x00 /* 2 devices for keyboard and mouse controller*/
  125 +#define LDEV_KBC2 0x01
  126 +#define LDEV_MOUSE 0x01
  127 +#define LDEV_RTC_APC 0x02 /*Real Time Clock and Advanced Power Control*/
  128 +#define LDEV_FDC 0x03 /*floppy disk controller*/
  129 +#define LDEV_PARP 0x04 /*Parallel port*/
  130 +#define LDEV_UART2 0x05
  131 +#define LDEV_UART1 0x06
  132 +#define LDEV_GPIO 0x07 /*General Purpose IO and chip select output signals*/
  133 +#define LDEV_POWRMAN 0x08 /*Power Managment*/
  134 +
  135 +#define CFG_NS87308_KBC1 (1 << LDEV_KBC1)
  136 +#define CFG_NS87308_KBC2 (1 << LDEV_KBC2)
  137 +#define CFG_NS87308_MOUSE (1 << LDEV_MOUSE)
  138 +#define CFG_NS87308_RTC_APC (1 << LDEV_RTC_APC)
  139 +#define CFG_NS87308_FDC (1 << LDEV_FDC)
  140 +#define CFG_NS87308_PARP (1 << LDEV_PARP)
  141 +#define CFG_NS87308_UART2 (1 << LDEV_UART2)
  142 +#define CFG_NS87308_UART1 (1 << LDEV_UART1)
  143 +#define CFG_NS87308_GPIO (1 << LDEV_GPIO)
  144 +#define CFG_NS87308_POWRMAN (1 << LDEV_POWRMAN)
  145 +
  146 +/*some functions and macro's for doing configuration */
  147 +
  148 +static inline void read_pnp_config(unsigned char index, unsigned char *data)
  149 +{
  150 + pci_writeb(index,IO_INDEX);
  151 + pci_readb(IO_DATA, *data);
  152 +}
  153 +
  154 +static inline void write_pnp_config(unsigned char index, unsigned char data)
  155 +{
  156 + pci_writeb(index,IO_INDEX);
  157 + pci_writeb(data, IO_DATA);
  158 +}
  159 +
  160 +static inline void pnp_set_device(unsigned char dev)
  161 +{
  162 + write_pnp_config(LOGICAL_DEVICE, dev);
  163 +}
  164 +
  165 +static inline void write_pm_reg(unsigned short base, unsigned char index, unsigned char data)
  166 +{
  167 + pci_writeb(index, CFG_ISA_IO + base);
  168 + eieio();
  169 + pci_writeb(data, CFG_ISA_IO + base + 1);
  170 +}
  171 +
  172 +/*void write_pnp_config(unsigned char index, unsigned char data);
  173 +void pnp_set_device(unsigned char dev);
  174 +*/
  175 +
  176 +#define PNP_SET_DEVICE_BASE(dev,base) \
  177 + pnp_set_device(dev); \
  178 + write_pnp_config(ACTIVATE, ACTIVATE_OFF); \
  179 + write_pnp_config(BASE_ADDR_HIGH, ((base) >> 8) & 0xff ); \
  180 + write_pnp_config(BASE_ADDR_LOW, (base) &0xff); \
  181 + write_pnp_config(ACTIVATE, ACTIVATE_ON);
  182 +
  183 +#define PNP_ACTIVATE_DEVICE(dev) \
  184 + pnp_set_device(dev); \
  185 + write_pnp_config(ACTIVATE, ACTIVATE_ON);
  186 +
  187 +#define PNP_DEACTIVATE_DEVICE(dev) \
  188 + pnp_set_device(dev); \
  189 + write_pnp_config(ACTIVATE, ACTIVATE_OFF);
  190 +
  191 +
  192 +static inline void write_pgcs_config(unsigned char index, unsigned char data)
  193 +{
  194 + write_pnp_config(PGCS_INDEX, index);
  195 + write_pnp_config(PGCS_DATA, data);
  196 +}
  197 +
  198 +/* these macrose configure the 3 CS lines
  199 + on the sandpoint board these controll NVRAM
  200 + CS0 is connected to NVRAMCS
  201 + CS1 is connected to NVRAMAS0
  202 + CS2 is connected to NVRAMAS1
  203 + */
  204 +#define PGCS_CS_ASSERT_ON_WRITE 0x10
  205 +#define PGCS_CS_ASSERT_ON_READ 0x20
  206 +
  207 +#define PNP_PGCS_CSLINE_BASE(cs, base) \
  208 + write_pgcs_config((cs) << 2, ((base) >> 8) & 0xff ); \
  209 + write_pgcs_config(((cs) << 2) + 1, (base) & 0xff );
  210 +
  211 +#define PNP_PGCS_CSLINE_CONF(cs, conf) \
  212 + write_pgcs_config(((cs) << 2) + 2, (conf) );
  213 +
  214 +
  215 +/* The following sections are for 87308 extensions to the standard compoents it emulates */
  216 +
  217 +/* extensions to 16550*/
  218 +
  219 +#define MCR_MDSL_MSK 0xe0 /*mode select mask*/
  220 +#define MCR_MDSL_UART 0x00 /*uart, default*/
  221 +#define MCR_MDSL_SHRPIR 0x02 /*Sharp IR*/
  222 +#define MCR_MDSL_SIR 0x03 /*SIR*/
  223 +#define MCR_MDSL_CIR 0x06 /*Consumer IR*/
  224 +
  225 +#define FCR_TXFTH0 0x10 /* these bits control threshod of data level in fifo */
  226 +#define FCR_TXFTH1 0x20 /* for interrupt trigger */
  227 +
  228 +/*
  229 + * Default NS87308 configuration
  230 + */
  231 +#ifndef CFG_NS87308_KBC1_BASE
  232 +#define CFG_NS87308_KBC1_BASE 0x0060
  233 +#endif
  234 +#ifndef CFG_NS87308_RTC_BASE
  235 +#define CFG_NS87308_RTC_BASE 0x0070
  236 +#endif
  237 +#ifndef CFG_NS87308_FDC_BASE
  238 +#define CFG_NS87308_FDC_BASE 0x03F0
  239 +#endif
  240 +#ifndef CFG_NS87308_LPT_BASE
  241 +#define CFG_NS87308_LPT_BASE 0x0278
  242 +#endif
  243 +#ifndef CFG_NS87308_UART1_BASE
  244 +#define CFG_NS87308_UART1_BASE 0x03F8
  245 +#endif
  246 +#ifndef CFG_NS87308_UART2_BASE
  247 +#define CFG_NS87308_UART2_BASE 0x02F8
  248 +#endif
  249 +
  250 +#endif /*_NS87308_H_*/
  1 +/*
  2 + * (C) Copyright 2001
  3 + * Denis Peter, MPL AG Switzerland
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + *
  23 + */
  24 + #ifndef _SCSI_H
  25 + #define _SCSI_H
  26 +
  27 +typedef struct SCSI_cmd_block{
  28 + unsigned char cmd[16]; /* command */
  29 + unsigned char sense_buf[64]; /* for request sense */
  30 + unsigned char status; /* SCSI Status */
  31 + unsigned char target; /* Target ID */
  32 + unsigned char lun; /* Target LUN */
  33 + unsigned char cmdlen; /* command len */
  34 + unsigned long datalen; /* Total data length */
  35 + unsigned char * pdata; /* pointer to data */
  36 + unsigned char msgout[12]; /* Messge out buffer (NOT USED) */
  37 + unsigned char msgin[12]; /* Message in buffer */
  38 + unsigned char sensecmdlen; /* Sense command len */
  39 + unsigned long sensedatalen; /* Sense data len */
  40 + unsigned char sensecmd[6]; /* Sense command */
  41 + unsigned long contr_stat; /* Controller Status */
  42 + unsigned long trans_bytes; /* tranfered bytes */
  43 +
  44 + unsigned int priv;
  45 +}ccb;
  46 +
  47 +/*-----------------------------------------------------------
  48 +**
  49 +** SCSI constants.
  50 +**
  51 +**-----------------------------------------------------------
  52 +*/
  53 +
  54 +/*
  55 +** Messages
  56 +*/
  57 +
  58 +#define M_COMPLETE (0x00)
  59 +#define M_EXTENDED (0x01)
  60 +#define M_SAVE_DP (0x02)
  61 +#define M_RESTORE_DP (0x03)
  62 +#define M_DISCONNECT (0x04)
  63 +#define M_ID_ERROR (0x05)
  64 +#define M_ABORT (0x06)
  65 +#define M_REJECT (0x07)
  66 +#define M_NOOP (0x08)
  67 +#define M_PARITY (0x09)
  68 +#define M_LCOMPLETE (0x0a)
  69 +#define M_FCOMPLETE (0x0b)
  70 +#define M_RESET (0x0c)
  71 +#define M_ABORT_TAG (0x0d)
  72 +#define M_CLEAR_QUEUE (0x0e)
  73 +#define M_INIT_REC (0x0f)
  74 +#define M_REL_REC (0x10)
  75 +#define M_TERMINATE (0x11)
  76 +#define M_SIMPLE_TAG (0x20)
  77 +#define M_HEAD_TAG (0x21)
  78 +#define M_ORDERED_TAG (0x22)
  79 +#define M_IGN_RESIDUE (0x23)
  80 +#define M_IDENTIFY (0x80)
  81 +
  82 +#define M_X_MODIFY_DP (0x00)
  83 +#define M_X_SYNC_REQ (0x01)
  84 +#define M_X_WIDE_REQ (0x03)
  85 +#define M_X_PPR_REQ (0x04)
  86 +
  87 +
  88 +/*
  89 +** Status
  90 +*/
  91 +
  92 +#define S_GOOD (0x00)
  93 +#define S_CHECK_COND (0x02)
  94 +#define S_COND_MET (0x04)
  95 +#define S_BUSY (0x08)
  96 +#define S_INT (0x10)
  97 +#define S_INT_COND_MET (0x14)
  98 +#define S_CONFLICT (0x18)
  99 +#define S_TERMINATED (0x20)
  100 +#define S_QUEUE_FULL (0x28)
  101 +#define S_ILLEGAL (0xff)
  102 +#define S_SENSE (0x80)
  103 +
  104 +/*
  105 + * Sense_keys
  106 + */
  107 +
  108 +#define SENSE_NO_SENSE 0x0
  109 +#define SENSE_RECOVERED_ERROR 0x1
  110 +#define SENSE_NOT_READY 0x2
  111 +#define SENSE_MEDIUM_ERROR 0x3
  112 +#define SENSE_HARDWARE_ERROR 0x4
  113 +#define SENSE_ILLEGAL_REQUEST 0x5
  114 +#define SENSE_UNIT_ATTENTION 0x6
  115 +#define SENSE_DATA_PROTECT 0x7
  116 +#define SENSE_BLANK_CHECK 0x8
  117 +#define SENSE_VENDOR_SPECIFIC 0x9
  118 +#define SENSE_COPY_ABORTED 0xA
  119 +#define SENSE_ABORTED_COMMAND 0xB
  120 +#define SENSE_VOLUME_OVERFLOW 0xD
  121 +#define SENSE_MISCOMPARE 0xE
  122 +
  123 +
  124 +#define SCSI_CHANGE_DEF 0x40 /* Change Definition (Optional) */
  125 +#define SCSI_COMPARE 0x39 /* Compare (O) */
  126 +#define SCSI_COPY 0x18 /* Copy (O) */
  127 +#define SCSI_COP_VERIFY 0x3A /* Copy and Verify (O) */
  128 +#define SCSI_INQUIRY 0x12 /* Inquiry (MANDATORY) */
  129 +#define SCSI_LOG_SELECT 0x4C /* Log Select (O) */
  130 +#define SCSI_LOG_SENSE 0x4D /* Log Sense (O) */
  131 +#define SCSI_MODE_SEL6 0x15 /* Mode Select 6-byte (Device Specific) */
  132 +#define SCSI_MODE_SEL10 0x55 /* Mode Select 10-byte (Device Specific) */
  133 +#define SCSI_MODE_SEN6 0x1A /* Mode Sense 6-byte (Device Specific) */
  134 +#define SCSI_MODE_SEN10 0x5A /* Mode Sense 10-byte (Device Specific) */
  135 +#define SCSI_READ_BUFF 0x3C /* Read Buffer (O) */
  136 +#define SCSI_REQ_SENSE 0x03 /* Request Sense (MANDATORY) */
  137 +#define SCSI_SEND_DIAG 0x1D /* Send Diagnostic (O) */
  138 +#define SCSI_TST_U_RDY 0x00 /* Test Unit Ready (MANDATORY) */
  139 +#define SCSI_WRITE_BUFF 0x3B /* Write Buffer (O) */
  140 +/***************************************************************************
  141 + * %%% Commands Unique to Direct Access Devices %%%
  142 + ***************************************************************************/
  143 +#define SCSI_COMPARE 0x39 /* Compare (O) */
  144 +#define SCSI_FORMAT 0x04 /* Format Unit (MANDATORY) */
  145 +#define SCSI_LCK_UN_CAC 0x36 /* Lock Unlock Cache (O) */
  146 +#define SCSI_PREFETCH 0x34 /* Prefetch (O) */
  147 +#define SCSI_MED_REMOVL 0x1E /* Prevent/Allow medium Removal (O) */
  148 +#define SCSI_READ6 0x08 /* Read 6-byte (MANDATORY) */
  149 +#define SCSI_READ10 0x28 /* Read 10-byte (MANDATORY) */
  150 +#define SCSI_RD_CAPAC 0x25 /* Read Capacity (MANDATORY) */
  151 +#define SCSI_RD_DEFECT 0x37 /* Read Defect Data (O) */
  152 +#define SCSI_READ_LONG 0x3E /* Read Long (O) */
  153 +#define SCSI_REASS_BLK 0x07 /* Reassign Blocks (O) */
  154 +#define SCSI_RCV_DIAG 0x1C /* Receive Diagnostic Results (O) */
  155 +#define SCSI_RELEASE 0x17 /* Release Unit (MANDATORY) */
  156 +#define SCSI_REZERO 0x01 /* Rezero Unit (O) */
  157 +#define SCSI_SRCH_DAT_E 0x31 /* Search Data Equal (O) */
  158 +#define SCSI_SRCH_DAT_H 0x30 /* Search Data High (O) */
  159 +#define SCSI_SRCH_DAT_L 0x32 /* Search Data Low (O) */
  160 +#define SCSI_SEEK6 0x0B /* Seek 6-Byte (O) */
  161 +#define SCSI_SEEK10 0x2B /* Seek 10-Byte (O) */
  162 +#define SCSI_SEND_DIAG 0x1D /* Send Diagnostics (MANDATORY) */
  163 +#define SCSI_SET_LIMIT 0x33 /* Set Limits (O) */
  164 +#define SCSI_START_STP 0x1B /* Start/Stop Unit (O) */
  165 +#define SCSI_SYNC_CACHE 0x35 /* Synchronize Cache (O) */
  166 +#define SCSI_VERIFY 0x2F /* Verify (O) */
  167 +#define SCSI_WRITE6 0x0A /* Write 6-Byte (MANDATORY) */
  168 +#define SCSI_WRITE10 0x2A /* Write 10-Byte (MANDATORY) */
  169 +#define SCSI_WRT_VERIFY 0x2E /* Write and Verify (O) */
  170 +#define SCSI_WRITE_LONG 0x3F /* Write Long (O) */
  171 +#define SCSI_WRITE_SAME 0x41 /* Write Same (O) */
  172 +
  173 +
  174 +/****************************************************************************
  175 + * decleration of functions which have to reside in the LowLevel Part Driver
  176 + */
  177 +
  178 +void scsi_print_error(ccb *pccb);
  179 +int scsi_exec(ccb *pccb);
  180 +void scsi_bus_reset(void);
  181 +void scsi_low_level_init(int busdevfunc);
  182 +
  183 +
  184 +/***************************************************************************
  185 + * functions residing inside cmd_scsi.c
  186 + */
  187 +void scsi_init(void);
  188 +
  189 +
  190 +
  191 +#define SCSI_IDENTIFY 0xC0 /* not used */
  192 +
  193 +/* Hardware errors */
  194 +#define SCSI_SEL_TIME_OUT 0x00000101 /* Selection time out */
  195 +#define SCSI_HNS_TIME_OUT 0x00000102 /* Handshake */
  196 +#define SCSI_MA_TIME_OUT 0x00000103 /* Phase error */
  197 +#define SCSI_UNEXP_DIS 0x00000104 /* unexpected disconnect */
  198 +
  199 +#define SCSI_INT_STATE 0x00010000 /* unknown Interrupt number is stored in 16 LSB */
  200 +
  201 +
  202 +
  203 +#ifndef TRUE
  204 +#define TRUE 1
  205 +#endif
  206 +#ifndef FALSE
  207 +#define FALSE 0
  208 +#endif
  209 +
  210 +
  211 +
  212 +
  213 +
  214 +#endif /* _SCSI_H */
  1 +/*
  2 + * (C) Copyright 2001
  3 + * Denis Peter, MPL AG Switzerland
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + *
  23 + *
  24 + * Most of these definitions are derived from
  25 + * linux/drivers/scsi/sym53c8xx_defs.h
  26 + *
  27 + */
  28 +
  29 +#ifndef _SYM53C8XX_DEFS_H
  30 +#define _SYM53C8XX_DEFS_H
  31 +
  32 +
  33 +#define SCNTL0 0x00 /* full arb., ena parity, par->ATN */
  34 +
  35 +#define SCNTL1 0x01 /* no reset */
  36 + #define ISCON 0x10 /* connected to scsi */
  37 + #define CRST 0x08 /* force reset */
  38 + #define IARB 0x02 /* immediate arbitration */
  39 +
  40 +#define SCNTL2 0x02 /* no disconnect expected */
  41 + #define SDU 0x80 /* cmd: disconnect will raise error */
  42 + #define CHM 0x40 /* sta: chained mode */
  43 + #define WSS 0x08 /* sta: wide scsi send [W]*/
  44 + #define WSR 0x01 /* sta: wide scsi received [W]*/
  45 +
  46 +#define SCNTL3 0x03 /* cnf system clock dependent */
  47 + #define EWS 0x08 /* cmd: enable wide scsi [W]*/
  48 + #define ULTRA 0x80 /* cmd: ULTRA enable */
  49 + /* bits 0-2, 7 rsvd for C1010 */
  50 +
  51 +#define SCID 0x04 /* cnf host adapter scsi address */
  52 + #define RRE 0x40 /* r/w:e enable response to resel. */
  53 + #define SRE 0x20 /* r/w:e enable response to select */
  54 +
  55 +#define SXFER 0x05 /* ### Sync speed and count */
  56 + /* bits 6-7 rsvd for C1010 */
  57 +
  58 +#define SDID 0x06 /* ### Destination-ID */
  59 +
  60 +#define GPREG 0x07 /* ??? IO-Pins */
  61 +
  62 +#define SFBR 0x08 /* ### First byte in phase */
  63 +
  64 +#define SOCL 0x09
  65 + #define CREQ 0x80 /* r/w: SCSI-REQ */
  66 + #define CACK 0x40 /* r/w: SCSI-ACK */
  67 + #define CBSY 0x20 /* r/w: SCSI-BSY */
  68 + #define CSEL 0x10 /* r/w: SCSI-SEL */
  69 + #define CATN 0x08 /* r/w: SCSI-ATN */
  70 + #define CMSG 0x04 /* r/w: SCSI-MSG */
  71 + #define CC_D 0x02 /* r/w: SCSI-C_D */
  72 + #define CI_O 0x01 /* r/w: SCSI-I_O */
  73 +
  74 +#define SSID 0x0a
  75 +
  76 +#define SBCL 0x0b
  77 +
  78 +#define DSTAT 0x0c
  79 + #define DFE 0x80 /* sta: dma fifo empty */
  80 + #define MDPE 0x40 /* int: master data parity error */
  81 + #define BF 0x20 /* int: script: bus fault */
  82 + #define ABRT 0x10 /* int: script: command aborted */
  83 + #define SSI 0x08 /* int: script: single step */
  84 + #define SIR 0x04 /* int: script: interrupt instruct. */
  85 + #define IID 0x01 /* int: script: illegal instruct. */
  86 +
  87 +#define SSTAT0 0x0d
  88 + #define ILF 0x80 /* sta: data in SIDL register lsb */
  89 + #define ORF 0x40 /* sta: data in SODR register lsb */
  90 + #define OLF 0x20 /* sta: data in SODL register lsb */
  91 + #define AIP 0x10 /* sta: arbitration in progress */
  92 + #define LOA 0x08 /* sta: arbitration lost */
  93 + #define WOA 0x04 /* sta: arbitration won */
  94 + #define IRST 0x02 /* sta: scsi reset signal */
  95 + #define SDP 0x01 /* sta: scsi parity signal */
  96 +
  97 +#define SSTAT1 0x0e
  98 + #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
  99 +
  100 +#define SSTAT2 0x0f
  101 + #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
  102 + #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
  103 + #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
  104 + #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
  105 + #define LDSC 0x02 /* sta: disconnect & reconnect */
  106 +
  107 +#define DSA 0x10 /* --> Base page */
  108 +#define DSA1 0x11
  109 +#define DSA2 0x12
  110 +#define DSA3 0x13
  111 +
  112 +#define ISTAT 0x14 /* --> Main Command and status */
  113 + #define CABRT 0x80 /* cmd: abort current operation */
  114 + #define SRST 0x40 /* mod: reset chip */
  115 + #define SIGP 0x20 /* r/w: message from host to ncr */
  116 + #define SEM 0x10 /* r/w: message between host + ncr */
  117 + #define CON 0x08 /* sta: connected to scsi */
  118 + #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
  119 + #define SIP 0x02 /* sta: scsi-interrupt */
  120 + #define DIP 0x01 /* sta: host/script interrupt */
  121 +
  122 +
  123 +#define CTEST0 0x18
  124 +#define CTEST1 0x19
  125 +#define CTEST2 0x1a
  126 + #define CSIGP 0x40
  127 + /* bits 0-2,7 rsvd for C1010 */
  128 +
  129 +#define CTEST3 0x1b
  130 + #define FLF 0x08 /* cmd: flush dma fifo */
  131 + #define CLF 0x04 /* cmd: clear dma fifo */
  132 + #define FM 0x02 /* mod: fetch pin mode */
  133 + #define WRIE 0x01 /* mod: write and invalidate enable */
  134 + /* bits 4-7 rsvd for C1010 */
  135 +
  136 +#define DFIFO 0x20
  137 +#define CTEST4 0x21
  138 + #define BDIS 0x80 /* mod: burst disable */
  139 + #define MPEE 0x08 /* mod: master parity error enable */
  140 +
  141 +#define CTEST5 0x22
  142 + #define DFS 0x20 /* mod: dma fifo size */
  143 + /* bits 0-1, 3-7 rsvd for C1010 */
  144 +#define CTEST6 0x23
  145 +
  146 +#define DBC 0x24 /* ### Byte count and command */
  147 +#define DNAD 0x28 /* ### Next command register */
  148 +#define DSP 0x2c /* --> Script Pointer */
  149 +#define DSPS 0x30 /* --> Script pointer save/opcode#2 */
  150 +
  151 +#define SCRATCHA 0x34 /* Temporary register a */
  152 +#define SCRATCHA1 0x35
  153 +#define SCRATCHA2 0x36
  154 +#define SCRATCHA3 0x37
  155 +
  156 +#define DMODE 0x38
  157 + #define BL_2 0x80 /* mod: burst length shift value +2 */
  158 + #define BL_1 0x40 /* mod: burst length shift value +1 */
  159 + #define ERL 0x08 /* mod: enable read line */
  160 + #define ERMP 0x04 /* mod: enable read multiple */
  161 + #define BOF 0x02 /* mod: burst op code fetch */
  162 + #define MAN 0x01 /* mod: manual start */
  163 +
  164 +#define DIEN 0x39
  165 +#define SBR 0x3a
  166 +
  167 +#define DCNTL 0x3b /* --> Script execution control */
  168 + #define CLSE 0x80 /* mod: cache line size enable */
  169 + #define PFF 0x40 /* cmd: pre-fetch flush */
  170 + #define PFEN 0x20 /* mod: pre-fetch enable */
  171 + #define SSM 0x10 /* mod: single step mode */
  172 + #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
  173 + #define STD 0x04 /* cmd: start dma mode */
  174 + #define IRQD 0x02 /* mod: irq disable */
  175 + #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
  176 + /* bits 0-1 rsvd for C1010 */
  177 +
  178 +#define ADDER 0x3c
  179 +
  180 +#define SIEN 0x40 /* -->: interrupt enable */
  181 +#define SIST 0x42 /* <--: interrupt status */
  182 + #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
  183 + #define STO 0x0400/* sta: timeout (select) */
  184 + #define GEN 0x0200/* sta: timeout (general) */
  185 + #define HTH 0x0100/* sta: timeout (handshake) */
  186 + #define MA 0x80 /* sta: phase mismatch */
  187 + #define CMP 0x40 /* sta: arbitration complete */
  188 + #define SEL 0x20 /* sta: selected by another device */
  189 + #define RSL 0x10 /* sta: reselected by another device*/
  190 + #define SGE 0x08 /* sta: gross error (over/underflow)*/
  191 + #define UDC 0x04 /* sta: unexpected disconnect */
  192 + #define RST 0x02 /* sta: scsi bus reset detected */
  193 + #define PAR 0x01 /* sta: scsi parity error */
  194 +
  195 +#define SLPAR 0x44
  196 +#define SWIDE 0x45
  197 +#define MACNTL 0x46
  198 +#define GPCNTL 0x47
  199 +#define STIME0 0x48 /* cmd: timeout for select&handshake*/
  200 +#define STIME1 0x49 /* cmd: timeout user defined */
  201 +#define RESPID 0x4a /* sta: Reselect-IDs */
  202 +
  203 +#define STEST0 0x4c
  204 +
  205 +#define STEST1 0x4d
  206 + #define SCLK 0x80 /* Use the PCI clock as SCSI clock */
  207 + #define DBLEN 0x08 /* clock doubler running */
  208 + #define DBLSEL 0x04 /* clock doubler selected */
  209 +
  210 +
  211 +#define STEST2 0x4e
  212 + #define ROF 0x40 /* reset scsi offset (after gross error!) */
  213 + #define EXT 0x02 /* extended filtering */
  214 +
  215 +#define STEST3 0x4f
  216 + #define TE 0x80 /* c: tolerAnt enable */
  217 + #define HSC 0x20 /* c: Halt SCSI Clock */
  218 + #define CSF 0x02 /* c: clear scsi fifo */
  219 +
  220 +#define SIDL 0x50 /* Lowlevel: latched from scsi data */
  221 +#define STEST4 0x52
  222 + #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
  223 + #define SMODE_HVD 0x40 /* High Voltage Differential */
  224 + #define SMODE_SE 0x80 /* Single Ended */
  225 + #define SMODE_LVD 0xc0 /* Low Voltage Differential */
  226 + #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
  227 + /* bits 0-5 rsvd for C1010 */
  228 +
  229 +#define SODL 0x54 /* Lowlevel: data out to scsi data */
  230 +
  231 +#define SBDL 0x58 /* Lowlevel: data from scsi data */
  232 +
  233 +
  234 +
  235 +
  236 +/*-----------------------------------------------------------
  237 +**
  238 +** Utility macros for the script.
  239 +**
  240 +**-----------------------------------------------------------
  241 +*/
  242 +
  243 +#define REG(r) (r)
  244 +
  245 +/*-----------------------------------------------------------
  246 +**
  247 +** SCSI phases
  248 +**
  249 +** DT phases illegal for ncr driver.
  250 +**
  251 +**-----------------------------------------------------------
  252 +*/
  253 +
  254 +#define SCR_DATA_OUT 0x00000000
  255 +#define SCR_DATA_IN 0x01000000
  256 +#define SCR_COMMAND 0x02000000
  257 +#define SCR_STATUS 0x03000000
  258 +#define SCR_DT_DATA_OUT 0x04000000
  259 +#define SCR_DT_DATA_IN 0x05000000
  260 +#define SCR_MSG_OUT 0x06000000
  261 +#define SCR_MSG_IN 0x07000000
  262 +
  263 +#define SCR_ILG_OUT 0x04000000
  264 +#define SCR_ILG_IN 0x05000000
  265 +
  266 +/*-----------------------------------------------------------
  267 +**
  268 +** Data transfer via SCSI.
  269 +**
  270 +**-----------------------------------------------------------
  271 +**
  272 +** MOVE_ABS (LEN)
  273 +** <<start address>>
  274 +**
  275 +** MOVE_IND (LEN)
  276 +** <<dnad_offset>>
  277 +**
  278 +** MOVE_TBL
  279 +** <<dnad_offset>>
  280 +**
  281 +**-----------------------------------------------------------
  282 +*/
  283 +
  284 +#define OPC_MOVE 0x08000000
  285 +
  286 +#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
  287 +#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
  288 +#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
  289 +
  290 +#define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
  291 +#define SCR_CHMOV_IND(l) ((0x20000000) | (l))
  292 +#define SCR_CHMOV_TBL (0x10000000)
  293 +
  294 +
  295 +/*-----------------------------------------------------------
  296 +**
  297 +** Selection
  298 +**
  299 +**-----------------------------------------------------------
  300 +**
  301 +** SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
  302 +** <<alternate_address>>
  303 +**
  304 +** SEL_TBL | << dnad_offset>> [ | REL_JMP]
  305 +** <<alternate_address>>
  306 +**
  307 +**-----------------------------------------------------------
  308 +*/
  309 +
  310 +#define SCR_SEL_ABS 0x40000000
  311 +#define SCR_SEL_ABS_ATN 0x41000000
  312 +#define SCR_SEL_TBL 0x42000000
  313 +#define SCR_SEL_TBL_ATN 0x43000000
  314 +
  315 +
  316 +#define SCR_JMP_REL 0x04000000
  317 +#define SCR_ID(id) (((unsigned long)(id)) << 16)
  318 +
  319 +/*-----------------------------------------------------------
  320 +**
  321 +** Waiting for Disconnect or Reselect
  322 +**
  323 +**-----------------------------------------------------------
  324 +**
  325 +** WAIT_DISC
  326 +** dummy: <<alternate_address>>
  327 +**
  328 +** WAIT_RESEL
  329 +** <<alternate_address>>
  330 +**
  331 +**-----------------------------------------------------------
  332 +*/
  333 +
  334 +#define SCR_WAIT_DISC 0x48000000
  335 +#define SCR_WAIT_RESEL 0x50000000
  336 +
  337 +/*-----------------------------------------------------------
  338 +**
  339 +** Bit Set / Reset
  340 +**
  341 +**-----------------------------------------------------------
  342 +**
  343 +** SET (flags {|.. })
  344 +**
  345 +** CLR (flags {|.. })
  346 +**
  347 +**-----------------------------------------------------------
  348 +*/
  349 +
  350 +#define SCR_SET(f) (0x58000000 | (f))
  351 +#define SCR_CLR(f) (0x60000000 | (f))
  352 +
  353 +#define SCR_CARRY 0x00000400
  354 +#define SCR_TRG 0x00000200
  355 +#define SCR_ACK 0x00000040
  356 +#define SCR_ATN 0x00000008
  357 +
  358 +
  359 +
  360 +
  361 +/*-----------------------------------------------------------
  362 +**
  363 +** Memory to memory move
  364 +**
  365 +**-----------------------------------------------------------
  366 +**
  367 +** COPY (bytecount)
  368 +** << source_address >>
  369 +** << destination_address >>
  370 +**
  371 +** SCR_COPY sets the NO FLUSH option by default.
  372 +** SCR_COPY_F does not set this option.
  373 +**
  374 +** For chips which do not support this option,
  375 +** ncr_copy_and_bind() will remove this bit.
  376 +**-----------------------------------------------------------
  377 +*/
  378 +
  379 +#define SCR_NO_FLUSH 0x01000000
  380 +
  381 +#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
  382 +#define SCR_COPY_F(n) (0xc0000000 | (n))
  383 +
  384 +/*-----------------------------------------------------------
  385 +**
  386 +** Register move and binary operations
  387 +**
  388 +**-----------------------------------------------------------
  389 +**
  390 +** SFBR_REG (reg, op, data) reg = SFBR op data
  391 +** << 0 >>
  392 +**
  393 +** REG_SFBR (reg, op, data) SFBR = reg op data
  394 +** << 0 >>
  395 +**
  396 +** REG_REG (reg, op, data) reg = reg op data
  397 +** << 0 >>
  398 +**
  399 +**-----------------------------------------------------------
  400 +** On 810A, 860, 825A, 875, 895 and 896 chips the content
  401 +** of SFBR register can be used as data (SCR_SFBR_DATA).
  402 +** The 896 has additionnal IO registers starting at
  403 +** offset 0x80. Bit 7 of register offset is stored in
  404 +** bit 7 of the SCRIPTS instruction first DWORD.
  405 +**-----------------------------------------------------------
  406 +*/
  407 +
  408 +#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */
  409 +
  410 +#define SCR_SFBR_REG(reg,op,data) \
  411 + (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
  412 +
  413 +#define SCR_REG_SFBR(reg,op,data) \
  414 + (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
  415 +
  416 +#define SCR_REG_REG(reg,op,data) \
  417 + (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
  418 +
  419 +
  420 +#define SCR_LOAD 0x00000000
  421 +#define SCR_SHL 0x01000000
  422 +#define SCR_OR 0x02000000
  423 +#define SCR_XOR 0x03000000
  424 +#define SCR_AND 0x04000000
  425 +#define SCR_SHR 0x05000000
  426 +#define SCR_ADD 0x06000000
  427 +#define SCR_ADDC 0x07000000
  428 +
  429 +#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
  430 +
  431 +/*-----------------------------------------------------------
  432 +**
  433 +** FROM_REG (reg) SFBR = reg
  434 +** << 0 >>
  435 +**
  436 +** TO_REG (reg) reg = SFBR
  437 +** << 0 >>
  438 +**
  439 +** LOAD_REG (reg, data) reg = <data>
  440 +** << 0 >>
  441 +**
  442 +** LOAD_SFBR(data) SFBR = <data>
  443 +** << 0 >>
  444 +**
  445 +**-----------------------------------------------------------
  446 +*/
  447 +
  448 +#define SCR_FROM_REG(reg) \
  449 + SCR_REG_SFBR(reg,SCR_OR,0)
  450 +
  451 +#define SCR_TO_REG(reg) \
  452 + SCR_SFBR_REG(reg,SCR_OR,0)
  453 +
  454 +#define SCR_LOAD_REG(reg,data) \
  455 + SCR_REG_REG(reg,SCR_LOAD,data)
  456 +
  457 +#define SCR_LOAD_SFBR(data) \
  458 + (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
  459 +
  460 +/*-----------------------------------------------------------
  461 +**
  462 +** LOAD from memory to register.
  463 +** STORE from register to memory.
  464 +**
  465 +** Only supported by 810A, 860, 825A, 875, 895 and 896.
  466 +**
  467 +**-----------------------------------------------------------
  468 +**
  469 +** LOAD_ABS (LEN)
  470 +** <<start address>>
  471 +**
  472 +** LOAD_REL (LEN) (DSA relative)
  473 +** <<dsa_offset>>
  474 +**
  475 +**-----------------------------------------------------------
  476 +*/
  477 +
  478 +#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
  479 +#define SCR_NO_FLUSH2 0x02000000
  480 +#define SCR_DSA_REL2 0x10000000
  481 +
  482 +#define SCR_LOAD_R(reg, how, n) \
  483 + (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
  484 +
  485 +#define SCR_STORE_R(reg, how, n) \
  486 + (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
  487 +
  488 +#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
  489 +#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
  490 +#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
  491 +#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
  492 +
  493 +#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
  494 +#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
  495 +#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
  496 +#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
  497 +
  498 +
  499 +/*-----------------------------------------------------------
  500 +**
  501 +** Waiting for Disconnect or Reselect
  502 +**
  503 +**-----------------------------------------------------------
  504 +**
  505 +** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
  506 +** <<address>>
  507 +**
  508 +** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
  509 +** <<distance>>
  510 +**
  511 +** CALL [ | IFTRUE/IFFALSE ( ... ) ]
  512 +** <<address>>
  513 +**
  514 +** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
  515 +** <<distance>>
  516 +**
  517 +** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
  518 +** <<dummy>>
  519 +**
  520 +** INT [ | IFTRUE/IFFALSE ( ... ) ]
  521 +** <<ident>>
  522 +**
  523 +** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
  524 +** <<ident>>
  525 +**
  526 +** Conditions:
  527 +** WHEN (phase)
  528 +** IF (phase)
  529 +** CARRYSET
  530 +** DATA (data, mask)
  531 +**
  532 +**-----------------------------------------------------------
  533 +*/
  534 +
  535 +#define SCR_NO_OP 0x80000000
  536 +#define SCR_JUMP 0x80080000
  537 +#define SCR_JUMP64 0x80480000
  538 +#define SCR_JUMPR 0x80880000
  539 +#define SCR_CALL 0x88080000
  540 +#define SCR_CALLR 0x88880000
  541 +#define SCR_RETURN 0x90080000
  542 +#define SCR_INT 0x98080000
  543 +#define SCR_INT_FLY 0x98180000
  544 +
  545 +#define IFFALSE(arg) (0x00080000 | (arg))
  546 +#define IFTRUE(arg) (0x00000000 | (arg))
  547 +
  548 +#define WHEN(phase) (0x00030000 | (phase))
  549 +#define IF(phase) (0x00020000 | (phase))
  550 +
  551 +#define DATA(D) (0x00040000 | ((D) & 0xff))
  552 +#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
  553 +
  554 +#define CARRYSET (0x00200000)
  555 +
  556 +
  557 +
  558 +#define SIR_COMPLETE 0x10000000
  559 +/* script errors */
  560 +#define SIR_SEL_ATN_NO_MSG_OUT 0x00000001
  561 +#define SIR_CMD_OUT_ILL_PH 0x00000002
  562 +#define SIR_STATUS_ILL_PH 0x00000003
  563 +#define SIR_MSG_RECEIVED 0x00000004
  564 +#define SIR_DATA_IN_ERR 0x00000005
  565 +#define SIR_DATA_OUT_ERR 0x00000006
  566 +#define SIR_SCRIPT_ERROR 0x00000007
  567 +#define SIR_MSG_OUT_NO_CMD 0x00000008
  568 +#define SIR_MSG_OVER7 0x00000009
  569 +/* Fly interrupt */
  570 +#define INT_ON_FY 0x00000080
  571 +
  572 +/* Hardware errors are defined in scsi.h */
  573 +
  574 +#define SCSI_IDENTIFY 0xC0
  575 +
  576 +#ifndef TRUE
  577 +#define TRUE 1
  578 +#endif
  579 +#ifndef FALSE
  580 +#define FALSE 0
  581 +#endif
  582 +
  583 +#endif