Commit e9d6a20034788258bc5008dc2665aabe9ce28b1c
1 parent
2110eeaf0f
Exists in
v2017.01-smarct4x
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arm: socfpga: reset: Add EMAC reset functions
Add functions to reset the EMAC ethernet blocks. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
Showing 2 changed files with 20 additions and 0 deletions Side-by-side Diff
arch/arm/cpu/armv7/socfpga/reset_manager.c
| ... | ... | @@ -49,4 +49,21 @@ |
| 49 | 49 | { |
| 50 | 50 | writel(0, &reset_manager_base->per_mod_reset); |
| 51 | 51 | } |
| 52 | + | |
| 53 | +/* Change the reset state for EMAC 0 and EMAC 1 */ | |
| 54 | +void socfpga_emac_reset(int enable) | |
| 55 | +{ | |
| 56 | + const void *reset = &reset_manager_base->per_mod_reset; | |
| 57 | + | |
| 58 | + if (enable) { | |
| 59 | + setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB); | |
| 60 | + setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB); | |
| 61 | + } else { | |
| 62 | +#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS) | |
| 63 | + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB); | |
| 64 | +#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS) | |
| 65 | + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB); | |
| 66 | +#endif | |
| 67 | + } | |
| 68 | +} |
arch/arm/include/asm/arch-socfpga/reset_manager.h
| ... | ... | @@ -10,6 +10,7 @@ |
| 10 | 10 | void reset_cpu(ulong addr); |
| 11 | 11 | void reset_deassert_peripherals_handoff(void); |
| 12 | 12 | |
| 13 | +void socfpga_emac_reset(int enable); | |
| 13 | 14 | void socfpga_watchdog_reset(void); |
| 14 | 15 | |
| 15 | 16 | struct socfpga_reset_manager { |
| ... | ... | @@ -29,6 +30,8 @@ |
| 29 | 30 | #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 |
| 30 | 31 | #endif |
| 31 | 32 | |
| 33 | +#define RSTMGR_PERMODRST_EMAC0_LSB 0 | |
| 34 | +#define RSTMGR_PERMODRST_EMAC1_LSB 1 | |
| 32 | 35 | #define RSTMGR_PERMODRST_L4WD0_LSB 6 |
| 33 | 36 | |
| 34 | 37 | #endif /* _RESET_MANAGER_H_ */ |