mpc8308rdb: add support for Spansion SPI flash on header J8

The SPI pins are routed to header J8 for testing SPI functionality. A Spansion flash has been wired up and tested on this header. This patch breaks support for the second TSEC interface, since the GPIO pin used as a chip select is pinmuxed with some of the TSEC pins. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

mpc8308rdb: add support for Spansion SPI flash on header J8
The SPI pins are routed to header J8 for testing SPI functionality. A Spansion flash has been wired up and tested on this header. This patch breaks support for the second TSEC interface, since the GPIO pin used as a chip select is pinmuxed with some of the TSEC pins. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Ira W. Snyder · Kim Phillips
1 parent f138ca1373
Showing 2 changed files with 62 additions and 0 deletions Side-by-side Diff
board/freescale/mpc8308rdb/mpc8308rdb.c
include/configs/MPC8308RDB.h
@@ -24,6 +24,7 @@
 #include <common.h>
 #include <hwconfig.h>
 #include <i2c.h>
+#include <spi.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <pci.h>
@@ -36,6 +37,35 @@
  
 DECLARE_GLOBAL_DATA_PTR;
  
+/*
+ * The following are used to control the SPI chip selects for the SPI command.
+ */
+#ifdef CONFIG_MPC8XXX_SPI
+
+#define SPI_CS_MASK	0x00400000
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+	/* active low */
+	clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+	/* inactive high */
+	setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
+}
+#endif /* CONFIG_MPC8XXX_SPI */
+
 static u8 read_board_info(void)
 {
 	u8 val8;
@@ -109,6 +139,25 @@
 */
 int misc_init_r(void)
 {
+#ifdef CONFIG_MPC8XXX_SPI
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	sysconf83xx_t *sysconf = &immr->sysconf;
+
+	/*
+	 * Set proper bits in SICRH to allow SPI on header J8
+	 *
+	 * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
+	 * switch. The pinmux configuration does not have a fine enough
+	 * granularity to support both simultaneously.
+	 */
+	clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
+	puts("WARNING: SPI enabled, TSEC2 support is broken\n");
+
+	/* Set header J8 SPI chip select output, disabled */
+	setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
+	setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
+#endif
+
 #ifdef CONFIG_VSC7385_IMAGE
 	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
 		CONFIG_VSC7385_IMAGE_SIZE)) {
@@ -340,6 +340,19 @@
 #define CONFIG_SYS_I2C_OFFSET	0x3000
 #define CONFIG_SYS_I2C2_OFFSET	0x3100
  
+/*
+ * SPI on header J8
+ *
+ * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
+ * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
+ */
+#ifdef CONFIG_MPC8XXX_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_USE_SPIFLASH
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#endif
  
 /*
  * Board info - revision and where boot from
...	...	@@ -24,6 +24,7 @@
24	24	#include <common.h>
25	25	#include <hwconfig.h>
26	26	#include <i2c.h>
	27	+#include <spi.h>
27	28	#include <libfdt.h>
28	29	#include <fdt_support.h>
29	30	#include <pci.h>
...	...	@@ -36,6 +37,35 @@
36	37
37	38	DECLARE_GLOBAL_DATA_PTR;
38	39
	40	+/*
	41	+ * The following are used to control the SPI chip selects for the SPI command.
	42	+ */
	43	+#ifdef CONFIG_MPC8XXX_SPI
	44	+
	45	+#define SPI_CS_MASK 0x00400000
	46	+
	47	+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	48	+{
	49	+ return bus == 0 && cs == 0;
	50	+}
	51	+
	52	+void spi_cs_activate(struct spi_slave *slave)
	53	+{
	54	+ immap_t immr = (immap_t )CONFIG_SYS_IMMR;
	55	+
	56	+ /* active low */
	57	+ clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
	58	+}
	59	+
	60	+void spi_cs_deactivate(struct spi_slave *slave)
	61	+{
	62	+ immap_t immr = (immap_t )CONFIG_SYS_IMMR;
	63	+
	64	+ /* inactive high */
	65	+ setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
	66	+}
	67	+#endif /* CONFIG_MPC8XXX_SPI */
	68	+
39	69	static u8 read_board_info(void)
40	70	{
41	71	u8 val8;
...	...	@@ -109,6 +139,25 @@
109	139	*/
110	140	int misc_init_r(void)
111	141	{
	142	+#ifdef CONFIG_MPC8XXX_SPI
	143	+ immap_t immr = (immap_t )CONFIG_SYS_IMMR;
	144	+ sysconf83xx_t *sysconf = &immr->sysconf;
	145	+
	146	+ /*
	147	+ * Set proper bits in SICRH to allow SPI on header J8
	148	+ *
	149	+ * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
	150	+ * switch. The pinmux configuration does not have a fine enough
	151	+ * granularity to support both simultaneously.
	152	+ */
	153	+ clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
	154	+ puts("WARNING: SPI enabled, TSEC2 support is broken\n");
	155	+
	156	+ /* Set header J8 SPI chip select output, disabled */
	157	+ setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
	158	+ setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
	159	+#endif
	160	+
112	161	#ifdef CONFIG_VSC7385_IMAGE
113	162	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
114	163	CONFIG_VSC7385_IMAGE_SIZE)) {
...	...	@@ -340,6 +340,19 @@
340	340	#define CONFIG_SYS_I2C_OFFSET 0x3000
341	341	#define CONFIG_SYS_I2C2_OFFSET 0x3100
342	342
	343	+/*
	344	+ * SPI on header J8
	345	+ *
	346	+ * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
	347	+ * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
	348	+ */
	349	+#ifdef CONFIG_MPC8XXX_SPI
	350	+#define CONFIG_CMD_SPI
	351	+#define CONFIG_USE_SPIFLASH
	352	+#define CONFIG_SPI_FLASH
	353	+#define CONFIG_SPI_FLASH_SPANSION
	354	+#define CONFIG_CMD_SF
	355	+#endif
343	356
344	357	/*
345	358	* Board info - revision and where boot from