Commit ea339205a94706d8b9170bbd89e8c1373df9a92f
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Updated PCI mapping for esd CPCI2DP board.
Add support for error LED. Patch by Matthias Fuchs, 07 Nov 2005
Showing 3 changed files with 18 additions and 10 deletions Side-by-side Diff
CHANGELOG
| ... | ... | @@ -2,6 +2,10 @@ |
| 2 | 2 | Changes for U-Boot 1.1.4: |
| 3 | 3 | ====================================================================== |
| 4 | 4 | |
| 5 | +* Updated PCI mapping for esd CPCI2DP board. | |
| 6 | + Add support for error LED. | |
| 7 | + Patch by Matthias Fuchs, 07 Nov 2005 | |
| 8 | + | |
| 5 | 9 | * Fix MPC85xx PCI support (pci_register_hose() before pci config access) |
| 6 | 10 | Patch by Stefan Roese, 07 Nov 2005 |
| 7 | 11 |
board/esd/cpci2dp/cpci2dp.c
| ... | ... | @@ -31,14 +31,17 @@ |
| 31 | 31 | unsigned long cntrl0Reg; |
| 32 | 32 | |
| 33 | 33 | /* |
| 34 | - * Setup GPIO pins (CS4 as GPIO) | |
| 34 | + * Setup GPIO pins (CS4+CS7 as GPIO) | |
| 35 | 35 | */ |
| 36 | 36 | cntrl0Reg = mfdcr(cntrl0); |
| 37 | - mtdcr(cntrl0, cntrl0Reg | 0x00800000); | |
| 37 | + mtdcr(cntrl0, cntrl0Reg | 0x00900000); | |
| 38 | 38 | |
| 39 | - out32(GPIO0_OR, CFG_INTA_FAKE | CFG_EEPROM_WP); /* set output pins to high */ | |
| 40 | - out32(GPIO0_ODR, CFG_INTA_FAKE); /* INTA# is open drain */ | |
| 41 | - out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP); /* setup for output */ | |
| 39 | + /* set output pins to high */ | |
| 40 | + out32(GPIO0_OR, CFG_INTA_FAKE | CFG_EEPROM_WP | CFG_PB_LED); | |
| 41 | + /* INTA# is open drain */ | |
| 42 | + out32(GPIO0_ODR, CFG_INTA_FAKE); | |
| 43 | + /* setup for output */ | |
| 44 | + out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP); | |
| 42 | 45 | |
| 43 | 46 | /* |
| 44 | 47 | * IRQ 0-15 405GP internally generated; active high; level sensitive |
include/configs/CPCI2DP.h
| ... | ... | @@ -146,9 +146,9 @@ |
| 146 | 146 | #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ |
| 147 | 147 | #define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ |
| 148 | 148 | #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
| 149 | -#define CFG_PCI_PTM2LA 0xef600000 /* point to internal regs + PB0/1 */ | |
| 149 | +#define CFG_PCI_PTM2LA 0xef000000 /* point to internal regs + PB0/1 */ | |
| 150 | 150 | #define CFG_PCI_PTM2MS 0xff000001 /* 16MB, enable */ |
| 151 | -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
| 151 | +#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ | |
| 152 | 152 | |
| 153 | 153 | /*----------------------------------------------------------------------- |
| 154 | 154 | * Start addresses for the final memory configuration |
| 155 | 155 | |
| ... | ... | @@ -237,11 +237,11 @@ |
| 237 | 237 | |
| 238 | 238 | /* Memory Bank 2 (PB0) initialization */ |
| 239 | 239 | #define CFG_EBC_PB2AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */ |
| 240 | -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
| 240 | +#define CFG_EBC_PB2CR 0xEF018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
| 241 | 241 | |
| 242 | 242 | /* Memory Bank 3 (PB1) initialization */ |
| 243 | 243 | #define CFG_EBC_PB3AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */ |
| 244 | -#define CFG_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ | |
| 244 | +#define CFG_EBC_PB3CR 0xEF118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ | |
| 245 | 245 | |
| 246 | 246 | /*----------------------------------------------------------------------- |
| 247 | 247 | * Definitions for initial stack pointer and data area (in data cache) |
| ... | ... | @@ -258,6 +258,7 @@ |
| 258 | 258 | * GPIO definitions |
| 259 | 259 | */ |
| 260 | 260 | #define CFG_EEPROM_WP (0x80000000 >> 13) /* GPIO13 */ |
| 261 | +#define CFG_PB_LED (0x80000000 >> 16) /* GPIO16 */ | |
| 261 | 262 | #define CFG_INTA_FAKE (0x80000000 >> 23) /* GPIO23 */ |
| 262 | 263 | |
| 263 | 264 | /* |