Eric Lee / smarc-uboot

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Commit ea909b7604306a400ee3abf57e2fa7b2dde5dde1

Authored by wdenk
1 parent b2184c314d
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

* Added support for both PCMCIA slots (at the same time!) on MPC8xx 

* Patch by Rod Boyce, 21 Nov 2002:
  fix PCMCIA on MBX8xx board

* Patch by Pierre Aubert , 21 Nov 2002
  Add CFG_CPM_POST_WORD_ADDR to make the offset of the
  bootmode word in DPRAM configurable

Showing 18 changed files with 161 additions and 194 deletions Side-by-side Diff

... ... @@ -2,6 +2,15 @@
2 2 Changes since for U-Boot 0.1.0:
3 3 ======================================================================
4 4  
  5 +* Added support for both PCMCIA slots (at the same time!) on MPC8xx
  6 +
  7 +* Patch by Rod Boyce, 21 Nov 2002:
  8 + fix PCMCIA on MBX8xx board
  9 +
  10 +* Patch by Pierre Aubert , 21 Nov 2002
  11 + Add CFG_CPM_POST_WORD_ADDR to make the offset of the
  12 + bootmode word in DPRAM configurable
  13 +
5 14 * Patch by Daniel Engström, 18 Nov 2002:
6 15 Fixes for x86 port (mostly strings issues)
7 16  
... ... @@ -1653,6 +1653,12 @@
1653 1653 wrong setting might damage your board. Read
1654 1654 doc/README.MBX before setting this variable!
1655 1655  
  1656 +- CFG_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only)
  1657 + Offset of the bootmode word in DPRAM used by post
  1658 + (Power On Self Tests). This definition overrides
  1659 + #define'd default value in commproc.h resp.
  1660 + cpm_8260.h.
  1661 +
1656 1662 Building the Software:
1657 1663 ======================
1658 1664  
board/sc520_cdp/flash.c
Diff comments   View file @ ea909b7
... ... @@ -171,7 +171,7 @@
171 171 int flash_erase (flash_info_t *info, int s_first, int s_last)
172 172 {
173 173 ulong result;
174   - int iflag, cflag, prot, sect;
  174 + int iflag, prot, sect;
175 175 int rc = ERR_OK;
176 176 int chip1, chip2;
177 177  
board/sc520_cdp/sc520_cdp.c
Diff comments   View file @ ea909b7
... ... @@ -285,5 +285,7 @@
285 285 minor |= ali512x_cio_in(20)?1:0;
286 286  
287 287 printf("AMD SC520 CDP revision %d.%d\n", major, minor);
  288 +
  289 + return 0;
288 290 }
... ... @@ -80,7 +80,7 @@
80 80 static void print_funcid (int func);
81 81 static void print_fixed (volatile uchar *p);
82 82 static int identify (volatile uchar *p);
83   -static int check_ide_device (void);
  83 +static int check_ide_device (int slot);
84 84 #endif /* CONFIG_IDE_8xx_PCCARD */
85 85  
86 86 static u_int m8xx_get_graycode(u_int size);
... ... @@ -139,6 +139,8 @@
139 139 int i;
140 140 u_long reg, base;
141 141 pcmcia_win_t *win;
  142 + u_int slotbit;
  143 + u_int rc, slot;
142 144  
143 145 debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
144 146  
145 147  
146 148  
147 149  
148 150  
149 151  
150 152  
151 153  
... ... @@ -152,36 +154,42 @@
152 154 return (1);
153 155 }
154 156  
  157 + slotbit = PCMCIA_SLOT_x;
155 158 for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
156 159 win->br = base;
157 160  
  161 +#if (PCMCIA_SOCKETS_NO == 2)
  162 + if (i == 4) /* Another slot starting from win 4 */
  163 + slotbit = (slotbit ? PCMCIA_PSLOT_A : PCMCIA_PSLOT_B);
  164 +#endif
158 165 switch (i) {
159 166 #ifdef CONFIG_IDE_8xx_PCCARD
  167 + case 4:
160 168 case 0: { /* map attribute memory */
161 169 win->or = ( PCMCIA_BSIZE_64M
162 170 | PCMCIA_PPS_8
163 171 | PCMCIA_PRS_ATTR
164   - | PCMCIA_SLOT_x
  172 + | slotbit
165 173 | PCMCIA_PV
166 174 | CFG_PCMCIA_TIMING );
167 175 break;
168 176 }
169   -
  177 + case 5:
170 178 case 1: { /* map I/O window for data reg */
171 179 win->or = ( PCMCIA_BSIZE_1K
172 180 | PCMCIA_PPS_16
173 181 | PCMCIA_PRS_IO
174   - | PCMCIA_SLOT_x
  182 + | slotbit
175 183 | PCMCIA_PV
176 184 | CFG_PCMCIA_TIMING );
177 185 break;
178 186 }
179   -
  187 + case 6:
180 188 case 2: { /* map I/O window for command/ctrl reg block */
181 189 win->or = ( PCMCIA_BSIZE_1K
182 190 | PCMCIA_PPS_8
183 191 | PCMCIA_PRS_IO
184   - | PCMCIA_SLOT_x
  192 + | slotbit
185 193 | PCMCIA_PV
186 194 | CFG_PCMCIA_TIMING );
187 195 break;
188 196  
189 197  
... ... @@ -198,19 +206,21 @@
198 206 ++win;
199 207 }
200 208  
201   - /* turn off voltage */
202   - if (voltage_set(_slot_, 0, 0))
203   - return (1);
204   -
205   - /* Enable external hardware */
206   - if (hardware_enable(_slot_))
207   - return (1);
208   -
  209 + for (i = 0, rc = 0, slot = _slot_; i < PCMCIA_SOCKETS_NO; i++, slot = !slot) {
  210 + /* turn off voltage */
  211 + if ((rc = voltage_set(slot, 0, 0)))
  212 + continue;
  213 +
  214 + /* Enable external hardware */
  215 + if ((rc = hardware_enable(slot)))
  216 + continue;
  217 +
209 218 #ifdef CONFIG_IDE_8xx_PCCARD
210   - if (check_ide_device())
211   - return (1);
  219 + if ((rc = check_ide_device(i)))
  220 + continue;
212 221 #endif
213   - return (0);
  222 + }
  223 + return (rc);
214 224 }
215 225  
216 226 /* ------------------------------------------------------------------------- */
217 227  
... ... @@ -258,11 +268,11 @@
258 268 #define MAX_TUPEL_SZ 512
259 269 #define MAX_FEATURES 4
260 270  
261   -static int check_ide_device (void)
  271 +static int check_ide_device (int slot)
262 272 {
263 273 volatile uchar *ident = NULL;
264 274 volatile uchar *feature_p[MAX_FEATURES];
265   - volatile uchar *p, *start;
  275 + volatile uchar *p, *start, *addr;
266 276 int n_features = 0;
267 277 uchar func_id = ~0;
268 278 uchar code, len;
269 279  
... ... @@ -270,9 +280,11 @@
270 280 int found = 0;
271 281 int i;
272 282  
273   - debug ("PCMCIA MEM: %08X\n", CFG_PCMCIA_MEM_ADDR);
  283 + addr = (volatile uchar *)(CFG_PCMCIA_MEM_ADDR +
  284 + CFG_PCMCIA_MEM_SIZE * (slot * 4));
  285 + debug ("PCMCIA MEM: %08X\n", addr);
274 286  
275   - start = p = (volatile uchar *) CFG_PCMCIA_MEM_ADDR;
  287 + start = p = (volatile uchar *) addr;
276 288  
277 289 while ((p - start) < MAX_TUPEL_SZ) {
278 290  
... ... @@ -336,7 +348,7 @@
336 348 }
337 349  
338 350 /* set I/O area in config reg -> only valid for ARGOSY D5!!! */
339   - *((uchar *)(CFG_PCMCIA_MEM_ADDR + config_base)) = 1;
  351 + *((uchar *)(addr + config_base)) = 1;
340 352  
341 353 return (0);
342 354 }
... ... @@ -564,7 +576,7 @@
564 576 debug ("[%d] %s: PIPR(%p)=0x%x\n",
565 577 __LINE__,__FUNCTION__,
566 578 &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
567   - if (pcmp->pcmc_pipr & 0x00001800) {
  579 + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
568 580 printf (" No Card found\n");
569 581 return (1);
570 582 }
... ... @@ -791,7 +803,7 @@
791 803 debug ("[%d] %s: PIPR(%p)=0x%x\n",
792 804 __LINE__,__FUNCTION__,
793 805 &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
794   - if (pcmp->pcmc_pipr & 0x00001800) {
  806 + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
795 807 printf (" No Card found\n");
796 808 return (1);
797 809 }
... ... @@ -1096,7 +1108,7 @@
1096 1108 debug ("[%d] %s: PIPR(%p)=0x%x\n",
1097 1109 __LINE__,__FUNCTION__,
1098 1110 &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
1099   - if (pcmp->pcmc_pipr & 0x00001800) {
  1111 + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
1100 1112 printf (" No Card found\n");
1101 1113 return (1);
1102 1114 }
... ... @@ -1366,7 +1378,7 @@
1366 1378 debug ("[%d] %s: PIPR(%p)=0x%x\n",
1367 1379 __LINE__,__FUNCTION__,
1368 1380 &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
1369   - if (pcmp->pcmc_pipr & 0x00001800) {
  1381 + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
1370 1382 printf (" No Card found\n");
1371 1383 return (1);
1372 1384 }
... ... @@ -1694,11 +1706,11 @@
1694 1706 /*
1695 1707 * Make sure there is a card in the slot, then configure the interface.
1696 1708 */
1697   - udelay (10000);
1698   - debug ("[%d] %s: PIPR(%p)=0x%x\n", __LINE__, __FUNCTION__,
1699   - &(pcmp->pcmc_pipr), pcmp->pcmc_pipr);
1700   -
1701   - if (pcmp->pcmc_pipr & 0x00001800) {
  1709 + udelay(10000);
  1710 + debug ("[%d] %s: PIPR(%p)=0x%x\n",
  1711 + __LINE__,__FUNCTION__,
  1712 + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
  1713 + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
1702 1714 printf (" No Card found\n");
1703 1715 return (1);
1704 1716 }
... ... @@ -1816,7 +1828,7 @@
1816 1828 debug ("[%d] %s: PIPR(%p)=0x%x\n",
1817 1829 __LINE__,__FUNCTION__,
1818 1830 &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
1819   - if (pcmp->pcmc_pipr & 0x00001800) {
  1831 + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
1820 1832 printf (" No Card found\n");
1821 1833 return (1);
1822 1834 }
1823 1835  
1824 1836  
1825 1837  
1826 1838  
... ... @@ -2008,32 +2020,33 @@
2008 2020 sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
2009 2021  
2010 2022 /* clear interrupt state, and disable interrupts */
2011   - pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
2012   - pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
  2023 + pcmp->pcmc_pscr = PCMCIA_MASK(slot);
  2024 + pcmp->pcmc_per &= ~PCMCIA_MASK(slot);
2013 2025  
2014 2026 /* disable interrupts & DMA */
2015   - PCMCIA_PGCRX(_slot_) = 0;
  2027 + PCMCIA_PGCRX(slot) = 0;
2016 2028  
2017 2029 /*
2018 2030 * Disable PCMCIA buffers (isolate the interface)
2019 2031 * and assert RESET signal
2020 2032 */
2021 2033 debug ("Disable PCMCIA buffers and assert RESET\n");
2022   - reg = PCMCIA_PGCRX(_slot_);
  2034 + reg = PCMCIA_PGCRX(slot);
2023 2035 reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
2024 2036 reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
2025   - PCMCIA_PGCRX(_slot_) = reg;
2026   - udelay(500);
  2037 + PCMCIA_PGCRX(slot) = reg;
  2038 + udelay(2500);
2027 2039  
2028 2040 /*
2029 2041 * Configure Port B pins for
2030 2042 * 3 Volts enable
2031 2043 */
2032   - cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3;
2033   - cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
2034   - /* remove all power */
2035   - cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */
2036   -
  2044 + if (slot) { /* Slot A is built-in */
  2045 + cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3;
  2046 + cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
  2047 + /* remove all power */
  2048 + cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */
  2049 + }
2037 2050 /*
2038 2051 * Make sure there is a card in the slot, then configure the interface.
2039 2052 */
... ... @@ -2041,7 +2054,7 @@
2041 2054 debug ("[%d] %s: PIPR(%p)=0x%x\n",
2042 2055 __LINE__,__FUNCTION__,
2043 2056 &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
2044   - if (pcmp->pcmc_pipr & 0x00001800) {
  2057 + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
2045 2058 printf (" No Card found\n");
2046 2059 return (1);
2047 2060 }
... ... @@ -2049,6 +2062,7 @@
2049 2062 /*
2050 2063 * Power On.
2051 2064 */
  2065 + printf("\n Slot %c:", 'A' + slot);
2052 2066 mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
2053 2067 reg = pcmp->pcmc_pipr;
2054 2068 debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
... ... @@ -2058,7 +2072,8 @@
2058 2072 if ((reg & mask) == mask) {
2059 2073 puts (" 5.0V card found: NOT SUPPORTED !!!\n");
2060 2074 } else {
2061   - cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3;
  2075 + if(slot)
  2076 + cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3;
2062 2077 puts (" 3.3V card found: ");
2063 2078 }
2064 2079 #if 0
2065 2080  
... ... @@ -2068,10 +2083,10 @@
2068 2083 udelay(500000);
2069 2084 #endif
2070 2085 debug ("Enable PCMCIA buffers and stop RESET\n");
2071   - reg = PCMCIA_PGCRX(_slot_);
  2086 + reg = PCMCIA_PGCRX(slot);
2072 2087 reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
2073 2088 reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
2074   - PCMCIA_PGCRX(_slot_) = reg;
  2089 + PCMCIA_PGCRX(slot) = reg;
2075 2090  
2076 2091 udelay(250000); /* some cards need >150 ms to come up :-( */
2077 2092  
2078 2093  
2079 2094  
2080 2095  
... ... @@ -2097,16 +2112,17 @@
2097 2112 cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
2098 2113  
2099 2114 /* remove all power */
2100   - cp->cp_pbdat |= DDC4000_PCMCIA_B_3V3;
  2115 + if (slot)
  2116 + cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3;
2101 2117  
2102 2118 /* Configure PCMCIA General Control Register */
2103   - PCMCIA_PGCRX(_slot_) = 0;
  2119 + PCMCIA_PGCRX(slot) = 0;
2104 2120  
2105 2121 debug ("Disable PCMCIA buffers and assert RESET\n");
2106   - reg = PCMCIA_PGCRX(_slot_);
  2122 + reg = PCMCIA_PGCRX(slot);
2107 2123 reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
2108 2124 reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
2109   - PCMCIA_PGCRX(_slot_) = reg;
  2125 + PCMCIA_PGCRX(slot) = reg;
2110 2126  
2111 2127 udelay(10000);
2112 2128  
... ... @@ -2128,6 +2144,9 @@
2128 2144 " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
2129 2145 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
2130 2146  
  2147 + if (!slot) /* Slot A is not configurable */
  2148 + return 0;
  2149 +
2131 2150 immap = (immap_t *)CFG_IMMR;
2132 2151 pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
2133 2152 cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
2134 2153  
... ... @@ -2137,10 +2156,10 @@
2137 2156 * and assert RESET signal
2138 2157 */
2139 2158 debug ("Disable PCMCIA buffers and assert RESET\n");
2140   - reg = PCMCIA_PGCRX(_slot_);
  2159 + reg = PCMCIA_PGCRX(slot);
2141 2160 reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
2142 2161 reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
2143   - PCMCIA_PGCRX(_slot_) = reg;
  2162 + PCMCIA_PGCRX(slot) = reg;
2144 2163 udelay(500);
2145 2164  
2146 2165 debug ("PCMCIA power OFF\n");
2147 2166  
2148 2167  
2149 2168  
... ... @@ -2166,21 +2185,21 @@
2166 2185 puts("PCMCIA: vcc not supported");
2167 2186 break;
2168 2187 }
2169   -
  2188 + udelay(10000);
2170 2189 /* Checking supported voltages */
2171 2190  
2172 2191 debug ("PIPR: 0x%x --> %s\n",
2173 2192 pcmp->pcmc_pipr,
2174   - (pcmp->pcmc_pipr & 0x00008000)
  2193 + (pcmp->pcmc_pipr & (0x80000000 >> (slot << 4)))
2175 2194 ? "only 5 V --> NOT SUPPORTED"
2176 2195 : "can do 3.3V");
2177 2196  
2178 2197  
2179 2198 debug ("Enable PCMCIA buffers and stop RESET\n");
2180   - reg = PCMCIA_PGCRX(_slot_);
  2199 + reg = PCMCIA_PGCRX(slot);
2181 2200 reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
2182 2201 reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
2183   - PCMCIA_PGCRX(_slot_) = reg;
  2202 + PCMCIA_PGCRX(slot) = reg;
2184 2203 udelay(500);
2185 2204  
2186 2205 debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
... ... @@ -131,10 +131,14 @@
131 131 ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc)
132 132 BFD_ROOT_DIR = /usr/local/tools
133 133 else
  134 +ifeq ($(HOSTARCH),$(ARCH))
  135 +# native
  136 +BFD_ROOT_DIR = /usr
  137 +else
134 138 #BFD_ROOT_DIR = /LinuxPPC/CDK # Linux/i386
135 139 #BFD_ROOT_DIR = /usr/pkg/cross # NetBSD/i386
136   -#BFD_ROOT_DIR = /usr # native
137 140 BFD_ROOT_DIR = /opt/powerpc
  141 +endif
138 142 endif
139 143  
140 144 #########################################################################
drivers/pci_indirect.c
Diff comments   View file @ ea909b7
... ... @@ -12,6 +12,7 @@
12 12 #include <common.h>
13 13  
14 14 #ifdef CONFIG_PCI
  15 +#ifndef __I386__
15 16  
16 17 #include <asm/processor.h>
17 18 #include <asm/io.h>
... ... @@ -71,5 +72,6 @@
71 72 hose->cfg_data = (unsigned char *) cfg_data;
72 73 }
73 74  
  75 +#endif
74 76 #endif
include/asm-ppc/cpm_8260.h
Diff comments   View file @ ea909b7
... ... @@ -136,7 +136,11 @@
136 136  
137 137 /* Parameter RAM offsets from the base.
138 138 */
  139 +#ifndef CFG_CPM_POST_WORD_ADDR
139 140 #define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */
  141 +#else
  142 +#define CPM_POST_WORD_ADDR CFG_CPM_POST_WORD_ADDR
  143 +#endif
140 144 #define PROFF_SCC1 ((uint)0x8000)
141 145 #define PROFF_SCC2 ((uint)0x8100)
142 146 #define PROFF_SCC3 ((uint)0x8200)
... ... @@ -77,7 +77,11 @@
77 77  
78 78 #endif
79 79  
  80 +#ifndef CFG_CPM_POST_WORD_ADDR
80 81 #define CPM_POST_WORD_ADDR 0x07FC
  82 +#else
  83 +#define CPM_POST_WORD_ADDR CFG_CPM_POST_WORD_ADDR
  84 +#endif
81 85  
82 86 #define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
83 87  
include/configs/KUP4K.h
Diff comments   View file @ ea909b7
... ... @@ -270,7 +270,8 @@
270 270 *
271 271 */
272 272  
273   -#define CONFIG_PCMCIA_SLOT_B 1 /* KUP4K use SLOT_B */
  273 +/* KUP4K use both slots, SLOT_A as "primary". */
  274 +#define CONFIG_PCMCIA_SLOT_A 1
274 275  
275 276 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
276 277 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
... ... @@ -281,6 +282,8 @@
281 282 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
282 283 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
283 284  
  285 +#define PCMCIA_SOCKETS_NO 2
  286 +#define PCMCIA_MEM_WIN_NO 8
284 287 /*-----------------------------------------------------------------------
285 288 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
286 289 *-----------------------------------------------------------------------
287 290  
... ... @@ -292,10 +295,12 @@
292 295 #undef CONFIG_IDE_LED /* LED for ide not supported */
293 296 #undef CONFIG_IDE_RESET /* reset for ide not supported */
294 297  
295   -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
296   -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
  298 +#define CFG_IDE_MAXBUS 2
  299 +#define CFG_IDE_MAXDEVICE 4
297 300  
298 301 #define CFG_ATA_IDE0_OFFSET 0x0000
  302 +
  303 +#define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE)
299 304  
300 305 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
301 306  
include/configs/lwmon.h
Diff comments   View file @ ea909b7
... ... @@ -67,15 +67,16 @@
67 67 #undef CONFIG_BOOTARGS
68 68  
69 69 /* POST support */
70   -#define CONFIG_POST (CFG_POST_CACHE | \
  70 +#define CONFIG_POST (CFG_POST_CACHE | \
71 71 CFG_POST_WATCHDOG | \
72   - CFG_POST_RTC | \
73   - CFG_POST_MEMORY | \
74   - CFG_POST_CPU | \
75   - CFG_POST_UART | \
76   - CFG_POST_ETHER | \
77   - CFG_POST_SPI | \
78   - CFG_POST_USB | \
  72 + CFG_POST_RTC | \
  73 + CFG_POST_MEMORY | \
  74 + CFG_POST_CPU | \
  75 + CFG_POST_UART | \
  76 + CFG_POST_ETHER | \
  77 + CFG_POST_I2C | \
  78 + CFG_POST_SPI | \
  79 + CFG_POST_USB | \
79 80 CFG_POST_SPR)
80 81  
81 82 #define CONFIG_BOOTCOMMAND "run flash_self"
82 83  
... ... @@ -116,16 +117,11 @@
116 117 #undef CONFIG_STATUS_LED /* Status LED disabled */
117 118  
118 119 /* enable I2C and select the hardware/software driver */
119   -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
120   -#undef CONFIG_SOFT_I2C /* I2C bit-banged */
  120 +#undef CONFIG_HARD_I2C /* I2C with hardware support */
  121 +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
121 122  
122   -#ifdef CONFIG_HARD_I2C
123   -/*
124   - * Hardware (CPM) I2C driver configuration
125   - */
126   -# define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
127   -# define CFG_I2C_SLAVE 0xFE
128   -#endif /* CONFIG_HARD_I2C */
  123 +#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
  124 +#define CFG_I2C_SLAVE 0xFE
129 125  
130 126 #ifdef CONFIG_SOFT_I2C
131 127 /*
include/mpc75x.h
View file @ ea909b7
1   -/*
2   - * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3   - * Andreas Heppel <aheppel@sysgo.de>
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -
24   -/*
25   - * mpc75x.h
26   - *
27   - * MPC75x/MPC74xx specific definitions
28   - */
29   -
30   -#ifndef __MPC75X_H__
31   -#define __MPC75X_H__
32   -
33   -/*----------------------------------------------------------------
34   - * Exception offsets (PowerPC standard)
35   - */
36   -#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */
37   -
38   -/*----------------------------------------------------------------
39   - * l2cr values
40   - */
41   -#define l2cr 1017
42   -
43   -#define L2CR_L2E 0x80000000 /* bit 0 - enable */
44   -#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
45   -#define L2CR_L2SIZ_2M 0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */
46   -#define L2CR_L2SIZ_1M 0x30000000 /* ... 1MB */
47   -#define L2CR_L2SIZ_HM 0x20000000 /* ... 512K */
48   -#define L2CR_L2SIZ_QM 0x10000000 /* ... 256k */
49   -#define L2CR_L2CLK_1 0x02000000 /* bits 4-6 clock ratio div 1 */
50   -#define L2CR_L2CLK_1_5 0x04000000 /* bits 4-6 clock ratio div 1.5 */
51   -#define L2CR_L2CLK_2 0x08000000 /* bits 4-6 clock ratio div 2 */
52   -#define L2CR_L2CLK_2_5 0x0a000000 /* bits 4-6 clock ratio div 2.5 */
53   -#define L2CR_L2CLK_3 0x0c000000 /* bits 4-6 clock ratio div 3 */
54   -#define L2CR_L2CLK_3_5 0x06000000 /* bits 4-6 clock ratio div 3.5 */
55   -#define L2CR_L2CLK_4 0x0e000000 /* bits 4-6 clock ratio div 4 */
56   -#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */
57   -#define L2CR_DO 0x00400000 /* bit 9 - enable caching of instr. in L2 */
58   -#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
59   -#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
60   -#define L2CR_L2WT 0x00080000 /* bit 12 - l2 write-through */
61   -#define L2CR_TS 0x00040000 /* bit 13 - test support on */
62   -#define L2CR_TS_OFF -L2CR_TS /* bit 13 - test support off */
63   -#define L2CR_L2OH_5 0x00000000 /* bits 14-15 - output hold time = short */
64   -#define L2CR_L2OH_1 0x00010000 /* bits 14-15 - output hold time = medium */
65   -#define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */
66   -#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
67   -
68   -/*----------------------------------------------------------------
69   - * BAT settings. Look in config_<BOARD>.h for the actual setup
70   - */
71   -
72   -#define BATU_BL_128K 0x00000000
73   -#define BATU_BL_256K 0x00000004
74   -#define BATU_BL_512K 0x0000000c
75   -#define BATU_BL_1M 0x0000001c
76   -#define BATU_BL_2M 0x0000003c
77   -#define BATU_BL_4M 0x0000007c
78   -#define BATU_BL_8M 0x000000fc
79   -#define BATU_BL_16M 0x000001fc
80   -#define BATU_BL_32M 0x000003fc
81   -#define BATU_BL_64M 0x000007fc
82   -#define BATU_BL_128M 0x00000ffc
83   -#define BATU_BL_256M 0x00001ffc
84   -
85   -#define BATU_VS 0x00000002
86   -#define BATU_VP 0x00000001
87   -#define BATU_INVALID 0x00000000
88   -
89   -#define BATL_WRITETHROUGH 0x00000080
90   -#define BATL_CACHEINHIBIT 0x00000040
91   -#define BATL_COHERENT 0x00000020
92   -#define BATL_GUARDED 0x00000010
93   -
94   -#define BATL_NO_ACCESS 0x00000000
95   -#define BATL_RO 0x00000001
96   -#define BATL_RW 0x00000002
97   -
98   -#endif /* __MPC75X_H__ */
... ... @@ -76,8 +76,12 @@
76 76 #error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
77 77 #endif
78 78  
  79 +#ifndef PCMCIA_SOCKETS_NO
79 80 #define PCMCIA_SOCKETS_NO 1
  81 +#endif
  82 +#ifndef PCMCIA_MEM_WIN_NO
80 83 #define PCMCIA_MEM_WIN_NO 4
  84 +#endif
81 85 #define PCMCIA_IO_WIN_NO 2
82 86  
83 87 /* define _slot_ to be able to optimize macros */
lib_i386/i386_linux.c
Diff comments   View file @ ea909b7
... ... @@ -47,7 +47,7 @@
47 47 void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
48 48 ulong addr, ulong *len_ptr, int verify)
49 49 {
50   - ulong base_ptr;
  50 + void *base_ptr;
51 51  
52 52 ulong len = 0, checksum;
53 53 ulong initrd_start, initrd_end;
... ... @@ -150,7 +150,7 @@
150 150 initrd_end = 0;
151 151 }
152 152  
153   - base_ptr = load_zimage(addr + sizeof(image_header_t), ntohl(hdr->ih_size),
  153 + base_ptr = load_zimage((void*)addr + sizeof(image_header_t), ntohl(hdr->ih_size),
154 154 initrd_start, initrd_end-initrd_start, 0);
155 155  
156 156 if (NULL == base_ptr) {
lib_i386/pci_type1.c
Diff comments   View file @ ea909b7
... ... @@ -17,16 +17,16 @@
17 17 #include <asm/io.h>
18 18 #include <pci.h>
19 19  
20   -#define cfg_read(val, addr, type, op) *val = op((type)(addr))
21   -#define cfg_write(val, addr, type, op) op((val), (type *)(addr))
  20 +#define cfg_read(val, addr, op) *val = op((int)(addr))
  21 +#define cfg_write(val, addr, op) op((val), (int)(addr))
22 22  
23 23 #define TYPE1_PCI_OP(rw, size, type, op, mask) \
24 24 static int \
25 25 type1_##rw##_config_##size(struct pci_controller *hose, \
26 26 pci_dev_t dev, int offset, type val) \
27 27 { \
28   - outl(dev | (offset & 0xfc) | 0x80000000, hose->cfg_addr); \
29   - cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
  28 + outl(dev | (offset & 0xfc) | 0x80000000, (int)hose->cfg_addr); \
  29 + cfg_##rw(val, hose->cfg_data + (offset & mask), op); \
30 30 return 0; \
31 31 }
32 32  
... ... @@ -24,6 +24,7 @@
24 24 #include <common.h>
25 25 #include <asm/io.h>
26 26 #include <asm/ptrace.h>
  27 +#include <asm/realmode.h>
27 28  
28 29  
29 30 #define REALMODE_BASE ((char*)0x7c0)
30 31  
31 32  
... ... @@ -44,16 +45,16 @@
44 45 /* copy the realmode switch code */
45 46 if (i386boot_realmode_size > (REALMODE_MAILBOX-REALMODE_BASE)) {
46 47 printf("realmode switch too large (%ld bytes, max is %d)\n",
47   - i386boot_realmode_size, (REALMODE_MAILBOX-REALMODE_BASE));
  48 + i386boot_realmode_size, (int)(REALMODE_MAILBOX-REALMODE_BASE));
48 49 return -1;
49 50 }
50 51  
51   - memcpy(REALMODE_BASE, i386boot_realmode, i386boot_realmode_size);
  52 + memcpy(REALMODE_BASE, (void*)i386boot_realmode, i386boot_realmode_size);
52 53  
53 54  
54 55 in->eip = off;
55 56 in->xcs = seg;
56   - if (3>in->esp & 0xffff) {
  57 + if (3>(in->esp & 0xffff)) {
57 58 printf("Warning: entering realmode with sp < 4 will fail\n");
58 59 }
59 60  
... ... @@ -78,6 +78,7 @@
78 78 int ic = icache_status ();
79 79 int ret = 0;
80 80  
  81 + WATCHDOG_RESET();
81 82 if (ic)
82 83 icache_disable ();
83 84  
84 85  
85 86  
... ... @@ -89,15 +90,16 @@
89 90 ret = cpu_post_test_two ();
90 91 if (ret == 0)
91 92 ret = cpu_post_test_twox ();
  93 + WATCHDOG_RESET();
92 94 if (ret == 0)
93 95 ret = cpu_post_test_three ();
94 96 if (ret == 0)
95 97 ret = cpu_post_test_threex ();
96 98 if (ret == 0)
97 99 ret = cpu_post_test_threei ();
98   - WATCHDOG_RESET();
99 100 if (ret == 0)
100 101 ret = cpu_post_test_andi ();
  102 + WATCHDOG_RESET();
101 103 if (ret == 0)
102 104 ret = cpu_post_test_srawi ();
103 105 if (ret == 0)
104 106  
105 107  
106 108  
107 109  
... ... @@ -106,24 +108,28 @@
106 108 ret = cpu_post_test_rlwinm ();
107 109 if (ret == 0)
108 110 ret = cpu_post_test_rlwimi ();
  111 + WATCHDOG_RESET();
109 112 if (ret == 0)
110 113 ret = cpu_post_test_store ();
111 114 if (ret == 0)
112 115 ret = cpu_post_test_load ();
113   - WATCHDOG_RESET();
114 116 if (ret == 0)
115 117 ret = cpu_post_test_cr ();
116 118 if (ret == 0)
117 119 ret = cpu_post_test_b ();
  120 + WATCHDOG_RESET();
118 121 if (ret == 0)
119 122 ret = cpu_post_test_multi ();
120 123 if (ret == 0)
121 124 ret = cpu_post_test_string ();
122 125 if (ret == 0)
123 126 ret = cpu_post_test_complex ();
  127 + WATCHDOG_RESET();
124 128  
125 129 if (ic)
126 130 icache_enable ();
  131 +
  132 + WATCHDOG_RESET();
127 133  
128 134 return ret;
129 135 }
... ... @@ -193,18 +193,21 @@
193 193 (flags & test_flags[last] & POST_ALWAYS) &&
194 194 (flags & test_flags[last] & POST_MEM)) {
195 195  
196   - post_run_single (post_list + last, test_flags[last],
197   - flags | POST_REBOOT, last);
  196 + post_run_single (post_list + last,
  197 + test_flags[last],
  198 + flags | POST_REBOOT, last);
198 199  
199 200 for (i = last + 1; i < post_list_size; i++) {
200   - post_run_single (post_list + i, test_flags[i],
201   - flags, i);
  201 + post_run_single (post_list + i,
  202 + test_flags[i],
  203 + flags, i);
202 204 }
203 205 }
204 206 } else {
205 207 for (i = 0; i < post_list_size; i++) {
206   - post_run_single (post_list + i, test_flags[i], flags,
207   - i);
  208 + post_run_single (post_list + i,
  209 + test_flags[i],
  210 + flags, i);
208 211 }
209 212 }
210 213