Eric Lee / smarc-uboot

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Commit eaae4ee2bd349797a69f74240abd8329e18d5dbd

Authored by Marek Vasut
Committed by Marek Vasut
1 parent 72c2f4acd7
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

sh: r2dplus: Switch to DM PCI driver 

Add DT entry for the DM PCI driver, update board configs
and drop ad-hoc board init code for the PCI bus. Instead,
let the DM PCI driver initialize and operate the hardware.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Showing 4 changed files with 16 additions and 20 deletions Side-by-side Diff

arch/sh/dts/sh7751-r2dplus.dts
Diff comments   View file @ eaae4ee
... ... @@ -9,5 +9,19 @@
9 9 / {
10 10 model = "R2D";
11 11 compatible = "renesas,r2d", "renesas,sh7751";
  12 +
  13 + pci@fe200000 {
  14 + compatible = "renesas,pci-sh7751";
  15 + device_type = "pci";
  16 + reg = <0 0xfe200000 0 0x1000>;
  17 + status = "okay";
  18 +
  19 + bus-range = <0 0>;
  20 + #address-cells = <3>;
  21 + #size-cells = <2>;
  22 + #interrupt-cells = <1>;
  23 + ranges = <0x01000000 0 0xfe240000 0 0xfe240000 0 0x00040000
  24 + 0x02000000 0 0xfd000000 0 0xfd000000 0 0x01000000>;
  25 + };
12 26 };
board/renesas/r2dplus/r2dplus.c
Diff comments   View file @ eaae4ee
... ... @@ -9,7 +9,6 @@
9 9 #include <netdev.h>
10 10 #include <asm/processor.h>
11 11 #include <asm/io.h>
12   -#include <asm/pci.h>
13 12  
14 13 int checkboard(void)
15 14 {
... ... @@ -43,12 +42,6 @@
43 42 outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */
44 43 outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */
45 44 }
46   -}
47   -
48   -static struct pci_controller hose;
49   -void pci_init_board(void)
50   -{
51   - pci_sh7751_init(&hose);
52 45 }
53 46  
54 47 int board_eth_init(bd_t *bis)
configs/r2dplus_defconfig
Diff comments   View file @ eaae4ee
... ... @@ -25,6 +25,8 @@
25 25 CONFIG_SYS_FLASH_CFI=y
26 26 CONFIG_RTL8139=y
27 27 CONFIG_PCI=y
  28 +CONFIG_DM_PCI=y
  29 +CONFIG_DM_PCI_COMPAT=y
28 30 CONFIG_SCIF_CONSOLE=y
29 31 CONFIG_USE_PRIVATE_LIBGCC=y
include/configs/r2dplus.h
Diff comments   View file @ eaae4ee
... ... @@ -64,20 +64,7 @@
64 64 /*
65 65 * SuperH PCI Bridge Configration
66 66 */
67   -#define CONFIG_SH4_PCI
68 67 #define CONFIG_SH7751_PCI
69   -#define CONFIG_PCI_SCAN_SHOW 1
70   -#define __mem_pci
71   -
72   -#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
73   -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
74   -#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
75   -#define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
76   -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
77   -#define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
78   -#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
79   -#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
80   -#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
81 68  
82 69 #endif /* __CONFIG_H */