Eric Lee / smarc-uboot

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Commit eb335355b9563c74ef0f54259439e6f2b57a3167

Authored by Ye.Li
Committed by Ye Li
1 parent 6e12809eef
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

ENGR00315894-81 gis: Add gis module 

Add gis module, current gis is support vadc input.
Add power down function to lcdif driver.

Signed-off-by: Sandor Yu <R01008@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit a007b00dd8ef9f773dfdebef0b1deb0990281793)
(cherry picked from commit a31dcdafb0963381e7213c59f79a340ef27ec2e2)
(cherry picked from commit 02dfe2e4af5f51d39a51542fb0e81f93faf505bc)
(cherry picked from commit a8e94954d8ccc44c41d77a5e356d6a99b3d45649)
(cherry picked from commit 0864a17afbc93fed72273c7d7d3be0fc8681e794)
(cherry picked from commit 20918f8e062111ca11bc9e3b82732145792c87c2)

Showing 7 changed files with 610 additions and 0 deletions Side-by-side Diff

arch/arm/mach-imx/cpu.c
Diff comments   View file @ eb33535
... ... @@ -21,6 +21,10 @@
21 21 #include <thermal.h>
22 22 #include <sata.h>
23 23  
  24 +#ifdef CONFIG_VIDEO_GIS
  25 +#include <gis.h>
  26 +#endif
  27 +
24 28 #ifdef CONFIG_FSL_ESDHC_IMX
25 29 #include <fsl_esdhc_imx.h>
26 30 #endif
... ... @@ -275,6 +279,10 @@
275 279 #if defined(CONFIG_VIDEO_IPUV3)
276 280 /* disable video before launching O/S */
277 281 ipuv3_fb_shutdown();
  282 +#endif
  283 +#ifdef CONFIG_VIDEO_GIS
  284 + /* Entry for GIS */
  285 + mxc_disable_gis();
278 286 #endif
279 287 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
280 288 lcdif_power_down();
drivers/video/Makefile
Diff comments   View file @ eb33535
... ... @@ -69,6 +69,10 @@
69 69 obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
70 70 obj-$(CONFIG_VIDEO_VESA) += vesa.o
71 71 obj-$(CONFIG_MXC_EPDC) += mxc_epdc_fb.o
  72 +obj-$(CONFIG_VIDEO_VADC) += mxc_vadc.o
  73 +obj-$(CONFIG_VIDEO_CSI) += mxc_csi.o
  74 +obj-$(CONFIG_VIDEO_PXP) += mxc_pxp.o
  75 +obj-$(CONFIG_VIDEO_GIS) += mxc_gis.o
72 76  
73 77 obj-y += bridge/
74 78 obj-y += sunxi/
drivers/video/mxc_gis.c
Diff comments   View file @ eb33535
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
  4 + *
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <malloc.h>
  9 +#include <video_fb.h>
  10 +
  11 +#include <asm/arch/imx-regs.h>
  12 +#include <asm/arch/sys_proto.h>
  13 +#include <linux/errno.h>
  14 +#include <asm/io.h>
  15 +
  16 +#include <linux/string.h>
  17 +#include <linux/list.h>
  18 +#include <linux/fb.h>
  19 +#include <gis.h>
  20 +#include <mxsfb.h>
  21 +
  22 +#include "mxc_gis.h"
  23 +#include "mxc_csi.h"
  24 +#include "mxc_pxp.h"
  25 +#include "mxc_vadc.h"
  26 +
  27 +#define CHANNEL_OFFSET 36
  28 +#define COMMAND_OFFSET 8
  29 +#define REG_OFFSET 4
  30 +#define COMMAND_OPCODE_SHIFT 8
  31 +
  32 +enum {
  33 + CMD_SET_ACC = 0,
  34 + CMD_WR_DATA,
  35 + CMD_WR_ACC,
  36 + CMD_WR_ALU,
  37 + CMD_MOV_ACC,
  38 + CMD_RD_DATA,
  39 + CMD_RD_ALU,
  40 + CMD_WR_FB_CSI,
  41 + CMD_WR_FB_PXP_IN,
  42 + CMD_WR_FB_PXP_OUT,
  43 + CMD_WR_FB_LCDIF,
  44 +};
  45 +
  46 +enum {
  47 + ALU_AND = 0,
  48 + ALU_OR,
  49 + ALU_XOR,
  50 + ALU_ADD,
  51 + ALU_SUB,
  52 +};
  53 +
  54 +enum {
  55 + CH_MAPPING_CSI_ISR = 0,
  56 + CH_MAPPING_CSI_FB_UPDATE,
  57 + CH_MAPPING_PXP_ISR,
  58 + CH_MAPPING_LCDIF_FB_UPDATE,
  59 + CH_MAPPING_PXP_KICK,
  60 + CH_MAPPING_CHANNEL_UNUSED = 0xf,
  61 +};
  62 +
  63 +enum {
  64 + LCDIF1_SEL = 0x10,
  65 + LCDIF0_SEL = 0x8,
  66 + PXP_SEL = 0x4,
  67 + CSI1_SEL = 0x2,
  68 + CSI0_SEL = 0x1,
  69 +};
  70 +
  71 +struct command_opcode {
  72 + unsigned opcode:4;
  73 + unsigned alu:3;
  74 + unsigned acc_neg:1;
  75 +};
  76 +
  77 +struct command_param {
  78 + union {
  79 + struct command_opcode cmd_bits;
  80 + u8 cmd_opc;
  81 + };
  82 + u32 addr;
  83 + u32 data;
  84 +};
  85 +
  86 +struct channel_param {
  87 + u32 ch_num;
  88 + u32 ch_map;
  89 + u32 cmd_num;
  90 + struct command_param cmd_data[4];
  91 +};
  92 +
  93 +static void *csibuf0, *csibuf1, *fb0, *fb1;
  94 +static struct mxs_gis_regs *gis_regs;
  95 +static struct mxs_pxp_regs *pxp_regs;
  96 +static struct mxs_csi_regs *csi_regs;
  97 +static struct mxs_lcdif_regs *lcdif_regs;
  98 +static u32 lcdif_sel;
  99 +static bool gis_running;
  100 +
  101 +static void config_channel(struct channel_param *ch)
  102 +{
  103 + u32 val, i;
  104 + u32 reg_offset;
  105 +
  106 + /* Config channel map and command */
  107 + switch (ch->ch_num) {
  108 + case 0:
  109 + val = readl(&gis_regs->hw_gis_config0);
  110 + val &= ~(GIS_CONFIG0_CH0_MAPPING_MASK | GIS_CONFIG0_CH0_NUM_MASK);
  111 + val |= ch->ch_map << GIS_CONFIG0_CH0_MAPPING_SHIFT;
  112 + val |= ch->cmd_num << GIS_CONFIG0_CH0_NUM_SHIFT;
  113 + writel(val, &gis_regs->hw_gis_config0);
  114 + break;
  115 + case 1:
  116 + val = readl(&gis_regs->hw_gis_config0);
  117 + val &= ~(GIS_CONFIG0_CH1_MAPPING_MASK | GIS_CONFIG0_CH1_NUM_MASK);
  118 + val |= ch->ch_map << GIS_CONFIG0_CH1_MAPPING_SHIFT;
  119 + val |= ch->cmd_num << GIS_CONFIG0_CH1_NUM_SHIFT;
  120 + writel(val, &gis_regs->hw_gis_config0);
  121 + break;
  122 + case 2:
  123 + val = readl(&gis_regs->hw_gis_config0);
  124 + val &= ~(GIS_CONFIG0_CH2_MAPPING_MASK | GIS_CONFIG0_CH2_NUM_MASK);
  125 + val |= ch->ch_map << GIS_CONFIG0_CH2_MAPPING_SHIFT;
  126 + val |= ch->cmd_num << GIS_CONFIG0_CH2_NUM_SHIFT;
  127 + writel(val, &gis_regs->hw_gis_config0);
  128 + break;
  129 + case 3:
  130 + val = readl(&gis_regs->hw_gis_config0);
  131 + val &= ~(GIS_CONFIG0_CH3_MAPPING_MASK | GIS_CONFIG0_CH3_NUM_MASK);
  132 + val |= ch->ch_map << GIS_CONFIG0_CH3_MAPPING_SHIFT;
  133 + val |= ch->cmd_num << GIS_CONFIG0_CH3_NUM_SHIFT;
  134 + writel(val, &gis_regs->hw_gis_config0);
  135 + break;
  136 + case 4:
  137 + val = readl(&gis_regs->hw_gis_config1);
  138 + val &= ~(GIS_CONFIG1_CH4_MAPPING_MASK | GIS_CONFIG1_CH4_NUM_MASK);
  139 + val |= ch->ch_map << GIS_CONFIG1_CH4_MAPPING_SHIFT;
  140 + val |= ch->cmd_num << GIS_CONFIG1_CH4_NUM_SHIFT;
  141 + writel(val, &gis_regs->hw_gis_config1);
  142 + break;
  143 + case 5:
  144 + val = readl(&gis_regs->hw_gis_config1);
  145 + val &= ~(GIS_CONFIG1_CH5_MAPPING_MASK | GIS_CONFIG1_CH5_NUM_MASK);
  146 + val |= ch->ch_map << GIS_CONFIG1_CH5_MAPPING_SHIFT;
  147 + val |= ch->cmd_num << GIS_CONFIG1_CH5_NUM_SHIFT;
  148 + writel(val, &gis_regs->hw_gis_config1);
  149 + break;
  150 + default:
  151 + printf("Error channel num\n");
  152 + }
  153 +
  154 + /* Config command */
  155 + for (i = 0; i < ch->cmd_num; i++) {
  156 + val = readl(&gis_regs->hw_gis_ch0_ctrl + ch->ch_num * CHANNEL_OFFSET);
  157 + val &= ~(0xFF << (COMMAND_OPCODE_SHIFT * i));
  158 + val |= ch->cmd_data[i].cmd_opc << (COMMAND_OPCODE_SHIFT * i);
  159 + writel(val, &gis_regs->hw_gis_ch0_ctrl + ch->ch_num * CHANNEL_OFFSET);
  160 +
  161 + reg_offset = ch->ch_num * CHANNEL_OFFSET + i * COMMAND_OFFSET;
  162 + writel(ch->cmd_data[i].addr, &gis_regs->hw_gis_ch0_addr0 + reg_offset);
  163 + writel(ch->cmd_data[i].data, &gis_regs->hw_gis_ch0_data0 + reg_offset);
  164 + }
  165 +}
  166 +
  167 +static void gis_channel_init(void)
  168 +{
  169 + struct channel_param ch;
  170 + int ret;
  171 + u32 addr0, data0, addr1, data1;
  172 + u32 val;
  173 +
  174 + /* Restart the GIS block */
  175 + ret = mxs_reset_block(&gis_regs->hw_gis_ctrl_reg);
  176 + if (ret) {
  177 + debug("MXS GIS: Block reset timeout\n");
  178 + return;
  179 + }
  180 +
  181 + writel((u32)csibuf0, &gis_regs->hw_gis_fb0);
  182 + writel((u32)csibuf1, &gis_regs->hw_gis_fb1);
  183 + writel((u32)fb0, &gis_regs->hw_gis_pxp_fb0);
  184 + writel((u32)fb1, &gis_regs->hw_gis_pxp_fb1);
  185 +
  186 + /* Config channel 0 -- CSI clean interrupt */
  187 + addr0 = (u32)&csi_regs->csi_csisr;
  188 + data0 = BIT_DMA_TSF_DONE_FB1 | BIT_DMA_TSF_DONE_FB2 | BIT_SOF_INT;
  189 + ch.ch_num = 0;
  190 + ch.ch_map = CH_MAPPING_CSI_ISR;
  191 + ch.cmd_num = 1;
  192 + ch.cmd_data[0].cmd_bits.opcode = CMD_WR_DATA;
  193 + ch.cmd_data[0].cmd_bits.alu = ALU_AND;
  194 + ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
  195 + ch.cmd_data[0].addr = CSI0_SEL << GIS_CH_ADDR_SEL_SHIFT | addr0;
  196 + ch.cmd_data[0].data = data0;
  197 + config_channel(&ch);
  198 +
  199 + /* Config channel 1 -- CSI set next framebuffer addr */
  200 + addr0 = (u32)&csi_regs->csi_csidmasa_fb1;
  201 + data0 = (u32)&csi_regs->csi_csidmasa_fb2;
  202 + ch.ch_num = 1;
  203 + ch.ch_map = CH_MAPPING_CSI_FB_UPDATE;
  204 + ch.cmd_num = 1;
  205 + ch.cmd_data[0].cmd_bits.opcode = CMD_WR_FB_CSI;
  206 + ch.cmd_data[0].cmd_bits.alu = ALU_AND;
  207 + ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
  208 + ch.cmd_data[0].addr = CSI0_SEL << GIS_CH_ADDR_SEL_SHIFT | addr0;
  209 + ch.cmd_data[0].data = data0;
  210 + config_channel(&ch);
  211 +
  212 + /* Config channel 2 -- PXP clear interrupt and set framebuffer */
  213 + addr0 = (u32)&pxp_regs->pxp_stat_clr;
  214 + data0 = BM_PXP_STAT_IRQ;
  215 + addr1 = (u32)&pxp_regs->pxp_out_buf;
  216 + data1 = 0;
  217 + ch.ch_num = 2;
  218 + ch.ch_map = CH_MAPPING_PXP_ISR;
  219 + ch.cmd_num = 2;
  220 + ch.cmd_data[0].cmd_bits.opcode = CMD_WR_DATA;
  221 + ch.cmd_data[0].cmd_bits.alu = ALU_AND;
  222 + ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
  223 + ch.cmd_data[0].addr = PXP_SEL << GIS_CH_ADDR_SEL_SHIFT | addr0;
  224 + ch.cmd_data[0].data = data0;
  225 + ch.cmd_data[1].cmd_bits.opcode = CMD_WR_FB_PXP_OUT;
  226 + ch.cmd_data[1].cmd_bits.alu = ALU_AND;
  227 + ch.cmd_data[1].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
  228 + ch.cmd_data[1].addr = PXP_SEL << GIS_CH_ADDR_SEL_SHIFT | addr1;
  229 + ch.cmd_data[1].data = data1;
  230 + config_channel(&ch);
  231 +
  232 + /* Config channel 3 -- LCDIF set framebuffer to display */
  233 + addr0 = (u32)&lcdif_regs->hw_lcdif_next_buf;
  234 + data0 = 0;
  235 + ch.ch_num = 3;
  236 + ch.ch_map = CH_MAPPING_LCDIF_FB_UPDATE;
  237 + ch.cmd_num = 1;
  238 + ch.cmd_data[0].cmd_bits.opcode = CMD_WR_FB_LCDIF;
  239 + ch.cmd_data[0].cmd_bits.alu = ALU_AND;
  240 + ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
  241 + ch.cmd_data[0].addr = ((lcdif_sel == 0) ? LCDIF0_SEL : LCDIF1_SEL) << GIS_CH_ADDR_SEL_SHIFT | addr0;
  242 + ch.cmd_data[0].data = data0;
  243 + config_channel(&ch);
  244 +
  245 + /* Config channel 4 -- PXP kick to process next framebuffer */
  246 + addr0 = (u32)&pxp_regs->pxp_ps_buf;
  247 + data0 = 0;
  248 + addr1 = (u32)&pxp_regs->pxp_ctrl;
  249 + data1 = BM_PXP_CTRL_IRQ_ENABLE | BM_PXP_CTRL_ENABLE;
  250 + ch.ch_num = 4;
  251 + ch.ch_map = CH_MAPPING_PXP_KICK;
  252 + ch.cmd_num = 2;
  253 + ch.cmd_data[0].cmd_bits.opcode = CMD_WR_FB_PXP_IN;
  254 + ch.cmd_data[0].cmd_bits.alu = ALU_AND;
  255 + ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
  256 + ch.cmd_data[0].addr = PXP_SEL << GIS_CH_ADDR_SEL_SHIFT | addr0;
  257 + ch.cmd_data[0].data = data0;
  258 + ch.cmd_data[1].cmd_bits.opcode = CMD_WR_DATA;
  259 + ch.cmd_data[1].cmd_bits.alu = ALU_AND;
  260 + ch.cmd_data[1].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
  261 + ch.cmd_data[1].addr = PXP_SEL << GIS_CH_ADDR_SEL_SHIFT | addr1;
  262 + ch.cmd_data[1].data = data1;
  263 + config_channel(&ch);
  264 +
  265 + /* start gis */
  266 + val = readl(&gis_regs->hw_gis_ctrl);
  267 + if (lcdif_sel == 1)
  268 + val |= GIS_CTRL_ENABLE_SET | GIS_CTRL_LCDIF_SEL_LCDIF1;
  269 + else
  270 + val |= GIS_CTRL_ENABLE_SET | GIS_CTRL_LCDIF_SEL_LCDIF0;
  271 + writel(val, &gis_regs->hw_gis_ctrl);
  272 +}
  273 +
  274 +void mxc_disable_gis(void)
  275 +{
  276 + u32 val;
  277 +
  278 + if (!gis_running)
  279 + return;
  280 +
  281 + /* Stop gis */
  282 + val = GIS_CTRL_SFTRST_SET | GIS_CTRL_CLK_GATE_SET;
  283 + writel(val, &gis_regs->hw_gis_ctrl);
  284 +
  285 + /* Stop pxp */
  286 + mxs_reset_block(&pxp_regs->pxp_ctrl_reg);
  287 + val = BM_PXP_CTRL_SFTRST | BM_PXP_CTRL_CLKGATE;
  288 + writel(val , &pxp_regs->pxp_ctrl);
  289 +
  290 + csi_disable();
  291 +
  292 + vadc_power_down();
  293 +}
  294 +
  295 +void mxc_enable_gis(void)
  296 +{
  297 + struct sensor_data sensor;
  298 + struct csi_conf_param csi_conf;
  299 + struct pxp_config_data pxp_conf;
  300 + struct display_panel panel;
  301 + u32 csimemsize, pxpmemsize;
  302 + char const *gis_input = env_get("gis");
  303 +
  304 + gis_regs = (struct mxs_gis_regs *)GIS_BASE_ADDR;
  305 + pxp_regs = (struct mxs_pxp_regs *)PXP_BASE_ADDR;
  306 + csi_regs = (struct mxs_csi_regs *)CSI1_BASE_ADDR;
  307 +
  308 + gis_running = false;
  309 +
  310 + if (gis_input != NULL && !strcmp(gis_input, "vadc")) {
  311 + printf("gis input --- vadc\n");
  312 + /* vadc_in 0 */
  313 + vadc_config(0);
  314 +
  315 + /* Get vadc mode */
  316 + vadc_get_std(&sensor);
  317 + } else {
  318 + printf("gis input --- No input\n");
  319 + return;
  320 + }
  321 +
  322 + /* Get display mode */
  323 + mxs_lcd_get_panel(&panel);
  324 +
  325 + lcdif_regs = (struct mxs_lcdif_regs *)panel.reg_base;
  326 + if (panel.reg_base == LCDIF2_BASE_ADDR)
  327 + lcdif_sel = 1;
  328 + else
  329 + lcdif_sel = 0;
  330 +
  331 + /* Allocate csi buffer */
  332 + if (sensor.pixel_fmt == FMT_YUV444) {
  333 + csimemsize = sensor.width * sensor.height * 4;
  334 + csi_conf.bpp = 32;
  335 + } else {
  336 + csimemsize = sensor.width * sensor.height * 2;
  337 + csi_conf.bpp = 16;
  338 + }
  339 +
  340 + pxpmemsize = panel.width * panel.height * panel.gdfbytespp;
  341 + csibuf0 = malloc(csimemsize);
  342 + csibuf1 = malloc(csimemsize);
  343 + fb0 = malloc(pxpmemsize);
  344 + fb1 = malloc(pxpmemsize);
  345 + if (!csibuf0 || !csibuf1 || !fb0 || !fb1) {
  346 + printf("MXSGIS: Error allocating csibuffer!\n");
  347 + return;
  348 + }
  349 + /* Wipe framebuffer */
  350 + memset(csibuf0, 0, csimemsize);
  351 + memset(csibuf1, 0, csimemsize);
  352 + memset(fb0, 0, pxpmemsize);
  353 + memset(fb1, 0, pxpmemsize);
  354 +
  355 + /*config csi */
  356 + csi_conf.width = sensor.width;
  357 + csi_conf.height = sensor.height;
  358 + csi_conf.btvmode = true;
  359 + csi_conf.std = sensor.std_id;
  360 + csi_conf.fb0addr = csibuf0;
  361 + csi_conf.fb1addr = csibuf1;
  362 + csi_config(&csi_conf);
  363 +
  364 + /* config pxp */
  365 + pxp_conf.s0_param.pixel_fmt = sensor.pixel_fmt;
  366 + pxp_conf.s0_param.width = sensor.width;
  367 + pxp_conf.s0_param.height = sensor.height;
  368 + pxp_conf.s0_param.stride = sensor.width * csi_conf.bpp/8;
  369 + pxp_conf.s0_param.paddr = csibuf0;
  370 +
  371 + switch (panel.gdfindex) {
  372 + case GDF_32BIT_X888RGB:
  373 + pxp_conf.out_param.pixel_fmt = FMT_RGB888;
  374 + break;
  375 + case GDF_16BIT_565RGB:
  376 + pxp_conf.out_param.pixel_fmt = FMT_RGB565;
  377 + break;
  378 + default:
  379 + printf("GIS unsupported format!");
  380 + }
  381 +
  382 + pxp_conf.out_param.width = panel.width;
  383 + pxp_conf.out_param.height = panel.height;
  384 + pxp_conf.out_param.stride = pxp_conf.out_param.width * panel.gdfbytespp;
  385 + pxp_conf.out_param.paddr = fb0;
  386 + pxp_config(&pxp_conf);
  387 +
  388 + gis_running = true;
  389 +
  390 + /* Config gis */
  391 + gis_channel_init();
  392 +}
drivers/video/mxc_gis.h
Diff comments   View file @ eb33535
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
  4 + *
  5 + */
  6 +
  7 +#ifndef MXC_GIS_H
  8 +#define MXC_GIS_H
  9 +
  10 +#include <asm/mach-imx/regs-common.h>
  11 +
  12 +struct mxs_gis_regs {
  13 + mxs_reg_32(hw_gis_ctrl) /* 0x00 */
  14 + mxs_reg_32(hw_gis_config0) /* 0x10 */
  15 + mxs_reg_32(hw_gis_config1) /* 0x20 */
  16 + mxs_reg_32(hw_gis_fb0) /* 0x30 */
  17 + mxs_reg_32(hw_gis_fb1) /* 0x40 */
  18 + mxs_reg_32(hw_gis_pxp_fb0) /* 0x50 */
  19 + mxs_reg_32(hw_gis_pxp_fb1) /* 0x60 */
  20 +
  21 + mxs_reg_32(hw_gis_ch0_ctrl) /* 0x70 */
  22 + mxs_reg_32(hw_gis_ch0_addr0) /* 0x80 */
  23 + mxs_reg_32(hw_gis_ch0_data0) /* 0x90 */
  24 + mxs_reg_32(hw_gis_ch0_addr1) /* 0xa0 */
  25 + mxs_reg_32(hw_gis_ch0_data1) /* 0xb0 */
  26 + mxs_reg_32(hw_gis_ch0_addr2) /* 0xc0 */
  27 + mxs_reg_32(hw_gis_ch0_data2) /* 0xd0 */
  28 + mxs_reg_32(hw_gis_ch0_addr3) /* 0xe0 */
  29 + mxs_reg_32(hw_gis_ch0_data3) /* 0xf0 */
  30 +
  31 + mxs_reg_32(hw_gis_ch1_ctrl) /* 0x100 */
  32 + mxs_reg_32(hw_gis_ch1_addr0) /* 0x110 */
  33 + mxs_reg_32(hw_gis_ch1_data0) /* 0x120 */
  34 + mxs_reg_32(hw_gis_ch1_addr1) /* 0x130 */
  35 + mxs_reg_32(hw_gis_ch1_data1) /* 0x140 */
  36 + mxs_reg_32(hw_gis_ch1_addr2) /* 0x150 */
  37 + mxs_reg_32(hw_gis_ch1_data2) /* 0x160 */
  38 + mxs_reg_32(hw_gis_ch1_addr3) /* 0x170 */
  39 + mxs_reg_32(hw_gis_ch1_data3) /* 0x180 */
  40 +
  41 + mxs_reg_32(hw_gis_ch2_ctrl) /* 0x190 */
  42 + mxs_reg_32(hw_gis_ch2_addr0) /* 0x1a0 */
  43 + mxs_reg_32(hw_gis_ch2_data0) /* 0x1b0 */
  44 + mxs_reg_32(hw_gis_ch2_addr1) /* 0x1c0 */
  45 + mxs_reg_32(hw_gis_ch2_data1) /* 0x1d0 */
  46 + mxs_reg_32(hw_gis_ch2_addr2) /* 0x1e0 */
  47 + mxs_reg_32(hw_gis_ch2_data2) /* 0x1f0 */
  48 + mxs_reg_32(hw_gis_ch2_addr3) /* 0x200 */
  49 + mxs_reg_32(hw_gis_ch2_data3) /* 0x210 */
  50 +
  51 + mxs_reg_32(hw_gis_ch3_ctrl) /* 0x220 */
  52 + mxs_reg_32(hw_gis_ch3_addr0) /* 0x230 */
  53 + mxs_reg_32(hw_gis_ch3_data0) /* 0x240 */
  54 + mxs_reg_32(hw_gis_ch3_addr1) /* 0x250 */
  55 + mxs_reg_32(hw_gis_ch3_data1) /* 0x260 */
  56 + mxs_reg_32(hw_gis_ch3_addr2) /* 0x270 */
  57 + mxs_reg_32(hw_gis_ch3_data2) /* 0x280 */
  58 + mxs_reg_32(hw_gis_ch3_addr3) /* 0x290 */
  59 + mxs_reg_32(hw_gis_ch3_data3) /* 0x2a0 */
  60 +
  61 + mxs_reg_32(hw_gis_ch4_ctrl) /* 0x2b0 */
  62 + mxs_reg_32(hw_gis_ch4_addr0) /* 0x2c0 */
  63 + mxs_reg_32(hw_gis_ch4_data0) /* 0x2d0 */
  64 + mxs_reg_32(hw_gis_ch4_addr1) /* 0x2e0 */
  65 + mxs_reg_32(hw_gis_ch4_data1) /* 0x2f0 */
  66 + mxs_reg_32(hw_gis_ch4_addr2) /* 0x300 */
  67 + mxs_reg_32(hw_gis_ch4_data2) /* 0x310 */
  68 + mxs_reg_32(hw_gis_ch4_addr3) /* 0x320 */
  69 + mxs_reg_32(hw_gis_ch4_data3) /* 0x330 */
  70 +
  71 + mxs_reg_32(hw_gis_ch5_ctrl) /* 0x340 */
  72 + mxs_reg_32(hw_gis_ch5_addr0) /* 0x350 */
  73 + mxs_reg_32(hw_gis_ch5_data0) /* 0x360 */
  74 + mxs_reg_32(hw_gis_ch5_addr1) /* 0x370 */
  75 + mxs_reg_32(hw_gis_ch5_data1) /* 0x380 */
  76 + mxs_reg_32(hw_gis_ch5_addr2) /* 0x390 */
  77 + mxs_reg_32(hw_gis_ch5_data2) /* 0x3a0 */
  78 + mxs_reg_32(hw_gis_ch5_addr3) /* 0x3b0 */
  79 + mxs_reg_32(hw_gis_ch5_data3) /* 0x3c0 */
  80 +
  81 + mxs_reg_32(hw_gis_debug0) /* 0x3d0 */
  82 + mxs_reg_32(hw_gis_debug1) /* 0x3e0 */
  83 + mxs_reg_32(hw_gis_version) /* 0x3f0 */
  84 +};
  85 +
  86 +/* register bit */
  87 +#define GIS_CTRL_SFTRST_CLR 0
  88 +#define GIS_CTRL_SFTRST_SET (1 << 31)
  89 +#define GIS_CTRL_CLK_GATE_CLR 0
  90 +#define GIS_CTRL_CLK_GATE_SET (1 << 30)
  91 +#define GIS_CTRL_LCDIF1_IRQ_POL_LOW 0
  92 +#define GIS_CTRL_LCDIF1_IRQ_POL_HIGH (1 << 8)
  93 +#define GIS_CTRL_LCDIF0_IRQ_POL_LOW 0
  94 +#define GIS_CTRL_LCDIF0_IRQ_POL_HIGH (1 << 7)
  95 +#define GIS_CTRL_PXP_IRQ_POL_LOW 0
  96 +#define GIS_CTRL_PXP_IRQ_POL_HIGH (1 << 6)
  97 +#define GIS_CTRL_CSI1_IRQ_POL_LOW 0
  98 +#define GIS_CTRL_CSI1_IRQ_POL_HIGH (1 << 5)
  99 +#define GIS_CTRL_CSI0_IRQ_POL_LOW 0
  100 +#define GIS_CTRL_CSI0_IRQ_POL_HIGH (1 << 4)
  101 +#define GIS_CTRL_CSI_SEL_CSI0 0
  102 +#define GIS_CTRL_CSI_SEL_CSI1 (1 << 3)
  103 +#define GIS_CTRL_LCDIF_SEL_LCDIF0 0
  104 +#define GIS_CTRL_LCDIF_SEL_LCDIF1 (1 << 2)
  105 +#define GIS_CTRL_FB_START_FB0 0
  106 +#define GIS_CTRL_FB_START_FB1 (1 << 1)
  107 +#define GIS_CTRL_ENABLE_CLR 0
  108 +#define GIS_CTRL_ENABLE_SET (1 << 0)
  109 +
  110 +#define GIS_CONFIG0_CH3_NUM_MASK (0x7 << 27)
  111 +#define GIS_CONFIG0_CH3_NUM_SHIFT 27
  112 +#define GIS_CONFIG0_CH3_MAPPING_MASK (0x7 << 24)
  113 +#define GIS_CONFIG0_CH3_MAPPING_SHIFT 24
  114 +#define GIS_CONFIG0_CH2_NUM_MASK (0x7 << 19)
  115 +#define GIS_CONFIG0_CH2_NUM_SHIFT 19
  116 +#define GIS_CONFIG0_CH2_MAPPING_MASK (0x7 << 16)
  117 +#define GIS_CONFIG0_CH2_MAPPING_SHIFT 16
  118 +#define GIS_CONFIG0_CH1_NUM_MASK (0x7 << 11)
  119 +#define GIS_CONFIG0_CH1_NUM_SHIFT 11
  120 +#define GIS_CONFIG0_CH1_MAPPING_MASK (0x7 << 8)
  121 +#define GIS_CONFIG0_CH1_MAPPING_SHIFT 8
  122 +#define GIS_CONFIG0_CH0_NUM_MASK (0x7 << 3)
  123 +#define GIS_CONFIG0_CH0_NUM_SHIFT 3
  124 +#define GIS_CONFIG0_CH0_MAPPING_MASK (0x7 << 0)
  125 +#define GIS_CONFIG0_CH0_MAPPING_SHIFT 0
  126 +
  127 +#define GIS_CONFIG1_CH5_NUM_MASK (0x7 << 11)
  128 +#define GIS_CONFIG1_CH5_NUM_SHIFT 11
  129 +#define GIS_CONFIG1_CH5_MAPPING_MASK (0x7 << 8)
  130 +#define GIS_CONFIG1_CH5_MAPPING_SHIFT 8
  131 +#define GIS_CONFIG1_CH4_NUM_MASK (0x7 << 3)
  132 +#define GIS_CONFIG1_CH4_NUM_SHIFT 3
  133 +#define GIS_CONFIG1_CH4_MAPPING_MASK (0x7 << 0)
  134 +#define GIS_CONFIG1_CH4_MAPPING_SHIFT 0
  135 +
  136 +#define GIS_CH_CTRL_CMD3_ACC_MASK (0x1 << 31)
  137 +#define GIS_CH_CTRL_CMD3_ACC_SHIFT 31
  138 +#define GIS_CH_CTRL_CMD3_ALU_MASK (0x7 << 28)
  139 +#define GIS_CH_CTRL_CMD3_ALU_SHIFT 28
  140 +#define GIS_CH_CTRL_CMD3_OPCODE_MASK (0xF << 24)
  141 +#define GIS_CH_CTRL_CMD3_OPCODE_SHIFT 24
  142 +#define GIS_CH_CTRL_CMD2_ACC_MASK (0x1 << 23)
  143 +#define GIS_CH_CTRL_CMD2_ACC_SHIFT 23
  144 +#define GIS_CH_CTRL_CMD2_ALU_MASK (0xF << 20)
  145 +#define GIS_CH_CTRL_CMD2_ALU_SHIFT 20
  146 +#define GIS_CH_CTRL_CMD2_OPCODE_MASK (0xF << 16)
  147 +#define GIS_CH_CTRL_CMD2_OPCODE_SHIFT 16
  148 +#define GIS_CH_CTRL_CMD1_ACC_MASK (0x1 << 15)
  149 +#define GIS_CH_CTRL_CMD1_ACC_SHIFT 15
  150 +#define GIS_CH_CTRL_CMD1_ALU_MASK (0x7 << 12)
  151 +#define GIS_CH_CTRL_CMD1_ALU_SHIFT 12
  152 +#define GIS_CH_CTRL_CMD1_OPCODE_MASK (0xF << 8)
  153 +#define GIS_CH_CTRL_CMD1_OPCODE_SHIFT 8
  154 +#define GIS_CH_CTRL_CMD0_ACC_MASK (0x1 << 7)
  155 +#define GIS_CH_CTRL_CMD0_ACC_SHIFT 7
  156 +#define GIS_CH_CTRL_CMD0_ALU_MASK (0x7 << 4)
  157 +#define GIS_CH_CTRL_CMD0_ALU_SHIFT 4
  158 +#define GIS_CH_CTRL_CMD0_OPCODE_MASK (0xF << 0)
  159 +#define GIS_CH_CTRL_CMD0_OPCODE_SHIFT 0
  160 +
  161 +#define GIS_CH_CTRL_CMD_ACC_NO_NEGATE 0
  162 +#define GIS_CH_CTRL_CMD_ACC_NEGATE 1
  163 +
  164 +#define GIS_CH_ADDR_SEL_MASK (0xF8 << 27)
  165 +#define GIS_CH_ADDR_SEL_LCDIF1 (0x1 << 31)
  166 +#define GIS_CH_ADDR_SEL_LCDIF0 (0x1 << 30)
  167 +#define GIS_CH_ADDR_SEL_PXP (0x1 << 29)
  168 +#define GIS_CH_ADDR_SEL_CSI1 (0x1 << 28)
  169 +#define GIS_CH_ADDR_SEL_CSI0 (0x1 << 27)
  170 +#define GIS_CH_ADDR_SEL_SHIFT 27
  171 +#define GIS_CH_ADDR_ADDR_MASK 0x7FFFFFF
  172 +#define GIS_CH_ADDR_ADDR_SHIFT 0
  173 +
  174 +#endif
drivers/video/mxsfb.c
Diff comments   View file @ eb33535
... ... @@ -27,6 +27,9 @@
27 27 #include <linux/fb.h>
28 28 #include <mxsfb.h>
29 29  
  30 +#ifdef CONFIG_VIDEO_GIS
  31 +#include <gis.h>
  32 +#endif
30 33  
31 34 #define PS2KHZ(ps) (1000000000UL / (ps))
32 35 #define HZ2PS(hz) (1000000000UL / ((hz) / 1000))
... ... @@ -313,6 +316,11 @@
313 316 ret = mxs_probe_common(panel.isaBase, &mode, bpp, (u32)fb);
314 317 if (ret)
315 318 goto dealloc_fb;
  319 +
  320 +#ifdef CONFIG_VIDEO_GIS
  321 + /* Entry for GIS */
  322 + mxc_enable_gis();
  323 +#endif
316 324  
317 325 return (void *)&panel;
318 326  
  1 +/*
  2 + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef GIS_H
  8 +#define GIS_H
  9 +
  10 +#define FMT_YUV444 0
  11 +#define FMT_YUYV 1
  12 +#define FMT_UYVY 2
  13 +#define FMT_RGB565 3
  14 +#define FMT_RGB888 4
  15 +
  16 +void mxc_enable_gis(void);
  17 +void mxc_disable_gis(void);
  18 +
  19 +#endif
scripts/config_whitelist.txt
Diff comments   View file @ eb33535
... ... @@ -4230,15 +4230,19 @@
4230 4230 CONFIG_VIDEO_BMP_LOGO
4231 4231 CONFIG_VIDEO_BMP_RLE8
4232 4232 CONFIG_VIDEO_CORALP
  4233 +CONFIG_VIDEO_CSI
4233 4234 CONFIG_VIDEO_DA8XX
4234 4235 CONFIG_VIDEO_FONT_4X6
  4236 +CONFIG_VIDEO_GIS
4235 4237 CONFIG_VIDEO_LCD_I2C_BUS
4236 4238 CONFIG_VIDEO_LOGO
4237 4239 CONFIG_VIDEO_MB862xx
4238 4240 CONFIG_VIDEO_MB862xx_ACCEL
4239 4241 CONFIG_VIDEO_MXS
4240 4242 CONFIG_VIDEO_MXS_MODE_SYSTEM
  4243 +CONFIG_VIDEO_PXP
4241 4244 CONFIG_VIDEO_STD_TIMINGS
  4245 +CONFIG_VIDEO_VADC
4242 4246 CONFIG_VIDEO_VCXK
4243 4247 CONFIG_VID_FLS_ENV
4244 4248 CONFIG_VM86