Commit eb86dd583476e310319df7429b0f13b331526410
Committed by
Priyanka Jain
Priyanka Jain
1 parent
cb082cf906
Exists in
smarc_8mq_lf_v2020.04
and in
4 other branches
configs: ls1088aqds: add COMMON_ENV to fix distroboot
Add COMMON_ENV(kernel_addr_r, fdt_addr_r and so on) to fix a bug that faild to boot to ubuntu, failed log as follows, ## Executing script at 80000000 load - load binary file from a filesystemUsage: load <interface> [<dev[:part]> [<addr> [<filename> [bytes [pos]]]]] - Load binary file filename from partition part on device type interface instance dev to address addr in memory. bytes gives the size to load in bytes. If bytes is 0 or omitted, the file is read until the end. pos gives the file byte position to start reading from. If pos is 0 or omitted, the file is read from the start. ... Bad Linux ARM64 Image magic! SCRIPT FAILED: continuing... Signed-off-by: Biwen Li <biwen.li@nxp.com>
Showing 1 changed file with 12 additions and 0 deletions Inline Diff
include/configs/ls1088aqds.h
| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* | 2 | /* |
| 3 | * Copyright 2017, 2020 NXP | 3 | * Copyright 2017, 2020 NXP |
| 4 | */ | 4 | */ |
| 5 | 5 | ||
| 6 | #ifndef __LS1088A_QDS_H | 6 | #ifndef __LS1088A_QDS_H |
| 7 | #define __LS1088A_QDS_H | 7 | #define __LS1088A_QDS_H |
| 8 | 8 | ||
| 9 | #include "ls1088a_common.h" | 9 | #include "ls1088a_common.h" |
| 10 | 10 | ||
| 11 | 11 | ||
| 12 | #ifndef __ASSEMBLY__ | 12 | #ifndef __ASSEMBLY__ |
| 13 | unsigned long get_board_sys_clk(void); | 13 | unsigned long get_board_sys_clk(void); |
| 14 | unsigned long get_board_ddr_clk(void); | 14 | unsigned long get_board_ddr_clk(void); |
| 15 | #endif | 15 | #endif |
| 16 | 16 | ||
| 17 | #ifdef CONFIG_TFABOOT | 17 | #ifdef CONFIG_TFABOOT |
| 18 | #define CONFIG_SYS_MMC_ENV_DEV 0 | 18 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 19 | 19 | ||
| 20 | #define CONFIG_MISC_INIT_R | 20 | #define CONFIG_MISC_INIT_R |
| 21 | #else | 21 | #else |
| 22 | #if defined(CONFIG_QSPI_BOOT) | 22 | #if defined(CONFIG_QSPI_BOOT) |
| 23 | #elif defined(CONFIG_SD_BOOT) | 23 | #elif defined(CONFIG_SD_BOOT) |
| 24 | #define CONFIG_SYS_MMC_ENV_DEV 0 | 24 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 25 | #endif | 25 | #endif |
| 26 | #endif | 26 | #endif |
| 27 | 27 | ||
| 28 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) | 28 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
| 29 | #define CONFIG_QIXIS_I2C_ACCESS | 29 | #define CONFIG_QIXIS_I2C_ACCESS |
| 30 | #define SYS_NO_FLASH | 30 | #define SYS_NO_FLASH |
| 31 | 31 | ||
| 32 | #undef CONFIG_CMD_IMLS | 32 | #undef CONFIG_CMD_IMLS |
| 33 | #define CONFIG_SYS_CLK_FREQ 100000000 | 33 | #define CONFIG_SYS_CLK_FREQ 100000000 |
| 34 | #define CONFIG_DDR_CLK_FREQ 100000000 | 34 | #define CONFIG_DDR_CLK_FREQ 100000000 |
| 35 | #else | 35 | #else |
| 36 | #define CONFIG_QIXIS_I2C_ACCESS | 36 | #define CONFIG_QIXIS_I2C_ACCESS |
| 37 | #ifndef CONFIG_DM_I2C | 37 | #ifndef CONFIG_DM_I2C |
| 38 | #define CONFIG_SYS_I2C_EARLY_INIT | 38 | #define CONFIG_SYS_I2C_EARLY_INIT |
| 39 | #endif | 39 | #endif |
| 40 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() | 40 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() |
| 41 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | 41 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() |
| 42 | #endif | 42 | #endif |
| 43 | 43 | ||
| 44 | #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) | 44 | #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) |
| 45 | #define COUNTER_FREQUENCY 25000000 /* 25MHz */ | 45 | #define COUNTER_FREQUENCY 25000000 /* 25MHz */ |
| 46 | 46 | ||
| 47 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | 47 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 48 | 48 | ||
| 49 | #define CONFIG_DDR_SPD | 49 | #define CONFIG_DDR_SPD |
| 50 | #define CONFIG_DDR_ECC | 50 | #define CONFIG_DDR_ECC |
| 51 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | 51 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
| 52 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | 52 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
| 53 | #define SPD_EEPROM_ADDRESS 0x51 | 53 | #define SPD_EEPROM_ADDRESS 0x51 |
| 54 | #define CONFIG_SYS_SPD_BUS_NUM 0 | 54 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
| 55 | 55 | ||
| 56 | 56 | ||
| 57 | /* | 57 | /* |
| 58 | * IFC Definitions | 58 | * IFC Definitions |
| 59 | */ | 59 | */ |
| 60 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) | 60 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) |
| 61 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) | 61 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) |
| 62 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | 62 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
| 63 | #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) | 63 | #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) |
| 64 | 64 | ||
| 65 | #define CONFIG_SYS_NOR0_CSPR \ | 65 | #define CONFIG_SYS_NOR0_CSPR \ |
| 66 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | 66 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ |
| 67 | CSPR_PORT_SIZE_16 | \ | 67 | CSPR_PORT_SIZE_16 | \ |
| 68 | CSPR_MSEL_NOR | \ | 68 | CSPR_MSEL_NOR | \ |
| 69 | CSPR_V) | 69 | CSPR_V) |
| 70 | #define CONFIG_SYS_NOR0_CSPR_EARLY \ | 70 | #define CONFIG_SYS_NOR0_CSPR_EARLY \ |
| 71 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ | 71 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ |
| 72 | CSPR_PORT_SIZE_16 | \ | 72 | CSPR_PORT_SIZE_16 | \ |
| 73 | CSPR_MSEL_NOR | \ | 73 | CSPR_MSEL_NOR | \ |
| 74 | CSPR_V) | 74 | CSPR_V) |
| 75 | #define CONFIG_SYS_NOR1_CSPR \ | 75 | #define CONFIG_SYS_NOR1_CSPR \ |
| 76 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ | 76 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ |
| 77 | CSPR_PORT_SIZE_16 | \ | 77 | CSPR_PORT_SIZE_16 | \ |
| 78 | CSPR_MSEL_NOR | \ | 78 | CSPR_MSEL_NOR | \ |
| 79 | CSPR_V) | 79 | CSPR_V) |
| 80 | #define CONFIG_SYS_NOR1_CSPR_EARLY \ | 80 | #define CONFIG_SYS_NOR1_CSPR_EARLY \ |
| 81 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ | 81 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ |
| 82 | CSPR_PORT_SIZE_16 | \ | 82 | CSPR_PORT_SIZE_16 | \ |
| 83 | CSPR_MSEL_NOR | \ | 83 | CSPR_MSEL_NOR | \ |
| 84 | CSPR_V) | 84 | CSPR_V) |
| 85 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) | 85 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) |
| 86 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | 86 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ |
| 87 | FTIM0_NOR_TEADC(0x5) | \ | 87 | FTIM0_NOR_TEADC(0x5) | \ |
| 88 | FTIM0_NOR_TAVDS(0x6) | \ | 88 | FTIM0_NOR_TAVDS(0x6) | \ |
| 89 | FTIM0_NOR_TEAHC(0x5)) | 89 | FTIM0_NOR_TEAHC(0x5)) |
| 90 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | 90 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ |
| 91 | FTIM1_NOR_TRAD_NOR(0x1a) | \ | 91 | FTIM1_NOR_TRAD_NOR(0x1a) | \ |
| 92 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | 92 | FTIM1_NOR_TSEQRAD_NOR(0x13)) |
| 93 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ | 93 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ |
| 94 | FTIM2_NOR_TCH(0x8) | \ | 94 | FTIM2_NOR_TCH(0x8) | \ |
| 95 | FTIM2_NOR_TWPH(0xe) | \ | 95 | FTIM2_NOR_TWPH(0xe) | \ |
| 96 | FTIM2_NOR_TWP(0x1c)) | 96 | FTIM2_NOR_TWP(0x1c)) |
| 97 | #define CONFIG_SYS_NOR_FTIM3 0x04000000 | 97 | #define CONFIG_SYS_NOR_FTIM3 0x04000000 |
| 98 | #define CONFIG_SYS_IFC_CCR 0x01000000 | 98 | #define CONFIG_SYS_IFC_CCR 0x01000000 |
| 99 | 99 | ||
| 100 | #ifndef SYS_NO_FLASH | 100 | #ifndef SYS_NO_FLASH |
| 101 | #define CONFIG_SYS_FLASH_QUIET_TEST | 101 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 102 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | 102 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 103 | 103 | ||
| 104 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | 104 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 105 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | 105 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
| 106 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | 106 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 107 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | 107 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 108 | 108 | ||
| 109 | #define CONFIG_SYS_FLASH_EMPTY_INFO | 109 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 110 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ | 110 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ |
| 111 | CONFIG_SYS_FLASH_BASE + 0x40000000} | 111 | CONFIG_SYS_FLASH_BASE + 0x40000000} |
| 112 | #endif | 112 | #endif |
| 113 | #endif | 113 | #endif |
| 114 | 114 | ||
| 115 | #define CONFIG_NAND_FSL_IFC | 115 | #define CONFIG_NAND_FSL_IFC |
| 116 | #define CONFIG_SYS_NAND_MAX_ECCPOS 256 | 116 | #define CONFIG_SYS_NAND_MAX_ECCPOS 256 |
| 117 | #define CONFIG_SYS_NAND_MAX_OOBFREE 2 | 117 | #define CONFIG_SYS_NAND_MAX_OOBFREE 2 |
| 118 | 118 | ||
| 119 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) | 119 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) |
| 120 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | 120 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 121 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | 121 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ |
| 122 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | 122 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ |
| 123 | | CSPR_V) | 123 | | CSPR_V) |
| 124 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) | 124 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) |
| 125 | 125 | ||
| 126 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | 126 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
| 127 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | 127 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ |
| 128 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | 128 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ |
| 129 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | 129 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ |
| 130 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | 130 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ |
| 131 | | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ | 131 | | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ |
| 132 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | 132 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ |
| 133 | 133 | ||
| 134 | #define CONFIG_SYS_NAND_ONFI_DETECTION | 134 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
| 135 | 135 | ||
| 136 | /* ONFI NAND Flash mode0 Timing Params */ | 136 | /* ONFI NAND Flash mode0 Timing Params */ |
| 137 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | 137 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ |
| 138 | FTIM0_NAND_TWP(0x18) | \ | 138 | FTIM0_NAND_TWP(0x18) | \ |
| 139 | FTIM0_NAND_TWCHT(0x07) | \ | 139 | FTIM0_NAND_TWCHT(0x07) | \ |
| 140 | FTIM0_NAND_TWH(0x0a)) | 140 | FTIM0_NAND_TWH(0x0a)) |
| 141 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | 141 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
| 142 | FTIM1_NAND_TWBE(0x39) | \ | 142 | FTIM1_NAND_TWBE(0x39) | \ |
| 143 | FTIM1_NAND_TRR(0x0e) | \ | 143 | FTIM1_NAND_TRR(0x0e) | \ |
| 144 | FTIM1_NAND_TRP(0x18)) | 144 | FTIM1_NAND_TRP(0x18)) |
| 145 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | 145 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ |
| 146 | FTIM2_NAND_TREH(0x0a) | \ | 146 | FTIM2_NAND_TREH(0x0a) | \ |
| 147 | FTIM2_NAND_TWHRE(0x1e)) | 147 | FTIM2_NAND_TWHRE(0x1e)) |
| 148 | #define CONFIG_SYS_NAND_FTIM3 0x0 | 148 | #define CONFIG_SYS_NAND_FTIM3 0x0 |
| 149 | 149 | ||
| 150 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | 150 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
| 151 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | 151 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 152 | #define CONFIG_MTD_NAND_VERIFY_WRITE | 152 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
| 153 | #define CONFIG_CMD_NAND | 153 | #define CONFIG_CMD_NAND |
| 154 | 154 | ||
| 155 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | 155 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
| 156 | 156 | ||
| 157 | #define CONFIG_FSL_QIXIS | 157 | #define CONFIG_FSL_QIXIS |
| 158 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 | 158 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 |
| 159 | #define QIXIS_LBMAP_SWITCH 6 | 159 | #define QIXIS_LBMAP_SWITCH 6 |
| 160 | #define QIXIS_QMAP_MASK 0xe0 | 160 | #define QIXIS_QMAP_MASK 0xe0 |
| 161 | #define QIXIS_QMAP_SHIFT 5 | 161 | #define QIXIS_QMAP_SHIFT 5 |
| 162 | #define QIXIS_LBMAP_MASK 0x0f | 162 | #define QIXIS_LBMAP_MASK 0x0f |
| 163 | #define QIXIS_LBMAP_SHIFT 0 | 163 | #define QIXIS_LBMAP_SHIFT 0 |
| 164 | #define QIXIS_LBMAP_DFLTBANK 0x0e | 164 | #define QIXIS_LBMAP_DFLTBANK 0x0e |
| 165 | #define QIXIS_LBMAP_ALTBANK 0x2e | 165 | #define QIXIS_LBMAP_ALTBANK 0x2e |
| 166 | #define QIXIS_LBMAP_SD 0x00 | 166 | #define QIXIS_LBMAP_SD 0x00 |
| 167 | #define QIXIS_LBMAP_EMMC 0x00 | 167 | #define QIXIS_LBMAP_EMMC 0x00 |
| 168 | #define QIXIS_LBMAP_IFC 0x00 | 168 | #define QIXIS_LBMAP_IFC 0x00 |
| 169 | #define QIXIS_LBMAP_SD_QSPI 0x0e | 169 | #define QIXIS_LBMAP_SD_QSPI 0x0e |
| 170 | #define QIXIS_LBMAP_QSPI 0x0e | 170 | #define QIXIS_LBMAP_QSPI 0x0e |
| 171 | #define QIXIS_RCW_SRC_IFC 0x25 | 171 | #define QIXIS_RCW_SRC_IFC 0x25 |
| 172 | #define QIXIS_RCW_SRC_SD 0x40 | 172 | #define QIXIS_RCW_SRC_SD 0x40 |
| 173 | #define QIXIS_RCW_SRC_EMMC 0x41 | 173 | #define QIXIS_RCW_SRC_EMMC 0x41 |
| 174 | #define QIXIS_RCW_SRC_QSPI 0x62 | 174 | #define QIXIS_RCW_SRC_QSPI 0x62 |
| 175 | #define QIXIS_RST_CTL_RESET 0x41 | 175 | #define QIXIS_RST_CTL_RESET 0x41 |
| 176 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | 176 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 |
| 177 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | 177 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 |
| 178 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | 178 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 |
| 179 | #define QIXIS_RST_FORCE_MEM 0x01 | 179 | #define QIXIS_RST_FORCE_MEM 0x01 |
| 180 | #define QIXIS_STAT_PRES1 0xb | 180 | #define QIXIS_STAT_PRES1 0xb |
| 181 | #define QIXIS_SDID_MASK 0x07 | 181 | #define QIXIS_SDID_MASK 0x07 |
| 182 | #define QIXIS_ESDHC_NO_ADAPTER 0x7 | 182 | #define QIXIS_ESDHC_NO_ADAPTER 0x7 |
| 183 | 183 | ||
| 184 | #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) | 184 | #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) |
| 185 | #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | 185 | #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ |
| 186 | | CSPR_PORT_SIZE_8 \ | 186 | | CSPR_PORT_SIZE_8 \ |
| 187 | | CSPR_MSEL_GPCM \ | 187 | | CSPR_MSEL_GPCM \ |
| 188 | | CSPR_V) | 188 | | CSPR_V) |
| 189 | #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | 189 | #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ |
| 190 | | CSPR_PORT_SIZE_8 \ | 190 | | CSPR_PORT_SIZE_8 \ |
| 191 | | CSPR_MSEL_GPCM \ | 191 | | CSPR_MSEL_GPCM \ |
| 192 | | CSPR_V) | 192 | | CSPR_V) |
| 193 | 193 | ||
| 194 | #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024) | 194 | #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024) |
| 195 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) | 195 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
| 196 | #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) | 196 | #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) |
| 197 | #else | 197 | #else |
| 198 | #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) | 198 | #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) |
| 199 | #endif | 199 | #endif |
| 200 | /* QIXIS Timing parameters*/ | 200 | /* QIXIS Timing parameters*/ |
| 201 | #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | 201 | #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ |
| 202 | FTIM0_GPCM_TEADC(0x0e) | \ | 202 | FTIM0_GPCM_TEADC(0x0e) | \ |
| 203 | FTIM0_GPCM_TEAHC(0x0e)) | 203 | FTIM0_GPCM_TEAHC(0x0e)) |
| 204 | #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | 204 | #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ |
| 205 | FTIM1_GPCM_TRAD(0x3f)) | 205 | FTIM1_GPCM_TRAD(0x3f)) |
| 206 | #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ | 206 | #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ |
| 207 | FTIM2_GPCM_TCH(0xf) | \ | 207 | FTIM2_GPCM_TCH(0xf) | \ |
| 208 | FTIM2_GPCM_TWP(0x3E)) | 208 | FTIM2_GPCM_TWP(0x3E)) |
| 209 | #define SYS_FPGA_CS_FTIM3 0x0 | 209 | #define SYS_FPGA_CS_FTIM3 0x0 |
| 210 | 210 | ||
| 211 | #ifdef CONFIG_TFABOOT | 211 | #ifdef CONFIG_TFABOOT |
| 212 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | 212 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
| 213 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY | 213 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY |
| 214 | #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR | 214 | #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR |
| 215 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | 215 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
| 216 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | 216 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
| 217 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | 217 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 218 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | 218 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 219 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | 219 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 220 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | 220 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 221 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT | 221 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT |
| 222 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY | 222 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY |
| 223 | #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR | 223 | #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR |
| 224 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY | 224 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY |
| 225 | #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK | 225 | #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK |
| 226 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | 226 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR |
| 227 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | 227 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 228 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | 228 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 229 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | 229 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 230 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | 230 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 231 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT | 231 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 232 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | 232 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR |
| 233 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | 233 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK |
| 234 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | 234 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR |
| 235 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | 235 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 236 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | 236 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 237 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | 237 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 238 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | 238 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 |
| 239 | #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT | 239 | #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT |
| 240 | #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR | 240 | #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR |
| 241 | #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL | 241 | #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL |
| 242 | #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK | 242 | #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK |
| 243 | #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR | 243 | #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR |
| 244 | #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 | 244 | #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 |
| 245 | #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 | 245 | #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 |
| 246 | #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 | 246 | #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 |
| 247 | #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 | 247 | #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 |
| 248 | #else | 248 | #else |
| 249 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) | 249 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
| 250 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | 250 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 251 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | 251 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
| 252 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | 252 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK |
| 253 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | 253 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR |
| 254 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | 254 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 255 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | 255 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 256 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | 256 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 257 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | 257 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 |
| 258 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT | 258 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT |
| 259 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR | 259 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR |
| 260 | #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL | 260 | #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL |
| 261 | #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK | 261 | #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK |
| 262 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR | 262 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR |
| 263 | #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 | 263 | #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 |
| 264 | #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 | 264 | #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 |
| 265 | #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 | 265 | #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 |
| 266 | #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 | 266 | #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 |
| 267 | #else | 267 | #else |
| 268 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | 268 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
| 269 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY | 269 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY |
| 270 | #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR | 270 | #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR |
| 271 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | 271 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
| 272 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | 272 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
| 273 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | 273 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 274 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | 274 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 275 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | 275 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 276 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | 276 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 277 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT | 277 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT |
| 278 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY | 278 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY |
| 279 | #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR | 279 | #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR |
| 280 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY | 280 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY |
| 281 | #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK | 281 | #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK |
| 282 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | 282 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR |
| 283 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | 283 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 284 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | 284 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 285 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | 285 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 286 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | 286 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 287 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT | 287 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 288 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | 288 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR |
| 289 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | 289 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK |
| 290 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | 290 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR |
| 291 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | 291 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 292 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | 292 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 293 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | 293 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 294 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | 294 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 |
| 295 | #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT | 295 | #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT |
| 296 | #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR | 296 | #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR |
| 297 | #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL | 297 | #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL |
| 298 | #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK | 298 | #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK |
| 299 | #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR | 299 | #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR |
| 300 | #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 | 300 | #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 |
| 301 | #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 | 301 | #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 |
| 302 | #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 | 302 | #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 |
| 303 | #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 | 303 | #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 |
| 304 | #endif | 304 | #endif |
| 305 | #endif | 305 | #endif |
| 306 | 306 | ||
| 307 | #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 | 307 | #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 |
| 308 | 308 | ||
| 309 | /* | 309 | /* |
| 310 | * I2C bus multiplexer | 310 | * I2C bus multiplexer |
| 311 | */ | 311 | */ |
| 312 | #define I2C_MUX_PCA_ADDR_PRI 0x77 | 312 | #define I2C_MUX_PCA_ADDR_PRI 0x77 |
| 313 | #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ | 313 | #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ |
| 314 | #define I2C_RETIMER_ADDR 0x18 | 314 | #define I2C_RETIMER_ADDR 0x18 |
| 315 | #define I2C_RETIMER_ADDR2 0x19 | 315 | #define I2C_RETIMER_ADDR2 0x19 |
| 316 | #define I2C_MUX_CH_DEFAULT 0x8 | 316 | #define I2C_MUX_CH_DEFAULT 0x8 |
| 317 | #define I2C_MUX_CH5 0xD | 317 | #define I2C_MUX_CH5 0xD |
| 318 | 318 | ||
| 319 | #define I2C_MUX_CH_VOL_MONITOR 0xA | 319 | #define I2C_MUX_CH_VOL_MONITOR 0xA |
| 320 | 320 | ||
| 321 | /* Voltage monitor on channel 2*/ | 321 | /* Voltage monitor on channel 2*/ |
| 322 | #define I2C_VOL_MONITOR_ADDR 0x63 | 322 | #define I2C_VOL_MONITOR_ADDR 0x63 |
| 323 | #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 | 323 | #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 |
| 324 | #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 | 324 | #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 |
| 325 | #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 | 325 | #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 |
| 326 | #define I2C_SVDD_MONITOR_ADDR 0x4F | 326 | #define I2C_SVDD_MONITOR_ADDR 0x4F |
| 327 | 327 | ||
| 328 | #define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv" | 328 | #define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv" |
| 329 | #define CONFIG_VID | 329 | #define CONFIG_VID |
| 330 | 330 | ||
| 331 | /* The lowest and highest voltage allowed for LS1088AQDS */ | 331 | /* The lowest and highest voltage allowed for LS1088AQDS */ |
| 332 | #define VDD_MV_MIN 819 | 332 | #define VDD_MV_MIN 819 |
| 333 | #define VDD_MV_MAX 1212 | 333 | #define VDD_MV_MAX 1212 |
| 334 | 334 | ||
| 335 | #define CONFIG_VOL_MONITOR_LTC3882_SET | 335 | #define CONFIG_VOL_MONITOR_LTC3882_SET |
| 336 | #define CONFIG_VOL_MONITOR_LTC3882_READ | 336 | #define CONFIG_VOL_MONITOR_LTC3882_READ |
| 337 | 337 | ||
| 338 | /* PM Bus commands code for LTC3882*/ | 338 | /* PM Bus commands code for LTC3882*/ |
| 339 | #define PMBUS_CMD_PAGE 0x0 | 339 | #define PMBUS_CMD_PAGE 0x0 |
| 340 | #define PMBUS_CMD_READ_VOUT 0x8B | 340 | #define PMBUS_CMD_READ_VOUT 0x8B |
| 341 | #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 | 341 | #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 |
| 342 | #define PMBUS_CMD_VOUT_COMMAND 0x21 | 342 | #define PMBUS_CMD_VOUT_COMMAND 0x21 |
| 343 | 343 | ||
| 344 | #define PWM_CHANNEL0 0x0 | 344 | #define PWM_CHANNEL0 0x0 |
| 345 | 345 | ||
| 346 | /* | 346 | /* |
| 347 | * RTC configuration | 347 | * RTC configuration |
| 348 | */ | 348 | */ |
| 349 | #define RTC | 349 | #define RTC |
| 350 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ | 350 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ |
| 351 | 351 | ||
| 352 | /* EEPROM */ | 352 | /* EEPROM */ |
| 353 | #define CONFIG_ID_EEPROM | 353 | #define CONFIG_ID_EEPROM |
| 354 | #define CONFIG_SYS_I2C_EEPROM_NXID | 354 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 355 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | 355 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 |
| 356 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | 356 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 357 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | 357 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 358 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | 358 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
| 359 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | 359 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 |
| 360 | 360 | ||
| 361 | #ifdef CONFIG_FSL_DSPI | 361 | #ifdef CONFIG_FSL_DSPI |
| 362 | #define CONFIG_SPI_FLASH_STMICRO | 362 | #define CONFIG_SPI_FLASH_STMICRO |
| 363 | #define CONFIG_SPI_FLASH_SST | 363 | #define CONFIG_SPI_FLASH_SST |
| 364 | #define CONFIG_SPI_FLASH_EON | 364 | #define CONFIG_SPI_FLASH_EON |
| 365 | #if !defined(CONFIG_TFABOOT) && \ | 365 | #if !defined(CONFIG_TFABOOT) && \ |
| 366 | !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) | 366 | !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) |
| 367 | #endif | 367 | #endif |
| 368 | #endif | 368 | #endif |
| 369 | 369 | ||
| 370 | #define CONFIG_CMD_MEMINFO | 370 | #define CONFIG_CMD_MEMINFO |
| 371 | #define CONFIG_SYS_MEMTEST_START 0x80000000 | 371 | #define CONFIG_SYS_MEMTEST_START 0x80000000 |
| 372 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff | 372 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff |
| 373 | 373 | ||
| 374 | #ifdef CONFIG_SPL_BUILD | 374 | #ifdef CONFIG_SPL_BUILD |
| 375 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | 375 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE |
| 376 | #else | 376 | #else |
| 377 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE | 377 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
| 378 | #endif | 378 | #endif |
| 379 | 379 | ||
| 380 | #define CONFIG_FSL_MEMAC | 380 | #define CONFIG_FSL_MEMAC |
| 381 | 381 | ||
| 382 | /* MMC */ | 382 | /* MMC */ |
| 383 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | 383 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 |
| 384 | #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ | 384 | #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ |
| 385 | QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) | 385 | QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) |
| 386 | 386 | ||
| 387 | #define COMMON_ENV \ | ||
| 388 | "kernelheader_addr_r=0x80200000\0" \ | ||
| 389 | "fdtheader_addr_r=0x80100000\0" \ | ||
| 390 | "kernel_addr_r=0x81000000\0" \ | ||
| 391 | "fdt_addr_r=0x90000000\0" \ | ||
| 392 | "load_addr=0xa0000000\0" | ||
| 393 | |||
| 387 | /* Initial environment variables */ | 394 | /* Initial environment variables */ |
| 388 | #ifdef CONFIG_NXP_ESBC | 395 | #ifdef CONFIG_NXP_ESBC |
| 389 | #undef CONFIG_EXTRA_ENV_SETTINGS | 396 | #undef CONFIG_EXTRA_ENV_SETTINGS |
| 390 | #define CONFIG_EXTRA_ENV_SETTINGS \ | 397 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 398 | COMMON_ENV \ | ||
| 391 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | 399 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ |
| 392 | "loadaddr=0x90100000\0" \ | 400 | "loadaddr=0x90100000\0" \ |
| 393 | "kernel_addr=0x100000\0" \ | 401 | "kernel_addr=0x100000\0" \ |
| 394 | "ramdisk_addr=0x800000\0" \ | 402 | "ramdisk_addr=0x800000\0" \ |
| 395 | "ramdisk_size=0x2000000\0" \ | 403 | "ramdisk_size=0x2000000\0" \ |
| 396 | "fdt_high=0xa0000000\0" \ | 404 | "fdt_high=0xa0000000\0" \ |
| 397 | "initrd_high=0xffffffffffffffff\0" \ | 405 | "initrd_high=0xffffffffffffffff\0" \ |
| 398 | "kernel_start=0x1000000\0" \ | 406 | "kernel_start=0x1000000\0" \ |
| 399 | "kernel_load=0xa0000000\0" \ | 407 | "kernel_load=0xa0000000\0" \ |
| 400 | "kernel_size=0x2800000\0" \ | 408 | "kernel_size=0x2800000\0" \ |
| 401 | "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \ | 409 | "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \ |
| 402 | "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \ | 410 | "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \ |
| 403 | "sf read 0xa0e00000 0xe00000 0x100000;" \ | 411 | "sf read 0xa0e00000 0xe00000 0x100000;" \ |
| 404 | "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \ | 412 | "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \ |
| 405 | "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \ | 413 | "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \ |
| 406 | "mcmemsize=0x70000000 \0" | 414 | "mcmemsize=0x70000000 \0" |
| 407 | #else /* if !(CONFIG_NXP_ESBC) */ | 415 | #else /* if !(CONFIG_NXP_ESBC) */ |
| 408 | #ifdef CONFIG_TFABOOT | 416 | #ifdef CONFIG_TFABOOT |
| 409 | #define QSPI_MC_INIT_CMD \ | 417 | #define QSPI_MC_INIT_CMD \ |
| 410 | "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ | 418 | "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ |
| 411 | "sf read 0x80100000 0xE00000 0x100000;" \ | 419 | "sf read 0x80100000 0xE00000 0x100000;" \ |
| 412 | "fsl_mc start mc 0x80000000 0x80100000\0" | 420 | "fsl_mc start mc 0x80000000 0x80100000\0" |
| 413 | #define SD_MC_INIT_CMD \ | 421 | #define SD_MC_INIT_CMD \ |
| 414 | "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ | 422 | "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ |
| 415 | "mmc read 0x80100000 0x7000 0x800;" \ | 423 | "mmc read 0x80100000 0x7000 0x800;" \ |
| 416 | "fsl_mc start mc 0x80000000 0x80100000\0" | 424 | "fsl_mc start mc 0x80000000 0x80100000\0" |
| 417 | #define IFC_MC_INIT_CMD \ | 425 | #define IFC_MC_INIT_CMD \ |
| 418 | "fsl_mc start mc 0x580A00000 0x580E00000\0" | 426 | "fsl_mc start mc 0x580A00000 0x580E00000\0" |
| 419 | 427 | ||
| 420 | #undef CONFIG_EXTRA_ENV_SETTINGS | 428 | #undef CONFIG_EXTRA_ENV_SETTINGS |
| 421 | #define CONFIG_EXTRA_ENV_SETTINGS \ | 429 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 430 | COMMON_ENV \ | ||
| 422 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | 431 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ |
| 423 | "loadaddr=0x90100000\0" \ | 432 | "loadaddr=0x90100000\0" \ |
| 424 | "kernel_addr=0x100000\0" \ | 433 | "kernel_addr=0x100000\0" \ |
| 425 | "kernel_addr_sd=0x800\0" \ | 434 | "kernel_addr_sd=0x800\0" \ |
| 426 | "ramdisk_addr=0x800000\0" \ | 435 | "ramdisk_addr=0x800000\0" \ |
| 427 | "ramdisk_size=0x2000000\0" \ | 436 | "ramdisk_size=0x2000000\0" \ |
| 428 | "fdt_high=0xa0000000\0" \ | 437 | "fdt_high=0xa0000000\0" \ |
| 429 | "initrd_high=0xffffffffffffffff\0" \ | 438 | "initrd_high=0xffffffffffffffff\0" \ |
| 430 | "kernel_start=0x1000000\0" \ | 439 | "kernel_start=0x1000000\0" \ |
| 431 | "kernel_start_sd=0x8000\0" \ | 440 | "kernel_start_sd=0x8000\0" \ |
| 432 | "kernel_load=0xa0000000\0" \ | 441 | "kernel_load=0xa0000000\0" \ |
| 433 | "kernel_size=0x2800000\0" \ | 442 | "kernel_size=0x2800000\0" \ |
| 434 | "kernel_size_sd=0x14000\0" \ | 443 | "kernel_size_sd=0x14000\0" \ |
| 435 | "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ | 444 | "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ |
| 436 | "sf read 0x80100000 0xE00000 0x100000;" \ | 445 | "sf read 0x80100000 0xE00000 0x100000;" \ |
| 437 | "fsl_mc start mc 0x80000000 0x80100000\0" \ | 446 | "fsl_mc start mc 0x80000000 0x80100000\0" \ |
| 438 | "mcmemsize=0x70000000 \0" \ | 447 | "mcmemsize=0x70000000 \0" \ |
| 439 | "BOARD=ls1088aqds\0" \ | 448 | "BOARD=ls1088aqds\0" \ |
| 440 | "scriptaddr=0x80000000\0" \ | 449 | "scriptaddr=0x80000000\0" \ |
| 441 | "scripthdraddr=0x80080000\0" \ | 450 | "scripthdraddr=0x80080000\0" \ |
| 442 | BOOTENV \ | 451 | BOOTENV \ |
| 443 | "boot_scripts=ls1088aqds_boot.scr\0" \ | 452 | "boot_scripts=ls1088aqds_boot.scr\0" \ |
| 444 | "boot_script_hdr=hdr_ls1088aqds_bs.out\0" \ | 453 | "boot_script_hdr=hdr_ls1088aqds_bs.out\0" \ |
| 445 | "scan_dev_for_boot_part=" \ | 454 | "scan_dev_for_boot_part=" \ |
| 446 | "part list ${devtype} ${devnum} devplist; " \ | 455 | "part list ${devtype} ${devnum} devplist; " \ |
| 447 | "env exists devplist || setenv devplist 1; " \ | 456 | "env exists devplist || setenv devplist 1; " \ |
| 448 | "for distro_bootpart in ${devplist}; do " \ | 457 | "for distro_bootpart in ${devplist}; do " \ |
| 449 | "if fstype ${devtype} " \ | 458 | "if fstype ${devtype} " \ |
| 450 | "${devnum}:${distro_bootpart} " \ | 459 | "${devnum}:${distro_bootpart} " \ |
| 451 | "bootfstype; then " \ | 460 | "bootfstype; then " \ |
| 452 | "run scan_dev_for_boot; " \ | 461 | "run scan_dev_for_boot; " \ |
| 453 | "fi; " \ | 462 | "fi; " \ |
| 454 | "done\0" \ | 463 | "done\0" \ |
| 455 | "boot_a_script=" \ | 464 | "boot_a_script=" \ |
| 456 | "load ${devtype} ${devnum}:${distro_bootpart} " \ | 465 | "load ${devtype} ${devnum}:${distro_bootpart} " \ |
| 457 | "${scriptaddr} ${prefix}${script}; " \ | 466 | "${scriptaddr} ${prefix}${script}; " \ |
| 458 | "env exists secureboot && load ${devtype} " \ | 467 | "env exists secureboot && load ${devtype} " \ |
| 459 | "${devnum}:${distro_bootpart} " \ | 468 | "${devnum}:${distro_bootpart} " \ |
| 460 | "${scripthdraddr} ${prefix}${boot_script_hdr}; "\ | 469 | "${scripthdraddr} ${prefix}${boot_script_hdr}; "\ |
| 461 | "env exists secureboot " \ | 470 | "env exists secureboot " \ |
| 462 | "&& esbc_validate ${scripthdraddr};" \ | 471 | "&& esbc_validate ${scripthdraddr};" \ |
| 463 | "source ${scriptaddr}\0" \ | 472 | "source ${scriptaddr}\0" \ |
| 464 | "qspi_bootcmd=echo Trying load from qspi..; " \ | 473 | "qspi_bootcmd=echo Trying load from qspi..; " \ |
| 465 | "sf probe 0:0; " \ | 474 | "sf probe 0:0; " \ |
| 466 | "sf read 0x80001000 0xd00000 0x100000; " \ | 475 | "sf read 0x80001000 0xd00000 0x100000; " \ |
| 467 | "fsl_mc lazyapply dpl 0x80001000 && " \ | 476 | "fsl_mc lazyapply dpl 0x80001000 && " \ |
| 468 | "sf read $kernel_load $kernel_start " \ | 477 | "sf read $kernel_load $kernel_start " \ |
| 469 | "$kernel_size && bootm $kernel_load#$BOARD\0" \ | 478 | "$kernel_size && bootm $kernel_load#$BOARD\0" \ |
| 470 | "sd_bootcmd=echo Trying load from sd card..; " \ | 479 | "sd_bootcmd=echo Trying load from sd card..; " \ |
| 471 | "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\ | 480 | "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\ |
| 472 | "fsl_mc lazyapply dpl 0x80001000 && " \ | 481 | "fsl_mc lazyapply dpl 0x80001000 && " \ |
| 473 | "mmc read $kernel_load $kernel_start_sd " \ | 482 | "mmc read $kernel_load $kernel_start_sd " \ |
| 474 | "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \ | 483 | "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \ |
| 475 | "nor_bootcmd=echo Trying load from nor..; " \ | 484 | "nor_bootcmd=echo Trying load from nor..; " \ |
| 476 | "fsl_mc lazyapply dpl 0x580d00000 && " \ | 485 | "fsl_mc lazyapply dpl 0x580d00000 && " \ |
| 477 | "cp.b $kernel_start $kernel_load " \ | 486 | "cp.b $kernel_start $kernel_load " \ |
| 478 | "$kernel_size && bootm $kernel_load#$BOARD\0" | 487 | "$kernel_size && bootm $kernel_load#$BOARD\0" |
| 479 | #else | 488 | #else |
| 480 | #if defined(CONFIG_QSPI_BOOT) | 489 | #if defined(CONFIG_QSPI_BOOT) |
| 481 | #undef CONFIG_EXTRA_ENV_SETTINGS | 490 | #undef CONFIG_EXTRA_ENV_SETTINGS |
| 482 | #define CONFIG_EXTRA_ENV_SETTINGS \ | 491 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 492 | COMMON_ENV \ | ||
| 483 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | 493 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ |
| 484 | "loadaddr=0x90100000\0" \ | 494 | "loadaddr=0x90100000\0" \ |
| 485 | "kernel_addr=0x100000\0" \ | 495 | "kernel_addr=0x100000\0" \ |
| 486 | "ramdisk_addr=0x800000\0" \ | 496 | "ramdisk_addr=0x800000\0" \ |
| 487 | "ramdisk_size=0x2000000\0" \ | 497 | "ramdisk_size=0x2000000\0" \ |
| 488 | "fdt_high=0xa0000000\0" \ | 498 | "fdt_high=0xa0000000\0" \ |
| 489 | "initrd_high=0xffffffffffffffff\0" \ | 499 | "initrd_high=0xffffffffffffffff\0" \ |
| 490 | "kernel_start=0x1000000\0" \ | 500 | "kernel_start=0x1000000\0" \ |
| 491 | "kernel_load=0xa0000000\0" \ | 501 | "kernel_load=0xa0000000\0" \ |
| 492 | "kernel_size=0x2800000\0" \ | 502 | "kernel_size=0x2800000\0" \ |
| 493 | "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ | 503 | "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ |
| 494 | "sf read 0x80100000 0xE00000 0x100000;" \ | 504 | "sf read 0x80100000 0xE00000 0x100000;" \ |
| 495 | "fsl_mc start mc 0x80000000 0x80100000\0" \ | 505 | "fsl_mc start mc 0x80000000 0x80100000\0" \ |
| 496 | "mcmemsize=0x70000000 \0" | 506 | "mcmemsize=0x70000000 \0" |
| 497 | #elif defined(CONFIG_SD_BOOT) | 507 | #elif defined(CONFIG_SD_BOOT) |
| 498 | #undef CONFIG_EXTRA_ENV_SETTINGS | 508 | #undef CONFIG_EXTRA_ENV_SETTINGS |
| 499 | #define CONFIG_EXTRA_ENV_SETTINGS \ | 509 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 510 | COMMON_ENV \ | ||
| 500 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | 511 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ |
| 501 | "loadaddr=0x90100000\0" \ | 512 | "loadaddr=0x90100000\0" \ |
| 502 | "kernel_addr=0x800\0" \ | 513 | "kernel_addr=0x800\0" \ |
| 503 | "ramdisk_addr=0x800000\0" \ | 514 | "ramdisk_addr=0x800000\0" \ |
| 504 | "ramdisk_size=0x2000000\0" \ | 515 | "ramdisk_size=0x2000000\0" \ |
| 505 | "fdt_high=0xa0000000\0" \ | 516 | "fdt_high=0xa0000000\0" \ |
| 506 | "initrd_high=0xffffffffffffffff\0" \ | 517 | "initrd_high=0xffffffffffffffff\0" \ |
| 507 | "kernel_start=0x8000\0" \ | 518 | "kernel_start=0x8000\0" \ |
| 508 | "kernel_load=0xa0000000\0" \ | 519 | "kernel_load=0xa0000000\0" \ |
| 509 | "kernel_size=0x14000\0" \ | 520 | "kernel_size=0x14000\0" \ |
| 510 | "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ | 521 | "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ |
| 511 | "mmc read 0x80100000 0x7000 0x800;" \ | 522 | "mmc read 0x80100000 0x7000 0x800;" \ |
| 512 | "fsl_mc start mc 0x80000000 0x80100000\0" \ | 523 | "fsl_mc start mc 0x80000000 0x80100000\0" \ |
| 513 | "mcmemsize=0x70000000 \0" | 524 | "mcmemsize=0x70000000 \0" |
| 514 | #else /* NOR BOOT */ | 525 | #else /* NOR BOOT */ |
| 515 | #undef CONFIG_EXTRA_ENV_SETTINGS | 526 | #undef CONFIG_EXTRA_ENV_SETTINGS |
| 516 | #define CONFIG_EXTRA_ENV_SETTINGS \ | 527 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 528 | COMMON_ENV \ | ||
| 517 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | 529 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ |
| 518 | "loadaddr=0x90100000\0" \ | 530 | "loadaddr=0x90100000\0" \ |
| 519 | "kernel_addr=0x100000\0" \ | 531 | "kernel_addr=0x100000\0" \ |
| 520 | "ramdisk_addr=0x800000\0" \ | 532 | "ramdisk_addr=0x800000\0" \ |
| 521 | "ramdisk_size=0x2000000\0" \ | 533 | "ramdisk_size=0x2000000\0" \ |
| 522 | "fdt_high=0xa0000000\0" \ | 534 | "fdt_high=0xa0000000\0" \ |
| 523 | "initrd_high=0xffffffffffffffff\0" \ | 535 | "initrd_high=0xffffffffffffffff\0" \ |
| 524 | "kernel_start=0x1000000\0" \ | 536 | "kernel_start=0x1000000\0" \ |
| 525 | "kernel_load=0xa0000000\0" \ | 537 | "kernel_load=0xa0000000\0" \ |
| 526 | "kernel_size=0x2800000\0" \ | 538 | "kernel_size=0x2800000\0" \ |
| 527 | "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \ | 539 | "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \ |
| 528 | "mcmemsize=0x70000000 \0" | 540 | "mcmemsize=0x70000000 \0" |
| 529 | #endif | 541 | #endif |
| 530 | #endif /* CONFIG_TFABOOT */ | 542 | #endif /* CONFIG_TFABOOT */ |
| 531 | #endif /* CONFIG_NXP_ESBC */ | 543 | #endif /* CONFIG_NXP_ESBC */ |
| 532 | 544 | ||
| 533 | #ifdef CONFIG_TFABOOT | 545 | #ifdef CONFIG_TFABOOT |
| 534 | #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ | 546 | #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ |
| 535 | "env exists secureboot && esbc_halt;;" | 547 | "env exists secureboot && esbc_halt;;" |
| 536 | #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ | 548 | #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ |
| 537 | "env exists secureboot && esbc_halt;;" | 549 | "env exists secureboot && esbc_halt;;" |
| 538 | #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ | 550 | #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ |
| 539 | "env exists secureboot && esbc_halt;;" | 551 | "env exists secureboot && esbc_halt;;" |
| 540 | #endif | 552 | #endif |
| 541 | 553 | ||
| 542 | #ifdef CONFIG_FSL_MC_ENET | 554 | #ifdef CONFIG_FSL_MC_ENET |
| 543 | #define CONFIG_FSL_MEMAC | 555 | #define CONFIG_FSL_MEMAC |
| 544 | #define RGMII_PHY1_ADDR 0x1 | 556 | #define RGMII_PHY1_ADDR 0x1 |
| 545 | #define RGMII_PHY2_ADDR 0x2 | 557 | #define RGMII_PHY2_ADDR 0x2 |
| 546 | #define SGMII_CARD_PORT1_PHY_ADDR 0x1C | 558 | #define SGMII_CARD_PORT1_PHY_ADDR 0x1C |
| 547 | #define SGMII_CARD_PORT2_PHY_ADDR 0x1d | 559 | #define SGMII_CARD_PORT2_PHY_ADDR 0x1d |
| 548 | #define SGMII_CARD_PORT3_PHY_ADDR 0x1E | 560 | #define SGMII_CARD_PORT3_PHY_ADDR 0x1E |
| 549 | #define SGMII_CARD_PORT4_PHY_ADDR 0x1F | 561 | #define SGMII_CARD_PORT4_PHY_ADDR 0x1F |
| 550 | 562 | ||
| 551 | #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 | 563 | #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 |
| 552 | #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 | 564 | #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 |
| 553 | #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 | 565 | #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 |
| 554 | #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 | 566 | #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 |
| 555 | #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 | 567 | #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 |
| 556 | #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 | 568 | #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 |
| 557 | #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 | 569 | #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 |
| 558 | #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 | 570 | #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 |
| 559 | #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 | 571 | #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 |
| 560 | #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 | 572 | #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 |
| 561 | #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa | 573 | #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa |
| 562 | #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb | 574 | #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb |
| 563 | #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc | 575 | #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc |
| 564 | #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd | 576 | #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd |
| 565 | #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe | 577 | #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe |
| 566 | #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf | 578 | #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf |
| 567 | 579 | ||
| 568 | #define CONFIG_ETHPRIME "DPMAC1@xgmii" | 580 | #define CONFIG_ETHPRIME "DPMAC1@xgmii" |
| 569 | 581 | ||
| 570 | #endif | 582 | #endif |
| 571 | 583 | ||
| 572 | #define BOOT_TARGET_DEVICES(func) \ | 584 | #define BOOT_TARGET_DEVICES(func) \ |
| 573 | func(USB, usb, 0) \ | 585 | func(USB, usb, 0) \ |
| 574 | func(MMC, mmc, 0) \ | 586 | func(MMC, mmc, 0) \ |
| 575 | func(SCSI, scsi, 0) \ | 587 | func(SCSI, scsi, 0) \ |
| 576 | func(DHCP, dhcp, na) | 588 | func(DHCP, dhcp, na) |
| 577 | #include <config_distro_bootcmd.h> | 589 | #include <config_distro_bootcmd.h> |
| 578 | 590 | ||
| 579 | #include <asm/fsl_secure_boot.h> | 591 | #include <asm/fsl_secure_boot.h> |
| 580 | 592 | ||
| 581 | #endif /* __LS1088A_QDS_H */ | 593 | #endif /* __LS1088A_QDS_H */ |
| 582 | 594 |