Eric Lee / smarc-uboot

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Commit ebca902aeb3af3eaedd2787928184ad84a86b98f

Authored by Tom Rini
2 parents df13a44377 b4e9bdcd05
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

Merge git://git.denx.de/u-boot-imx 

Signed-off-by: Tom Rini <trini@konsulko.com>

Showing 69 changed files Side-by-side Diff

... ... @@ -792,8 +792,12 @@
792 792 ifeq ($(CONFIG_MX6)$(CONFIG_SECURE_BOOT), yy)
793 793 ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot-ivt.img
794 794 else
  795 +ifeq ($(CONFIG_MX7)$(CONFIG_SECURE_BOOT), yy)
  796 +ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot-ivt.img
  797 +else
795 798 ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
796 799 endif
  800 +endif
797 801 ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
798 802 ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb
799 803 ifeq ($(CONFIG_SPL_FRAMEWORK),y)
800 804  
... ... @@ -856,11 +860,11 @@
856 860  
857 861 quiet_cmd_mkimage = MKIMAGE $@
858 862 cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
859   - $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT))
  863 + >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
860 864  
861 865 quiet_cmd_mkfitimage = MKIMAGE $@
862 866 cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ \
863   - $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT))
  867 + >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
864 868  
865 869 quiet_cmd_cat = CAT $@
866 870 cmd_cat = cat $(filter-out $(PHONY), $^) > $@
... ... @@ -444,22 +444,6 @@
444 444 select SUPPORT_SPL
445 445 select PL011_SERIAL
446 446  
447   -config TARGET_IMX31_PHYCORE
448   - bool "Support imx31_phycore_eet"
449   - select CPU_ARM1136
450   - select BOARD_EARLY_INIT_F
451   -
452   -config TARGET_IMX31_PHYCORE_EET
453   - bool "Support imx31_phycore_eet"
454   - select BOARD_LATE_INIT
455   - select CPU_ARM1136
456   - select BOARD_EARLY_INIT_F
457   -
458   -config TARGET_MX31ADS
459   - bool "Support mx31ads"
460   - select CPU_ARM1136
461   - select BOARD_EARLY_INIT_F
462   -
463 447 config TARGET_MX31PDK
464 448 bool "Support mx31pdk"
465 449 select BOARD_LATE_INIT
... ... @@ -1335,7 +1319,6 @@
1335 1319 source "board/freescale/ls1012aqds/Kconfig"
1336 1320 source "board/freescale/ls1012ardb/Kconfig"
1337 1321 source "board/freescale/ls1012afrdm/Kconfig"
1338   -source "board/freescale/mx31ads/Kconfig"
1339 1322 source "board/freescale/mx31pdk/Kconfig"
1340 1323 source "board/freescale/mx35pdk/Kconfig"
1341 1324 source "board/freescale/s32v234evb/Kconfig"
... ... @@ -1345,7 +1328,6 @@
1345 1328 source "board/h2200/Kconfig"
1346 1329 source "board/hisilicon/hikey/Kconfig"
1347 1330 source "board/hisilicon/poplar/Kconfig"
1348   -source "board/imx31_phycore/Kconfig"
1349 1331 source "board/isee/igep003x/Kconfig"
1350 1332 source "board/phytec/pcm051/Kconfig"
1351 1333 source "board/silica/pengwyn/Kconfig"
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
Diff comments   View file @ ebca902
... ... @@ -14,6 +14,9 @@
14 14 select SYS_FSL_ERRATUM_A009008
15 15 select ARCH_EARLY_INIT_R
16 16 select BOARD_EARLY_INIT_F
  17 + select SYS_I2C_MXC
  18 + select SYS_I2C_MXC_I2C1
  19 + select SYS_I2C_MXC_I2C2
17 20 imply PANIC_HANG
18 21  
19 22 config ARCH_LS1043A
... ... @@ -41,6 +44,11 @@
41 44 select SYS_FSL_HAS_DDR4
42 45 select ARCH_EARLY_INIT_R
43 46 select BOARD_EARLY_INIT_F
  47 + select SYS_I2C_MXC
  48 + select SYS_I2C_MXC_I2C1
  49 + select SYS_I2C_MXC_I2C2
  50 + select SYS_I2C_MXC_I2C3
  51 + select SYS_I2C_MXC_I2C4
44 52 imply SCSI
45 53 imply SCSI_AHCI
46 54 imply CMD_PCI
... ... @@ -70,6 +78,11 @@
70 78 select SYS_FSL_SRDS_2
71 79 select ARCH_EARLY_INIT_R
72 80 select BOARD_EARLY_INIT_F
  81 + select SYS_I2C_MXC
  82 + select SYS_I2C_MXC_I2C1
  83 + select SYS_I2C_MXC_I2C2
  84 + select SYS_I2C_MXC_I2C3
  85 + select SYS_I2C_MXC_I2C4
73 86 imply SCSI
74 87 imply SCSI_AHCI
75 88  
... ... @@ -102,6 +115,11 @@
102 115 select FSL_TZASC_1
103 116 select ARCH_EARLY_INIT_R
104 117 select BOARD_EARLY_INIT_F
  118 + select SYS_I2C_MXC
  119 + select SYS_I2C_MXC_I2C1
  120 + select SYS_I2C_MXC_I2C2
  121 + select SYS_I2C_MXC_I2C3
  122 + select SYS_I2C_MXC_I2C4
105 123 imply SCSI
106 124 imply PANIC_HANG
107 125  
... ... @@ -144,6 +162,11 @@
144 162 select SYS_FSL_ERRATUM_A009203
145 163 select ARCH_EARLY_INIT_R
146 164 select BOARD_EARLY_INIT_F
  165 + select SYS_I2C_MXC
  166 + select SYS_I2C_MXC_I2C1
  167 + select SYS_I2C_MXC_I2C2
  168 + select SYS_I2C_MXC_I2C3
  169 + select SYS_I2C_MXC_I2C4
147 170 imply PANIC_HANG
148 171  
149 172 config FSL_LSCH2
arch/arm/dts/imx6ul.dtsi
Diff comments   View file @ ebca902
... ... @@ -881,6 +881,14 @@
881 881 status = "disabled";
882 882 };
883 883  
  884 + wdog3: wdog@021e4000 {
  885 + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
  886 + reg = <0x021e4000 0x4000>;
  887 + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  888 + clocks = <&clks IMX6UL_CLK_WDOG3>;
  889 + status = "disabled";
  890 + };
  891 +
884 892 uart2: serial@021e8000 {
885 893 compatible = "fsl,imx6ul-uart",
886 894 "fsl,imx6q-uart";
arch/arm/dts/imx6ull.dtsi
Diff comments   View file @ ebca902
... ... @@ -1026,6 +1026,14 @@
1026 1026 status = "disabled";
1027 1027 };
1028 1028  
  1029 + wdog3: wdog@021e4000 {
  1030 + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
  1031 + reg = <0x021e4000 0x4000>;
  1032 + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  1033 + clocks = <&clks IMX6UL_CLK_WDOG3>;
  1034 + status = "disabled";
  1035 + };
  1036 +
1029 1037 uart2: serial@021e8000 {
1030 1038 compatible = "fsl,imx6ul-uart",
1031 1039 "fsl,imx6q-uart", "fsl,imx21-uart";
arch/arm/include/asm/arch-mx6/imx-regs.h
Diff comments   View file @ ebca902
... ... @@ -232,7 +232,11 @@
232 232 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
233 233 #define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000)
234 234 #define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000)
  235 +#if defined(CONFIG_MX6UL)
  236 +#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
  237 +#else
235 238 #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
  239 +#endif
236 240 #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
237 241  
238 242 #define CONFIG_SYS_FSL_SEC_OFFSET 0
arch/arm/include/asm/arch-mx7/imx-regs.h
Diff comments   View file @ ebca902
... ... @@ -264,6 +264,8 @@
264 264 u32 ddrc_rcr;
265 265 };
266 266  
  267 +#define src_base ((struct src *)SRC_BASE_ADDR)
  268 +
267 269 #define SRC_M4_REG_OFFSET 0xC
268 270 #define SRC_M4C_NON_SCLR_RST_OFFSET 0
269 271 #define SRC_M4C_NON_SCLR_RST_MASK BIT(0)
arch/arm/include/asm/mach-imx/sys_proto.h
Diff comments   View file @ ebca902
... ... @@ -107,6 +107,7 @@
107 107  
108 108 void init_aips(void);
109 109 void init_src(void);
  110 +void init_snvs(void);
110 111 void imx_wdog_disable_powerdown(void);
111 112  
112 113 int board_mmc_get_env_dev(int devno);
arch/arm/mach-imx/Makefile
Diff comments   View file @ ebca902
... ... @@ -78,9 +78,11 @@
78 78 quiet_cmd_cpp_cfg = CFGS $@
79 79 cmd_cpp_cfg = $(CPP) $(cpp_flags) -x c -o $@ $<
80 80  
81   -IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%).cfgtmp
  81 +# mkimage source config file
  82 +IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%)
82 83  
83   -$(IMX_CONFIG): %.cfgtmp: % FORCE
  84 +# How to create a cpp processed config file, they all use the same source
  85 +%.cfgout: $(IMX_CONFIG) FORCE
84 86 $(Q)mkdir -p $(dir $@)
85 87 $(call if_changed_dep,cpp_cfg)
86 88  
... ... @@ -88,7 +90,7 @@
88 90 -e $(CONFIG_SYS_TEXT_BASE)
89 91 u-boot.imx: MKIMAGEOUTPUT = u-boot.imx.log
90 92  
91   -u-boot.imx: u-boot.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE
  93 +u-boot.imx: u-boot.bin u-boot.cfgout $(PLUGIN).bin FORCE
92 94 $(call if_changed,mkimage)
93 95  
94 96 ifeq ($(CONFIG_OF_SEPARATE),y)
95 97  
96 98  
... ... @@ -96,16 +98,15 @@
96 98 -e $(CONFIG_SYS_TEXT_BASE)
97 99 u-boot-dtb.imx: MKIMAGEOUTPUT = u-boot-dtb.imx.log
98 100  
99   -u-boot-dtb.imx: u-boot-dtb.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE
  101 +u-boot-dtb.imx: u-boot-dtb.bin u-boot-dtb.cfgout $(PLUGIN).bin FORCE
100 102 $(call if_changed,mkimage)
101 103 endif
102 104  
103 105 MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imximage \
104 106 -e $(CONFIG_SPL_TEXT_BASE)
105   -
106 107 SPL: MKIMAGEOUTPUT = SPL.log
107 108  
108   -SPL: spl/u-boot-spl.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE
  109 +SPL: spl/u-boot-spl.bin spl/u-boot-spl.cfgout $(PLUGIN).bin FORCE
109 110 $(call if_changed,mkimage)
110 111  
111 112 MKIMAGEFLAGS_u-boot.uim = -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
... ... @@ -133,7 +134,7 @@
133 134 spl/u-boot-nand-spl.imx: SPL FORCE
134 135 $(call if_changed,u-boot-nand-spl_imx)
135 136  
136   -targets += $(addprefix ../../../,$(IMX_CONFIG) SPL u-boot.uim spl/u-boot-nand-spl.imx)
  137 +targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx)
137 138  
138 139 obj-$(CONFIG_ARM64) += sip.o
139 140  
arch/arm/mach-imx/hab.c
Diff comments   View file @ ebca902
... ... @@ -341,6 +341,31 @@
341 341 return 0;
342 342 }
343 343  
  344 +static int do_authenticate_image_or_failover(cmd_tbl_t *cmdtp, int flag,
  345 + int argc, char * const argv[])
  346 +{
  347 + int ret = CMD_RET_FAILURE;
  348 +
  349 + if (argc != 4) {
  350 + ret = CMD_RET_USAGE;
  351 + goto error;
  352 + }
  353 +
  354 + if (!imx_hab_is_enabled()) {
  355 + printf("error: secure boot disabled\n");
  356 + goto error;
  357 + }
  358 +
  359 + if (do_authenticate_image(NULL, flag, argc, argv) != CMD_RET_SUCCESS) {
  360 + fprintf(stderr, "authentication fail -> %s %s %s %s\n",
  361 + argv[0], argv[1], argv[2], argv[3]);
  362 + do_hab_failsafe(0, 0, 1, NULL);
  363 + };
  364 + ret = CMD_RET_SUCCESS;
  365 +error:
  366 + return ret;
  367 +}
  368 +
344 369 U_BOOT_CMD(
345 370 hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
346 371 "display HAB status",
... ... @@ -360,6 +385,16 @@
360 385 hab_failsafe, CONFIG_SYS_MAXARGS, 1, do_hab_failsafe,
361 386 "run BootROM failsafe routine",
362 387 ""
  388 + );
  389 +
  390 +U_BOOT_CMD(
  391 + hab_auth_img_or_fail, 4, 0,
  392 + do_authenticate_image_or_failover,
  393 + "authenticate image via HAB on failure drop to USB BootROM mode",
  394 + "addr length ivt_offset\n"
  395 + "addr - image hex address\n"
  396 + "length - image hex length\n"
  397 + "ivt_offset - hex offset of IVT in the image"
363 398 );
364 399  
365 400 #endif /* !defined(CONFIG_SPL_BUILD) */
arch/arm/mach-imx/mx6/Kconfig
Diff comments   View file @ ebca902
... ... @@ -387,6 +387,16 @@
387 387 config TARGET_TITANIUM
388 388 bool "titanium"
389 389  
  390 +config TARGET_KP_IMX6Q_TPC
  391 + bool "K+P KP_IMX6Q_TPC i.MX6 Quad"
  392 + select MX6QDL
  393 + select BOARD_LATE_INIT
  394 + select BOARD_EARLY_INIT_F
  395 + select SUPPORT_SPL
  396 + select DM
  397 + select DM_THERMAL
  398 + imply CMD_SPL
  399 +
390 400 config TARGET_TQMA6
391 401 bool "TQ Systems TQMa6 board"
392 402 select BOARD_LATE_INIT
... ... @@ -493,6 +503,7 @@
493 503 source "board/tqc/tqma6/Kconfig"
494 504 source "board/toradex/apalis_imx6/Kconfig"
495 505 source "board/toradex/colibri_imx6/Kconfig"
  506 +source "board/k+p/kp_imx6q_tpc/Kconfig"
496 507 source "board/udoo/Kconfig"
497 508 source "board/udoo/neo/Kconfig"
498 509 source "board/wandboard/Kconfig"
arch/arm/mach-imx/mx6/ddr.c
Diff comments   View file @ ebca902
... ... @@ -85,6 +85,23 @@
85 85 writel(val_ctrl, reg_ctrl);
86 86 }
87 87  
  88 +static void correct_mpwldectr_result(void *reg)
  89 +{
  90 + /* Limit is 200/256 of CK, which is WL_HC_DELx | 0x48. */
  91 + const unsigned int limit = 0x148;
  92 + u32 val = readl(reg);
  93 + u32 old = val;
  94 +
  95 + if ((val & 0x17f) > limit)
  96 + val &= 0xffff << 16;
  97 +
  98 + if (((val >> 16) & 0x17f) > limit)
  99 + val &= 0xffff;
  100 +
  101 + if (old != val)
  102 + writel(val, reg);
  103 +}
  104 +
88 105 int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
89 106 {
90 107 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
... ... @@ -174,6 +191,13 @@
174 191 writel(ldectrl[3], &mmdc1->mpwldectrl1);
175 192 }
176 193 errors |= 4;
  194 + }
  195 +
  196 + correct_mpwldectr_result(&mmdc0->mpwldectrl0);
  197 + correct_mpwldectr_result(&mmdc0->mpwldectrl1);
  198 + if (sysinfo->dsize == 2) {
  199 + correct_mpwldectr_result(&mmdc1->mpwldectrl0);
  200 + correct_mpwldectr_result(&mmdc1->mpwldectrl1);
177 201 }
178 202  
179 203 /*
arch/arm/mach-imx/mx7/Makefile
Diff comments   View file @ ebca902
... ... @@ -5,7 +5,7 @@
5 5 #
6 6 #
7 7  
8   -obj-y := soc.o clock.o clock_slice.o ddr.o
  8 +obj-y := soc.o clock.o clock_slice.o ddr.o snvs.o
9 9  
10 10 ifdef CONFIG_ARMV7_PSCI
11 11 obj-y += psci-mx7.o psci.o
arch/arm/mach-imx/mx7/snvs.c
Diff comments   View file @ ebca902
  1 +/*
  2 + * Copyright 2018 Linaro
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <asm/io.h>
  8 +#include <asm/arch/imx-regs.h>
  9 +#include <linux/bitops.h>
  10 +
  11 +#define SNVS_HPCOMR 0x04
  12 +#define SNVS_HPCOMR_NPSWA_EN BIT(31)
  13 +
  14 +void init_snvs(void)
  15 +{
  16 + u32 val;
  17 +
  18 + /* Ensure SNVS HPCOMR sets NPSWA_EN to allow unpriv access to SNVS LP */
  19 + val = readl(SNVS_BASE_ADDR + SNVS_HPCOMR);
  20 + val |= SNVS_HPCOMR_NPSWA_EN;
  21 + writel(val, SNVS_BASE_ADDR + SNVS_HPCOMR);
  22 +}
arch/arm/mach-imx/mx7/soc.c
Diff comments   View file @ ebca902
... ... @@ -18,6 +18,7 @@
18 18 #include <dm.h>
19 19 #include <imx_thermal.h>
20 20 #include <fsl_sec.h>
  21 +#include <asm/setup.h>
21 22  
22 23 #if defined(CONFIG_IMX_THERMAL)
23 24 static const struct imx_thermal_plat imx7_thermal_plat = {
... ... @@ -179,6 +180,8 @@
179 180 isolate_resource();
180 181 #endif
181 182  
  183 + init_snvs();
  184 +
182 185 return 0;
183 186 }
184 187  
... ... @@ -201,6 +204,27 @@
201 204 #endif
202 205  
203 206 #ifdef CONFIG_SERIAL_TAG
  207 +/*
  208 + * OCOTP_TESTER
  209 + * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
  210 + * OCOTP_TESTER describes a unique ID based on silicon wafer
  211 + * and die X/Y position
  212 + *
  213 + * OCOTOP_TESTER offset 0x410
  214 + * 31:0 fuse 0
  215 + * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
  216 + *
  217 + * OCOTP_TESTER1 offset 0x420
  218 + * 31:24 fuse 1
  219 + * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
  220 + * 23:16 fuse 1
  221 + * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
  222 + * 15:11 fuse 1
  223 + * The wafer number of the wafer on which the device was fabricated/SJC
  224 + * CHALLENGE/ Unique ID
  225 + * 10:0 fuse 1
  226 + * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
  227 + */
204 228 void get_board_serial(struct tag_serialnr *serialnr)
205 229 {
206 230 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
arch/arm/mach-imx/spl.c
Diff comments   View file @ ebca902
... ... @@ -101,6 +101,29 @@
101 101 /* Translate iMX7/MX8M boot device to the SPL boot device enumeration */
102 102 u32 spl_boot_device(void)
103 103 {
  104 +#if defined(CONFIG_MX7)
  105 + unsigned int bmode = readl(&src_base->sbmr2);
  106 +
  107 + /*
  108 + * Check for BMODE if serial downloader is enabled
  109 + * BOOT_MODE - see IMX7DRM Table 6-24
  110 + */
  111 + if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
  112 + return BOOT_DEVICE_BOARD;
  113 +
  114 + /*
  115 + * The above method does not detect that the boot ROM used
  116 + * serial downloader in case the boot ROM decided to use the
  117 + * serial downloader as a fall back (primary boot source failed).
  118 + *
  119 + * Infer that the boot ROM used the USB serial downloader by
  120 + * checking whether the USB PHY is currently active... This
  121 + * assumes that SPL did not (yet) initialize the USB PHY...
  122 + */
  123 + if (is_boot_from_usb())
  124 + return BOOT_DEVICE_BOARD;
  125 +#endif
  126 +
104 127 enum boot_device boot_device_spl = get_boot_device();
105 128  
106 129 switch (boot_device_spl) {
board/freescale/mx31ads/Kconfig
View file @ ebca902
1   -if TARGET_MX31ADS
2   -
3   -config SYS_BOARD
4   - default "mx31ads"
5   -
6   -config SYS_VENDOR
7   - default "freescale"
8   -
9   -config SYS_SOC
10   - default "mx31"
11   -
12   -config SYS_CONFIG_NAME
13   - default "mx31ads"
14   -
15   -endif
board/freescale/mx31ads/MAINTAINERS
View file @ ebca902
1   -MX31ADS BOARD
2   -#M: (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
3   -S: Orphan (since 2013-09)
4   -F: board/freescale/mx31ads/
5   -F: include/configs/mx31ads.h
6   -F: configs/mx31ads_defconfig
board/freescale/mx31ads/Makefile
View file @ ebca902
1   -#
2   -# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
3   -#
4   -# SPDX-License-Identifier: GPL-2.0+
5   -#
6   -
7   -obj-y := mx31ads.o
8   -obj-y += lowlevel_init.o
board/freescale/mx31ads/lowlevel_init.S
View file @ ebca902
1   -/*
2   - * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include <asm/arch/imx-regs.h>
8   -
9   -.macro REG reg, val
10   - ldr r2, =\reg
11   - ldr r3, =\val
12   - str r3, [r2]
13   -.endm
14   -
15   -.macro REG8 reg, val
16   - ldr r2, =\reg
17   - ldr r3, =\val
18   - strb r3, [r2]
19   -.endm
20   -
21   -.macro DELAY loops
22   - ldr r2, =\loops
23   -1:
24   - subs r2, r2, #1
25   - nop
26   - bcs 1b
27   -.endm
28   -
29   -/* RedBoot: AIPS setup - Only setup MPROTx registers.
30   - * The PACR default values are good.*/
31   -.macro init_aips
32   - /*
33   - * Set all MPROTx to be non-bufferable, trusted for R/W,
34   - * not forced to user-mode.
35   - */
36   - ldr r0, =0x43F00000
37   - ldr r1, =0x77777777
38   - str r1, [r0, #0x00]
39   - str r1, [r0, #0x04]
40   - ldr r0, =0x53F00000
41   - str r1, [r0, #0x00]
42   - str r1, [r0, #0x04]
43   -
44   - /*
45   - * Clear the on and off peripheral modules Supervisor Protect bit
46   - * for SDMA to access them. Did not change the AIPS control registers
47   - * (offset 0x20) access type
48   - */
49   - ldr r0, =0x43F00000
50   - ldr r1, =0x0
51   - str r1, [r0, #0x40]
52   - str r1, [r0, #0x44]
53   - str r1, [r0, #0x48]
54   - str r1, [r0, #0x4C]
55   - ldr r1, [r0, #0x50]
56   - and r1, r1, #0x00FFFFFF
57   - str r1, [r0, #0x50]
58   -
59   - ldr r0, =0x53F00000
60   - ldr r1, =0x0
61   - str r1, [r0, #0x40]
62   - str r1, [r0, #0x44]
63   - str r1, [r0, #0x48]
64   - str r1, [r0, #0x4C]
65   - ldr r1, [r0, #0x50]
66   - and r1, r1, #0x00FFFFFF
67   - str r1, [r0, #0x50]
68   -.endm /* init_aips */
69   -
70   -/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */
71   -.macro init_max
72   - ldr r0, =0x43F04000
73   - /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
74   - ldr r1, =0x00302154
75   - str r1, [r0, #0x000] /* for S0 */
76   - str r1, [r0, #0x100] /* for S1 */
77   - str r1, [r0, #0x200] /* for S2 */
78   - str r1, [r0, #0x300] /* for S3 */
79   - str r1, [r0, #0x400] /* for S4 */
80   - /* SGPCR - always park on last master */
81   - ldr r1, =0x10
82   - str r1, [r0, #0x010] /* for S0 */
83   - str r1, [r0, #0x110] /* for S1 */
84   - str r1, [r0, #0x210] /* for S2 */
85   - str r1, [r0, #0x310] /* for S3 */
86   - str r1, [r0, #0x410] /* for S4 */
87   - /* MGPCR - restore default values */
88   - ldr r1, =0x0
89   - str r1, [r0, #0x800] /* for M0 */
90   - str r1, [r0, #0x900] /* for M1 */
91   - str r1, [r0, #0xA00] /* for M2 */
92   - str r1, [r0, #0xB00] /* for M3 */
93   - str r1, [r0, #0xC00] /* for M4 */
94   - str r1, [r0, #0xD00] /* for M5 */
95   -.endm /* init_max */
96   -
97   -/* RedBoot: M3IF setup */
98   -.macro init_m3if
99   - /* Configure M3IF registers */
100   - ldr r1, =0xB8003000
101   - /*
102   - * M3IF Control Register (M3IFCTL)
103   - * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
104   - * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
105   - * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
106   - * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
107   - * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
108   - * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
109   - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
110   - * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
111   - * ------------
112   - * 0x00000040
113   - */
114   - ldr r0, =0x00000040
115   - str r0, [r1] /* M3IF control reg */
116   -.endm /* init_m3if */
117   -
118   -/* RedBoot: To support 133MHz DDR */
119   -.macro init_drive_strength
120   - /*
121   - * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
122   - * in SW_PAD_CTL registers
123   - */
124   -
125   - /* SDCLK */
126   - ldr r1, =0x43FAC200
127   - ldr r0, [r1, #0x6C]
128   - bic r0, r0, #(1 << 12)
129   - str r0, [r1, #0x6C]
130   -
131   - /* CAS */
132   - ldr r0, [r1, #0x70]
133   - bic r0, r0, #(1 << 22)
134   - str r0, [r1, #0x70]
135   -
136   - /* RAS */
137   - ldr r0, [r1, #0x74]
138   - bic r0, r0, #(1 << 2)
139   - str r0, [r1, #0x74]
140   -
141   - /* CS2 (CSD0) */
142   - ldr r0, [r1, #0x7C]
143   - bic r0, r0, #(1 << 22)
144   - str r0, [r1, #0x7C]
145   -
146   - /* DQM3 */
147   - ldr r0, [r1, #0x84]
148   - bic r0, r0, #(1 << 22)
149   - str r0, [r1, #0x84]
150   -
151   - /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
152   - ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
153   -pad_loop:
154   - ldr r0, [r1, #0x88]
155   - bic r0, r0, #(1 << 22)
156   - bic r0, r0, #(1 << 12)
157   - bic r0, r0, #(1 << 2)
158   - str r0, [r1, #0x88]
159   - add r1, r1, #4
160   - subs r2, r2, #0x1
161   - bne pad_loop
162   -.endm /* init_drive_strength */
163   -
164   -/* CPLD on CS4 setup */
165   -.macro init_cs4
166   - ldr r0, =WEIM_BASE
167   - ldr r1, =0x0000D843
168   - str r1, [r0, #0x40]
169   - ldr r1, =0x22252521
170   - str r1, [r0, #0x44]
171   - ldr r1, =0x22220A00
172   - str r1, [r0, #0x48]
173   -.endm /* init_cs4 */
174   -
175   -.globl lowlevel_init
176   -lowlevel_init:
177   -
178   - /* Redboot initializes very early AIPS, what for?
179   - * Then it also initializes Multi-Layer AHB Crossbar Switch,
180   - * M3IF */
181   - /* Also setup the Peripheral Port Remap register inside the core */
182   - ldr r0, =0x40000015 /* start from AIPS 2GB region */
183   - mcr p15, 0, r0, c15, c2, 4
184   -
185   - init_aips
186   -
187   - init_max
188   -
189   - init_m3if
190   -
191   - init_drive_strength
192   -
193   - init_cs4
194   -
195   - /* Image Processing Unit: */
196   - /* Too early to switch display on? */
197   - REG IPU_CONF, IPU_CONF_DI_EN /* Switch on Display Interface */
198   - /* Clock Control Module: */
199   - REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
200   -
201   - DELAY 0x40000
202   -
203   - REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
204   - REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS /* Switch to MCU PLL */
205   -
206   - /* PBC CPLD on CS4 */
207   - mov r1, #CS4_BASE
208   - ldrh r1, [r1, #0x2]
209   - /* Is 27MHz switch set? */
210   - ands r1, r1, #0x10
211   -
212   - /* 532-133-66.5 */
213   - ldr r0, =CCM_BASE
214   - ldr r1, =0xFF871D58
215   - /* PDR0 */
216   - str r1, [r0, #0x4]
217   - ldreq r1, MPCTL_PARAM_532
218   - ldrne r1, MPCTL_PARAM_532_27
219   - /* MPCTL */
220   - str r1, [r0, #0x10]
221   -
222   - /* Set UPLL=240MHz, USB=60MHz */
223   - ldr r1, =0x49FCFE7F
224   - /* PDR1 */
225   - str r1, [r0, #0x8]
226   - ldreq r1, UPCTL_PARAM_240
227   - ldrne r1, UPCTL_PARAM_240_27
228   - /* UPCTL */
229   - str r1, [r0, #0x14]
230   - /* default CLKO to 1/8 of the ARM core */
231   - mov r1, #0x000002C0
232   - add r1, r1, #0x00000006
233   - /* COSR */
234   - str r1, [r0, #0x1c]
235   -
236   - /* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */
237   -/* REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
238   -
239   - /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
240   -/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/
241   - /* Default: 1, 4, 12, 1 */
242   - REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
243   -
244   - /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
245   - REG 0xB8001010, 0x00000004
246   - REG 0xB8001004, 0x006ac73a
247   - REG 0xB8001000, 0x92100000
248   - REG 0x80000f00, 0x12344321
249   - REG 0xB8001000, 0xa2100000
250   - REG 0x80000000, 0x12344321
251   - REG 0x80000000, 0x12344321
252   - REG 0xB8001000, 0xb2100000
253   - REG8 0x80000033, 0xda
254   - REG8 0x81000000, 0xff
255   - REG 0xB8001000, 0x82226080
256   - REG 0x80000000, 0xDEADBEEF
257   - REG 0xB8001010, 0x0000000c
258   -
259   - mov pc, lr
260   -
261   -MPCTL_PARAM_532:
262   - .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
263   -MPCTL_PARAM_532_27:
264   - .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0))
265   -UPCTL_PARAM_240:
266   - .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
267   -UPCTL_PARAM_240_27:
268   - .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0))
board/freescale/mx31ads/mx31ads.c
View file @ ebca902
1   -/*
2   - * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include <common.h>
8   -#include <netdev.h>
9   -#include <asm/io.h>
10   -#include <asm/arch/clock.h>
11   -#include <asm/arch/imx-regs.h>
12   -#include <asm/arch/sys_proto.h>
13   -
14   -DECLARE_GLOBAL_DATA_PTR;
15   -
16   -int dram_init(void)
17   -{
18   - /* dram_init must store complete ramsize in gd->ram_size */
19   - gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
20   - PHYS_SDRAM_1_SIZE);
21   - return 0;
22   -}
23   -
24   -int board_early_init_f(void)
25   -{
26   - int i;
27   -
28   - /* CS0: Nor Flash */
29   - /*
30   - * CS0L and CS0A values are from the RedBoot sources by Freescale
31   - * and are also equal to those used by Sascha Hauer for the Phytec
32   - * i.MX31 board. CS0U is just a slightly optimized hardware default:
33   - * the only non-zero field "Wait State Control" is set to half the
34   - * default value.
35   - */
36   - static const struct mxc_weimcs cs0 = {
37   - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
38   - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0),
39   - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
40   - CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
41   - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
42   - CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
43   - };
44   -
45   - mxc_setup_weimcs(0, &cs0);
46   -
47   - /* setup pins for UART1 */
48   - mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
49   - mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
50   - mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
51   - mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
52   -
53   - /* SPI2 */
54   - mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
55   - mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
56   - mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
57   - mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
58   - mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
59   - mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
60   - mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
61   -
62   - /* start SPI2 clock */
63   - __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
64   -
65   - /* PBC setup */
66   - /* Enable UART transceivers also reset the Ethernet/external UART */
67   - readw(CS4_BASE + 4);
68   -
69   - writew(0x8023, CS4_BASE + 4);
70   -
71   - /* RedBoot also has an empty loop with 100000 iterations here -
72   - * clock doesn't run yet */
73   - for (i = 0; i < 100000; i++)
74   - ;
75   -
76   - /* Clear the reset, toggle the LEDs */
77   - writew(0xDF, CS4_BASE + 6);
78   -
79   - /* clock still doesn't run */
80   - for (i = 0; i < 100000; i++)
81   - ;
82   -
83   - /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */
84   - readb(CS4_BASE + 8);
85   - readb(CS4_BASE + 7);
86   - readb(CS4_BASE + 8);
87   - readb(CS4_BASE + 7);
88   -
89   - return 0;
90   -}
91   -
92   -int board_init(void)
93   -{
94   - gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */
95   -
96   - return 0;
97   -}
98   -
99   -int checkboard(void)
100   -{
101   - printf("Board: MX31ADS\n");
102   - return 0;
103   -}
104   -
105   -#ifdef CONFIG_CMD_NET
106   -int board_eth_init(bd_t *bis)
107   -{
108   - int rc = 0;
109   -#ifdef CONFIG_CS8900
110   - rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
111   -#endif
112   - return rc;
113   -}
114   -#endif
board/freescale/mx31ads/u-boot.lds
View file @ ebca902
1   -/*
2   - * January 2004 - Changed to support H4 device
3   - * Copyright (c) 2004 Texas Instruments
4   - *
5   - * (C) Copyright 2002
6   - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
7   - *
8   - * SPDX-License-Identifier: GPL-2.0+
9   - */
10   -
11   -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
12   -OUTPUT_ARCH(arm)
13   -ENTRY(_start)
14   -SECTIONS
15   -{
16   - . = 0x00000000;
17   -
18   - . = ALIGN(4);
19   - .text :
20   - {
21   - *(.__image_copy_start)
22   - /* WARNING - the following is hand-optimized to fit within */
23   - /* the sector layout of our flash chips! XXX FIXME XXX */
24   -
25   - * (.vectors)
26   - arch/arm/cpu/arm1136/start.o (.text*)
27   - board/freescale/mx31ads/built-in.o (.text*)
28   - arch/arm/lib/built-in.o (.text*)
29   - net/built-in.o (.text*)
30   - drivers/mtd/built-in.o (.text*)
31   -
32   - . = DEFINED(env_offset) ? env_offset : .;
33   - env/embedded.o(.text*)
34   -
35   - *(.text*)
36   - }
37   - . = ALIGN(4);
38   - .rodata : { *(.rodata*) }
39   -
40   - . = ALIGN(4);
41   - .data : {
42   - *(.data*)
43   - }
44   -
45   - . = ALIGN(4);
46   -
47   - . = ALIGN(4);
48   - .u_boot_list : {
49   - KEEP(*(SORT(.u_boot_list*)));
50   - }
51   -
52   - . = ALIGN(4);
53   -
54   - .image_copy_end :
55   - {
56   - *(.__image_copy_end)
57   - }
58   -
59   - .rel_dyn_start :
60   - {
61   - *(.__rel_dyn_start)
62   - }
63   -
64   - .rel.dyn : {
65   - *(.rel*)
66   - }
67   -
68   - .rel_dyn_end :
69   - {
70   - *(.__rel_dyn_end)
71   - }
72   -
73   - .hash : { *(.hash*) }
74   -
75   - .end :
76   - {
77   - *(.__end)
78   - }
79   -
80   - _image_binary_end = .;
81   -
82   -/*
83   - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
84   - * __bss_base and __bss_limit are for linker only (overlay ordering)
85   - */
86   -
87   - .bss_start __rel_dyn_start (OVERLAY) : {
88   - KEEP(*(.__bss_start));
89   - __bss_base = .;
90   - }
91   -
92   - .bss __bss_base (OVERLAY) : {
93   - *(.bss*)
94   - . = ALIGN(4);
95   - __bss_limit = .;
96   - }
97   - .bss_end __bss_limit (OVERLAY) : {
98   - KEEP(*(.__bss_end));
99   - }
100   -
101   - .dynsym _image_binary_end : { *(.dynsym) }
102   - .dynbss : { *(.dynbss) }
103   - .dynstr : { *(.dynstr*) }
104   - .dynamic : { *(.dynamic*) }
105   - .gnu.hash : { *(.gnu.hash) }
106   - .plt : { *(.plt*) }
107   - .interp : { *(.interp*) }
108   - .gnu : { *(.gnu*) }
109   - .ARM.exidx : { *(.ARM.exidx*) }
110   -}
board/ge/bx50v3/bx50v3.c
Diff comments   View file @ ebca902
... ... @@ -786,23 +786,6 @@
786 786 add_board_boot_modes(board_boot_modes);
787 787 #endif
788 788  
789   -#ifdef CONFIG_VIDEO_IPUV3
790   - /* We need at least 200ms between power on and backlight on
791   - * as per specifications from CHI MEI */
792   - mdelay(250);
793   -
794   - /* enable backlight PWM 1 */
795   - pwm_init(0, 0, 0);
796   -
797   - /* duty cycle 5000000ns, period: 5000000ns */
798   - pwm_config(0, 5000000, 5000000);
799   -
800   - /* Backlight Power */
801   - gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
802   -
803   - pwm_enable(0);
804   -#endif
805   -
806 789 /* board specific pmic init */
807 790 pmic_init();
808 791  
... ... @@ -843,4 +826,32 @@
843 826 printf("BOARD: %s\n", CONFIG_BOARD_NAME);
844 827 return 0;
845 828 }
  829 +
  830 +static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  831 +{
  832 +#ifdef CONFIG_VIDEO_IPUV3
  833 + /* We need at least 200ms between power on and backlight on
  834 + * as per specifications from CHI MEI */
  835 + mdelay(250);
  836 +
  837 + /* enable backlight PWM 1 */
  838 + pwm_init(0, 0, 0);
  839 +
  840 + /* duty cycle 5000000ns, period: 5000000ns */
  841 + pwm_config(0, 5000000, 5000000);
  842 +
  843 + /* Backlight Power */
  844 + gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
  845 +
  846 + pwm_enable(0);
  847 +#endif
  848 +
  849 + return 0;
  850 +}
  851 +
  852 +U_BOOT_CMD(
  853 + bx50_backlight_enable, 1, 1, do_backlight_enable,
  854 + "enable Bx50 backlight",
  855 + ""
  856 +);
board/imx31_phycore/Kconfig
View file @ ebca902
1   -if TARGET_IMX31_PHYCORE || TARGET_IMX31_PHYCORE_EET
2   -
3   -config SYS_BOARD
4   - default "imx31_phycore"
5   -
6   -config SYS_SOC
7   - default "mx31"
8   -
9   -config SYS_CONFIG_NAME
10   - default "imx31_phycore"
11   -
12   -endif
board/imx31_phycore/MAINTAINERS
View file @ ebca902
1   -IMX31_PHYCORE BOARD
2   -#M: -
3   -S: Maintained
4   -F: board/imx31_phycore/
5   -F: include/configs/imx31_phycore.h
6   -F: configs/imx31_phycore_defconfig
7   -
8   -IMX31_PHYCORE_EET BOARD
9   -#M: (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
10   -S: Orphan (since 2013-09)
11   -F: configs/imx31_phycore_eet_defconfig
board/imx31_phycore/Makefile
View file @ ebca902
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y := imx31_phycore.o
9   -obj-y += lowlevel_init.o
board/imx31_phycore/imx31_phycore.c
View file @ ebca902
1   -/*
2   - *
3   - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -
9   -#include <common.h>
10   -#include <s6e63d6.h>
11   -#include <netdev.h>
12   -#include <asm/arch/clock.h>
13   -#include <asm/arch/imx-regs.h>
14   -#include <asm/mach-types.h>
15   -#include <asm/arch/sys_proto.h>
16   -
17   -DECLARE_GLOBAL_DATA_PTR;
18   -
19   -int dram_init(void)
20   -{
21   - /* dram_init must store complete ramsize in gd->ram_size */
22   - gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
23   - PHYS_SDRAM_1_SIZE);
24   - return 0;
25   -}
26   -
27   -int board_init(void)
28   -{
29   -
30   - gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */
31   - gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
32   -
33   - return 0;
34   -}
35   -
36   -int board_early_init_f(void)
37   -{
38   - /* CS0: Nor Flash */
39   - static const struct mxc_weimcs cs0 = {
40   - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
41   - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
42   - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
43   - CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
44   - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
45   - CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
46   - };
47   -
48   - /* CS1: Network Controller */
49   - static const struct mxc_weimcs cs1 = {
50   - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
51   - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6),
52   - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
53   - CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
54   - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
55   - CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
56   - };
57   -
58   - /* CS4: SRAM */
59   - static const struct mxc_weimcs cs4 = {
60   - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
61   - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
62   - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
63   - CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
64   - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
65   - CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
66   - };
67   -
68   - mxc_setup_weimcs(0, &cs0);
69   - mxc_setup_weimcs(1, &cs1);
70   - mxc_setup_weimcs(4, &cs4);
71   -
72   - /* setup pins for UART1 */
73   - mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
74   - mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
75   - mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
76   - mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
77   -
78   - /* setup pins for I2C2 (for EEPROM, RTC) */
79   - mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
80   - mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA);
81   -
82   - return 0;
83   -}
84   -
85   -#ifdef CONFIG_BOARD_LATE_INIT
86   -int board_late_init(void)
87   -{
88   -#ifdef CONFIG_S6E63D6
89   - struct s6e63d6 data = {
90   - /*
91   - * See comment in mxc_spi.c::decode_cs() for .cs field format.
92   - * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect
93   - * 2 of the SPI controller #1, since it is unused.
94   - */
95   - .cs = 2 | (57 << 8),
96   - .bus = 0,
97   - .id = 0,
98   - };
99   - int ret;
100   -
101   - /* SPI1 */
102   - mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
103   - mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
104   - mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
105   - mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
106   - mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
107   - mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
108   - mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
109   -
110   - /* start SPI1 clock */
111   - __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
112   -
113   - /* GPIO 57 */
114   - /* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
115   - mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
116   -
117   - /* SPI1 CS2 is free */
118   - ret = s6e63d6_init(&data);
119   - if (ret)
120   - return ret;
121   -
122   - /*
123   - * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
124   - * OLED display connected to a S6E63D6 SPI display controller in the
125   - * 18 bit RGB mode
126   - */
127   - s6e63d6_index(&data, 2);
128   - s6e63d6_param(&data, 0x0182);
129   - s6e63d6_index(&data, 3);
130   - s6e63d6_param(&data, 0x8130);
131   - s6e63d6_index(&data, 0x10);
132   - s6e63d6_param(&data, 0x0000);
133   - s6e63d6_index(&data, 5);
134   - s6e63d6_param(&data, 0x0001);
135   - s6e63d6_index(&data, 0x22);
136   -#endif
137   - return 0;
138   -}
139   -#endif
140   -
141   -int checkboard (void)
142   -{
143   - printf("Board: Phytec phyCore i.MX31\n");
144   - return 0;
145   -}
146   -
147   -int board_eth_init(bd_t *bis)
148   -{
149   - int rc = 0;
150   -#ifdef CONFIG_SMC911X
151   - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
152   -#endif
153   - return rc;
154   -}
board/imx31_phycore/lowlevel_init.S
View file @ ebca902
1   -/*
2   - *
3   - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <asm/arch/imx-regs.h>
9   -
10   -.macro REG reg, val
11   - ldr r2, =\reg
12   - ldr r3, =\val
13   - str r3, [r2]
14   -.endm
15   -
16   -.macro REG8 reg, val
17   - ldr r2, =\reg
18   - ldr r3, =\val
19   - strb r3, [r2]
20   -.endm
21   -
22   -.macro DELAY loops
23   - ldr r2, =\loops
24   -1:
25   - subs r2, r2, #1
26   - nop
27   - bcs 1b
28   -.endm
29   -
30   -.globl lowlevel_init
31   -lowlevel_init:
32   -
33   - REG IPU_CONF, IPU_CONF_DI_EN
34   - REG CCM_CCMR, 0x074B0BF5
35   -
36   - DELAY 0x40000
37   -
38   - REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
39   - REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
40   -
41   - REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
42   -
43   - REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
44   -
45   - REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1)
46   -
47   - REG 0x43FAC26C, 0 /* SDCLK */
48   - REG 0x43FAC270, 0 /* CAS */
49   - REG 0x43FAC274, 0 /* RAS */
50   - REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */
51   - REG 0x43FAC284, 0 /* DQM3 */
52   - REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
53   - REG 0x43FAC28C, 0
54   - REG 0x43FAC290, 0
55   - REG 0x43FAC294, 0
56   - REG 0x43FAC298, 0
57   - REG 0x43FAC29C, 0
58   - REG 0x43FAC2A0, 0
59   - REG 0x43FAC2A4, 0
60   - REG 0x43FAC2A8, 0
61   - REG 0x43FAC2AC, 0
62   - REG 0x43FAC2B0, 0
63   - REG 0x43FAC2B4, 0
64   - REG 0x43FAC2B8, 0
65   - REG 0x43FAC2BC, 0
66   - REG 0x43FAC2C0, 0
67   - REG 0x43FAC2C4, 0
68   - REG 0x43FAC2C8, 0
69   - REG 0x43FAC2CC, 0
70   - REG 0x43FAC2D0, 0
71   - REG 0x43FAC2D4, 0
72   - REG 0x43FAC2D8, 0
73   - REG 0x43FAC2DC, 0
74   - REG 0xB8001010, 0x00000004
75   - REG 0xB8001004, 0x006ac73a
76   - REG 0xB8001000, 0x92100000
77   - REG 0x80000f00, 0x12344321
78   - REG 0xB8001000, 0xa2100000
79   - REG 0x80000000, 0x12344321
80   - REG 0x80000000, 0x12344321
81   - REG 0xB8001000, 0xb2100000
82   - REG8 0x80000033, 0xda
83   - REG8 0x81000000, 0xff
84   - REG 0xB8001000, 0x82226080
85   - REG 0x80000000, 0xDEADBEEF
86   - REG 0xB8001010, 0x0000000c
87   -
88   - mov pc, lr
board/k+p/bootscripts/tpcboot.cmd
Diff comments   View file @ ebca902
  1 +#
  2 +# Copyright (C) 2018
  3 +# Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  4 +#
  5 +#
  6 +# This is an example file to generate boot.scr - a boot script for U-Boot
  7 +# Generate boot.scr:
  8 +# ./tools/mkimage -c none -A arm -T script -d tpcboot.cmd boot.scr
  9 +#
  10 +# SPDX-License-Identifier: GPL-2.0+
  11 +
  12 +
  13 +# Input envs (to be set in environment)
  14 +# Mandatory:
  15 +# kernel_file = "fitImage"
  16 +# boardname = "XXXX" // set automatically in u-boot
  17 +# boardsoc = "imx6q" // set automatically in u-boot
  18 +#
  19 +# Optional:
  20 +# bootcmd_force = "nfs" "tftp_kernel"
  21 +# If not set - eMMC/SD boot
  22 +
  23 +# Generic setup
  24 +setenv mmcroot "/dev/mmcblk${devnum}p2 rootwait rw"
  25 +setenv displayargs ""
  26 +setenv mmcargs "setenv bootargs console=${console} ${smp} root=${mmcroot} \
  27 + ${displayargs}"
  28 +setenv boot_fitImage "
  29 + setenv fdt_conf 'conf@${boardsoc}-${boardname}.dtb';
  30 + setenv itbcfg "\"#\${fdt_conf}\"";
  31 + print itbcfg;
  32 + bootm '${loadaddr}${itbcfg}';"
  33 +
  34 +#------------------------------------------------------------
  35 +#
  36 +# Provide default 'bootcmd' command
  37 +#------------------------------------------------------------
  38 +setenv bootcmd "
  39 +if test -e ${devtype} ${devnum}:${distro_bootpart} ${kernel_file}; then
  40 + echo Found kernel image: ${kernel_file};
  41 + if load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} \
  42 + ${kernel_file}; then
  43 + run mmcargs;
  44 + run boot_fitImage;
  45 + fi;
  46 +fi;"
  47 +
  48 +#------------------------------------------------------------
  49 +#
  50 +# Provide 'boot_tftp_kernel' command
  51 +#------------------------------------------------------------
  52 +setenv download_kernel "tftpboot ${loadaddr} ${kernel_file}"
  53 +
  54 +setenv boot_tftp_kernel "
  55 +if run download_kernel; then
  56 + run mmcargs;
  57 + run boot_fitImage;
  58 +fi"
  59 +
  60 +#------------------------------------------------------------
  61 +#
  62 +# Provide 'boot_nfs' command
  63 +#------------------------------------------------------------
  64 +setenv rootpath "/srv/tftp/KP/rootfs"
  65 +setenv nfsargs "setenv bootargs root=/dev/nfs rw \
  66 + nfsroot=${serverip}:${rootpath},nolock,nfsvers=3"
  67 +setenv addip "setenv bootargs ${bootargs} \
  68 + ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:\
  69 + ${hostname}:eth0:on"
  70 +
  71 +setenv boot_nfs "
  72 +if run download_kernel; then
  73 + run nfsargs;
  74 + run addip;
  75 + setenv bootargs ${bootargs} console=${console};
  76 +
  77 + run boot_fitImage;
  78 +fi"
  79 +
  80 +#------------------------------------------------------------
  81 +#
  82 +# Set correct boot flow
  83 +#------------------------------------------------------------
  84 +
  85 +setenv bcmd "
  86 +if test ! -n ${bootcmd_force}; then
  87 + run bootcmd;
  88 +fi;
  89 +if test ${bootcmd_force} = nfs; then
  90 + run boot_nfs;
  91 +else if test ${bootcmd_force} = tftp_kernel; then
  92 + run boot_tftp_kernel;
  93 + fi;
  94 +fi"
  95 +
  96 +run bcmd
board/k+p/kp_imx6q_tpc/Kconfig
Diff comments   View file @ ebca902
  1 +if TARGET_KP_IMX6Q_TPC
  2 +
  3 +config SYS_BOARD
  4 + default "kp_imx6q_tpc"
  5 +
  6 +config SYS_VENDOR
  7 + default "k+p"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "kp_imx6q_tpc"
  11 +
  12 +endif
board/k+p/kp_imx6q_tpc/MAINTAINERS
Diff comments   View file @ ebca902
  1 +KP_IMX6Q_TPC BOARD
  2 +M: Lukasz Majewski <lukma@denx.de>
  3 +S: Maintained
  4 +F: board/k+p/kp_imx6q_tpc/
  5 +F: include/configs/kp_imx6q_tpc.h
  6 +F: configs/kp_imx6q_tpc_defconfig
board/k+p/kp_imx6q_tpc/Makefile
Diff comments   View file @ ebca902
  1 +#
  2 +# Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +ifdef CONFIG_SPL_BUILD
  8 +obj-y := kp_imx6q_tpc_spl.o
  9 +else
  10 +obj-y := kp_imx6q_tpc.o
  11 +endif
board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
Diff comments   View file @ ebca902
  1 +/*
  2 + * K+P iMX6Q KP_IMX6Q_TPC board configuration
  3 + *
  4 + * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <asm/arch/clock.h>
  11 +#include <asm/arch/crm_regs.h>
  12 +#include <asm/arch/imx-regs.h>
  13 +#include <asm/arch/iomux.h>
  14 +#include <asm/arch/mx6-pins.h>
  15 +#include <asm/arch/sys_proto.h>
  16 +#include <asm/gpio.h>
  17 +#include <asm/io.h>
  18 +#include <asm/mach-imx/boot_mode.h>
  19 +#include <asm/mach-imx/iomux-v3.h>
  20 +#include <asm/mach-imx/mxc_i2c.h>
  21 +#include <errno.h>
  22 +#include <fsl_esdhc.h>
  23 +#include <fuse.h>
  24 +#include <i2c.h>
  25 +#include <miiphy.h>
  26 +#include <mmc.h>
  27 +#include <net.h>
  28 +#include <netdev.h>
  29 +#include <usb.h>
  30 +#include <usb/ehci-ci.h>
  31 +
  32 +DECLARE_GLOBAL_DATA_PTR;
  33 +
  34 +#define ENET_PAD_CTRL \
  35 + (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  36 + PAD_CTL_HYS)
  37 +
  38 +#define I2C_PAD_CTRL \
  39 + (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  40 + PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  41 +
  42 +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  43 +
  44 +static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info0 = {
  45 + .scl = {
  46 + .i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL | PC,
  47 + .gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
  48 + .gp = IMX_GPIO_NR(5, 27)
  49 + },
  50 + .sda = {
  51 + .i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA | PC,
  52 + .gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
  53 + .gp = IMX_GPIO_NR(5, 26)
  54 + }
  55 +};
  56 +
  57 +static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info1 = {
  58 + .scl = {
  59 + .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
  60 + .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
  61 + .gp = IMX_GPIO_NR(4, 12)
  62 + },
  63 + .sda = {
  64 + .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
  65 + .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  66 + .gp = IMX_GPIO_NR(4, 13)
  67 + }
  68 +};
  69 +
  70 +int dram_init(void)
  71 +{
  72 + gd->ram_size = imx_ddr_size();
  73 + return 0;
  74 +}
  75 +
  76 +/*
  77 + * Do not overwrite the console
  78 + * Use always serial for U-Boot console
  79 + */
  80 +int overwrite_console(void)
  81 +{
  82 + return 1;
  83 +}
  84 +
  85 +#ifdef CONFIG_FEC_MXC
  86 +static iomux_v3_cfg_t const enet_pads[] = {
  87 + IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  88 + IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  89 + IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  90 + IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  91 + IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  92 + IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  93 + IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  94 + IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  95 + MUX_PAD_CTRL(ENET_PAD_CTRL)),
  96 + IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  97 + IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  98 + IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  99 + IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  100 + IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  101 + IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  102 + IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  103 + MUX_PAD_CTRL(ENET_PAD_CTRL)),
  104 + /* AR8031 PHY Reset */
  105 + IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  106 +};
  107 +
  108 +static void eth_phy_reset(void)
  109 +{
  110 + /* Reset AR8031 PHY */
  111 + gpio_direction_output(IMX_GPIO_NR(1, 25), 0);
  112 + mdelay(10);
  113 + gpio_set_value(IMX_GPIO_NR(1, 25), 1);
  114 + udelay(100);
  115 +}
  116 +
  117 +static int setup_fec_clock(void)
  118 +{
  119 + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  120 +
  121 + /* set gpr1[21] to select anatop clock */
  122 + clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
  123 +
  124 + return enable_fec_anatop_clock(0, ENET_50MHZ);
  125 +}
  126 +
  127 +int board_eth_init(bd_t *bis)
  128 +{
  129 + SETUP_IOMUX_PADS(enet_pads);
  130 + setup_fec_clock();
  131 + eth_phy_reset();
  132 +
  133 + return cpu_eth_init(bis);
  134 +}
  135 +
  136 +static int ar8031_phy_fixup(struct phy_device *phydev)
  137 +{
  138 + unsigned short val;
  139 +
  140 + /* To enable AR8031 output a 125MHz clk from CLK_25M */
  141 + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  142 + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  143 + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  144 +
  145 + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  146 + val &= 0xffe3;
  147 + val |= 0x18;
  148 + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  149 +
  150 + /* introduce tx clock delay */
  151 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  152 + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  153 + val |= 0x0100;
  154 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  155 +
  156 + return 0;
  157 +}
  158 +
  159 +int board_phy_config(struct phy_device *phydev)
  160 +{
  161 + ar8031_phy_fixup(phydev);
  162 +
  163 + if (phydev->drv->config)
  164 + phydev->drv->config(phydev);
  165 +
  166 + return 0;
  167 +}
  168 +#endif
  169 +
  170 +#ifdef CONFIG_FSL_ESDHC
  171 +
  172 +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
  173 +static struct fsl_esdhc_cfg usdhc_cfg[] = {
  174 + { USDHC2_BASE_ADDR },
  175 + { USDHC4_BASE_ADDR },
  176 +};
  177 +
  178 +int board_mmc_getcd(struct mmc *mmc)
  179 +{
  180 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  181 +
  182 + switch (cfg->esdhc_base) {
  183 + case USDHC2_BASE_ADDR:
  184 + return !gpio_get_value(USDHC2_CD_GPIO);
  185 + case USDHC4_BASE_ADDR:
  186 + return 1; /* eMMC/uSDHC4 is always present */
  187 + }
  188 +
  189 + return 0;
  190 +}
  191 +
  192 +int board_mmc_init(bd_t *bis)
  193 +{
  194 + int i, ret;
  195 +
  196 + /*
  197 + * According to the board_mmc_init() the following map is done:
  198 + * (U-Boot device node) (Physical Port)
  199 + * mmc0 micro SD
  200 + * mmc2 eMMC
  201 + */
  202 + gpio_direction_input(USDHC2_CD_GPIO);
  203 +
  204 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  205 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  206 +
  207 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  208 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  209 + if (ret)
  210 + return ret;
  211 + }
  212 +
  213 + return 0;
  214 +}
  215 +#endif
  216 +
  217 +#ifdef CONFIG_USB_EHCI_MX6
  218 +static void setup_usb(void)
  219 +{
  220 + /*
  221 + * Set daisy chain for otg_pin_id on MX6Q.
  222 + * For MX6DL, this bit is reserved.
  223 + */
  224 + imx_iomux_set_gpr_register(1, 13, 1, 0);
  225 +}
  226 +
  227 +int board_usb_phy_mode(int port)
  228 +{
  229 + if (port == 1)
  230 + return USB_INIT_HOST;
  231 + else
  232 + return USB_INIT_DEVICE;
  233 +}
  234 +
  235 +int board_ehci_power(int port, int on)
  236 +{
  237 + switch (port) {
  238 + case 0:
  239 + break;
  240 + case 1:
  241 + gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
  242 + break;
  243 + default:
  244 + printf("MXC USB port %d not yet supported\n", port);
  245 + return -EINVAL;
  246 + }
  247 +
  248 + return 0;
  249 +}
  250 +#endif
  251 +
  252 +int board_early_init_f(void)
  253 +{
  254 +#ifdef CONFIG_USB_EHCI_MX6
  255 + setup_usb();
  256 +#endif
  257 +
  258 + return 0;
  259 +}
  260 +
  261 +int board_init(void)
  262 +{
  263 + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  264 +
  265 + /* address of boot parameters */
  266 + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  267 +
  268 + /* Enable eim_slow clocks */
  269 + setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
  270 +
  271 + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info0);
  272 + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info1);
  273 +
  274 + return 0;
  275 +}
  276 +
  277 +#ifdef CONFIG_CMD_BMODE
  278 +static const struct boot_mode board_boot_modes[] = {
  279 + /* 4 bit bus width */
  280 + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  281 + /* 8 bit bus width */
  282 + {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
  283 + {NULL, 0},
  284 +};
  285 +#endif
  286 +
  287 +int board_late_init(void)
  288 +{
  289 +#ifdef CONFIG_CMD_BMODE
  290 + add_board_boot_modes(board_boot_modes);
  291 +#endif
  292 +
  293 + env_set("boardname", "kp-tpc");
  294 + env_set("boardsoc", "imx6q");
  295 + return 0;
  296 +}
  297 +
  298 +int checkboard(void)
  299 +{
  300 + puts("Board: K+P KP_IMX6Q_TPC i.MX6Q\n");
  301 + return 0;
  302 +}
board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
Diff comments   View file @ ebca902
  1 +/*
  2 + * K+P iMX6Q KP_IMX6Q_TPC board configuration
  3 + *
  4 + * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <asm/arch/clock.h>
  11 +#include <asm/arch/crm_regs.h>
  12 +#include <asm/arch/imx-regs.h>
  13 +#include <asm/arch/iomux.h>
  14 +#include <asm/arch/mx6-ddr.h>
  15 +#include <asm/arch/mx6-pins.h>
  16 +#include <asm/arch/sys_proto.h>
  17 +#include <asm/gpio.h>
  18 +#include <asm/mach-imx/boot_mode.h>
  19 +#include <asm/mach-imx/iomux-v3.h>
  20 +#include <asm/mach-imx/mxc_i2c.h>
  21 +#include <asm/io.h>
  22 +#include <errno.h>
  23 +#include <fuse.h>
  24 +#include <fsl_esdhc.h>
  25 +#include <i2c.h>
  26 +#include <mmc.h>
  27 +#include <spl.h>
  28 +
  29 +#define UART_PAD_CTRL \
  30 + (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  31 + PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  32 +
  33 +#define USDHC_PAD_CTRL \
  34 + (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  35 + PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  36 +
  37 +DECLARE_GLOBAL_DATA_PTR;
  38 +
  39 +static void ccgr_init(void)
  40 +{
  41 + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  42 +
  43 + writel(0x00C03F3F, &ccm->CCGR0);
  44 + writel(0x0030FC03, &ccm->CCGR1);
  45 + writel(0x0FFFC000, &ccm->CCGR2);
  46 + writel(0x3FF00000, &ccm->CCGR3);
  47 + writel(0x00FFF300, &ccm->CCGR4);
  48 + writel(0x0F0000C3, &ccm->CCGR5);
  49 + writel(0x000003FF, &ccm->CCGR6);
  50 +}
  51 +
  52 +/* onboard microSD */
  53 +static iomux_v3_cfg_t const usdhc2_pads[] = {
  54 + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  55 + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  56 + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  57 + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  58 + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  59 + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  60 + IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  61 +};
  62 +
  63 +/* eMMC */
  64 +static iomux_v3_cfg_t const usdhc4_pads[] = {
  65 + IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  66 + IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  67 + IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  68 + IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  69 + IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  70 + IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  71 + IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  72 + IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  73 + IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  74 + IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  75 +};
  76 +
  77 +/* SD */
  78 +static void setup_iomux_sd(void)
  79 +{
  80 + SETUP_IOMUX_PADS(usdhc2_pads);
  81 + SETUP_IOMUX_PADS(usdhc4_pads);
  82 +}
  83 +
  84 +/* UART */
  85 +static iomux_v3_cfg_t const uart1_pads[] = {
  86 + IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  87 + IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  88 +};
  89 +
  90 +static void setup_iomux_uart(void)
  91 +{
  92 + SETUP_IOMUX_PADS(uart1_pads);
  93 +}
  94 +
  95 +/* USB */
  96 +static iomux_v3_cfg_t const usb_pads[] = {
  97 + IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
  98 + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  99 +};
  100 +
  101 +static void setup_iomux_usb(void)
  102 +{
  103 + SETUP_IOMUX_PADS(usb_pads);
  104 +}
  105 +
  106 +/* DDR3 */
  107 +static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
  108 + .dram_sdclk_0 = 0x00000030,
  109 + .dram_sdclk_1 = 0x00000030,
  110 + .dram_cas = 0x00000030,
  111 + .dram_ras = 0x00000030,
  112 + .dram_reset = 0x00000030,
  113 + .dram_sdcke0 = 0x00003000,
  114 + .dram_sdcke1 = 0x00003000,
  115 + .dram_sdba2 = 0x00000000,
  116 + .dram_sdodt0 = 0x00000030,
  117 + .dram_sdodt1 = 0x00000030,
  118 +
  119 + .dram_sdqs0 = 0x00000018,
  120 + .dram_sdqs1 = 0x00000018,
  121 + .dram_sdqs2 = 0x00000018,
  122 + .dram_sdqs3 = 0x00000018,
  123 + .dram_sdqs4 = 0x00000018,
  124 + .dram_sdqs5 = 0x00000018,
  125 + .dram_sdqs6 = 0x00000018,
  126 + .dram_sdqs7 = 0x00000018,
  127 +
  128 + .dram_dqm0 = 0x00000018,
  129 + .dram_dqm1 = 0x00000018,
  130 + .dram_dqm2 = 0x00000018,
  131 + .dram_dqm3 = 0x00000018,
  132 + .dram_dqm4 = 0x00000018,
  133 + .dram_dqm5 = 0x00000018,
  134 + .dram_dqm6 = 0x00000018,
  135 + .dram_dqm7 = 0x00000018,
  136 +};
  137 +
  138 +static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
  139 + .grp_ddr_type = 0x000c0000,
  140 + .grp_ddrmode_ctl = 0x00020000,
  141 + .grp_ddrpke = 0x00000000,
  142 + .grp_addds = 0x00000030,
  143 + .grp_ctlds = 0x00000030,
  144 + .grp_ddrmode = 0x00020000,
  145 + .grp_b0ds = 0x00000018,
  146 + .grp_b1ds = 0x00000018,
  147 + .grp_b2ds = 0x00000018,
  148 + .grp_b3ds = 0x00000018,
  149 + .grp_b4ds = 0x00000018,
  150 + .grp_b5ds = 0x00000018,
  151 + .grp_b6ds = 0x00000018,
  152 + .grp_b7ds = 0x00000018,
  153 +};
  154 +
  155 +static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
  156 + .p0_mpwldectrl0 = 0x001F001F,
  157 + .p0_mpwldectrl1 = 0x001F001F,
  158 + .p1_mpwldectrl0 = 0x001F001F,
  159 + .p1_mpwldectrl1 = 0x001F001F,
  160 + .p0_mpdgctrl0 = 0x43270338,
  161 + .p0_mpdgctrl1 = 0x03200314,
  162 + .p1_mpdgctrl0 = 0x431A032F,
  163 + .p1_mpdgctrl1 = 0x03200263,
  164 + .p0_mprddlctl = 0x4B434748,
  165 + .p1_mprddlctl = 0x4445404C,
  166 + .p0_mpwrdlctl = 0x38444542,
  167 + .p1_mpwrdlctl = 0x4935493A,
  168 +};
  169 +
  170 +/* MT41K256M16 (4Gb density) */
  171 +static const struct mx6_ddr3_cfg mt41k256m16 = {
  172 + .mem_speed = 1600,
  173 + .density = 4,
  174 + .width = 16,
  175 + .banks = 8,
  176 + .rowaddr = 15,
  177 + .coladdr = 10,
  178 + .pagesz = 2,
  179 + .trcd = 1375,
  180 + .trcmin = 4875,
  181 + .trasmin = 3500,
  182 +};
  183 +
  184 +#ifdef CONFIG_MX6_DDRCAL
  185 +static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
  186 +{
  187 + struct mx6_mmdc_calibration calibration = {0};
  188 +
  189 + mmdc_read_calibration(sysinfo, &calibration);
  190 +
  191 + debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
  192 + debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
  193 + debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
  194 + debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
  195 + debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
  196 + debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
  197 + debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
  198 + debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
  199 + debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
  200 + debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
  201 + debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
  202 + debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
  203 +}
  204 +
  205 +static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
  206 +{
  207 + int ret;
  208 +
  209 + /* Perform DDR DRAM calibration */
  210 + udelay(100);
  211 + ret = mmdc_do_write_level_calibration(sysinfo);
  212 + if (ret) {
  213 + printf("DDR: Write level calibration error [%d]\n", ret);
  214 + return;
  215 + }
  216 +
  217 + ret = mmdc_do_dqs_calibration(sysinfo);
  218 + if (ret) {
  219 + printf("DDR: DQS calibration error [%d]\n", ret);
  220 + return;
  221 + }
  222 +
  223 + spl_dram_print_cal(sysinfo);
  224 +}
  225 +#endif /* CONFIG_MX6_DDRCAL */
  226 +
  227 +static void spl_dram_init(void)
  228 +{
  229 + struct mx6_ddr_sysinfo sysinfo = {
  230 + /* width of data bus:0=16,1=32,2=64 */
  231 + .dsize = 2,
  232 + /* config for full 4GB range so that get_mem_size() works */
  233 + .cs_density = 32, /* 32Gb per CS */
  234 + /* single chip select */
  235 + .ncs = 1,
  236 + .cs1_mirror = 0,
  237 + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
  238 + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
  239 + .walat = 1, /* Write additional latency */
  240 + .ralat = 5, /* Read additional latency */
  241 + .mif3_mode = 3, /* Command prediction working mode */
  242 + .bi_on = 1, /* Bank interleaving enabled */
  243 + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  244 + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  245 + .pd_fast_exit = 1, /* enable precharge power-down fast exit */
  246 + .ddr_type = DDR_TYPE_DDR3,
  247 + .refsel = 1, /* Refresh cycles at 32KHz */
  248 + .refr = 7, /* 8 refresh commands per refresh cycle */
  249 + };
  250 +
  251 + mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  252 + mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k256m16);
  253 +
  254 +#ifdef CONFIG_MX6_DDRCAL
  255 + spl_dram_perform_cal(&sysinfo);
  256 +#endif
  257 +}
  258 +
  259 +struct fsl_esdhc_cfg usdhc_cfg[] = {
  260 + {USDHC2_BASE_ADDR},
  261 + {USDHC4_BASE_ADDR},
  262 +};
  263 +
  264 +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
  265 +int board_mmc_getcd(struct mmc *mmc)
  266 +{
  267 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  268 + int ret = 0;
  269 +
  270 + switch (cfg->esdhc_base) {
  271 + case USDHC2_BASE_ADDR:
  272 + ret = !gpio_get_value(USDHC2_CD_GPIO);
  273 + break;
  274 + case USDHC4_BASE_ADDR:
  275 + ret = 1; /* eMMC/uSDHC4 is always present */
  276 + break;
  277 + }
  278 +
  279 + return ret;
  280 +}
  281 +
  282 +int board_mmc_init(bd_t *bd)
  283 +{
  284 + struct src *psrc = (struct src *)SRC_BASE_ADDR;
  285 + unsigned int reg = readl(&psrc->sbmr1) >> 11;
  286 + /*
  287 + * Upon reading BOOT_CFG register the following map is done:
  288 + * Bit 11 and 12 of BOOT_CFG register can determine the current
  289 + * mmc port
  290 + * 0x1 SD1
  291 + * 0x3 SD4
  292 + */
  293 +
  294 + switch (reg & 0x3) {
  295 + case 0x1:
  296 + SETUP_IOMUX_PADS(usdhc2_pads);
  297 + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
  298 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  299 + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  300 + break;
  301 + case 0x3:
  302 + SETUP_IOMUX_PADS(usdhc4_pads);
  303 + usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
  304 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  305 + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  306 + break;
  307 + }
  308 +
  309 + return fsl_esdhc_initialize(bd, &usdhc_cfg[0]);
  310 +}
  311 +
  312 +void board_init_f(ulong dummy)
  313 +{
  314 + /* setup AIPS and disable watchdog */
  315 + arch_cpu_init();
  316 +
  317 + ccgr_init();
  318 + gpr_init();
  319 +
  320 + /* setup GP timer */
  321 + timer_init();
  322 +
  323 + setup_iomux_sd();
  324 + setup_iomux_uart();
  325 + setup_iomux_usb();
  326 +
  327 + /* UART clocks enabled and gd valid - init serial console */
  328 + preloader_console_init();
  329 +
  330 + /* DDR initialization */
  331 + spl_dram_init();
  332 +
  333 + /* Clear the BSS. */
  334 + memset(__bss_start, 0, __bss_end - __bss_start);
  335 +
  336 + /* load/boot image from boot device */
  337 + board_init_r(NULL, 0);
  338 +}
board/solidrun/mx6cuboxi/mx6cuboxi.c
Diff comments   View file @ ebca902
... ... @@ -428,7 +428,7 @@
428 428 .dram_sdclk_1 = 0x00020030,
429 429 .dram_cas = 0x00020030,
430 430 .dram_ras = 0x00020030,
431   - .dram_reset = 0x00020030,
  431 + .dram_reset = 0x000c0030,
432 432 .dram_sdcke0 = 0x00003000,
433 433 .dram_sdcke1 = 0x00003000,
434 434 .dram_sdba2 = 0x00000000,
... ... @@ -584,7 +584,6 @@
584 584 .trcd = 1375,
585 585 .trcmin = 4875,
586 586 .trasmin = 3500,
587   - .SRT = 1,
588 587 };
589 588  
590 589 static struct mx6_ddr3_cfg mem_ddr_4g = {
board/wandboard/wandboard.c
Diff comments   View file @ ebca902
... ... @@ -28,7 +28,6 @@
28 28 #include <miiphy.h>
29 29 #include <netdev.h>
30 30 #include <phy.h>
31   -#include <input.h>
32 31 #include <i2c.h>
33 32 #include <power/pmic.h>
34 33 #include <power/pfuze100_pmic.h>
... ... @@ -23,6 +23,8 @@
23 23 #include <power/pmic.h>
24 24 #include <power/pfuze3000_pmic.h>
25 25 #include "../freescale/common/pfuze.h"
  26 +#include <asm/setup.h>
  27 +#include <asm/bootm.h>
26 28  
27 29 DECLARE_GLOBAL_DATA_PTR;
28 30  
... ... @@ -186,6 +188,10 @@
186 188 int board_late_init(void)
187 189 {
188 190 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  191 +#ifdef CONFIG_SERIAL_TAG
  192 + struct tag_serialnr serialnr;
  193 + char serial_string[0x20];
  194 +#endif
189 195  
190 196 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
191 197  
... ... @@ -196,6 +202,14 @@
196 202 * since we use PMIC_PWRON to reset the board.
197 203 */
198 204 clrsetbits_le16(&wdog->wcr, 0, 0x10);
  205 +
  206 +#ifdef CONFIG_SERIAL_TAG
  207 + /* Set serial# standard environment variable based on OTP settings */
  208 + get_board_serial(&serialnr);
  209 + snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x",
  210 + serialnr.low, serialnr.high);
  211 + env_set("serial#", serial_string);
  212 +#endif
199 213  
200 214 return 0;
201 215 }
configs/dms-ba16-1g_defconfig
Diff comments   View file @ ebca902
... ... @@ -33,6 +33,7 @@
33 33 CONFIG_FSL_ESDHC=y
34 34 CONFIG_SPI_FLASH=y
35 35 CONFIG_SPI_FLASH_STMICRO=y
  36 +CONFIG_SPI_FLASH_WINBOND=y
36 37 CONFIG_PHYLIB=y
37 38 CONFIG_MXC_SPI=y
38 39 CONFIG_USB=y
configs/dms-ba16_defconfig
Diff comments   View file @ ebca902
... ... @@ -32,6 +32,7 @@
32 32 CONFIG_FSL_ESDHC=y
33 33 CONFIG_SPI_FLASH=y
34 34 CONFIG_SPI_FLASH_STMICRO=y
  35 +CONFIG_SPI_FLASH_WINBOND=y
35 36 CONFIG_PHYLIB=y
36 37 CONFIG_MXC_SPI=y
37 38 CONFIG_USB=y
configs/imx31_phycore_defconfig
View file @ ebca902
1   -CONFIG_ARM=y
2   -CONFIG_TARGET_IMX31_PHYCORE=y
3   -CONFIG_SYS_TEXT_BASE=0xA0000000
4   -CONFIG_BOOTDELAY=3
5   -# CONFIG_AUTO_COMPLETE is not set
6   -CONFIG_SYS_PROMPT="uboot> "
7   -CONFIG_CMD_IMLS=y
8   -CONFIG_CMD_EEPROM=y
9   -CONFIG_CMD_I2C=y
10   -# CONFIG_CMD_SETEXPR is not set
11   -CONFIG_CMD_PING=y
12   -CONFIG_MTDPARTS_DEFAULT="mtdparts=physmap-flash.0:128k(uboot)ro,1536k(kernel),-(root)"
13   -CONFIG_ENV_IS_IN_EEPROM=y
14   -# CONFIG_MMC is not set
15   -CONFIG_MTD_NOR_FLASH=y
16   -CONFIG_NETDEVICES=y
17   -CONFIG_SMC911X=y
18   -CONFIG_SMC911X_BASE=0xa8000000
19   -CONFIG_SMC911X_32_BIT=y
configs/imx31_phycore_eet_defconfig
View file @ ebca902
1   -CONFIG_ARM=y
2   -CONFIG_TARGET_IMX31_PHYCORE_EET=y
3   -CONFIG_SYS_TEXT_BASE=0xA0000000
4   -CONFIG_BOOTDELAY=3
5   -# CONFIG_CONSOLE_MUX is not set
6   -CONFIG_SYS_CONSOLE_IS_IN_ENV=y
7   -# CONFIG_AUTO_COMPLETE is not set
8   -CONFIG_CMD_IMLS=y
9   -CONFIG_CMD_EEPROM=y
10   -CONFIG_CMD_I2C=y
11   -CONFIG_CMD_SPI=y
12   -# CONFIG_CMD_SETEXPR is not set
13   -CONFIG_CMD_PING=y
14   -CONFIG_CMD_BMP=y
15   -CONFIG_MTDPARTS_DEFAULT="mtdparts=physmap-flash.0:128k(uboot)ro,1536k(kernel),-(root)"
16   -CONFIG_ENV_IS_IN_EEPROM=y
17   -CONFIG_MXC_GPIO=y
18   -# CONFIG_MMC is not set
19   -CONFIG_MTD_NOR_FLASH=y
20   -CONFIG_NETDEVICES=y
21   -CONFIG_SMC911X=y
22   -CONFIG_SMC911X_BASE=0xa8000000
23   -CONFIG_SMC911X_32_BIT=y
24   -CONFIG_MXC_SPI=y
25   -CONFIG_VIDEO=y
configs/kp_imx6q_tpc_defconfig
Diff comments   View file @ ebca902
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_MX6=y
  3 +CONFIG_SYS_TEXT_BASE=0x17800000
  4 +CONFIG_SPL_GPIO_SUPPORT=y
  5 +CONFIG_SPL_LIBCOMMON_SUPPORT=y
  6 +CONFIG_SPL_LIBGENERIC_SUPPORT=y
  7 +CONFIG_MX6_DDRCAL=y
  8 +CONFIG_TARGET_KP_IMX6Q_TPC=y
  9 +CONFIG_SPL_MMC_SUPPORT=y
  10 +CONFIG_SPL_SERIAL_SUPPORT=y
  11 +CONFIG_SPL_WATCHDOG_SUPPORT=y
  12 +CONFIG_DISTRO_DEFAULTS=y
  13 +CONFIG_FIT=y
  14 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
  15 +CONFIG_BOOTDELAY=3
  16 +# CONFIG_USE_BOOTCOMMAND is not set
  17 +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
  18 +CONFIG_SPL=y
  19 +CONFIG_SPL_RAW_IMAGE_SUPPORT=y
  20 +CONFIG_AUTOBOOT_KEYED=y
  21 +CONFIG_AUTOBOOT_STOP_STR="."
  22 +# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
  23 +# CONFIG_CMD_ELF is not set
  24 +# CONFIG_CMD_FLASH is not set
  25 +CONFIG_CMD_GPIO=y
  26 +CONFIG_CMD_I2C=y
  27 +CONFIG_CMD_MMC=y
  28 +CONFIG_CMD_USB=y
  29 +CONFIG_CMD_CACHE=y
  30 +CONFIG_CMD_TIME=y
  31 +CONFIG_CMD_EXT4_WRITE=y
  32 +# CONFIG_ISO_PARTITION is not set
  33 +# CONFIG_EFI_PARTITION is not set
  34 +CONFIG_ENV_IS_IN_MMC=y
  35 +CONFIG_PHYLIB=y
  36 +CONFIG_PHY_ATHEROS=y
  37 +CONFIG_NETDEVICES=y
  38 +CONFIG_FEC_MXC=y
  39 +CONFIG_IMX_THERMAL=y
  40 +CONFIG_USB=y
  41 +CONFIG_USB_STORAGE=y
  42 +CONFIG_OF_LIBFDT=y
configs/mx31ads_defconfig
View file @ ebca902
1   -CONFIG_ARM=y
2   -CONFIG_TARGET_MX31ADS=y
3   -CONFIG_SYS_TEXT_BASE=0xA0000000
4   -# CONFIG_AUTO_COMPLETE is not set
5   -CONFIG_CMD_IMLS=y
6   -CONFIG_CMD_SPI=y
7   -# CONFIG_CMD_SETEXPR is not set
8   -CONFIG_CMD_DHCP=y
9   -CONFIG_CMD_PING=y
10   -CONFIG_CMD_DATE=y
11   -CONFIG_ENV_IS_IN_FLASH=y
12   -CONFIG_MXC_GPIO=y
13   -# CONFIG_MMC is not set
14   -CONFIG_MTD_NOR_FLASH=y
15   -CONFIG_MXC_SPI=y
configs/pico-imx7d_defconfig
Diff comments   View file @ ebca902
... ... @@ -23,6 +23,7 @@
23 23 CONFIG_CMD_EXT4_WRITE=y
24 24 CONFIG_CMD_FAT=y
25 25 CONFIG_FSL_ESDHC=y
  26 +CONFIG_CMD_FS_GENERIC=y
26 27 CONFIG_PHYLIB=y
27 28 CONFIG_USB=y
28 29 CONFIG_USB_EHCI_HCD=y
... ... @@ -33,12 +33,12 @@
33 33 Data Size: 327680 Bytes = 320.00 kB = 0.31 MB
34 34 Load Address: 177ff420
35 35 Entry Point: 17800000
36   -HAB Blocks: 177ff400 00000000 0004dc00
37   - ^^^^^^^^ ^^^^^^^^ ^^^^^^^^
38   - | | |
39   - | | -------- (1)
40   - | |
41   - | ------------------- (2)
  36 +HAB Blocks: 0x177ff400 0x00000000 0x0004dc00
  37 + ^^^^^^^^^^ ^^^^^^^^^^ ^^^^^^^^^^
  38 + | | |
  39 + | | ----- (1)
  40 + | |
  41 + | ---------------- (2)
42 42 |
43 43 --------------------------- (3)
44 44  
... ... @@ -78,7 +78,7 @@
78 78 Data Size: 61440 Bytes = 60.00 kB = 0.06 MB
79 79 Load Address: 00907420
80 80 Entry Point: 00908000
81   - HAB Blocks: 00907400 00000000 0000cc00
  81 + HAB Blocks: 0x00907400 0x00000000 0x0000cc00
82 82  
83 83 Example Output of the u-boot-ivt.img (firmware_ivt) creation:
84 84 Image Name: U-Boot 2016.11-rc1-31589-g2a4411
... ... @@ -149,12 +149,175 @@
149 149 both 7-bit and 10-bit addresses.
150 150  
151 151 config SYS_I2C_MXC
152   - bool "NXP i.MX I2C driver"
153   - depends on MX6
  152 + bool "NXP MXC I2C driver"
154 153 help
155   - Add support for the NXP i.MX I2C driver. This supports upto for bus
  154 + Add support for the NXP I2C driver. This supports upto for bus
156 155 channels and operating on standard mode upto 100 kbits/s and fast
157 156 mode upto 400 kbits/s.
  157 +
  158 +if SYS_I2C_MXC
  159 +config SYS_I2C_MXC_I2C1
  160 + bool "NXP MXC I2C1"
  161 + help
  162 + Add support for NXP MXC I2C Controller 1.
  163 + Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A
  164 +
  165 +config SYS_I2C_MXC_I2C2
  166 + bool "NXP MXC I2C2"
  167 + help
  168 + Add support for NXP MXC I2C Controller 2.
  169 + Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A
  170 +
  171 +config SYS_I2C_MXC_I2C3
  172 + bool "NXP MXC I2C3"
  173 + help
  174 + Add support for NXP MXC I2C Controller 3.
  175 + Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A
  176 +
  177 +config SYS_I2C_MXC_I2C4
  178 + bool "NXP MXC I2C4"
  179 + help
  180 + Add support for NXP MXC I2C Controller 4.
  181 + Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A
  182 +
  183 +config SYS_I2C_MXC_I2C5
  184 + bool "NXP MXC I2C5"
  185 + help
  186 + Add support for NXP MXC I2C Controller 5.
  187 + Required for SoCs which have I2C MXC controller 5 eg LX2160A
  188 +
  189 +config SYS_I2C_MXC_I2C6
  190 + bool "NXP MXC I2C6"
  191 + help
  192 + Add support for NXP MXC I2C Controller 6.
  193 + Required for SoCs which have I2C MXC controller 6 eg LX2160A
  194 +
  195 +config SYS_I2C_MXC_I2C7
  196 + bool "NXP MXC I2C7"
  197 + help
  198 + Add support for NXP MXC I2C Controller 7.
  199 + Required for SoCs which have I2C MXC controller 7 eg LX2160A
  200 +
  201 +config SYS_I2C_MXC_I2C8
  202 + bool "NXP MXC I2C8"
  203 + help
  204 + Add support for NXP MXC I2C Controller 8.
  205 + Required for SoCs which have I2C MXC controller 8 eg LX2160A
  206 +endif
  207 +
  208 +if SYS_I2C_MXC_I2C1
  209 +config SYS_MXC_I2C1_SPEED
  210 + int "I2C Channel 1 speed"
  211 + default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
  212 + default 100000
  213 + help
  214 + MXC I2C Channel 1 speed
  215 +
  216 +config SYS_MXC_I2C1_SLAVE
  217 + int "I2C1 Slave"
  218 + default 0
  219 + help
  220 + MXC I2C1 Slave
  221 +endif
  222 +
  223 +if SYS_I2C_MXC_I2C2
  224 +config SYS_MXC_I2C2_SPEED
  225 + int "I2C Channel 2 speed"
  226 + default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
  227 + default 100000
  228 + help
  229 + MXC I2C Channel 2 speed
  230 +
  231 +config SYS_MXC_I2C2_SLAVE
  232 + int "I2C2 Slave"
  233 + default 0
  234 + help
  235 + MXC I2C2 Slave
  236 +endif
  237 +
  238 +if SYS_I2C_MXC_I2C3
  239 +config SYS_MXC_I2C3_SPEED
  240 + int "I2C Channel 3 speed"
  241 + default 100000
  242 + help
  243 + MXC I2C Channel 3 speed
  244 +
  245 +config SYS_MXC_I2C3_SLAVE
  246 + int "I2C3 Slave"
  247 + default 0
  248 + help
  249 + MXC I2C3 Slave
  250 +endif
  251 +
  252 +if SYS_I2C_MXC_I2C4
  253 +config SYS_MXC_I2C4_SPEED
  254 + int "I2C Channel 4 speed"
  255 + default 100000
  256 + help
  257 + MXC I2C Channel 4 speed
  258 +
  259 +config SYS_MXC_I2C4_SLAVE
  260 + int "I2C4 Slave"
  261 + default 0
  262 + help
  263 + MXC I2C4 Slave
  264 +endif
  265 +
  266 +if SYS_I2C_MXC_I2C5
  267 +config SYS_MXC_I2C5_SPEED
  268 + int "I2C Channel 5 speed"
  269 + default 100000
  270 + help
  271 + MXC I2C Channel 5 speed
  272 +
  273 +config SYS_MXC_I2C5_SLAVE
  274 + int "I2C5 Slave"
  275 + default 0
  276 + help
  277 + MXC I2C5 Slave
  278 +endif
  279 +
  280 +if SYS_I2C_MXC_I2C6
  281 +config SYS_MXC_I2C6_SPEED
  282 + int "I2C Channel 6 speed"
  283 + default 100000
  284 + help
  285 + MXC I2C Channel 6 speed
  286 +
  287 +config SYS_MXC_I2C6_SLAVE
  288 + int "I2C6 Slave"
  289 + default 0
  290 + help
  291 + MXC I2C6 Slave
  292 +endif
  293 +
  294 +if SYS_I2C_MXC_I2C7
  295 +config SYS_MXC_I2C7_SPEED
  296 + int "I2C Channel 7 speed"
  297 + default 100000
  298 + help
  299 + MXC I2C Channel 7 speed
  300 +
  301 +config SYS_MXC_I2C7_SLAVE
  302 + int "I2C7 Slave"
  303 + default 0
  304 + help
  305 + MXC I2C7 Slave
  306 +endif
  307 +
  308 +if SYS_I2C_MXC_I2C8
  309 +config SYS_MXC_I2C8_SPEED
  310 + int "I2C Channel 8 speed"
  311 + default 100000
  312 + help
  313 + MXC I2C Channel 8 speed
  314 +
  315 +config SYS_MXC_I2C8_SLAVE
  316 + int "I2C8 Slave"
  317 + default 0
  318 + help
  319 + MXC I2C8 Slave
  320 +endif
158 321  
159 322 config SYS_I2C_OMAP24XX
160 323 bool "TI OMAP2+ I2C driver"
drivers/i2c/mxc_i2c.c
Diff comments   View file @ ebca902
... ... @@ -589,6 +589,22 @@
589 589 #define I2C4_BASE_ADDR 0
590 590 #endif
591 591  
  592 +#if !defined(I2C5_BASE_ADDR)
  593 +#define I2C5_BASE_ADDR 0
  594 +#endif
  595 +
  596 +#if !defined(I2C6_BASE_ADDR)
  597 +#define I2C6_BASE_ADDR 0
  598 +#endif
  599 +
  600 +#if !defined(I2C7_BASE_ADDR)
  601 +#define I2C7_BASE_ADDR 0
  602 +#endif
  603 +
  604 +#if !defined(I2C8_BASE_ADDR)
  605 +#define I2C8_BASE_ADDR 0
  606 +#endif
  607 +
592 608 static struct mxc_i2c_bus mxc_i2c_buses[] = {
593 609 #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
594 610 defined(CONFIG_FSL_LAYERSCAPE)
595 611  
... ... @@ -596,11 +612,19 @@
596 612 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
597 613 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
598 614 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
  615 + { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
  616 + { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
  617 + { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
  618 + { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
599 619 #else
600 620 { 0, I2C1_BASE_ADDR, 0 },
601 621 { 1, I2C2_BASE_ADDR, 0 },
602 622 { 2, I2C3_BASE_ADDR, 0 },
603 623 { 3, I2C4_BASE_ADDR, 0 },
  624 + { 4, I2C5_BASE_ADDR, 0 },
  625 + { 5, I2C6_BASE_ADDR, 0 },
  626 + { 6, I2C7_BASE_ADDR, 0 },
  627 + { 7, I2C8_BASE_ADDR, 0 },
604 628 #endif
605 629 };
606 630  
... ... @@ -736,6 +760,38 @@
736 760 mxc_i2c_set_bus_speed,
737 761 CONFIG_SYS_MXC_I2C4_SPEED,
738 762 CONFIG_SYS_MXC_I2C4_SLAVE, 3)
  763 +#endif
  764 +
  765 +#ifdef CONFIG_SYS_I2C_MXC_I2C5
  766 +U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe,
  767 + mxc_i2c_read, mxc_i2c_write,
  768 + mxc_i2c_set_bus_speed,
  769 + CONFIG_SYS_MXC_I2C5_SPEED,
  770 + CONFIG_SYS_MXC_I2C5_SLAVE, 4)
  771 +#endif
  772 +
  773 +#ifdef CONFIG_SYS_I2C_MXC_I2C6
  774 +U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe,
  775 + mxc_i2c_read, mxc_i2c_write,
  776 + mxc_i2c_set_bus_speed,
  777 + CONFIG_SYS_MXC_I2C6_SPEED,
  778 + CONFIG_SYS_MXC_I2C6_SLAVE, 5)
  779 +#endif
  780 +
  781 +#ifdef CONFIG_SYS_I2C_MXC_I2C7
  782 +U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe,
  783 + mxc_i2c_read, mxc_i2c_write,
  784 + mxc_i2c_set_bus_speed,
  785 + CONFIG_SYS_MXC_I2C7_SPEED,
  786 + CONFIG_SYS_MXC_I2C7_SLAVE, 6)
  787 +#endif
  788 +
  789 +#ifdef CONFIG_SYS_I2C_MXC_I2C8
  790 +U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe,
  791 + mxc_i2c_read, mxc_i2c_write,
  792 + mxc_i2c_set_bus_speed,
  793 + CONFIG_SYS_MXC_I2C8_SPEED,
  794 + CONFIG_SYS_MXC_I2C8_SLAVE, 7)
739 795 #endif
740 796  
741 797 #else
drivers/video/Makefile
Diff comments   View file @ ebca902
... ... @@ -30,7 +30,6 @@
30 30 obj-$(CONFIG_PXA_LCD) += pxa_lcd.o
31 31 obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o
32 32 obj-$(CONFIG_S6E8AX0) += s6e8ax0.o
33   -obj-$(CONFIG_S6E63D6) += s6e63d6.o
34 33 obj-$(CONFIG_LD9040) += ld9040.o
35 34 obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o
36 35 obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
drivers/video/s6e63d6.c
View file @ ebca902
1   -/*
2   - * Copyright (C) 2009
3   - * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -#include <common.h>
8   -#include <spi.h>
9   -#include <s6e63d6.h>
10   -
11   -/*
12   - * Each transfer is performed as:
13   - * 1. chip-select active
14   - * 2. send 8-bit start code
15   - * 3. send 16-bit data
16   - * 4. chip-select inactive
17   - */
18   -static int send_word(struct s6e63d6 *data, u8 rs, u16 word)
19   -{
20   - /*
21   - * The start byte looks like (binary):
22   - * 01110<ID><RS><R/W>
23   - * RS is 0 for index or 1 for data, and R/W is 0 for write.
24   - */
25   - u32 buf8 = 0x70 | data->id | (rs & 2);
26   - u32 buf16 = cpu_to_le16(word);
27   - u32 buf_in;
28   - int err;
29   -
30   - err = spi_xfer(data->slave, 8, &buf8, &buf_in, SPI_XFER_BEGIN);
31   - if (err)
32   - return err;
33   -
34   - return spi_xfer(data->slave, 16, &buf16, &buf_in, SPI_XFER_END);
35   -}
36   -
37   -/* Index and param differ in Register Select bit */
38   -int s6e63d6_index(struct s6e63d6 *data, u8 idx)
39   -{
40   - return send_word(data, 0, idx);
41   -}
42   -
43   -int s6e63d6_param(struct s6e63d6 *data, u16 param)
44   -{
45   - return send_word(data, 2, param);
46   -}
47   -
48   -int s6e63d6_init(struct s6e63d6 *data)
49   -{
50   - if (data->id != 0 && data->id != 4) {
51   - printf("s6e63d6: invalid ID %u\n", data->id);
52   - return 1;
53   - }
54   -
55   - data->slave = spi_setup_slave(data->bus, data->cs, 100000, SPI_MODE_3);
56   - if (!data->slave)
57   - return 1;
58   -
59   - return 0;
60   -}
include/configs/ge_bx50v3.h
Diff comments   View file @ ebca902
... ... @@ -124,6 +124,7 @@
124 124 "swappartitions=" \
125 125 "setexpr partnum 3 - ${partnum}\0" \
126 126 "failbootcmd=" \
  127 + "bx50_backlight_enable; " \
127 128 "msg=\"Monitor failed to start. Try again, or contact GE Service for support.\"; " \
128 129 "echo $msg; " \
129 130 "setenv stdout vga; " \
include/configs/imx31_phycore.h
View file @ ebca902
1   -/*
2   - * (C) Copyright 2004
3   - * Texas Instruments.
4   - * Richard Woodruff <r-woodruff2@ti.com>
5   - * Kshitij Gupta <kshitij@ti.com>
6   - *
7   - * Configuration settings for the phyCORE-i.MX31 board.
8   - *
9   - * SPDX-License-Identifier: GPL-2.0+
10   - */
11   -
12   -#ifndef __CONFIG_H
13   -#define __CONFIG_H
14   -
15   -#include <asm/arch/imx-regs.h>
16   -
17   -/* High Level Configuration Options */
18   -#define CONFIG_MX31 /* This is a mx31 */
19   -#define CONFIG_MX31_CLK32 32000
20   -
21   -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
22   -#define CONFIG_SETUP_MEMORY_TAGS
23   -#define CONFIG_INITRD_TAG
24   -
25   -/*
26   - * Size of malloc() pool
27   - */
28   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024)
29   -
30   -/*
31   - * Hardware drivers
32   - */
33   -
34   -#define CONFIG_SYS_I2C
35   -#define CONFIG_SYS_I2C_MXC
36   -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
37   -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
38   -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
39   -#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET
40   -
41   -#define CONFIG_MXC_UART
42   -#define CONFIG_MXC_UART_BASE UART1_BASE
43   -
44   -/* allow to overwrite serial and ethaddr */
45   -#define CONFIG_ENV_OVERWRITE
46   -
47   -/***********************************************************
48   - * Command definition
49   - ***********************************************************/
50   -
51   -#define CONFIG_NETMASK 255.255.255.0
52   -#define CONFIG_IPADDR 192.168.23.168
53   -#define CONFIG_SERVERIP 192.168.23.2
54   -
55   -#define CONFIG_EXTRA_ENV_SETTINGS \
56   - "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
57   - "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
58   - "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
59   - "bootargs_flash=setenv bootargs $(bootargs) " \
60   - "root=/dev/mtdblock2 rootfstype=jffs2\0" \
61   - "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \
62   - "bootcmd=run bootcmd_net\0" \
63   - "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;" \
64   - "tftpboot 0x80000000 $(uimage);bootm\0" \
65   - "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;" \
66   - "bootm 0x80000000\0" \
67   - "unlock=yes\0" \
68   - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
69   - "prg_uboot=tftpboot 0x80000000 $(uboot);" \
70   - "protect off 0xa0000000 +0x20000;" \
71   - "erase 0xa0000000 +0x20000;" \
72   - "cp.b 0x80000000 0xa0000000 $(filesize)\0" \
73   - "prg_kernel=tftpboot 0x80000000 $(uimage);" \
74   - "erase 0xa0040000 +0x180000;" \
75   - "cp.b 0x80000000 0xa0040000 $(filesize)\0" \
76   - "prg_jffs2=tftpboot 0x80000000 $(jffs2);" \
77   - "erase 0xa01c0000 0xa1ffffff;" \
78   - "cp.b 0x80000000 0xa01c0000 $(filesize)\0" \
79   - "videomode=video=ctfb:x:240,y:320,depth:16,mode:0," \
80   - "pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1," \
81   - "sync:1241513985,vmode:0\0"
82   -
83   -/*
84   - * Miscellaneous configurable options
85   - */
86   -
87   -#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
88   -#define CONFIG_SYS_MEMTEST_END 0x10000
89   -
90   -#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */
91   -
92   -/*
93   - * Physical Memory Map
94   - */
95   -#define CONFIG_NR_DRAM_BANKS 1
96   -#define PHYS_SDRAM_1 0x80000000
97   -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
98   -
99   -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
100   -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
101   -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
102   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
103   - GENERATED_GBL_DATA_SIZE)
104   -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
105   - CONFIG_SYS_GBL_DATA_OFFSET)
106   -
107   -/*
108   - * FLASH and environment organization
109   - */
110   -#define CONFIG_SYS_FLASH_BASE 0xa0000000
111   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
112   -#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max # of sectors/chip */
113   -/* Monitor at beginning of flash */
114   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
115   -
116   -#define CONFIG_ENV_OFFSET 0x00 /* env. starts here */
117   -#define CONFIG_ENV_SIZE 4096
118   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
119   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
120   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10 ms delay */
121   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* byte addr. lenght */
122   -
123   -/*
124   - * CFI FLASH driver setup
125   - */
126   -#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
127   -#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/mtd/cfi_flash.c */
128   -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */
129   -#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
130   -
131   -/*
132   - * Timeout for Flash Erase and Flash Write
133   - * timeout values are in ticks
134   - */
135   -#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ)
136   -#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ)
137   -
138   -/*
139   - * JFFS2 partitions
140   - */
141   -#define CONFIG_JFFS2_DEV "nor0"
142   -
143   -/* EET platform additions */
144   -#ifdef CONFIG_TARGET_IMX31_PHYCORE_EET
145   -#define CONFIG_HARD_SPI
146   -
147   -#define CONFIG_S6E63D6
148   -
149   -#define CONFIG_VIDEO_MX3
150   -#define CONFIG_VIDEO_LOGO
151   -#define CONFIG_SPLASH_SCREEN
152   -#define CONFIG_BMP_16BPP
153   -#endif
154   -
155   -#endif /* __CONFIG_H */
include/configs/kp_imx6q_tpc.h
Diff comments   View file @ ebca902
  1 +/*
  2 + * K+P iMX6Q KP_IMX6Q_TPC board configuration
  3 + *
  4 + * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __KP_IMX6Q_TPC_IMX6_CONFIG_H_
  10 +#define __KP_IMX6Q_TPC_IMX6_CONFIG_H_
  11 +
  12 +#include <asm/arch/imx-regs.h>
  13 +
  14 +#include "mx6_common.h"
  15 +
  16 +/* SPL */
  17 +#include "imx6_spl.h" /* common IMX6 SPL configuration */
  18 +
  19 +/* Miscellaneous configurable options */
  20 +#define CONFIG_CMDLINE_TAG
  21 +#define CONFIG_SETUP_MEMORY_TAGS
  22 +#define CONFIG_INITRD_TAG
  23 +#define CONFIG_REVISION_TAG
  24 +
  25 +#define CONFIG_BOUNCE_BUFFER
  26 +
  27 +/* Size of malloc() pool */
  28 +#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M)
  29 +
  30 +/* FEC ethernet */
  31 +#define CONFIG_MII
  32 +#define IMX_FEC_BASE ENET_BASE_ADDR
  33 +#define CONFIG_FEC_XCV_TYPE RGMII
  34 +#define CONFIG_ETHPRIME "FEC"
  35 +#define CONFIG_FEC_MXC_PHYADDR 0
  36 +#define CONFIG_ARP_TIMEOUT 200UL
  37 +
  38 +/* Fuses */
  39 +#ifdef CONFIG_CMD_FUSE
  40 +#define CONFIG_MXC_OCOTP
  41 +#endif
  42 +
  43 +/* I2C Configs */
  44 +#define CONFIG_SYS_I2C
  45 +#define CONFIG_SYS_I2C_MXC
  46 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  47 +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  48 +#define CONFIG_SYS_I2C_SPEED 100000
  49 +
  50 +/* MMC Configs */
  51 +#define CONFIG_FSL_ESDHC
  52 +#define CONFIG_FSL_USDHC
  53 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
  54 +#define CONFIG_SYS_FSL_USDHC_NUM 2
  55 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* 0 = SDHC2, 1 = SDHC4 (eMMC) */
  56 +
  57 +/* UART */
  58 +#define CONFIG_MXC_UART
  59 +#define CONFIG_MXC_UART_BASE UART1_BASE
  60 +#define CONFIG_CONS_INDEX 1
  61 +#define CONFIG_BAUDRATE 115200
  62 +
  63 +/* USB Configs */
  64 +#ifdef CONFIG_CMD_USB
  65 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  66 +#define CONFIG_USB_HOST_ETHER
  67 +#define CONFIG_USB_ETHER_ASIX
  68 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
  69 +#define CONFIG_MXC_USB_FLAGS 0
  70 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
  71 +#endif
  72 +
  73 +/* Watchdog */
  74 +#define CONFIG_HW_WATCHDOG
  75 +#define CONFIG_IMX_WATCHDOG
  76 +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
  77 +
  78 +/* allow to overwrite serial and ethaddr */
  79 +#define CONFIG_ENV_OVERWRITE
  80 +
  81 +#define CONFIG_LOADADDR 0x12000000
  82 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  83 +
  84 +#ifndef CONFIG_SPL_BUILD
  85 +#define CONFIG_EXTRA_ENV_SETTINGS \
  86 + "console=ttymxc0,115200\0" \
  87 + "fdt_addr=0x18000000\0" \
  88 + "fdt_high=0xffffffff\0" \
  89 + "initrd_high=0xffffffff\0" \
  90 + "kernel_addr_r=0x10008000\0" \
  91 + "fdt_addr_r=0x13000000\0" \
  92 + "ramdisk_addr_r=0x18000000\0" \
  93 + "scriptaddr=0x14000000\0" \
  94 + "kernel_file=fitImage\0"\
  95 + "rdinit=/sbin/init\0" \
  96 + "addinitrd=setenv bootargs ${bootargs} rdinit=${rdinit} ${debug} \0" \
  97 + "fit_config=mx6q_tpc70_conf\0" \
  98 + "upd_image=st.4k\0" \
  99 + "updargs=setenv bootargs console=${console} ${smp}"\
  100 + "rdinit=${rdinit} ${debug} ${displayargs}\0" \
  101 + "loadusb=usb start; " \
  102 + "fatload usb 0 ${loadaddr} ${upd_image}\0" \
  103 + "usbupd=echo Booting update from usb ...; " \
  104 + "setenv bootargs; " \
  105 + "run updargs; " \
  106 + "run loadusb; " \
  107 + "bootm ${loadaddr}#${fit_config}\0" \
  108 + BOOTENV
  109 +
  110 +#define CONFIG_BOOTCOMMAND "run usbupd; run distro_bootcmd"
  111 +
  112 +#define BOOT_TARGET_DEVICES(func) \
  113 + func(MMC, mmc, 0) \
  114 + func(MMC, mmc, 1) \
  115 + func(USB, usb, 0) \
  116 + func(DHCP, dhcp, na)
  117 +
  118 +#include <config_distro_bootcmd.h>
  119 +#endif
  120 +
  121 +/* Physical Memory Map */
  122 +#define CONFIG_NR_DRAM_BANKS 1
  123 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
  124 +
  125 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
  126 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
  127 +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
  128 +
  129 +#define CONFIG_SYS_INIT_SP_OFFSET \
  130 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  131 +
  132 +#define CONFIG_SYS_INIT_SP_ADDR \
  133 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  134 +
  135 +/* Environment */
  136 +#define CONFIG_ENV_SIZE (SZ_8K)
  137 +#define CONFIG_ENV_OFFSET 0x100000
  138 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
  139 +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
  140 +
  141 +#endif /* __KP_IMX6Q_TPC_IMX6_CONFIG_H_ */
include/configs/ls1012a_common.h
Diff comments   View file @ ebca902
... ... @@ -75,9 +75,6 @@
75 75  
76 76 /* I2C */
77 77 #define CONFIG_SYS_I2C
78   -#define CONFIG_SYS_I2C_MXC
79   -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
80   -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
81 78  
82 79 #define CONFIG_SYS_NS16550_SERIAL
83 80 #define CONFIG_SYS_NS16550_REG_SIZE 1
include/configs/ls1043a_common.h
Diff comments   View file @ ebca902
... ... @@ -147,11 +147,6 @@
147 147  
148 148 /* I2C */
149 149 #define CONFIG_SYS_I2C
150   -#define CONFIG_SYS_I2C_MXC
151   -#define CONFIG_SYS_I2C_MXC_I2C1
152   -#define CONFIG_SYS_I2C_MXC_I2C2
153   -#define CONFIG_SYS_I2C_MXC_I2C3
154   -#define CONFIG_SYS_I2C_MXC_I2C4
155 150  
156 151 /* PCIe */
157 152 #ifndef SPL_NO_PCIE
include/configs/ls1046a_common.h
Diff comments   View file @ ebca902
... ... @@ -125,11 +125,6 @@
125 125  
126 126 /* I2C */
127 127 #define CONFIG_SYS_I2C
128   -#define CONFIG_SYS_I2C_MXC
129   -#define CONFIG_SYS_I2C_MXC_I2C1
130   -#define CONFIG_SYS_I2C_MXC_I2C2
131   -#define CONFIG_SYS_I2C_MXC_I2C3
132   -#define CONFIG_SYS_I2C_MXC_I2C4
133 128  
134 129 /* PCIe */
135 130 #define CONFIG_PCIE1 /* PCIE controller 1 */
include/configs/ls1088a_common.h
Diff comments   View file @ ebca902
... ... @@ -67,11 +67,6 @@
67 67  
68 68 /* I2C */
69 69 #define CONFIG_SYS_I2C
70   -#define CONFIG_SYS_I2C_MXC
71   -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
72   -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
73   -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
74   -#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
75 70  
76 71 /* Serial Port */
77 72 #define CONFIG_SYS_NS16550_SERIAL
include/configs/ls2080a_common.h
Diff comments   View file @ ebca902
... ... @@ -77,11 +77,6 @@
77 77  
78 78 /* I2C */
79 79 #define CONFIG_SYS_I2C
80   -#define CONFIG_SYS_I2C_MXC
81   -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
82   -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
83   -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
84   -#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
85 80  
86 81 /* Serial Port */
87 82 #define CONFIG_SYS_NS16550_SERIAL
include/configs/ls2080a_emu.h
Diff comments   View file @ ebca902
... ... @@ -12,9 +12,6 @@
12 12 #define CONFIG_SYS_CLK_FREQ 100000000
13 13 #define CONFIG_DDR_CLK_FREQ 133333333
14 14  
15   -#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
16   -#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
17   -
18 15 #define CONFIG_DDR_SPD
19 16 #define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */
20 17 #define SPD_EEPROM_ADDRESS1 0x51
include/configs/ls2080a_simu.h
Diff comments   View file @ ebca902
... ... @@ -12,9 +12,6 @@
12 12 #define CONFIG_SYS_CLK_FREQ 100000000
13 13 #define CONFIG_DDR_CLK_FREQ 133333333
14 14  
15   -#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
16   -#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
17   -
18 15 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
19 16 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
20 17 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
include/configs/mx31ads.h
View file @ ebca902
1   -/*
2   - * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
3   - *
4   - * Configuration settings for the MX31ADS Freescale board.
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#ifndef __CONFIG_H
10   -#define __CONFIG_H
11   -
12   -#include <asm/arch/imx-regs.h>
13   -
14   - /* High Level Configuration Options */
15   -#define CONFIG_MX31 1 /* This is a mx31 */
16   -
17   -#define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS
18   -
19   -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
20   -#define CONFIG_SETUP_MEMORY_TAGS 1
21   -#define CONFIG_INITRD_TAG 1
22   -
23   -/*
24   - * Size of malloc() pool
25   - */
26   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
27   -
28   -/*
29   - * Hardware drivers
30   - */
31   -
32   -#define CONFIG_MXC_UART
33   -#define CONFIG_MXC_UART_BASE UART1_BASE
34   -
35   -#define CONFIG_HARD_SPI 1
36   -#define CONFIG_DEFAULT_SPI_BUS 1
37   -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
38   -
39   -/* PMIC Controller */
40   -#define CONFIG_POWER
41   -#define CONFIG_POWER_SPI
42   -#define CONFIG_POWER_FSL
43   -#define CONFIG_FSL_PMIC_BUS 1
44   -#define CONFIG_FSL_PMIC_CS 0
45   -#define CONFIG_FSL_PMIC_CLK 1000000
46   -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
47   -#define CONFIG_FSL_PMIC_BITLEN 32
48   -#define CONFIG_RTC_MC13XXX
49   -
50   -/* allow to overwrite serial and ethaddr */
51   -#define CONFIG_ENV_OVERWRITE
52   -
53   -#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
54   -
55   -#define CONFIG_EXTRA_ENV_SETTINGS \
56   - "netdev=eth0\0" \
57   - "uboot_addr=0xa0000000\0" \
58   - "uboot=mx31ads/u-boot.bin\0" \
59   - "kernel=mx31ads/uImage\0" \
60   - "nfsroot=/opt/eldk/arm\0" \
61   - "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
62   - "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
63   - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
64   - "bootcmd=run bootcmd_net\0" \
65   - "bootcmd_net=run bootargs_base bootargs_nfs; " \
66   - "tftpboot ${loadaddr} ${kernel}; bootm\0" \
67   - "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
68   - "protect off ${uboot_addr} 0xa003ffff; " \
69   - "erase ${uboot_addr} 0xa003ffff; " \
70   - "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
71   - "setenv filesize; saveenv\0"
72   -
73   -#define CONFIG_CS8900
74   -#define CONFIG_CS8900_BASE 0xb4020300
75   -#define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */
76   -
77   -/*
78   - * The MX31ADS board seems to have a hardware "peculiarity" confirmed under
79   - * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
80   - * controller inverted. The controller is capable of detecting and correcting
81   - * this, but it needs 4 network packets for that. Which means, at startup, you
82   - * will not receive answers to the first 4 packest, unless there have been some
83   - * broadcasts on the network, or your board is on a hub. Reducing the ARP
84   - * timeout from default 5 seconds to 200ms we speed up the initial TFTP
85   - * transfer, should the user wish one, significantly.
86   - */
87   -#define CONFIG_ARP_TIMEOUT 200UL
88   -
89   -/*
90   - * Miscellaneous configurable options
91   - */
92   -
93   -#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
94   -#define CONFIG_SYS_MEMTEST_END 0x10000
95   -
96   -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
97   -
98   -/*-----------------------------------------------------------------------
99   - * Physical Memory Map
100   - */
101   -#define CONFIG_NR_DRAM_BANKS 1
102   -#define PHYS_SDRAM_1 CSD0_BASE
103   -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
104   -
105   -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
106   -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
107   -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
108   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
109   - GENERATED_GBL_DATA_SIZE)
110   -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
111   - CONFIG_SYS_GBL_DATA_OFFSET)
112   -
113   -/*-----------------------------------------------------------------------
114   - * FLASH and environment organization
115   - */
116   -#define CONFIG_SYS_FLASH_BASE CS0_BASE
117   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
118   -#define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */
119   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
120   -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */
121   -
122   -#define CONFIG_ENV_SECT_SIZE (128 * 1024)
123   -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
124   -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
125   -
126   -/* Address and size of Redundant Environment Sector */
127   -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
128   -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
129   -
130   -/*-----------------------------------------------------------------------
131   - * CFI FLASH driver setup
132   - */
133   -#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
134   -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
135   -#define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */
136   -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
137   -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
138   -
139   -/*
140   - * JFFS2 partitions
141   - */
142   -#define CONFIG_JFFS2_DEV "nor0"
143   -
144   -#endif /* __CONFIG_H */
include/configs/mx53ppd.h
Diff comments   View file @ ebca902
... ... @@ -197,8 +197,8 @@
197 197 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
198 198  
199 199 /* FLASH and environment organization */
200   -#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
201   -#define CONFIG_ENV_SIZE (8 * 1024)
  200 +#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
  201 +#define CONFIG_ENV_SIZE (10 * 1024)
202 202 #define CONFIG_ENV_IS_IN_MMC
203 203 #define CONFIG_SYS_MMC_ENV_DEV 0
204 204  
include/configs/mx7_common.h
Diff comments   View file @ ebca902
... ... @@ -57,6 +57,9 @@
57 57 /* Secure boot (HAB) support */
58 58 #ifdef CONFIG_SECURE_BOOT
59 59 #define CONFIG_CSF_SIZE 0x2000
  60 +#ifdef CONFIG_SPL_BUILD
  61 +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  62 +#endif
60 63 #endif
61 64  
62 65 #endif
include/configs/pico-imx7d.h
Diff comments   View file @ ebca902
... ... @@ -50,8 +50,8 @@
50 50 "finduuid=part uuid mmc 0:2 uuid\0" \
51 51 "mmcargs=setenv bootargs console=${console},${baudrate} " \
52 52 "root=PARTUUID=${uuid} rootwait rw\0" \
53   - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
54   - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  53 + "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  54 + "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
55 55 "mmcboot=echo Booting from mmc ...; " \
56 56 "run finduuid; " \
57 57 "run mmcargs; " \
include/configs/warp7.h
Diff comments   View file @ ebca902
... ... @@ -24,6 +24,9 @@
24 24 #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
25 25 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
26 26  
  27 +/* Switch on SERIAL_TAG */
  28 +#define CONFIG_SERIAL_TAG
  29 +
27 30 #define CONFIG_DFU_ENV_SETTINGS \
28 31 "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
29 32  
... ... @@ -56,6 +56,7 @@
56 56 #define DCD_CHECK_BITS_SET_PARAM 0x14
57 57 #define DCD_CHECK_BITS_CLR_PARAM 0x04
58 58  
  59 +#ifndef __ASSEMBLY__
59 60 enum imximage_cmd {
60 61 CMD_INVALID,
61 62 CMD_IMAGE_VERSION,
... ... @@ -197,5 +198,6 @@
197 198 typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
198 199 uint32_t entry_point, uint32_t flash_offset);
199 200  
  201 +#endif /* __ASSEMBLY__ */
200 202 #endif /* _IMXIMAGE_H_ */
include/s6e63d6.h
View file @ ebca902
1   -/*
2   - * Copyright (C) 2009
3   - * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -#ifndef _S6E63D6_H_
8   -#define _S6E63D6_H_
9   -
10   -struct s6e63d6 {
11   - unsigned int bus;
12   - unsigned int cs;
13   - unsigned int id;
14   - struct spi_slave *slave;
15   -};
16   -
17   -extern int s6e63d6_init(struct s6e63d6 *data);
18   -extern int s6e63d6_index(struct s6e63d6 *data, u8 idx);
19   -extern int s6e63d6_param(struct s6e63d6 *data, u16 param);
20   -
21   -#endif
scripts/Makefile.lib
Diff comments   View file @ ebca902
... ... @@ -521,7 +521,7 @@
521 521 MKIMAGEOUTPUT ?= /dev/null
522 522 quiet_cmd_mkimage = MKIMAGE $@
523 523 cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
524   - $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT))
  524 + >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
525 525  
526 526 # fdtgrep
527 527 # ---------------------------------------------------------------------------
scripts/Makefile.spl
Diff comments   View file @ ebca902
... ... @@ -144,7 +144,7 @@
144 144  
145 145 quiet_cmd_mkimage = MKIMAGE $@
146 146 cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
147   - $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT))
  147 + >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
148 148  
149 149 MKIMAGEFLAGS_MLO = -T omapimage -a $(CONFIG_SPL_TEXT_BASE)
150 150  
... ... @@ -516,7 +516,7 @@
516 516 offs = (char *)&hdr_v2->data.dcd_table
517 517 - (char *)hdr_v2;
518 518  
519   - printf("HAB Blocks: %08x %08x %08x\n",
  519 + printf("HAB Blocks: 0x%08x 0x%08x 0x%08x\n",
520 520 (uint32_t)fhdr_v2->self, 0,
521 521 hdr_v2->boot_data.size - imximage_ivt_offset -
522 522 imximage_csf_size);