mips: Add MIPSfpga platform support

MIPSfpga is an FPGA based dev platform. In a nutshell, its a microAptiv cpu core with lots of Xilinx IP blocks The FPGA dev board used is the Nexys4DDR board by Digilent. For more information, check the Readme file in board/imgtec/xilfpga Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

mips: Add MIPSfpga platform support
MIPSfpga is an FPGA based dev platform. In a nutshell, its a microAptiv cpu core with lots of Xilinx IP blocks The FPGA dev board used is the Nexys4DDR board by Digilent. For more information, check the Readme file in board/imgtec/xilfpga Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Zubair Lutfullah Kakakhel · Daniel Schwierzeck
1 parent d4e85377e7
Showing 8 changed files with 211 additions and 0 deletions Side-by-side Diff
arch/mips/Kconfig
board/imgtec/xilfpga/Kconfig
board/imgtec/xilfpga/MAINTAINERS
board/imgtec/xilfpga/Makefile
board/imgtec/xilfpga/README
board/imgtec/xilfpga/xilfpga.c
configs/imgtec_xilfpga_defconfig
include/configs/imgtec_xilfpga.h
@@ -73,10 +73,25 @@
 	select OF_CONTROL
 	select DM
  
+config TARGET_XILFPGA
+	bool "Support Imagination Xilfpga"
+	select OF_CONTROL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+	select DM_ETH
+	select SUPPORTS_LITTLE_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select SUPPORTS_CPU_MIPS32_R2
+	select MIPS_L1_CACHE_SHIFT_4
+	help
+	  This supports IMGTEC MIPSfpga platform
+
 endchoice
  
 source "board/dbau1x00/Kconfig"
 source "board/imgtec/malta/Kconfig"
+source "board/imgtec/xilfpga/Kconfig"
 source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
+if TARGET_XILFPGA
+
+config SYS_BOARD
+	default "xilfpga"
+
+config SYS_VENDOR
+	default "imgtec"
+
+config SYS_CONFIG_NAME
+	default "imgtec_xilfpga"
+
+config SYS_TEXT_BASE
+	default 0x80C00000
+
+endif
+XILFPGA BOARD
+M:	Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
+S:	Maintained
+F:	board/imgtec/xilfpga
+F:	include/configs/xilfpga.h
+F:	configs/imgtec_xilfpga_defconfig
+#
+# Copyright (C) 2016, Imagination Technologies Ltd.
+# Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+obj-y := xilfpga.o
+/*
+ * Copyright (C) 2016, Imagination Technologies Ltd.
+ *
+ * Zubair Lutfullah Kakakhel, Zubair.Kakakhel@imgtec.com
+ */
+
+MIPSfpga
+=======================================
+
+MIPSfpga is an FPGA based development platform by Imagination Technologies
+As we are dealing with a MIPS core instantiated on an FPGA, specifications
+are fluid and can be varied in RTL.
+
+The example project provided by IMGTEC runs on the Nexys4DDR board by
+Digilent powered by the ARTIX-7 FPGA by Xilinx. Relevant details about
+the example project and the Nexys4DDR board:
+
+- microAptiv UP core m14Kc
+- 50MHz clock speed
+- 128Mbyte DDR RAM	at 0x0000_0000
+- 8Kbyte RAM		at 0x1000_0000
+- axi_intc		at 0x1020_0000
+- axi_uart16550		at 0x1040_0000
+- axi_gpio		at 0x1060_0000
+- axi_i2c		at 0x10A0_0000
+- custom_gpio		at 0x10C0_0000
+- axi_ethernetlite	at 0x10E0_0000
+- 8Kbyte BootRAM	at 0x1FC0_0000
+- 16Mbyte QPI		at 0x1D00_0000
+
+Boot protocol:
+--------------
+
+The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000.
+This is for easy reprogrammibility via JTAG.
+
+DDR initialization is already handled by a HW IP block.
+
+When the example project bitstream is loaded, the cpu_reset button
+needs to be pressed.
+
+The bootram initializes the cache and axi_uart
+Then checks if there is anything non 0xffff_ffff at location 0x1D40_0000
+
+If there is, then that is considered as u-boot. u-boot is copied from
+0x1D40_0000 to memory and the bootram jumps into u-boot code.
+
+At this point, the board is ready to load the Linux kernel + buildroot initramfs
+
+This can be done in multiple ways:
+
+1- JTAG load the binary and jump into it.
+2- Load kernel stored in the QSPI flash at 0x1D80_0000
+3- Load uImage via tftp. Ethernet works in u-boot.
+   e.g. env set server ip 192.168.154.45; dhcp uImage; bootm
+/*
+ * Imagination Technologies MIPSfpga platform code
+ *
+ * Copyright (C) 2016, Imagination Technologies Ltd.
+ *
+ * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#include <common.h>
+
+/* initialize the DDR Controller and PHY */
+phys_size_t initdram(int board_type)
+{
+	/* MIG IP block is smart and doesn't need SW
+	 * to do any init */
+	return CONFIG_SYS_SDRAM_SIZE;	/* in bytes */
+}
+CONFIG_MIPS=y
+CONFIG_SYS_MALLOC_F_LEN=0x600
+CONFIG_TARGET_XILFPGA=y
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="nexys4ddr"
+CONFIG_BOOTDELAY=5
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="MIPSfpga # "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SAVEENV is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_CLK=y
+CONFIG_XILINX_EMACLITE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CMD_DHRYSTONE=y
+/*
+ * Copyright (C) 2016, Imagination Technologies Ltd.
+ *
+ * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Imagination Technologies Ltd. MIPSfpga
+ */
+
+#ifndef __XILFPGA_CONFIG_H
+#define __XILFPGA_CONFIG_H
+
+/* BootROM + MIG is pretty smart. DDR and Cache initialized */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*--------------------------------------------
+ * CPU configuration
+ */
+/* CPU Timer rate */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	50000000
+
+/* Cache Configuration */
+#define CONFIG_SYS_MIPS_CACHE_MODE	CONF_CM_CACHABLE_NONCOHERENT
+
+/*----------------------------------------------------------------------
+ * Memory Layout
+ */
+
+/* SDRAM Configuration (for final code, data, stack, heap) */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000	/* 128 Mbytes */
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000)
+
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_LOAD_ADDR		0x80500000 /* default load address */
+
+/*----------------------------------------------------------------------
+ * Commands
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+/*-------------------------------------------------
+ * FLASH configuration
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*------------------------------------------------------------
+ * Console Configuration
+ */
+#define CONFIG_SYS_CBSIZE		1024 /* Console I/O Buffer Size   */
+#define CONFIG_SYS_MAXARGS		16   /* max number of command args*/
+#define CONFIG_BAUDRATE			115200
+
+/* -------------------------------------------------
+ * Environment
+ */
+#define CONFIG_ENV_IS_NOWHERE	1
+#define CONFIG_ENV_SIZE		0x4000
+
+/* ---------------------------------------------------------------------
+ * Board boot configuration
+ */
+#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
+
+#endif	/* __XILFPGA_CONFIG_H */
...	...	@@ -73,10 +73,25 @@
73	73	select OF_CONTROL
74	74	select DM
75	75
	76	+config TARGET_XILFPGA
	77	+ bool "Support Imagination Xilfpga"
	78	+ select OF_CONTROL
	79	+ select DM
	80	+ select DM_SERIAL
	81	+ select DM_GPIO
	82	+ select DM_ETH
	83	+ select SUPPORTS_LITTLE_ENDIAN
	84	+ select SUPPORTS_CPU_MIPS32_R1
	85	+ select SUPPORTS_CPU_MIPS32_R2
	86	+ select MIPS_L1_CACHE_SHIFT_4
	87	+ help
	88	+ This supports IMGTEC MIPSfpga platform
	89	+
76	90	endchoice
77	91
78	92	source "board/dbau1x00/Kconfig"
79	93	source "board/imgtec/malta/Kconfig"
	94	+source "board/imgtec/xilfpga/Kconfig"
80	95	source "board/micronas/vct/Kconfig"
81	96	source "board/pb1x00/Kconfig"
82	97	source "board/qemu-mips/Kconfig"
	1	+if TARGET_XILFPGA
	2	+
	3	+config SYS_BOARD
	4	+ default "xilfpga"
	5	+
	6	+config SYS_VENDOR
	7	+ default "imgtec"
	8	+
	9	+config SYS_CONFIG_NAME
	10	+ default "imgtec_xilfpga"
	11	+
	12	+config SYS_TEXT_BASE
	13	+ default 0x80C00000
	14	+
	15	+endif
	1	+XILFPGA BOARD
	2	+M: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
	3	+S: Maintained
	4	+F: board/imgtec/xilfpga
	5	+F: include/configs/xilfpga.h
	6	+F: configs/imgtec_xilfpga_defconfig
	1	+#
	2	+# Copyright (C) 2016, Imagination Technologies Ltd.
	3	+# Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
	4	+#
	5	+# SPDX-License-Identifier: GPL-2.0+
	6	+#
	7	+obj-y := xilfpga.o
	1	+/*
	2	+ * Copyright (C) 2016, Imagination Technologies Ltd.
	3	+ *
	4	+ * Zubair Lutfullah Kakakhel, Zubair.Kakakhel@imgtec.com
	5	+ */
	6	+
	7	+MIPSfpga
	8	+=======================================
	9	+
	10	+MIPSfpga is an FPGA based development platform by Imagination Technologies
	11	+As we are dealing with a MIPS core instantiated on an FPGA, specifications
	12	+are fluid and can be varied in RTL.
	13	+
	14	+The example project provided by IMGTEC runs on the Nexys4DDR board by
	15	+Digilent powered by the ARTIX-7 FPGA by Xilinx. Relevant details about
	16	+the example project and the Nexys4DDR board:
	17	+
	18	+- microAptiv UP core m14Kc
	19	+- 50MHz clock speed
	20	+- 128Mbyte DDR RAM at 0x0000_0000
	21	+- 8Kbyte RAM at 0x1000_0000
	22	+- axi_intc at 0x1020_0000
	23	+- axi_uart16550 at 0x1040_0000
	24	+- axi_gpio at 0x1060_0000
	25	+- axi_i2c at 0x10A0_0000
	26	+- custom_gpio at 0x10C0_0000
	27	+- axi_ethernetlite at 0x10E0_0000
	28	+- 8Kbyte BootRAM at 0x1FC0_0000
	29	+- 16Mbyte QPI at 0x1D00_0000
	30	+
	31	+Boot protocol:
	32	+--------------
	33	+
	34	+The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000.
	35	+This is for easy reprogrammibility via JTAG.
	36	+
	37	+DDR initialization is already handled by a HW IP block.
	38	+
	39	+When the example project bitstream is loaded, the cpu_reset button
	40	+needs to be pressed.
	41	+
	42	+The bootram initializes the cache and axi_uart
	43	+Then checks if there is anything non 0xffff_ffff at location 0x1D40_0000
	44	+
	45	+If there is, then that is considered as u-boot. u-boot is copied from
	46	+0x1D40_0000 to memory and the bootram jumps into u-boot code.
	47	+
	48	+At this point, the board is ready to load the Linux kernel + buildroot initramfs
	49	+
	50	+This can be done in multiple ways:
	51	+
	52	+1- JTAG load the binary and jump into it.
	53	+2- Load kernel stored in the QSPI flash at 0x1D80_0000
	54	+3- Load uImage via tftp. Ethernet works in u-boot.
	55	+ e.g. env set server ip 192.168.154.45; dhcp uImage; bootm
	1	+/*
	2	+ * Imagination Technologies MIPSfpga platform code
	3	+ *
	4	+ * Copyright (C) 2016, Imagination Technologies Ltd.
	5	+ *
	6	+ * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
	7	+ *
	8	+ * SPDX-License-Identifier: GPL-2.0+
	9	+ *
	10	+ */
	11	+
	12	+#include <common.h>
	13	+
	14	+/* initialize the DDR Controller and PHY */
	15	+phys_size_t initdram(int board_type)
	16	+{
	17	+ /* MIG IP block is smart and doesn't need SW
	18	+ * to do any init */
	19	+ return CONFIG_SYS_SDRAM_SIZE; /* in bytes */
	20	+}
	1	+CONFIG_MIPS=y
	2	+CONFIG_SYS_MALLOC_F_LEN=0x600
	3	+CONFIG_TARGET_XILFPGA=y
	4	+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
	5	+CONFIG_MIPS_BOOT_FDT=y
	6	+CONFIG_DEFAULT_DEVICE_TREE="nexys4ddr"
	7	+CONFIG_BOOTDELAY=5
	8	+CONFIG_HUSH_PARSER=y
	9	+CONFIG_SYS_PROMPT="MIPSfpga # "
	10	+# CONFIG_CMD_IMLS is not set
	11	+# CONFIG_CMD_SAVEENV is not set
	12	+CONFIG_CMD_MEMINFO=y
	13	+# CONFIG_CMD_FLASH is not set
	14	+# CONFIG_CMD_FPGA is not set
	15	+CONFIG_CMD_DHCP=y
	16	+CONFIG_CMD_MII=y
	17	+CONFIG_CMD_PING=y
	18	+CONFIG_CMD_TIME=y
	19	+CONFIG_OF_EMBED=y
	20	+CONFIG_NET_RANDOM_ETHADDR=y
	21	+CONFIG_NETCONSOLE=y
	22	+CONFIG_CLK=y
	23	+CONFIG_XILINX_EMACLITE=y
	24	+CONFIG_SYS_NS16550=y
	25	+CONFIG_CMD_DHRYSTONE=y